[PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/csr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9b5bd5d7b49..bb500afdeb5 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -502,6 +502,7 @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno,
 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
 {
     if ((status & MSTATUS_FS) == MSTATUS_FS ||
+        (status & MSTATUS_VS) == MSTATUS_VS ||
         (status & MSTATUS_XS) == MSTATUS_XS) {
         switch (xl) {
         case MXL_RV32:
-- 
2.25.1

On 10/29/21 1:58 AM, frank.chang@sifive.com wrote:
> From: Frank Chang<frank.chang@sifive.com>
> 
> Signed-off-by: Frank Chang<frank.chang@sifive.com>
> ---
>   target/riscv/csr.c | 1 +
>   1 file changed, 1 insertion(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

• [PATCH v9 01/76] target/riscv: drop vector 0.7.1 and add 1.0 support
• [PATCH v9 02/76] target/riscv: Use FIELD_EX32() to extract wd field
• [PATCH v9 03/76] target/riscv: rvv-1.0: add mstatus VS field
• [PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty
• [PATCH v9 05/76] target/riscv: rvv-1.0: add sstatus VS field
• [PATCH v9 06/76] target/riscv: rvv-1.0: introduce writable misa.v field
• [PATCH v9 07/76] target/riscv: rvv-1.0: add translation-time vector context status
• [PATCH v9 08/76] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
• [PATCH v9 09/76] target/riscv: rvv-1.0: add vcsr register
• [PATCH v9 10/76] target/riscv: rvv-1.0: add vlenb register
• [PATCH v9 11/76] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
• [PATCH v9 12/76] target/riscv: rvv-1.0: remove MLEN calculations
• [PATCH v9 13/76] target/riscv: rvv-1.0: add fractional LMUL
• [PATCH v9 14/76] target/riscv: rvv-1.0: add VMA and VTA
• [PATCH v9 15/76] target/riscv: rvv-1.0: update check functions
• [PATCH v9 16/76] target/riscv: introduce more imm value modes in translator functions
• [PATCH v9 17/76] target/riscv: rvv:1.0: add translation-time nan-box helper function
• [PATCH v9 18/76] target/riscv: rvv-1.0: remove amo operations instructions
• [PATCH v9 19/76] target/riscv: rvv-1.0: configure instructions
• [PATCH v9 20/76] target/riscv: rvv-1.0: stride load and store instructions
• [PATCH v9 21/76] target/riscv: rvv-1.0: index load and store instructions
• [PATCH v9 22/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
• [PATCH v9 23/76] target/riscv: rvv-1.0: fault-only-first unit stride load
• [PATCH v9 24/76] target/riscv: rvv-1.0: load/store whole register instructions
• [PATCH v9 25/76] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
• [PATCH v9 26/76] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
• [PATCH v9 27/76] target/riscv: rvv-1.0: floating-point square-root instruction
• [PATCH v9 28/76] target/riscv: rvv-1.0: floating-point classify instructions
• [PATCH v9 29/76] target/riscv: rvv-1.0: count population in mask instruction
• [PATCH v9 30/76] target/riscv: rvv-1.0: find-first-set mask bit instruction
• [PATCH v9 31/76] target/riscv: rvv-1.0: set-X-first mask bit instructions
• [PATCH v9 32/76] target/riscv: rvv-1.0: iota instruction
• [PATCH v9 33/76] target/riscv: rvv-1.0: element index instruction
• [PATCH v9 34/76] target/riscv: rvv-1.0: allow load element with sign-extended
• [PATCH v9 35/76] target/riscv: rvv-1.0: register gather instructions
• [PATCH v9 36/76] target/riscv: rvv-1.0: integer scalar move instructions
• [PATCH v9 37/76] target/riscv: rvv-1.0: floating-point move instruction
• [PATCH v9 38/76] target/riscv: rvv-1.0: floating-point scalar move instructions
• [PATCH v9 39/76] target/riscv: rvv-1.0: whole register move instructions
• [PATCH v9 40/76] target/riscv: rvv-1.0: integer extension instructions
• [PATCH v9 41/76] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
• [PATCH v9 42/76] target/riscv: rvv-1.0: single-width bit shift instructions
• [PATCH v9 43/76] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
• [PATCH v9 44/76] target/riscv: rvv-1.0: narrowing integer right shift instructions
• [PATCH v9 45/76] target/riscv: rvv-1.0: widening integer multiply-add instructions
• [PATCH v9 46/76] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
• [PATCH v9 47/76] target/riscv: rvv-1.0: integer comparison instructions
• [PATCH v9 48/76] target/riscv: rvv-1.0: floating-point compare instructions
• [PATCH v9 49/76] target/riscv: rvv-1.0: mask-register logical instructions
• [PATCH v9 50/76] target/riscv: rvv-1.0: slide instructions
• [PATCH v9 51/76] target/riscv: rvv-1.0: floating-point slide instructions
• [PATCH v9 52/76] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
• [PATCH v9 53/76] target/riscv: rvv-1.0: single-width floating-point reduction
• [PATCH v9 54/76] target/riscv: rvv-1.0: widening floating-point reduction instructions
• [PATCH v9 55/76] target/riscv: rvv-1.0: single-width scaling shift instructions
• [PATCH v9 56/76] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
• [PATCH v9 57/76] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
• [PATCH v9 58/76] target/riscv: rvv-1.0: remove integer extract instruction
• [PATCH v9 59/76] target/riscv: rvv-1.0: floating-point min/max instructions
• [PATCH v9 60/76] target/riscv: introduce floating-point rounding mode enum
• [PATCH v9 61/76] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
• [PATCH v9 62/76] target/riscv: rvv-1.0: widening floating-point/integer type-convert
• [PATCH v9 63/76] target/riscv: add "set round to odd" rounding mode helper function
• [PATCH v9 64/76] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
• [PATCH v9 65/76] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
• [PATCH v9 66/76] target/riscv: rvv-1.0: implement vstart CSR
• [PATCH v9 67/76] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
• [PATCH v9 68/76] target/riscv: gdb: support vector registers for rv64 & rv32
• [PATCH v9 69/76] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
• [PATCH v9 70/76] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
• [PATCH v9 71/76] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
• [PATCH v9 72/76] target/riscv: rvv-1.0: add vsetivli instruction
• [PATCH v9 73/76] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
• [PATCH v9 74/76] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
• [PATCH v9 75/76] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
• [PATCH v9 76/76] target/riscv: rvv-1.0: update opivv_vadc_check() comment