[v2] riscv-to-apply queue

[PULL v2 00/18] riscv-to-apply queue

Alistair Francis posted 18 patches 4 years, 1 month ago

Diff against v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v3 v3 v3 v3
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Maintainers: Bin Meng <bin.meng@windriver.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Alistair Francis <alistair.francis@wdc.com>, Peter Maydell <peter.maydell@linaro.org>, "Alex Bennée" <alex.bennee@linaro.org>, Aurelien Jarno <aurelien@aurel32.net>

There is a newer version of this series

include/fpu/softfloat.h                 |  10 ++
include/hw/riscv/boot.h                 |   2 +
include/hw/riscv/microchip_pfsoc.h      |   1 -
include/hw/riscv/sifive_u.h             |   1 -
include/hw/riscv/virt.h                 |   1 -
target/riscv/cpu.h                      |  17 +-
target/riscv/cpu_bits.h                 | 102 +++++++++++-
fpu/softfloat.c                         |  19 ++-
hw/riscv/boot.c                         |  25 +++
hw/riscv/microchip_pfsoc.c              |  14 +-
hw/riscv/opentitan.c                    |   4 +-
hw/riscv/sifive_u.c                     |  14 +-
hw/riscv/virt.c                         |  20 +--
target/riscv/cpu.c                      |  13 ++
target/riscv/cpu_helper.c               |  72 +++-----
target/riscv/csr.c                      | 285 ++++++++++++++++++++++++++++++++
target/riscv/fpu_helper.c               |  16 +-
target/riscv/machine.c                  |  27 +++
target/riscv/translate.c                |  43 +++++
fpu/softfloat-parts.c.inc               |  25 ++-
target/riscv/insn_trans/trans_rva.c.inc |   3 +
target/riscv/insn_trans/trans_rvd.c.inc |   2 +
target/riscv/insn_trans/trans_rvf.c.inc |   2 +
target/riscv/insn_trans/trans_rvi.c.inc |   2 +
24 files changed, 605 insertions(+), 115 deletions(-)

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[PULL v2 00/18] riscv-to-apply queue

Posted by Alistair Francis 4 years, 1 month ago

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit c52d69e7dbaaed0ffdef8125e79218672c30161d:

  Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20211027' into staging (2021-10-27 11:45:18 -0700)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211029-1

for you to fetch changes up to 15161e425ee1bb1180f9cec574cda44fb10c0931:

  target/riscv: change the api for RVF/RVD fmin/fmax (2021-10-29 16:56:12 +1000)

----------------------------------------------------------------
Fifth RISC-V PR for QEMU 6.2

 - Use a shared PLIC config helper function
 - Fixup the OpenTitan PLIC configuration
 - Add support for the experimental J extension
 - Update the fmin/fmax handling
 - Fixup VS interrupt forwarding

----------------------------------------------------------------
Alexey Baturo (7):
      target/riscv: Add J-extension into RISC-V
      target/riscv: Add CSR defines for RISC-V PM extension
      target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
      target/riscv: Add J extension state description
      target/riscv: Print new PM CSRs in QEMU logs
      target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions
      target/riscv: Allow experimental J-ext to be turned on

Alistair Francis (6):
      hw/riscv: virt: Don't use a macro for the PLIC configuration
      hw/riscv: boot: Add a PLIC config string function
      hw/riscv: sifive_u: Use the PLIC config helper function
      hw/riscv: microchip_pfsoc: Use the PLIC config helper function
      hw/riscv: virt: Use the PLIC config helper function
      hw/riscv: opentitan: Fixup the PLIC context addresses

Anatoly Parshintsev (1):
      target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension

Chih-Min Chao (2):
      softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
      target/riscv: change the api for RVF/RVD fmin/fmax

Jose Martins (2):
      target/riscv: fix VS interrupts forwarding to HS
      target/riscv: remove force HS exception

 include/fpu/softfloat.h                 |  10 ++
 include/hw/riscv/boot.h                 |   2 +
 include/hw/riscv/microchip_pfsoc.h      |   1 -
 include/hw/riscv/sifive_u.h             |   1 -
 include/hw/riscv/virt.h                 |   1 -
 target/riscv/cpu.h                      |  17 +-
 target/riscv/cpu_bits.h                 | 102 +++++++++++-
 fpu/softfloat.c                         |  19 ++-
 hw/riscv/boot.c                         |  25 +++
 hw/riscv/microchip_pfsoc.c              |  14 +-
 hw/riscv/opentitan.c                    |   4 +-
 hw/riscv/sifive_u.c                     |  14 +-
 hw/riscv/virt.c                         |  20 +--
 target/riscv/cpu.c                      |  13 ++
 target/riscv/cpu_helper.c               |  72 +++-----
 target/riscv/csr.c                      | 285 ++++++++++++++++++++++++++++++++
 target/riscv/fpu_helper.c               |  16 +-
 target/riscv/machine.c                  |  27 +++
 target/riscv/translate.c                |  43 +++++
 fpu/softfloat-parts.c.inc               |  25 ++-
 target/riscv/insn_trans/trans_rva.c.inc |   3 +
 target/riscv/insn_trans/trans_rvd.c.inc |   2 +
 target/riscv/insn_trans/trans_rvf.c.inc |   2 +
 target/riscv/insn_trans/trans_rvi.c.inc |   2 +
 24 files changed, 605 insertions(+), 115 deletions(-)

Re: [PULL v2 00/18] riscv-to-apply queue

Posted by Richard Henderson 4 years, 1 month ago

On 10/29/21 12:07 AM, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
> 
> The following changes since commit c52d69e7dbaaed0ffdef8125e79218672c30161d:
> 
>    Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20211027' into staging (2021-10-27 11:45:18 -0700)
> 
> are available in the Git repository at:
> 
>    git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211029-1
> 
> for you to fetch changes up to 15161e425ee1bb1180f9cec574cda44fb10c0931:
> 
>    target/riscv: change the api for RVF/RVD fmin/fmax (2021-10-29 16:56:12 +1000)
> 
> ----------------------------------------------------------------
> Fifth RISC-V PR for QEMU 6.2
> 
>   - Use a shared PLIC config helper function
>   - Fixup the OpenTitan PLIC configuration
>   - Add support for the experimental J extension
>   - Update the fmin/fmax handling
>   - Fixup VS interrupt forwarding
> 
> ----------------------------------------------------------------
> Alexey Baturo (7):
>        target/riscv: Add J-extension into RISC-V
>        target/riscv: Add CSR defines for RISC-V PM extension
>        target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
>        target/riscv: Add J extension state description
>        target/riscv: Print new PM CSRs in QEMU logs
>        target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions
>        target/riscv: Allow experimental J-ext to be turned on
> 
> Alistair Francis (6):
>        hw/riscv: virt: Don't use a macro for the PLIC configuration
>        hw/riscv: boot: Add a PLIC config string function
>        hw/riscv: sifive_u: Use the PLIC config helper function
>        hw/riscv: microchip_pfsoc: Use the PLIC config helper function
>        hw/riscv: virt: Use the PLIC config helper function
>        hw/riscv: opentitan: Fixup the PLIC context addresses
> 
> Anatoly Parshintsev (1):
>        target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension
> 
> Chih-Min Chao (2):
>        softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
>        target/riscv: change the api for RVF/RVD fmin/fmax
> 
> Jose Martins (2):
>        target/riscv: fix VS interrupts forwarding to HS
>        target/riscv: remove force HS exception
> 
>   include/fpu/softfloat.h                 |  10 ++
>   include/hw/riscv/boot.h                 |   2 +
>   include/hw/riscv/microchip_pfsoc.h      |   1 -
>   include/hw/riscv/sifive_u.h             |   1 -
>   include/hw/riscv/virt.h                 |   1 -
>   target/riscv/cpu.h                      |  17 +-
>   target/riscv/cpu_bits.h                 | 102 +++++++++++-
>   fpu/softfloat.c                         |  19 ++-
>   hw/riscv/boot.c                         |  25 +++
>   hw/riscv/microchip_pfsoc.c              |  14 +-
>   hw/riscv/opentitan.c                    |   4 +-
>   hw/riscv/sifive_u.c                     |  14 +-
>   hw/riscv/virt.c                         |  20 +--
>   target/riscv/cpu.c                      |  13 ++
>   target/riscv/cpu_helper.c               |  72 +++-----
>   target/riscv/csr.c                      | 285 ++++++++++++++++++++++++++++++++
>   target/riscv/fpu_helper.c               |  16 +-
>   target/riscv/machine.c                  |  27 +++
>   target/riscv/translate.c                |  43 +++++
>   fpu/softfloat-parts.c.inc               |  25 ++-
>   target/riscv/insn_trans/trans_rva.c.inc |   3 +
>   target/riscv/insn_trans/trans_rvd.c.inc |   2 +
>   target/riscv/insn_trans/trans_rvf.c.inc |   2 +
>   target/riscv/insn_trans/trans_rvi.c.inc |   2 +
>   24 files changed, 605 insertions(+), 115 deletions(-)

Applied, thanks.

r~