Missing review: 3 & 4 (Not reviewed by Richard: 10, 18, 21, 25)
Since v2/v1:
- Addressed Richard comments (thanks, I learned a lot doing so!
Although I consider this series 'boring' I enjoyed working on
your review comments).
Since v1:
- Included Jiaxun R-b tags, but they are conditional on Richard
ones.
v1 unchanged cover:
Hi,
This series converts 2000+ lines of switch() code to decodetree
description, so this hard-to-review/modify switch is auto generated
by the decodetree script. This is a big win for maintenance (and
indeed the convertion revealed 2 bugs).
Massive convertions are - beside being often boring - bug-prone.
In this series we re-start running the MSA tests (the tests are
run automagically in the 'build-user-static' job on gitlab CI).
Although boring, the conversion is very clean, so I hope it will
be easy enough to review. The TRANS*() macros are heavily used.
When possible, constant fields are hold with tcg_constant().
Note, various opcodes can be optimized using TCG host vectors.
We won't address that in this series, as it makes the resulting
review harder. We will post that in a following series. Here we
simply dummy-convert.
The resulting msa.decode file is quite pleasant to look at, and
the diff-stat is encouraging: number of LoC halved.
Regards,
Phil.
git: https://gitlab.com/philmd/qemu.git tree/mips-msa-decodetree
Based-on: <20211023164329.328137-1-f4bug@amsat.org>
Philippe Mathieu-Daudé (32):
target/mips: Fix MSA MADDV.B opcode
target/mips: Fix MSA MSUBV.B opcode
tests/tcg/mips: Run MSA opcodes tests on user-mode emulation
target/mips: Use dup_const() to simplify
target/mips: Have check_msa_access() return a boolean
target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
target/mips: Convert MSA LDI opcode to decodetree
target/mips: Convert MSA I5 instruction format to decodetree
target/mips: Convert MSA BIT instruction format to decodetree
target/mips: Convert MSA SHF opcode to decodetree
target/mips: Convert MSA I8 instruction format to decodetree
target/mips: Convert MSA load/store instruction format to decodetree
target/mips: Convert MSA 2RF instruction format to decodetree
target/mips: Convert MSA FILL opcode to decodetree
target/mips: Convert MSA 2R instruction format to decodetree
target/mips: Convert MSA VEC instruction format to decodetree
target/mips: Convert MSA 3RF instruction format to decodetree
(DF_HALF)
target/mips: Convert MSA 3RF instruction format to decodetree
(DF_WORD)
target/mips: Convert MSA 3R instruction format to decodetree (part
1/4)
target/mips: Convert MSA 3R instruction format to decodetree (part
2/4)
target/mips: Convert MSA 3R instruction format to decodetree (part
3/4)
target/mips: Convert MSA 3R instruction format to decodetree (part
4/4)
target/mips: Convert MSA ELM instruction format to decodetree
target/mips: Convert MSA COPY_U opcode to decodetree
target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
target/mips: Convert MSA MOVE.V opcode to decodetree
target/mips: Convert CFCMSA opcode to decodetree
target/mips: Convert CTCMSA opcode to decodetree
target/mips: Remove generic MSA opcode
target/mips: Remove one MSA unnecessary decodetree overlap group
target/mips: Adjust style in msa_translate_init()
tests/tcg/mips/ase-msa.mak | 30 +
target/mips/tcg/msa.decode | 243 ++-
target/mips/tcg/msa_helper.c | 64 +-
target/mips/tcg/msa_translate.c | 2743 +++++++---------------------
MAINTAINERS | 1 +
tests/tcg/mips/Makefile.target | 5 +
tests/tcg/mips64/Makefile.target | 9 +
tests/tcg/mips64el/Makefile.target | 12 +
tests/tcg/mipsel/Makefile.target | 9 +
9 files changed, 970 insertions(+), 2146 deletions(-)
create mode 100644 tests/tcg/mips/ase-msa.mak
create mode 100644 tests/tcg/mips64/Makefile.target
create mode 100644 tests/tcg/mips64el/Makefile.target
create mode 100644 tests/tcg/mipsel/Makefile.target
--
2.31.1