[PULL 00/18] riscv-to-apply queue
[PULL 0/2] riscv-to-apply queue
1
From: Alistair Francis <alistair.francis@wdc.com>
1
From: Alistair Francis <alistair.francis@wdc.com>
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2
3
The following changes since commit c52d69e7dbaaed0ffdef8125e79218672c30161d:
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The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:
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Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20211027' into staging (2021-10-27 11:45:18 -0700)
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Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211028
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git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122
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10
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for you to fetch changes up to 344b61e1478c8eb37e81b96f63d8f5071f5a38e1:
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for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:
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12
13
target/riscv: remove force HS exception (2021-10-28 14:39:23 +1000)
13
hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)
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14
15
----------------------------------------------------------------
15
----------------------------------------------------------------
16
Fifth RISC-V PR for QEMU 6.2
16
Seventh RISC-V PR for QEMU 6.2
17
17
18
- Use a shared PLIC config helper function
18
- Deprecate IF_NONE for SiFive OTP
19
- Fixup the OpenTitan PLIC configuration
19
- Don't reset SiFive OTP content
20
- Add support for the experimental J extension
21
- Update the fmin/fmax handling
22
- Fixup VS interrupt forwarding
23
20
24
----------------------------------------------------------------
21
----------------------------------------------------------------
25
Alexey Baturo (7):
22
Philippe Mathieu-Daudé (1):
26
target/riscv: Add J-extension into RISC-V
23
hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
27
target/riscv: Add CSR defines for RISC-V PM extension
28
target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
29
target/riscv: Add J extension state description
30
target/riscv: Print new PM CSRs in QEMU logs
31
target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions
32
target/riscv: Allow experimental J-ext to be turned on
33
24
34
Alistair Francis (6):
25
Thomas Huth (1):
35
hw/riscv: virt: Don't use a macro for the PLIC configuration
26
hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
36
hw/riscv: boot: Add a PLIC config string function
37
hw/riscv: sifive_u: Use the PLIC config helper function
38
hw/riscv: microchip_pfsoc: Use the PLIC config helper function
39
hw/riscv: virt: Use the PLIC config helper function
40
hw/riscv: opentitan: Fixup the PLIC context addresses
41
27
42
Anatoly Parshintsev (1):
28
docs/about/deprecated.rst | 6 ++++++
43
target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension
29
hw/misc/sifive_u_otp.c | 22 +++++++++++++---------
30
2 files changed, 19 insertions(+), 9 deletions(-)
44
31
45
Chih-Min Chao (2):
46
softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
47
target/riscv: change the api for RVF/RVD fmin/fmax
48
49
Jose Martins (2):
50
target/riscv: fix VS interrupts forwarding to HS
51
target/riscv: remove force HS exception
52
53
include/fpu/softfloat.h | 10 ++
54
include/hw/riscv/boot.h | 2 +
55
include/hw/riscv/microchip_pfsoc.h | 1 -
56
include/hw/riscv/sifive_u.h | 1 -
57
include/hw/riscv/virt.h | 1 -
58
target/riscv/cpu.h | 17 +-
59
target/riscv/cpu_bits.h | 102 +++++++++++-
60
fpu/softfloat.c | 19 ++-
61
hw/riscv/boot.c | 25 +++
62
hw/riscv/microchip_pfsoc.c | 14 +-
63
hw/riscv/opentitan.c | 4 +-
64
hw/riscv/sifive_u.c | 14 +-
65
hw/riscv/virt.c | 20 +--
66
target/riscv/cpu.c | 13 ++
67
target/riscv/cpu_helper.c | 72 +++-----
68
target/riscv/csr.c | 285 ++++++++++++++++++++++++++++++++
69
target/riscv/fpu_helper.c | 16 +-
70
target/riscv/machine.c | 27 +++
71
target/riscv/translate.c | 43 +++++
72
fpu/softfloat-parts.c.inc | 25 ++-
73
target/riscv/insn_trans/trans_rva.c.inc | 3 +
74
target/riscv/insn_trans/trans_rvd.c.inc | 2 +
75
target/riscv/insn_trans/trans_rvf.c.inc | 2 +
76
target/riscv/insn_trans/trans_rvi.c.inc | 2 +
77
24 files changed, 605 insertions(+), 115 deletions(-)
78
diff view generated by jsdifflib
[PULL 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration
Deleted patch
1
From: Alistair Francis <alistair.francis@wdc.com>
2
1
3
Using a macro for the PLIC configuration doesn't make the code any
4
easier to read. Instead it makes it harder to figure out what is going
5
on, so let's remove it.
6
7
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20211022060133.3045020-1-alistair.francis@opensource.wdc.com
11
---
12
include/hw/riscv/virt.h | 1 -
13
hw/riscv/virt.c | 2 +-
14
2 files changed, 1 insertion(+), 2 deletions(-)
15
16
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/riscv/virt.h
19
+++ b/include/hw/riscv/virt.h
20
@@ -XXX,XX +XXX,XX @@ enum {
21
VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
22
};
23
24
-#define VIRT_PLIC_HART_CONFIG "MS"
25
#define VIRT_PLIC_NUM_SOURCES 127
26
#define VIRT_PLIC_NUM_PRIORITIES 7
27
#define VIRT_PLIC_PRIORITY_BASE 0x04
28
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/riscv/virt.c
31
+++ b/hw/riscv/virt.c
32
@@ -XXX,XX +XXX,XX @@ static char *plic_hart_config_string(int hart_count)
33
int i;
34
35
for (i = 0; i < hart_count; i++) {
36
- vals[i] = VIRT_PLIC_HART_CONFIG;
37
+ vals[i] = "MS";
38
}
39
vals[i] = NULL;
40
41
--
42
2.31.1
43
44
diff view generated by jsdifflib
[PULL 02/18] hw/riscv: boot: Add a PLIC config string function
Deleted patch
1
From: Alistair Francis <alistair.francis@wdc.com>
2
1
3
Add a generic function that can create the PLIC strings.
4
5
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8
Message-id: 20211022060133.3045020-2-alistair.francis@opensource.wdc.com
9
---
10
include/hw/riscv/boot.h | 2 ++
11
hw/riscv/boot.c | 25 +++++++++++++++++++++++++
12
2 files changed, 27 insertions(+)
13
14
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/riscv/boot.h
17
+++ b/include/hw/riscv/boot.h
18
@@ -XXX,XX +XXX,XX @@
19
20
bool riscv_is_32bit(RISCVHartArrayState *harts);
21
22
+char *riscv_plic_hart_config_string(int hart_count);
23
+
24
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
25
target_ulong firmware_end_addr);
26
target_ulong riscv_find_and_load_firmware(MachineState *machine,
27
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/riscv/boot.c
30
+++ b/hw/riscv/boot.c
31
@@ -XXX,XX +XXX,XX @@ bool riscv_is_32bit(RISCVHartArrayState *harts)
32
return harts->harts[0].env.misa_mxl_max == MXL_RV32;
33
}
34
35
+/*
36
+ * Return the per-socket PLIC hart topology configuration string
37
+ * (caller must free with g_free())
38
+ */
39
+char *riscv_plic_hart_config_string(int hart_count)
40
+{
41
+ g_autofree const char **vals = g_new(const char *, hart_count + 1);
42
+ int i;
43
+
44
+ for (i = 0; i < hart_count; i++) {
45
+ CPUState *cs = qemu_get_cpu(i);
46
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
47
+
48
+ if (riscv_has_ext(env, RVS)) {
49
+ vals[i] = "MS";
50
+ } else {
51
+ vals[i] = "M";
52
+ }
53
+ }
54
+ vals[i] = NULL;
55
+
56
+ /* g_strjoinv() obliges us to cast away const here */
57
+ return g_strjoinv(",", (char **)vals);
58
+}
59
+
60
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
61
target_ulong firmware_end_addr) {
62
if (riscv_is_32bit(harts)) {
63
--
64
2.31.1
65
66
diff view generated by jsdifflib
[PULL 03/18] hw/riscv: sifive_u: Use the PLIC config helper function
Deleted patch
1
From: Alistair Francis <alistair.francis@wdc.com>
2
1
3
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6
Tested-by: Bin Meng <bmeng.cn@gmail.com>
7
Message-id: 20211022060133.3045020-3-alistair.francis@opensource.wdc.com
8
---
9
include/hw/riscv/sifive_u.h | 1 -
10
hw/riscv/sifive_u.c | 14 +-------------
11
2 files changed, 1 insertion(+), 14 deletions(-)
12
13
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/riscv/sifive_u.h
16
+++ b/include/hw/riscv/sifive_u.h
17
@@ -XXX,XX +XXX,XX @@ enum {
18
#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
19
#define SIFIVE_U_COMPUTE_CPU_COUNT 4
20
21
-#define SIFIVE_U_PLIC_HART_CONFIG "MS"
22
#define SIFIVE_U_PLIC_NUM_SOURCES 54
23
#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
24
#define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
25
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/riscv/sifive_u.c
28
+++ b/hw/riscv/sifive_u.c
29
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
30
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
31
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
32
char *plic_hart_config;
33
- size_t plic_hart_config_len;
34
int i, j;
35
NICInfo *nd = &nd_table[0];
36
37
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
38
l2lim_mem);
39
40
/* create PLIC hart topology configuration string */
41
- plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
42
- ms->smp.cpus;
43
- plic_hart_config = g_malloc0(plic_hart_config_len);
44
- for (i = 0; i < ms->smp.cpus; i++) {
45
- if (i != 0) {
46
- strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
47
- plic_hart_config_len);
48
- } else {
49
- strncat(plic_hart_config, "M", plic_hart_config_len);
50
- }
51
- plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
52
- }
53
+ plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
54
55
/* MMIO */
56
s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
57
--
58
2.31.1
59
60
diff view generated by jsdifflib
[PULL 04/18] hw/riscv: microchip_pfsoc: Use the PLIC config helper function
Deleted patch
1
From: Alistair Francis <alistair.francis@wdc.com>
2
1
3
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6
Tested-by: Bin Meng <bmeng.cn@gmail.com>
7
Message-id: 20211022060133.3045020-4-alistair.francis@opensource.wdc.com
8
---
9
include/hw/riscv/microchip_pfsoc.h | 1 -
10
hw/riscv/microchip_pfsoc.c | 14 +-------------
11
2 files changed, 1 insertion(+), 14 deletions(-)
12
13
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/riscv/microchip_pfsoc.h
16
+++ b/include/hw/riscv/microchip_pfsoc.h
17
@@ -XXX,XX +XXX,XX @@ enum {
18
#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
19
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
20
21
-#define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS"
22
#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
23
#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
24
#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
25
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/riscv/microchip_pfsoc.c
28
+++ b/hw/riscv/microchip_pfsoc.c
29
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
30
MemoryRegion *envm_data = g_new(MemoryRegion, 1);
31
MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1);
32
char *plic_hart_config;
33
- size_t plic_hart_config_len;
34
NICInfo *nd;
35
int i;
36
37
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
38
l2lim_mem);
39
40
/* create PLIC hart topology configuration string */
41
- plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
42
- ms->smp.cpus;
43
- plic_hart_config = g_malloc0(plic_hart_config_len);
44
- for (i = 0; i < ms->smp.cpus; i++) {
45
- if (i != 0) {
46
- strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
47
- plic_hart_config_len);
48
- } else {
49
- strncat(plic_hart_config, "M", plic_hart_config_len);
50
- }
51
- plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
52
- }
53
+ plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
54
55
/* PLIC */
56
s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
57
--
58
2.31.1
59
60
diff view generated by jsdifflib
[PULL 05/18] hw/riscv: virt: Use the PLIC config helper function
Deleted patch
1
From: Alistair Francis <alistair.francis@wdc.com>
2
1
3
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6
Tested-by: Bin Meng <bmeng.cn@gmail.com>
7
Message-id: 20211022060133.3045020-5-alistair.francis@opensource.wdc.com
8
---
9
hw/riscv/virt.c | 20 +-------------------
10
1 file changed, 1 insertion(+), 19 deletions(-)
11
12
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/riscv/virt.c
15
+++ b/hw/riscv/virt.c
16
@@ -XXX,XX +XXX,XX @@ static FWCfgState *create_fw_cfg(const MachineState *mc)
17
return fw_cfg;
18
}
19
20
-/*
21
- * Return the per-socket PLIC hart topology configuration string
22
- * (caller must free with g_free())
23
- */
24
-static char *plic_hart_config_string(int hart_count)
25
-{
26
- g_autofree const char **vals = g_new(const char *, hart_count + 1);
27
- int i;
28
-
29
- for (i = 0; i < hart_count; i++) {
30
- vals[i] = "MS";
31
- }
32
- vals[i] = NULL;
33
-
34
- /* g_strjoinv() obliges us to cast away const here */
35
- return g_strjoinv(",", (char **)vals);
36
-}
37
-
38
static void virt_machine_init(MachineState *machine)
39
{
40
const MemMapEntry *memmap = virt_memmap;
41
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
42
}
43
44
/* Per-socket PLIC hart topology configuration string */
45
- plic_hart_config = plic_hart_config_string(hart_count);
46
+ plic_hart_config = riscv_plic_hart_config_string(hart_count);
47
48
/* Per-socket PLIC */
49
s->plic[i] = sifive_plic_create(
50
--
51
2.31.1
52
53
diff view generated by jsdifflib
[PULL 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses
Deleted patch
1
From: Alistair Francis <alistair.francis@wdc.com>
2
1
3
Fixup the PLIC context address to correctly support the threshold and
4
claim register.
5
6
Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build")
7
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9
Message-id: 20211025040657.262696-1-alistair.francis@opensource.wdc.com
10
---
11
hw/riscv/opentitan.c | 4 ++--
12
1 file changed, 2 insertions(+), 2 deletions(-)
13
14
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/riscv/opentitan.c
17
+++ b/hw/riscv/opentitan.c
18
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
19
qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
20
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
21
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
22
- qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200004);
23
- qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 4);
24
+ qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
25
+ qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
26
qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
27
28
if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
29
--
30
2.31.1
31
32
diff view generated by jsdifflib
[PULL 07/18] target/riscv: Add J-extension into RISC-V
Deleted patch
1
From: Alexey Baturo <baturo.alexey@gmail.com>
2
1
3
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
7
Message-id: 20211025173609.2724490-2-space.monkey.delivers@gmail.com
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
10
target/riscv/cpu.h | 2 ++
11
1 file changed, 2 insertions(+)
12
13
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/cpu.h
16
+++ b/target/riscv/cpu.h
17
@@ -XXX,XX +XXX,XX @@
18
#define RVS RV('S')
19
#define RVU RV('U')
20
#define RVH RV('H')
21
+#define RVJ RV('J')
22
23
/* S extension denotes that Supervisor mode exists, however it is possible
24
to have a core that support S mode but does not have an MMU and there
25
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
26
bool ext_s;
27
bool ext_u;
28
bool ext_h;
29
+ bool ext_j;
30
bool ext_v;
31
bool ext_zba;
32
bool ext_zbb;
33
--
34
2.31.1
35
36
diff view generated by jsdifflib
[PULL 08/18] target/riscv: Add CSR defines for RISC-V PM extension
Deleted patch
1
From: Alexey Baturo <baturo.alexey@gmail.com>
2
1
3
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20211025173609.2724490-3-space.monkey.delivers@gmail.com
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
---
8
target/riscv/cpu_bits.h | 96 +++++++++++++++++++++++++++++++++++++++++
9
1 file changed, 96 insertions(+)
10
11
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/cpu_bits.h
14
+++ b/target/riscv/cpu_bits.h
15
@@ -XXX,XX +XXX,XX @@
16
#define CSR_MHPMCOUNTER30H 0xb9e
17
#define CSR_MHPMCOUNTER31H 0xb9f
18
19
+/*
20
+ * User PointerMasking registers
21
+ * NB: actual CSR numbers might be changed in future
22
+ */
23
+#define CSR_UMTE 0x4c0
24
+#define CSR_UPMMASK 0x4c1
25
+#define CSR_UPMBASE 0x4c2
26
+
27
+/*
28
+ * Machine PointerMasking registers
29
+ * NB: actual CSR numbers might be changed in future
30
+ */
31
+#define CSR_MMTE 0x3c0
32
+#define CSR_MPMMASK 0x3c1
33
+#define CSR_MPMBASE 0x3c2
34
+
35
+/*
36
+ * Supervisor PointerMaster registers
37
+ * NB: actual CSR numbers might be changed in future
38
+ */
39
+#define CSR_SMTE 0x1c0
40
+#define CSR_SPMMASK 0x1c1
41
+#define CSR_SPMBASE 0x1c2
42
+
43
+/*
44
+ * Hypervisor PointerMaster registers
45
+ * NB: actual CSR numbers might be changed in future
46
+ */
47
+#define CSR_VSMTE 0x2c0
48
+#define CSR_VSPMMASK 0x2c1
49
+#define CSR_VSPMBASE 0x2c2
50
+
51
/* mstatus CSR bits */
52
#define MSTATUS_UIE 0x00000001
53
#define MSTATUS_SIE 0x00000002
54
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
55
#define MIE_UTIE (1 << IRQ_U_TIMER)
56
#define MIE_SSIE (1 << IRQ_S_SOFT)
57
#define MIE_USIE (1 << IRQ_U_SOFT)
58
+
59
+/* General PointerMasking CSR bits*/
60
+#define PM_ENABLE 0x00000001ULL
61
+#define PM_CURRENT 0x00000002ULL
62
+#define PM_INSN 0x00000004ULL
63
+#define PM_XS_MASK 0x00000003ULL
64
+
65
+/* PointerMasking XS bits values */
66
+#define PM_EXT_DISABLE 0x00000000ULL
67
+#define PM_EXT_INITIAL 0x00000001ULL
68
+#define PM_EXT_CLEAN 0x00000002ULL
69
+#define PM_EXT_DIRTY 0x00000003ULL
70
+
71
+/* Offsets for every pair of control bits per each priv level */
72
+#define XS_OFFSET 0ULL
73
+#define U_OFFSET 2ULL
74
+#define S_OFFSET 5ULL
75
+#define M_OFFSET 8ULL
76
+
77
+#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
78
+#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
79
+#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
80
+#define U_PM_INSN (PM_INSN << U_OFFSET)
81
+#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
82
+#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
83
+#define S_PM_INSN (PM_INSN << S_OFFSET)
84
+#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
85
+#define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
86
+#define M_PM_INSN (PM_INSN << M_OFFSET)
87
+
88
+/* mmte CSR bits */
89
+#define MMTE_PM_XS_BITS PM_XS_BITS
90
+#define MMTE_U_PM_ENABLE U_PM_ENABLE
91
+#define MMTE_U_PM_CURRENT U_PM_CURRENT
92
+#define MMTE_U_PM_INSN U_PM_INSN
93
+#define MMTE_S_PM_ENABLE S_PM_ENABLE
94
+#define MMTE_S_PM_CURRENT S_PM_CURRENT
95
+#define MMTE_S_PM_INSN S_PM_INSN
96
+#define MMTE_M_PM_ENABLE M_PM_ENABLE
97
+#define MMTE_M_PM_CURRENT M_PM_CURRENT
98
+#define MMTE_M_PM_INSN M_PM_INSN
99
+#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \
100
+ MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \
101
+ MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \
102
+ MMTE_PM_XS_BITS)
103
+
104
+/* (v)smte CSR bits */
105
+#define SMTE_PM_XS_BITS PM_XS_BITS
106
+#define SMTE_U_PM_ENABLE U_PM_ENABLE
107
+#define SMTE_U_PM_CURRENT U_PM_CURRENT
108
+#define SMTE_U_PM_INSN U_PM_INSN
109
+#define SMTE_S_PM_ENABLE S_PM_ENABLE
110
+#define SMTE_S_PM_CURRENT S_PM_CURRENT
111
+#define SMTE_S_PM_INSN S_PM_INSN
112
+#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \
113
+ SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \
114
+ SMTE_PM_XS_BITS)
115
+
116
+/* umte CSR bits */
117
+#define UMTE_U_PM_ENABLE U_PM_ENABLE
118
+#define UMTE_U_PM_CURRENT U_PM_CURRENT
119
+#define UMTE_U_PM_INSN U_PM_INSN
120
+#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
121
+
122
#endif
123
--
124
2.31.1
125
126
diff view generated by jsdifflib
[PULL 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
Deleted patch
1
From: Alexey Baturo <baturo.alexey@gmail.com>
2
1
3
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20211025173609.2724490-4-space.monkey.delivers@gmail.com
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
---
8
target/riscv/cpu.h | 11 ++
9
target/riscv/cpu.c | 2 +
10
target/riscv/csr.c | 285 +++++++++++++++++++++++++++++++++++++++++++++
11
3 files changed, 298 insertions(+)
12
13
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/cpu.h
16
+++ b/target/riscv/cpu.h
17
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
18
19
/* True if in debugger mode. */
20
bool debugger;
21
+
22
+ /*
23
+ * CSRs for PointerMasking extension
24
+ */
25
+ target_ulong mmte;
26
+ target_ulong mpmmask;
27
+ target_ulong mpmbase;
28
+ target_ulong spmmask;
29
+ target_ulong spmbase;
30
+ target_ulong upmmask;
31
+ target_ulong upmbase;
32
#endif
33
34
float_status fp_status;
35
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/cpu.c
38
+++ b/target/riscv/cpu.c
39
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
40
env->mcause = 0;
41
env->pc = env->resetvec;
42
env->two_stage_lookup = false;
43
+ /* mmte is supposed to have pm.current hardwired to 1 */
44
+ env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
45
#endif
46
cs->exception_index = RISCV_EXCP_NONE;
47
env->load_res = -1;
48
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/riscv/csr.c
51
+++ b/target/riscv/csr.c
52
@@ -XXX,XX +XXX,XX @@ static RISCVException hmode32(CPURISCVState *env, int csrno)
53
54
}
55
56
+/* Checks if PointerMasking registers could be accessed */
57
+static RISCVException pointer_masking(CPURISCVState *env, int csrno)
58
+{
59
+ /* Check if j-ext is present */
60
+ if (riscv_has_ext(env, RVJ)) {
61
+ return RISCV_EXCP_NONE;
62
+ }
63
+ return RISCV_EXCP_ILLEGAL_INST;
64
+}
65
+
66
static RISCVException pmp(CPURISCVState *env, int csrno)
67
{
68
if (riscv_feature(env, RISCV_FEATURE_PMP)) {
69
@@ -XXX,XX +XXX,XX @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
70
return RISCV_EXCP_NONE;
71
}
72
73
+/*
74
+ * Functions to access Pointer Masking feature registers
75
+ * We have to check if current priv lvl could modify
76
+ * csr in given mode
77
+ */
78
+static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
79
+{
80
+ int csr_priv = get_field(csrno, 0x300);
81
+ int pm_current;
82
+
83
+ /*
84
+ * If priv lvls differ that means we're accessing csr from higher priv lvl,
85
+ * so allow the access
86
+ */
87
+ if (env->priv != csr_priv) {
88
+ return false;
89
+ }
90
+ switch (env->priv) {
91
+ case PRV_M:
92
+ pm_current = get_field(env->mmte, M_PM_CURRENT);
93
+ break;
94
+ case PRV_S:
95
+ pm_current = get_field(env->mmte, S_PM_CURRENT);
96
+ break;
97
+ case PRV_U:
98
+ pm_current = get_field(env->mmte, U_PM_CURRENT);
99
+ break;
100
+ default:
101
+ g_assert_not_reached();
102
+ }
103
+ /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
104
+ return !pm_current;
105
+}
106
+
107
+static RISCVException read_mmte(CPURISCVState *env, int csrno,
108
+ target_ulong *val)
109
+{
110
+ *val = env->mmte & MMTE_MASK;
111
+ return RISCV_EXCP_NONE;
112
+}
113
+
114
+static RISCVException write_mmte(CPURISCVState *env, int csrno,
115
+ target_ulong val)
116
+{
117
+ uint64_t mstatus;
118
+ target_ulong wpri_val = val & MMTE_MASK;
119
+
120
+ if (val != wpri_val) {
121
+ qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
122
+ "MMTE: WPRI violation written 0x", val,
123
+ "vs expected 0x", wpri_val);
124
+ }
125
+ /* for machine mode pm.current is hardwired to 1 */
126
+ wpri_val |= MMTE_M_PM_CURRENT;
127
+
128
+ /* hardwiring pm.instruction bit to 0, since it's not supported yet */
129
+ wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
130
+ env->mmte = wpri_val | PM_EXT_DIRTY;
131
+
132
+ /* Set XS and SD bits, since PM CSRs are dirty */
133
+ mstatus = env->mstatus | MSTATUS_XS;
134
+ write_mstatus(env, csrno, mstatus);
135
+ return RISCV_EXCP_NONE;
136
+}
137
+
138
+static RISCVException read_smte(CPURISCVState *env, int csrno,
139
+ target_ulong *val)
140
+{
141
+ *val = env->mmte & SMTE_MASK;
142
+ return RISCV_EXCP_NONE;
143
+}
144
+
145
+static RISCVException write_smte(CPURISCVState *env, int csrno,
146
+ target_ulong val)
147
+{
148
+ target_ulong wpri_val = val & SMTE_MASK;
149
+
150
+ if (val != wpri_val) {
151
+ qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
152
+ "SMTE: WPRI violation written 0x", val,
153
+ "vs expected 0x", wpri_val);
154
+ }
155
+
156
+ /* if pm.current==0 we can't modify current PM CSRs */
157
+ if (check_pm_current_disabled(env, csrno)) {
158
+ return RISCV_EXCP_NONE;
159
+ }
160
+
161
+ wpri_val |= (env->mmte & ~SMTE_MASK);
162
+ write_mmte(env, csrno, wpri_val);
163
+ return RISCV_EXCP_NONE;
164
+}
165
+
166
+static RISCVException read_umte(CPURISCVState *env, int csrno,
167
+ target_ulong *val)
168
+{
169
+ *val = env->mmte & UMTE_MASK;
170
+ return RISCV_EXCP_NONE;
171
+}
172
+
173
+static RISCVException write_umte(CPURISCVState *env, int csrno,
174
+ target_ulong val)
175
+{
176
+ target_ulong wpri_val = val & UMTE_MASK;
177
+
178
+ if (val != wpri_val) {
179
+ qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
180
+ "UMTE: WPRI violation written 0x", val,
181
+ "vs expected 0x", wpri_val);
182
+ }
183
+
184
+ if (check_pm_current_disabled(env, csrno)) {
185
+ return RISCV_EXCP_NONE;
186
+ }
187
+
188
+ wpri_val |= (env->mmte & ~UMTE_MASK);
189
+ write_mmte(env, csrno, wpri_val);
190
+ return RISCV_EXCP_NONE;
191
+}
192
+
193
+static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
194
+ target_ulong *val)
195
+{
196
+ *val = env->mpmmask;
197
+ return RISCV_EXCP_NONE;
198
+}
199
+
200
+static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
201
+ target_ulong val)
202
+{
203
+ uint64_t mstatus;
204
+
205
+ env->mpmmask = val;
206
+ env->mmte |= PM_EXT_DIRTY;
207
+
208
+ /* Set XS and SD bits, since PM CSRs are dirty */
209
+ mstatus = env->mstatus | MSTATUS_XS;
210
+ write_mstatus(env, csrno, mstatus);
211
+ return RISCV_EXCP_NONE;
212
+}
213
+
214
+static RISCVException read_spmmask(CPURISCVState *env, int csrno,
215
+ target_ulong *val)
216
+{
217
+ *val = env->spmmask;
218
+ return RISCV_EXCP_NONE;
219
+}
220
+
221
+static RISCVException write_spmmask(CPURISCVState *env, int csrno,
222
+ target_ulong val)
223
+{
224
+ uint64_t mstatus;
225
+
226
+ /* if pm.current==0 we can't modify current PM CSRs */
227
+ if (check_pm_current_disabled(env, csrno)) {
228
+ return RISCV_EXCP_NONE;
229
+ }
230
+ env->spmmask = val;
231
+ env->mmte |= PM_EXT_DIRTY;
232
+
233
+ /* Set XS and SD bits, since PM CSRs are dirty */
234
+ mstatus = env->mstatus | MSTATUS_XS;
235
+ write_mstatus(env, csrno, mstatus);
236
+ return RISCV_EXCP_NONE;
237
+}
238
+
239
+static RISCVException read_upmmask(CPURISCVState *env, int csrno,
240
+ target_ulong *val)
241
+{
242
+ *val = env->upmmask;
243
+ return RISCV_EXCP_NONE;
244
+}
245
+
246
+static RISCVException write_upmmask(CPURISCVState *env, int csrno,
247
+ target_ulong val)
248
+{
249
+ uint64_t mstatus;
250
+
251
+ /* if pm.current==0 we can't modify current PM CSRs */
252
+ if (check_pm_current_disabled(env, csrno)) {
253
+ return RISCV_EXCP_NONE;
254
+ }
255
+ env->upmmask = val;
256
+ env->mmte |= PM_EXT_DIRTY;
257
+
258
+ /* Set XS and SD bits, since PM CSRs are dirty */
259
+ mstatus = env->mstatus | MSTATUS_XS;
260
+ write_mstatus(env, csrno, mstatus);
261
+ return RISCV_EXCP_NONE;
262
+}
263
+
264
+static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
265
+ target_ulong *val)
266
+{
267
+ *val = env->mpmbase;
268
+ return RISCV_EXCP_NONE;
269
+}
270
+
271
+static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
272
+ target_ulong val)
273
+{
274
+ uint64_t mstatus;
275
+
276
+ env->mpmbase = val;
277
+ env->mmte |= PM_EXT_DIRTY;
278
+
279
+ /* Set XS and SD bits, since PM CSRs are dirty */
280
+ mstatus = env->mstatus | MSTATUS_XS;
281
+ write_mstatus(env, csrno, mstatus);
282
+ return RISCV_EXCP_NONE;
283
+}
284
+
285
+static RISCVException read_spmbase(CPURISCVState *env, int csrno,
286
+ target_ulong *val)
287
+{
288
+ *val = env->spmbase;
289
+ return RISCV_EXCP_NONE;
290
+}
291
+
292
+static RISCVException write_spmbase(CPURISCVState *env, int csrno,
293
+ target_ulong val)
294
+{
295
+ uint64_t mstatus;
296
+
297
+ /* if pm.current==0 we can't modify current PM CSRs */
298
+ if (check_pm_current_disabled(env, csrno)) {
299
+ return RISCV_EXCP_NONE;
300
+ }
301
+ env->spmbase = val;
302
+ env->mmte |= PM_EXT_DIRTY;
303
+
304
+ /* Set XS and SD bits, since PM CSRs are dirty */
305
+ mstatus = env->mstatus | MSTATUS_XS;
306
+ write_mstatus(env, csrno, mstatus);
307
+ return RISCV_EXCP_NONE;
308
+}
309
+
310
+static RISCVException read_upmbase(CPURISCVState *env, int csrno,
311
+ target_ulong *val)
312
+{
313
+ *val = env->upmbase;
314
+ return RISCV_EXCP_NONE;
315
+}
316
+
317
+static RISCVException write_upmbase(CPURISCVState *env, int csrno,
318
+ target_ulong val)
319
+{
320
+ uint64_t mstatus;
321
+
322
+ /* if pm.current==0 we can't modify current PM CSRs */
323
+ if (check_pm_current_disabled(env, csrno)) {
324
+ return RISCV_EXCP_NONE;
325
+ }
326
+ env->upmbase = val;
327
+ env->mmte |= PM_EXT_DIRTY;
328
+
329
+ /* Set XS and SD bits, since PM CSRs are dirty */
330
+ mstatus = env->mstatus | MSTATUS_XS;
331
+ write_mstatus(env, csrno, mstatus);
332
+ return RISCV_EXCP_NONE;
333
+}
334
+
335
#endif
336
337
/*
338
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
339
[CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
340
[CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
341
342
+ /* User Pointer Masking */
343
+ [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
344
+ [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
345
+ [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase, write_upmbase },
346
+ /* Machine Pointer Masking */
347
+ [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
348
+ [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
349
+ [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
350
+ /* Supervisor Pointer Masking */
351
+ [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
352
+ [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask, write_spmmask },
353
+ [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase },
354
+
355
/* Performance Counters */
356
[CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero },
357
[CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
358
--
359
2.31.1
360
361
diff view generated by jsdifflib
[PULL 10/18] target/riscv: Add J extension state description
Deleted patch
1
From: Alexey Baturo <baturo.alexey@gmail.com>
2
1
3
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20211025173609.2724490-5-space.monkey.delivers@gmail.com
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
---
8
target/riscv/machine.c | 27 +++++++++++++++++++++++++++
9
1 file changed, 27 insertions(+)
10
11
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/machine.c
14
+++ b/target/riscv/machine.c
15
@@ -XXX,XX +XXX,XX @@ static bool vector_needed(void *opaque)
16
return riscv_has_ext(env, RVV);
17
}
18
19
+static bool pointermasking_needed(void *opaque)
20
+{
21
+ RISCVCPU *cpu = opaque;
22
+ CPURISCVState *env = &cpu->env;
23
+
24
+ return riscv_has_ext(env, RVJ);
25
+}
26
+
27
static const VMStateDescription vmstate_vector = {
28
.name = "cpu/vector",
29
.version_id = 1,
30
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_vector = {
31
}
32
};
33
34
+static const VMStateDescription vmstate_pointermasking = {
35
+ .name = "cpu/pointer_masking",
36
+ .version_id = 1,
37
+ .minimum_version_id = 1,
38
+ .needed = pointermasking_needed,
39
+ .fields = (VMStateField[]) {
40
+ VMSTATE_UINTTL(env.mmte, RISCVCPU),
41
+ VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
42
+ VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
43
+ VMSTATE_UINTTL(env.spmmask, RISCVCPU),
44
+ VMSTATE_UINTTL(env.spmbase, RISCVCPU),
45
+ VMSTATE_UINTTL(env.upmmask, RISCVCPU),
46
+ VMSTATE_UINTTL(env.upmbase, RISCVCPU),
47
+
48
+ VMSTATE_END_OF_LIST()
49
+ }
50
+};
51
+
52
static const VMStateDescription vmstate_hyper = {
53
.name = "cpu/hyper",
54
.version_id = 1,
55
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
56
&vmstate_pmp,
57
&vmstate_hyper,
58
&vmstate_vector,
59
+ &vmstate_pointermasking,
60
NULL
61
}
62
};
63
--
64
2.31.1
65
66
diff view generated by jsdifflib
[PULL 11/18] target/riscv: Print new PM CSRs in QEMU logs
Deleted patch
1
From: Alexey Baturo <baturo.alexey@gmail.com>
2
1
3
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20211025173609.2724490-6-space.monkey.delivers@gmail.com
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
---
8
target/riscv/cpu.c | 7 +++++++
9
1 file changed, 7 insertions(+)
10
11
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/cpu.c
14
+++ b/target/riscv/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
16
CSR_MSCRATCH,
17
CSR_SSCRATCH,
18
CSR_SATP,
19
+ CSR_MMTE,
20
+ CSR_UPMBASE,
21
+ CSR_UPMMASK,
22
+ CSR_SPMBASE,
23
+ CSR_SPMMASK,
24
+ CSR_MPMBASE,
25
+ CSR_MPMMASK,
26
};
27
28
for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
29
--
30
2.31.1
31
32
diff view generated by jsdifflib
[PULL 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions
Deleted patch
1
From: Alexey Baturo <baturo.alexey@gmail.com>
2
1
3
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Message-id: 20211025173609.2724490-7-space.monkey.delivers@gmail.com
7
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
---
9
target/riscv/translate.c | 8 ++++++++
10
target/riscv/insn_trans/trans_rva.c.inc | 3 +++
11
target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
12
target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
13
target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
14
5 files changed, 17 insertions(+)
15
16
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/translate.c
19
+++ b/target/riscv/translate.c
20
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
21
ctx->base.is_jmp = DISAS_NORETURN;
22
}
23
24
+/*
25
+ * Temp stub: generates address adjustment for PointerMasking
26
+ */
27
+static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
28
+{
29
+ return src;
30
+}
31
+
32
#ifndef CONFIG_USER_ONLY
33
/* The states of mstatus_fs are:
34
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
35
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/insn_trans/trans_rva.c.inc
38
+++ b/target/riscv/insn_trans/trans_rva.c.inc
39
@@ -XXX,XX +XXX,XX @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
40
if (a->rl) {
41
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
42
}
43
+ src1 = gen_pm_adjust_address(ctx, src1);
44
tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
45
if (a->aq) {
46
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
47
@@ -XXX,XX +XXX,XX @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
48
TCGLabel *l2 = gen_new_label();
49
50
src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
51
+ src1 = gen_pm_adjust_address(ctx, src1);
52
tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
53
54
/*
55
@@ -XXX,XX +XXX,XX @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
56
TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
57
TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
58
59
+ src1 = gen_pm_adjust_address(ctx, src1);
60
func(dest, src1, src2, ctx->mem_idx, mop);
61
62
gen_set_gpr(ctx, a->rd, dest);
63
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/riscv/insn_trans/trans_rvd.c.inc
66
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
67
@@ -XXX,XX +XXX,XX @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
68
tcg_gen_addi_tl(temp, addr, a->imm);
69
addr = temp;
70
}
71
+ addr = gen_pm_adjust_address(ctx, addr);
72
73
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ);
74
75
@@ -XXX,XX +XXX,XX @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
76
tcg_gen_addi_tl(temp, addr, a->imm);
77
addr = temp;
78
}
79
+ addr = gen_pm_adjust_address(ctx, addr);
80
81
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ);
82
83
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
84
index XXXXXXX..XXXXXXX 100644
85
--- a/target/riscv/insn_trans/trans_rvf.c.inc
86
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
87
@@ -XXX,XX +XXX,XX @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
88
tcg_gen_addi_tl(temp, addr, a->imm);
89
addr = temp;
90
}
91
+ addr = gen_pm_adjust_address(ctx, addr);
92
93
dest = cpu_fpr[a->rd];
94
tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
95
@@ -XXX,XX +XXX,XX @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
96
tcg_gen_addi_tl(temp, addr, a->imm);
97
addr = temp;
98
}
99
+ addr = gen_pm_adjust_address(ctx, addr);
100
101
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
102
103
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/riscv/insn_trans/trans_rvi.c.inc
106
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
107
@@ -XXX,XX +XXX,XX @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
108
tcg_gen_addi_tl(temp, addr, a->imm);
109
addr = temp;
110
}
111
+ addr = gen_pm_adjust_address(ctx, addr);
112
113
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
114
gen_set_gpr(ctx, a->rd, dest);
115
@@ -XXX,XX +XXX,XX @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
116
tcg_gen_addi_tl(temp, addr, a->imm);
117
addr = temp;
118
}
119
+ addr = gen_pm_adjust_address(ctx, addr);
120
121
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
122
return true;
123
--
124
2.31.1
125
126
diff view generated by jsdifflib
[PULL 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension
Deleted patch
1
From: Anatoly Parshintsev <kupokupokupopo@gmail.com>
2
1
3
Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Message-id: 20211025173609.2724490-8-space.monkey.delivers@gmail.com
7
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
---
9
target/riscv/cpu.h | 2 ++
10
target/riscv/cpu_helper.c | 18 ++++++++++++++++++
11
target/riscv/translate.c | 39 +++++++++++++++++++++++++++++++++++++--
12
3 files changed, 57 insertions(+), 2 deletions(-)
13
14
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/riscv/cpu.h
17
+++ b/target/riscv/cpu.h
18
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, HLSX, 10, 1)
19
FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
20
/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
21
FIELD(TB_FLAGS, XL, 13, 2)
22
+/* If PointerMasking should be applied */
23
+FIELD(TB_FLAGS, PM_ENABLED, 15, 1)
24
25
#ifdef TARGET_RISCV32
26
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
27
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/riscv/cpu_helper.c
30
+++ b/target/riscv/cpu_helper.c
31
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
32
flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
33
get_field(env->mstatus_hs, MSTATUS_FS));
34
}
35
+ if (riscv_has_ext(env, RVJ)) {
36
+ int priv = flags & TB_FLAGS_PRIV_MMU_MASK;
37
+ bool pm_enabled = false;
38
+ switch (priv) {
39
+ case PRV_U:
40
+ pm_enabled = env->mmte & U_PM_ENABLE;
41
+ break;
42
+ case PRV_S:
43
+ pm_enabled = env->mmte & S_PM_ENABLE;
44
+ break;
45
+ case PRV_M:
46
+ pm_enabled = env->mmte & M_PM_ENABLE;
47
+ break;
48
+ default:
49
+ g_assert_not_reached();
50
+ }
51
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
52
+ }
53
#endif
54
55
flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
56
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/riscv/translate.c
59
+++ b/target/riscv/translate.c
60
@@ -XXX,XX +XXX,XX @@ static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
61
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
62
static TCGv load_res;
63
static TCGv load_val;
64
+/* globals for PM CSRs */
65
+static TCGv pm_mask[4];
66
+static TCGv pm_base[4];
67
68
#include "exec/gen-icount.h"
69
70
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
71
TCGv zero;
72
/* Space for 3 operands plus 1 extra for address computation. */
73
TCGv temp[4];
74
+ /* PointerMasking extension */
75
+ bool pm_enabled;
76
+ TCGv pm_mask;
77
+ TCGv pm_base;
78
} DisasContext;
79
80
static inline bool has_ext(DisasContext *ctx, uint32_t ext)
81
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
82
}
83
84
/*
85
- * Temp stub: generates address adjustment for PointerMasking
86
+ * Generates address adjustment for PointerMasking
87
*/
88
static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
89
{
90
- return src;
91
+ TCGv temp;
92
+ if (!s->pm_enabled) {
93
+ /* Load unmodified address */
94
+ return src;
95
+ } else {
96
+ temp = temp_new(s);
97
+ tcg_gen_andc_tl(temp, src, s->pm_mask);
98
+ tcg_gen_or_tl(temp, temp, s->pm_base);
99
+ return temp;
100
+ }
101
}
102
103
#ifndef CONFIG_USER_ONLY
104
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
105
ctx->cs = cs;
106
ctx->ntemp = 0;
107
memset(ctx->temp, 0, sizeof(ctx->temp));
108
+ ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
109
+ int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
110
+ ctx->pm_mask = pm_mask[priv];
111
+ ctx->pm_base = pm_base[priv];
112
113
ctx->zero = tcg_constant_tl(0);
114
}
115
@@ -XXX,XX +XXX,XX @@ void riscv_translate_init(void)
116
"load_res");
117
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
118
"load_val");
119
+#ifndef CONFIG_USER_ONLY
120
+ /* Assign PM CSRs to tcg globals */
121
+ pm_mask[PRV_U] =
122
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
123
+ pm_base[PRV_U] =
124
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
125
+ pm_mask[PRV_S] =
126
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
127
+ pm_base[PRV_S] =
128
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
129
+ pm_mask[PRV_M] =
130
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
131
+ pm_base[PRV_M] =
132
+ tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
133
+#endif
134
}
135
--
136
2.31.1
137
138
diff view generated by jsdifflib
[PULL 14/18] target/riscv: Allow experimental J-ext to be turned on
Deleted patch
1
From: Alexey Baturo <baturo.alexey@gmail.com>
2
1
3
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20211025173609.2724490-9-space.monkey.delivers@gmail.com
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
10
target/riscv/cpu.c | 4 ++++
11
1 file changed, 4 insertions(+)
12
13
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/cpu.c
16
+++ b/target/riscv/cpu.c
17
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
18
}
19
set_vext_version(env, vext_version);
20
}
21
+ if (cpu->cfg.ext_j) {
22
+ ext |= RVJ;
23
+ }
24
25
set_misa(env, env->misa_mxl, ext);
26
}
27
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
28
DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
29
DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
30
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
31
+ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
32
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
33
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
34
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
35
--
36
2.31.1
37
38
diff view generated by jsdifflib
[PULL 15/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
Deleted patch
1
From: Chih-Min Chao <chihmin.chao@sifive.com>
2
1
3
For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN,
4
5
The original logic:
6
Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan.
7
8
The alternative path:
9
Set invalid flag if ft1 == sNaN || ft2 == sNaN.
10
Return NaN only if ft1 == NaN && ft2 == NaN.
11
12
The IEEE 754 spec allows both implementation and some architecture such
13
as riscv choose different defintions in two spec versions.
14
(riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to
15
alternative)
16
17
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
18
Signed-off-by: Frank Chang <frank.chang@sifive.com>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20211016085428.3001501-2-frank.chang@sifive.com
21
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
22
---
23
include/fpu/softfloat.h | 10 ++++++++++
24
fpu/softfloat.c | 19 +++++++++++++------
25
fpu/softfloat-parts.c.inc | 25 +++++++++++++++++++++++--
26
3 files changed, 46 insertions(+), 8 deletions(-)
27
28
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/fpu/softfloat.h
31
+++ b/include/fpu/softfloat.h
32
@@ -XXX,XX +XXX,XX @@ float16 float16_minnum(float16, float16, float_status *status);
33
float16 float16_maxnum(float16, float16, float_status *status);
34
float16 float16_minnummag(float16, float16, float_status *status);
35
float16 float16_maxnummag(float16, float16, float_status *status);
36
+float16 float16_minimum_number(float16, float16, float_status *status);
37
+float16 float16_maximum_number(float16, float16, float_status *status);
38
float16 float16_sqrt(float16, float_status *status);
39
FloatRelation float16_compare(float16, float16, float_status *status);
40
FloatRelation float16_compare_quiet(float16, float16, float_status *status);
41
@@ -XXX,XX +XXX,XX @@ bfloat16 bfloat16_minnum(bfloat16, bfloat16, float_status *status);
42
bfloat16 bfloat16_maxnum(bfloat16, bfloat16, float_status *status);
43
bfloat16 bfloat16_minnummag(bfloat16, bfloat16, float_status *status);
44
bfloat16 bfloat16_maxnummag(bfloat16, bfloat16, float_status *status);
45
+bfloat16 bfloat16_minimum_number(bfloat16, bfloat16, float_status *status);
46
+bfloat16 bfloat16_maximum_number(bfloat16, bfloat16, float_status *status);
47
bfloat16 bfloat16_sqrt(bfloat16, float_status *status);
48
FloatRelation bfloat16_compare(bfloat16, bfloat16, float_status *status);
49
FloatRelation bfloat16_compare_quiet(bfloat16, bfloat16, float_status *status);
50
@@ -XXX,XX +XXX,XX @@ float32 float32_minnum(float32, float32, float_status *status);
51
float32 float32_maxnum(float32, float32, float_status *status);
52
float32 float32_minnummag(float32, float32, float_status *status);
53
float32 float32_maxnummag(float32, float32, float_status *status);
54
+float32 float32_minimum_number(float32, float32, float_status *status);
55
+float32 float32_maximum_number(float32, float32, float_status *status);
56
bool float32_is_quiet_nan(float32, float_status *status);
57
bool float32_is_signaling_nan(float32, float_status *status);
58
float32 float32_silence_nan(float32, float_status *status);
59
@@ -XXX,XX +XXX,XX @@ float64 float64_minnum(float64, float64, float_status *status);
60
float64 float64_maxnum(float64, float64, float_status *status);
61
float64 float64_minnummag(float64, float64, float_status *status);
62
float64 float64_maxnummag(float64, float64, float_status *status);
63
+float64 float64_minimum_number(float64, float64, float_status *status);
64
+float64 float64_maximum_number(float64, float64, float_status *status);
65
bool float64_is_quiet_nan(float64 a, float_status *status);
66
bool float64_is_signaling_nan(float64, float_status *status);
67
float64 float64_silence_nan(float64, float_status *status);
68
@@ -XXX,XX +XXX,XX @@ float128 float128_minnum(float128, float128, float_status *status);
69
float128 float128_maxnum(float128, float128, float_status *status);
70
float128 float128_minnummag(float128, float128, float_status *status);
71
float128 float128_maxnummag(float128, float128, float_status *status);
72
+float128 float128_minimum_number(float128, float128, float_status *status);
73
+float128 float128_maximum_number(float128, float128, float_status *status);
74
bool float128_is_quiet_nan(float128, float_status *status);
75
bool float128_is_signaling_nan(float128, float_status *status);
76
float128 float128_silence_nan(float128, float_status *status);
77
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/fpu/softfloat.c
80
+++ b/fpu/softfloat.c
81
@@ -XXX,XX +XXX,XX @@ enum {
82
minmax_isnum = 2,
83
/* Set for the IEEE 754-2008 minNumMag() and minNumMag() operations. */
84
minmax_ismag = 4,
85
+ /*
86
+ * Set for the IEEE 754-2019 minimumNumber() and maximumNumber()
87
+ * operations.
88
+ */
89
+ minmax_isnumber = 8,
90
};
91
92
/* Simple helpers for checking if, or what kind of, NaN we have */
93
@@ -XXX,XX +XXX,XX @@ static float128 float128_minmax(float128 a, float128 b,
94
{ return type##_minmax(a, b, s, flags); }
95
96
#define MINMAX_2(type) \
97
- MINMAX_1(type, max, 0) \
98
- MINMAX_1(type, maxnum, minmax_isnum) \
99
- MINMAX_1(type, maxnummag, minmax_isnum | minmax_ismag) \
100
- MINMAX_1(type, min, minmax_ismin) \
101
- MINMAX_1(type, minnum, minmax_ismin | minmax_isnum) \
102
- MINMAX_1(type, minnummag, minmax_ismin | minmax_isnum | minmax_ismag)
103
+ MINMAX_1(type, max, 0) \
104
+ MINMAX_1(type, maxnum, minmax_isnum) \
105
+ MINMAX_1(type, maxnummag, minmax_isnum | minmax_ismag) \
106
+ MINMAX_1(type, maximum_number, minmax_isnumber) \
107
+ MINMAX_1(type, min, minmax_ismin) \
108
+ MINMAX_1(type, minnum, minmax_ismin | minmax_isnum) \
109
+ MINMAX_1(type, minnummag, minmax_ismin | minmax_isnum | minmax_ismag) \
110
+ MINMAX_1(type, minimum_number, minmax_ismin | minmax_isnumber) \
111
112
MINMAX_2(float16)
113
MINMAX_2(bfloat16)
114
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
115
index XXXXXXX..XXXXXXX 100644
116
--- a/fpu/softfloat-parts.c.inc
117
+++ b/fpu/softfloat-parts.c.inc
118
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(minmax)(FloatPartsN *a, FloatPartsN *b,
119
120
if (unlikely(ab_mask & float_cmask_anynan)) {
121
/*
122
- * For minnum/maxnum, if one operand is a QNaN, and the other
123
+ * For minNum/maxNum (IEEE 754-2008)
124
+ * or minimumNumber/maximumNumber (IEEE 754-2019),
125
+ * if one operand is a QNaN, and the other
126
* operand is numerical, then return numerical argument.
127
*/
128
- if ((flags & minmax_isnum)
129
+ if ((flags & (minmax_isnum | minmax_isnumber))
130
&& !(ab_mask & float_cmask_snan)
131
&& (ab_mask & ~float_cmask_qnan)) {
132
return is_nan(a->cls) ? b : a;
133
}
134
+
135
+ /*
136
+ * In IEEE 754-2019, minNum, maxNum, minNumMag and maxNumMag
137
+ * are removed and replaced with minimum, minimumNumber, maximum
138
+ * and maximumNumber.
139
+ * minimumNumber/maximumNumber behavior for SNaN is changed to:
140
+ * If both operands are NaNs, a QNaN is returned.
141
+ * If either operand is a SNaN,
142
+ * an invalid operation exception is signaled,
143
+ * but unless both operands are NaNs,
144
+ * the SNaN is otherwise ignored and not converted to a QNaN.
145
+ */
146
+ if ((flags & minmax_isnumber)
147
+ && (ab_mask & float_cmask_snan)
148
+ && (ab_mask & ~float_cmask_anynan)) {
149
+ float_raise(float_flag_invalid, s);
150
+ return is_nan(a->cls) ? b : a;
151
+ }
152
+
153
return parts_pick_nan(a, b, s);
154
}
155
156
--
157
2.31.1
158
159
diff view generated by jsdifflib
[PULL 16/18] target/riscv: change the api for RVF/RVD fmin/fmax
Deleted patch
1
From: Chih-Min Chao <chihmin.chao@sifive.com>
2
1
3
The sNaN propagation behavior has been changed since
4
cd20cee7 in https://github.com/riscv/riscv-isa-manual.
5
6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
7
Signed-off-by: Frank Chang <frank.chang@sifive.com>
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20211016085428.3001501-3-frank.chang@sifive.com
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/fpu_helper.c | 16 ++++++++++++----
13
1 file changed, 12 insertions(+), 4 deletions(-)
14
15
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/fpu_helper.c
18
+++ b/target/riscv/fpu_helper.c
19
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
20
{
21
float32 frs1 = check_nanbox_s(rs1);
22
float32 frs2 = check_nanbox_s(rs2);
23
- return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status));
24
+ return nanbox_s(env->priv_ver < PRIV_VERSION_1_11_0 ?
25
+ float32_minnum(frs1, frs2, &env->fp_status) :
26
+ float32_minimum_number(frs1, frs2, &env->fp_status));
27
}
28
29
uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
30
{
31
float32 frs1 = check_nanbox_s(rs1);
32
float32 frs2 = check_nanbox_s(rs2);
33
- return nanbox_s(float32_maxnum(frs1, frs2, &env->fp_status));
34
+ return nanbox_s(env->priv_ver < PRIV_VERSION_1_11_0 ?
35
+ float32_maxnum(frs1, frs2, &env->fp_status) :
36
+ float32_maximum_number(frs1, frs2, &env->fp_status));
37
}
38
39
uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1)
40
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
41
42
uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
43
{
44
- return float64_minnum(frs1, frs2, &env->fp_status);
45
+ return env->priv_ver < PRIV_VERSION_1_11_0 ?
46
+ float64_minnum(frs1, frs2, &env->fp_status) :
47
+ float64_minimum_number(frs1, frs2, &env->fp_status);
48
}
49
50
uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
51
{
52
- return float64_maxnum(frs1, frs2, &env->fp_status);
53
+ return env->priv_ver < PRIV_VERSION_1_11_0 ?
54
+ float64_maxnum(frs1, frs2, &env->fp_status) :
55
+ float64_maximum_number(frs1, frs2, &env->fp_status);
56
}
57
58
uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1)
59
--
60
2.31.1
61
62
diff view generated by jsdifflib
[PULL 17/18] target/riscv: fix VS interrupts forwarding to HS
[PULL 1/2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
1
From: Jose Martins <josemartins90@gmail.com>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when
3
Configuring a drive with "if=none" is meant for creation of a backend
4
not delegated in hideleg (which was not being taken into account). This
4
only, it should not get automatically assigned to a device frontend.
5
was mainly because hs level sie was not always considered enabled when
5
Use "if=pflash" for the One-Time-Programmable device instead (like
6
it should. The spec states that "Interrupts for higher-privilege modes,
6
it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).
7
y>x, are always globally enabled regardless of the setting of the global
8
yIE bit for the higher-privilege mode." and also "For purposes of
9
interrupt global enables, HS-mode is considered more privileged than
10
VS-mode, and VS-mode is considered more privileged than VU-mode". Also,
11
vs-level interrupts were not being taken into account unless V=1, but
12
should be unless delegated.
13
7
14
Finally, there is no need for a special case for to handle vs interrupts
8
Since the old way of configuring the device has already been published
15
as the current privilege level, the state of the global ie and of the
9
with the previous QEMU versions, we cannot remove this immediately, but
16
delegation registers should be enough to route all interrupts to the
10
have to deprecate it and support it for at least two more releases.
17
appropriate privilege level in riscv_cpu_do_interrupt.
18
11
19
Signed-off-by: Jose Martins <josemartins90@gmail.com>
12
Signed-off-by: Thomas Huth <thuth@redhat.com>
13
Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Markus Armbruster <armbru@redhat.com>
20
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
21
Message-id: 20211026145126.11025-2-josemartins90@gmail.com
16
Message-id: 20211119102549.217755-1-thuth@redhat.com
22
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
23
---
18
---
24
target/riscv/cpu_helper.c | 28 ++++++++--------------------
19
docs/about/deprecated.rst | 6 ++++++
25
1 file changed, 8 insertions(+), 20 deletions(-)
20
hw/misc/sifive_u_otp.c | 9 ++++++++-
21
2 files changed, 14 insertions(+), 1 deletion(-)
26
22
27
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
23
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
28
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
29
--- a/target/riscv/cpu_helper.c
25
--- a/docs/about/deprecated.rst
30
+++ b/target/riscv/cpu_helper.c
26
+++ b/docs/about/deprecated.rst
31
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
27
@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
32
#ifndef CONFIG_USER_ONLY
28
However, short-form booleans are deprecated and full explicit ``arg_name=on``
33
static int riscv_cpu_local_irq_pending(CPURISCVState *env)
29
form is preferred.
34
{
30
35
- target_ulong irqs;
31
+``-drive if=none`` for the sifive_u OTP device (since 6.2)
36
+ target_ulong virt_enabled = riscv_cpu_virt_enabled(env);
32
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
37
33
+
38
target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
34
+Using ``-drive if=none`` to configure the OTP device of the sifive_u
39
target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
35
+RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
40
- target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE);
36
+
41
37
42
- target_ulong pending = env->mip & env->mie &
38
QEMU Machine Protocol (QMP) commands
43
- ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
39
------------------------------------
44
- target_ulong vspending = (env->mip & env->mie &
40
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
45
- (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
41
index XXXXXXX..XXXXXXX 100644
46
+ target_ulong pending = env->mip & env->mie;
42
--- a/hw/misc/sifive_u_otp.c
47
43
+++ b/hw/misc/sifive_u_otp.c
48
target_ulong mie = env->priv < PRV_M ||
44
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
49
(env->priv == PRV_M && mstatus_mie);
45
TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
50
target_ulong sie = env->priv < PRV_S ||
46
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
51
(env->priv == PRV_S && mstatus_sie);
47
52
- target_ulong hs_sie = env->priv < PRV_S ||
48
- dinfo = drive_get_next(IF_NONE);
53
- (env->priv == PRV_S && hs_mstatus_sie);
49
+ dinfo = drive_get_next(IF_PFLASH);
54
+ target_ulong hsie = virt_enabled || sie;
50
+ if (!dinfo) {
55
+ target_ulong vsie = virt_enabled && sie;
51
+ dinfo = drive_get_next(IF_NONE);
56
52
+ if (dinfo) {
57
- if (riscv_cpu_virt_enabled(env)) {
53
+ warn_report("using \"-drive if=none\" for the OTP is deprecated, "
58
- target_ulong pending_hs_irq = pending & -hs_sie;
54
+ "use \"-drive if=pflash\" instead.");
59
-
55
+ }
60
- if (pending_hs_irq) {
56
+ }
61
- riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP);
57
if (dinfo) {
62
- return ctz64(pending_hs_irq);
58
int ret;
63
- }
59
uint64_t perm;
64
-
65
- pending = vspending;
66
- }
67
-
68
- irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie);
69
+ target_ulong irqs =
70
+ (pending & ~env->mideleg & -mie) |
71
+ (pending & env->mideleg & ~env->hideleg & -hsie) |
72
+ (pending & env->mideleg & env->hideleg & -vsie);
73
74
if (irqs) {
75
return ctz64(irqs); /* since non-zero */
76
--
60
--
77
2.31.1
61
2.31.1
78
62
79
63
diff view generated by jsdifflib
[PULL 18/18] target/riscv: remove force HS exception
[PULL 2/2] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
1
From: Jose Martins <josemartins90@gmail.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
There is no need to "force an hs exception" as the current privilege
3
Once a "One Time Programmable" is programmed, it shouldn't be reset.
4
level, the state of the global ie and of the delegation registers should
5
be enough to route the interrupt to the appropriate privilege level in
6
riscv_cpu_do_interrupt. The is true for both asynchronous and
7
synchronous exceptions, specifically, guest page faults which must be
8
hardwired to zero hedeleg. As such the hs_force_except mechanism can be
9
removed.
10
4
11
Signed-off-by: Jose Martins <josemartins90@gmail.com>
5
Do not re-initialize the OTP content in the DeviceReset handler,
6
initialize it once in the DeviceRealize one.
7
8
Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20211026145126.11025-3-josemartins90@gmail.com
11
Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
13
---
16
target/riscv/cpu.h | 2 --
14
hw/misc/sifive_u_otp.c | 13 +++++--------
17
target/riscv/cpu_bits.h | 6 ------
15
1 file changed, 5 insertions(+), 8 deletions(-)
18
target/riscv/cpu_helper.c | 26 +-------------------------
19
3 files changed, 1 insertion(+), 33 deletions(-)
20
16
21
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
17
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
22
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu.h
19
--- a/hw/misc/sifive_u_otp.c
24
+++ b/target/riscv/cpu.h
20
+++ b/hw/misc/sifive_u_otp.c
25
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
21
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
26
bool riscv_cpu_fp_enabled(CPURISCVState *env);
22
27
bool riscv_cpu_virt_enabled(CPURISCVState *env);
23
if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
28
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
24
error_setg(errp, "failed to read the initial flash content");
29
-bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
25
+ return;
30
-void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
26
}
31
bool riscv_cpu_two_stage_lookup(int mmu_idx);
27
}
32
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
28
}
33
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
34
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/riscv/cpu_bits.h
37
+++ b/target/riscv/cpu_bits.h
38
@@ -XXX,XX +XXX,XX @@ typedef enum {
39
40
/* Virtulisation Register Fields */
41
#define VIRT_ONOFF 1
42
-/* This is used to save state for when we take an exception. If this is set
43
- * that means that we want to force a HS level exception (no matter what the
44
- * delegation is set to). This will occur for things such as a second level
45
- * page table fault.
46
- */
47
-#define FORCE_HS_EXCEP 2
48
49
/* RV32 satp CSR field masks */
50
#define SATP32_MODE 0x80000000
51
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/riscv/cpu_helper.c
54
+++ b/target/riscv/cpu_helper.c
55
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
56
env->virt = set_field(env->virt, VIRT_ONOFF, enable);
57
}
58
59
-bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env)
60
-{
61
- if (!riscv_has_ext(env, RVH)) {
62
- return false;
63
- }
64
-
65
- return get_field(env->virt, FORCE_HS_EXCEP);
66
-}
29
-}
67
-
30
-
68
-void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
31
-static void sifive_u_otp_reset(DeviceState *dev)
69
-{
32
-{
70
- if (!riscv_has_ext(env, RVH)) {
33
- SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
71
- return;
34
72
- }
35
/* Initialize all fuses' initial value to 0xFFs */
73
-
36
memset(s->fuse, 0xff, sizeof(s->fuse));
74
- env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
37
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
75
-}
38
serial_data = s->serial;
76
-
39
if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
77
bool riscv_cpu_two_stage_lookup(int mmu_idx)
40
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
78
{
41
- error_report("write error index<%d>", index);
79
return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
42
+ error_setg(errp, "failed to write index<%d>", index);
80
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
43
+ return;
81
82
RISCVCPU *cpu = RISCV_CPU(cs);
83
CPURISCVState *env = &cpu->env;
84
- bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env);
85
uint64_t s;
86
87
/* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
88
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
89
case RISCV_EXCP_INST_GUEST_PAGE_FAULT:
90
case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
91
case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
92
- force_hs_execp = true;
93
- /* fallthrough */
94
case RISCV_EXCP_INST_ADDR_MIS:
95
case RISCV_EXCP_INST_ACCESS_FAULT:
96
case RISCV_EXCP_LOAD_ADDR_MIS:
97
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
98
env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
99
}
100
101
- if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
102
- !force_hs_execp) {
103
+ if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) {
104
/* Trap to VS mode */
105
/*
106
* See if we need to adjust cause. Yes if its VS mode interrupt
107
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
108
htval = env->guest_phys_fault_addr;
109
110
riscv_cpu_set_virt_enabled(env, 0);
111
- riscv_cpu_set_force_hs_excep(env, 0);
112
} else {
113
/* Trap into HS mode */
114
env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
115
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
116
117
/* Trapping to M mode, virt is disabled */
118
riscv_cpu_set_virt_enabled(env, 0);
119
- riscv_cpu_set_force_hs_excep(env, 0);
120
}
44
}
121
45
122
s = env->mstatus;
46
serial_data = ~(s->serial);
47
if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
48
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
49
- error_report("write error index<%d>", index + 1);
50
+ error_setg(errp, "failed to write index<%d>", index + 1);
51
+ return;
52
}
53
}
54
55
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
56
57
device_class_set_props(dc, sifive_u_otp_properties);
58
dc->realize = sifive_u_otp_realize;
59
- dc->reset = sifive_u_otp_reset;
60
}
61
62
static const TypeInfo sifive_u_otp_info = {
123
--
63
--
124
2.31.1
64
2.31.1
125
65
126
66
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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