[v4] QEMU RISC-V AIA support

[PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts

Posted by Anup Patel 4 years, 3 months ago

The guest external interrupts from an interrupt controller are
delivered only when the Guest/VM is running (i.e. V=1). This means
any guest external interrupt which is triggered while the Guest/VM
is not running (i.e. V=0) will be missed on QEMU resulting in Guest
with sluggish response to serial console input and other I/O events.

To solve this, we check and inject interrupt after setting V=1.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 target/riscv/cpu_helper.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index bb7ac9890b..04df3792a8 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -287,6 +287,19 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
     }
 
     env->virt = set_field(env->virt, VIRT_ONOFF, enable);
+
+    if (enable) {
+       /*
+        * The guest external interrupts from an interrupt controller are
+        * delivered only when the Guest/VM is running (i.e. V=1). This means
+        * any guest external interrupt which is triggered while the Guest/VM
+        * is not running (i.e. V=0) will be missed on QEMU resulting in guest
+        * with sluggish response to serial console input and other I/O events.
+        *
+        * To solve this, we check and inject interrupt after setting V=1.
+        */
+        riscv_cpu_update_mip(env_archcpu(env), 0, 0);
+    }
 }
 
 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env)
-- 
2.25.1

Re: [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts

Posted by Alistair Francis 4 years, 3 months ago

On Tue, Oct 26, 2021 at 5:41 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The guest external interrupts from an interrupt controller are
> delivered only when the Guest/VM is running (i.e. V=1). This means
> any guest external interrupt which is triggered while the Guest/VM
> is not running (i.e. V=0) will be missed on QEMU resulting in Guest
> with sluggish response to serial console input and other I/O events.
>
> To solve this, we check and inject interrupt after setting V=1.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_helper.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index bb7ac9890b..04df3792a8 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -287,6 +287,19 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable)
>      }
>
>      env->virt = set_field(env->virt, VIRT_ONOFF, enable);
> +
> +    if (enable) {
> +       /*
> +        * The guest external interrupts from an interrupt controller are
> +        * delivered only when the Guest/VM is running (i.e. V=1). This means
> +        * any guest external interrupt which is triggered while the Guest/VM
> +        * is not running (i.e. V=0) will be missed on QEMU resulting in guest
> +        * with sluggish response to serial console input and other I/O events.
> +        *
> +        * To solve this, we check and inject interrupt after setting V=1.
> +        */
> +        riscv_cpu_update_mip(env_archcpu(env), 0, 0);
> +    }
>  }
>
>  bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env)
> --
> 2.25.1
>
>