1 | The following changes since commit 6587b0c1331d427b0939c37e763842550ed581db: | 1 | The following changes since commit 7c18f2d663521f1b31b821a13358ce38075eaf7d: |
---|---|---|---|
2 | 2 | ||
3 | Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-10-15' into staging (2021-10-15 14:16:28 -0700) | 3 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-04-29 23:07:17 +0100) |
4 | 4 | ||
5 | are available in the Git repository at: | 5 | are available in the Git repository at: |
6 | 6 | ||
7 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211016 | 7 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230502 |
8 | 8 | ||
9 | for you to fetch changes up to 995b87dedc78b0467f5f18bbc3546072ba97516a: | 9 | for you to fetch changes up to bdc7fba1c5a29ae218b45353daac9308fe1aae82: |
10 | 10 | ||
11 | Revert "cpu: Move cpu_common_props to hw/core/cpu.c" (2021-10-15 16:39:15 -0700) | 11 | tcg: Introduce tcg_out_movext2 (2023-05-02 12:15:41 +0100) |
12 | 12 | ||
13 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
14 | Move gdb singlestep to generic code | 14 | Misc tcg-related patch queue. |
15 | Fix cpu_common_props | ||
16 | 15 | ||
17 | ---------------------------------------------------------------- | 16 | ---------------------------------------------------------------- |
18 | Richard Henderson (24): | 17 | Dickon Hood (1): |
19 | accel/tcg: Handle gdb singlestep in cpu_tb_exec | 18 | qemu/bitops.h: Limit rotate amounts |
20 | target/alpha: Drop checks for singlestep_enabled | ||
21 | target/avr: Drop checks for singlestep_enabled | ||
22 | target/cris: Drop checks for singlestep_enabled | ||
23 | target/hexagon: Drop checks for singlestep_enabled | ||
24 | target/arm: Drop checks for singlestep_enabled | ||
25 | target/hppa: Drop checks for singlestep_enabled | ||
26 | target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt | ||
27 | target/i386: Drop check for singlestep_enabled | ||
28 | target/m68k: Drop checks for singlestep_enabled | ||
29 | target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP | ||
30 | target/microblaze: Drop checks for singlestep_enabled | ||
31 | target/mips: Fix single stepping | ||
32 | target/mips: Drop exit checks for singlestep_enabled | ||
33 | target/openrisc: Drop checks for singlestep_enabled | ||
34 | target/ppc: Drop exit checks for singlestep_enabled | ||
35 | target/riscv: Remove dead code after exception | ||
36 | target/riscv: Remove exit_tb and lookup_and_goto_ptr | ||
37 | target/rx: Drop checks for singlestep_enabled | ||
38 | target/s390x: Drop check for singlestep_enabled | ||
39 | target/sh4: Drop check for singlestep_enabled | ||
40 | target/tricore: Drop check for singlestep_enabled | ||
41 | target/xtensa: Drop check for singlestep_enabled | ||
42 | Revert "cpu: Move cpu_common_props to hw/core/cpu.c" | ||
43 | 19 | ||
44 | include/hw/core/cpu.h | 1 + | 20 | Kiran Ostrolenk (1): |
45 | target/i386/helper.h | 1 - | 21 | qemu/host-utils.h: Add clz and ctz functions for lower-bit integers |
46 | target/rx/helper.h | 1 - | ||
47 | target/sh4/helper.h | 1 - | ||
48 | target/tricore/helper.h | 1 - | ||
49 | accel/tcg/cpu-exec.c | 11 ++++ | ||
50 | cpu.c | 21 ++++++++ | ||
51 | hw/core/cpu-common.c | 17 +----- | ||
52 | target/alpha/translate.c | 13 ++--- | ||
53 | target/arm/translate-a64.c | 10 +--- | ||
54 | target/arm/translate.c | 36 +++---------- | ||
55 | target/avr/translate.c | 19 ++----- | ||
56 | target/cris/translate.c | 16 ------ | ||
57 | target/hexagon/translate.c | 12 +---- | ||
58 | target/hppa/translate.c | 17 ++---- | ||
59 | target/i386/tcg/misc_helper.c | 8 --- | ||
60 | target/i386/tcg/translate.c | 9 ++-- | ||
61 | target/m68k/translate.c | 44 ++++----------- | ||
62 | target/microblaze/translate.c | 18 ++----- | ||
63 | target/mips/tcg/translate.c | 75 ++++++++++++-------------- | ||
64 | target/openrisc/translate.c | 18 ++----- | ||
65 | target/ppc/translate.c | 38 +++---------- | ||
66 | target/riscv/translate.c | 27 +--------- | ||
67 | target/rx/op_helper.c | 8 --- | ||
68 | target/rx/translate.c | 12 +---- | ||
69 | target/s390x/tcg/translate.c | 8 +-- | ||
70 | target/sh4/op_helper.c | 5 -- | ||
71 | target/sh4/translate.c | 14 ++--- | ||
72 | target/tricore/op_helper.c | 7 --- | ||
73 | target/tricore/translate.c | 14 +---- | ||
74 | target/xtensa/translate.c | 25 +++------ | ||
75 | target/riscv/insn_trans/trans_privileged.c.inc | 10 ++-- | ||
76 | target/riscv/insn_trans/trans_rvi.c.inc | 8 ++- | ||
77 | target/riscv/insn_trans/trans_rvv.c.inc | 2 +- | ||
78 | 34 files changed, 141 insertions(+), 386 deletions(-) | ||
79 | 22 | ||
23 | Nazar Kazakov (2): | ||
24 | tcg: Add tcg_gen_gvec_andcs | ||
25 | tcg: Add tcg_gen_gvec_rotrs | ||
26 | |||
27 | Richard Henderson (7): | ||
28 | softmmu: Tidy dirtylimit_dirty_ring_full_time | ||
29 | qemu/int128: Re-shuffle Int128Alias members | ||
30 | migration/xbzrle: Use __attribute__((target)) for avx512 | ||
31 | accel/tcg: Add cpu_ld*_code_mmu | ||
32 | tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 | ||
33 | tcg/mips: Conditionalize tcg_out_exts_i32_i64 | ||
34 | tcg: Introduce tcg_out_movext2 | ||
35 | |||
36 | Weiwei Li (1): | ||
37 | accel/tcg: Uncache the host address for instruction fetch when tlb size < 1 | ||
38 | |||
39 | meson.build | 5 +-- | ||
40 | accel/tcg/tcg-runtime.h | 1 + | ||
41 | include/exec/cpu_ldst.h | 9 ++++++ | ||
42 | include/qemu/bitops.h | 24 +++++++++----- | ||
43 | include/qemu/host-utils.h | 54 +++++++++++++++++++++++++++++++ | ||
44 | include/qemu/int128.h | 4 +-- | ||
45 | include/tcg/tcg-op-gvec.h | 4 +++ | ||
46 | accel/tcg/cputlb.c | 53 ++++++++++++++++++++++++++++++ | ||
47 | accel/tcg/tcg-runtime-gvec.c | 11 +++++++ | ||
48 | accel/tcg/user-exec.c | 58 +++++++++++++++++++++++++++++++++ | ||
49 | migration/xbzrle.c | 9 +++--- | ||
50 | softmmu/dirtylimit.c | 15 ++++++--- | ||
51 | tcg/tcg-op-gvec.c | 28 ++++++++++++++++ | ||
52 | tcg/tcg.c | 69 +++++++++++++++++++++++++++++++++++++--- | ||
53 | tcg/arm/tcg-target.c.inc | 44 +++++++++++-------------- | ||
54 | tcg/i386/tcg-target.c.inc | 19 +++++------ | ||
55 | tcg/loongarch64/tcg-target.c.inc | 4 ++- | ||
56 | tcg/mips/tcg-target.c.inc | 4 ++- | ||
57 | 18 files changed, 347 insertions(+), 68 deletions(-) | diff view generated by jsdifflib |
1 | GDB single-stepping is now handled generically, which means | 1 | Drop inline marker: let compiler decide. |
---|---|---|---|
2 | we don't need to do anything in the wrappers. | ||
3 | 2 | ||
4 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 3 | Change return type to uint64_t: this matches the computation in the |
4 | return statement and the local variable assignment in the caller. | ||
5 | |||
6 | Rename local to dirty_ring_size_MB to fix typo. | ||
7 | Simplify conversion to MiB via qemu_target_page_bits and right shift. | ||
8 | |||
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
10 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
11 | Reviewed-by: Juan Quintela <quintela@redhat.com> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 13 | --- |
7 | target/riscv/translate.c | 27 +------------------ | 14 | softmmu/dirtylimit.c | 15 ++++++++++----- |
8 | .../riscv/insn_trans/trans_privileged.c.inc | 4 +-- | 15 | 1 file changed, 10 insertions(+), 5 deletions(-) |
9 | target/riscv/insn_trans/trans_rvi.c.inc | 8 +++--- | ||
10 | target/riscv/insn_trans/trans_rvv.c.inc | 2 +- | ||
11 | 4 files changed, 7 insertions(+), 34 deletions(-) | ||
12 | 16 | ||
13 | diff --git a/target/riscv/translate.c b/target/riscv/translate.c | 17 | diff --git a/softmmu/dirtylimit.c b/softmmu/dirtylimit.c |
14 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/riscv/translate.c | 19 | --- a/softmmu/dirtylimit.c |
16 | +++ b/target/riscv/translate.c | 20 | +++ b/softmmu/dirtylimit.c |
17 | @@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp) | 21 | @@ -XXX,XX +XXX,XX @@ bool dirtylimit_vcpu_index_valid(int cpu_index) |
18 | ctx->base.is_jmp = DISAS_NORETURN; | 22 | cpu_index >= ms->smp.max_cpus); |
19 | } | 23 | } |
20 | 24 | ||
21 | -static void gen_exception_debug(void) | 25 | -static inline int64_t dirtylimit_dirty_ring_full_time(uint64_t dirtyrate) |
22 | -{ | 26 | +static uint64_t dirtylimit_dirty_ring_full_time(uint64_t dirtyrate) |
23 | - gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG)); | ||
24 | -} | ||
25 | - | ||
26 | -/* Wrapper around tcg_gen_exit_tb that handles single stepping */ | ||
27 | -static void exit_tb(DisasContext *ctx) | ||
28 | -{ | ||
29 | - if (ctx->base.singlestep_enabled) { | ||
30 | - gen_exception_debug(); | ||
31 | - } else { | ||
32 | - tcg_gen_exit_tb(NULL, 0); | ||
33 | - } | ||
34 | -} | ||
35 | - | ||
36 | -/* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */ | ||
37 | -static void lookup_and_goto_ptr(DisasContext *ctx) | ||
38 | -{ | ||
39 | - if (ctx->base.singlestep_enabled) { | ||
40 | - gen_exception_debug(); | ||
41 | - } else { | ||
42 | - tcg_gen_lookup_and_goto_ptr(); | ||
43 | - } | ||
44 | -} | ||
45 | - | ||
46 | static void gen_exception_illegal(DisasContext *ctx) | ||
47 | { | 27 | { |
48 | generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); | 28 | static uint64_t max_dirtyrate; |
49 | @@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) | 29 | - uint32_t dirty_ring_size = kvm_dirty_ring_size(); |
50 | tcg_gen_exit_tb(ctx->base.tb, n); | 30 | - uint64_t dirty_ring_size_meory_MB = |
51 | } else { | 31 | - dirty_ring_size * qemu_target_page_size() >> 20; |
52 | tcg_gen_movi_tl(cpu_pc, dest); | 32 | + unsigned target_page_bits = qemu_target_page_bits(); |
53 | - lookup_and_goto_ptr(ctx); | 33 | + uint64_t dirty_ring_size_MB; |
54 | + tcg_gen_lookup_and_goto_ptr(); | 34 | + |
35 | + /* So far, the largest (non-huge) page size is 64k, i.e. 16 bits. */ | ||
36 | + assert(target_page_bits < 20); | ||
37 | + | ||
38 | + /* Convert ring size (pages) to MiB (2**20). */ | ||
39 | + dirty_ring_size_MB = kvm_dirty_ring_size() >> (20 - target_page_bits); | ||
40 | |||
41 | if (max_dirtyrate < dirtyrate) { | ||
42 | max_dirtyrate = dirtyrate; | ||
55 | } | 43 | } |
44 | |||
45 | - return dirty_ring_size_meory_MB * 1000000 / max_dirtyrate; | ||
46 | + return dirty_ring_size_MB * 1000000 / max_dirtyrate; | ||
56 | } | 47 | } |
57 | 48 | ||
58 | diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc | 49 | static inline bool dirtylimit_done(uint64_t quota, |
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/riscv/insn_trans/trans_privileged.c.inc | ||
61 | +++ b/target/riscv/insn_trans/trans_privileged.c.inc | ||
62 | @@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) | ||
63 | |||
64 | if (has_ext(ctx, RVS)) { | ||
65 | gen_helper_sret(cpu_pc, cpu_env, cpu_pc); | ||
66 | - exit_tb(ctx); /* no chaining */ | ||
67 | + tcg_gen_exit_tb(NULL, 0); /* no chaining */ | ||
68 | ctx->base.is_jmp = DISAS_NORETURN; | ||
69 | } else { | ||
70 | return false; | ||
71 | @@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) | ||
72 | #ifndef CONFIG_USER_ONLY | ||
73 | tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); | ||
74 | gen_helper_mret(cpu_pc, cpu_env, cpu_pc); | ||
75 | - exit_tb(ctx); /* no chaining */ | ||
76 | + tcg_gen_exit_tb(NULL, 0); /* no chaining */ | ||
77 | ctx->base.is_jmp = DISAS_NORETURN; | ||
78 | return true; | ||
79 | #else | ||
80 | diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc | ||
81 | index XXXXXXX..XXXXXXX 100644 | ||
82 | --- a/target/riscv/insn_trans/trans_rvi.c.inc | ||
83 | +++ b/target/riscv/insn_trans/trans_rvi.c.inc | ||
84 | @@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) | ||
85 | if (a->rd != 0) { | ||
86 | tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn); | ||
87 | } | ||
88 | - | ||
89 | - /* No chaining with JALR. */ | ||
90 | - lookup_and_goto_ptr(ctx); | ||
91 | + tcg_gen_lookup_and_goto_ptr(); | ||
92 | |||
93 | if (misaligned) { | ||
94 | gen_set_label(misaligned); | ||
95 | @@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a) | ||
96 | * however we need to end the translation block | ||
97 | */ | ||
98 | tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); | ||
99 | - exit_tb(ctx); | ||
100 | + tcg_gen_exit_tb(NULL, 0); | ||
101 | ctx->base.is_jmp = DISAS_NORETURN; | ||
102 | return true; | ||
103 | } | ||
104 | @@ -XXX,XX +XXX,XX @@ static bool do_csr_post(DisasContext *ctx) | ||
105 | { | ||
106 | /* We may have changed important cpu state -- exit to main loop. */ | ||
107 | tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); | ||
108 | - exit_tb(ctx); | ||
109 | + tcg_gen_exit_tb(NULL, 0); | ||
110 | ctx->base.is_jmp = DISAS_NORETURN; | ||
111 | return true; | ||
112 | } | ||
113 | diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc | ||
114 | index XXXXXXX..XXXXXXX 100644 | ||
115 | --- a/target/riscv/insn_trans/trans_rvv.c.inc | ||
116 | +++ b/target/riscv/insn_trans/trans_rvv.c.inc | ||
117 | @@ -XXX,XX +XXX,XX @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) | ||
118 | gen_set_gpr(ctx, a->rd, dst); | ||
119 | |||
120 | tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); | ||
121 | - lookup_and_goto_ptr(ctx); | ||
122 | + tcg_gen_lookup_and_goto_ptr(); | ||
123 | ctx->base.is_jmp = DISAS_NORETURN; | ||
124 | return true; | ||
125 | } | ||
126 | -- | 50 | -- |
127 | 2.25.1 | 51 | 2.34.1 |
128 | 52 | ||
129 | 53 | diff view generated by jsdifflib |
1 | Currently the change in cpu_tb_exec is masked by the debug exception | 1 | From: Weiwei Li <liweiwei@iscas.ac.cn> |
---|---|---|---|
2 | being raised by the translators. But this allows us to remove that code. | ||
3 | 2 | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 3 | When PMP entry overlap part of the page, we'll set the tlb_size to 1, which |
4 | will make the address in tlb entry set with TLB_INVALID_MASK, and the next | ||
5 | access will again go through tlb_fill.However, this way will not work in | ||
6 | tb_gen_code() => get_page_addr_code_hostp(): the TLB host address will be | ||
7 | cached, and the following instructions can use this host address directly | ||
8 | which may lead to the bypass of PMP related check. | ||
9 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1542. | ||
10 | |||
11 | Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
12 | Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> | ||
13 | Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-Id: <20230422130329.23555-6-liweiwei@iscas.ac.cn> | ||
5 | --- | 16 | --- |
6 | accel/tcg/cpu-exec.c | 11 +++++++++++ | 17 | accel/tcg/cputlb.c | 5 +++++ |
7 | 1 file changed, 11 insertions(+) | 18 | 1 file changed, 5 insertions(+) |
8 | 19 | ||
9 | diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c | 20 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c |
10 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
11 | --- a/accel/tcg/cpu-exec.c | 22 | --- a/accel/tcg/cputlb.c |
12 | +++ b/accel/tcg/cpu-exec.c | 23 | +++ b/accel/tcg/cputlb.c |
13 | @@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) | 24 | @@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr, |
14 | cc->set_pc(cpu, last_tb->pc); | 25 | if (p == NULL) { |
15 | } | 26 | return -1; |
16 | } | 27 | } |
17 | + | 28 | + |
18 | + /* | 29 | + if (full->lg_page_size < TARGET_PAGE_BITS) { |
19 | + * If gdb single-step, and we haven't raised another exception, | 30 | + return -1; |
20 | + * raise a debug exception. Single-step with another exception | ||
21 | + * is handled in cpu_handle_exception. | ||
22 | + */ | ||
23 | + if (unlikely(cpu->singlestep_enabled) && cpu->exception_index == -1) { | ||
24 | + cpu->exception_index = EXCP_DEBUG; | ||
25 | + cpu_loop_exit(cpu); | ||
26 | + } | 31 | + } |
27 | + | 32 | + |
28 | return last_tb; | 33 | if (hostp) { |
29 | } | 34 | *hostp = p; |
30 | 35 | } | |
31 | -- | 36 | -- |
32 | 2.25.1 | 37 | 2.34.1 |
33 | |||
34 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | GDB single-stepping is now handled generically. | ||
2 | 1 | ||
3 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | target/alpha/translate.c | 13 +++---------- | ||
7 | 1 file changed, 3 insertions(+), 10 deletions(-) | ||
8 | |||
9 | diff --git a/target/alpha/translate.c b/target/alpha/translate.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/target/alpha/translate.c | ||
12 | +++ b/target/alpha/translate.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
14 | tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); | ||
15 | /* FALLTHRU */ | ||
16 | case DISAS_PC_UPDATED: | ||
17 | - if (!ctx->base.singlestep_enabled) { | ||
18 | - tcg_gen_lookup_and_goto_ptr(); | ||
19 | - break; | ||
20 | - } | ||
21 | - /* FALLTHRU */ | ||
22 | + tcg_gen_lookup_and_goto_ptr(); | ||
23 | + break; | ||
24 | case DISAS_PC_UPDATED_NOCHAIN: | ||
25 | - if (ctx->base.singlestep_enabled) { | ||
26 | - gen_excp_1(EXCP_DEBUG, 0); | ||
27 | - } else { | ||
28 | - tcg_gen_exit_tb(NULL, 0); | ||
29 | - } | ||
30 | + tcg_gen_exit_tb(NULL, 0); | ||
31 | break; | ||
32 | default: | ||
33 | g_assert_not_reached(); | ||
34 | -- | ||
35 | 2.25.1 | ||
36 | |||
37 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | GDB single-stepping is now handled generically. | ||
2 | 1 | ||
3 | Tested-by: Michael Rolnik <mrolnik@gmail.com> | ||
4 | Reviewed-by: Michael Rolnik <mrolnik@gmail.com> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | --- | ||
8 | target/avr/translate.c | 19 ++++--------------- | ||
9 | 1 file changed, 4 insertions(+), 15 deletions(-) | ||
10 | |||
11 | diff --git a/target/avr/translate.c b/target/avr/translate.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/avr/translate.c | ||
14 | +++ b/target/avr/translate.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) | ||
16 | tcg_gen_exit_tb(tb, n); | ||
17 | } else { | ||
18 | tcg_gen_movi_i32(cpu_pc, dest); | ||
19 | - if (ctx->base.singlestep_enabled) { | ||
20 | - gen_helper_debug(cpu_env); | ||
21 | - } else { | ||
22 | - tcg_gen_lookup_and_goto_ptr(); | ||
23 | - } | ||
24 | + tcg_gen_lookup_and_goto_ptr(); | ||
25 | } | ||
26 | ctx->base.is_jmp = DISAS_NORETURN; | ||
27 | } | ||
28 | @@ -XXX,XX +XXX,XX @@ static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | ||
29 | tcg_gen_movi_tl(cpu_pc, ctx->npc); | ||
30 | /* fall through */ | ||
31 | case DISAS_LOOKUP: | ||
32 | - if (!ctx->base.singlestep_enabled) { | ||
33 | - tcg_gen_lookup_and_goto_ptr(); | ||
34 | - break; | ||
35 | - } | ||
36 | - /* fall through */ | ||
37 | + tcg_gen_lookup_and_goto_ptr(); | ||
38 | + break; | ||
39 | case DISAS_EXIT: | ||
40 | - if (ctx->base.singlestep_enabled) { | ||
41 | - gen_helper_debug(cpu_env); | ||
42 | - } else { | ||
43 | - tcg_gen_exit_tb(NULL, 0); | ||
44 | - } | ||
45 | + tcg_gen_exit_tb(NULL, 0); | ||
46 | break; | ||
47 | default: | ||
48 | g_assert_not_reached(); | ||
49 | -- | ||
50 | 2.25.1 | ||
51 | |||
52 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | GDB single-stepping is now handled generically. | ||
2 | 1 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | --- | ||
5 | target/cris/translate.c | 16 ---------------- | ||
6 | 1 file changed, 16 deletions(-) | ||
7 | |||
8 | diff --git a/target/cris/translate.c b/target/cris/translate.c | ||
9 | index XXXXXXX..XXXXXXX 100644 | ||
10 | --- a/target/cris/translate.c | ||
11 | +++ b/target/cris/translate.c | ||
12 | @@ -XXX,XX +XXX,XX @@ static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
13 | } | ||
14 | } | ||
15 | |||
16 | - if (unlikely(dc->base.singlestep_enabled)) { | ||
17 | - switch (is_jmp) { | ||
18 | - case DISAS_TOO_MANY: | ||
19 | - case DISAS_UPDATE_NEXT: | ||
20 | - tcg_gen_movi_tl(env_pc, npc); | ||
21 | - /* fall through */ | ||
22 | - case DISAS_JUMP: | ||
23 | - case DISAS_UPDATE: | ||
24 | - t_gen_raise_exception(EXCP_DEBUG); | ||
25 | - return; | ||
26 | - default: | ||
27 | - break; | ||
28 | - } | ||
29 | - g_assert_not_reached(); | ||
30 | - } | ||
31 | - | ||
32 | switch (is_jmp) { | ||
33 | case DISAS_TOO_MANY: | ||
34 | gen_goto_tb(dc, 0, npc); | ||
35 | -- | ||
36 | 2.25.1 | ||
37 | |||
38 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | GDB single-stepping is now handled generically. | ||
2 | 1 | ||
3 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | target/hexagon/translate.c | 12 ++---------- | ||
7 | 1 file changed, 2 insertions(+), 10 deletions(-) | ||
8 | |||
9 | diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/target/hexagon/translate.c | ||
12 | +++ b/target/hexagon/translate.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static void gen_end_tb(DisasContext *ctx) | ||
14 | { | ||
15 | gen_exec_counters(ctx); | ||
16 | tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); | ||
17 | - if (ctx->base.singlestep_enabled) { | ||
18 | - gen_exception_raw(EXCP_DEBUG); | ||
19 | - } else { | ||
20 | - tcg_gen_exit_tb(NULL, 0); | ||
21 | - } | ||
22 | + tcg_gen_exit_tb(NULL, 0); | ||
23 | ctx->base.is_jmp = DISAS_NORETURN; | ||
24 | } | ||
25 | |||
26 | @@ -XXX,XX +XXX,XX @@ static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
27 | case DISAS_TOO_MANY: | ||
28 | gen_exec_counters(ctx); | ||
29 | tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); | ||
30 | - if (ctx->base.singlestep_enabled) { | ||
31 | - gen_exception_raw(EXCP_DEBUG); | ||
32 | - } else { | ||
33 | - tcg_gen_exit_tb(NULL, 0); | ||
34 | - } | ||
35 | + tcg_gen_exit_tb(NULL, 0); | ||
36 | break; | ||
37 | case DISAS_NORETURN: | ||
38 | break; | ||
39 | -- | ||
40 | 2.25.1 | ||
41 | |||
42 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | GDB single-stepping is now handled generically. | ||
2 | 1 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | --- | ||
5 | target/arm/translate-a64.c | 10 ++-------- | ||
6 | target/arm/translate.c | 36 ++++++------------------------------ | ||
7 | 2 files changed, 8 insertions(+), 38 deletions(-) | ||
8 | |||
9 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/target/arm/translate-a64.c | ||
12 | +++ b/target/arm/translate-a64.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) | ||
14 | gen_a64_set_pc_im(dest); | ||
15 | if (s->ss_active) { | ||
16 | gen_step_complete_exception(s); | ||
17 | - } else if (s->base.singlestep_enabled) { | ||
18 | - gen_exception_internal(EXCP_DEBUG); | ||
19 | } else { | ||
20 | tcg_gen_lookup_and_goto_ptr(); | ||
21 | s->base.is_jmp = DISAS_NORETURN; | ||
22 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
23 | { | ||
24 | DisasContext *dc = container_of(dcbase, DisasContext, base); | ||
25 | |||
26 | - if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) { | ||
27 | + if (unlikely(dc->ss_active)) { | ||
28 | /* Note that this means single stepping WFI doesn't halt the CPU. | ||
29 | * For conditional branch insns this is harmless unreachable code as | ||
30 | * gen_goto_tb() has already handled emitting the debug exception | ||
31 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
32 | /* fall through */ | ||
33 | case DISAS_EXIT: | ||
34 | case DISAS_JUMP: | ||
35 | - if (dc->base.singlestep_enabled) { | ||
36 | - gen_exception_internal(EXCP_DEBUG); | ||
37 | - } else { | ||
38 | - gen_step_complete_exception(dc); | ||
39 | - } | ||
40 | + gen_step_complete_exception(dc); | ||
41 | break; | ||
42 | case DISAS_NORETURN: | ||
43 | break; | ||
44 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/translate.c | ||
47 | +++ b/target/arm/translate.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp) | ||
49 | tcg_temp_free_i32(tcg_excp); | ||
50 | } | ||
51 | |||
52 | -static void gen_step_complete_exception(DisasContext *s) | ||
53 | +static void gen_singlestep_exception(DisasContext *s) | ||
54 | { | ||
55 | /* We just completed step of an insn. Move from Active-not-pending | ||
56 | * to Active-pending, and then also take the swstep exception. | ||
57 | @@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s) | ||
58 | s->base.is_jmp = DISAS_NORETURN; | ||
59 | } | ||
60 | |||
61 | -static void gen_singlestep_exception(DisasContext *s) | ||
62 | -{ | ||
63 | - /* Generate the right kind of exception for singlestep, which is | ||
64 | - * either the architectural singlestep or EXCP_DEBUG for QEMU's | ||
65 | - * gdb singlestepping. | ||
66 | - */ | ||
67 | - if (s->ss_active) { | ||
68 | - gen_step_complete_exception(s); | ||
69 | - } else { | ||
70 | - gen_exception_internal(EXCP_DEBUG); | ||
71 | - } | ||
72 | -} | ||
73 | - | ||
74 | -static inline bool is_singlestepping(DisasContext *s) | ||
75 | -{ | ||
76 | - /* Return true if we are singlestepping either because of | ||
77 | - * architectural singlestep or QEMU gdbstub singlestep. This does | ||
78 | - * not include the command line '-singlestep' mode which is rather | ||
79 | - * misnamed as it only means "one instruction per TB" and doesn't | ||
80 | - * affect the code we generate. | ||
81 | - */ | ||
82 | - return s->base.singlestep_enabled || s->ss_active; | ||
83 | -} | ||
84 | - | ||
85 | void clear_eci_state(DisasContext *s) | ||
86 | { | ||
87 | /* | ||
88 | @@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s) | ||
89 | /* Is the new PC value in the magic range indicating exception return? */ | ||
90 | tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label); | ||
91 | /* No: end the TB as we would for a DISAS_JMP */ | ||
92 | - if (is_singlestepping(s)) { | ||
93 | + if (s->ss_active) { | ||
94 | gen_singlestep_exception(s); | ||
95 | } else { | ||
96 | tcg_gen_exit_tb(NULL, 0); | ||
97 | @@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest) | ||
98 | /* Jump, specifying which TB number to use if we gen_goto_tb() */ | ||
99 | static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) | ||
100 | { | ||
101 | - if (unlikely(is_singlestepping(s))) { | ||
102 | + if (unlikely(s->ss_active)) { | ||
103 | /* An indirect jump so that we still trigger the debug exception. */ | ||
104 | gen_set_pc_im(s, dest); | ||
105 | s->base.is_jmp = DISAS_JUMP; | ||
106 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | ||
107 | dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK; | ||
108 | |||
109 | /* If architectural single step active, limit to 1. */ | ||
110 | - if (is_singlestepping(dc)) { | ||
111 | + if (dc->ss_active) { | ||
112 | dc->base.max_insns = 1; | ||
113 | } | ||
114 | |||
115 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
116 | * insn codepath itself. | ||
117 | */ | ||
118 | gen_bx_excret_final_code(dc); | ||
119 | - } else if (unlikely(is_singlestepping(dc))) { | ||
120 | + } else if (unlikely(dc->ss_active)) { | ||
121 | /* Unconditional and "condition passed" instruction codepath. */ | ||
122 | switch (dc->base.is_jmp) { | ||
123 | case DISAS_SWI: | ||
124 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
125 | /* "Condition failed" instruction codepath for the branch/trap insn */ | ||
126 | gen_set_label(dc->condlabel); | ||
127 | gen_set_condexec(dc); | ||
128 | - if (unlikely(is_singlestepping(dc))) { | ||
129 | + if (unlikely(dc->ss_active)) { | ||
130 | gen_set_pc_im(dc, dc->base.pc_next); | ||
131 | gen_singlestep_exception(dc); | ||
132 | } else { | ||
133 | -- | ||
134 | 2.25.1 | ||
135 | |||
136 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | GDB single-stepping is now handled generically. | ||
2 | 1 | ||
3 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | target/hppa/translate.c | 17 ++++------------- | ||
7 | 1 file changed, 4 insertions(+), 13 deletions(-) | ||
8 | |||
9 | diff --git a/target/hppa/translate.c b/target/hppa/translate.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/target/hppa/translate.c | ||
12 | +++ b/target/hppa/translate.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int which, | ||
14 | } else { | ||
15 | copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b); | ||
16 | copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var); | ||
17 | - if (ctx->base.singlestep_enabled) { | ||
18 | - gen_excp_1(EXCP_DEBUG); | ||
19 | - } else { | ||
20 | - tcg_gen_lookup_and_goto_ptr(); | ||
21 | - } | ||
22 | + tcg_gen_lookup_and_goto_ptr(); | ||
23 | } | ||
24 | } | ||
25 | |||
26 | @@ -XXX,XX +XXX,XX @@ static bool do_rfi(DisasContext *ctx, bool rfi_r) | ||
27 | gen_helper_rfi(cpu_env); | ||
28 | } | ||
29 | /* Exit the TB to recognize new interrupts. */ | ||
30 | - if (ctx->base.singlestep_enabled) { | ||
31 | - gen_excp_1(EXCP_DEBUG); | ||
32 | - } else { | ||
33 | - tcg_gen_exit_tb(NULL, 0); | ||
34 | - } | ||
35 | + tcg_gen_exit_tb(NULL, 0); | ||
36 | ctx->base.is_jmp = DISAS_NORETURN; | ||
37 | |||
38 | return nullify_end(ctx); | ||
39 | @@ -XXX,XX +XXX,XX @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | ||
40 | nullify_save(ctx); | ||
41 | /* FALLTHRU */ | ||
42 | case DISAS_IAQ_N_UPDATED: | ||
43 | - if (ctx->base.singlestep_enabled) { | ||
44 | - gen_excp_1(EXCP_DEBUG); | ||
45 | - } else if (is_jmp != DISAS_IAQ_N_STALE_EXIT) { | ||
46 | + if (is_jmp != DISAS_IAQ_N_STALE_EXIT) { | ||
47 | tcg_gen_lookup_and_goto_ptr(); | ||
48 | + break; | ||
49 | } | ||
50 | /* FALLTHRU */ | ||
51 | case DISAS_EXIT: | ||
52 | -- | ||
53 | 2.25.1 | ||
54 | |||
55 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | We were using singlestep_enabled as a proxy for whether | ||
2 | translator_use_goto_tb would always return false. | ||
3 | 1 | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | target/i386/tcg/translate.c | 5 +++-- | ||
7 | 1 file changed, 3 insertions(+), 2 deletions(-) | ||
8 | |||
9 | diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/target/i386/tcg/translate.c | ||
12 | +++ b/target/i386/tcg/translate.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) | ||
14 | DisasContext *dc = container_of(dcbase, DisasContext, base); | ||
15 | CPUX86State *env = cpu->env_ptr; | ||
16 | uint32_t flags = dc->base.tb->flags; | ||
17 | + uint32_t cflags = tb_cflags(dc->base.tb); | ||
18 | int cpl = (flags >> HF_CPL_SHIFT) & 3; | ||
19 | int iopl = (flags >> IOPL_SHIFT) & 3; | ||
20 | |||
21 | @@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) | ||
22 | dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX]; | ||
23 | dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX]; | ||
24 | dc->cpuid_xsave_features = env->features[FEAT_XSAVE]; | ||
25 | - dc->jmp_opt = !(dc->base.singlestep_enabled || | ||
26 | + dc->jmp_opt = !((cflags & CF_NO_GOTO_TB) || | ||
27 | (flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK))); | ||
28 | /* | ||
29 | * If jmp_opt, we want to handle each string instruction individually. | ||
30 | * For icount also disable repz optimization so that each iteration | ||
31 | * is accounted separately. | ||
32 | */ | ||
33 | - dc->repz_opt = !dc->jmp_opt && !(tb_cflags(dc->base.tb) & CF_USE_ICOUNT); | ||
34 | + dc->repz_opt = !dc->jmp_opt && !(cflags & CF_USE_ICOUNT); | ||
35 | |||
36 | dc->T0 = tcg_temp_new(); | ||
37 | dc->T1 = tcg_temp_new(); | ||
38 | -- | ||
39 | 2.25.1 | ||
40 | |||
41 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | GDB single-stepping is now handled generically. | ||
2 | 1 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | --- | ||
5 | target/i386/helper.h | 1 - | ||
6 | target/i386/tcg/misc_helper.c | 8 -------- | ||
7 | target/i386/tcg/translate.c | 4 +--- | ||
8 | 3 files changed, 1 insertion(+), 12 deletions(-) | ||
9 | |||
10 | diff --git a/target/i386/helper.h b/target/i386/helper.h | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/i386/helper.h | ||
13 | +++ b/target/i386/helper.h | ||
14 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(syscall, void, env, int) | ||
15 | DEF_HELPER_2(sysret, void, env, int) | ||
16 | #endif | ||
17 | DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int) | ||
18 | -DEF_HELPER_FLAGS_1(debug, TCG_CALL_NO_WG, noreturn, env) | ||
19 | DEF_HELPER_1(reset_rf, void, env) | ||
20 | DEF_HELPER_FLAGS_3(raise_interrupt, TCG_CALL_NO_WG, noreturn, env, int, int) | ||
21 | DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, int) | ||
22 | diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/target/i386/tcg/misc_helper.c | ||
25 | +++ b/target/i386/tcg/misc_helper.c | ||
26 | @@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend) | ||
27 | do_pause(env); | ||
28 | } | ||
29 | |||
30 | -void QEMU_NORETURN helper_debug(CPUX86State *env) | ||
31 | -{ | ||
32 | - CPUState *cs = env_cpu(env); | ||
33 | - | ||
34 | - cs->exception_index = EXCP_DEBUG; | ||
35 | - cpu_loop_exit(cs); | ||
36 | -} | ||
37 | - | ||
38 | uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx) | ||
39 | { | ||
40 | if ((env->cr[4] & CR4_PKE_MASK) == 0) { | ||
41 | diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/i386/tcg/translate.c | ||
44 | +++ b/target/i386/tcg/translate.c | ||
45 | @@ -XXX,XX +XXX,XX @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr) | ||
46 | if (s->base.tb->flags & HF_RF_MASK) { | ||
47 | gen_helper_reset_rf(cpu_env); | ||
48 | } | ||
49 | - if (s->base.singlestep_enabled) { | ||
50 | - gen_helper_debug(cpu_env); | ||
51 | - } else if (recheck_tf) { | ||
52 | + if (recheck_tf) { | ||
53 | gen_helper_rechecking_single_step(cpu_env); | ||
54 | tcg_gen_exit_tb(NULL, 0); | ||
55 | } else if (s->flags & HF_TF_MASK) { | ||
56 | -- | ||
57 | 2.25.1 | ||
58 | |||
59 | diff view generated by jsdifflib |
1 | GDB single-stepping is now handled generically. | 1 | From: Dickon Hood <dickon.hood@codethink.co.uk> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 3 | Rotates have been fixed up to only allow for reasonable rotate amounts |
4 | (ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv | ||
5 | vector rotate instructions. | ||
6 | |||
7 | Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-Id: <20230428144757.57530-9-lawrence.hunter@codethink.co.uk> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | --- | 11 | --- |
6 | target/tricore/helper.h | 1 - | 12 | include/qemu/bitops.h | 24 ++++++++++++++++-------- |
7 | target/tricore/op_helper.c | 7 ------- | 13 | 1 file changed, 16 insertions(+), 8 deletions(-) |
8 | target/tricore/translate.c | 14 +------------- | ||
9 | 3 files changed, 1 insertion(+), 21 deletions(-) | ||
10 | 14 | ||
11 | diff --git a/target/tricore/helper.h b/target/tricore/helper.h | 15 | diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h |
12 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/tricore/helper.h | 17 | --- a/include/qemu/bitops.h |
14 | +++ b/target/tricore/helper.h | 18 | +++ b/include/qemu/bitops.h |
15 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(psw_write, void, env, i32) | 19 | @@ -XXX,XX +XXX,XX @@ static inline unsigned long find_first_zero_bit(const unsigned long *addr, |
16 | DEF_HELPER_1(psw_read, i32, env) | 20 | */ |
17 | /* Exceptions */ | 21 | static inline uint8_t rol8(uint8_t word, unsigned int shift) |
18 | DEF_HELPER_3(raise_exception_sync, noreturn, env, i32, i32) | 22 | { |
19 | -DEF_HELPER_2(qemu_excp, noreturn, env, i32) | 23 | - return (word << shift) | (word >> ((8 - shift) & 7)); |
20 | diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c | 24 | + shift &= 7; |
21 | index XXXXXXX..XXXXXXX 100644 | 25 | + return (word << shift) | (word >> (8 - shift)); |
22 | --- a/target/tricore/op_helper.c | ||
23 | +++ b/target/tricore/op_helper.c | ||
24 | @@ -XXX,XX +XXX,XX @@ static void raise_exception_sync_helper(CPUTriCoreState *env, uint32_t class, | ||
25 | raise_exception_sync_internal(env, class, tin, pc, 0); | ||
26 | } | 26 | } |
27 | 27 | ||
28 | -void helper_qemu_excp(CPUTriCoreState *env, uint32_t excp) | 28 | /** |
29 | -{ | 29 | @@ -XXX,XX +XXX,XX @@ static inline uint8_t rol8(uint8_t word, unsigned int shift) |
30 | - CPUState *cs = env_cpu(env); | 30 | */ |
31 | - cs->exception_index = excp; | 31 | static inline uint8_t ror8(uint8_t word, unsigned int shift) |
32 | - cpu_loop_exit(cs); | 32 | { |
33 | -} | 33 | - return (word >> shift) | (word << ((8 - shift) & 7)); |
34 | - | 34 | + shift &= 7; |
35 | /* Addressing mode helper */ | 35 | + return (word >> shift) | (word << (8 - shift)); |
36 | |||
37 | static uint16_t reverse16(uint16_t val) | ||
38 | diff --git a/target/tricore/translate.c b/target/tricore/translate.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/tricore/translate.c | ||
41 | +++ b/target/tricore/translate.c | ||
42 | @@ -XXX,XX +XXX,XX @@ static inline void gen_save_pc(target_ulong pc) | ||
43 | tcg_gen_movi_tl(cpu_PC, pc); | ||
44 | } | 36 | } |
45 | 37 | ||
46 | -static void generate_qemu_excp(DisasContext *ctx, int excp) | 38 | /** |
47 | -{ | 39 | @@ -XXX,XX +XXX,XX @@ static inline uint8_t ror8(uint8_t word, unsigned int shift) |
48 | - TCGv_i32 tmp = tcg_const_i32(excp); | 40 | */ |
49 | - gen_helper_qemu_excp(cpu_env, tmp); | 41 | static inline uint16_t rol16(uint16_t word, unsigned int shift) |
50 | - ctx->base.is_jmp = DISAS_NORETURN; | ||
51 | - tcg_temp_free(tmp); | ||
52 | -} | ||
53 | - | ||
54 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) | ||
55 | { | 42 | { |
56 | if (translator_use_goto_tb(&ctx->base, dest)) { | 43 | - return (word << shift) | (word >> ((16 - shift) & 15)); |
57 | @@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) | 44 | + shift &= 15; |
58 | tcg_gen_exit_tb(ctx->base.tb, n); | 45 | + return (word << shift) | (word >> (16 - shift)); |
59 | } else { | ||
60 | gen_save_pc(dest); | ||
61 | - if (ctx->base.singlestep_enabled) { | ||
62 | - generate_qemu_excp(ctx, EXCP_DEBUG); | ||
63 | - } else { | ||
64 | - tcg_gen_lookup_and_goto_ptr(); | ||
65 | - } | ||
66 | + tcg_gen_lookup_and_goto_ptr(); | ||
67 | } | ||
68 | } | 46 | } |
69 | 47 | ||
48 | /** | ||
49 | @@ -XXX,XX +XXX,XX @@ static inline uint16_t rol16(uint16_t word, unsigned int shift) | ||
50 | */ | ||
51 | static inline uint16_t ror16(uint16_t word, unsigned int shift) | ||
52 | { | ||
53 | - return (word >> shift) | (word << ((16 - shift) & 15)); | ||
54 | + shift &= 15; | ||
55 | + return (word >> shift) | (word << (16 - shift)); | ||
56 | } | ||
57 | |||
58 | /** | ||
59 | @@ -XXX,XX +XXX,XX @@ static inline uint16_t ror16(uint16_t word, unsigned int shift) | ||
60 | */ | ||
61 | static inline uint32_t rol32(uint32_t word, unsigned int shift) | ||
62 | { | ||
63 | - return (word << shift) | (word >> ((32 - shift) & 31)); | ||
64 | + shift &= 31; | ||
65 | + return (word << shift) | (word >> (32 - shift)); | ||
66 | } | ||
67 | |||
68 | /** | ||
69 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t rol32(uint32_t word, unsigned int shift) | ||
70 | */ | ||
71 | static inline uint32_t ror32(uint32_t word, unsigned int shift) | ||
72 | { | ||
73 | - return (word >> shift) | (word << ((32 - shift) & 31)); | ||
74 | + shift &= 31; | ||
75 | + return (word >> shift) | (word << (32 - shift)); | ||
76 | } | ||
77 | |||
78 | /** | ||
79 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t ror32(uint32_t word, unsigned int shift) | ||
80 | */ | ||
81 | static inline uint64_t rol64(uint64_t word, unsigned int shift) | ||
82 | { | ||
83 | - return (word << shift) | (word >> ((64 - shift) & 63)); | ||
84 | + shift &= 63; | ||
85 | + return (word << shift) | (word >> (64 - shift)); | ||
86 | } | ||
87 | |||
88 | /** | ||
89 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t rol64(uint64_t word, unsigned int shift) | ||
90 | */ | ||
91 | static inline uint64_t ror64(uint64_t word, unsigned int shift) | ||
92 | { | ||
93 | - return (word >> shift) | (word << ((64 - shift) & 63)); | ||
94 | + shift &= 63; | ||
95 | + return (word >> shift) | (word << (64 - shift)); | ||
96 | } | ||
97 | |||
98 | /** | ||
70 | -- | 99 | -- |
71 | 2.25.1 | 100 | 2.34.1 |
72 | |||
73 | diff view generated by jsdifflib |
1 | We have already set DISAS_NORETURN in generate_exception, | 1 | From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> |
---|---|---|---|
2 | which makes the exit_tb unreachable. | ||
3 | 2 | ||
4 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 3 | This is for use in the RISC-V vclz and vctz instructions (implemented in |
4 | proceeding commit). | ||
5 | |||
6 | Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-Id: <20230428144757.57530-11-lawrence.hunter@codethink.co.uk> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | --- | 10 | --- |
7 | target/riscv/insn_trans/trans_privileged.c.inc | 6 +----- | 11 | include/qemu/host-utils.h | 54 +++++++++++++++++++++++++++++++++++++++ |
8 | 1 file changed, 1 insertion(+), 5 deletions(-) | 12 | 1 file changed, 54 insertions(+) |
9 | 13 | ||
10 | diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc | 14 | diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h |
11 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/target/riscv/insn_trans/trans_privileged.c.inc | 16 | --- a/include/qemu/host-utils.h |
13 | +++ b/target/riscv/insn_trans/trans_privileged.c.inc | 17 | +++ b/include/qemu/host-utils.h |
14 | @@ -XXX,XX +XXX,XX @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a) | 18 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) |
15 | { | ||
16 | /* always generates U-level ECALL, fixed in do_interrupt handler */ | ||
17 | generate_exception(ctx, RISCV_EXCP_U_ECALL); | ||
18 | - exit_tb(ctx); /* no chaining */ | ||
19 | - ctx->base.is_jmp = DISAS_NORETURN; | ||
20 | return true; | ||
21 | } | 19 | } |
22 | 20 | #endif | |
23 | @@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) | 21 | |
24 | post = opcode_at(&ctx->base, post_addr); | 22 | +/** |
25 | } | 23 | + * clz8 - count leading zeros in a 8-bit value. |
26 | 24 | + * @val: The value to search | |
27 | - if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) { | 25 | + * |
28 | + if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) { | 26 | + * Returns 8 if the value is zero. Note that the GCC builtin is |
29 | generate_exception(ctx, RISCV_EXCP_SEMIHOST); | 27 | + * undefined if the value is zero. |
30 | } else { | 28 | + * |
31 | generate_exception(ctx, RISCV_EXCP_BREAKPOINT); | 29 | + * Note that the GCC builtin will upcast its argument to an `unsigned int` |
32 | } | 30 | + * so this function subtracts off the number of prepended zeroes. |
33 | - exit_tb(ctx); /* no chaining */ | 31 | + */ |
34 | - ctx->base.is_jmp = DISAS_NORETURN; | 32 | +static inline int clz8(uint8_t val) |
35 | return true; | 33 | +{ |
34 | + return val ? __builtin_clz(val) - 24 : 8; | ||
35 | +} | ||
36 | + | ||
37 | +/** | ||
38 | + * clz16 - count leading zeros in a 16-bit value. | ||
39 | + * @val: The value to search | ||
40 | + * | ||
41 | + * Returns 16 if the value is zero. Note that the GCC builtin is | ||
42 | + * undefined if the value is zero. | ||
43 | + * | ||
44 | + * Note that the GCC builtin will upcast its argument to an `unsigned int` | ||
45 | + * so this function subtracts off the number of prepended zeroes. | ||
46 | + */ | ||
47 | +static inline int clz16(uint16_t val) | ||
48 | +{ | ||
49 | + return val ? __builtin_clz(val) - 16 : 16; | ||
50 | +} | ||
51 | + | ||
52 | /** | ||
53 | * clz32 - count leading zeros in a 32-bit value. | ||
54 | * @val: The value to search | ||
55 | @@ -XXX,XX +XXX,XX @@ static inline int clo64(uint64_t val) | ||
56 | return clz64(~val); | ||
36 | } | 57 | } |
37 | 58 | ||
59 | +/** | ||
60 | + * ctz8 - count trailing zeros in a 8-bit value. | ||
61 | + * @val: The value to search | ||
62 | + * | ||
63 | + * Returns 8 if the value is zero. Note that the GCC builtin is | ||
64 | + * undefined if the value is zero. | ||
65 | + */ | ||
66 | +static inline int ctz8(uint8_t val) | ||
67 | +{ | ||
68 | + return val ? __builtin_ctz(val) : 8; | ||
69 | +} | ||
70 | + | ||
71 | +/** | ||
72 | + * ctz16 - count trailing zeros in a 16-bit value. | ||
73 | + * @val: The value to search | ||
74 | + * | ||
75 | + * Returns 16 if the value is zero. Note that the GCC builtin is | ||
76 | + * undefined if the value is zero. | ||
77 | + */ | ||
78 | +static inline int ctz16(uint16_t val) | ||
79 | +{ | ||
80 | + return val ? __builtin_ctz(val) : 16; | ||
81 | +} | ||
82 | + | ||
83 | /** | ||
84 | * ctz32 - count trailing zeros in a 32-bit value. | ||
85 | * @val: The value to search | ||
38 | -- | 86 | -- |
39 | 2.25.1 | 87 | 2.34.1 |
40 | |||
41 | diff view generated by jsdifflib |
1 | GDB single-stepping is now handled generically. | 1 | From: Nazar Kazakov <nazar.kazakov@codethink.co.uk> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 3 | Add tcg expander and helper functions for and-compliment |
4 | vector with scalar operand. | ||
5 | |||
6 | Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | ||
7 | Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk> | ||
8 | [rth: Split out of larger patch.] | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | --- | 10 | --- |
6 | target/mips/tcg/translate.c | 50 +++++++++++++------------------------ | 11 | accel/tcg/tcg-runtime.h | 1 + |
7 | 1 file changed, 18 insertions(+), 32 deletions(-) | 12 | include/tcg/tcg-op-gvec.h | 2 ++ |
13 | accel/tcg/tcg-runtime-gvec.c | 11 +++++++++++ | ||
14 | tcg/tcg-op-gvec.c | 17 +++++++++++++++++ | ||
15 | 4 files changed, 31 insertions(+) | ||
8 | 16 | ||
9 | diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c | 17 | diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h |
10 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
11 | --- a/target/mips/tcg/translate.c | 19 | --- a/accel/tcg/tcg-runtime.h |
12 | +++ b/target/mips/tcg/translate.c | 20 | +++ b/accel/tcg/tcg-runtime.h |
13 | @@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) | 21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_nor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
14 | tcg_gen_exit_tb(ctx->base.tb, n); | 22 | DEF_HELPER_FLAGS_4(gvec_eqv, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
15 | } else { | 23 | |
16 | gen_save_pc(dest); | 24 | DEF_HELPER_FLAGS_4(gvec_ands, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) |
17 | - if (ctx->base.singlestep_enabled) { | 25 | +DEF_HELPER_FLAGS_4(gvec_andcs, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) |
18 | - save_cpu_state(ctx, 0); | 26 | DEF_HELPER_FLAGS_4(gvec_xors, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) |
19 | - gen_helper_raise_exception_debug(cpu_env); | 27 | DEF_HELPER_FLAGS_4(gvec_ors, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) |
20 | - } else { | 28 | |
21 | - tcg_gen_lookup_and_goto_ptr(); | 29 | diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h |
22 | - } | 30 | index XXXXXXX..XXXXXXX 100644 |
23 | + tcg_gen_lookup_and_goto_ptr(); | 31 | --- a/include/tcg/tcg-op-gvec.h |
24 | } | 32 | +++ b/include/tcg/tcg-op-gvec.h |
33 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
34 | |||
35 | void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
36 | TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); | ||
37 | +void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
38 | + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); | ||
39 | void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
40 | TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); | ||
41 | void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
42 | diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/accel/tcg/tcg-runtime-gvec.c | ||
45 | +++ b/accel/tcg/tcg-runtime-gvec.c | ||
46 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc) | ||
47 | clear_high(d, oprsz, desc); | ||
25 | } | 48 | } |
26 | 49 | ||
27 | @@ -XXX,XX +XXX,XX @@ static void gen_branch(DisasContext *ctx, int insn_bytes) | 50 | +void HELPER(gvec_andcs)(void *d, void *a, uint64_t b, uint32_t desc) |
28 | } else { | 51 | +{ |
29 | tcg_gen_mov_tl(cpu_PC, btarget); | 52 | + intptr_t oprsz = simd_oprsz(desc); |
30 | } | 53 | + intptr_t i; |
31 | - if (ctx->base.singlestep_enabled) { | 54 | + |
32 | - save_cpu_state(ctx, 0); | 55 | + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { |
33 | - gen_helper_raise_exception_debug(cpu_env); | 56 | + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) & ~b; |
34 | - } | 57 | + } |
35 | tcg_gen_lookup_and_goto_ptr(); | 58 | + clear_high(d, oprsz, desc); |
36 | break; | 59 | +} |
37 | default: | 60 | + |
38 | @@ -XXX,XX +XXX,XX @@ static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | 61 | void HELPER(gvec_xors)(void *d, void *a, uint64_t b, uint32_t desc) |
39 | { | 62 | { |
40 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | 63 | intptr_t oprsz = simd_oprsz(desc); |
41 | 64 | diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c | |
42 | - if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) { | 65 | index XXXXXXX..XXXXXXX 100644 |
43 | - save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXIT); | 66 | --- a/tcg/tcg-op-gvec.c |
44 | - gen_helper_raise_exception_debug(cpu_env); | 67 | +++ b/tcg/tcg-op-gvec.c |
45 | - } else { | 68 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs, |
46 | - switch (ctx->base.is_jmp) { | 69 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands); |
47 | - case DISAS_STOP: | ||
48 | - gen_save_pc(ctx->base.pc_next); | ||
49 | - tcg_gen_lookup_and_goto_ptr(); | ||
50 | - break; | ||
51 | - case DISAS_NEXT: | ||
52 | - case DISAS_TOO_MANY: | ||
53 | - save_cpu_state(ctx, 0); | ||
54 | - gen_goto_tb(ctx, 0, ctx->base.pc_next); | ||
55 | - break; | ||
56 | - case DISAS_EXIT: | ||
57 | - tcg_gen_exit_tb(NULL, 0); | ||
58 | - break; | ||
59 | - case DISAS_NORETURN: | ||
60 | - break; | ||
61 | - default: | ||
62 | - g_assert_not_reached(); | ||
63 | - } | ||
64 | + switch (ctx->base.is_jmp) { | ||
65 | + case DISAS_STOP: | ||
66 | + gen_save_pc(ctx->base.pc_next); | ||
67 | + tcg_gen_lookup_and_goto_ptr(); | ||
68 | + break; | ||
69 | + case DISAS_NEXT: | ||
70 | + case DISAS_TOO_MANY: | ||
71 | + save_cpu_state(ctx, 0); | ||
72 | + gen_goto_tb(ctx, 0, ctx->base.pc_next); | ||
73 | + break; | ||
74 | + case DISAS_EXIT: | ||
75 | + tcg_gen_exit_tb(NULL, 0); | ||
76 | + break; | ||
77 | + case DISAS_NORETURN: | ||
78 | + break; | ||
79 | + default: | ||
80 | + g_assert_not_reached(); | ||
81 | } | ||
82 | } | 70 | } |
83 | 71 | ||
72 | +void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
73 | + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) | ||
74 | +{ | ||
75 | + static GVecGen2s g = { | ||
76 | + .fni8 = tcg_gen_andc_i64, | ||
77 | + .fniv = tcg_gen_andc_vec, | ||
78 | + .fno = gen_helper_gvec_andcs, | ||
79 | + .prefer_i64 = TCG_TARGET_REG_BITS == 64, | ||
80 | + .vece = MO_64 | ||
81 | + }; | ||
82 | + | ||
83 | + TCGv_i64 tmp = tcg_temp_ebb_new_i64(); | ||
84 | + tcg_gen_dup_i64(vece, tmp, c); | ||
85 | + tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g); | ||
86 | + tcg_temp_free_i64(tmp); | ||
87 | +} | ||
88 | + | ||
89 | static const GVecGen2s gop_xors = { | ||
90 | .fni8 = tcg_gen_xor_i64, | ||
91 | .fniv = tcg_gen_xor_vec, | ||
84 | -- | 92 | -- |
85 | 2.25.1 | 93 | 2.34.1 |
86 | |||
87 | diff view generated by jsdifflib |
1 | This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f. | 1 | From: Nazar Kazakov <nazar.kazakov@codethink.co.uk> |
---|---|---|---|
2 | 2 | ||
3 | Despite a comment saying why cpu_common_props cannot be placed in | 3 | Add tcg expander and helper functions for rotate right |
4 | a file that is compiled once, it was moved anyway. Revert that. | 4 | vector with scalar operand. |
5 | 5 | ||
6 | Since then, Property is not defined in hw/core/cpu.h, so it is now | 6 | Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> |
7 | easier to declare a function to install the properties rather than | 7 | Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk> |
8 | the Property array itself. | 8 | [rth: Split out of larger patch; mask rotation count.] |
9 | |||
10 | Cc: Eduardo Habkost <ehabkost@redhat.com> | ||
11 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
13 | --- | 10 | --- |
14 | include/hw/core/cpu.h | 1 + | 11 | include/tcg/tcg-op-gvec.h | 2 ++ |
15 | cpu.c | 21 +++++++++++++++++++++ | 12 | tcg/tcg-op-gvec.c | 11 +++++++++++ |
16 | hw/core/cpu-common.c | 17 +---------------- | 13 | 2 files changed, 13 insertions(+) |
17 | 3 files changed, 23 insertions(+), 16 deletions(-) | ||
18 | 14 | ||
19 | diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h | 15 | diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h |
20 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/include/hw/core/cpu.h | 17 | --- a/include/tcg/tcg-op-gvec.h |
22 | +++ b/include/hw/core/cpu.h | 18 | +++ b/include/tcg/tcg-op-gvec.h |
23 | @@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) | 19 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, |
24 | GCC_FMT_ATTR(2, 3); | 20 | TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); |
25 | 21 | void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, | |
26 | /* $(top_srcdir)/cpu.c */ | 22 | TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); |
27 | +void cpu_class_init_props(DeviceClass *dc); | 23 | +void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs, |
28 | void cpu_exec_initfn(CPUState *cpu); | 24 | + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); |
29 | void cpu_exec_realizefn(CPUState *cpu, Error **errp); | 25 | |
30 | void cpu_exec_unrealizefn(CPUState *cpu); | 26 | /* |
31 | diff --git a/cpu.c b/cpu.c | 27 | * Perform vector shift by vector element, modulo the element size. |
28 | diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/cpu.c | 30 | --- a/tcg/tcg-op-gvec.c |
34 | +++ b/cpu.c | 31 | +++ b/tcg/tcg-op-gvec.c |
35 | @@ -XXX,XX +XXX,XX @@ void cpu_exec_unrealizefn(CPUState *cpu) | 32 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, |
36 | cpu_list_remove(cpu); | 33 | do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); |
37 | } | 34 | } |
38 | 35 | ||
39 | +static Property cpu_common_props[] = { | 36 | +void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs, |
40 | +#ifndef CONFIG_USER_ONLY | 37 | + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) |
41 | + /* | 38 | +{ |
42 | + * Create a memory property for softmmu CPU object, | 39 | + TCGv_i32 tmp = tcg_temp_ebb_new_i32(); |
43 | + * so users can wire up its memory. (This can't go in hw/core/cpu.c | ||
44 | + * because that file is compiled only once for both user-mode | ||
45 | + * and system builds.) The default if no link is set up is to use | ||
46 | + * the system address space. | ||
47 | + */ | ||
48 | + DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, | ||
49 | + MemoryRegion *), | ||
50 | +#endif | ||
51 | + DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false), | ||
52 | + DEFINE_PROP_END_OF_LIST(), | ||
53 | +}; | ||
54 | + | 40 | + |
55 | +void cpu_class_init_props(DeviceClass *dc) | 41 | + tcg_gen_neg_i32(tmp, shift); |
56 | +{ | 42 | + tcg_gen_andi_i32(tmp, tmp, (8 << vece) - 1); |
57 | + device_class_set_props(dc, cpu_common_props); | 43 | + tcg_gen_gvec_rotls(vece, dofs, aofs, tmp, oprsz, maxsz); |
44 | + tcg_temp_free_i32(tmp); | ||
58 | +} | 45 | +} |
59 | + | 46 | + |
60 | void cpu_exec_initfn(CPUState *cpu) | 47 | /* |
61 | { | 48 | * Expand D = A << (B % element bits) |
62 | cpu->as = NULL; | 49 | * |
63 | diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/hw/core/cpu-common.c | ||
66 | +++ b/hw/core/cpu-common.c | ||
67 | @@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu) | ||
68 | return cpu->cpu_index; | ||
69 | } | ||
70 | |||
71 | -static Property cpu_common_props[] = { | ||
72 | -#ifndef CONFIG_USER_ONLY | ||
73 | - /* Create a memory property for softmmu CPU object, | ||
74 | - * so users can wire up its memory. (This can't go in hw/core/cpu.c | ||
75 | - * because that file is compiled only once for both user-mode | ||
76 | - * and system builds.) The default if no link is set up is to use | ||
77 | - * the system address space. | ||
78 | - */ | ||
79 | - DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, | ||
80 | - MemoryRegion *), | ||
81 | -#endif | ||
82 | - DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false), | ||
83 | - DEFINE_PROP_END_OF_LIST(), | ||
84 | -}; | ||
85 | - | ||
86 | static void cpu_class_init(ObjectClass *klass, void *data) | ||
87 | { | ||
88 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
89 | @@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data) | ||
90 | dc->realize = cpu_common_realizefn; | ||
91 | dc->unrealize = cpu_common_unrealizefn; | ||
92 | dc->reset = cpu_common_reset; | ||
93 | - device_class_set_props(dc, cpu_common_props); | ||
94 | + cpu_class_init_props(dc); | ||
95 | /* | ||
96 | * Reason: CPUs still need special care by board code: wiring up | ||
97 | * IRQs, adding reset handlers, halting non-first CPUs, ... | ||
98 | -- | 50 | -- |
99 | 2.25.1 | 51 | 2.34.1 |
100 | |||
101 | diff view generated by jsdifflib |
1 | We were using singlestep_enabled as a proxy for whether | 1 | Clang 14, with --enable-tcg-interpreter errors with |
---|---|---|---|
2 | translator_use_goto_tb would always return false. | 2 | |
3 | include/qemu/int128.h:487:16: error: alignment of field 'i' (128 bits) | ||
4 | does not match the alignment of the first field in transparent union; | ||
5 | transparent_union attribute ignored [-Werror,-Wignored-attributes] | ||
6 | __int128_t i; | ||
7 | ^ | ||
8 | include/qemu/int128.h:486:12: note: alignment of first field is 64 bits | ||
9 | Int128 s; | ||
10 | ^ | ||
11 | 1 error generated. | ||
12 | |||
13 | By placing the __uint128_t member first, this is avoided. | ||
3 | 14 | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 15 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
16 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
17 | Message-Id: <20230501204625.277361-1-richard.henderson@linaro.org> | ||
5 | --- | 18 | --- |
6 | target/microblaze/translate.c | 4 ++-- | 19 | include/qemu/int128.h | 4 ++-- |
7 | 1 file changed, 2 insertions(+), 2 deletions(-) | 20 | 1 file changed, 2 insertions(+), 2 deletions(-) |
8 | 21 | ||
9 | diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c | 22 | diff --git a/include/qemu/int128.h b/include/qemu/int128.h |
10 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
11 | --- a/target/microblaze/translate.c | 24 | --- a/include/qemu/int128.h |
12 | +++ b/target/microblaze/translate.c | 25 | +++ b/include/qemu/int128.h |
13 | @@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) | 26 | @@ -XXX,XX +XXX,XX @@ static inline void bswap128s(Int128 *s) |
14 | break; | 27 | */ |
15 | 28 | #ifdef CONFIG_INT128 | |
16 | case DISAS_JUMP: | 29 | typedef union { |
17 | - if (dc->jmp_dest != -1 && !cs->singlestep_enabled) { | 30 | - Int128 s; |
18 | + if (dc->jmp_dest != -1 && !(tb_cflags(dc->base.tb) & CF_NO_GOTO_TB)) { | 31 | - __int128_t i; |
19 | /* Direct jump. */ | 32 | __uint128_t u; |
20 | tcg_gen_discard_i32(cpu_btarget); | 33 | + __int128_t i; |
21 | 34 | + Int128 s; | |
22 | @@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) | 35 | } Int128Alias __attribute__((transparent_union)); |
23 | return; | 36 | #else |
24 | } | 37 | typedef Int128 Int128Alias; |
25 | |||
26 | - /* Indirect jump (or direct jump w/ singlestep) */ | ||
27 | + /* Indirect jump (or direct jump w/ goto_tb disabled) */ | ||
28 | tcg_gen_mov_i32(cpu_pc, cpu_btarget); | ||
29 | tcg_gen_discard_i32(cpu_btarget); | ||
30 | |||
31 | -- | 38 | -- |
32 | 2.25.1 | 39 | 2.34.1 |
33 | 40 | ||
34 | 41 | diff view generated by jsdifflib |
1 | GDB single-stepping is now handled generically. | 1 | Use the attribute, which is supported by clang, instead of |
---|---|---|---|
2 | the #pragma, which is not supported and, for some reason, | ||
3 | also not detected by the meson probe, so we fail by -Werror. | ||
2 | 4 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Juan Quintela <quintela@redhat.com> | ||
7 | Message-Id: <20230501210555.289806-1-richard.henderson@linaro.org> | ||
4 | --- | 8 | --- |
5 | target/s390x/tcg/translate.c | 8 ++------ | 9 | meson.build | 5 +---- |
6 | 1 file changed, 2 insertions(+), 6 deletions(-) | 10 | migration/xbzrle.c | 9 ++++----- |
11 | 2 files changed, 5 insertions(+), 9 deletions(-) | ||
7 | 12 | ||
8 | diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c | 13 | diff --git a/meson.build b/meson.build |
9 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
10 | --- a/target/s390x/tcg/translate.c | 15 | --- a/meson.build |
11 | +++ b/target/s390x/tcg/translate.c | 16 | +++ b/meson.build |
12 | @@ -XXX,XX +XXX,XX @@ struct DisasContext { | 17 | @@ -XXX,XX +XXX,XX @@ config_host_data.set('CONFIG_AVX512F_OPT', get_option('avx512f') \ |
13 | uint64_t pc_tmp; | 18 | config_host_data.set('CONFIG_AVX512BW_OPT', get_option('avx512bw') \ |
14 | uint32_t ilen; | 19 | .require(have_cpuid_h, error_message: 'cpuid.h not available, cannot enable AVX512BW') \ |
15 | enum cc_op cc_op; | 20 | .require(cc.links(''' |
16 | - bool do_debug; | 21 | - #pragma GCC push_options |
17 | }; | 22 | - #pragma GCC target("avx512bw") |
18 | 23 | #include <cpuid.h> | |
19 | /* Information carried about a condition to be evaluated. */ | 24 | #include <immintrin.h> |
20 | @@ -XXX,XX +XXX,XX @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | 25 | - static int bar(void *a) { |
21 | 26 | - | |
22 | dc->cc_op = CC_OP_DYNAMIC; | 27 | + static int __attribute__((target("avx512bw"))) bar(void *a) { |
23 | dc->ex_value = dc->base.tb->cs_base; | 28 | __m512i *x = a; |
24 | - dc->do_debug = dc->base.singlestep_enabled; | 29 | __m512i res= _mm512_abs_epi8(*x); |
30 | return res[1]; | ||
31 | diff --git a/migration/xbzrle.c b/migration/xbzrle.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/migration/xbzrle.c | ||
34 | +++ b/migration/xbzrle.c | ||
35 | @@ -XXX,XX +XXX,XX @@ int xbzrle_decode_buffer(uint8_t *src, int slen, uint8_t *dst, int dlen) | ||
25 | } | 36 | } |
26 | 37 | ||
27 | static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs) | 38 | #if defined(CONFIG_AVX512BW_OPT) |
28 | @@ -XXX,XX +XXX,XX @@ static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | 39 | -#pragma GCC push_options |
29 | /* FALLTHRU */ | 40 | -#pragma GCC target("avx512bw") |
30 | case DISAS_PC_CC_UPDATED: | 41 | #include <immintrin.h> |
31 | /* Exit the TB, either by raising a debug exception or by return. */ | 42 | -int xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int slen, |
32 | - if (dc->do_debug) { | 43 | - uint8_t *dst, int dlen) |
33 | - gen_exception(EXCP_DEBUG); | 44 | + |
34 | - } else if ((dc->base.tb->flags & FLAG_MASK_PER) || | 45 | +int __attribute__((target("avx512bw"))) |
35 | - dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) { | 46 | +xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int slen, |
36 | + if ((dc->base.tb->flags & FLAG_MASK_PER) || | 47 | + uint8_t *dst, int dlen) |
37 | + dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) { | 48 | { |
38 | tcg_gen_exit_tb(NULL, 0); | 49 | uint32_t zrun_len = 0, nzrun_len = 0; |
39 | } else { | 50 | int d = 0, i = 0, num = 0; |
40 | tcg_gen_lookup_and_goto_ptr(); | 51 | @@ -XXX,XX +XXX,XX @@ int xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int slen, |
52 | } | ||
53 | return d; | ||
54 | } | ||
55 | -#pragma GCC pop_options | ||
56 | #endif | ||
41 | -- | 57 | -- |
42 | 2.25.1 | 58 | 2.34.1 |
43 | |||
44 | diff view generated by jsdifflib |
1 | GDB single-stepping is now handled generically. | 1 | At least RISC-V has the need to be able to perform a read |
---|---|---|---|
2 | Reuse gen_debug_exception to handle architectural debug exceptions. | 2 | using execute permissions, outside of translation. |
3 | Add helpers to facilitate this. | ||
3 | 4 | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
7 | Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
8 | Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
9 | Message-Id: <20230325105429.1142530-9-richard.henderson@linaro.org> | ||
10 | Message-Id: <20230412114333.118895-9-richard.henderson@linaro.org> | ||
5 | --- | 11 | --- |
6 | target/ppc/translate.c | 38 ++++++++------------------------------ | 12 | include/exec/cpu_ldst.h | 9 +++++++ |
7 | 1 file changed, 8 insertions(+), 30 deletions(-) | 13 | accel/tcg/cputlb.c | 48 ++++++++++++++++++++++++++++++++++ |
14 | accel/tcg/user-exec.c | 58 +++++++++++++++++++++++++++++++++++++++++ | ||
15 | 3 files changed, 115 insertions(+) | ||
8 | 16 | ||
9 | diff --git a/target/ppc/translate.c b/target/ppc/translate.c | 17 | diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h |
10 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
11 | --- a/target/ppc/translate.c | 19 | --- a/include/exec/cpu_ldst.h |
12 | +++ b/target/ppc/translate.c | 20 | +++ b/include/exec/cpu_ldst.h |
13 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, |
14 | 22 | # define cpu_stq_mmu cpu_stq_le_mmu | |
15 | #define CPU_SINGLE_STEP 0x1 | 23 | #endif |
16 | #define CPU_BRANCH_STEP 0x2 | 24 | |
17 | -#define GDBSTUB_SINGLE_STEP 0x4 | 25 | +uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, |
18 | 26 | + MemOpIdx oi, uintptr_t ra); | |
19 | /* Include definitions for instructions classes and implementations flags */ | 27 | +uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, |
20 | /* #define PPC_DEBUG_DISAS */ | 28 | + MemOpIdx oi, uintptr_t ra); |
21 | @@ -XXX,XX +XXX,XX @@ static uint32_t gen_prep_dbgex(DisasContext *ctx) | 29 | +uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr, |
22 | 30 | + MemOpIdx oi, uintptr_t ra); | |
23 | static void gen_debug_exception(DisasContext *ctx) | 31 | +uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr, |
24 | { | 32 | + MemOpIdx oi, uintptr_t ra); |
25 | - gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG)); | 33 | + |
26 | + gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); | 34 | uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr); |
27 | ctx->base.is_jmp = DISAS_NORETURN; | 35 | uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr); |
36 | uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr); | ||
37 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/accel/tcg/cputlb.c | ||
40 | +++ b/accel/tcg/cputlb.c | ||
41 | @@ -XXX,XX +XXX,XX @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr) | ||
42 | MemOpIdx oi = make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true)); | ||
43 | return full_ldq_code(env, addr, oi, 0); | ||
28 | } | 44 | } |
29 | 45 | + | |
30 | @@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) | 46 | +uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, |
31 | 47 | + MemOpIdx oi, uintptr_t retaddr) | |
32 | static void gen_lookup_and_goto_ptr(DisasContext *ctx) | 48 | +{ |
33 | { | 49 | + return full_ldub_code(env, addr, oi, retaddr); |
34 | - int sse = ctx->singlestep_enabled; | 50 | +} |
35 | - if (unlikely(sse)) { | 51 | + |
36 | - if (sse & GDBSTUB_SINGLE_STEP) { | 52 | +uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, |
37 | - gen_debug_exception(ctx); | 53 | + MemOpIdx oi, uintptr_t retaddr) |
38 | - } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { | 54 | +{ |
39 | - gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); | 55 | + MemOp mop = get_memop(oi); |
40 | - } else { | 56 | + int idx = get_mmuidx(oi); |
41 | - tcg_gen_exit_tb(NULL, 0); | 57 | + uint16_t ret; |
42 | - } | 58 | + |
43 | + if (unlikely(ctx->singlestep_enabled)) { | 59 | + ret = full_lduw_code(env, addr, make_memop_idx(MO_TEUW, idx), retaddr); |
44 | + gen_debug_exception(ctx); | 60 | + if ((mop & MO_BSWAP) != MO_TE) { |
45 | } else { | 61 | + ret = bswap16(ret); |
46 | tcg_gen_lookup_and_goto_ptr(); | 62 | + } |
47 | } | 63 | + return ret; |
48 | @@ -XXX,XX +XXX,XX @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | 64 | +} |
49 | ctx->singlestep_enabled = 0; | 65 | + |
50 | if ((hflags >> HFLAGS_SE) & 1) { | 66 | +uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr, |
51 | ctx->singlestep_enabled |= CPU_SINGLE_STEP; | 67 | + MemOpIdx oi, uintptr_t retaddr) |
52 | + ctx->base.max_insns = 1; | 68 | +{ |
53 | } | 69 | + MemOp mop = get_memop(oi); |
54 | if ((hflags >> HFLAGS_BE) & 1) { | 70 | + int idx = get_mmuidx(oi); |
55 | ctx->singlestep_enabled |= CPU_BRANCH_STEP; | 71 | + uint32_t ret; |
56 | } | 72 | + |
57 | - if (unlikely(ctx->base.singlestep_enabled)) { | 73 | + ret = full_ldl_code(env, addr, make_memop_idx(MO_TEUL, idx), retaddr); |
58 | - ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; | 74 | + if ((mop & MO_BSWAP) != MO_TE) { |
59 | - } | 75 | + ret = bswap32(ret); |
60 | - | 76 | + } |
61 | - if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) { | 77 | + return ret; |
62 | - ctx->base.max_insns = 1; | 78 | +} |
63 | - } | 79 | + |
80 | +uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr, | ||
81 | + MemOpIdx oi, uintptr_t retaddr) | ||
82 | +{ | ||
83 | + MemOp mop = get_memop(oi); | ||
84 | + int idx = get_mmuidx(oi); | ||
85 | + uint64_t ret; | ||
86 | + | ||
87 | + ret = full_ldq_code(env, addr, make_memop_idx(MO_TEUQ, idx), retaddr); | ||
88 | + if ((mop & MO_BSWAP) != MO_TE) { | ||
89 | + ret = bswap64(ret); | ||
90 | + } | ||
91 | + return ret; | ||
92 | +} | ||
93 | diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c | ||
94 | index XXXXXXX..XXXXXXX 100644 | ||
95 | --- a/accel/tcg/user-exec.c | ||
96 | +++ b/accel/tcg/user-exec.c | ||
97 | @@ -XXX,XX +XXX,XX @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) | ||
98 | return ret; | ||
64 | } | 99 | } |
65 | 100 | ||
66 | static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) | 101 | +uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, |
67 | @@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | 102 | + MemOpIdx oi, uintptr_t ra) |
68 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | 103 | +{ |
69 | DisasJumpType is_jmp = ctx->base.is_jmp; | 104 | + void *haddr; |
70 | target_ulong nip = ctx->base.pc_next; | 105 | + uint8_t ret; |
71 | - int sse; | 106 | + |
72 | 107 | + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_INST_FETCH); | |
73 | if (is_jmp == DISAS_NORETURN) { | 108 | + ret = ldub_p(haddr); |
74 | /* We have already exited the TB. */ | 109 | + clear_helper_retaddr(); |
75 | @@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | 110 | + return ret; |
76 | } | 111 | +} |
77 | 112 | + | |
78 | /* Honor single stepping. */ | 113 | +uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, |
79 | - sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP); | 114 | + MemOpIdx oi, uintptr_t ra) |
80 | - if (unlikely(sse)) { | 115 | +{ |
81 | + if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) | 116 | + void *haddr; |
82 | + && (nip <= 0x100 || nip > 0xf00)) { | 117 | + uint16_t ret; |
83 | switch (is_jmp) { | 118 | + |
84 | case DISAS_TOO_MANY: | 119 | + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_INST_FETCH); |
85 | case DISAS_EXIT_UPDATE: | 120 | + ret = lduw_p(haddr); |
86 | @@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | 121 | + clear_helper_retaddr(); |
87 | g_assert_not_reached(); | 122 | + if (get_memop(oi) & MO_BSWAP) { |
88 | } | 123 | + ret = bswap16(ret); |
89 | 124 | + } | |
90 | - if (sse & GDBSTUB_SINGLE_STEP) { | 125 | + return ret; |
91 | - gen_debug_exception(ctx); | 126 | +} |
92 | - return; | 127 | + |
93 | - } | 128 | +uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr, |
94 | - /* else CPU_SINGLE_STEP... */ | 129 | + MemOpIdx oi, uintptr_t ra) |
95 | - if (nip <= 0x100 || nip > 0xf00) { | 130 | +{ |
96 | - gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); | 131 | + void *haddr; |
97 | - return; | 132 | + uint32_t ret; |
98 | - } | 133 | + |
99 | + gen_debug_exception(ctx); | 134 | + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_INST_FETCH); |
100 | + return; | 135 | + ret = ldl_p(haddr); |
101 | } | 136 | + clear_helper_retaddr(); |
102 | 137 | + if (get_memop(oi) & MO_BSWAP) { | |
103 | switch (is_jmp) { | 138 | + ret = bswap32(ret); |
139 | + } | ||
140 | + return ret; | ||
141 | +} | ||
142 | + | ||
143 | +uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr, | ||
144 | + MemOpIdx oi, uintptr_t ra) | ||
145 | +{ | ||
146 | + void *haddr; | ||
147 | + uint64_t ret; | ||
148 | + | ||
149 | + validate_memop(oi, MO_BEUQ); | ||
150 | + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); | ||
151 | + ret = ldq_p(haddr); | ||
152 | + clear_helper_retaddr(); | ||
153 | + if (get_memop(oi) & MO_BSWAP) { | ||
154 | + ret = bswap64(ret); | ||
155 | + } | ||
156 | + return ret; | ||
157 | +} | ||
158 | + | ||
159 | #include "ldst_common.c.inc" | ||
160 | |||
161 | /* | ||
104 | -- | 162 | -- |
105 | 2.25.1 | 163 | 2.34.1 |
106 | |||
107 | diff view generated by jsdifflib |
1 | GDB single-stepping is now handled generically. | 1 | Since TCG_TYPE_I32 values are kept sign-extended in registers, |
---|---|---|---|
2 | via ".w" instructions, we need not extend if the register matches. | ||
3 | This is already relied upon by comparisons. | ||
2 | 4 | ||
3 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | --- | 7 | --- |
6 | target/sh4/helper.h | 1 - | 8 | tcg/loongarch64/tcg-target.c.inc | 4 +++- |
7 | target/sh4/op_helper.c | 5 ----- | 9 | 1 file changed, 3 insertions(+), 1 deletion(-) |
8 | target/sh4/translate.c | 14 +++----------- | ||
9 | 3 files changed, 3 insertions(+), 17 deletions(-) | ||
10 | 10 | ||
11 | diff --git a/target/sh4/helper.h b/target/sh4/helper.h | 11 | diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc |
12 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/sh4/helper.h | 13 | --- a/tcg/loongarch64/tcg-target.c.inc |
14 | +++ b/target/sh4/helper.h | 14 | +++ b/tcg/loongarch64/tcg-target.c.inc |
15 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env) | 15 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) |
16 | DEF_HELPER_1(raise_slot_illegal_instruction, noreturn, env) | 16 | |
17 | DEF_HELPER_1(raise_fpu_disable, noreturn, env) | 17 | static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) |
18 | DEF_HELPER_1(raise_slot_fpu_disable, noreturn, env) | 18 | { |
19 | -DEF_HELPER_1(debug, noreturn, env) | 19 | - tcg_out_ext32s(s, ret, arg); |
20 | DEF_HELPER_1(sleep, noreturn, env) | 20 | + if (ret != arg) { |
21 | DEF_HELPER_2(trapa, noreturn, env, i32) | 21 | + tcg_out_ext32s(s, ret, arg); |
22 | DEF_HELPER_1(exclusive, noreturn, env) | 22 | + } |
23 | diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/target/sh4/op_helper.c | ||
26 | +++ b/target/sh4/op_helper.c | ||
27 | @@ -XXX,XX +XXX,XX @@ void helper_raise_slot_fpu_disable(CPUSH4State *env) | ||
28 | raise_exception(env, 0x820, 0); | ||
29 | } | 23 | } |
30 | 24 | ||
31 | -void helper_debug(CPUSH4State *env) | 25 | static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) |
32 | -{ | ||
33 | - raise_exception(env, EXCP_DEBUG, 0); | ||
34 | -} | ||
35 | - | ||
36 | void helper_sleep(CPUSH4State *env) | ||
37 | { | ||
38 | CPUState *cs = env_cpu(env); | ||
39 | diff --git a/target/sh4/translate.c b/target/sh4/translate.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/target/sh4/translate.c | ||
42 | +++ b/target/sh4/translate.c | ||
43 | @@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) | ||
44 | tcg_gen_exit_tb(ctx->base.tb, n); | ||
45 | } else { | ||
46 | tcg_gen_movi_i32(cpu_pc, dest); | ||
47 | - if (ctx->base.singlestep_enabled) { | ||
48 | - gen_helper_debug(cpu_env); | ||
49 | - } else if (use_exit_tb(ctx)) { | ||
50 | + if (use_exit_tb(ctx)) { | ||
51 | tcg_gen_exit_tb(NULL, 0); | ||
52 | } else { | ||
53 | tcg_gen_lookup_and_goto_ptr(); | ||
54 | @@ -XXX,XX +XXX,XX @@ static void gen_jump(DisasContext * ctx) | ||
55 | delayed jump as immediate jump are conditinal jumps */ | ||
56 | tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); | ||
57 | tcg_gen_discard_i32(cpu_delayed_pc); | ||
58 | - if (ctx->base.singlestep_enabled) { | ||
59 | - gen_helper_debug(cpu_env); | ||
60 | - } else if (use_exit_tb(ctx)) { | ||
61 | + if (use_exit_tb(ctx)) { | ||
62 | tcg_gen_exit_tb(NULL, 0); | ||
63 | } else { | ||
64 | tcg_gen_lookup_and_goto_ptr(); | ||
65 | @@ -XXX,XX +XXX,XX @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | ||
66 | switch (ctx->base.is_jmp) { | ||
67 | case DISAS_STOP: | ||
68 | gen_save_cpu_state(ctx, true); | ||
69 | - if (ctx->base.singlestep_enabled) { | ||
70 | - gen_helper_debug(cpu_env); | ||
71 | - } else { | ||
72 | - tcg_gen_exit_tb(NULL, 0); | ||
73 | - } | ||
74 | + tcg_gen_exit_tb(NULL, 0); | ||
75 | break; | ||
76 | case DISAS_NEXT: | ||
77 | case DISAS_TOO_MANY: | ||
78 | -- | 26 | -- |
79 | 2.25.1 | 27 | 2.34.1 |
80 | 28 | ||
81 | 29 | diff view generated by jsdifflib |
1 | GDB single-stepping is now handled generically. | 1 | Since TCG_TYPE_I32 values are kept sign-extended in registers, we need not |
---|---|---|---|
2 | extend if the register matches. This is already relied upon by comparisons. | ||
2 | 3 | ||
3 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | --- | 6 | --- |
6 | target/rx/helper.h | 1 - | 7 | tcg/mips/tcg-target.c.inc | 4 +++- |
7 | target/rx/op_helper.c | 8 -------- | 8 | 1 file changed, 3 insertions(+), 1 deletion(-) |
8 | target/rx/translate.c | 12 ++---------- | ||
9 | 3 files changed, 2 insertions(+), 19 deletions(-) | ||
10 | 9 | ||
11 | diff --git a/target/rx/helper.h b/target/rx/helper.h | 10 | diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc |
12 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/rx/helper.h | 12 | --- a/tcg/mips/tcg-target.c.inc |
14 | +++ b/target/rx/helper.h | 13 | +++ b/tcg/mips/tcg-target.c.inc |
15 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env) | 14 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) |
16 | DEF_HELPER_1(raise_access_fault, noreturn, env) | 15 | |
17 | DEF_HELPER_1(raise_privilege_violation, noreturn, env) | 16 | static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) |
18 | DEF_HELPER_1(wait, noreturn, env) | 17 | { |
19 | -DEF_HELPER_1(debug, noreturn, env) | 18 | - tcg_out_ext32s(s, rd, rs); |
20 | DEF_HELPER_2(rxint, noreturn, env, i32) | 19 | + if (rd != rs) { |
21 | DEF_HELPER_1(rxbrk, noreturn, env) | 20 | + tcg_out_ext32s(s, rd, rs); |
22 | DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32) | 21 | + } |
23 | diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/target/rx/op_helper.c | ||
26 | +++ b/target/rx/op_helper.c | ||
27 | @@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_wait(CPURXState *env) | ||
28 | raise_exception(env, EXCP_HLT, 0); | ||
29 | } | 22 | } |
30 | 23 | ||
31 | -void QEMU_NORETURN helper_debug(CPURXState *env) | 24 | static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) |
32 | -{ | ||
33 | - CPUState *cs = env_cpu(env); | ||
34 | - | ||
35 | - cs->exception_index = EXCP_DEBUG; | ||
36 | - cpu_loop_exit(cs); | ||
37 | -} | ||
38 | - | ||
39 | void QEMU_NORETURN helper_rxint(CPURXState *env, uint32_t vec) | ||
40 | { | ||
41 | raise_exception(env, 0x100 + vec, 0); | ||
42 | diff --git a/target/rx/translate.c b/target/rx/translate.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/rx/translate.c | ||
45 | +++ b/target/rx/translate.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) | ||
47 | tcg_gen_exit_tb(dc->base.tb, n); | ||
48 | } else { | ||
49 | tcg_gen_movi_i32(cpu_pc, dest); | ||
50 | - if (dc->base.singlestep_enabled) { | ||
51 | - gen_helper_debug(cpu_env); | ||
52 | - } else { | ||
53 | - tcg_gen_lookup_and_goto_ptr(); | ||
54 | - } | ||
55 | + tcg_gen_lookup_and_goto_ptr(); | ||
56 | } | ||
57 | dc->base.is_jmp = DISAS_NORETURN; | ||
58 | } | ||
59 | @@ -XXX,XX +XXX,XX @@ static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | ||
60 | gen_goto_tb(ctx, 0, dcbase->pc_next); | ||
61 | break; | ||
62 | case DISAS_JUMP: | ||
63 | - if (ctx->base.singlestep_enabled) { | ||
64 | - gen_helper_debug(cpu_env); | ||
65 | - } else { | ||
66 | - tcg_gen_lookup_and_goto_ptr(); | ||
67 | - } | ||
68 | + tcg_gen_lookup_and_goto_ptr(); | ||
69 | break; | ||
70 | case DISAS_UPDATE: | ||
71 | tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); | ||
72 | -- | 25 | -- |
73 | 2.25.1 | 26 | 2.34.1 |
74 | 27 | ||
75 | 28 | diff view generated by jsdifflib |
1 | GDB single-stepping is now handled generically. | 1 | This is common code in most qemu_{ld,st} slow paths, moving two |
---|---|---|---|
2 | 2 | registers when there may be overlap between sources and destinations. | |
3 | Acked-by: Laurent Vivier <laurent@vivier.eu> | 3 | At present, this is only used by 32-bit hosts for 64-bit data, |
4 | but will shortly be used for more than that. | ||
5 | |||
6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | --- | 8 | --- |
6 | target/m68k/translate.c | 44 +++++++++-------------------------------- | 9 | tcg/tcg.c | 69 ++++++++++++++++++++++++++++++++++++--- |
7 | 1 file changed, 9 insertions(+), 35 deletions(-) | 10 | tcg/arm/tcg-target.c.inc | 44 ++++++++++--------------- |
8 | 11 | tcg/i386/tcg-target.c.inc | 19 +++++------ | |
9 | diff --git a/target/m68k/translate.c b/target/m68k/translate.c | 12 | 3 files changed, 90 insertions(+), 42 deletions(-) |
13 | |||
14 | diff --git a/tcg/tcg.c b/tcg/tcg.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
11 | --- a/target/m68k/translate.c | 16 | --- a/tcg/tcg.c |
12 | +++ b/target/m68k/translate.c | 17 | +++ b/tcg/tcg.c |
13 | @@ -XXX,XX +XXX,XX @@ static void do_writebacks(DisasContext *s) | 18 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); |
14 | } | 19 | static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); |
20 | static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg); | ||
21 | static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long); | ||
22 | -static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) | ||
23 | - __attribute__((unused)); | ||
24 | +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2); | ||
25 | static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); | ||
26 | static void tcg_out_goto_tb(TCGContext *s, int which); | ||
27 | static void tcg_out_op(TCGContext *s, TCGOpcode opc, | ||
28 | @@ -XXX,XX +XXX,XX @@ void tcg_raise_tb_overflow(TCGContext *s) | ||
29 | siglongjmp(s->jmp_trans, -2); | ||
15 | } | 30 | } |
16 | 31 | ||
17 | -static bool is_singlestepping(DisasContext *s) | 32 | +typedef struct TCGMovExtend { |
18 | -{ | 33 | + TCGReg dst; |
19 | - /* | 34 | + TCGReg src; |
20 | - * Return true if we are singlestepping either because of | 35 | + TCGType dst_type; |
21 | - * architectural singlestep or QEMU gdbstub singlestep. This does | 36 | + TCGType src_type; |
22 | - * not include the command line '-singlestep' mode which is rather | 37 | + MemOp src_ext; |
23 | - * misnamed as it only means "one instruction per TB" and doesn't | 38 | +} TCGMovExtend; |
24 | - * affect the code we generate. | 39 | + |
25 | - */ | 40 | /** |
26 | - return s->base.singlestep_enabled || s->ss_active; | 41 | * tcg_out_movext -- move and extend |
27 | -} | 42 | * @s: tcg context |
28 | - | 43 | @@ -XXX,XX +XXX,XX @@ void tcg_raise_tb_overflow(TCGContext *s) |
29 | /* is_jmp field values */ | 44 | * |
30 | #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ | 45 | * Move or extend @src into @dst, depending on @src_ext and the types. |
31 | #define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */ | 46 | */ |
32 | @@ -XXX,XX +XXX,XX @@ static void gen_exception(DisasContext *s, uint32_t dest, int nr) | 47 | -static void __attribute__((unused)) |
33 | s->base.is_jmp = DISAS_NORETURN; | 48 | -tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst, |
49 | - TCGType src_type, MemOp src_ext, TCGReg src) | ||
50 | +static void tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst, | ||
51 | + TCGType src_type, MemOp src_ext, TCGReg src) | ||
52 | { | ||
53 | switch (src_ext) { | ||
54 | case MO_UB: | ||
55 | @@ -XXX,XX +XXX,XX @@ tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst, | ||
56 | } | ||
34 | } | 57 | } |
35 | 58 | ||
36 | -static void gen_singlestep_exception(DisasContext *s) | 59 | +/* Minor variations on a theme, using a structure. */ |
37 | -{ | 60 | +static void tcg_out_movext1_new_src(TCGContext *s, const TCGMovExtend *i, |
38 | - /* | 61 | + TCGReg src) |
39 | - * Generate the right kind of exception for singlestep, which is | 62 | +{ |
40 | - * either the architectural singlestep or EXCP_DEBUG for QEMU's | 63 | + tcg_out_movext(s, i->dst_type, i->dst, i->src_type, i->src_ext, src); |
41 | - * gdb singlestepping. | 64 | +} |
42 | - */ | 65 | + |
43 | - if (s->ss_active) { | 66 | +static void tcg_out_movext1(TCGContext *s, const TCGMovExtend *i) |
44 | - gen_raise_exception(EXCP_TRACE); | 67 | +{ |
45 | - } else { | 68 | + tcg_out_movext1_new_src(s, i, i->src); |
46 | - gen_raise_exception(EXCP_DEBUG); | 69 | +} |
47 | - } | 70 | + |
48 | -} | 71 | +/** |
49 | - | 72 | + * tcg_out_movext2 -- move and extend two pair |
50 | static inline void gen_addr_fault(DisasContext *s) | 73 | + * @s: tcg context |
74 | + * @i1: first move description | ||
75 | + * @i2: second move description | ||
76 | + * @scratch: temporary register, or -1 for none | ||
77 | + * | ||
78 | + * As tcg_out_movext, for both @i1 and @i2, caring for overlap | ||
79 | + * between the sources and destinations. | ||
80 | + */ | ||
81 | + | ||
82 | +static void __attribute__((unused)) | ||
83 | +tcg_out_movext2(TCGContext *s, const TCGMovExtend *i1, | ||
84 | + const TCGMovExtend *i2, int scratch) | ||
85 | +{ | ||
86 | + TCGReg src1 = i1->src; | ||
87 | + TCGReg src2 = i2->src; | ||
88 | + | ||
89 | + if (i1->dst != src2) { | ||
90 | + tcg_out_movext1(s, i1); | ||
91 | + tcg_out_movext1(s, i2); | ||
92 | + return; | ||
93 | + } | ||
94 | + if (i2->dst == src1) { | ||
95 | + TCGType src1_type = i1->src_type; | ||
96 | + TCGType src2_type = i2->src_type; | ||
97 | + | ||
98 | + if (tcg_out_xchg(s, MAX(src1_type, src2_type), src1, src2)) { | ||
99 | + /* The data is now in the correct registers, now extend. */ | ||
100 | + src1 = i2->src; | ||
101 | + src2 = i1->src; | ||
102 | + } else { | ||
103 | + tcg_debug_assert(scratch >= 0); | ||
104 | + tcg_out_mov(s, src1_type, scratch, src1); | ||
105 | + src1 = scratch; | ||
106 | + } | ||
107 | + } | ||
108 | + tcg_out_movext1_new_src(s, i2, src2); | ||
109 | + tcg_out_movext1_new_src(s, i1, src1); | ||
110 | +} | ||
111 | + | ||
112 | #define C_PFX1(P, A) P##A | ||
113 | #define C_PFX2(P, A, B) P##A##_##B | ||
114 | #define C_PFX3(P, A, B, C) P##A##_##B##_##C | ||
115 | diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc | ||
116 | index XXXXXXX..XXXXXXX 100644 | ||
117 | --- a/tcg/arm/tcg-target.c.inc | ||
118 | +++ b/tcg/arm/tcg-target.c.inc | ||
119 | @@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, | ||
120 | |||
121 | static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) | ||
51 | { | 122 | { |
52 | gen_exception(s, s->base.pc_next, EXCP_ADDRESS); | 123 | - TCGReg argreg, datalo, datahi; |
53 | @@ -XXX,XX +XXX,XX @@ static void gen_exit_tb(DisasContext *s) | 124 | + TCGReg argreg; |
54 | /* Generate a jump to an immediate address. */ | 125 | MemOpIdx oi = lb->oi; |
55 | static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) | 126 | MemOp opc = get_memop(oi); |
127 | |||
128 | @@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) | ||
129 | /* Use the canonical unsigned helpers and minimize icache usage. */ | ||
130 | tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); | ||
131 | |||
132 | - datalo = lb->datalo_reg; | ||
133 | - datahi = lb->datahi_reg; | ||
134 | if ((opc & MO_SIZE) == MO_64) { | ||
135 | - if (datalo != TCG_REG_R1) { | ||
136 | - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); | ||
137 | - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); | ||
138 | - } else if (datahi != TCG_REG_R0) { | ||
139 | - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); | ||
140 | - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); | ||
141 | - } else { | ||
142 | - tcg_out_mov_reg(s, COND_AL, TCG_REG_TMP, TCG_REG_R0); | ||
143 | - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); | ||
144 | - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_TMP); | ||
145 | - } | ||
146 | + TCGMovExtend ext[2] = { | ||
147 | + { .dst = lb->datalo_reg, .dst_type = TCG_TYPE_I32, | ||
148 | + .src = TCG_REG_R0, .src_type = TCG_TYPE_I32, .src_ext = MO_UL }, | ||
149 | + { .dst = lb->datahi_reg, .dst_type = TCG_TYPE_I32, | ||
150 | + .src = TCG_REG_R1, .src_type = TCG_TYPE_I32, .src_ext = MO_UL }, | ||
151 | + }; | ||
152 | + tcg_out_movext2(s, &ext[0], &ext[1], TCG_REG_TMP); | ||
153 | } else { | ||
154 | - tcg_out_movext(s, TCG_TYPE_I32, datalo, | ||
155 | + tcg_out_movext(s, TCG_TYPE_I32, lb->datalo_reg, | ||
156 | TCG_TYPE_I32, opc & MO_SSIZE, TCG_REG_R0); | ||
157 | } | ||
158 | |||
159 | @@ -XXX,XX +XXX,XX @@ static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) | ||
160 | |||
161 | if (TARGET_LONG_BITS == 64) { | ||
162 | /* 64-bit target address is aligned into R2:R3. */ | ||
163 | - if (l->addrhi_reg != TCG_REG_R2) { | ||
164 | - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, l->addrlo_reg); | ||
165 | - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, l->addrhi_reg); | ||
166 | - } else if (l->addrlo_reg != TCG_REG_R3) { | ||
167 | - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, l->addrhi_reg); | ||
168 | - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, l->addrlo_reg); | ||
169 | - } else { | ||
170 | - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, TCG_REG_R2); | ||
171 | - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, TCG_REG_R3); | ||
172 | - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, TCG_REG_R1); | ||
173 | - } | ||
174 | + TCGMovExtend ext[2] = { | ||
175 | + { .dst = TCG_REG_R2, .dst_type = TCG_TYPE_I32, | ||
176 | + .src = l->addrlo_reg, | ||
177 | + .src_type = TCG_TYPE_I32, .src_ext = MO_UL }, | ||
178 | + { .dst = TCG_REG_R3, .dst_type = TCG_TYPE_I32, | ||
179 | + .src = l->addrhi_reg, | ||
180 | + .src_type = TCG_TYPE_I32, .src_ext = MO_UL }, | ||
181 | + }; | ||
182 | + tcg_out_movext2(s, &ext[0], &ext[1], TCG_REG_TMP); | ||
183 | } else { | ||
184 | tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, l->addrlo_reg); | ||
185 | } | ||
186 | diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc | ||
187 | index XXXXXXX..XXXXXXX 100644 | ||
188 | --- a/tcg/i386/tcg-target.c.inc | ||
189 | +++ b/tcg/i386/tcg-target.c.inc | ||
190 | @@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) | ||
56 | { | 191 | { |
57 | - if (unlikely(is_singlestepping(s))) { | 192 | MemOpIdx oi = l->oi; |
58 | + if (unlikely(s->ss_active)) { | 193 | MemOp opc = get_memop(oi); |
59 | update_cc_op(s); | 194 | - TCGReg data_reg; |
60 | tcg_gen_movi_i32(QREG_PC, dest); | 195 | tcg_insn_unit **label_ptr = &l->label_ptr[0]; |
61 | - gen_singlestep_exception(s); | 196 | |
62 | + gen_raise_exception(EXCP_TRACE); | 197 | /* resolve label address */ |
63 | } else if (translator_use_goto_tb(&s->base, dest)) { | 198 | @@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) |
64 | tcg_gen_goto_tb(n); | 199 | |
65 | tcg_gen_movi_i32(QREG_PC, dest); | 200 | tcg_out_branch(s, 1, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); |
66 | @@ -XXX,XX +XXX,XX @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) | 201 | |
67 | 202 | - data_reg = l->datalo_reg; | |
68 | dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS); | 203 | if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { |
69 | /* If architectural single step active, limit to 1 */ | 204 | - if (data_reg == TCG_REG_EDX) { |
70 | - if (is_singlestepping(dc)) { | 205 | - /* xchg %edx, %eax */ |
71 | + if (dc->ss_active) { | 206 | - tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0); |
72 | dc->base.max_insns = 1; | 207 | - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EAX); |
73 | } | 208 | - } else { |
74 | } | 209 | - tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); |
75 | @@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | 210 | - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX); |
76 | break; | 211 | - } |
77 | case DISAS_TOO_MANY: | 212 | + TCGMovExtend ext[2] = { |
78 | update_cc_op(dc); | 213 | + { .dst = l->datalo_reg, .dst_type = TCG_TYPE_I32, |
79 | - if (is_singlestepping(dc)) { | 214 | + .src = TCG_REG_EAX, .src_type = TCG_TYPE_I32, .src_ext = MO_UL }, |
80 | + if (dc->ss_active) { | 215 | + { .dst = l->datahi_reg, .dst_type = TCG_TYPE_I32, |
81 | tcg_gen_movi_i32(QREG_PC, dc->pc); | 216 | + .src = TCG_REG_EDX, .src_type = TCG_TYPE_I32, .src_ext = MO_UL }, |
82 | - gen_singlestep_exception(dc); | 217 | + }; |
83 | + gen_raise_exception(EXCP_TRACE); | 218 | + tcg_out_movext2(s, &ext[0], &ext[1], -1); |
84 | } else { | 219 | } else { |
85 | gen_jmp_tb(dc, 0, dc->pc); | 220 | - tcg_out_movext(s, l->type, data_reg, |
86 | } | 221 | + tcg_out_movext(s, l->type, l->datalo_reg, |
87 | break; | 222 | TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_EAX); |
88 | case DISAS_JUMP: | 223 | } |
89 | /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */ | 224 | |
90 | - if (is_singlestepping(dc)) { | ||
91 | - gen_singlestep_exception(dc); | ||
92 | + if (dc->ss_active) { | ||
93 | + gen_raise_exception(EXCP_TRACE); | ||
94 | } else { | ||
95 | tcg_gen_lookup_and_goto_ptr(); | ||
96 | } | ||
97 | @@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
98 | * We updated CC_OP and PC in gen_exit_tb, but also modified | ||
99 | * other state that may require returning to the main loop. | ||
100 | */ | ||
101 | - if (is_singlestepping(dc)) { | ||
102 | - gen_singlestep_exception(dc); | ||
103 | + if (dc->ss_active) { | ||
104 | + gen_raise_exception(EXCP_TRACE); | ||
105 | } else { | ||
106 | tcg_gen_exit_tb(NULL, 0); | ||
107 | } | ||
108 | -- | 225 | -- |
109 | 2.25.1 | 226 | 2.34.1 |
110 | 227 | ||
111 | 228 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | GDB single-stepping is now handled generically. | ||
2 | 1 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | --- | ||
5 | target/microblaze/translate.c | 14 ++------------ | ||
6 | 1 file changed, 2 insertions(+), 12 deletions(-) | ||
7 | |||
8 | diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c | ||
9 | index XXXXXXX..XXXXXXX 100644 | ||
10 | --- a/target/microblaze/translate.c | ||
11 | +++ b/target/microblaze/translate.c | ||
12 | @@ -XXX,XX +XXX,XX @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec) | ||
13 | |||
14 | static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) | ||
15 | { | ||
16 | - if (dc->base.singlestep_enabled) { | ||
17 | - TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); | ||
18 | - tcg_gen_movi_i32(cpu_pc, dest); | ||
19 | - gen_helper_raise_exception(cpu_env, tmp); | ||
20 | - tcg_temp_free_i32(tmp); | ||
21 | - } else if (translator_use_goto_tb(&dc->base, dest)) { | ||
22 | + if (translator_use_goto_tb(&dc->base, dest)) { | ||
23 | tcg_gen_goto_tb(n); | ||
24 | tcg_gen_movi_i32(cpu_pc, dest); | ||
25 | tcg_gen_exit_tb(dc->base.tb, n); | ||
26 | @@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) | ||
27 | /* Indirect jump (or direct jump w/ goto_tb disabled) */ | ||
28 | tcg_gen_mov_i32(cpu_pc, cpu_btarget); | ||
29 | tcg_gen_discard_i32(cpu_btarget); | ||
30 | - | ||
31 | - if (unlikely(cs->singlestep_enabled)) { | ||
32 | - gen_raise_exception(dc, EXCP_DEBUG); | ||
33 | - } else { | ||
34 | - tcg_gen_lookup_and_goto_ptr(); | ||
35 | - } | ||
36 | + tcg_gen_lookup_and_goto_ptr(); | ||
37 | return; | ||
38 | |||
39 | default: | ||
40 | -- | ||
41 | 2.25.1 | ||
42 | |||
43 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | As per an ancient comment in mips_tr_translate_insn about the | ||
2 | expectations of gdb, when restarting the insn in a delay slot | ||
3 | we also re-execute the branch. Which means that we are | ||
4 | expected to execute two insns in this case. | ||
5 | 1 | ||
6 | This has been broken since 8b86d6d2580, where we forced max_insns | ||
7 | to 1 while single-stepping. This resulted in an exit from the | ||
8 | translator loop after the branch but before the delay slot is | ||
9 | translated. | ||
10 | |||
11 | Increase the max_insns to 2 for this case. In addition, bypass | ||
12 | the end-of-page check, for when the branch itself ends the page. | ||
13 | |||
14 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
15 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
16 | --- | ||
17 | target/mips/tcg/translate.c | 25 ++++++++++++++++--------- | ||
18 | 1 file changed, 16 insertions(+), 9 deletions(-) | ||
19 | |||
20 | diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/target/mips/tcg/translate.c | ||
23 | +++ b/target/mips/tcg/translate.c | ||
24 | @@ -XXX,XX +XXX,XX @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | ||
25 | ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 | | ||
26 | INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; | ||
27 | |||
28 | + /* | ||
29 | + * Execute a branch and its delay slot as a single instruction. | ||
30 | + * This is what GDB expects and is consistent with what the | ||
31 | + * hardware does (e.g. if a delay slot instruction faults, the | ||
32 | + * reported PC is the PC of the branch). | ||
33 | + */ | ||
34 | + if (ctx->base.singlestep_enabled && (ctx->hflags & MIPS_HFLAG_BMASK)) { | ||
35 | + ctx->base.max_insns = 2; | ||
36 | + } | ||
37 | + | ||
38 | LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, | ||
39 | ctx->hflags); | ||
40 | } | ||
41 | @@ -XXX,XX +XXX,XX @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) | ||
42 | if (ctx->base.is_jmp != DISAS_NEXT) { | ||
43 | return; | ||
44 | } | ||
45 | + | ||
46 | /* | ||
47 | - * Execute a branch and its delay slot as a single instruction. | ||
48 | - * This is what GDB expects and is consistent with what the | ||
49 | - * hardware does (e.g. if a delay slot instruction faults, the | ||
50 | - * reported PC is the PC of the branch). | ||
51 | + * End the TB on (most) page crossings. | ||
52 | + * See mips_tr_init_disas_context about single-stepping a branch | ||
53 | + * together with its delay slot. | ||
54 | */ | ||
55 | - if (ctx->base.singlestep_enabled && | ||
56 | - (ctx->hflags & MIPS_HFLAG_BMASK) == 0) { | ||
57 | - ctx->base.is_jmp = DISAS_TOO_MANY; | ||
58 | - } | ||
59 | - if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE) { | ||
60 | + if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE | ||
61 | + && !ctx->base.singlestep_enabled) { | ||
62 | ctx->base.is_jmp = DISAS_TOO_MANY; | ||
63 | } | ||
64 | } | ||
65 | -- | ||
66 | 2.25.1 | ||
67 | |||
68 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | GDB single-stepping is now handled generically. | ||
2 | 1 | ||
3 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | --- | ||
6 | target/openrisc/translate.c | 18 +++--------------- | ||
7 | 1 file changed, 3 insertions(+), 15 deletions(-) | ||
8 | |||
9 | diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/target/openrisc/translate.c | ||
12 | +++ b/target/openrisc/translate.c | ||
13 | @@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | ||
14 | /* The jump destination is indirect/computed; use jmp_pc. */ | ||
15 | tcg_gen_mov_tl(cpu_pc, jmp_pc); | ||
16 | tcg_gen_discard_tl(jmp_pc); | ||
17 | - if (unlikely(dc->base.singlestep_enabled)) { | ||
18 | - gen_exception(dc, EXCP_DEBUG); | ||
19 | - } else { | ||
20 | - tcg_gen_lookup_and_goto_ptr(); | ||
21 | - } | ||
22 | + tcg_gen_lookup_and_goto_ptr(); | ||
23 | break; | ||
24 | } | ||
25 | /* The jump destination is direct; use jmp_pc_imm. | ||
26 | @@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | ||
27 | break; | ||
28 | } | ||
29 | tcg_gen_movi_tl(cpu_pc, jmp_dest); | ||
30 | - if (unlikely(dc->base.singlestep_enabled)) { | ||
31 | - gen_exception(dc, EXCP_DEBUG); | ||
32 | - } else { | ||
33 | - tcg_gen_lookup_and_goto_ptr(); | ||
34 | - } | ||
35 | + tcg_gen_lookup_and_goto_ptr(); | ||
36 | break; | ||
37 | |||
38 | case DISAS_EXIT: | ||
39 | - if (unlikely(dc->base.singlestep_enabled)) { | ||
40 | - gen_exception(dc, EXCP_DEBUG); | ||
41 | - } else { | ||
42 | - tcg_gen_exit_tb(NULL, 0); | ||
43 | - } | ||
44 | + tcg_gen_exit_tb(NULL, 0); | ||
45 | break; | ||
46 | default: | ||
47 | g_assert_not_reached(); | ||
48 | -- | ||
49 | 2.25.1 | ||
50 | |||
51 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | GDB single-stepping is now handled generically. | ||
2 | 1 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | --- | ||
5 | target/xtensa/translate.c | 25 ++++++++----------------- | ||
6 | 1 file changed, 8 insertions(+), 17 deletions(-) | ||
7 | |||
8 | diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c | ||
9 | index XXXXXXX..XXXXXXX 100644 | ||
10 | --- a/target/xtensa/translate.c | ||
11 | +++ b/target/xtensa/translate.c | ||
12 | @@ -XXX,XX +XXX,XX @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) | ||
13 | if (dc->icount) { | ||
14 | tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); | ||
15 | } | ||
16 | - if (dc->base.singlestep_enabled) { | ||
17 | - gen_exception(dc, EXCP_DEBUG); | ||
18 | + if (dc->op_flags & XTENSA_OP_POSTPROCESS) { | ||
19 | + slot = gen_postprocess(dc, slot); | ||
20 | + } | ||
21 | + if (slot >= 0) { | ||
22 | + tcg_gen_goto_tb(slot); | ||
23 | + tcg_gen_exit_tb(dc->base.tb, slot); | ||
24 | } else { | ||
25 | - if (dc->op_flags & XTENSA_OP_POSTPROCESS) { | ||
26 | - slot = gen_postprocess(dc, slot); | ||
27 | - } | ||
28 | - if (slot >= 0) { | ||
29 | - tcg_gen_goto_tb(slot); | ||
30 | - tcg_gen_exit_tb(dc->base.tb, slot); | ||
31 | - } else { | ||
32 | - tcg_gen_exit_tb(NULL, 0); | ||
33 | - } | ||
34 | + tcg_gen_exit_tb(NULL, 0); | ||
35 | } | ||
36 | dc->base.is_jmp = DISAS_NORETURN; | ||
37 | } | ||
38 | @@ -XXX,XX +XXX,XX @@ static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
39 | case DISAS_NORETURN: | ||
40 | break; | ||
41 | case DISAS_TOO_MANY: | ||
42 | - if (dc->base.singlestep_enabled) { | ||
43 | - tcg_gen_movi_i32(cpu_pc, dc->pc); | ||
44 | - gen_exception(dc, EXCP_DEBUG); | ||
45 | - } else { | ||
46 | - gen_jumpi(dc, dc->pc, 0); | ||
47 | - } | ||
48 | + gen_jumpi(dc, dc->pc, 0); | ||
49 | break; | ||
50 | default: | ||
51 | g_assert_not_reached(); | ||
52 | -- | ||
53 | 2.25.1 | ||
54 | |||
55 | diff view generated by jsdifflib |