[PULL 00/24] tcg patch queue
[PULL v3 00/91] tcg patch queue
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The following changes since commit 6587b0c1331d427b0939c37e763842550ed581db:
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Version 3 fixes a rebase error from v2 affecting ARM BFC insn.
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Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-10-15' into staging (2021-10-15 14:16:28 -0700)
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r~
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The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:
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Merge tag 'linux-user-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2023-03-12 10:57:00 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211016
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230313
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for you to fetch changes up to 995b87dedc78b0467f5f18bbc3546072ba97516a:
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for you to fetch changes up to 0c8b6b9a6383e2e37ff3d1d12b40c58b7ed36c1c:
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Revert "cpu: Move cpu_common_props to hw/core/cpu.c" (2021-10-15 16:39:15 -0700)
17
tcg: Drop tcg_const_* (2023-03-13 07:03:39 -0700)
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13
----------------------------------------------------------------
19
----------------------------------------------------------------
14
Move gdb singlestep to generic code
20
accel/tcg: Fix NB_MMU_MODES to 16
15
Fix cpu_common_props
21
Balance of the target/ patchset which eliminates tcg_temp_free
22
Balance of the target/ patchset which eliminates tcg_const
16
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17
----------------------------------------------------------------
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----------------------------------------------------------------
18
Richard Henderson (24):
25
Anton Johansson (23):
19
accel/tcg: Handle gdb singlestep in cpu_tb_exec
26
include/exec: Set default `NB_MMU_MODES` to 16
20
target/alpha: Drop checks for singlestep_enabled
27
target/alpha: Remove `NB_MMU_MODES` define
21
target/avr: Drop checks for singlestep_enabled
28
target/arm: Remove `NB_MMU_MODES` define
22
target/cris: Drop checks for singlestep_enabled
29
target/avr: Remove `NB_MMU_MODES` define
23
target/hexagon: Drop checks for singlestep_enabled
30
target/cris: Remove `NB_MMU_MODES` define
24
target/arm: Drop checks for singlestep_enabled
31
target/hexagon: Remove `NB_MMU_MODES` define
25
target/hppa: Drop checks for singlestep_enabled
32
target/hppa: Remove `NB_MMU_MODES` define
26
target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt
33
target/i386: Remove `NB_MMU_MODES` define
27
target/i386: Drop check for singlestep_enabled
34
target/loongarch: Remove `NB_MMU_MODES` define
28
target/m68k: Drop checks for singlestep_enabled
35
target/m68k: Remove `NB_MMU_MODES` define
29
target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP
36
target/microblaze: Remove `NB_MMU_MODES` define
30
target/microblaze: Drop checks for singlestep_enabled
37
target/mips: Remove `NB_MMU_MODES` define
31
target/mips: Fix single stepping
38
target/nios2: Remove `NB_MMU_MODES` define
32
target/mips: Drop exit checks for singlestep_enabled
39
target/openrisc: Remove `NB_MMU_MODES` define
33
target/openrisc: Drop checks for singlestep_enabled
40
target/ppc: Remove `NB_MMU_MODES` define
34
target/ppc: Drop exit checks for singlestep_enabled
41
target/riscv: Remove `NB_MMU_MODES` define
35
target/riscv: Remove dead code after exception
42
target/rx: Remove `NB_MMU_MODES` define
36
target/riscv: Remove exit_tb and lookup_and_goto_ptr
43
target/s390x: Remove `NB_MMU_MODES` define
37
target/rx: Drop checks for singlestep_enabled
44
target/sh4: Remove `NB_MMU_MODES` define
38
target/s390x: Drop check for singlestep_enabled
45
target/sparc: Remove `NB_MMU_MODES` define
39
target/sh4: Drop check for singlestep_enabled
46
target/tricore: Remove `NB_MMU_MODES` define
40
target/tricore: Drop check for singlestep_enabled
47
target/xtensa: Remove `NB_MMU_MODES` define
41
target/xtensa: Drop check for singlestep_enabled
48
include/exec: Remove guards around `NB_MMU_MODES`
42
Revert "cpu: Move cpu_common_props to hw/core/cpu.c"
43
49
44
include/hw/core/cpu.h | 1 +
50
Richard Henderson (68):
45
target/i386/helper.h | 1 -
51
target/mips: Drop tcg_temp_free from micromips_translate.c.inc
46
target/rx/helper.h | 1 -
52
target/mips: Drop tcg_temp_free from msa_translate.c
47
target/sh4/helper.h | 1 -
53
target/mips: Drop tcg_temp_free from mxu_translate.c
48
target/tricore/helper.h | 1 -
54
target/mips: Drop tcg_temp_free from nanomips_translate.c.inc
49
accel/tcg/cpu-exec.c | 11 ++++
55
target/mips: Drop tcg_temp_free from octeon_translate.c
50
cpu.c | 21 ++++++++
56
target/mips: Drop tcg_temp_free from translate_addr_const.c
51
hw/core/cpu-common.c | 17 +-----
57
target/mips: Drop tcg_temp_free from tx79_translate.c
52
target/alpha/translate.c | 13 ++---
58
target/mips: Drop tcg_temp_free from vr54xx_translate.c
53
target/arm/translate-a64.c | 10 +---
59
target/mips: Drop tcg_temp_free from translate.c
54
target/arm/translate.c | 36 +++----------
60
target/s390x: Drop free_compare
55
target/avr/translate.c | 19 ++-----
61
target/s390x: Drop tcg_temp_free from translate_vx.c.inc
56
target/cris/translate.c | 16 ------
62
target/s390x: Drop tcg_temp_free from translate.c
57
target/hexagon/translate.c | 12 +----
63
target/s390x: Remove assert vs g_in2
58
target/hppa/translate.c | 17 ++----
64
target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext
59
target/i386/tcg/misc_helper.c | 8 ---
65
tcg: Create tcg/tcg-temp-internal.h
60
target/i386/tcg/translate.c | 9 ++--
66
target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS
61
target/m68k/translate.c | 44 ++++-----------
67
target/avr: Avoid use of tcg_const_i32 throughout
62
target/microblaze/translate.c | 18 ++-----
68
target/cris: Avoid use of tcg_const_i32 throughout
63
target/mips/tcg/translate.c | 75 ++++++++++++--------------
69
target/hppa: Avoid tcg_const_i64 in trans_fid_f
64
target/openrisc/translate.c | 18 ++-----
70
target/hppa: Avoid use of tcg_const_i32 throughout
65
target/ppc/translate.c | 38 +++----------
71
target/i386: Avoid use of tcg_const_* throughout
66
target/riscv/translate.c | 27 +---------
72
target/m68k: Avoid tcg_const_i32 when modified
67
target/rx/op_helper.c | 8 ---
73
target/m68k: Avoid tcg_const_i32 in bfop_reg
68
target/rx/translate.c | 12 +----
74
target/m68k: Avoid tcg_const_* throughout
69
target/s390x/tcg/translate.c | 8 +--
75
target/mips: Split out gen_lxl
70
target/sh4/op_helper.c | 5 --
76
target/mips: Split out gen_lxr
71
target/sh4/translate.c | 14 ++---
77
target/mips: Avoid tcg_const_tl in gen_r6_ld
72
target/tricore/op_helper.c | 7 ---
78
target/mips: Avoid tcg_const_* throughout
73
target/tricore/translate.c | 14 +----
79
target/ppc: Split out gen_vx_vmul10
74
target/xtensa/translate.c | 25 +++------
80
target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad
75
target/riscv/insn_trans/trans_privileged.c.inc | 10 ++--
81
target/rx: Use tcg_gen_abs_i32
76
target/riscv/insn_trans/trans_rvi.c.inc | 8 ++-
82
target/rx: Use cpu_psw_z as temp in flags computation
77
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
83
target/rx: Avoid tcg_const_i32 when new temp needed
78
34 files changed, 141 insertions(+), 386 deletions(-)
84
target/rx: Avoid tcg_const_i32
85
target/s390x: Avoid tcg_const_i64
86
target/sh4: Avoid tcg_const_i32 for TAS.B
87
target/sh4: Avoid tcg_const_i32
88
tcg/sparc: Avoid tcg_const_tl in gen_edge
89
target/tricore: Split t_n as constant from temp as variable
90
target/tricore: Rename t_off10 and use tcg_constant_i32
91
target/tricore: Use setcondi instead of explicit allocation
92
target/tricore: Drop some temp initialization
93
target/tricore: Avoid tcg_const_i32
94
tcg: Replace tcg_const_i64 in tcg-op.c
95
target/arm: Use rmode >= 0 for need_rmode
96
target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf
97
target/arm: Improve arm_rmode_to_sf
98
target/arm: Consistently use ARMFPRounding during translation
99
target/arm: Create gen_set_rmode, gen_restore_rmode
100
target/arm: Improve trans_BFCI
101
target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
102
target/arm: Avoid tcg_const_* in translate-mve.c
103
target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
104
target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
105
target/arm: Avoid tcg_const_ptr in handle_rev
106
target/m68k: Use tcg_constant_i32 in gen_ea_mode
107
target/ppc: Avoid tcg_const_i64 in do_vcntmb
108
target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
109
target/ppc: Avoid tcg_const_* in xxeval
110
target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
111
target/ppc: Avoid tcg_const_* in fp-impl.c.inc
112
target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
113
target/ppc: Rewrite trans_ADDG6S
114
target/ppc: Fix gen_tlbsx_booke206
115
target/ppc: Avoid tcg_const_* in translate.c
116
target/tricore: Use min/max for saturate
117
tcg: Drop tcg_const_*_vec
118
tcg: Drop tcg_const_*
79
119
120
include/exec/cpu-defs.h | 9 +-
121
include/tcg/tcg-op.h | 4 -
122
include/tcg/tcg-temp-internal.h | 83 +++
123
include/tcg/tcg.h | 64 ---
124
target/alpha/cpu-param.h | 2 -
125
target/arm/cpu-param.h | 2 -
126
target/arm/internals.h | 12 +-
127
target/arm/tcg/translate.h | 17 +
128
target/avr/cpu-param.h | 1 -
129
target/cris/cpu-param.h | 1 -
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target/hexagon/cpu-param.h | 2 -
131
target/hppa/cpu-param.h | 1 -
132
target/i386/cpu-param.h | 1 -
133
target/loongarch/cpu-param.h | 1 -
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target/m68k/cpu-param.h | 1 -
135
target/microblaze/cpu-param.h | 1 -
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target/microblaze/cpu.h | 2 +-
137
target/mips/cpu-param.h | 1 -
138
target/nios2/cpu-param.h | 1 -
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target/openrisc/cpu-param.h | 1 -
140
target/ppc/cpu-param.h | 1 -
141
target/riscv/cpu-param.h | 1 -
142
target/rx/cpu-param.h | 2 -
143
target/s390x/cpu-param.h | 1 -
144
target/sh4/cpu-param.h | 1 -
145
target/sparc/cpu-param.h | 2 -
146
target/tricore/cpu-param.h | 1 -
147
target/xtensa/cpu-param.h | 1 -
148
accel/tcg/plugin-gen.c | 1 +
149
target/arm/tcg/translate-a64.c | 168 +++---
150
target/arm/tcg/translate-mve.c | 56 +-
151
target/arm/tcg/translate-sve.c | 28 +-
152
target/arm/tcg/translate-vfp.c | 26 +-
153
target/arm/tcg/translate.c | 14 +-
154
target/arm/vfp_helper.c | 35 +-
155
target/avr/translate.c | 48 +-
156
target/cris/translate.c | 46 +-
157
target/hppa/translate.c | 35 +-
158
target/i386/tcg/translate.c | 83 +--
159
target/m68k/translate.c | 231 ++++----
160
target/mips/tcg/msa_translate.c | 9 -
161
target/mips/tcg/mxu_translate.c | 55 +-
162
target/mips/tcg/octeon_translate.c | 23 -
163
target/mips/tcg/translate.c | 819 +++++------------------------
164
target/mips/tcg/translate_addr_const.c | 7 -
165
target/mips/tcg/tx79_translate.c | 45 +-
166
target/mips/tcg/vr54xx_translate.c | 4 -
167
target/ppc/translate.c | 148 +++---
168
target/rx/translate.c | 84 ++-
169
target/s390x/tcg/translate.c | 208 +-------
170
target/sh4/translate.c | 35 +-
171
target/sparc/translate.c | 14 +-
172
target/tricore/translate.c | 476 ++++++++---------
173
tcg/tcg-op-gvec.c | 1 +
174
tcg/tcg-op-vec.c | 35 +-
175
tcg/tcg-op.c | 13 +-
176
tcg/tcg.c | 17 +-
177
target/cris/translate_v10.c.inc | 26 +-
178
target/mips/tcg/micromips_translate.c.inc | 12 +-
179
target/mips/tcg/nanomips_translate.c.inc | 143 +----
180
target/ppc/power8-pmu-regs.c.inc | 4 +-
181
target/ppc/translate/fixedpoint-impl.c.inc | 44 +-
182
target/ppc/translate/fp-impl.c.inc | 26 +-
183
target/ppc/translate/vmx-impl.c.inc | 130 ++---
184
target/ppc/translate/vsx-impl.c.inc | 36 +-
185
target/s390x/tcg/translate_vx.c.inc | 143 -----
186
tcg/i386/tcg-target.c.inc | 9 +-
187
67 files changed, 1166 insertions(+), 2388 deletions(-)
188
create mode 100644 include/tcg/tcg-temp-internal.h
diff view generated by jsdifflib
[PULL 01/24] accel/tcg: Handle gdb singlestep in cpu_tb_exec
[PULL v3 73/91] target/arm: Improve trans_BFCI
1
Currently the change in cpu_tb_exec is masked by the debug exception
1
Reorg temporary usage so that we can use tcg_constant_i32.
2
being raised by the translators. But this allows us to remove that code.
2
tcg_gen_deposit_i32 already has a width == 32 special case,
3
so remove the check here.
3
4
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
7
---
6
accel/tcg/cpu-exec.c | 11 +++++++++++
8
target/arm/tcg/translate.c | 14 ++++++--------
7
1 file changed, 11 insertions(+)
9
1 file changed, 6 insertions(+), 8 deletions(-)
8
10
9
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
11
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
10
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
11
--- a/accel/tcg/cpu-exec.c
13
--- a/target/arm/tcg/translate.c
12
+++ b/accel/tcg/cpu-exec.c
14
+++ b/target/arm/tcg/translate.c
13
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
15
@@ -XXX,XX +XXX,XX @@ static bool trans_UBFX(DisasContext *s, arg_UBFX *a)
14
cc->set_pc(cpu, last_tb->pc);
16
15
}
17
static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
18
{
19
- TCGv_i32 tmp;
20
int msb = a->msb, lsb = a->lsb;
21
+ TCGv_i32 t_in, t_rd;
22
int width;
23
24
if (!ENABLE_ARCH_6T2) {
25
@@ -XXX,XX +XXX,XX @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
26
width = msb + 1 - lsb;
27
if (a->rn == 15) {
28
/* BFC */
29
- tmp = tcg_const_i32(0);
30
+ t_in = tcg_constant_i32(0);
31
} else {
32
/* BFI */
33
- tmp = load_reg(s, a->rn);
34
+ t_in = load_reg(s, a->rn);
16
}
35
}
17
+
36
- if (width != 32) {
18
+ /*
37
- TCGv_i32 tmp2 = load_reg(s, a->rd);
19
+ * If gdb single-step, and we haven't raised another exception,
38
- tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width);
20
+ * raise a debug exception. Single-step with another exception
39
- }
21
+ * is handled in cpu_handle_exception.
40
- store_reg(s, a->rd, tmp);
22
+ */
41
+ t_rd = load_reg(s, a->rd);
23
+ if (unlikely(cpu->singlestep_enabled) && cpu->exception_index == -1) {
42
+ tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width);
24
+ cpu->exception_index = EXCP_DEBUG;
43
+ store_reg(s, a->rd, t_rd);
25
+ cpu_loop_exit(cpu);
44
return true;
26
+ }
27
+
28
return last_tb;
29
}
45
}
30
46
31
--
47
--
32
2.25.1
48
2.34.1
33
49
34
50
diff view generated by jsdifflib
[PULL 02/24] target/alpha: Drop checks for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/alpha/translate.c | 13 +++----------
7
1 file changed, 3 insertions(+), 10 deletions(-)
8
9
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/alpha/translate.c
12
+++ b/target/alpha/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
14
tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);
15
/* FALLTHRU */
16
case DISAS_PC_UPDATED:
17
- if (!ctx->base.singlestep_enabled) {
18
- tcg_gen_lookup_and_goto_ptr();
19
- break;
20
- }
21
- /* FALLTHRU */
22
+ tcg_gen_lookup_and_goto_ptr();
23
+ break;
24
case DISAS_PC_UPDATED_NOCHAIN:
25
- if (ctx->base.singlestep_enabled) {
26
- gen_excp_1(EXCP_DEBUG, 0);
27
- } else {
28
- tcg_gen_exit_tb(NULL, 0);
29
- }
30
+ tcg_gen_exit_tb(NULL, 0);
31
break;
32
default:
33
g_assert_not_reached();
34
--
35
2.25.1
36
37
diff view generated by jsdifflib
[PULL 03/24] target/avr: Drop checks for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Tested-by: Michael Rolnik <mrolnik@gmail.com>
4
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
target/avr/translate.c | 19 ++++---------------
9
1 file changed, 4 insertions(+), 15 deletions(-)
10
11
diff --git a/target/avr/translate.c b/target/avr/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/avr/translate.c
14
+++ b/target/avr/translate.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
16
tcg_gen_exit_tb(tb, n);
17
} else {
18
tcg_gen_movi_i32(cpu_pc, dest);
19
- if (ctx->base.singlestep_enabled) {
20
- gen_helper_debug(cpu_env);
21
- } else {
22
- tcg_gen_lookup_and_goto_ptr();
23
- }
24
+ tcg_gen_lookup_and_goto_ptr();
25
}
26
ctx->base.is_jmp = DISAS_NORETURN;
27
}
28
@@ -XXX,XX +XXX,XX @@ static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
29
tcg_gen_movi_tl(cpu_pc, ctx->npc);
30
/* fall through */
31
case DISAS_LOOKUP:
32
- if (!ctx->base.singlestep_enabled) {
33
- tcg_gen_lookup_and_goto_ptr();
34
- break;
35
- }
36
- /* fall through */
37
+ tcg_gen_lookup_and_goto_ptr();
38
+ break;
39
case DISAS_EXIT:
40
- if (ctx->base.singlestep_enabled) {
41
- gen_helper_debug(cpu_env);
42
- } else {
43
- tcg_gen_exit_tb(NULL, 0);
44
- }
45
+ tcg_gen_exit_tb(NULL, 0);
46
break;
47
default:
48
g_assert_not_reached();
49
--
50
2.25.1
51
52
diff view generated by jsdifflib
[PULL 04/24] target/cris: Drop checks for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/cris/translate.c | 16 ----------------
6
1 file changed, 16 deletions(-)
7
8
diff --git a/target/cris/translate.c b/target/cris/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/target/cris/translate.c
11
+++ b/target/cris/translate.c
12
@@ -XXX,XX +XXX,XX @@ static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
13
}
14
}
15
16
- if (unlikely(dc->base.singlestep_enabled)) {
17
- switch (is_jmp) {
18
- case DISAS_TOO_MANY:
19
- case DISAS_UPDATE_NEXT:
20
- tcg_gen_movi_tl(env_pc, npc);
21
- /* fall through */
22
- case DISAS_JUMP:
23
- case DISAS_UPDATE:
24
- t_gen_raise_exception(EXCP_DEBUG);
25
- return;
26
- default:
27
- break;
28
- }
29
- g_assert_not_reached();
30
- }
31
-
32
switch (is_jmp) {
33
case DISAS_TOO_MANY:
34
gen_goto_tb(dc, 0, npc);
35
--
36
2.25.1
37
38
diff view generated by jsdifflib
[PULL 05/24] target/hexagon: Drop checks for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/hexagon/translate.c | 12 ++----------
7
1 file changed, 2 insertions(+), 10 deletions(-)
8
9
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/hexagon/translate.c
12
+++ b/target/hexagon/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void gen_end_tb(DisasContext *ctx)
14
{
15
gen_exec_counters(ctx);
16
tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
17
- if (ctx->base.singlestep_enabled) {
18
- gen_exception_raw(EXCP_DEBUG);
19
- } else {
20
- tcg_gen_exit_tb(NULL, 0);
21
- }
22
+ tcg_gen_exit_tb(NULL, 0);
23
ctx->base.is_jmp = DISAS_NORETURN;
24
}
25
26
@@ -XXX,XX +XXX,XX @@ static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
27
case DISAS_TOO_MANY:
28
gen_exec_counters(ctx);
29
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
30
- if (ctx->base.singlestep_enabled) {
31
- gen_exception_raw(EXCP_DEBUG);
32
- } else {
33
- tcg_gen_exit_tb(NULL, 0);
34
- }
35
+ tcg_gen_exit_tb(NULL, 0);
36
break;
37
case DISAS_NORETURN:
38
break;
39
--
40
2.25.1
41
42
diff view generated by jsdifflib
[PULL 06/24] target/arm: Drop checks for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/arm/translate-a64.c | 10 ++--------
6
target/arm/translate.c | 36 ++++++------------------------------
7
2 files changed, 8 insertions(+), 38 deletions(-)
8
9
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/arm/translate-a64.c
12
+++ b/target/arm/translate-a64.c
13
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
14
gen_a64_set_pc_im(dest);
15
if (s->ss_active) {
16
gen_step_complete_exception(s);
17
- } else if (s->base.singlestep_enabled) {
18
- gen_exception_internal(EXCP_DEBUG);
19
} else {
20
tcg_gen_lookup_and_goto_ptr();
21
s->base.is_jmp = DISAS_NORETURN;
22
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
23
{
24
DisasContext *dc = container_of(dcbase, DisasContext, base);
25
26
- if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) {
27
+ if (unlikely(dc->ss_active)) {
28
/* Note that this means single stepping WFI doesn't halt the CPU.
29
* For conditional branch insns this is harmless unreachable code as
30
* gen_goto_tb() has already handled emitting the debug exception
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
32
/* fall through */
33
case DISAS_EXIT:
34
case DISAS_JUMP:
35
- if (dc->base.singlestep_enabled) {
36
- gen_exception_internal(EXCP_DEBUG);
37
- } else {
38
- gen_step_complete_exception(dc);
39
- }
40
+ gen_step_complete_exception(dc);
41
break;
42
case DISAS_NORETURN:
43
break;
44
diff --git a/target/arm/translate.c b/target/arm/translate.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/translate.c
47
+++ b/target/arm/translate.c
48
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
49
tcg_temp_free_i32(tcg_excp);
50
}
51
52
-static void gen_step_complete_exception(DisasContext *s)
53
+static void gen_singlestep_exception(DisasContext *s)
54
{
55
/* We just completed step of an insn. Move from Active-not-pending
56
* to Active-pending, and then also take the swstep exception.
57
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
58
s->base.is_jmp = DISAS_NORETURN;
59
}
60
61
-static void gen_singlestep_exception(DisasContext *s)
62
-{
63
- /* Generate the right kind of exception for singlestep, which is
64
- * either the architectural singlestep or EXCP_DEBUG for QEMU's
65
- * gdb singlestepping.
66
- */
67
- if (s->ss_active) {
68
- gen_step_complete_exception(s);
69
- } else {
70
- gen_exception_internal(EXCP_DEBUG);
71
- }
72
-}
73
-
74
-static inline bool is_singlestepping(DisasContext *s)
75
-{
76
- /* Return true if we are singlestepping either because of
77
- * architectural singlestep or QEMU gdbstub singlestep. This does
78
- * not include the command line '-singlestep' mode which is rather
79
- * misnamed as it only means "one instruction per TB" and doesn't
80
- * affect the code we generate.
81
- */
82
- return s->base.singlestep_enabled || s->ss_active;
83
-}
84
-
85
void clear_eci_state(DisasContext *s)
86
{
87
/*
88
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)
89
/* Is the new PC value in the magic range indicating exception return? */
90
tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);
91
/* No: end the TB as we would for a DISAS_JMP */
92
- if (is_singlestepping(s)) {
93
+ if (s->ss_active) {
94
gen_singlestep_exception(s);
95
} else {
96
tcg_gen_exit_tb(NULL, 0);
97
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
98
/* Jump, specifying which TB number to use if we gen_goto_tb() */
99
static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
100
{
101
- if (unlikely(is_singlestepping(s))) {
102
+ if (unlikely(s->ss_active)) {
103
/* An indirect jump so that we still trigger the debug exception. */
104
gen_set_pc_im(s, dest);
105
s->base.is_jmp = DISAS_JUMP;
106
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
107
dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK;
108
109
/* If architectural single step active, limit to 1. */
110
- if (is_singlestepping(dc)) {
111
+ if (dc->ss_active) {
112
dc->base.max_insns = 1;
113
}
114
115
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
116
* insn codepath itself.
117
*/
118
gen_bx_excret_final_code(dc);
119
- } else if (unlikely(is_singlestepping(dc))) {
120
+ } else if (unlikely(dc->ss_active)) {
121
/* Unconditional and "condition passed" instruction codepath. */
122
switch (dc->base.is_jmp) {
123
case DISAS_SWI:
124
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
125
/* "Condition failed" instruction codepath for the branch/trap insn */
126
gen_set_label(dc->condlabel);
127
gen_set_condexec(dc);
128
- if (unlikely(is_singlestepping(dc))) {
129
+ if (unlikely(dc->ss_active)) {
130
gen_set_pc_im(dc, dc->base.pc_next);
131
gen_singlestep_exception(dc);
132
} else {
133
--
134
2.25.1
135
136
diff view generated by jsdifflib
[PULL 07/24] target/hppa: Drop checks for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/hppa/translate.c | 17 ++++-------------
7
1 file changed, 4 insertions(+), 13 deletions(-)
8
9
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/hppa/translate.c
12
+++ b/target/hppa/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int which,
14
} else {
15
copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b);
16
copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var);
17
- if (ctx->base.singlestep_enabled) {
18
- gen_excp_1(EXCP_DEBUG);
19
- } else {
20
- tcg_gen_lookup_and_goto_ptr();
21
- }
22
+ tcg_gen_lookup_and_goto_ptr();
23
}
24
}
25
26
@@ -XXX,XX +XXX,XX @@ static bool do_rfi(DisasContext *ctx, bool rfi_r)
27
gen_helper_rfi(cpu_env);
28
}
29
/* Exit the TB to recognize new interrupts. */
30
- if (ctx->base.singlestep_enabled) {
31
- gen_excp_1(EXCP_DEBUG);
32
- } else {
33
- tcg_gen_exit_tb(NULL, 0);
34
- }
35
+ tcg_gen_exit_tb(NULL, 0);
36
ctx->base.is_jmp = DISAS_NORETURN;
37
38
return nullify_end(ctx);
39
@@ -XXX,XX +XXX,XX @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
40
nullify_save(ctx);
41
/* FALLTHRU */
42
case DISAS_IAQ_N_UPDATED:
43
- if (ctx->base.singlestep_enabled) {
44
- gen_excp_1(EXCP_DEBUG);
45
- } else if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
46
+ if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
47
tcg_gen_lookup_and_goto_ptr();
48
+ break;
49
}
50
/* FALLTHRU */
51
case DISAS_EXIT:
52
--
53
2.25.1
54
55
diff view generated by jsdifflib
[PULL 08/24] target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt
Deleted patch
1
We were using singlestep_enabled as a proxy for whether
2
translator_use_goto_tb would always return false.
3
1
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/i386/tcg/translate.c | 5 +++--
7
1 file changed, 3 insertions(+), 2 deletions(-)
8
9
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/i386/tcg/translate.c
12
+++ b/target/i386/tcg/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
14
DisasContext *dc = container_of(dcbase, DisasContext, base);
15
CPUX86State *env = cpu->env_ptr;
16
uint32_t flags = dc->base.tb->flags;
17
+ uint32_t cflags = tb_cflags(dc->base.tb);
18
int cpl = (flags >> HF_CPL_SHIFT) & 3;
19
int iopl = (flags >> IOPL_SHIFT) & 3;
20
21
@@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
22
dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
23
dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
24
dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
25
- dc->jmp_opt = !(dc->base.singlestep_enabled ||
26
+ dc->jmp_opt = !((cflags & CF_NO_GOTO_TB) ||
27
(flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)));
28
/*
29
* If jmp_opt, we want to handle each string instruction individually.
30
* For icount also disable repz optimization so that each iteration
31
* is accounted separately.
32
*/
33
- dc->repz_opt = !dc->jmp_opt && !(tb_cflags(dc->base.tb) & CF_USE_ICOUNT);
34
+ dc->repz_opt = !dc->jmp_opt && !(cflags & CF_USE_ICOUNT);
35
36
dc->T0 = tcg_temp_new();
37
dc->T1 = tcg_temp_new();
38
--
39
2.25.1
40
41
diff view generated by jsdifflib
[PULL 09/24] target/i386: Drop check for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/i386/helper.h | 1 -
6
target/i386/tcg/misc_helper.c | 8 --------
7
target/i386/tcg/translate.c | 4 +---
8
3 files changed, 1 insertion(+), 12 deletions(-)
9
10
diff --git a/target/i386/helper.h b/target/i386/helper.h
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/i386/helper.h
13
+++ b/target/i386/helper.h
14
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(syscall, void, env, int)
15
DEF_HELPER_2(sysret, void, env, int)
16
#endif
17
DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int)
18
-DEF_HELPER_FLAGS_1(debug, TCG_CALL_NO_WG, noreturn, env)
19
DEF_HELPER_1(reset_rf, void, env)
20
DEF_HELPER_FLAGS_3(raise_interrupt, TCG_CALL_NO_WG, noreturn, env, int, int)
21
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, int)
22
diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/i386/tcg/misc_helper.c
25
+++ b/target/i386/tcg/misc_helper.c
26
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend)
27
do_pause(env);
28
}
29
30
-void QEMU_NORETURN helper_debug(CPUX86State *env)
31
-{
32
- CPUState *cs = env_cpu(env);
33
-
34
- cs->exception_index = EXCP_DEBUG;
35
- cpu_loop_exit(cs);
36
-}
37
-
38
uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx)
39
{
40
if ((env->cr[4] & CR4_PKE_MASK) == 0) {
41
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/i386/tcg/translate.c
44
+++ b/target/i386/tcg/translate.c
45
@@ -XXX,XX +XXX,XX @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr)
46
if (s->base.tb->flags & HF_RF_MASK) {
47
gen_helper_reset_rf(cpu_env);
48
}
49
- if (s->base.singlestep_enabled) {
50
- gen_helper_debug(cpu_env);
51
- } else if (recheck_tf) {
52
+ if (recheck_tf) {
53
gen_helper_rechecking_single_step(cpu_env);
54
tcg_gen_exit_tb(NULL, 0);
55
} else if (s->flags & HF_TF_MASK) {
56
--
57
2.25.1
58
59
diff view generated by jsdifflib
[PULL 10/24] target/m68k: Drop checks for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Acked-by: Laurent Vivier <laurent@vivier.eu>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/m68k/translate.c | 44 +++++++++--------------------------------
7
1 file changed, 9 insertions(+), 35 deletions(-)
8
9
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/m68k/translate.c
12
+++ b/target/m68k/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void do_writebacks(DisasContext *s)
14
}
15
}
16
17
-static bool is_singlestepping(DisasContext *s)
18
-{
19
- /*
20
- * Return true if we are singlestepping either because of
21
- * architectural singlestep or QEMU gdbstub singlestep. This does
22
- * not include the command line '-singlestep' mode which is rather
23
- * misnamed as it only means "one instruction per TB" and doesn't
24
- * affect the code we generate.
25
- */
26
- return s->base.singlestep_enabled || s->ss_active;
27
-}
28
-
29
/* is_jmp field values */
30
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
31
#define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
32
@@ -XXX,XX +XXX,XX @@ static void gen_exception(DisasContext *s, uint32_t dest, int nr)
33
s->base.is_jmp = DISAS_NORETURN;
34
}
35
36
-static void gen_singlestep_exception(DisasContext *s)
37
-{
38
- /*
39
- * Generate the right kind of exception for singlestep, which is
40
- * either the architectural singlestep or EXCP_DEBUG for QEMU's
41
- * gdb singlestepping.
42
- */
43
- if (s->ss_active) {
44
- gen_raise_exception(EXCP_TRACE);
45
- } else {
46
- gen_raise_exception(EXCP_DEBUG);
47
- }
48
-}
49
-
50
static inline void gen_addr_fault(DisasContext *s)
51
{
52
gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
53
@@ -XXX,XX +XXX,XX @@ static void gen_exit_tb(DisasContext *s)
54
/* Generate a jump to an immediate address. */
55
static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
56
{
57
- if (unlikely(is_singlestepping(s))) {
58
+ if (unlikely(s->ss_active)) {
59
update_cc_op(s);
60
tcg_gen_movi_i32(QREG_PC, dest);
61
- gen_singlestep_exception(s);
62
+ gen_raise_exception(EXCP_TRACE);
63
} else if (translator_use_goto_tb(&s->base, dest)) {
64
tcg_gen_goto_tb(n);
65
tcg_gen_movi_i32(QREG_PC, dest);
66
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
67
68
dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS);
69
/* If architectural single step active, limit to 1 */
70
- if (is_singlestepping(dc)) {
71
+ if (dc->ss_active) {
72
dc->base.max_insns = 1;
73
}
74
}
75
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
76
break;
77
case DISAS_TOO_MANY:
78
update_cc_op(dc);
79
- if (is_singlestepping(dc)) {
80
+ if (dc->ss_active) {
81
tcg_gen_movi_i32(QREG_PC, dc->pc);
82
- gen_singlestep_exception(dc);
83
+ gen_raise_exception(EXCP_TRACE);
84
} else {
85
gen_jmp_tb(dc, 0, dc->pc);
86
}
87
break;
88
case DISAS_JUMP:
89
/* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
90
- if (is_singlestepping(dc)) {
91
- gen_singlestep_exception(dc);
92
+ if (dc->ss_active) {
93
+ gen_raise_exception(EXCP_TRACE);
94
} else {
95
tcg_gen_lookup_and_goto_ptr();
96
}
97
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
98
* We updated CC_OP and PC in gen_exit_tb, but also modified
99
* other state that may require returning to the main loop.
100
*/
101
- if (is_singlestepping(dc)) {
102
- gen_singlestep_exception(dc);
103
+ if (dc->ss_active) {
104
+ gen_raise_exception(EXCP_TRACE);
105
} else {
106
tcg_gen_exit_tb(NULL, 0);
107
}
108
--
109
2.25.1
110
111
diff view generated by jsdifflib
[PULL 11/24] target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP
Deleted patch
1
We were using singlestep_enabled as a proxy for whether
2
translator_use_goto_tb would always return false.
3
1
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/microblaze/translate.c | 4 ++--
7
1 file changed, 2 insertions(+), 2 deletions(-)
8
9
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/microblaze/translate.c
12
+++ b/target/microblaze/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
14
break;
15
16
case DISAS_JUMP:
17
- if (dc->jmp_dest != -1 && !cs->singlestep_enabled) {
18
+ if (dc->jmp_dest != -1 && !(tb_cflags(dc->base.tb) & CF_NO_GOTO_TB)) {
19
/* Direct jump. */
20
tcg_gen_discard_i32(cpu_btarget);
21
22
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
23
return;
24
}
25
26
- /* Indirect jump (or direct jump w/ singlestep) */
27
+ /* Indirect jump (or direct jump w/ goto_tb disabled) */
28
tcg_gen_mov_i32(cpu_pc, cpu_btarget);
29
tcg_gen_discard_i32(cpu_btarget);
30
31
--
32
2.25.1
33
34
diff view generated by jsdifflib
[PULL 12/24] target/microblaze: Drop checks for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/microblaze/translate.c | 14 ++------------
6
1 file changed, 2 insertions(+), 12 deletions(-)
7
8
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/target/microblaze/translate.c
11
+++ b/target/microblaze/translate.c
12
@@ -XXX,XX +XXX,XX @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
13
14
static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
15
{
16
- if (dc->base.singlestep_enabled) {
17
- TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
18
- tcg_gen_movi_i32(cpu_pc, dest);
19
- gen_helper_raise_exception(cpu_env, tmp);
20
- tcg_temp_free_i32(tmp);
21
- } else if (translator_use_goto_tb(&dc->base, dest)) {
22
+ if (translator_use_goto_tb(&dc->base, dest)) {
23
tcg_gen_goto_tb(n);
24
tcg_gen_movi_i32(cpu_pc, dest);
25
tcg_gen_exit_tb(dc->base.tb, n);
26
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
27
/* Indirect jump (or direct jump w/ goto_tb disabled) */
28
tcg_gen_mov_i32(cpu_pc, cpu_btarget);
29
tcg_gen_discard_i32(cpu_btarget);
30
-
31
- if (unlikely(cs->singlestep_enabled)) {
32
- gen_raise_exception(dc, EXCP_DEBUG);
33
- } else {
34
- tcg_gen_lookup_and_goto_ptr();
35
- }
36
+ tcg_gen_lookup_and_goto_ptr();
37
return;
38
39
default:
40
--
41
2.25.1
42
43
diff view generated by jsdifflib
[PULL 13/24] target/mips: Fix single stepping
Deleted patch
1
As per an ancient comment in mips_tr_translate_insn about the
2
expectations of gdb, when restarting the insn in a delay slot
3
we also re-execute the branch. Which means that we are
4
expected to execute two insns in this case.
5
1
6
This has been broken since 8b86d6d2580, where we forced max_insns
7
to 1 while single-stepping. This resulted in an exit from the
8
translator loop after the branch but before the delay slot is
9
translated.
10
11
Increase the max_insns to 2 for this case. In addition, bypass
12
the end-of-page check, for when the branch itself ends the page.
13
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
---
17
target/mips/tcg/translate.c | 25 ++++++++++++++++---------
18
1 file changed, 16 insertions(+), 9 deletions(-)
19
20
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/mips/tcg/translate.c
23
+++ b/target/mips/tcg/translate.c
24
@@ -XXX,XX +XXX,XX @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
25
ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
26
INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
27
28
+ /*
29
+ * Execute a branch and its delay slot as a single instruction.
30
+ * This is what GDB expects and is consistent with what the
31
+ * hardware does (e.g. if a delay slot instruction faults, the
32
+ * reported PC is the PC of the branch).
33
+ */
34
+ if (ctx->base.singlestep_enabled && (ctx->hflags & MIPS_HFLAG_BMASK)) {
35
+ ctx->base.max_insns = 2;
36
+ }
37
+
38
LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
39
ctx->hflags);
40
}
41
@@ -XXX,XX +XXX,XX @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
42
if (ctx->base.is_jmp != DISAS_NEXT) {
43
return;
44
}
45
+
46
/*
47
- * Execute a branch and its delay slot as a single instruction.
48
- * This is what GDB expects and is consistent with what the
49
- * hardware does (e.g. if a delay slot instruction faults, the
50
- * reported PC is the PC of the branch).
51
+ * End the TB on (most) page crossings.
52
+ * See mips_tr_init_disas_context about single-stepping a branch
53
+ * together with its delay slot.
54
*/
55
- if (ctx->base.singlestep_enabled &&
56
- (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
57
- ctx->base.is_jmp = DISAS_TOO_MANY;
58
- }
59
- if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE) {
60
+ if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE
61
+ && !ctx->base.singlestep_enabled) {
62
ctx->base.is_jmp = DISAS_TOO_MANY;
63
}
64
}
65
--
66
2.25.1
67
68
diff view generated by jsdifflib
[PULL 14/24] target/mips: Drop exit checks for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/mips/tcg/translate.c | 50 +++++++++++++------------------------
7
1 file changed, 18 insertions(+), 32 deletions(-)
8
9
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/mips/tcg/translate.c
12
+++ b/target/mips/tcg/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
14
tcg_gen_exit_tb(ctx->base.tb, n);
15
} else {
16
gen_save_pc(dest);
17
- if (ctx->base.singlestep_enabled) {
18
- save_cpu_state(ctx, 0);
19
- gen_helper_raise_exception_debug(cpu_env);
20
- } else {
21
- tcg_gen_lookup_and_goto_ptr();
22
- }
23
+ tcg_gen_lookup_and_goto_ptr();
24
}
25
}
26
27
@@ -XXX,XX +XXX,XX @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
28
} else {
29
tcg_gen_mov_tl(cpu_PC, btarget);
30
}
31
- if (ctx->base.singlestep_enabled) {
32
- save_cpu_state(ctx, 0);
33
- gen_helper_raise_exception_debug(cpu_env);
34
- }
35
tcg_gen_lookup_and_goto_ptr();
36
break;
37
default:
38
@@ -XXX,XX +XXX,XX @@ static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
39
{
40
DisasContext *ctx = container_of(dcbase, DisasContext, base);
41
42
- if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) {
43
- save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXIT);
44
- gen_helper_raise_exception_debug(cpu_env);
45
- } else {
46
- switch (ctx->base.is_jmp) {
47
- case DISAS_STOP:
48
- gen_save_pc(ctx->base.pc_next);
49
- tcg_gen_lookup_and_goto_ptr();
50
- break;
51
- case DISAS_NEXT:
52
- case DISAS_TOO_MANY:
53
- save_cpu_state(ctx, 0);
54
- gen_goto_tb(ctx, 0, ctx->base.pc_next);
55
- break;
56
- case DISAS_EXIT:
57
- tcg_gen_exit_tb(NULL, 0);
58
- break;
59
- case DISAS_NORETURN:
60
- break;
61
- default:
62
- g_assert_not_reached();
63
- }
64
+ switch (ctx->base.is_jmp) {
65
+ case DISAS_STOP:
66
+ gen_save_pc(ctx->base.pc_next);
67
+ tcg_gen_lookup_and_goto_ptr();
68
+ break;
69
+ case DISAS_NEXT:
70
+ case DISAS_TOO_MANY:
71
+ save_cpu_state(ctx, 0);
72
+ gen_goto_tb(ctx, 0, ctx->base.pc_next);
73
+ break;
74
+ case DISAS_EXIT:
75
+ tcg_gen_exit_tb(NULL, 0);
76
+ break;
77
+ case DISAS_NORETURN:
78
+ break;
79
+ default:
80
+ g_assert_not_reached();
81
}
82
}
83
84
--
85
2.25.1
86
87
diff view generated by jsdifflib
[PULL 15/24] target/openrisc: Drop checks for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/openrisc/translate.c | 18 +++---------------
7
1 file changed, 3 insertions(+), 15 deletions(-)
8
9
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/openrisc/translate.c
12
+++ b/target/openrisc/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
14
/* The jump destination is indirect/computed; use jmp_pc. */
15
tcg_gen_mov_tl(cpu_pc, jmp_pc);
16
tcg_gen_discard_tl(jmp_pc);
17
- if (unlikely(dc->base.singlestep_enabled)) {
18
- gen_exception(dc, EXCP_DEBUG);
19
- } else {
20
- tcg_gen_lookup_and_goto_ptr();
21
- }
22
+ tcg_gen_lookup_and_goto_ptr();
23
break;
24
}
25
/* The jump destination is direct; use jmp_pc_imm.
26
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
27
break;
28
}
29
tcg_gen_movi_tl(cpu_pc, jmp_dest);
30
- if (unlikely(dc->base.singlestep_enabled)) {
31
- gen_exception(dc, EXCP_DEBUG);
32
- } else {
33
- tcg_gen_lookup_and_goto_ptr();
34
- }
35
+ tcg_gen_lookup_and_goto_ptr();
36
break;
37
38
case DISAS_EXIT:
39
- if (unlikely(dc->base.singlestep_enabled)) {
40
- gen_exception(dc, EXCP_DEBUG);
41
- } else {
42
- tcg_gen_exit_tb(NULL, 0);
43
- }
44
+ tcg_gen_exit_tb(NULL, 0);
45
break;
46
default:
47
g_assert_not_reached();
48
--
49
2.25.1
50
51
diff view generated by jsdifflib
[PULL 16/24] target/ppc: Drop exit checks for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
Reuse gen_debug_exception to handle architectural debug exceptions.
3
1
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/ppc/translate.c | 38 ++++++++------------------------------
7
1 file changed, 8 insertions(+), 30 deletions(-)
8
9
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/ppc/translate.c
12
+++ b/target/ppc/translate.c
13
@@ -XXX,XX +XXX,XX @@
14
15
#define CPU_SINGLE_STEP 0x1
16
#define CPU_BRANCH_STEP 0x2
17
-#define GDBSTUB_SINGLE_STEP 0x4
18
19
/* Include definitions for instructions classes and implementations flags */
20
/* #define PPC_DEBUG_DISAS */
21
@@ -XXX,XX +XXX,XX @@ static uint32_t gen_prep_dbgex(DisasContext *ctx)
22
23
static void gen_debug_exception(DisasContext *ctx)
24
{
25
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
26
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
27
ctx->base.is_jmp = DISAS_NORETURN;
28
}
29
30
@@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
31
32
static void gen_lookup_and_goto_ptr(DisasContext *ctx)
33
{
34
- int sse = ctx->singlestep_enabled;
35
- if (unlikely(sse)) {
36
- if (sse & GDBSTUB_SINGLE_STEP) {
37
- gen_debug_exception(ctx);
38
- } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
39
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
40
- } else {
41
- tcg_gen_exit_tb(NULL, 0);
42
- }
43
+ if (unlikely(ctx->singlestep_enabled)) {
44
+ gen_debug_exception(ctx);
45
} else {
46
tcg_gen_lookup_and_goto_ptr();
47
}
48
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
49
ctx->singlestep_enabled = 0;
50
if ((hflags >> HFLAGS_SE) & 1) {
51
ctx->singlestep_enabled |= CPU_SINGLE_STEP;
52
+ ctx->base.max_insns = 1;
53
}
54
if ((hflags >> HFLAGS_BE) & 1) {
55
ctx->singlestep_enabled |= CPU_BRANCH_STEP;
56
}
57
- if (unlikely(ctx->base.singlestep_enabled)) {
58
- ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
59
- }
60
-
61
- if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) {
62
- ctx->base.max_insns = 1;
63
- }
64
}
65
66
static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
67
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
68
DisasContext *ctx = container_of(dcbase, DisasContext, base);
69
DisasJumpType is_jmp = ctx->base.is_jmp;
70
target_ulong nip = ctx->base.pc_next;
71
- int sse;
72
73
if (is_jmp == DISAS_NORETURN) {
74
/* We have already exited the TB. */
75
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
76
}
77
78
/* Honor single stepping. */
79
- sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP);
80
- if (unlikely(sse)) {
81
+ if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)
82
+ && (nip <= 0x100 || nip > 0xf00)) {
83
switch (is_jmp) {
84
case DISAS_TOO_MANY:
85
case DISAS_EXIT_UPDATE:
86
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
87
g_assert_not_reached();
88
}
89
90
- if (sse & GDBSTUB_SINGLE_STEP) {
91
- gen_debug_exception(ctx);
92
- return;
93
- }
94
- /* else CPU_SINGLE_STEP... */
95
- if (nip <= 0x100 || nip > 0xf00) {
96
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
97
- return;
98
- }
99
+ gen_debug_exception(ctx);
100
+ return;
101
}
102
103
switch (is_jmp) {
104
--
105
2.25.1
106
107
diff view generated by jsdifflib
[PULL 17/24] target/riscv: Remove dead code after exception
Deleted patch
1
We have already set DISAS_NORETURN in generate_exception,
2
which makes the exit_tb unreachable.
3
1
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
target/riscv/insn_trans/trans_privileged.c.inc | 6 +-----
8
1 file changed, 1 insertion(+), 5 deletions(-)
9
10
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/riscv/insn_trans/trans_privileged.c.inc
13
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
14
@@ -XXX,XX +XXX,XX @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
15
{
16
/* always generates U-level ECALL, fixed in do_interrupt handler */
17
generate_exception(ctx, RISCV_EXCP_U_ECALL);
18
- exit_tb(ctx); /* no chaining */
19
- ctx->base.is_jmp = DISAS_NORETURN;
20
return true;
21
}
22
23
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
24
post = opcode_at(&ctx->base, post_addr);
25
}
26
27
- if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
28
+ if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
29
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
30
} else {
31
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
32
}
33
- exit_tb(ctx); /* no chaining */
34
- ctx->base.is_jmp = DISAS_NORETURN;
35
return true;
36
}
37
38
--
39
2.25.1
40
41
diff view generated by jsdifflib
[PULL 18/24] target/riscv: Remove exit_tb and lookup_and_goto_ptr
Deleted patch
1
GDB single-stepping is now handled generically, which means
2
we don't need to do anything in the wrappers.
3
1
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
target/riscv/translate.c | 27 +------------------
8
.../riscv/insn_trans/trans_privileged.c.inc | 4 +--
9
target/riscv/insn_trans/trans_rvi.c.inc | 8 +++---
10
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
11
4 files changed, 7 insertions(+), 34 deletions(-)
12
13
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/translate.c
16
+++ b/target/riscv/translate.c
17
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
18
ctx->base.is_jmp = DISAS_NORETURN;
19
}
20
21
-static void gen_exception_debug(void)
22
-{
23
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
24
-}
25
-
26
-/* Wrapper around tcg_gen_exit_tb that handles single stepping */
27
-static void exit_tb(DisasContext *ctx)
28
-{
29
- if (ctx->base.singlestep_enabled) {
30
- gen_exception_debug();
31
- } else {
32
- tcg_gen_exit_tb(NULL, 0);
33
- }
34
-}
35
-
36
-/* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
37
-static void lookup_and_goto_ptr(DisasContext *ctx)
38
-{
39
- if (ctx->base.singlestep_enabled) {
40
- gen_exception_debug();
41
- } else {
42
- tcg_gen_lookup_and_goto_ptr();
43
- }
44
-}
45
-
46
static void gen_exception_illegal(DisasContext *ctx)
47
{
48
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
49
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
50
tcg_gen_exit_tb(ctx->base.tb, n);
51
} else {
52
tcg_gen_movi_tl(cpu_pc, dest);
53
- lookup_and_goto_ptr(ctx);
54
+ tcg_gen_lookup_and_goto_ptr();
55
}
56
}
57
58
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/riscv/insn_trans/trans_privileged.c.inc
61
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
62
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
63
64
if (has_ext(ctx, RVS)) {
65
gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
66
- exit_tb(ctx); /* no chaining */
67
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
68
ctx->base.is_jmp = DISAS_NORETURN;
69
} else {
70
return false;
71
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
72
#ifndef CONFIG_USER_ONLY
73
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
74
gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
75
- exit_tb(ctx); /* no chaining */
76
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
77
ctx->base.is_jmp = DISAS_NORETURN;
78
return true;
79
#else
80
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/riscv/insn_trans/trans_rvi.c.inc
83
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
84
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
85
if (a->rd != 0) {
86
tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
87
}
88
-
89
- /* No chaining with JALR. */
90
- lookup_and_goto_ptr(ctx);
91
+ tcg_gen_lookup_and_goto_ptr();
92
93
if (misaligned) {
94
gen_set_label(misaligned);
95
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
96
* however we need to end the translation block
97
*/
98
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
99
- exit_tb(ctx);
100
+ tcg_gen_exit_tb(NULL, 0);
101
ctx->base.is_jmp = DISAS_NORETURN;
102
return true;
103
}
104
@@ -XXX,XX +XXX,XX @@ static bool do_csr_post(DisasContext *ctx)
105
{
106
/* We may have changed important cpu state -- exit to main loop. */
107
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
108
- exit_tb(ctx);
109
+ tcg_gen_exit_tb(NULL, 0);
110
ctx->base.is_jmp = DISAS_NORETURN;
111
return true;
112
}
113
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
114
index XXXXXXX..XXXXXXX 100644
115
--- a/target/riscv/insn_trans/trans_rvv.c.inc
116
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
117
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
118
gen_set_gpr(ctx, a->rd, dst);
119
120
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
121
- lookup_and_goto_ptr(ctx);
122
+ tcg_gen_lookup_and_goto_ptr();
123
ctx->base.is_jmp = DISAS_NORETURN;
124
return true;
125
}
126
--
127
2.25.1
128
129
diff view generated by jsdifflib
[PULL 19/24] target/rx: Drop checks for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/rx/helper.h | 1 -
7
target/rx/op_helper.c | 8 --------
8
target/rx/translate.c | 12 ++----------
9
3 files changed, 2 insertions(+), 19 deletions(-)
10
11
diff --git a/target/rx/helper.h b/target/rx/helper.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/rx/helper.h
14
+++ b/target/rx/helper.h
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
16
DEF_HELPER_1(raise_access_fault, noreturn, env)
17
DEF_HELPER_1(raise_privilege_violation, noreturn, env)
18
DEF_HELPER_1(wait, noreturn, env)
19
-DEF_HELPER_1(debug, noreturn, env)
20
DEF_HELPER_2(rxint, noreturn, env, i32)
21
DEF_HELPER_1(rxbrk, noreturn, env)
22
DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32)
23
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/rx/op_helper.c
26
+++ b/target/rx/op_helper.c
27
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_wait(CPURXState *env)
28
raise_exception(env, EXCP_HLT, 0);
29
}
30
31
-void QEMU_NORETURN helper_debug(CPURXState *env)
32
-{
33
- CPUState *cs = env_cpu(env);
34
-
35
- cs->exception_index = EXCP_DEBUG;
36
- cpu_loop_exit(cs);
37
-}
38
-
39
void QEMU_NORETURN helper_rxint(CPURXState *env, uint32_t vec)
40
{
41
raise_exception(env, 0x100 + vec, 0);
42
diff --git a/target/rx/translate.c b/target/rx/translate.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/rx/translate.c
45
+++ b/target/rx/translate.c
46
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
47
tcg_gen_exit_tb(dc->base.tb, n);
48
} else {
49
tcg_gen_movi_i32(cpu_pc, dest);
50
- if (dc->base.singlestep_enabled) {
51
- gen_helper_debug(cpu_env);
52
- } else {
53
- tcg_gen_lookup_and_goto_ptr();
54
- }
55
+ tcg_gen_lookup_and_goto_ptr();
56
}
57
dc->base.is_jmp = DISAS_NORETURN;
58
}
59
@@ -XXX,XX +XXX,XX @@ static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
60
gen_goto_tb(ctx, 0, dcbase->pc_next);
61
break;
62
case DISAS_JUMP:
63
- if (ctx->base.singlestep_enabled) {
64
- gen_helper_debug(cpu_env);
65
- } else {
66
- tcg_gen_lookup_and_goto_ptr();
67
- }
68
+ tcg_gen_lookup_and_goto_ptr();
69
break;
70
case DISAS_UPDATE:
71
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
72
--
73
2.25.1
74
75
diff view generated by jsdifflib
[PULL 20/24] target/s390x: Drop check for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/s390x/tcg/translate.c | 8 ++------
6
1 file changed, 2 insertions(+), 6 deletions(-)
7
8
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/target/s390x/tcg/translate.c
11
+++ b/target/s390x/tcg/translate.c
12
@@ -XXX,XX +XXX,XX @@ struct DisasContext {
13
uint64_t pc_tmp;
14
uint32_t ilen;
15
enum cc_op cc_op;
16
- bool do_debug;
17
};
18
19
/* Information carried about a condition to be evaluated. */
20
@@ -XXX,XX +XXX,XX @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
21
22
dc->cc_op = CC_OP_DYNAMIC;
23
dc->ex_value = dc->base.tb->cs_base;
24
- dc->do_debug = dc->base.singlestep_enabled;
25
}
26
27
static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs)
28
@@ -XXX,XX +XXX,XX @@ static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
29
/* FALLTHRU */
30
case DISAS_PC_CC_UPDATED:
31
/* Exit the TB, either by raising a debug exception or by return. */
32
- if (dc->do_debug) {
33
- gen_exception(EXCP_DEBUG);
34
- } else if ((dc->base.tb->flags & FLAG_MASK_PER) ||
35
- dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
36
+ if ((dc->base.tb->flags & FLAG_MASK_PER) ||
37
+ dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
38
tcg_gen_exit_tb(NULL, 0);
39
} else {
40
tcg_gen_lookup_and_goto_ptr();
41
--
42
2.25.1
43
44
diff view generated by jsdifflib
[PULL 21/24] target/sh4: Drop check for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/sh4/helper.h | 1 -
7
target/sh4/op_helper.c | 5 -----
8
target/sh4/translate.c | 14 +++-----------
9
3 files changed, 3 insertions(+), 17 deletions(-)
10
11
diff --git a/target/sh4/helper.h b/target/sh4/helper.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/sh4/helper.h
14
+++ b/target/sh4/helper.h
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
16
DEF_HELPER_1(raise_slot_illegal_instruction, noreturn, env)
17
DEF_HELPER_1(raise_fpu_disable, noreturn, env)
18
DEF_HELPER_1(raise_slot_fpu_disable, noreturn, env)
19
-DEF_HELPER_1(debug, noreturn, env)
20
DEF_HELPER_1(sleep, noreturn, env)
21
DEF_HELPER_2(trapa, noreturn, env, i32)
22
DEF_HELPER_1(exclusive, noreturn, env)
23
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/sh4/op_helper.c
26
+++ b/target/sh4/op_helper.c
27
@@ -XXX,XX +XXX,XX @@ void helper_raise_slot_fpu_disable(CPUSH4State *env)
28
raise_exception(env, 0x820, 0);
29
}
30
31
-void helper_debug(CPUSH4State *env)
32
-{
33
- raise_exception(env, EXCP_DEBUG, 0);
34
-}
35
-
36
void helper_sleep(CPUSH4State *env)
37
{
38
CPUState *cs = env_cpu(env);
39
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/sh4/translate.c
42
+++ b/target/sh4/translate.c
43
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
44
tcg_gen_exit_tb(ctx->base.tb, n);
45
} else {
46
tcg_gen_movi_i32(cpu_pc, dest);
47
- if (ctx->base.singlestep_enabled) {
48
- gen_helper_debug(cpu_env);
49
- } else if (use_exit_tb(ctx)) {
50
+ if (use_exit_tb(ctx)) {
51
tcg_gen_exit_tb(NULL, 0);
52
} else {
53
tcg_gen_lookup_and_goto_ptr();
54
@@ -XXX,XX +XXX,XX @@ static void gen_jump(DisasContext * ctx)
55
     delayed jump as immediate jump are conditinal jumps */
56
    tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
57
tcg_gen_discard_i32(cpu_delayed_pc);
58
- if (ctx->base.singlestep_enabled) {
59
- gen_helper_debug(cpu_env);
60
- } else if (use_exit_tb(ctx)) {
61
+ if (use_exit_tb(ctx)) {
62
tcg_gen_exit_tb(NULL, 0);
63
} else {
64
tcg_gen_lookup_and_goto_ptr();
65
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
66
switch (ctx->base.is_jmp) {
67
case DISAS_STOP:
68
gen_save_cpu_state(ctx, true);
69
- if (ctx->base.singlestep_enabled) {
70
- gen_helper_debug(cpu_env);
71
- } else {
72
- tcg_gen_exit_tb(NULL, 0);
73
- }
74
+ tcg_gen_exit_tb(NULL, 0);
75
break;
76
case DISAS_NEXT:
77
case DISAS_TOO_MANY:
78
--
79
2.25.1
80
81
diff view generated by jsdifflib
[PULL 22/24] target/tricore: Drop check for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/tricore/helper.h | 1 -
7
target/tricore/op_helper.c | 7 -------
8
target/tricore/translate.c | 14 +-------------
9
3 files changed, 1 insertion(+), 21 deletions(-)
10
11
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/tricore/helper.h
14
+++ b/target/tricore/helper.h
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(psw_write, void, env, i32)
16
DEF_HELPER_1(psw_read, i32, env)
17
/* Exceptions */
18
DEF_HELPER_3(raise_exception_sync, noreturn, env, i32, i32)
19
-DEF_HELPER_2(qemu_excp, noreturn, env, i32)
20
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/tricore/op_helper.c
23
+++ b/target/tricore/op_helper.c
24
@@ -XXX,XX +XXX,XX @@ static void raise_exception_sync_helper(CPUTriCoreState *env, uint32_t class,
25
raise_exception_sync_internal(env, class, tin, pc, 0);
26
}
27
28
-void helper_qemu_excp(CPUTriCoreState *env, uint32_t excp)
29
-{
30
- CPUState *cs = env_cpu(env);
31
- cs->exception_index = excp;
32
- cpu_loop_exit(cs);
33
-}
34
-
35
/* Addressing mode helper */
36
37
static uint16_t reverse16(uint16_t val)
38
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/tricore/translate.c
41
+++ b/target/tricore/translate.c
42
@@ -XXX,XX +XXX,XX @@ static inline void gen_save_pc(target_ulong pc)
43
tcg_gen_movi_tl(cpu_PC, pc);
44
}
45
46
-static void generate_qemu_excp(DisasContext *ctx, int excp)
47
-{
48
- TCGv_i32 tmp = tcg_const_i32(excp);
49
- gen_helper_qemu_excp(cpu_env, tmp);
50
- ctx->base.is_jmp = DISAS_NORETURN;
51
- tcg_temp_free(tmp);
52
-}
53
-
54
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
55
{
56
if (translator_use_goto_tb(&ctx->base, dest)) {
57
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
58
tcg_gen_exit_tb(ctx->base.tb, n);
59
} else {
60
gen_save_pc(dest);
61
- if (ctx->base.singlestep_enabled) {
62
- generate_qemu_excp(ctx, EXCP_DEBUG);
63
- } else {
64
- tcg_gen_lookup_and_goto_ptr();
65
- }
66
+ tcg_gen_lookup_and_goto_ptr();
67
}
68
}
69
70
--
71
2.25.1
72
73
diff view generated by jsdifflib
[PULL 23/24] target/xtensa: Drop check for singlestep_enabled
Deleted patch
1
GDB single-stepping is now handled generically.
2
1
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/xtensa/translate.c | 25 ++++++++-----------------
6
1 file changed, 8 insertions(+), 17 deletions(-)
7
8
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/target/xtensa/translate.c
11
+++ b/target/xtensa/translate.c
12
@@ -XXX,XX +XXX,XX @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
13
if (dc->icount) {
14
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
15
}
16
- if (dc->base.singlestep_enabled) {
17
- gen_exception(dc, EXCP_DEBUG);
18
+ if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
19
+ slot = gen_postprocess(dc, slot);
20
+ }
21
+ if (slot >= 0) {
22
+ tcg_gen_goto_tb(slot);
23
+ tcg_gen_exit_tb(dc->base.tb, slot);
24
} else {
25
- if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
26
- slot = gen_postprocess(dc, slot);
27
- }
28
- if (slot >= 0) {
29
- tcg_gen_goto_tb(slot);
30
- tcg_gen_exit_tb(dc->base.tb, slot);
31
- } else {
32
- tcg_gen_exit_tb(NULL, 0);
33
- }
34
+ tcg_gen_exit_tb(NULL, 0);
35
}
36
dc->base.is_jmp = DISAS_NORETURN;
37
}
38
@@ -XXX,XX +XXX,XX @@ static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
39
case DISAS_NORETURN:
40
break;
41
case DISAS_TOO_MANY:
42
- if (dc->base.singlestep_enabled) {
43
- tcg_gen_movi_i32(cpu_pc, dc->pc);
44
- gen_exception(dc, EXCP_DEBUG);
45
- } else {
46
- gen_jumpi(dc, dc->pc, 0);
47
- }
48
+ gen_jumpi(dc, dc->pc, 0);
49
break;
50
default:
51
g_assert_not_reached();
52
--
53
2.25.1
54
55
diff view generated by jsdifflib
[PULL 24/24] Revert "cpu: Move cpu_common_props to hw/core/cpu.c"
Deleted patch
1
This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f.
2
1
3
Despite a comment saying why cpu_common_props cannot be placed in
4
a file that is compiled once, it was moved anyway. Revert that.
5
6
Since then, Property is not defined in hw/core/cpu.h, so it is now
7
easier to declare a function to install the properties rather than
8
the Property array itself.
9
10
Cc: Eduardo Habkost <ehabkost@redhat.com>
11
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
include/hw/core/cpu.h | 1 +
15
cpu.c | 21 +++++++++++++++++++++
16
hw/core/cpu-common.c | 17 +----------------
17
3 files changed, 23 insertions(+), 16 deletions(-)
18
19
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/core/cpu.h
22
+++ b/include/hw/core/cpu.h
23
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
24
GCC_FMT_ATTR(2, 3);
25
26
/* $(top_srcdir)/cpu.c */
27
+void cpu_class_init_props(DeviceClass *dc);
28
void cpu_exec_initfn(CPUState *cpu);
29
void cpu_exec_realizefn(CPUState *cpu, Error **errp);
30
void cpu_exec_unrealizefn(CPUState *cpu);
31
diff --git a/cpu.c b/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/cpu.c
34
+++ b/cpu.c
35
@@ -XXX,XX +XXX,XX @@ void cpu_exec_unrealizefn(CPUState *cpu)
36
cpu_list_remove(cpu);
37
}
38
39
+static Property cpu_common_props[] = {
40
+#ifndef CONFIG_USER_ONLY
41
+ /*
42
+ * Create a memory property for softmmu CPU object,
43
+ * so users can wire up its memory. (This can't go in hw/core/cpu.c
44
+ * because that file is compiled only once for both user-mode
45
+ * and system builds.) The default if no link is set up is to use
46
+ * the system address space.
47
+ */
48
+ DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
49
+ MemoryRegion *),
50
+#endif
51
+ DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
52
+ DEFINE_PROP_END_OF_LIST(),
53
+};
54
+
55
+void cpu_class_init_props(DeviceClass *dc)
56
+{
57
+ device_class_set_props(dc, cpu_common_props);
58
+}
59
+
60
void cpu_exec_initfn(CPUState *cpu)
61
{
62
cpu->as = NULL;
63
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/core/cpu-common.c
66
+++ b/hw/core/cpu-common.c
67
@@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
68
return cpu->cpu_index;
69
}
70
71
-static Property cpu_common_props[] = {
72
-#ifndef CONFIG_USER_ONLY
73
- /* Create a memory property for softmmu CPU object,
74
- * so users can wire up its memory. (This can't go in hw/core/cpu.c
75
- * because that file is compiled only once for both user-mode
76
- * and system builds.) The default if no link is set up is to use
77
- * the system address space.
78
- */
79
- DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
80
- MemoryRegion *),
81
-#endif
82
- DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
83
- DEFINE_PROP_END_OF_LIST(),
84
-};
85
-
86
static void cpu_class_init(ObjectClass *klass, void *data)
87
{
88
DeviceClass *dc = DEVICE_CLASS(klass);
89
@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
90
dc->realize = cpu_common_realizefn;
91
dc->unrealize = cpu_common_unrealizefn;
92
dc->reset = cpu_common_reset;
93
- device_class_set_props(dc, cpu_common_props);
94
+ cpu_class_init_props(dc);
95
/*
96
* Reason: CPUs still need special care by board code: wiring up
97
* IRQs, adding reset handlers, halting non-first CPUs, ...
98
--
99
2.25.1
100
101
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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