The following changes since commit 6587b0c1331d427b0939c37e763842550ed581db:

Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-10-15' into staging (2021-10-15 14:16:28 -0700)

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211016

for you to fetch changes up to 995b87dedc78b0467f5f18bbc3546072ba97516a:

Revert "cpu: Move cpu_common_props to hw/core/cpu.c" (2021-10-15 16:39:15 -0700)

Move gdb singlestep to generic code

Fix cpu_common_props

Richard Henderson (24):

accel/tcg: Handle gdb singlestep in cpu_tb_exec

target/alpha: Drop checks for singlestep_enabled

target/avr: Drop checks for singlestep_enabled

target/cris: Drop checks for singlestep_enabled

target/hexagon: Drop checks for singlestep_enabled

target/arm: Drop checks for singlestep_enabled

target/hppa: Drop checks for singlestep_enabled

target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt

target/i386: Drop check for singlestep_enabled

target/m68k: Drop checks for singlestep_enabled

target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP

target/microblaze: Drop checks for singlestep_enabled

target/mips: Fix single stepping

target/mips: Drop exit checks for singlestep_enabled

target/openrisc: Drop checks for singlestep_enabled

target/ppc: Drop exit checks for singlestep_enabled

target/riscv: Remove dead code after exception

target/riscv: Remove exit_tb and lookup_and_goto_ptr

target/rx: Drop checks for singlestep_enabled

target/s390x: Drop check for singlestep_enabled

target/sh4: Drop check for singlestep_enabled

target/tricore: Drop check for singlestep_enabled

target/xtensa: Drop check for singlestep_enabled

Revert "cpu: Move cpu_common_props to hw/core/cpu.c"

include/hw/core/cpu.h | 1 +

target/i386/helper.h | 1 -

target/rx/helper.h | 1 -

target/sh4/helper.h | 1 -

target/tricore/helper.h | 1 -

accel/tcg/cpu-exec.c | 11 ++++

cpu.c | 21 ++++++++

hw/core/cpu-common.c | 17 +-----

target/alpha/translate.c | 13 ++---

target/arm/translate-a64.c | 10 +---

target/arm/translate.c | 36 +++----------

target/avr/translate.c | 19 ++-----

target/cris/translate.c | 16 ------

target/hexagon/translate.c | 12 +----

target/hppa/translate.c | 17 ++----

target/i386/tcg/misc_helper.c | 8 ---

target/i386/tcg/translate.c | 9 ++--

target/m68k/translate.c | 44 ++++-----------

target/microblaze/translate.c | 18 ++-----

target/mips/tcg/translate.c | 75 ++++++++++++--------------

target/openrisc/translate.c | 18 ++-----

target/ppc/translate.c | 38 +++----------

target/riscv/translate.c | 27 +---------

target/rx/op_helper.c | 8 ---

target/rx/translate.c | 12 +----

target/s390x/tcg/translate.c | 8 +--

target/sh4/op_helper.c | 5 --

target/sh4/translate.c | 14 ++---

target/tricore/op_helper.c | 7 ---

target/tricore/translate.c | 14 +----

target/xtensa/translate.c | 25 +++------

target/riscv/insn_trans/trans_privileged.c.inc | 10 ++--

target/riscv/insn_trans/trans_rvi.c.inc | 8 ++-

target/riscv/insn_trans/trans_rvv.c.inc | 2 +-

34 files changed, 141 insertions(+), 386 deletions(-)

GDB single-stepping is now handled generically.

Acked-by: Laurent Vivier <laurent@vivier.eu>

target/m68k/translate.c | 44 +++++++++--------------------------------

1 file changed, 9 insertions(+), 35 deletions(-)

diff --git a/target/m68k/translate.c b/target/m68k/translate.c

--- a/target/m68k/translate.c

+++ b/target/m68k/translate.c

@@ -XXX,XX +XXX,XX @@ static void do_writebacks(DisasContext *s)

-static bool is_singlestepping(DisasContext *s)

- /*

- * Return true if we are singlestepping either because of

- * architectural singlestep or QEMU gdbstub singlestep. This does

- * not include the command line '-singlestep' mode which is rather

- * misnamed as it only means "one instruction per TB" and doesn't

- * affect the code we generate.

- */

- return s->base.singlestep_enabled || s->ss_active;

/* is_jmp field values */

#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */

#define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */

@@ -XXX,XX +XXX,XX @@ static void gen_exception(DisasContext *s, uint32_t dest, int nr)

s->base.is_jmp = DISAS_NORETURN;

-static void gen_singlestep_exception(DisasContext *s)

-{

- /*

- * Generate the right kind of exception for singlestep, which is

- * either the architectural singlestep or EXCP_DEBUG for QEMU's

- * gdb singlestepping.

- */

- if (s->ss_active) {

- gen_raise_exception(EXCP_TRACE);

- } else {

- gen_raise_exception(EXCP_DEBUG);

- }

-}

-

static inline void gen_addr_fault(DisasContext *s)

{

gen_exception(s, s->base.pc_next, EXCP_ADDRESS);

@@ -XXX,XX +XXX,XX @@ static void gen_exit_tb(DisasContext *s)

/* Generate a jump to an immediate address. */

static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)

{

- if (unlikely(is_singlestepping(s))) {

+ if (unlikely(s->ss_active)) {

update_cc_op(s);

tcg_gen_movi_i32(QREG_PC, dest);

- gen_singlestep_exception(s);

+ gen_raise_exception(EXCP_TRACE);

} else if (translator_use_goto_tb(&s->base, dest)) {

tcg_gen_goto_tb(n);

tcg_gen_movi_i32(QREG_PC, dest);

@@ -XXX,XX +XXX,XX @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)

dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS);

/* If architectural single step active, limit to 1 */

- if (is_singlestepping(dc)) {

+ if (dc->ss_active) {

dc->base.max_insns = 1;

}

}

@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)

break;

case DISAS_TOO_MANY:

update_cc_op(dc);

- if (is_singlestepping(dc)) {

+ if (dc->ss_active) {

tcg_gen_movi_i32(QREG_PC, dc->pc);

- gen_singlestep_exception(dc);

+ gen_raise_exception(EXCP_TRACE);

} else {

gen_jmp_tb(dc, 0, dc->pc);

}

break;

case DISAS_JUMP:

/* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */

- if (is_singlestepping(dc)) {

- gen_singlestep_exception(dc);

+ if (dc->ss_active) {

+ gen_raise_exception(EXCP_TRACE);

} else {

tcg_gen_lookup_and_goto_ptr();

}

@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)

* We updated CC_OP and PC in gen_exit_tb, but also modified

* other state that may require returning to the main loop.

*/

- if (is_singlestepping(dc)) {

- gen_singlestep_exception(dc);

+ if (dc->ss_active) {

+ gen_raise_exception(EXCP_TRACE);

} else {

tcg_gen_exit_tb(NULL, 0);

}

2.25.1

This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f.

Despite a comment saying why cpu_common_props cannot be placed in

a file that is compiled once, it was moved anyway. Revert that.

Since then, Property is not defined in hw/core/cpu.h, so it is now

easier to declare a function to install the properties rather than

the Property array itself.

Cc: Eduardo Habkost <ehabkost@redhat.com>

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

include/hw/core/cpu.h | 1 +

cpu.c | 21 +++++++++++++++++++++

hw/core/cpu-common.c | 17 +----------------

3 files changed, 23 insertions(+), 16 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h

--- a/include/hw/core/cpu.h

+++ b/include/hw/core/cpu.h

@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)

GCC_FMT_ATTR(2, 3);

/* $(top_srcdir)/cpu.c */

+void cpu_class_init_props(DeviceClass *dc);

void cpu_exec_initfn(CPUState *cpu);

void cpu_exec_realizefn(CPUState *cpu, Error **errp);

void cpu_exec_unrealizefn(CPUState *cpu);

diff --git a/cpu.c b/cpu.c

--- a/cpu.c

+++ b/cpu.c

@@ -XXX,XX +XXX,XX @@ void cpu_exec_unrealizefn(CPUState *cpu)

cpu_list_remove(cpu);

}

+static Property cpu_common_props[] = {

+#ifndef CONFIG_USER_ONLY

+ /*

+ * Create a memory property for softmmu CPU object,

+ * so users can wire up its memory. (This can't go in hw/core/cpu.c

+ * because that file is compiled only once for both user-mode

+ * and system builds.) The default if no link is set up is to use

+ * the system address space.

+ */

+ DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,

+ MemoryRegion *),

+#endif

+ DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),

+ DEFINE_PROP_END_OF_LIST(),

+};

+

+void cpu_class_init_props(DeviceClass *dc)

+{

+ device_class_set_props(dc, cpu_common_props);

+}

+

void cpu_exec_initfn(CPUState *cpu)

{

cpu->as = NULL;

diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/core/cpu-common.c

+++ b/hw/core/cpu-common.c

@@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)

return cpu->cpu_index;

}

-static Property cpu_common_props[] = {

-#ifndef CONFIG_USER_ONLY

- /* Create a memory property for softmmu CPU object,

- * so users can wire up its memory. (This can't go in hw/core/cpu.c

- * because that file is compiled only once for both user-mode

- * and system builds.) The default if no link is set up is to use

- * the system address space.

- */

- DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,

- MemoryRegion *),

-#endif

- DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),

- DEFINE_PROP_END_OF_LIST(),

-};

-

static void cpu_class_init(ObjectClass *klass, void *data)

{

DeviceClass *dc = DEVICE_CLASS(klass);

@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)

dc->realize = cpu_common_realizefn;

dc->unrealize = cpu_common_unrealizefn;

dc->reset = cpu_common_reset;

- device_class_set_props(dc, cpu_common_props);

+ cpu_class_init_props(dc);

/*

* Reason: CPUs still need special care by board code: wiring up

* IRQs, adding reset handlers, halting non-first CPUs, ...

2.25.1

GDB single-stepping is now handled generically.

target/xtensa/translate.c | 25 ++++++++-----------------

1 file changed, 8 insertions(+), 17 deletions(-)

diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c

--- a/target/xtensa/translate.c

+++ b/target/xtensa/translate.c

@@ -XXX,XX +XXX,XX @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)

if (dc->icount) {

tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);

}

- if (dc->base.singlestep_enabled) {

- gen_exception(dc, EXCP_DEBUG);

+ if (dc->op_flags & XTENSA_OP_POSTPROCESS) {

+ slot = gen_postprocess(dc, slot);

+ }

+ if (slot >= 0) {

+ tcg_gen_goto_tb(slot);

+ tcg_gen_exit_tb(dc->base.tb, slot);

} else {

- if (dc->op_flags & XTENSA_OP_POSTPROCESS) {

- slot = gen_postprocess(dc, slot);

- }