[v8] support vector extension v1.0

[PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment

Posted by frank.chang@sifive.com 4 years, 3 months ago

From: Frank Chang <frank.chang@sifive.com>

Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is
moved to Section 11.4 in RVV v1.0 spec. Update the comment, no
functional changes.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index b78c13f0be7..de2e2e506fe 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1613,7 +1613,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
 
 /*
  * For vadc and vsbc, an illegal instruction exception is raised if the
- * destination vector register is v0 and LMUL > 1. (Section 12.4)
+ * destination vector register is v0 and LMUL > 1. (Section 11.4)
  */
 static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
 {
-- 
2.25.1

Re: [PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment

Posted by Alistair Francis 4 years, 3 months ago

On Fri, Oct 15, 2021 at 6:48 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is
> moved to Section 11.4 in RVV v1.0 spec. Update the comment, no
> functional changes.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index b78c13f0be7..de2e2e506fe 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1613,7 +1613,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
>
>  /*
>   * For vadc and vsbc, an illegal instruction exception is raised if the
> - * destination vector register is v0 and LMUL > 1. (Section 12.4)
> + * destination vector register is v0 and LMUL > 1. (Section 11.4)
>   */
>  static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
>  {
> --
> 2.25.1
>
>