On Fri, Oct 15, 2021 at 6:50 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction.
> vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 952768f8ded..d7c6bc9af26 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -78,7 +78,7 @@
> @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
> @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
> @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
> -@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
> +@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
> @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
>
> @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
> @@ -671,7 +671,7 @@ vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm
> vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
> vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
>
> -vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
> +vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
>
> # *** RV32 Zba Standard Extension ***
> --
> 2.25.1
>
>