[PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

From: Frank Chang <frank.chang@sifive.com>

If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0fb71875654..688dc1533b6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -48,6 +48,11 @@ static RISCVException fs(CPURISCVState *env, int csrno)
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
     if (env->misa & RVV) {
+#if !defined(CONFIG_USER_ONLY)
+        if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+            return RISCV_EXCP_ILLEGAL_INST;
+        }
+#endif
         return RISCV_EXCP_NONE;
     }
     return RISCV_EXCP_ILLEGAL_INST;
-- 
2.25.1

• [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
• [PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support
• [PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field
• [PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field
• [PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus VS field
• [PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field
• [PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status
• [PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
• [PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register
• [PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register
• [PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
• [PATCH v8 12/78] target/riscv: rvv-1.0: remove MLEN calculations
• [PATCH v8 13/78] target/riscv: rvv-1.0: add fractional LMUL
• [PATCH v8 14/78] target/riscv: rvv-1.0: add VMA and VTA
• [PATCH v8 15/78] target/riscv: rvv-1.0: update check functions
• [PATCH v8 16/78] target/riscv: introduce more imm value modes in translator functions
• [PATCH v8 17/78] target/riscv: rvv:1.0: add translation-time nan-box helper function
• [PATCH 18/76] target/riscv: rvv-1.0: configure instructions
• [PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions
• [PATCH v8 19/78] target/riscv: rvv-1.0: configure instructions
• [PATCH 19/76] target/riscv: rvv-1.0: stride load and store instructions
• [PATCH v8 20/78] target/riscv: rvv-1.0: stride load and store instructions
• [PATCH 20/76] target/riscv: rvv-1.0: index load and store instructions
• [PATCH v8 21/78] target/riscv: rvv-1.0: index load and store instructions
• [PATCH 21/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
• [PATCH v8 22/78] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
• [PATCH 22/76] target/riscv: rvv-1.0: fault-only-first unit stride load
• [PATCH v8 23/78] target/riscv: rvv-1.0: fault-only-first unit stride load
• [PATCH 23/76] target/riscv: rvv-1.0: amo operations
• [PATCH v8 24/78] target/riscv: rvv-1.0: load/store whole register instructions
• [PATCH v8 25/78] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
• [PATCH v8 26/78] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
• [PATCH v8 27/78] target/riscv: rvv-1.0: floating-point square-root instruction
• [PATCH v8 28/78] target/riscv: rvv-1.0: floating-point classify instructions
• [PATCH 29/76] target/riscv: rvv-1.0: mask population count instruction
• [PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction
• [PATCH v8 30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction
• [PATCH v8 31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions
• [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction
• [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction
• [PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended
• [PATCH v8 35/78] target/riscv: rvv-1.0: register gather instructions
• [PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions
• [PATCH v8 37/78] target/riscv: rvv-1.0: floating-point move instruction
• [PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions
• [PATCH v8 39/78] target/riscv: rvv-1.0: whole register move instructions
• [PATCH v8 40/78] target/riscv: rvv-1.0: integer extension instructions
• [PATCH v8 41/78] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
• [PATCH v8 42/78] target/riscv: rvv-1.0: single-width bit shift instructions
• [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
• [PATCH v8 44/78] target/riscv: rvv-1.0: narrowing integer right shift instructions
• [PATCH v8 45/78] target/riscv: rvv-1.0: widening integer multiply-add instructions
• [PATCH v8 46/78] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
• [PATCH v8 47/78] target/riscv: rvv-1.0: integer comparison instructions
• [PATCH v8 48/78] target/riscv: rvv-1.0: floating-point compare instructions
• [PATCH v8 49/78] target/riscv: rvv-1.0: mask-register logical instructions
• [PATCH v8 50/78] target/riscv: rvv-1.0: slide instructions
• [PATCH v8 51/78] target/riscv: rvv-1.0: floating-point slide instructions
• [PATCH v8 52/78] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
• [PATCH v8 53/78] target/riscv: rvv-1.0: single-width floating-point reduction
• [PATCH v8 54/78] target/riscv: rvv-1.0: widening floating-point reduction instructions
• [PATCH v8 55/78] target/riscv: rvv-1.0: single-width scaling shift instructions
• [PATCH v8 56/78] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
• [PATCH v8 57/78] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
• [PATCH v8 58/78] target/riscv: rvv-1.0: remove integer extract instruction
• [PATCH v8 59/78] target/riscv: rvv-1.0: floating-point min/max instructions
• [PATCH v8 60/78] target/riscv: introduce floating-point rounding mode enum
• [PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
• [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert
• [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function
• [PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
• [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
• [PATCH v8 66/78] target/riscv: rvv-1.0: implement vstart CSR
• [PATCH v8 67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
• [PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs
• [PATCH v8 69/78] target/riscv: gdb: support vector registers for rv64 & rv32
• [PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
• [PATCH v8 71/78] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
• [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs
• [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
• [PATCH v8 74/78] target/riscv: rvv-1.0: add vsetivli instruction
• [PATCH v8 75/78] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
• [PATCH v8 76/78] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
• [PATCH v8 77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
• [PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment