target/riscv/cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
Ensure the columns for all of the register names and values line up.
No functional change, just a minor tweak to the output.
Signed-off-by: Travis Geiselbrecht <travisg@gmail.com>
---
target/riscv/cpu.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1d69d1887e..660f9ce131 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -258,7 +258,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
if (riscv_has_ext(env, RVH)) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus",
(target_ulong)env->vsstatus);
}
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip);
@@ -289,8 +289,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
if (riscv_has_ext(env, RVH)) {
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
}
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
@@ -298,7 +298,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#endif
for (i = 0; i < 32; i++) {
- qemu_fprintf(f, " %s " TARGET_FMT_lx,
+ qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
riscv_int_regnames[i], env->gpr[i]);
if ((i & 3) == 3) {
qemu_fprintf(f, "\n");
@@ -306,7 +306,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
if (flags & CPU_DUMP_FPU) {
for (i = 0; i < 32; i++) {
- qemu_fprintf(f, " %s %016" PRIx64,
+ qemu_fprintf(f, " %-8s %016" PRIx64,
riscv_fpr_regnames[i], env->fpr[i]);
if ((i & 3) == 3) {
qemu_fprintf(f, "\n");
--
2.25.1
On Sat, Oct 9, 2021 at 3:51 PM Travis Geiselbrecht <travisg@gmail.com> wrote: > > Ensure the columns for all of the register names and values line up. > No functional change, just a minor tweak to the output. > > Signed-off-by: Travis Geiselbrecht <travisg@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 1d69d1887e..660f9ce131 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -258,7 +258,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > } > if (riscv_has_ext(env, RVH)) { > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); > - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus", > (target_ulong)env->vsstatus); > } > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); > @@ -289,8 +289,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); > if (riscv_has_ext(env, RVH)) { > - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); > - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); > + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); > } > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch); > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch); > @@ -298,7 +298,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > #endif > > for (i = 0; i < 32; i++) { > - qemu_fprintf(f, " %s " TARGET_FMT_lx, > + qemu_fprintf(f, " %-8s " TARGET_FMT_lx, > riscv_int_regnames[i], env->gpr[i]); > if ((i & 3) == 3) { > qemu_fprintf(f, "\n"); > @@ -306,7 +306,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > } > if (flags & CPU_DUMP_FPU) { > for (i = 0; i < 32; i++) { > - qemu_fprintf(f, " %s %016" PRIx64, > + qemu_fprintf(f, " %-8s %016" PRIx64, > riscv_fpr_regnames[i], env->fpr[i]); > if ((i & 3) == 3) { > qemu_fprintf(f, "\n"); > -- > 2.25.1 > >
On Sat, Oct 9, 2021 at 3:51 PM Travis Geiselbrecht <travisg@gmail.com> wrote: > > Ensure the columns for all of the register names and values line up. > No functional change, just a minor tweak to the output. > > Signed-off-by: Travis Geiselbrecht <travisg@gmail.com> Thanks! Applied to riscv-to-apply.next Alistair
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