Series comparison

-[PULL 00/26] riscv-to-apply queue
+[PULL 00/28] riscv-to-apply queue
-From: Alistair Francis <alistair.francis@wdc.com>
+The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
-The following changes since commit ca61fa4b803e5d0abaf6f1ceb690f23bb78a4def:
+  Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
   Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211006' into staging (2021-10-06 12:11:14 -0700)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211007
+  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
-for you to fetch changes up to 9ae6ecd848dcd1b32003526ab65a0d4c644dfb07:
+for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
-  hw/riscv: shakti_c: Mark as not user creatable (2021-10-07 08:41:33 +1000)
+  target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
 ----------------------------------------------------------------
-Third RISC-V PR for QEMU 6.2
+RISC-V PR for 9.1
- - Add Zb[abcs] instruction support
+* APLICs add child earlier than realize
- - Remove RVB support
+* Fix exposure of Zkr
- - Bug fix of setting mstatus_hs.[SD|FS] bits
+* Raise exceptions on wrs.nto
- - Mark some UART devices as 'input'
+* Implement SBI debug console (DBCN) calls for KVM
- - QOMify PolarFire MMUART
+* Support 64-bit addresses for initrd
- - Fixes for sifive PDMA
+* Change RISCV_EXCP_SEMIHOST exception number to 63
- - Mark shakti_c as not user creatable
+* Tolerate KVM disable ext errors
 * Set tval in breakpoints
 * Add support for Zve32x extension
 * Add support for Zve64x extension
 * Relax vector register check in RISCV gdbstub
 * Fix the element agnostic Vector function problem
 * Fix Zvkb extension config
 * Implement dynamic establishment of custom decoder
 * Add th.sxstatus CSR emulation
 * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
 * Check single width operator for vector fp widen instructions
 * Check single width operator for vfncvt.rod.f.f.w
 * Remove redudant SEW checking for vector fp narrow/widen instructions
 * Prioritize pmp errors in raise_mmu_exception()
 * Do not set mtval2 for non guest-page faults
 * Remove experimental prefix from "B" extension
 * Fixup CBO extension register calculation
 * Fix the hart bit setting of AIA
 * Fix reg_width in ricsv_gen_dynamic_vector_feature()
 * Decode all of the pmpcfg and pmpaddr CSRs
 * Raise an exception when CSRRS/CSRRC writes a read-only CSR
 ----------------------------------------------------------------
-Alistair Francis (1):
+Alexei Filippov (1):
-      hw/riscv: shakti_c: Mark as not user creatable
+      target/riscv: do not set mtval2 for non guest-page faults
-Bin Meng (5):
+Alistair Francis (2):
-      hw/char: ibex_uart: Register device in 'input' category
+      target/riscv: rvzicbo: Fixup CBO extension register calculation
-      hw/char: shakti_uart: Register device in 'input' category
+      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
       hw/char: sifive_uart: Register device in 'input' category
       hw/dma: sifive_pdma: Fix Control.claim bit detection
       hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed
-Frank Chang (1):
+Andrew Jones (2):
-      target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()
+      target/riscv/kvm: Fix exposure of Zkr
       target/riscv: Raise exceptions on wrs.nto
-Philipp Tomsich (16):
+Cheng Yang (1):
-      target/riscv: Introduce temporary in gen_add_uw()
+      hw/riscv/boot.c: Support 64-bit address for initrd
       target/riscv: fix clzw implementation to operate on arg1
       target/riscv: clwz must ignore high bits (use shift-left & changed logic)
       target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
       target/riscv: Reassign instructions to the Zba-extension
       target/riscv: Remove the W-form instructions from Zbs
       target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
       target/riscv: Reassign instructions to the Zbs-extension
       target/riscv: Add instructions of the Zbc-extension
       target/riscv: Reassign instructions to the Zbb-extension
       target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
       target/riscv: Add a REQUIRE_32BIT macro
       target/riscv: Add rev8 instruction, removing grev/grevi
       target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
       target/riscv: Remove RVB (replaced by Zb[abcs])
       disas/riscv: Add Zb[abcs] instructions
-Philippe Mathieu-Daudé (3):
+Christoph Müllner (1):
-      hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition
+      riscv: thead: Add th.sxstatus CSR emulation
       hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container
       hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART
- include/hw/char/mchp_pfsoc_mmuart.h     |  17 +-
+Clément Léger (1):
- target/riscv/cpu.h                      |  11 +-
+      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
  target/riscv/helper.h                   |   6 +-
  target/riscv/insn32.decode              | 115 ++++-----
  disas/riscv.c                           | 157 +++++++++++-
  hw/char/ibex_uart.c                     |   1 +
  hw/char/mchp_pfsoc_mmuart.c             | 116 +++++++--
  hw/char/shakti_uart.c                   |   1 +
  hw/char/sifive_uart.c                   |   1 +
  hw/dma/sifive_pdma.c                    |  13 +-
  hw/riscv/shakti_c.c                     |   7 +
  target/riscv/bitmanip_helper.c          |  65 +----
  target/riscv/cpu.c                      |  30 +--
  target/riscv/translate.c                |  36 ++-
  target/riscv/insn_trans/trans_rvb.c.inc | 419 ++++++++++----------------------
 files changed, 516 insertions(+), 479 deletions(-)
+Daniel Henrique Barboza (6):
+      target/riscv/kvm: implement SBI debug console (DBCN) calls
+      target/riscv/kvm: tolerate KVM disable ext errors
+      target/riscv/debug: set tval=pc in breakpoint exceptions
+      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
+      target/riscv: prioritize pmp errors in raise_mmu_exception()
+      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
+Huang Tao (2):
+      target/riscv: Fix the element agnostic function problem
+      target/riscv: Implement dynamic establishment of custom decoder
+Jason Chien (3):
+      target/riscv: Add support for Zve32x extension
+      target/riscv: Add support for Zve64x extension
+      target/riscv: Relax vector register check in RISCV gdbstub
+Max Chou (4):
+      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
+      target/riscv: rvv: Check single width operator for vector fp widen instructions
+      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
+      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
+Rob Bradford (1):
+      target/riscv: Remove experimental prefix from "B" extension
+Yangyu Chen (1):
+      target/riscv/cpu.c: fix Zvkb extension config
+Yong-Xuan Wang (1):
+      target/riscv/kvm.c: Fix the hart bit setting of AIA
+Yu-Ming Chang (1):
+      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
+yang.zhang (1):
+      hw/intc/riscv_aplic: APLICs should add child earlier than realize
+ MAINTAINERS                                    |   1 +
+ target/riscv/cpu.h                             |  11 ++
+ target/riscv/cpu_bits.h                        |   2 +-
+ target/riscv/cpu_cfg.h                         |   2 +
+ target/riscv/helper.h                          |   1 +
+ target/riscv/sbi_ecall_interface.h             |  17 +++
+ target/riscv/tcg/tcg-cpu.h                     |  15 +++
+ disas/riscv.c                                  |  65 +++++++++-
+ hw/intc/riscv_aplic.c                          |   8 +-
+ hw/riscv/boot.c                                |   4 +-
+ target/riscv/cpu.c                             |  10 +-
+ target/riscv/cpu_helper.c                      |  37 +++---
+ target/riscv/csr.c                             |  71 +++++++++--
+ target/riscv/debug.c                           |   3 +
+ target/riscv/gdbstub.c                         |   8 +-
+ target/riscv/kvm/kvm-cpu.c                     | 157 ++++++++++++++++++++++++-
+ target/riscv/op_helper.c                       |  17 ++-
+ target/riscv/tcg/tcg-cpu.c                     |  50 +++++---
+ target/riscv/th_csr.c                          |  79 +++++++++++++
+ target/riscv/translate.c                       |  31 +++--
+ target/riscv/vector_internals.c                |  22 ++++
+ target/riscv/insn_trans/trans_privileged.c.inc |   2 +
+ target/riscv/insn_trans/trans_rvv.c.inc        |  46 +++++---
+ target/riscv/insn_trans/trans_rvzawrs.c.inc    |  29 +++--
+ target/riscv/insn_trans/trans_rvzicbo.c.inc    |  16 ++-
+ target/riscv/meson.build                       |   1 +
+files changed, 596 insertions(+), 109 deletions(-)
+ create mode 100644 target/riscv/th_csr.c

-[PULL 22/26] hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container
+[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: "yang.zhang" <yang.zhang@hexintek.com>
-Our device have 2 different I/O regions:
+Since only root APLICs can have hw IRQ lines, aplic->parent should
-- a 16550 UART mapped for 32-bit accesses
+be initialized first.
 - 13 extra registers
-Instead of mapping each region on the main bus, introduce
+Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
-a container, map the 2 devices regions on the container,
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-and map the container on the main bus.
+Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Before:
+Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
   (qemu) info mtree
     ...
     0000000020100000-000000002010001f (prio 0, i/o): serial
     0000000020100020-000000002010101f (prio 0, i/o): mchp.pfsoc.mmuart
     0000000020102000-000000002010201f (prio 0, i/o): serial
     0000000020102020-000000002010301f (prio 0, i/o): mchp.pfsoc.mmuart
     0000000020104000-000000002010401f (prio 0, i/o): serial
     0000000020104020-000000002010501f (prio 0, i/o): mchp.pfsoc.mmuart
     0000000020106000-000000002010601f (prio 0, i/o): serial
     0000000020106020-000000002010701f (prio 0, i/o): mchp.pfsoc.mmuart
 After:
   (qemu) info mtree
     ...
     0000000020100000-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart
       0000000020100000-000000002010001f (prio 0, i/o): serial
       0000000020100020-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
     0000000020102000-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart
       0000000020102000-000000002010201f (prio 0, i/o): serial
       0000000020102020-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
     0000000020104000-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart
       0000000020104000-000000002010401f (prio 0, i/o): serial
       0000000020104020-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
     0000000020106000-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart
       0000000020106000-000000002010601f (prio 0, i/o): serial
       0000000020106020-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Tested-by: Bin Meng <bin.meng@windriver.com>
 Message-id: 20210925133407.1259392-3-f4bug@amsat.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/char/mchp_pfsoc_mmuart.h |  1 +
+ hw/intc/riscv_aplic.c | 8 ++++----
- hw/char/mchp_pfsoc_mmuart.c         | 11 ++++++++---
+file changed, 4 insertions(+), 4 deletions(-)
 files changed, 9 insertions(+), 3 deletions(-)
-diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
+diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/mchp_pfsoc_mmuart.h
+--- a/hw/intc/riscv_aplic.c
-+++ b/include/hw/char/mchp_pfsoc_mmuart.h
++++ b/hw/intc/riscv_aplic.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
- #define MCHP_PFSOC_MMUART_REG_COUNT 13
+     qdev_prop_set_bit(dev, "msimode", msimode);
+     qdev_prop_set_bit(dev, "mmode", mmode);
- typedef struct MchpPfSoCMMUartState {
-+    MemoryRegion container;
++    if (parent) {
-     MemoryRegion iomem;
++        riscv_aplic_add_child(parent, dev);
-     hwaddr base;
++    }
      qemu_irq irq;
 diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/mchp_pfsoc_mmuart.c
 +++ b/hw/char/mchp_pfsoc_mmuart.c
@@ -XXX,XX +XXX,XX @@
  #include "chardev/char.h"
  #include "hw/char/mchp_pfsoc_mmuart.h"
 +#define REGS_OFFSET 0x20
 +
- static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- {
-     MchpPfSoCMMUartState *s = opaque;
+     if (!is_kvm_aia(msimode)) {
-@@ -XXX,XX +XXX,XX @@ MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
+         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+     }
-     s = g_new0(MchpPfSoCMMUartState, 1);
+-    if (parent) {
-+    memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000);
+-        riscv_aplic_add_child(parent, dev);
-+
+-    }
-     memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
+-
--                          "mchp.pfsoc.mmuart", 0x1000);
+     if (!msimode) {
-+                          "mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET);
+         for (i = 0; i < num_harts; i++) {
-+    memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem);
+             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
      s->base = base;
      s->irq = irq;
 -    s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
 +    s->serial = serial_mm_init(&s->container, 0, 2, irq, 399193, chr,
                                 DEVICE_LITTLE_ENDIAN);
 -    memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
 +    memory_region_add_subregion(sysmem, base, &s->container);
      return s;
  }
 --
-.31.1
+.45.1

-[PULL 23/26] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART
+[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Andrew Jones <ajones@ventanamicro.com>
-- Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it
+The Zkr extension may only be exposed to KVM guests if the VMM
-- Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART
+implements the SEED CSR. Use the same implementation as TCG.
 - Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize()
 - Add DeviceReset() method
 - Add vmstate structure for migration
 - Register device in 'input' category
 - Keep mchp_pfsoc_mmuart_create() behavior
-Note, serial_mm_init() calls qdev_set_legacy_instance_id().
+Without this patch, running with a KVM which does not forward the
-This call is only needed for backwards-compatibility of incoming
+SEED CSR access to QEMU will result in an ILL exception being
-migration data with old versions of QEMU which implemented migration
+injected into the guest (this results in Linux guests crashing on
-of devices with hand-rolled code. Since this device didn't previously
+boot). And, when running with a KVM which does forward the access,
-handle migration at all, then it doesn't need to set the legacy
+QEMU will crash, since QEMU doesn't know what to do with the exit.
 instance ID.
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
-Reviewed-by: Bin Meng <bin.meng@windriver.com>
+Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
-Tested-by: Bin Meng <bin.meng@windriver.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-id: 20210925133407.1259392-4-f4bug@amsat.org
+Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/char/mchp_pfsoc_mmuart.h | 12 +++-
+ target/riscv/cpu.h         |  3 +++
- hw/char/mchp_pfsoc_mmuart.c         | 97 +++++++++++++++++++++++++----
+ target/riscv/csr.c         | 18 ++++++++++++++----
-files changed, 93 insertions(+), 16 deletions(-)
+ target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 files changed, 42 insertions(+), 4 deletions(-)
-diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/mchp_pfsoc_mmuart.h
+--- a/target/riscv/cpu.h
-+++ b/include/hw/char/mchp_pfsoc_mmuart.h
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
- #ifndef HW_MCHP_PFSOC_MMUART_H
- #define HW_MCHP_PFSOC_MMUART_H
+ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
-+#include "hw/sysbus.h"
++target_ulong riscv_new_csr_seed(target_ulong new_value,
- #include "hw/char/serial.h"
++                                target_ulong write_mask);
  #define MCHP_PFSOC_MMUART_REG_COUNT 13
 +#define TYPE_MCHP_PFSOC_UART "mchp.pfsoc.uart"
 +OBJECT_DECLARE_SIMPLE_TYPE(MchpPfSoCMMUartState, MCHP_PFSOC_UART)
 +
- typedef struct MchpPfSoCMMUartState {
+ uint8_t satp_mode_max_from_map(uint32_t map);
-+    /*< private >*/
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
-+    SysBusDevice parent_obj;
-+
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 +    /*< public >*/
      MemoryRegion container;
      MemoryRegion iomem;
 -    hwaddr base;
 -    qemu_irq irq;
 -    SerialMM *serial;
 +    SerialMM serial_mm;
      uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT];
  } MchpPfSoCMMUartState;
 diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/mchp_pfsoc_mmuart.c
+--- a/target/riscv/csr.c
-+++ b/hw/char/mchp_pfsoc_mmuart.c
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
+ #endif
- #include "qemu/osdep.h"
- #include "qemu/log.h"
+ /* Crypto Extension */
--#include "chardev/char.h"
+-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-+#include "qapi/error.h"
+-                               target_ulong *ret_value,
-+#include "migration/vmstate.h"
+-                               target_ulong new_value,
- #include "hw/char/mchp_pfsoc_mmuart.h"
+-                               target_ulong write_mask)
-+#include "hw/qdev-properties.h"
++target_ulong riscv_new_csr_seed(target_ulong new_value,
++                                target_ulong write_mask)
- #define REGS_OFFSET 0x20
+ {
+     uint16_t random_v;
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
+     Error *random_e = NULL;
-     },
+@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
- };
+         rval = random_v | SEED_OPST_ES16;
+     }
--MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
--    hwaddr base, qemu_irq irq, Chardev *chr)
++    return rval;
 +static void mchp_pfsoc_mmuart_reset(DeviceState *dev)
 +{
 +    MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev);
 +
 +    memset(s->reg, 0, sizeof(s->reg));
 +    device_cold_reset(DEVICE(&s->serial_mm));
 +}
 +
-+static void mchp_pfsoc_mmuart_init(Object *obj)
++static RISCVException rmw_seed(CPURISCVState *env, int csrno,
- {
++                               target_ulong *ret_value,
--    MchpPfSoCMMUartState *s;
++                               target_ulong new_value,
-+    MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(obj);
++                               target_ulong write_mask)
 -    s = g_new0(MchpPfSoCMMUartState, 1);
 +    object_initialize_child(obj, "serial-mm", &s->serial_mm, TYPE_SERIAL_MM);
 +    object_property_add_alias(obj, "chardev", OBJECT(&s->serial_mm), "chardev");
 +}
 -    memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000);
 +static void mchp_pfsoc_mmuart_realize(DeviceState *dev, Error **errp)
 +{
-+    MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev);
++    target_ulong rval;
++
--    memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
++    rval = riscv_new_csr_seed(new_value, write_mask);
-+    qdev_prop_set_uint8(DEVICE(&s->serial_mm), "regshift", 2);
++
-+    qdev_prop_set_uint32(DEVICE(&s->serial_mm), "baudbase", 399193);
+     if (ret_value) {
-+    qdev_prop_set_uint8(DEVICE(&s->serial_mm), "endianness",
+         *ret_value = rval;
-+                        DEVICE_LITTLE_ENDIAN);
+     }
-+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->serial_mm), errp)) {
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
-+        return;
+index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
      return ret;
  }
 +static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
 +{
 +    target_ulong csr_num = run->riscv_csr.csr_num;
 +    target_ulong new_value = run->riscv_csr.new_value;
 +    target_ulong write_mask = run->riscv_csr.write_mask;
 +    int ret = 0;
 +
 +    switch (csr_num) {
 +    case CSR_SEED:
 +        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "%s: un-handled CSR EXIT for CSR %lx\n",
 +                      __func__, csr_num);
 +        ret = -1;
 +        break;
 +    }
 +
-+    sysbus_pass_irq(SYS_BUS_DEVICE(dev), SYS_BUS_DEVICE(&s->serial_mm));
++    return ret;
 +
 +    memory_region_init(&s->container, OBJECT(s), "mchp.pfsoc.mmuart", 0x1000);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
 +
 +    memory_region_add_subregion(&s->container, 0,
 +                    sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial_mm), 0));
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &mchp_pfsoc_mmuart_ops, s,
                            "mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET);
      memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem);
 +}
 -    s->base = base;
 -    s->irq = irq;
 +static const VMStateDescription mchp_pfsoc_mmuart_vmstate = {
 +    .name = "mchp.pfsoc.uart",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(reg, MchpPfSoCMMUartState,
 +                             MCHP_PFSOC_MMUART_REG_COUNT),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static void mchp_pfsoc_mmuart_class_init(ObjectClass *oc, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(oc);
 +
 +    dc->realize = mchp_pfsoc_mmuart_realize;
 +    dc->reset = mchp_pfsoc_mmuart_reset;
 +    dc->vmsd = &mchp_pfsoc_mmuart_vmstate;
 +    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 +}
 +
-+static const TypeInfo mchp_pfsoc_mmuart_info = {
+ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
-+    .name          = TYPE_MCHP_PFSOC_UART,
+ {
-+    .parent        = TYPE_SYS_BUS_DEVICE,
+     int ret = 0;
-+    .instance_size = sizeof(MchpPfSoCMMUartState),
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
-+    .instance_init = mchp_pfsoc_mmuart_init,
+     case KVM_EXIT_RISCV_SBI:
-+    .class_init    = mchp_pfsoc_mmuart_class_init,
+         ret = kvm_riscv_handle_sbi(cs, run);
-+};
+         break;
-+
++    case KVM_EXIT_RISCV_CSR:
-+static void mchp_pfsoc_mmuart_register_types(void)
++        ret = kvm_riscv_handle_csr(cs, run);
-+{
++        break;
-+    type_register_static(&mchp_pfsoc_mmuart_info);
+     default:
-+}
+         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
-+
+                       __func__, run->exit_reason);
 +type_init(mchp_pfsoc_mmuart_register_types)
 +
 +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
 +                                               hwaddr base,
 +                                               qemu_irq irq, Chardev *chr)
 +{
 +    DeviceState *dev = qdev_new(TYPE_MCHP_PFSOC_UART);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 -    s->serial = serial_mm_init(&s->container, 0, 2, irq, 399193, chr,
 -                               DEVICE_LITTLE_ENDIAN);
 +    qdev_prop_set_chr(dev, "chardev", chr);
 +    sysbus_realize(sbd, &error_fatal);
 -    memory_region_add_subregion(sysmem, base, &s->container);
 +    memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(sbd, 0));
 +    sysbus_connect_irq(sbd, 0, irq);
 -    return s;
 +    return MCHP_PFSOC_UART(dev);
  }
 --
-.31.1
+.45.1

-[PULL 09/26] target/riscv: Add instructions of the Zbc-extension
+[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Andrew Jones <ajones@ventanamicro.com>
-The following instructions are part of Zbc:
+Implementing wrs.nto to always just return is consistent with the
- - clmul
+specification, as the instruction is permitted to terminate the
- - clmulh
+stall for any reason, but it's not useful for virtualization, where
- - clmulr
+we'd like the guest to trap to the hypervisor in order to allow
 scheduling of the lock holding VCPU. Change to always immediately
 raise exceptions when the appropriate conditions are present,
 otherwise continue to just return. Note, immediately raising
 exceptions is also consistent with the specification since the
 time limit that should expire prior to the exception is
 implementation-specific.
-Note that these instructions were already defined in the pre-0.93 and
+Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
-the 0.93 draft-B proposals, but had not been omitted in the earlier
+Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
-addition of draft-B to QEmu.
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu
+Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/helper.h                   |  2 ++
+ target/riscv/helper.h                       |  1 +
- target/riscv/insn32.decode              |  5 ++++
+ target/riscv/op_helper.c                    | 11 ++++++++
- target/riscv/bitmanip_helper.c          | 27 +++++++++++++++++++++
+ target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
- target/riscv/insn_trans/trans_rvb.c.inc | 32 ++++++++++++++++++++++++-
+files changed, 32 insertions(+), 9 deletions(-)
 files changed, 65 insertions(+), 1 deletion(-)
 diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/helper.h
 +++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
- DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+ DEF_HELPER_1(sret, tl, env)
- DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+ DEF_HELPER_1(mret, tl, env)
- DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+ DEF_HELPER_1(wfi, void, env)
-+DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
++DEF_HELPER_1(wrs_nto, void, env)
-+DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+ DEF_HELPER_1(tlb_flush, void, env)
+ DEF_HELPER_1(tlb_flush_all, void, env)
- /* Special functions */
+ /* Native Debug */
- DEF_HELPER_2(csrr, tl, env, int)
+diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/op_helper.c
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/op_helper.c
-@@ -XXX,XX +XXX,XX @@ roriw      0110000 .......... 101 ..... 0011011 @sh5
+@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
- greviw     0110100 .......... 101 ..... 0011011 @sh5
+     }
  gorciw     0010100 .......... 101 ..... 0011011 @sh5
 +# *** RV32 Zbc Standard Extension ***
 +clmul      0000101 .......... 001 ..... 0110011 @r
 +clmulh     0000101 .......... 011 ..... 0110011 @r
 +clmulr     0000101 .......... 010 ..... 0110011 @r
 +
  # *** RV32 Zbs Standard Extension ***
  bclr       0100100 .......... 001 ..... 0110011 @r
  bclri      01001. ........... 001 ..... 0010011 @sh
 diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/bitmanip_helper.c
 +++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@
   *
   * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
   * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
 + * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
   *
   * This program is free software; you can redistribute it and/or modify it
   * under the terms and conditions of the GNU General Public License,
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
  {
      return do_gorc(rs1, rs2, 32);
  }
-+
-+target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
++void helper_wrs_nto(CPURISCVState *env)
 +{
-+    target_ulong result = 0;
++    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
-+
++        get_field(env->hstatus, HSTATUS_VTW) &&
-+    for (int i = 0; i < TARGET_LONG_BITS; i++) {
++        !get_field(env->mstatus, MSTATUS_TW)) {
-+        if ((rs2 >> i) & 1) {
++        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
-+            result ^= (rs1 << i);
++    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
-+        }
++        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    }
-+
-+    return result;
 +}
 +
-+target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
+ void helper_tlb_flush(CPURISCVState *env)
  {
      CPUState *cs = env_cpu(env);
 diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
 +++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
   * this program.  If not, see <http://www.gnu.org/licenses/>.
   */
 -static bool trans_wrs(DisasContext *ctx)
 +static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
  {
      if (!ctx->cfg_ptr->ext_zawrs) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
      return true;
  }
 -#define GEN_TRANS_WRS(insn)                                     \
 -static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
 -{                                                               \
 -    (void)a;                                                    \
 -    return trans_wrs(ctx);                                      \
 -}
 +static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
 +{
-+    target_ulong result = 0;
++    if (!ctx->cfg_ptr->ext_zawrs) {
 +        return false;
 +    }
 -GEN_TRANS_WRS(wrs_nto)
 -GEN_TRANS_WRS(wrs_sto)
 +    /*
 +     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
 +     * should raise an exception when the implementation-specific bounded time
 +     * limit has expired. Our time limit is zero, so we either return
 +     * immediately, as does our implementation of wrs.sto, or raise an
 +     * exception, as handled by the wrs.nto helper.
 +     */
 +#ifndef CONFIG_USER_ONLY
 +    gen_helper_wrs_nto(tcg_env);
 +#endif
 +
-+    for (int i = 0; i < TARGET_LONG_BITS; i++) {
++    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
-+        if ((rs2 >> i) & 1) {
++    return trans_wrs_sto(ctx, NULL);
 +            result ^= (rs1 >> (TARGET_LONG_BITS - i - 1));
 +        }
 +    }
 +
 +    return result;
 +}
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
  /*
 - * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
 + * RISC-V translation routines for the Zb[acs] Standard Extension.
   *
   * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
   * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -XXX,XX +XXX,XX @@
      }                                            \
  } while (0)
 +#define REQUIRE_ZBC(ctx) do {                    \
 +    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
  #define REQUIRE_ZBS(ctx) do {                    \
      if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
          return false;                            \
@@ -XXX,XX +XXX,XX @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
      REQUIRE_ZBA(ctx);
      return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
  }
 +
 +static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
 +{
 +    REQUIRE_ZBC(ctx);
 +    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
 +}
 +
 +static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
 +{
 +     gen_helper_clmulr(dst, src1, src2);
 +     tcg_gen_shri_tl(dst, dst, 1);
 +}
 +
 +static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
 +{
 +    REQUIRE_ZBC(ctx);
 +    return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
 +}
 +
 +static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
 +{
 +    REQUIRE_ZBC(ctx);
 +    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
 +}
 --
-.31.1
+.45.1

-[PULL 14/26] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
+[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a
+SBI defines a Debug Console extension "DBCN" that will, in time, replace
-zext.h instruction is provided (built on pack/packh from pre-0.93
+the legacy console putchar and getchar SBI extensions.
-draft-B) is available.
+The appeal of the DBCN extension is that it allows multiple bytes to be
-This commit adds zext.h and removes the pack* instructions.
+read/written in the SBI console in a single SBI call.
-Note that the encodings for zext.h are different between RV32 and
+As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
-RV64, which is handled through REQUIRE_32BIT.
+module to userspace. But this will only happens if the KVM module
+actually supports this SBI extension and we activate it.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+We'll check for DBCN support during init time, checking if get-reg-list
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
-Message-id: 20210911140016.834071-15-philipp.tomsich@vrull.eu
+kvm_set_one_reg() during kvm_arch_init_vcpu().
 Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
 SBI_EXT_DBCN, reading and writing as required.
 A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
 host, takes around 20 seconds to boot without using DBCN. With this
 patch we're taking around 14 seconds to boot due to the speed-up in the
 terminal output.  There's no change in boot time if the guest isn't
 using earlycon.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn32.decode              | 12 ++--
+ target/riscv/sbi_ecall_interface.h |  17 +++++
- target/riscv/insn_trans/trans_rvb.c.inc | 86 ++++---------------------
+ target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
-files changed, 21 insertions(+), 77 deletions(-)
+files changed, 128 insertions(+)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/sbi_ecall_interface.h
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/sbi_ecall_interface.h
-@@ -XXX,XX +XXX,XX @@ rori       01100 ............ 101 ..... 0010011 @sh
+@@ -XXX,XX +XXX,XX @@
- sext_b     011000 000100 ..... 001 ..... 0010011 @r2
- sext_h     011000 000101 ..... 001 ..... 0010011 @r2
+ /* clang-format off */
- xnor       0100000 .......... 100 ..... 0110011 @r
-+# The encoding for zext.h differs between RV32 and RV64.
++#define SBI_SUCCESS                      0
-+# zext_h_32 denotes the RV32 variant.
++#define SBI_ERR_FAILED                  -1
-+zext_h_32  0000100 00000 ..... 100 ..... 0110011 @r2
++#define SBI_ERR_NOT_SUPPORTED           -2
++#define SBI_ERR_INVALID_PARAM           -3
- # *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
++#define SBI_ERR_DENIED                  -4
- clzw       0110000 00000 ..... 001 ..... 0011011 @r2
++#define SBI_ERR_INVALID_ADDRESS         -5
-@@ -XXX,XX +XXX,XX @@ rev8_64    011010 111000 ..... 101 ..... 0010011 @r2
++#define SBI_ERR_ALREADY_AVAILABLE       -6
- rolw       0110000 .......... 001 ..... 0111011 @r
++#define SBI_ERR_ALREADY_STARTED         -7
- roriw      0110000 .......... 101 ..... 0011011 @sh5
++#define SBI_ERR_ALREADY_STOPPED         -8
- rorw       0110000 .......... 101 ..... 0111011 @r
++#define SBI_ERR_NO_SHMEM                -9
-+# The encoding for zext.h differs between RV32 and RV64.
++
-+# When executing on RV64, the encoding used in RV32 is an illegal
+ /* SBI Extension IDs */
-+# instruction, so we use different handler functions to differentiate.
+ #define SBI_EXT_0_1_SET_TIMER           0x0
-+zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
+ #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
+@@ -XXX,XX +XXX,XX @@
- # *** RV32B Standard Extension ***
+ #define SBI_EXT_IPI                     0x735049
--pack       0000100 .......... 100 ..... 0110011 @r
+ #define SBI_EXT_RFENCE                  0x52464E43
--packu      0100100 .......... 100 ..... 0110011 @r
+ #define SBI_EXT_HSM                     0x48534D
--packh      0000100 .......... 111 ..... 0110011 @r
++#define SBI_EXT_DBCN                    0x4442434E
- # *** RV64B Standard Extension (in addition to RV32B) ***
+ /* SBI function IDs for BASE extension */
--packw      0000100 .......... 100 ..... 0111011 @r
+ #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
--packuw     0100100 .......... 100 ..... 0111011 @r
+@@ -XXX,XX +XXX,XX @@
+ #define SBI_EXT_HSM_HART_STOP           0x1
- # *** RV32 Zbc Standard Extension ***
+ #define SBI_EXT_HSM_HART_GET_STATUS     0x2
- clmul      0000101 .......... 001 ..... 0110011 @r
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
++/* SBI function IDs for DBCN extension */
 +#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
 +#define SBI_EXT_DBCN_CONSOLE_READ       0x1
 +#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
 +
  #define SBI_HSM_HART_STATUS_STARTED     0x0
  #define SBI_HSM_HART_STATUS_STOPPED     0x1
  #define SBI_HSM_HART_STATUS_START_PENDING   0x2
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
+@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
-     return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
+                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
- }
+ };
--static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
++static KVMCPUConfig kvm_sbi_dbcn = {
--{
++    .name = "sbi_dbcn",
--    tcg_gen_deposit_tl(ret, arg1, arg2,
++    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
--                       TARGET_LONG_BITS / 2,
++                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
--                       TARGET_LONG_BITS / 2);
++};
--}
++
--
+ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
--static bool trans_pack(DisasContext *ctx, arg_pack *a)
+ {
--{
+     CPURISCVState *env = &cpu->env;
--    REQUIRE_EXT(ctx, RVB);
+@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
--    return gen_arith(ctx, a, EXT_NONE, gen_pack);
+     return 0;
--}
+ }
--
--static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
++static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
--{
++                                             KVMScratchCPU *kvmcpu,
--    TCGv t = tcg_temp_new();
++                                             struct kvm_reg_list *reglist)
 -    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
 -    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
 -    tcg_temp_free(t);
 -}
 -
 -static bool trans_packu(DisasContext *ctx, arg_packu *a)
 -{
 -    REQUIRE_EXT(ctx, RVB);
 -    return gen_arith(ctx, a, EXT_NONE, gen_packu);
 -}
 -
 -static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    TCGv t = tcg_temp_new();
 -    tcg_gen_ext8u_tl(t, arg2);
 -    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
 -    tcg_temp_free(t);
 -}
 -
 -static bool trans_packh(DisasContext *ctx, arg_packh *a)
 -{
 -    REQUIRE_EXT(ctx, RVB);
 -    return gen_arith(ctx, a, EXT_NONE, gen_packh);
 -}
 -
  static bool trans_min(DisasContext *ctx, arg_min *a)
  {
      REQUIRE_ZBB(ctx);
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(1)
  GEN_TRANS_SHADD(2)
  GEN_TRANS_SHADD(3)
 +static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a)
 +{
-+    REQUIRE_32BIT(ctx);
++    struct kvm_reg_list *reg_search;
-+    REQUIRE_ZBB(ctx);
++
-+    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
++    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
 +                         sizeof(uint64_t), uint64_cmp);
 +
 +    if (reg_search) {
 +        kvm_sbi_dbcn.supported = true;
 +    }
 +}
 +
-+static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
+ static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                   struct kvm_reg_list *reglist)
  {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
      if (riscv_has_ext(&cpu->env, RVV)) {
          kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
      }
 +
 +    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
  }
  static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
      return ret;
  }
 +static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
 +{
-+    REQUIRE_64BIT(ctx);
++    target_ulong reg = 1;
-+    REQUIRE_ZBB(ctx);
++
-+    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
++    if (!kvm_sbi_dbcn.supported) {
 +        return 0;
 +    }
 +
 +    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
 +}
 +
- static void gen_clzw(TCGv ret, TCGv arg1)
+ int kvm_arch_init_vcpu(CPUState *cs)
  {
-     TCGv t = tcg_temp_new();
+     int ret = 0;
-@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
-     return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
+     kvm_riscv_update_cpu_misa_ext(cpu, cs);
- }
+     kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
--static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
++    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
--{
++
--    TCGv t = tcg_temp_new();
+     return ret;
--    tcg_gen_ext16s_tl(t, arg2);
+ }
--    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
--    tcg_temp_free(t);
+@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
--}
+     return true;
--
+ }
--static bool trans_packw(DisasContext *ctx, arg_packw *a)
--{
++static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
--    REQUIRE_64BIT(ctx);
++{
--    REQUIRE_EXT(ctx, RVB);
++    g_autofree uint8_t *buf = NULL;
--    return gen_arith(ctx, a, EXT_NONE, gen_packw);
++    RISCVCPU *cpu = RISCV_CPU(cs);
--}
++    target_ulong num_bytes;
--
++    uint64_t addr;
--static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
++    unsigned char ch;
--{
++    int ret;
--    TCGv t = tcg_temp_new();
++
--    tcg_gen_shri_tl(t, arg1, 16);
++    switch (run->riscv_sbi.function_id) {
--    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
++    case SBI_EXT_DBCN_CONSOLE_READ:
--    tcg_gen_ext32s_tl(ret, ret);
++    case SBI_EXT_DBCN_CONSOLE_WRITE:
--    tcg_temp_free(t);
++        num_bytes = run->riscv_sbi.args[0];
--}
++
--
++        if (num_bytes == 0) {
--static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
++            run->riscv_sbi.ret[0] = SBI_SUCCESS;
--{
++            run->riscv_sbi.ret[1] = 0;
--    REQUIRE_64BIT(ctx);
++            break;
--    REQUIRE_EXT(ctx, RVB);
++        }
--    return gen_arith(ctx, a, EXT_NONE, gen_packuw);
++
--}
++        addr = run->riscv_sbi.args[1];
--
++
- static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
++        /*
- {
++         * Handle the case where a 32 bit CPU is running in a
-     TCGv_i32 t1 = tcg_temp_new_i32();
++         * 64 bit addressing env.
 +         */
 +        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
 +            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
 +        }
 +
 +        buf = g_malloc0(num_bytes);
 +
 +        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
 +            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
 +                             "reading chardev");
 +                exit(1);
 +            }
 +
 +            cpu_physical_memory_write(addr, buf, ret);
 +        } else {
 +            cpu_physical_memory_read(addr, buf, num_bytes);
 +
 +            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
 +                             "writing chardev");
 +                exit(1);
 +            }
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = ret;
 +        break;
 +    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
 +        ch = run->riscv_sbi.args[0];
 +        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
 +
 +        if (ret < 0) {
 +            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
 +                         "writing chardev");
 +            exit(1);
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = 0;
 +        break;
 +    default:
 +        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
 +    }
 +}
 +
  static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
          }
          ret = 0;
          break;
 +    case SBI_EXT_DBCN:
 +        kvm_riscv_handle_sbi_dbcn(cs, run);
 +        break;
      default:
          qemu_log_mask(LOG_UNIMP,
                        "%s: un-handled SBI EXIT, specific reasons is %lu\n",
 --
-.31.1
+.45.1

-[PULL 26/26] hw/riscv: shakti_c: Mark as not user creatable
+[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
-From: Alistair Francis <alistair.francis@wdc.com>
+From: Cheng Yang <yangcheng.work@foxmail.com>
-Mark the shakti_c machine as not user creatable.
+Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
 to set the address of initrd in FDT to support 64-bit address.
-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/639
+Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-Id: <c617a04d4e3dd041a3427b47a1b1d5ab475a2edd.1632871759.git.alistair.francis@wdc.com>
 ---
- hw/riscv/shakti_c.c | 7 +++++++
+ hw/riscv/boot.c | 4 ++--
-file changed, 7 insertions(+)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
+diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/shakti_c.c
+--- a/hw/riscv/boot.c
-+++ b/hw/riscv/shakti_c.c
++++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
+@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
- {
+     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
-     DeviceClass *dc = DEVICE_CLASS(klass);
+     if (fdt) {
-     dc->realize = shakti_c_soc_state_realize;
+         end = start + size;
-+    /*
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-+     * Reasons:
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
-+     *     - Creates CPUS in riscv_hart_realize(), and can create unintended
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
-+     *       CPUs
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
-+     *     - Uses serial_hds in realize function, thus can't be used twice
+     }
 +     */
 +    dc->user_creatable = false;
  }
- static void shakti_c_soc_instance_init(Object *obj)
 --
-.31.1
+.45.1

-[PULL 25/26] hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed
+[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
-From: Bin Meng <bmeng.cn@gmail.com>
+From: Clément Léger <cleger@rivosinc.com>
-If Control.run bit is set while not preserving the Control.claim
+The current semihost exception number (16) is a reserved number (range
-bit, the DMA transfer shall not be started.
+[16-17]). The upcoming double trap specification uses that number for
 the double trap exception. Since the privileged spec (Table 22) defines
 ranges for custom uses change the semihosting exception number to 63
 which belongs to the range [48-63] in order to avoid any future
 collisions with reserved exception.
-The following result is PDMA tested in U-Boot on Unleashed board:
+Signed-off-by: Clément Léger <cleger@rivosinc.com>
-=> mw.l 0x3000000 0x0                      <= Disclaim channel 0
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-=> mw.l 0x3000000 0x1                      <= Claim channel 0
+Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
 => mw.l 0x3000004 0x55000000               <= wsize = rsize = 5 (2^5 = 32 bytes)
 => mw.q 0x3000008 0x2                      <= NextBytes = 2
 => mw.q 0x3000010 0x84000000               <= NextDestination = 0x84000000
 => mw.q 0x3000018 0x84001000               <= NextSource = 0x84001000
 => mw.l 0x84000000 0x87654321              <= Fill test data to dst
 => mw.l 0x84001000 0x12345678              <= Fill test data to src
 => md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
 84000000: 87654321                               !Ce.
 84001000: 12345678                               xV4.
 => md.l 0x3000000 8                        <= Dump PDMA status
 03000000: 00000001 55000000 00000002 00000000    .......U........
 03000010: 84000000 00000000 84001000 00000000    ................
 => mw.l 0x3000000 0x2                      <= Set channel 0 run bit only
 => md.l 0x3000000 8                        <= Dump PDMA status
 03000000: 00000000 55000000 00000002 00000000    .......U........
 03000010: 84000000 00000000 84001000 00000000    ................
 => md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
 84000000: 87654321                               !Ce.
 84001000: 12345678                               xV4.
 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210927072124.1564129-2-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/dma/sifive_pdma.c | 11 +++++++++--
+ target/riscv/cpu_bits.h | 2 +-
-file changed, 9 insertions(+), 2 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/dma/sifive_pdma.c
+--- a/target/riscv/cpu_bits.h
-+++ b/hw/dma/sifive_pdma.c
++++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
+@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
- {
+     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
-     SiFivePDMAState *s = opaque;
+     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
-     int ch = SIFIVE_PDMA_CHAN_NO(offset);
+     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
--    bool claimed;
+-    RISCV_EXCP_SEMIHOST = 0x10,
-+    bool claimed, run;
+     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
+     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
-     if (ch >= SIFIVE_PDMA_CHANS) {
+     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
-         qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
+     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
-@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
++    RISCV_EXCP_SEMIHOST = 0x3f,
-     switch (offset) {
+ } RISCVException;
-     case DMA_CONTROL:
-         claimed = !!(s->chan[ch].control & CONTROL_CLAIM);
+ #define RISCV_EXCP_INT_FLAG                0x80000000
 +        run = !!(s->chan[ch].control & CONTROL_RUN);
          if (!claimed && (value & CONTROL_CLAIM)) {
              /* reset Next* registers */
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
              s->chan[ch].next_src = 0;
          }
 +        /* claim bit can only be cleared when run is low */
 +        if (run && !(value & CONTROL_CLAIM)) {
 +            value |= CONTROL_CLAIM;
 +        }
 +
          s->chan[ch].control = value;
          /*
           * If channel was not claimed before run bit is set,
 +         * or if the channel is disclaimed when run was low,
           * DMA won't run.
           */
 -        if (!claimed) {
 +        if (!claimed || (!run && !(value & CONTROL_CLAIM))) {
              s->chan[ch].control &= ~CONTROL_RUN;
              return;
          }
 --
-.31.1
+.45.1

-[PULL 05/26] target/riscv: Reassign instructions to the Zba-extension
+[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-The following instructions are part of Zba:
+Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
- - add.uw (RV64 only)
+enabled, will fail with a kernel oops SIGILL right at the start. The
- - sh[123]add (RV32 and RV64)
+reason is that we can't expose zkr without implementing the SEED CSR.
- - sh[123]add.uw (RV64-only)
+Disabling zkr in the guest would be a workaround, but if the KVM doesn't
- - slli.uw (RV64-only)
+allow it we'll error out and never boot.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+In hindsight this is too strict. If we keep proceeding, despite not
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+disabling the extension in the KVM vcpu, we'll not add the extension in
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+the riscv,isa. The guest kernel will be unaware of the extension, i.e.
-Acked-by: Bin Meng <bmeng.cn@gmail.com>
+it doesn't matter if the KVM vcpu has it enabled underneath or not. So
-Message-id: 20210911140016.834071-6-philipp.tomsich@vrull.eu
+it's ok to keep booting in this case.
 Change our current logic to not error out if we fail to disable an
 extension in kvm_set_one_reg(), but show a warning and keep booting. It
 is important to throw a warning because we must make the user aware that
 the extension is still available in the vcpu, meaning that an
 ill-behaved guest can ignore the riscv,isa settings and  use the
 extension.
 The case we're handling happens with an EINVAL error code. If we fail to
 disable the extension in KVM for any other reason, error out.
 We'll also keep erroring out when we fail to enable an extension in KVM,
 since adding the extension in riscv,isa at this point will cause a guest
 malfunction because the extension isn't enabled in the vcpu.
 Suggested-by: Andrew Jones <ajones@ventanamicro.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn32.decode              | 20 ++++++++++++--------
+ target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
- target/riscv/insn_trans/trans_rvb.c.inc | 16 +++++++++++-----
+file changed, 8 insertions(+), 4 deletions(-)
 files changed, 23 insertions(+), 13 deletions(-)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ vamomaxd_v      10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
- vamominud_v     11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
- vamomaxud_v     11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+         ret = kvm_set_one_reg(cs, id, &reg);
+         if (ret != 0) {
-+# *** RV32 Zba Standard Extension ***
+-            error_report("Unable to %s extension %s in KVM, error %d",
-+sh1add     0010000 .......... 010 ..... 0110011 @r
+-                         reg ? "enable" : "disable",
-+sh2add     0010000 .......... 100 ..... 0110011 @r
+-                         multi_ext_cfg->name, ret);
-+sh3add     0010000 .......... 110 ..... 0110011 @r
+-            exit(EXIT_FAILURE);
-+
++            if (!reg && ret == -EINVAL) {
-+# *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
++                warn_report("KVM cannot disable extension %s",
-+add_uw     0000100 .......... 000 ..... 0111011 @r
++                            multi_ext_cfg->name);
-+sh1add_uw  0010000 .......... 010 ..... 0111011 @r
++            } else {
-+sh2add_uw  0010000 .......... 100 ..... 0111011 @r
++                error_report("Unable to enable extension %s in KVM, error %d",
-+sh3add_uw  0010000 .......... 110 ..... 0111011 @r
++                             multi_ext_cfg->name, ret);
-+slli_uw    00001 ............ 001 ..... 0011011 @sh
++                exit(EXIT_FAILURE);
-+
++            }
- # *** RV32B Standard Extension ***
+         }
- clz        011000 000000 ..... 001 ..... 0010011 @r2
+     }
  ctz        011000 000001 ..... 001 ..... 0010011 @r2
@@ -XXX,XX +XXX,XX @@ ror        0110000 .......... 101 ..... 0110011 @r
  rol        0110000 .......... 001 ..... 0110011 @r
  grev       0110100 .......... 101 ..... 0110011 @r
  gorc       0010100 .......... 101 ..... 0110011 @r
 -sh1add     0010000 .......... 010 ..... 0110011 @r
 -sh2add     0010000 .......... 100 ..... 0110011 @r
 -sh3add     0010000 .......... 110 ..... 0110011 @r
  bseti      00101. ........... 001 ..... 0010011 @sh
  bclri      01001. ........... 001 ..... 0010011 @sh
@@ -XXX,XX +XXX,XX @@ rorw       0110000 .......... 101 ..... 0111011 @r
  rolw       0110000 .......... 001 ..... 0111011 @r
  grevw      0110100 .......... 101 ..... 0111011 @r
  gorcw      0010100 .......... 101 ..... 0111011 @r
 -sh1add_uw  0010000 .......... 010 ..... 0111011 @r
 -sh2add_uw  0010000 .......... 100 ..... 0111011 @r
 -sh3add_uw  0010000 .......... 110 ..... 0111011 @r
 -add_uw     0000100 .......... 000 ..... 0111011 @r
  bsetiw     0010100 .......... 001 ..... 0011011 @sh5
  bclriw     0100100 .......... 001 ..... 0011011 @sh5
@@ -XXX,XX +XXX,XX @@ roriw      0110000 .......... 101 ..... 0011011 @sh5
  greviw     0110100 .......... 101 ..... 0011011 @sh5
  gorciw     0010100 .......... 101 ..... 0011011 @sh5
 -slli_uw    00001. ........... 001 ..... 0011011 @sh
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
  /*
 - * RISC-V translation routines for the RVB Standard Extension.
 + * RISC-V translation routines for the RVB draft and Zba Standard Extension.
   *
   * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
   * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
 + * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
   *
   * This program is free software; you can redistribute it and/or modify it
   * under the terms and conditions of the GNU General Public License,
@@ -XXX,XX +XXX,XX @@
   * this program.  If not, see <http://www.gnu.org/licenses/>.
   */
 +#define REQUIRE_ZBA(ctx) do {                    \
 +    if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) {      \
 +        return false;                            \
 +    }                                            \
 +} while (0)
  static void gen_clz(TCGv ret, TCGv arg1)
  {
@@ -XXX,XX +XXX,XX @@ GEN_SHADD(3)
  #define GEN_TRANS_SHADD(SHAMT)                                             \
  static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
  {                                                                          \
 -    REQUIRE_EXT(ctx, RVB);                                                 \
 +    REQUIRE_ZBA(ctx);                                                      \
      return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
                                      arg_sh##SHAMT##add_uw *a) \
  {                                                             \
      REQUIRE_64BIT(ctx);                                       \
 -    REQUIRE_EXT(ctx, RVB);                                    \
 +    REQUIRE_ZBA(ctx);                                         \
      return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
  }
@@ -XXX,XX +XXX,XX @@ static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
  static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBA(ctx);
      return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
  static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBA(ctx);
      return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
  }
 --
-.31.1
+.45.1

-New patch
+[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+We're not setting (s/m)tval when triggering breakpoints of type 2
+(mcontrol) and 6 (mcontrol6). According to the debug spec section
+.7.12, "Match Control Type 6":
+"The Privileged Spec says that breakpoint exceptions that occur on
+instruction fetches, loads, or stores update the tval CSR with either
+zero or the faulting virtual address. The faulting virtual address for
+an mcontrol6 trigger with action = 0 is the address being accessed and
+which caused that trigger to fire."
+A similar text is also found in the Debug spec section 5.7.11 w.r.t.
+mcontrol.
+Note that what we're doing ATM is not violating the spec, but it's
+simple enough to set mtval/stval and it makes life easier for any
+software that relies on this info.
+Given that we always use action = 0, save the faulting address for the
+mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
+used as as scratch area for traps with address information. 'tval' is
+then set during riscv_cpu_do_interrupt().
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu_helper.c | 1 +
+ target/riscv/debug.c      | 3 +++
+files changed, 4 insertions(+)
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+             tval = env->bins;
+             break;
+         case RISCV_EXCP_BREAKPOINT:
++            tval = env->badaddr;
+             if (cs->watchpoint_hit) {
+                 tval = cs->watchpoint_hit->hitaddr;
+                 cs->watchpoint_hit = NULL;
+diff --git a/target/riscv/debug.c b/target/riscv/debug.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/debug.c
++++ b/target/riscv/debug.c
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
+                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
+                     /* check U/S/M bit against current privilege level */
+                     if ((ctrl >> 3) & BIT(env->priv)) {
++                        env->badaddr = pc;
+                         return true;
+                     }
+                 }
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
+                     if (env->virt_enabled) {
+                         /* check VU/VS bit against current privilege level */
+                         if ((ctrl >> 23) & BIT(env->priv)) {
++                            env->badaddr = pc;
+                             return true;
+                         }
+                     } else {
+                         /* check U/S/M bit against current privilege level */
+                         if ((ctrl >> 3) & BIT(env->priv)) {
++                            env->badaddr = pc;
+                             return true;
+                         }
+                     }
+--
+.45.1

-New patch
+[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Privileged spec section 4.1.9 mentions:
+"When a trap is taken into S-mode, stval is written with
+exception-specific information to assist software in handling the trap.
+(...)
+If stval is written with a nonzero value when a breakpoint,
+address-misaligned, access-fault, or page-fault exception occurs on an
+instruction fetch, load, or store, then stval will contain the faulting
+virtual address."
+A similar text is found for mtval in section 3.1.16.
+Setting mtval/stval in this scenario is optional, but some softwares read
+these regs when handling ebreaks.
+Write 'badaddr' in all ebreak breakpoints to write the appropriate
+'tval' during riscv_do_cpu_interrrupt().
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
+file changed, 2 insertions(+)
+diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_privileged.c.inc
++++ b/target/riscv/insn_trans/trans_privileged.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
+     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
+         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
+     } else {
++        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
++                      offsetof(CPURISCVState, badaddr));
+         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
+     }
+     return true;
+--
+.45.1

-[PULL 08/26] target/riscv: Reassign instructions to the Zbs-extension
+[PULL 10/28] target/riscv: Add support for Zve32x extension
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Jason Chien <jason.chien@sifive.com>
-The following instructions are part of Zbs:
+Add support for Zve32x extension and replace some checks for Zve32f with
- - b{set,clr,ext,inv}
+Zve32x, since Zve32f depends on Zve32x.
  - b{set,clr,ext,inv}i
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
-Acked-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-id: 20210911140016.834071-9-philipp.tomsich@vrull.eu
+Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn32.decode              | 17 +++++++++--------
+ target/riscv/cpu_cfg.h                  |  1 +
- target/riscv/insn_trans/trans_rvb.c.inc | 25 +++++++++++++++----------
+ target/riscv/cpu.c                      |  2 ++
-files changed, 24 insertions(+), 18 deletions(-)
+ target/riscv/cpu_helper.c               |  2 +-
  target/riscv/csr.c                      |  2 +-
  target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
  target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 files changed, 15 insertions(+), 12 deletions(-)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@ min        0000101 .......... 100 ..... 0110011 @r
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
- minu       0000101 .......... 101 ..... 0110011 @r
+     bool ext_zhinx;
- max        0000101 .......... 110 ..... 0110011 @r
+     bool ext_zhinxmin;
- maxu       0000101 .......... 111 ..... 0110011 @r
+     bool ext_zve32f;
--bset       0010100 .......... 001 ..... 0110011 @r
++    bool ext_zve32x;
--bclr       0100100 .......... 001 ..... 0110011 @r
+     bool ext_zve64f;
--binv       0110100 .......... 001 ..... 0110011 @r
+     bool ext_zve64d;
--bext       0100100 .......... 101 ..... 0110011 @r
+     bool ext_zvbb;
- ror        0110000 .......... 101 ..... 0110011 @r
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
  rol        0110000 .......... 001 ..... 0110011 @r
  grev       0110100 .......... 101 ..... 0110011 @r
  gorc       0010100 .......... 101 ..... 0110011 @r
 -bseti      00101. ........... 001 ..... 0010011 @sh
 -bclri      01001. ........... 001 ..... 0010011 @sh
 -binvi      01101. ........... 001 ..... 0010011 @sh
 -bexti      01001. ........... 101 ..... 0010011 @sh
  rori       01100. ........... 101 ..... 0010011 @sh
  grevi      01101. ........... 101 ..... 0010011 @sh
  gorci      00101. ........... 101 ..... 0010011 @sh
@@ -XXX,XX +XXX,XX @@ roriw      0110000 .......... 101 ..... 0011011 @sh5
  greviw     0110100 .......... 101 ..... 0011011 @sh5
  gorciw     0010100 .......... 101 ..... 0011011 @sh5
 +# *** RV32 Zbs Standard Extension ***
 +bclr       0100100 .......... 001 ..... 0110011 @r
 +bclri      01001. ........... 001 ..... 0010011 @sh
 +bext       0100100 .......... 101 ..... 0110011 @r
 +bexti      01001. ........... 101 ..... 0010011 @sh
 +binv       0110100 .......... 001 ..... 0110011 @r
 +binvi      01101. ........... 001 ..... 0010011 @sh
 +bset       0010100 .......... 001 ..... 0110011 @r
 +bseti      00101. ........... 001 ..... 0010011 @sh
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
- /*
+     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
-- * RISC-V translation routines for the RVB draft and Zba Standard Extension.
+     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
-+ * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
+     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
-  *
++    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
-  * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
-  * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
-@@ -XXX,XX +XXX,XX @@
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
-     }                                            \
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
- } while (0)
+     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
+     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
-+#define REQUIRE_ZBS(ctx) do {                    \
+     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
-+    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
++    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
-+        return false;                            \
+     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
-+    }                                            \
+     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
-+} while (0)
+     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
-+
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
- static void gen_clz(TCGv ret, TCGv arg1)
+index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
      *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
      *cs_base = 0;
 -    if (cpu->cfg.ext_zve32f) {
 +    if (cpu->cfg.ext_zve32x) {
          /*
           * If env->vl equals to VLMAX, we can use generic vector operation
           * expanders (GVEC) to accerlate the vector operations.
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
  static RISCVException vs(CPURISCVState *env, int csrno)
  {
-     tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
+-    if (riscv_cpu_cfg(env)->ext_zve32f) {
- }
++    if (riscv_cpu_cfg(env)->ext_zve32x) {
--
+ #if !defined(CONFIG_USER_ONLY)
- static bool trans_clz(DisasContext *ctx, arg_clz *a)
+         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
              return RISCV_EXCP_ILLEGAL_INST;
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          return;
      }
 -    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
 -        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 -        return;
 +    /* The Zve32f extension depends on the Zve32x extension */
 +    if (cpu->cfg.ext_zve32f) {
 +        if (!riscv_has_ext(env, RVF)) {
 +            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 +            return;
 +        }
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
      }
      if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
      }
 -    /*
 -     * In principle Zve*x would also suffice here, were they supported
 -     * in qemu
 -     */
      if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
           cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
 -         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
 +         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
          error_setg(errp,
                     "Vector crypto extensions require V or Zve* extensions");
          return;
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
  {
-     REQUIRE_EXT(ctx, RVB);
+     TCGv s1, dst;
-@@ -XXX,XX +XXX,XX @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
+-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
- static bool trans_bset(DisasContext *ctx, arg_bset *a)
++    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
          return false;
      }
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
  {
--    REQUIRE_EXT(ctx, RVB);
+     TCGv dst;
-+    REQUIRE_ZBS(ctx);
-     return gen_shift(ctx, a, EXT_NONE, gen_bset);
+-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
- }
++    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
+         return false;
- static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
+     }
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBS(ctx);
      return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
  static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBS(ctx);
      return gen_shift(ctx, a, EXT_NONE, gen_bclr);
  }
  static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBS(ctx);
      return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
  static bool trans_binv(DisasContext *ctx, arg_binv *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBS(ctx);
      return gen_shift(ctx, a, EXT_NONE, gen_binv);
  }
  static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBS(ctx);
      return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
  static bool trans_bext(DisasContext *ctx, arg_bext *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBS(ctx);
      return gen_shift(ctx, a, EXT_NONE, gen_bext);
  }
  static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBS(ctx);
      return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
  }
 --
-.31.1
+.45.1

-[PULL 21/26] hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition
+[PULL 11/28] target/riscv: Add support for Zve64x extension
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Jason Chien <jason.chien@sifive.com>
-The current MCHP_PFSOC_MMUART_REG_SIZE definition represent the
+Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
-size occupied by all the registers. However all registers are
+enabling Zve64x enables Zve32x according to their dependency.
 -bit wide, and the MemoryRegionOps handlers are restricted to
 -bit:
-  static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
-      .read = mchp_pfsoc_mmuart_read,
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-      .write = mchp_pfsoc_mmuart_write,
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-      .impl = {
+Reviewed-by: Max Chou <max.chou@sifive.com>
-          .min_access_size = 4,
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-          .max_access_size = 4,
+Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
       },
 Avoid being triskaidekaphobic, simplify by using the number of
 registers.
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Bin Meng <bin.meng@windriver.com>
 Tested-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210925133407.1259392-2-f4bug@amsat.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/char/mchp_pfsoc_mmuart.h |  4 ++--
+ target/riscv/cpu_cfg.h     |  1 +
- hw/char/mchp_pfsoc_mmuart.c         | 14 ++++++++------
+ target/riscv/cpu.c         |  2 ++
-files changed, 10 insertions(+), 8 deletions(-)
+ target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 files changed, 14 insertions(+), 6 deletions(-)
-diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/mchp_pfsoc_mmuart.h
+--- a/target/riscv/cpu_cfg.h
-+++ b/include/hw/char/mchp_pfsoc_mmuart.h
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+     bool ext_zve32x;
- #include "hw/char/serial.h"
+     bool ext_zve64f;
+     bool ext_zve64d;
--#define MCHP_PFSOC_MMUART_REG_SIZE  52
++    bool ext_zve64x;
-+#define MCHP_PFSOC_MMUART_REG_COUNT 13
+     bool ext_zvbb;
+     bool ext_zvbc;
- typedef struct MchpPfSoCMMUartState {
+     bool ext_zvkb;
-     MemoryRegion iomem;
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ typedef struct MchpPfSoCMMUartState {
      SerialMM *serial;
 -    uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
 +    uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT];
  } MchpPfSoCMMUartState;
  /**
 diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/mchp_pfsoc_mmuart.c
+--- a/target/riscv/cpu.c
-+++ b/hw/char/mchp_pfsoc_mmuart.c
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
- {
+     ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
-     MchpPfSoCMMUartState *s = opaque;
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
--    if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
++    ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
-+    addr >>= 2;
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
-+    if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
+     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
-         qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
+     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
--                      __func__, addr);
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-+                      __func__, addr << 2);
+     MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
-         return 0;
+     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
      MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
 +    MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
      MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
      MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
      MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
      /* The Zve64d extension depends on the Zve64f extension */
      if (cpu->cfg.ext_zve64d) {
 +        if (!riscv_has_ext(env, RVD)) {
 +            error_setg(errp, "Zve64d/V extensions require D extension");
 +            return;
 +        }
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
      }
--    return s->reg[addr / sizeof(uint32_t)];
+-    /* The Zve64f extension depends on the Zve32f extension */
-+    return s->reg[addr];
++    /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
- }
+     if (cpu->cfg.ext_zve64f) {
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
- static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
-@@ -XXX,XX +XXX,XX @@ static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
+     }
-     MchpPfSoCMMUartState *s = opaque;
-     uint32_t val32 = (uint32_t)value;
+-    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
+-        error_setg(errp, "Zve64d/V extensions require D extension");
--    if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
+-        return;
-+    addr >>= 2;
++    /* The Zve64x extension depends on the Zve32x extension */
-+    if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
++    if (cpu->cfg.ext_zve64x) {
-         qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
--                      " v=0x%x\n", __func__, addr, val32);
+     }
-+                      " v=0x%x\n", __func__, addr << 2, val32);
      /* The Zve32f extension depends on the Zve32x extension */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          return;
      }
--    s->reg[addr / sizeof(uint32_t)] = val32;
+-    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
-+    s->reg[addr] = val32;
++    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
- }
+         error_setg(
+             errp,
- static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
+-            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
 +            "Zvbc and Zvknhb extensions require V or Zve64x extensions");
          return;
      }
 --
-.31.1
+.45.1

-[PULL 24/26] hw/dma: sifive_pdma: Fix Control.claim bit detection
+[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
-From: Bin Meng <bmeng.cn@gmail.com>
+From: Jason Chien <jason.chien@sifive.com>
-At present the codes detect whether the DMA channel is claimed by:
+In current implementation, the gdbstub allows reading vector registers
 only if V extension is supported. However, all vector extensions and
 vector crypto extensions have the vector registers and they all depend
 on Zve32x. The gdbstub should check for Zve32x instead.
-  claimed = !!s->chan[ch].control & CONTROL_CLAIM;
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-As ! has higher precedence over & (bitwise and), this is essentially
+Reviewed-by: Max Chou <max.chou@sifive.com>
+Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
   claimed = (!!s->chan[ch].control) & CONTROL_CLAIM;
 which is wrong, as any non-zero bit set in the control register will
 produce a result of a claimed channel.
 Fixes: de7c7988d25d ("hw/dma: sifive_pdma: reset Next* registers when Control.claim is set")
 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20210927072124.1564129-1-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/dma/sifive_pdma.c | 2 +-
+ target/riscv/gdbstub.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/dma/sifive_pdma.c
+--- a/target/riscv/gdbstub.c
-+++ b/hw/dma/sifive_pdma.c
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
-     offset &= 0xfff;
+                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
-     switch (offset) {
+);
-     case DMA_CONTROL:
+     }
--        claimed = !!s->chan[ch].control & CONTROL_CLAIM;
+-    if (env->misa_ext & RVV) {
-+        claimed = !!(s->chan[ch].control & CONTROL_CLAIM);
++    if (cpu->cfg.ext_zve32x) {
+         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
-         if (!claimed && (value & CONTROL_CLAIM)) {
+                                  riscv_gdb_set_vector,
-             /* reset Next* registers */
+                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
 --
-.31.1
+.45.1

-[PULL 20/26] hw/char: sifive_uart: Register device in 'input' category
+[PULL 13/28] target/riscv: Fix the element agnostic function problem
-From: Bin Meng <bmeng.cn@gmail.com>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-The category of sifive_uart device is not set. Put it into the
+In RVV and vcrypto instructions, the masked and tail elements are set to 1s
-'input' category.
+using vext_set_elems_1s function if the vma/vta bit is set. It is the element
 agnostic policy.
-Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
+However, this function can't deal the big endian situation. This patch fixes
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+the problem by adding handling of such case.
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210926105003.2716-3-bmeng.cn@gmail.com
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
 Suggested-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/char/sifive_uart.c | 1 +
+ target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
-file changed, 1 insertion(+)
+file changed, 22 insertions(+)
-diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
+diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/sifive_uart.c
+--- a/target/riscv/vector_internals.c
-+++ b/hw/char/sifive_uart.c
++++ b/target/riscv/vector_internals.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_uart_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
-     rc->phases.enter = sifive_uart_reset_enter;
+     if (tot - cnt == 0) {
-     rc->phases.hold  = sifive_uart_reset_hold;
+         return ;
-     device_class_set_props(dc, sifive_uart_properties);
+     }
-+    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
++
 +    if (HOST_BIG_ENDIAN) {
 +        /*
 +         * Deal the situation when the elements are insdie
 +         * only one uint64 block including setting the
 +         * masked-off element.
 +         */
 +        if (((tot - 1) ^ cnt) < 8) {
 +            memset(base + H1(tot - 1), -1, tot - cnt);
 +            return;
 +        }
 +        /*
 +         * Otherwise, at least cross two uint64_t blocks.
 +         * Set first unaligned block.
 +         */
 +        if (cnt % 8 != 0) {
 +            uint32_t j = ROUND_UP(cnt, 8);
 +            memset(base + H1(j - 1), -1, j - cnt);
 +            cnt = j;
 +        }
 +        /* Set other 64bit aligend blocks */
 +    }
      memset(base + cnt, -1, tot - cnt);
  }
- static const TypeInfo sifive_uart_info = {
 --
-.31.1
+.45.1

-[PULL 02/26] target/riscv: fix clzw implementation to operate on arg1
+[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Yangyu Chen <cyy@cyyself.name>
-The refactored gen_clzw() uses ret as its argument, instead of arg1.
+This code has a typo that writes zvkb to zvkg, causing users can't
-Fix it.
+enable zvkb through the config. This patch gets this fixed.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Signed-off-by: Yangyu Chen <cyy@cyyself.name>
 Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
-Message-id: 20210911140016.834071-3-philipp.tomsich@vrull.eu
+Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
-Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary")
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvb.c.inc | 2 +-
+ target/riscv/cpu.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(3)
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+     /* Vector cryptography extensions */
- static void gen_clzw(TCGv ret, TCGv arg1)
+     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
- {
+     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
--    tcg_gen_clzi_tl(ret, ret, 64);
+-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
-+    tcg_gen_clzi_tl(ret, arg1, 64);
++    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
-     tcg_gen_subi_tl(ret, ret, 32);
+     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
- }
+     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
+     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
 --
-.31.1
+.45.1

-[PULL 15/26] target/riscv: Remove RVB (replaced by Zb[abcs])
+[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-With everything classified as Zb[abcs] and pre-0.93 draft-B
+In this patch, we modify the decoder to be a freely composable data
-instructions that are not part of Zb[abcs] removed, we can remove the
+structure instead of a hardcoded one. It can be dynamically builded up
-remaining support code for RVB.
+according to the extensions.
 This approach has several benefits:
 . Provides support for heterogeneous cpu architectures. As we add decoder in
    RISCVCPU, each cpu can have their own decoder, and the decoders can be
    different due to cpu's features.
 . Improve the decoding efficiency. We run the guard_func to see if the decoder
    can be added to the dynamic_decoder when building up the decoder. Therefore,
    there is no need to run the guard_func when decoding each instruction. It can
    improve the decoding efficiency
 . For vendor or dynamic cpus, it allows them to customize their own decoder
    functions to improve decoding efficiency, especially when vendor-defined
    instruction sets increase. Because of dynamic building up, it can skip the other
    decoder guard functions when decoding.
 . Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
    overhead for users that don't need this particular vendor decoder.
-Note that RVB has been retired for good and misa.B will neither mean
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
-'some' or 'all of' Zb*:
+Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
-  https://lists.riscv.org/g/tech-bitmanip/message/532
+Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
 Message-id: 20210911140016.834071-16-philipp.tomsich@vrull.eu
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h         |  3 ---
+ target/riscv/cpu.h         |  1 +
- target/riscv/insn32.decode |  4 ----
+ target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
- target/riscv/cpu.c         | 26 --------------------------
+ target/riscv/cpu.c         |  1 +
-files changed, 33 deletions(-)
+ target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
  target/riscv/translate.c   | 31 +++++++++++++++----------------
 files changed, 47 insertions(+), 16 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
- #define RVS RV('S')
+     uint32_t pmu_avail_ctrs;
- #define RVU RV('U')
+     /* Mapping of events to counters */
- #define RVH RV('H')
+     GHashTable *pmu_event_ctr_map;
--#define RVB RV('B')
++    const GPtrArray *decoders;
+ };
- /* S extension denotes that Supervisor mode exists, however it is possible
-    to have a core that support S mode but does not have an MMU and there
+ /**
-@@ -XXX,XX +XXX,XX @@ enum {
+diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
  #define PRIV_VERSION_1_10_0 0x00011000
  #define PRIV_VERSION_1_11_0 0x00011100
 -#define BEXT_VERSION_0_93_0 0x00009300
  #define VEXT_VERSION_0_07_1 0x00000701
  enum {
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
          bool ext_f;
          bool ext_d;
          bool ext_c;
 -        bool ext_b;
          bool ext_s;
          bool ext_u;
          bool ext_h;
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/tcg/tcg-cpu.h
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/tcg/tcg-cpu.h
-@@ -XXX,XX +XXX,XX @@ rorw       0110000 .......... 101 ..... 0111011 @r
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
- # instruction, so we use different handler functions to differentiate.
+ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
- zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
+ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
--# *** RV32B Standard Extension ***
++struct DisasContext;
--
++struct RISCVCPUConfig;
--# *** RV64B Standard Extension (in addition to RV32B) ***
++typedef struct RISCVDecoder {
--
++    bool (*guard_func)(const struct RISCVCPUConfig *);
- # *** RV32 Zbc Standard Extension ***
++    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
- clmul      0000101 .......... 001 ..... 0110011 @r
++} RISCVDecoder;
- clmulh     0000101 .......... 011 ..... 0110011 @r
++
 +typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
 +
 +extern const size_t decoder_table_size;
 +
 +extern const RISCVDecoder decoder_table[];
 +
 +void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
 +
  #endif
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
-     env->priv_ver = priv_ver;
+             error_propagate(errp, local_err);
              return;
          }
 +        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
      } else if (kvm_enabled()) {
          riscv_kvm_cpu_finalize_features(cpu, &local_err);
          if (local_err != NULL) {
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
      }
  }
--static void set_bext_version(CPURISCVState *env, int bext_ver)
++void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
--{
++{
--    env->bext_ver = bext_ver;
++    GPtrArray *dynamic_decoders;
--}
++    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
 +    for (size_t i = 0; i < decoder_table_size; ++i) {
 +        if (decoder_table[i].guard_func &&
 +            decoder_table[i].guard_func(&cpu->cfg)) {
 +            g_ptr_array_add(dynamic_decoders,
 +                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
 +        }
 +    }
 +
 +    cpu->decoders = dynamic_decoders;
 +}
 +
  bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
  {
      return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/helper-info.c.inc"
  #undef  HELPER_H
 +#include "tcg/tcg-cpu.h"
 +
  /* global register indices */
  static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
  static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      /* FRM is known to contain a valid value. */
      bool frm_valid;
      bool insn_start_updated;
 +    const GPtrArray *decoders;
  } DisasContext;
  static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
      return (first_word & 3) == 3 ? 4 : 2;
  }
 +const RISCVDecoder decoder_table[] = {
 +    { always_true_p, decode_insn32 },
 +    { has_xthead_p, decode_xthead},
 +    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
 +};
 +
 +const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
 +
  static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
  {
 -    /*
 -     * A table with predicate (i.e., guard) functions and decoder functions
 -     * that are tested in-order until a decoder matches onto the opcode.
 -     */
 -    static const struct {
 -        bool (*guard_func)(const RISCVCPUConfig *);
 -        bool (*decode_func)(DisasContext *, uint32_t);
 -    } decoders[] = {
 -        { always_true_p,  decode_insn32 },
 -        { has_xthead_p, decode_xthead },
 -        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
 -    };
 -
- static void set_vext_version(CPURISCVState *env, int vext_ver)
+     ctx->virt_inst_excp = false;
- {
+     ctx->cur_insn_len = insn_len(opcode);
-     env->vext_ver = vext_ver;
+     /* Check for compressed insn */
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
-         if (cpu->cfg.ext_h) {
+                                              ctx->base.pc_next + 2));
-             target_misa |= RVH;
+         ctx->opcode = opcode32;
 -        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
 -            if (decoders[i].guard_func(ctx->cfg_ptr) &&
 -                decoders[i].decode_func(ctx, opcode32)) {
 +        for (guint i = 0; i < ctx->decoders->len; ++i) {
 +            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
 +            if (func(ctx, opcode32)) {
                  return;
              }
          }
--        if (cpu->cfg.ext_b) {
+@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
--            int bext_version = BEXT_VERSION_0_93_0;
+     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
--            target_misa |= RVB;
+     ctx->zero = tcg_constant_tl(0);
--
+     ctx->virt_inst_excp = false;
--            if (cpu->cfg.bext_spec) {
++    ctx->decoders = cpu->decoders;
--                if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
+ }
--                    bext_version = BEXT_VERSION_0_93_0;
--                } else {
+ static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 -                    error_setg(errp,
 -                           "Unsupported bitmanip spec version '%s'",
 -                           cpu->cfg.bext_spec);
 -                    return;
 -                }
 -            } else {
 -                qemu_log("bitmanip version is not specified, "
 -                         "use the default value v0.93\n");
 -            }
 -            set_bext_version(env, bext_version);
 -        }
          if (cpu->cfg.ext_v) {
              int vext_version = VEXT_VERSION_0_07_1;
              target_misa |= RVV;
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
      DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
      /* This is experimental so mark with 'x-' */
 -    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
      DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
      DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
      DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
      DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
      DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
      DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
 -    DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
      DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
      DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
      DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 --
-.31.1
+.45.1

-[PULL 04/26] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
+[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Christoph Müllner <christoph.muellner@vrull.eu>
-The bitmanipulation ISA extensions will be ratified as individual
+The th.sxstatus CSR can be used to identify available custom extension
-small extension packages instead of a large B-extension.  The first
+on T-Head CPUs. The CSR is documented here:
-new instructions through the door (these have completed public review)
+  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
 are Zb[abcs].
-This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
+An important property of this patch is, that the th.sxstatus MAEE field
-these in target/riscv/cpu.[ch].
+is not set (indicating that XTheadMae is not available).
 XTheadMae is a memory attribute extension (similar to Svpbmt) which is
 implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
 in PTEs that are marked as reserved. QEMU maintainers prefer to not
 implement XTheadMae, so we need give kernels a mechanism to identify
 if XTheadMae is available in a system or not. And this patch introduces
 this mechanism in QEMU in a way that's compatible with real HW
 (i.e., probing the th.sxstatus.MAEE bit).
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Further context can be found on the list:
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
 Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
-Message-id: 20210911140016.834071-5-philipp.tomsich@vrull.eu
+Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h | 4 ++++
+ MAINTAINERS              |  1 +
- target/riscv/cpu.c | 4 ++++
+ target/riscv/cpu.h       |  3 ++
-files changed, 8 insertions(+)
+ target/riscv/cpu.c       |  1 +
  target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
  target/riscv/meson.build |  1 +
 files changed, 85 insertions(+)
  create mode 100644 target/riscv/th_csr.c
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
+ S: Supported
+ F: target/riscv/insn_trans/trans_xthead.c.inc
+ F: target/riscv/xthead*.decode
++F: target/riscv/th_*
+ F: disas/riscv-xthead*
+ RISC-V XVentanaCondOps extension
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
+@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
-         bool ext_u;
+ uint8_t satp_mode_max_from_map(uint32_t map);
-         bool ext_h;
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
-         bool ext_v;
-+        bool ext_zba;
++/* Implemented in th_csr.c */
-+        bool ext_zbb;
++void th_register_custom_csrs(RISCVCPU *cpu);
-+        bool ext_zbc;
++
-+        bool ext_zbs;
+ #endif /* RISCV_CPU_H */
          bool ext_counters;
          bool ext_ifencei;
          bool ext_icsr;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
-     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
+     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
-     /* This is experimental so mark with 'x-' */
+ #ifndef CONFIG_USER_ONLY
-     DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
+     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
-+    DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
++    th_register_custom_csrs(cpu);
-+    DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
+ #endif
-+    DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
-+    DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
+     /* inherited from parent obj via riscv_cpu_init() */
-     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
-     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
+new file mode 100644
-     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/riscv/th_csr.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * T-Head-specific CSRs.
 + *
 + * Copyright (c) 2024 VRULL GmbH
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "cpu.h"
 +#include "cpu_vendorid.h"
 +
 +#define CSR_TH_SXSTATUS 0x5c0
 +
 +/* TH_SXSTATUS bits */
 +#define TH_SXSTATUS_UCME        BIT(16)
 +#define TH_SXSTATUS_MAEE        BIT(21)
 +#define TH_SXSTATUS_THEADISAEE  BIT(22)
 +
 +typedef struct {
 +    int csrno;
 +    int (*insertion_test)(RISCVCPU *cpu);
 +    riscv_csr_operations csr_ops;
 +} riscv_csr;
 +
 +static RISCVException smode(CPURISCVState *env, int csrno)
 +{
 +    if (riscv_has_ext(env, RVS)) {
 +        return RISCV_EXCP_NONE;
 +    }
 +
 +    return RISCV_EXCP_ILLEGAL_INST;
 +}
 +
 +static int test_thead_mvendorid(RISCVCPU *cpu)
 +{
 +    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
 +        return -1;
 +    }
 +
 +    return 0;
 +}
 +
 +static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
 +                                       target_ulong *val)
 +{
 +    /* We don't set MAEE here, because QEMU does not implement MAEE. */
 +    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static riscv_csr th_csr_list[] = {
 +    {
 +        .csrno = CSR_TH_SXSTATUS,
 +        .insertion_test = test_thead_mvendorid,
 +        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
 +    }
 +};
 +
 +void th_register_custom_csrs(RISCVCPU *cpu)
 +{
 +    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
 +        int csrno = th_csr_list[i].csrno;
 +        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
 +        if (!th_csr_list[i].insertion_test(cpu)) {
 +            riscv_set_csr_ops(csrno, csr_ops);
 +        }
 +    }
 +}
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/meson.build
 +++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
    'monitor.c',
    'machine.c',
    'pmu.c',
 +  'th_csr.c',
    'time_helper.c',
    'riscv-qmp-cmds.c',
  ))
 --
-.31.1
+.45.1

-[PULL 19/26] hw/char: shakti_uart: Register device in 'input' category
+[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
-From: Bin Meng <bmeng.cn@gmail.com>
+From: Max Chou <max.chou@sifive.com>
-The category of shakti_uart device is not set. Put it into the
+According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
-'input' category.
+instructions will be affected by Zvfhmin extension.
 And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
 conversions of
-Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
+* From 1*SEW(16/32) to 2*SEW(32/64)
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+* From 2*SEW(32/64) to 1*SEW(16/32)
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210926105003.2716-2-bmeng.cn@gmail.com
+Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/char/shakti_uart.c | 1 +
+ target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
-file changed, 1 insertion(+)
+file changed, 18 insertions(+), 2 deletions(-)
-diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/shakti_uart.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/hw/char/shakti_uart.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static void shakti_uart_class_init(ObjectClass *klass, void *data)
+@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
-     dc->reset = shakti_uart_reset;
+     }
      dc->realize = shakti_uart_realize;
      device_class_set_props(dc, shakti_uart_properties);
 +    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
  }
- static const TypeInfo shakti_uart_info = {
++static bool require_rvfmin(DisasContext *s)
 +{
 +    if (s->mstatus_fs == EXT_STATUS_DISABLED) {
 +        return false;
 +    }
 +
 +    switch (s->sew) {
 +    case MO_16:
 +        return s->cfg_ptr->ext_zvfhmin;
 +    case MO_32:
 +        return s->cfg_ptr->ext_zve32f;
 +    default:
 +        return false;
 +    }
 +}
 +
  static bool require_scale_rvf(DisasContext *s)
  {
      if (s->mstatus_fs == EXT_STATUS_DISABLED) {
@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
      }
      switch (s->sew) {
 -    case MO_8:
 -        return s->cfg_ptr->ext_zvfhmin;
      case MO_16:
          return s->cfg_ptr->ext_zve32f;
      case MO_32:
@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
  static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_widen_check(s, a) &&
 +           require_rvfmin(s) &&
             require_scale_rvfmin(s) &&
             (s->sew != MO_8);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
  static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_narrow_check(s, a) &&
 +           require_rvfmin(s) &&
             require_scale_rvfmin(s) &&
             (s->sew != MO_8);
  }
 --
-.31.1
+.45.1

-[PULL 10/26] target/riscv: Reassign instructions to the Zbb-extension
+[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Max Chou <max.chou@sifive.com>
-This reassigns the instructions that are part of Zbb into it, with the
+The require_scale_rvf function only checks the double width operator for
-notable exceptions of the instructions (rev8, zext.w and orc.b) that
+the vector floating point widen instructions, so most of the widen
-changed due to gorci, grevi and pack not being part of Zb[abcs].
+checking functions need to add require_rvf for single width operator.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+integer to double width float, so the opfxv_widen_check function doesn’t
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+need require_rvf for the single width operator(integer).
-Acked-by: Bin Meng <bmeng.cn@gmail.com>
-Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu
+Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn32.decode              | 40 ++++++++++---------
+ target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
- target/riscv/insn_trans/trans_rvb.c.inc | 51 ++++++++++++++-----------
+file changed, 5 insertions(+)
 files changed, 50 insertions(+), 41 deletions(-)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ sh2add_uw  0010000 .......... 100 ..... 0111011 @r
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf,  opfvf_check)
- sh3add_uw  0010000 .......... 110 ..... 0111011 @r
+ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
  slli_uw    00001 ............ 001 ..... 0011011 @sh
 -# *** RV32B Standard Extension ***
 +# *** RV32 Zbb Standard Extension ***
 +andn       0100000 .......... 111 ..... 0110011 @r
  clz        011000 000000 ..... 001 ..... 0010011 @r2
 -ctz        011000 000001 ..... 001 ..... 0010011 @r2
  cpop       011000 000010 ..... 001 ..... 0010011 @r2
 +ctz        011000 000001 ..... 001 ..... 0010011 @r2
 +max        0000101 .......... 110 ..... 0110011 @r
 +maxu       0000101 .......... 111 ..... 0110011 @r
 +min        0000101 .......... 100 ..... 0110011 @r
 +minu       0000101 .......... 101 ..... 0110011 @r
 +orn        0100000 .......... 110 ..... 0110011 @r
 +rol        0110000 .......... 001 ..... 0110011 @r
 +ror        0110000 .......... 101 ..... 0110011 @r
 +rori       01100 ............ 101 ..... 0010011 @sh
  sext_b     011000 000100 ..... 001 ..... 0010011 @r2
  sext_h     011000 000101 ..... 001 ..... 0010011 @r2
 -
 -andn       0100000 .......... 111 ..... 0110011 @r
 -orn        0100000 .......... 110 ..... 0110011 @r
  xnor       0100000 .......... 100 ..... 0110011 @r
 +
 +# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
 +clzw       0110000 00000 ..... 001 ..... 0011011 @r2
 +ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
 +cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
 +rolw       0110000 .......... 001 ..... 0111011 @r
 +roriw      0110000 .......... 101 ..... 0011011 @sh5
 +rorw       0110000 .......... 101 ..... 0111011 @r
 +
 +# *** RV32B Standard Extension ***
  pack       0000100 .......... 100 ..... 0110011 @r
  packu      0100100 .......... 100 ..... 0110011 @r
  packh      0000100 .......... 111 ..... 0110011 @r
 -min        0000101 .......... 100 ..... 0110011 @r
 -minu       0000101 .......... 101 ..... 0110011 @r
 -max        0000101 .......... 110 ..... 0110011 @r
 -maxu       0000101 .......... 111 ..... 0110011 @r
 -ror        0110000 .......... 101 ..... 0110011 @r
 -rol        0110000 .......... 001 ..... 0110011 @r
  grev       0110100 .......... 101 ..... 0110011 @r
  gorc       0010100 .......... 101 ..... 0110011 @r
 -rori       01100. ........... 101 ..... 0010011 @sh
  grevi      01101. ........... 101 ..... 0010011 @sh
  gorci      00101. ........... 101 ..... 0010011 @sh
  # *** RV64B Standard Extension (in addition to RV32B) ***
 -clzw       0110000 00000 ..... 001 ..... 0011011 @r2
 -ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
 -cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
 -
  packw      0000100 .......... 100 ..... 0111011 @r
  packuw     0100100 .......... 100 ..... 0111011 @r
 -rorw       0110000 .......... 101 ..... 0111011 @r
 -rolw       0110000 .......... 001 ..... 0111011 @r
  grevw      0110100 .......... 101 ..... 0111011 @r
  gorcw      0010100 .......... 101 ..... 0111011 @r
 -roriw      0110000 .......... 101 ..... 0011011 @sh5
  greviw     0110100 .......... 101 ..... 0011011 @sh5
  gorciw     0010100 .......... 101 ..... 0011011 @sh5
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
  /*
 - * RISC-V translation routines for the Zb[acs] Standard Extension.
 + * RISC-V translation routines for the Zb[abcs] Standard Extension.
   *
   * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
   * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -XXX,XX +XXX,XX @@
      }                                            \
  } while (0)
 +#define REQUIRE_ZBB(ctx) do {                    \
 +    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) {      \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
  #define REQUIRE_ZBC(ctx) do {                    \
      if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
          return false;                            \
@@ -XXX,XX +XXX,XX @@ static void gen_clz(TCGv ret, TCGv arg1)
  {
-     tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
+     return require_rvv(s) &&
- }
++           require_rvf(s) &&
-+
+            require_scale_rvf(s) &&
- static bool trans_clz(DisasContext *ctx, arg_clz *a)
+            (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
  static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
  {
--    REQUIRE_EXT(ctx, RVB);
+     return require_rvv(s) &&
-+    REQUIRE_ZBB(ctx);
++           require_rvf(s) &&
-     return gen_unary(ctx, a, EXT_ZERO, gen_clz);
+            require_scale_rvf(s) &&
- }
+            (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
-@@ -XXX,XX +XXX,XX @@ static void gen_ctz(TCGv ret, TCGv arg1)
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
+ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
  static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
  {
--    REQUIRE_EXT(ctx, RVB);
+     return require_rvv(s) &&
-+    REQUIRE_ZBB(ctx);
++           require_rvf(s) &&
-     return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
+            require_scale_rvf(s) &&
- }
+            (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
- static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
+@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
  static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
  {
--    REQUIRE_EXT(ctx, RVB);
+     return require_rvv(s) &&
-+    REQUIRE_ZBB(ctx);
++           require_rvf(s) &&
-     return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
+            require_scale_rvf(s) &&
- }
+            (s->sew != MO_8) &&
+            vext_check_isa_ill(s) &&
- static bool trans_andn(DisasContext *ctx, arg_andn *a)
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
  static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
  {
--    REQUIRE_EXT(ctx, RVB);
+     return reduction_widen_check(s, a) &&
-+    REQUIRE_ZBB(ctx);
++           require_rvf(s) &&
-     return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
+            require_scale_rvf(s) &&
- }
+            (s->sew != MO_8);
  static bool trans_orn(DisasContext *ctx, arg_orn *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
  }
  static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
  static bool trans_min(DisasContext *ctx, arg_min *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
  }
  static bool trans_max(DisasContext *ctx, arg_max *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
  }
  static bool trans_minu(DisasContext *ctx, arg_minu *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
  }
  static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
  }
  static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
  }
  static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
  static bool trans_ror(DisasContext *ctx, arg_ror *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
  }
  static bool trans_rori(DisasContext *ctx, arg_rori *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
  }
  static bool trans_rol(DisasContext *ctx, arg_rol *a)
  {
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_clzw(TCGv ret, TCGv arg1)
  static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_unary(ctx, a, EXT_NONE, gen_clzw);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_ctzw(TCGv ret, TCGv arg1)
  static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
  }
  static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      ctx->w = true;
      return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
  static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      ctx->w = true;
      return gen_shift(ctx, a, EXT_NONE, gen_rorw);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
  static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      ctx->w = true;
      return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
  static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
  {
      REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 +    REQUIRE_ZBB(ctx);
      ctx->w = true;
      return gen_shift(ctx, a, EXT_NONE, gen_rolw);
  }
 --
-.31.1
+.45.1

-[PULL 18/26] hw/char: ibex_uart: Register device in 'input' category
+[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
-From: Bin Meng <bmeng.cn@gmail.com>
+From: Max Chou <max.chou@sifive.com>
-The category of ibex_uart device is not set. Put it into the
+The opfv_narrow_check needs to check the single width float operator by
-'input' category.
+require_rvf.
-Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-id: 20210926105003.2716-1-bmeng.cn@gmail.com
+Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/char/ibex_uart.c | 1 +
+ target/riscv/insn_trans/trans_rvv.c.inc | 1 +
 file changed, 1 insertion(+)
-diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/ibex_uart.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/hw/char/ibex_uart.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static void ibex_uart_class_init(ObjectClass *klass, void *data)
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
-     dc->realize = ibex_uart_realize;
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
-     dc->vmsd = &vmstate_ibex_uart;
+ {
-     device_class_set_props(dc, ibex_uart_properties);
+     return opfv_narrow_check(s, a) &&
-+    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
++           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8);
  }
- static const TypeInfo ibex_uart_info = {
 --
-.31.1
+.45.1

-[PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
+[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Max Chou <max.chou@sifive.com>
-The 1.0.0 version of Zbb does not contain gorc/gorci.  Instead, a
+If the checking functions check both the single and double width
-orc.b instruction (equivalent to the orc.b pseudo-instruction built on
+operators at the same time, then the single width operator checking
-gorci from pre-0.93 draft-B) is available, mainly targeting
+functions (require_rvf[min]) will check whether the SEW is 8.
 string-processing workloads.
-This commit adds the new orc.b instruction and removed gorc/gorci.
+Signed-off-by: Max Chou <max.chou@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210911140016.834071-12-philipp.tomsich@vrull.eu
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/helper.h                   |  2 --
+ target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
- target/riscv/insn32.decode              |  6 +---
+file changed, 4 insertions(+), 12 deletions(-)
  target/riscv/bitmanip_helper.c          | 26 -----------------
  target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++--------------
 files changed, 18 insertions(+), 55 deletions(-)
-diff --git a/target/riscv/helper.h b/target/riscv/helper.h
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.h
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/helper.h
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
- /* Bitmanip */
+     return require_rvv(s) &&
- DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+            require_rvf(s) &&
- DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+            require_scale_rvf(s) &&
--DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+-           (s->sew != MO_8) &&
--DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+            vext_check_isa_ill(s) &&
- DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
  DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn32.decode
 +++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ max        0000101 .......... 110 ..... 0110011 @r
  maxu       0000101 .......... 111 ..... 0110011 @r
  min        0000101 .......... 100 ..... 0110011 @r
  minu       0000101 .......... 101 ..... 0110011 @r
 +orc_b      001010 000111 ..... 101 ..... 0010011 @r2
  orn        0100000 .......... 110 ..... 0110011 @r
  rol        0110000 .......... 001 ..... 0110011 @r
  ror        0110000 .......... 101 ..... 0110011 @r
@@ -XXX,XX +XXX,XX @@ pack       0000100 .......... 100 ..... 0110011 @r
  packu      0100100 .......... 100 ..... 0110011 @r
  packh      0000100 .......... 111 ..... 0110011 @r
  grev       0110100 .......... 101 ..... 0110011 @r
 -gorc       0010100 .......... 101 ..... 0110011 @r
 -
  grevi      01101. ........... 101 ..... 0010011 @sh
 -gorci      00101. ........... 101 ..... 0010011 @sh
  # *** RV64B Standard Extension (in addition to RV32B) ***
  packw      0000100 .......... 100 ..... 0111011 @r
  packuw     0100100 .......... 100 ..... 0111011 @r
  grevw      0110100 .......... 101 ..... 0111011 @r
 -gorcw      0010100 .......... 101 ..... 0111011 @r
  greviw     0110100 .......... 101 ..... 0011011 @sh5
 -gorciw     0010100 .......... 101 ..... 0011011 @sh5
  # *** RV32 Zbc Standard Extension ***
  clmul      0000101 .......... 001 ..... 0110011 @r
 diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/bitmanip_helper.c
 +++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
      return do_grev(rs1, rs2, 32);
  }
+@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
--static target_ulong do_gorc(target_ulong rs1,
+     return require_rvv(s) &&
--                            target_ulong rs2,
+            require_rvf(s) &&
--                            int bits)
+            require_scale_rvf(s) &&
--{
+-           (s->sew != MO_8) &&
--    target_ulong x = rs1;
+            vext_check_isa_ill(s) &&
--    int i, shift;
+            vext_check_ds(s, a->rd, a->rs2, a->vm);
--
+ }
--    for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
+@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
--        if (rs2 & shift) {
+     return require_rvv(s) &&
--            x |= do_swap(x, adjacent_masks[i], shift);
+            require_rvf(s) &&
--        }
+            require_scale_rvf(s) &&
--    }
+-           (s->sew != MO_8) &&
--
+            vext_check_isa_ill(s) &&
--    return x;
+            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
--}
+ }
--
+@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
--target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
+     return require_rvv(s) &&
--{
+            require_rvf(s) &&
--    return do_gorc(rs1, rs2, TARGET_LONG_BITS);
+            require_scale_rvf(s) &&
--}
+-           (s->sew != MO_8) &&
--
+            vext_check_isa_ill(s) &&
--target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
+            vext_check_dd(s, a->rd, a->rs2, a->vm);
--{
+ }
--    return do_gorc(rs1, rs2, 32);
+@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 -}
 -
  target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
  {
-     target_ulong result = 0;
+     return opfv_widen_check(s, a) &&
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+            require_rvfmin(s) &&
-index XXXXXXX..XXXXXXX 100644
+-           require_scale_rvfmin(s) &&
---- a/target/riscv/insn_trans/trans_rvb.c.inc
+-           (s->sew != MO_8);
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
++           require_scale_rvfmin(s);
@@ -XXX,XX +XXX,XX @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
      return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
  }
--static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
+ #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
-+static void gen_orc_b(TCGv ret, TCGv source1)
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
  {
--    REQUIRE_EXT(ctx, RVB);
+     return opfv_narrow_check(s, a) &&
--    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
+            require_rvfmin(s) &&
-+    TCGv  tmp = tcg_temp_new();
+-           require_scale_rvfmin(s) &&
-+    TCGv  ones = tcg_constant_tl(dup_const_tl(MO_8, 0x01));
+-           (s->sew != MO_8);
-+
++           require_scale_rvfmin(s);
 +    /* Set lsb in each byte if the byte was zero. */
 +    tcg_gen_sub_tl(tmp, source1, ones);
 +    tcg_gen_andc_tl(tmp, tmp, source1);
 +    tcg_gen_shri_tl(tmp, tmp, 7);
 +    tcg_gen_andc_tl(tmp, ones, tmp);
 +
 +    /* Replicate the lsb of each byte across the byte. */
 +    tcg_gen_muli_tl(ret, tmp, 0xff);
 +
 +    tcg_temp_free(tmp);
  }
--static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
 +static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
  {
--    REQUIRE_EXT(ctx, RVB);
+     return opfv_narrow_check(s, a) &&
--    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
+            require_rvf(s) &&
-+    REQUIRE_ZBB(ctx);
+-           require_scale_rvf(s) &&
-+    return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
+-           (s->sew != MO_8);
 +           require_scale_rvf(s);
  }
- #define GEN_SHADD(SHAMT)                                       \
+ #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
-@@ -XXX,XX +XXX,XX @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
+@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
-     return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
+ {
      return reduction_widen_check(s, a) &&
             require_rvf(s) &&
 -           require_scale_rvf(s) &&
 -           (s->sew != MO_8);
 +           require_scale_rvf(s);
  }
--static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
+ GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    ctx->w = true;
 -    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
 -}
 -
 -static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    ctx->w = true;
 -    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
 -}
 -
  #define GEN_SHADD_UW(SHAMT)                                       \
  static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
  {                                                                 \
 --
-.31.1
+.45.1

-[PULL 12/26] target/riscv: Add a REQUIRE_32BIT macro
+[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-With the changes to Zb[abcs], there's some encodings that are
+raise_mmu_exception(), as is today, is prioritizing guest page faults by
-different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,
+checking first if virt_enabled && !first_stage, and then considering the
-we'll need a helper macro allowing us to select on RV32, as well.
+regular inst/load/store faults.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+There's no mention in the spec about guest page fault being a higher
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+priority that PMP faults. In fact, privileged spec section 3.7.1 says:
 "Attempting to fetch an instruction from a PMP region that does not have
 execute permissions raises an instruction access-fault exception.
 Attempting to execute a load or load-reserved instruction which accesses
 a physical address within a PMP region without read permissions raises a
 load access-fault exception. Attempting to execute a store,
 store-conditional, or AMO instruction which accesses a physical address
 within a PMP region without write permissions raises a store
 access-fault exception."
 So, in fact, we're doing it wrong - PMP faults should always be thrown,
 regardless of also being a first or second stage fault.
 The way riscv_cpu_tlb_fill() and get_physical_address() work is
 adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
 reflected in the 'pmp_violation' flag. What we need is to change
 raise_mmu_exception() to prioritize it.
 Reported-by: Joseph Chan <jchan@ventanamicro.com>
 Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
-Message-id: 20210911140016.834071-13-philipp.tomsich@vrull.eu
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c | 6 ++++++
+ target/riscv/cpu_helper.c | 22 ++++++++++++----------
-file changed, 6 insertions(+)
+file changed, 12 insertions(+), 10 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/translate.c
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ EX_SH(12)
+@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
-     }                              \
- } while (0)
+     switch (access_type) {
+     case MMU_INST_FETCH:
-+#define REQUIRE_32BIT(ctx) do { \
+-        if (env->virt_enabled && !first_stage) {
-+    if (!is_32bit(ctx)) {       \
++        if (pmp_violation) {
-+        return false;           \
++            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
-+    }                           \
++        } else if (env->virt_enabled && !first_stage) {
-+} while (0)
+             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
-+
+         } else {
- #define REQUIRE_64BIT(ctx) do { \
+-            cs->exception_index = pmp_violation ?
-     if (is_32bit(ctx)) {        \
+-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
-         return false;           \
++            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
          }
          break;
      case MMU_DATA_LOAD:
 -        if (two_stage && !first_stage) {
 +        if (pmp_violation) {
 +            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
 +        } else if (two_stage && !first_stage) {
              cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
          } else {
 -            cs->exception_index = pmp_violation ?
 -                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
 +            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
          }
          break;
      case MMU_DATA_STORE:
 -        if (two_stage && !first_stage) {
 +        if (pmp_violation) {
 +            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
 +        } else if (two_stage && !first_stage) {
              cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
          } else {
 -            cs->exception_index = pmp_violation ?
 -                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
 -                RISCV_EXCP_STORE_PAGE_FAULT;
 +            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
          }
          break;
      default:
 --
-.31.1
+.45.1

-[PULL 07/26] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
+[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Alexei Filippov <alexei.filippov@syntacore.com>
-The Zb[abcs] ratification package does not include the proposed
+Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
-shift-one instructions. There currently is no clear plan to whether
+setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
-these (or variants of them) will be ratified as Zbo (or a different
+translation part, mtval2 will be set in case of successes 2 stage translation but
-extension) or what the timeframe for such a decision could be.
+failed pmp check.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
 should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
 page-fault is taken into M-mode, mtval2 is written with either zero or guest
 physical address that faulted, shifted by 2 bits. *For other traps, mtval2
 is set to zero...*
 Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Acked-by: Bin Meng <bmeng.cn@gmail.com>
+Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
-Message-id: 20210911140016.834071-8-philipp.tomsich@vrull.eu
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn32.decode              |  8 ---
+ target/riscv/cpu_helper.c | 12 ++++++------
- target/riscv/insn_trans/trans_rvb.c.inc | 70 -------------------------
+file changed, 6 insertions(+), 6 deletions(-)
 files changed, 78 deletions(-)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ bset       0010100 .......... 001 ..... 0110011 @r
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- bclr       0100100 .......... 001 ..... 0110011 @r
+                               __func__, pa, ret, prot_pmp, tlb_size);
- binv       0110100 .......... 001 ..... 0110011 @r
- bext       0100100 .......... 101 ..... 0110011 @r
+                 prot &= prot_pmp;
--slo        0010000 .......... 001 ..... 0110011 @r
+-            }
 -sro        0010000 .......... 101 ..... 0110011 @r
  ror        0110000 .......... 101 ..... 0110011 @r
  rol        0110000 .......... 001 ..... 0110011 @r
  grev       0110100 .......... 101 ..... 0110011 @r
@@ -XXX,XX +XXX,XX @@ bseti      00101. ........... 001 ..... 0010011 @sh
  bclri      01001. ........... 001 ..... 0010011 @sh
  binvi      01101. ........... 001 ..... 0010011 @sh
  bexti      01001. ........... 101 ..... 0010011 @sh
 -sloi       00100. ........... 001 ..... 0010011 @sh
 -sroi       00100. ........... 101 ..... 0010011 @sh
  rori       01100. ........... 101 ..... 0010011 @sh
  grevi      01101. ........... 101 ..... 0010011 @sh
  gorci      00101. ........... 101 ..... 0010011 @sh
@@ -XXX,XX +XXX,XX @@ cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
  packw      0000100 .......... 100 ..... 0111011 @r
  packuw     0100100 .......... 100 ..... 0111011 @r
 -slow       0010000 .......... 001 ..... 0111011 @r
 -srow       0010000 .......... 101 ..... 0111011 @r
  rorw       0110000 .......... 101 ..... 0111011 @r
  rolw       0110000 .......... 001 ..... 0111011 @r
  grevw      0110100 .......... 101 ..... 0111011 @r
  gorcw      0010100 .......... 101 ..... 0111011 @r
 -sloiw      0010000 .......... 001 ..... 0011011 @sh5
 -sroiw      0010000 .......... 101 ..... 0011011 @sh5
  roriw      0110000 .......... 101 ..... 0011011 @sh5
  greviw     0110100 .......... 101 ..... 0011011 @sh5
  gorciw     0010100 .......... 101 ..... 0011011 @sh5
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
      return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
  }
 -static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    tcg_gen_not_tl(ret, arg1);
 -    tcg_gen_shl_tl(ret, ret, arg2);
 -    tcg_gen_not_tl(ret, ret);
 -}
 -
--static bool trans_slo(DisasContext *ctx, arg_slo *a)
+-            if (ret != TRANSLATE_SUCCESS) {
--{
++            } else {
--    REQUIRE_EXT(ctx, RVB);
+                 /*
--    return gen_shift(ctx, a, EXT_NONE, gen_slo);
+                  * Guest physical address translation failed, this is a HS
--}
+                  * level exception
--
+                  */
--static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
+                 first_stage_error = false;
--{
+-                env->guest_phys_fault_addr = (im_address |
--    REQUIRE_EXT(ctx, RVB);
+-                                              (address &
--    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
+-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
--}
++                if (ret != TRANSLATE_PMP_FAIL) {
--
++                    env->guest_phys_fault_addr = (im_address |
--static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
++                                                  (address &
--{
++                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
--    tcg_gen_not_tl(ret, arg1);
++                }
--    tcg_gen_shr_tl(ret, ret, arg2);
+             }
--    tcg_gen_not_tl(ret, ret);
+         }
--}
+     } else {
 -
 -static bool trans_sro(DisasContext *ctx, arg_sro *a)
 -{
 -    REQUIRE_EXT(ctx, RVB);
 -    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
 -}
 -
 -static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
 -{
 -    REQUIRE_EXT(ctx, RVB);
 -    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
 -}
 -
  static bool trans_ror(DisasContext *ctx, arg_ror *a)
  {
      REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
      return gen_arith(ctx, a, EXT_NONE, gen_packuw);
  }
 -static bool trans_slow(DisasContext *ctx, arg_slow *a)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    ctx->w = true;
 -    return gen_shift(ctx, a, EXT_NONE, gen_slo);
 -}
 -
 -static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    ctx->w = true;
 -    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
 -}
 -
 -static bool trans_srow(DisasContext *ctx, arg_srow *a)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    ctx->w = true;
 -    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
 -}
 -
 -static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    ctx->w = true;
 -    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
 -}
 -
  static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
  {
      TCGv_i32 t1 = tcg_temp_new_i32();
 --
-.31.1
+.45.1

-[PULL 06/26] target/riscv: Remove the W-form instructions from Zbs
+[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Rob Bradford <rbradford@rivosinc.com>
-Zbs 1.0.0 (just as the 0.93 draft-B before) does not provide for W-form
+This extension has now been ratified:
-instructions for Zbs (single-bit instructions).  Remove them.
+https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
 removed.
-Note that these instructions had already been removed for the 0.93
+Since this is now a ratified extension add it to the list of extensions
-version of the draft-B extention and have not been present in the
+included in the "max" CPU variant.
 binutils patches circulating in January 2021.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Acked-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-id: 20210911140016.834071-7-philipp.tomsich@vrull.eu
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn32.decode              |  7 ----
+ target/riscv/cpu.c         | 2 +-
- target/riscv/insn_trans/trans_rvb.c.inc | 56 -------------------------
+ target/riscv/tcg/tcg-cpu.c | 2 +-
-files changed, 63 deletions(-)
+files changed, 2 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
+@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
+     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
- packw      0000100 .......... 100 ..... 0111011 @r
+     MISA_EXT_INFO(RVV, "v", "Vector operations"),
- packuw     0100100 .......... 100 ..... 0111011 @r
+     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
--bsetw      0010100 .......... 001 ..... 0111011 @r
+-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
--bclrw      0100100 .......... 001 ..... 0111011 @r
++    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
--binvw      0110100 .......... 001 ..... 0111011 @r
+ };
--bextw      0100100 .......... 101 ..... 0111011 @r
- slow       0010000 .......... 001 ..... 0111011 @r
+ static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
- srow       0010000 .......... 101 ..... 0111011 @r
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
  rorw       0110000 .......... 101 ..... 0111011 @r
@@ -XXX,XX +XXX,XX @@ rolw       0110000 .......... 001 ..... 0111011 @r
  grevw      0110100 .......... 101 ..... 0111011 @r
  gorcw      0010100 .......... 101 ..... 0111011 @r
 -bsetiw     0010100 .......... 001 ..... 0011011 @sh5
 -bclriw     0100100 .......... 001 ..... 0011011 @sh5
 -binviw     0110100 .......... 001 ..... 0011011 @sh5
  sloiw      0010000 .......... 001 ..... 0011011 @sh5
  sroiw      0010000 .......... 101 ..... 0011011 @sh5
  roriw      0110000 .......... 101 ..... 0011011 @sh5
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
+--- a/target/riscv/tcg/tcg-cpu.c
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/tcg/tcg-cpu.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
+@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
-     return gen_arith(ctx, a, EXT_NONE, gen_packuw);
+     const RISCVCPUMultiExtConfig *prop;
- }
+     /* Enable RVG, RVJ and RVV that are disabled by default */
--static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
+-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
--{
++    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
--    REQUIRE_64BIT(ctx);
--    REQUIRE_EXT(ctx, RVB);
+     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
--    ctx->w = true;
+         isa_ext_update_enabled(cpu, prop->offset, true);
 -    return gen_shift(ctx, a, EXT_NONE, gen_bset);
 -}
 -
 -static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    ctx->w = true;
 -    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
 -}
 -
 -static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    ctx->w = true;
 -    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
 -}
 -
 -static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    ctx->w = true;
 -    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
 -}
 -
 -static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    ctx->w = true;
 -    return gen_shift(ctx, a, EXT_NONE, gen_binv);
 -}
 -
 -static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    ctx->w = true;
 -    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
 -}
 -
 -static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
 -{
 -    REQUIRE_64BIT(ctx);
 -    REQUIRE_EXT(ctx, RVB);
 -    ctx->w = true;
 -    return gen_shift(ctx, a, EXT_NONE, gen_bext);
 -}
 -
  static bool trans_slow(DisasContext *ctx, arg_slow *a)
  {
      REQUIRE_64BIT(ctx);
 --
-.31.1
+.45.1

-[PULL 13/26] target/riscv: Add rev8 instruction, removing grev/grevi
+[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Alistair Francis <alistair23@gmail.com>
-The 1.0.0 version of Zbb does not contain grev/grevi.  Instead, a
+When running the instruction
 rev8 instruction (equivalent to the rev8 pseudo-instruction built on
 grevi from pre-0.93 draft-B) is available.
-This commit adds the new rev8 instruction and removes grev/grevi.
+```
     cbo.flush 0(x0)
 ```
-Note that there is no W-form of this instruction (both a
+QEMU would segfault.
 sign-extending and zero-extending 32-bit version can easily be
 synthesized by following rev8 with either a srai or srli instruction
 on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are
 different.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
 allocated.
 In order to fix this let's use the existing get_address()
 helper. This also has the benefit of performing pointer mask
 calculations on the address specified in rs1.
 The pointer masking specificiation specifically states:
 """
 Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
 """
 So this is the correct behaviour and we previously have been incorrectly
 not masking the address.
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
 Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-id: 20210911140016.834071-14-philipp.tomsich@vrull.eu
+Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/helper.h                   |  2 --
+ target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
- target/riscv/insn32.decode              | 12 ++++----
+file changed, 12 insertions(+), 4 deletions(-)
  target/riscv/bitmanip_helper.c          | 40 -------------------------
  target/riscv/insn_trans/trans_rvb.c.inc | 40 +++++--------------------
 files changed, 15 insertions(+), 79 deletions(-)
-diff --git a/target/riscv/helper.h b/target/riscv/helper.h
+diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.h
+--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
-+++ b/target/riscv/helper.h
++++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
  DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
  /* Bitmanip */
 -DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 -DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn32.decode
 +++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ min        0000101 .......... 100 ..... 0110011 @r
  minu       0000101 .......... 101 ..... 0110011 @r
  orc_b      001010 000111 ..... 101 ..... 0010011 @r2
  orn        0100000 .......... 110 ..... 0110011 @r
 +# The encoding for rev8 differs between RV32 and RV64.
 +# rev8_32 denotes the RV32 variant.
 +rev8_32    011010 011000 ..... 101 ..... 0010011 @r2
  rol        0110000 .......... 001 ..... 0110011 @r
  ror        0110000 .......... 101 ..... 0110011 @r
  rori       01100 ............ 101 ..... 0010011 @sh
@@ -XXX,XX +XXX,XX @@ xnor       0100000 .......... 100 ..... 0110011 @r
  clzw       0110000 00000 ..... 001 ..... 0011011 @r2
  ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
  cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
 +# The encoding for rev8 differs between RV32 and RV64.
 +# When executing on RV64, the encoding used in RV32 is an illegal
 +# instruction, so we use different handler functions to differentiate.
 +rev8_64    011010 111000 ..... 101 ..... 0010011 @r2
  rolw       0110000 .......... 001 ..... 0111011 @r
  roriw      0110000 .......... 101 ..... 0011011 @sh5
  rorw       0110000 .......... 101 ..... 0111011 @r
@@ -XXX,XX +XXX,XX @@ rorw       0110000 .......... 101 ..... 0111011 @r
  pack       0000100 .......... 100 ..... 0110011 @r
  packu      0100100 .......... 100 ..... 0110011 @r
  packh      0000100 .......... 111 ..... 0110011 @r
 -grev       0110100 .......... 101 ..... 0110011 @r
 -grevi      01101. ........... 101 ..... 0010011 @sh
  # *** RV64B Standard Extension (in addition to RV32B) ***
  packw      0000100 .......... 100 ..... 0111011 @r
  packuw     0100100 .......... 100 ..... 0111011 @r
 -grevw      0110100 .......... 101 ..... 0111011 @r
 -
 -greviw     0110100 .......... 101 ..... 0011011 @sh5
  # *** RV32 Zbc Standard Extension ***
  clmul      0000101 .......... 001 ..... 0110011 @r
 diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/bitmanip_helper.c
 +++ b/target/riscv/bitmanip_helper.c
 @@ -XXX,XX +XXX,XX @@
- #include "exec/helper-proto.h"
+ static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
  #include "tcg/tcg.h"
 -static const uint64_t adjacent_masks[] = {
 -    dup_const(MO_8, 0x55),
 -    dup_const(MO_8, 0x33),
 -    dup_const(MO_8, 0x0f),
 -    dup_const(MO_16, 0xff),
 -    dup_const(MO_32, 0xffff),
 -    UINT32_MAX
 -};
 -
 -static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
 -{
 -    return ((x & mask) << shift) | ((x & ~mask) >> shift);
 -}
 -
 -static target_ulong do_grev(target_ulong rs1,
 -                            target_ulong rs2,
 -                            int bits)
 -{
 -    target_ulong x = rs1;
 -    int i, shift;
 -
 -    for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
 -        if (rs2 & shift) {
 -            x = do_swap(x, adjacent_masks[i], shift);
 -        }
 -    }
 -
 -    return x;
 -}
 -
 -target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
 -{
 -    return do_grev(rs1, rs2, TARGET_LONG_BITS);
 -}
 -
 -target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
 -{
 -    return do_grev(rs1, rs2, 32);
 -}
 -
  target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
  {
-     target_ulong result = 0;
+     REQUIRE_ZICBOM(ctx);
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
-index XXXXXXX..XXXXXXX 100644
++    TCGv src = get_address(ctx, a->rs1, 0);
---- a/target/riscv/insn_trans/trans_rvb.c.inc
++
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
++    gen_helper_cbo_clean_flush(tcg_env, src);
-@@ -XXX,XX +XXX,XX @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
+     return true;
      return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
  }
--static bool trans_grev(DisasContext *ctx, arg_grev *a)
+ static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 +static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
  {
--    REQUIRE_EXT(ctx, RVB);
+     REQUIRE_ZICBOM(ctx);
--    return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
--}
++    TCGv src = get_address(ctx, a->rs1, 0);
--
++
--static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
++    gen_helper_cbo_clean_flush(tcg_env, src);
--{
+     return true;
 -    if (shamt == TARGET_LONG_BITS - 8) {
 -        /* rev8, byte swaps */
 -        tcg_gen_bswap_tl(dest, src);
 -    } else {
 -        gen_helper_grev(dest, src, tcg_constant_tl(shamt));
 -    }
 +    REQUIRE_32BIT(ctx);
 +    REQUIRE_ZBB(ctx);
 +    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
  }
--static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
+ static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
 +static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
  {
--    REQUIRE_EXT(ctx, RVB);
+     REQUIRE_ZICBOM(ctx);
--    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
+-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
-+    REQUIRE_64BIT(ctx);
++    TCGv src = get_address(ctx, a->rs1, 0);
-+    REQUIRE_ZBB(ctx);
++
-+    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
++    gen_helper_cbo_inval(tcg_env, src);
      return true;
  }
- static void gen_orc_b(TCGv ret, TCGv source1)
+ static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
-@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
+ {
-     return gen_shift(ctx, a, EXT_NONE, gen_rolw);
+     REQUIRE_ZICBOZ(ctx);
 -    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
 +    TCGv src = get_address(ctx, a->rs1, 0);
 +
 +    gen_helper_cbo_zero(tcg_env, src);
      return true;
  }
--static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
--{
--    REQUIRE_64BIT(ctx);
--    REQUIRE_EXT(ctx, RVB);
--    ctx->w = true;
--    return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
--}
--
--static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
--{
--    REQUIRE_64BIT(ctx);
--    REQUIRE_EXT(ctx, RVB);
--    ctx->w = true;
--    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
--}
--
- #define GEN_SHADD_UW(SHAMT)                                       \
- static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
- {                                                                 \
 --
-.31.1
+.45.1

-[PULL 03/26] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
+[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-Assume clzw being executed on a register that is not sign-extended, such
+In AIA spec, each hart (or each hart within a group) has a unique hart
-as for the following sequence that uses (1ULL << 63) | 392 as the operand
+number to locate the memory pages of interrupt files in the address
-to clzw:
+space. The number of bits required to represent any hart number is equal
-    bseti    a2, zero, 63
+to ceil(log2(hmax + 1)), where hmax is the largest hart number among
-    addi    a2, a2, 392
+groups.
     clzw    a3, a2
 The correct result of clzw would be 23, but the current implementation
 returns -32 (as it performs a 64bit clz, which results in 0 leading zero
 bits, and then subtracts 32).
-Fix this by changing the implementation to:
+However, if the largest hart number among groups is a power of 2, QEMU
-. shift the original register up by 32
+will pass an inaccurate hart-index-bit setting to Linux. For example, when
-. performs a target-length (64bit) clz
+the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
-. return 32 if no bits are set
+to represent 4 harts, but we passes 3 to Linux. The code needs to be
 updated to ensure accurate hart-index-bit settings.
-Marking this instruction as 'w-form' (i.e., setting ctx->w) would not
+Additionally, a Linux patch[1] is necessary to correctly recover the hart
-correctly model the behaviour, as the instruction should not perform
+index when the guest OS has only 1 hart, where the hart-index-bit is 0.
 a zero-extensions on the input (after all, it is not a .uw instruction)
 and the result is always in the range 0..32 (so neither a sign-extension
 nor a zero-extension on the result will ever be needed).  Consequently,
 we do not set ctx->w and mark the instruction as EXT_NONE.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
-Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
-Message-id: 20210911140016.834071-4-philipp.tomsich@vrull.eu
+Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvb.c.inc | 8 +++++---
+ target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
-file changed, 5 insertions(+), 3 deletions(-)
+file changed, 8 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(3)
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
+         }
- static void gen_clzw(TCGv ret, TCGv arg1)
+     }
- {
--    tcg_gen_clzi_tl(ret, arg1, 64);
+-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
--    tcg_gen_subi_tl(ret, ret, 32);
++
-+    TCGv t = tcg_temp_new();
++    if (max_hart_per_socket > 1) {
-+    tcg_gen_shli_tl(t, arg1, 32);
++        max_hart_per_socket--;
-+    tcg_gen_clzi_tl(ret, t, 32);
++        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
-+    tcg_temp_free(t);
++    } else {
- }
++        hart_bits = 0;
++    }
- static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
++
- {
+     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
-     REQUIRE_64BIT(ctx);
+                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
-     REQUIRE_EXT(ctx, RVB);
+                             &hart_bits, true, NULL);
 -    return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
 +    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
  }
  static void gen_ctzw(TCGv ret, TCGv arg1)
 --
-.31.1
+.45.1

-[PULL 01/26] target/riscv: Introduce temporary in gen_add_uw()
+[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Following the recent changes in translate.c, gen_add_uw() causes
+Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
-failures on CF3 and SPEC2017 due to the reuse of arg1.  Fix these
+in bytes, when in this context we want 'reg_width' as the length in
-regressions by introducing a temporary.
+bits.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Fix 'reg_width' back to the value in bits like 7cb59921c05a
 ("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
 beforehand.
 While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
 clarity about what the variable represents. 'bitsize' is also used in
 riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
 gdb_feature_builder_append_reg().
 Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
 Cc: Alex Bennée <alex.bennee@linaro.org>
 Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
 Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Acked-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
 Message-id: 20210911140016.834071-2-philipp.tomsich@vrull.eu
 Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*")
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
+ target/riscv/gdbstub.c | 6 +++---
-file changed, 4 insertions(+), 2 deletions(-)
+file changed, 3 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
+--- a/target/riscv/gdbstub.c
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD_UW(3)
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
+ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
  static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
  {
--    tcg_gen_ext32u_tl(arg1, arg1);
+     RISCVCPU *cpu = RISCV_CPU(cs);
--    tcg_gen_add_tl(ret, arg1, arg2);
+-    int reg_width = cpu->cfg.vlenb;
-+    TCGv t = tcg_temp_new();
++    int bitsize = cpu->cfg.vlenb << 3;
-+    tcg_gen_ext32u_tl(t, arg1);
+     GDBFeatureBuilder builder;
-+    tcg_gen_add_tl(ret, t, arg2);
+     int i;
-+    tcg_temp_free(t);
- }
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
- static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
+     /* First define types and totals in a whole VL */
      for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 -        int count = reg_width / vec_lanes[i].size;
 +        int count = bitsize / vec_lanes[i].size;
          gdb_feature_builder_append_tag(
              &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
              vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
      /* Define vector registers */
      for (i = 0; i < 32; i++) {
          gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
 -                                       reg_width, i, "riscv_vector", "vector");
 +                                       bitsize, i, "riscv_vector", "vector");
      }
      gdb_feature_builder_end(&builder);
 --
-.31.1
+.45.1

-[PULL 16/26] disas/riscv: Add Zb[abcs] instructions
+[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Alistair Francis <alistair23@gmail.com>
-With the addition of Zb[abcs], we also need to add disassembler
+Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
-support for these new instructions.
+CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
 CSRs are part of the disassembly.
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210911140016.834071-17-philipp.tomsich@vrull.eu
+Fixes: ea10325917 ("RISC-V Disassembler")
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- disas/riscv.c | 157 +++++++++++++++++++++++++++++++++++++++++++++++++-
+ disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
-file changed, 154 insertions(+), 3 deletions(-)
+file changed, 64 insertions(+), 1 deletion(-)
 diff --git a/disas/riscv.c b/disas/riscv.c
 index XXXXXXX..XXXXXXX 100644
 --- a/disas/riscv.c
 +++ b/disas/riscv.c
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
-     rv_op_fsflags = 316,
+     case 0x0383: return "mibound";
-     rv_op_fsrmi = 317,
+     case 0x0384: return "mdbase";
-     rv_op_fsflagsi = 318,
+     case 0x0385: return "mdbound";
-+    rv_op_bseti = 319,
+-    case 0x03a0: return "pmpcfg3";
-+    rv_op_bclri = 320,
++    case 0x03a0: return "pmpcfg0";
-+    rv_op_binvi = 321,
++    case 0x03a1: return "pmpcfg1";
-+    rv_op_bexti = 322,
++    case 0x03a2: return "pmpcfg2";
-+    rv_op_rori = 323,
++    case 0x03a3: return "pmpcfg3";
-+    rv_op_clz = 324,
++    case 0x03a4: return "pmpcfg4";
-+    rv_op_ctz = 325,
++    case 0x03a5: return "pmpcfg5";
-+    rv_op_cpop = 326,
++    case 0x03a6: return "pmpcfg6";
-+    rv_op_sext_h = 327,
++    case 0x03a7: return "pmpcfg7";
-+    rv_op_sext_b = 328,
++    case 0x03a8: return "pmpcfg8";
-+    rv_op_xnor = 329,
++    case 0x03a9: return "pmpcfg9";
-+    rv_op_orn = 330,
++    case 0x03aa: return "pmpcfg10";
-+    rv_op_andn = 331,
++    case 0x03ab: return "pmpcfg11";
-+    rv_op_rol = 332,
++    case 0x03ac: return "pmpcfg12";
-+    rv_op_ror = 333,
++    case 0x03ad: return "pmpcfg13";
-+    rv_op_sh1add = 334,
++    case 0x03ae: return "pmpcfg14";
-+    rv_op_sh2add = 335,
++    case 0x03af: return "pmpcfg15";
-+    rv_op_sh3add = 336,
+     case 0x03b0: return "pmpaddr0";
-+    rv_op_sh1add_uw = 337,
+     case 0x03b1: return "pmpaddr1";
-+    rv_op_sh2add_uw = 338,
+     case 0x03b2: return "pmpaddr2";
-+    rv_op_sh3add_uw = 339,
+@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
-+    rv_op_clmul = 340,
+     case 0x03bd: return "pmpaddr13";
-+    rv_op_clmulr = 341,
+     case 0x03be: return "pmpaddr14";
-+    rv_op_clmulh = 342,
+     case 0x03bf: return "pmpaddr15";
-+    rv_op_min = 343,
++    case 0x03c0: return "pmpaddr16";
-+    rv_op_minu = 344,
++    case 0x03c1: return "pmpaddr17";
-+    rv_op_max = 345,
++    case 0x03c2: return "pmpaddr18";
-+    rv_op_maxu = 346,
++    case 0x03c3: return "pmpaddr19";
-+    rv_op_clzw = 347,
++    case 0x03c4: return "pmpaddr20";
-+    rv_op_ctzw = 348,
++    case 0x03c5: return "pmpaddr21";
-+    rv_op_cpopw = 349,
++    case 0x03c6: return "pmpaddr22";
-+    rv_op_slli_uw = 350,
++    case 0x03c7: return "pmpaddr23";
-+    rv_op_add_uw = 351,
++    case 0x03c8: return "pmpaddr24";
-+    rv_op_rolw = 352,
++    case 0x03c9: return "pmpaddr25";
-+    rv_op_rorw = 353,
++    case 0x03ca: return "pmpaddr26";
-+    rv_op_rev8 = 354,
++    case 0x03cb: return "pmpaddr27";
-+    rv_op_zext_h = 355,
++    case 0x03cc: return "pmpaddr28";
-+    rv_op_roriw = 356,
++    case 0x03cd: return "pmpaddr29";
-+    rv_op_orc_b = 357,
++    case 0x03ce: return "pmpaddr30";
-+    rv_op_bset = 358,
++    case 0x03cf: return "pmpaddr31";
-+    rv_op_bclr = 359,
++    case 0x03d0: return "pmpaddr32";
-+    rv_op_binv = 360,
++    case 0x03d1: return "pmpaddr33";
-+    rv_op_bext = 361,
++    case 0x03d2: return "pmpaddr34";
- } rv_op;
++    case 0x03d3: return "pmpaddr35";
++    case 0x03d4: return "pmpaddr36";
- /* structures */
++    case 0x03d5: return "pmpaddr37";
-@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
++    case 0x03d6: return "pmpaddr38";
-     { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
++    case 0x03d7: return "pmpaddr39";
-     { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
++    case 0x03d8: return "pmpaddr40";
-     { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
++    case 0x03d9: return "pmpaddr41";
-+    { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
++    case 0x03da: return "pmpaddr42";
-+    { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
++    case 0x03db: return "pmpaddr43";
-+    { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
++    case 0x03dc: return "pmpaddr44";
-+    { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
++    case 0x03dd: return "pmpaddr45";
-+    { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
++    case 0x03de: return "pmpaddr46";
-+    { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
++    case 0x03df: return "pmpaddr47";
-+    { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
++    case 0x03e0: return "pmpaddr48";
-+    { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
++    case 0x03e1: return "pmpaddr49";
-+    { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
++    case 0x03e2: return "pmpaddr50";
-+    { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
++    case 0x03e3: return "pmpaddr51";
-+    { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
++    case 0x03e4: return "pmpaddr52";
-+    { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
++    case 0x03e5: return "pmpaddr53";
-+    { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
++    case 0x03e6: return "pmpaddr54";
-+    { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03e7: return "pmpaddr55";
-+    { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03e8: return "pmpaddr56";
-+    { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03e9: return "pmpaddr57";
-+    { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03ea: return "pmpaddr58";
-+    { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03eb: return "pmpaddr59";
-+    { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03ec: return "pmpaddr60";
-+    { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03ed: return "pmpaddr61";
-+    { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03ee: return "pmpaddr62";
-+    { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03ef: return "pmpaddr63";
-+    { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+     case 0x0780: return "mtohost";
-+    { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+     case 0x0781: return "mfromhost";
-+    { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+     case 0x0782: return "mreset";
 +    { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
 +    { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
 +    { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 +    { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
  };
  /* CSR names */
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 0: op = rv_op_addi; break;
              case 1:
                  switch (((inst >> 27) & 0b11111)) {
 -                case 0: op = rv_op_slli; break;
 +                case 0b00000: op = rv_op_slli; break;
 +                case 0b00101: op = rv_op_bseti; break;
 +                case 0b01001: op = rv_op_bclri; break;
 +                case 0b01101: op = rv_op_binvi; break;
 +                case 0b01100:
 +                    switch (((inst >> 20) & 0b1111111)) {
 +                    case 0b0000000: op = rv_op_clz; break;
 +                    case 0b0000001: op = rv_op_ctz; break;
 +                    case 0b0000010: op = rv_op_cpop; break;
 +                      /* 0b0000011 */
 +                    case 0b0000100: op = rv_op_sext_b; break;
 +                    case 0b0000101: op = rv_op_sext_h; break;
 +                    }
 +                    break;
                  }
                  break;
              case 2: op = rv_op_slti; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 4: op = rv_op_xori; break;
              case 5:
                  switch (((inst >> 27) & 0b11111)) {
 -                case 0: op = rv_op_srli; break;
 -                case 8: op = rv_op_srai; break;
 +                case 0b00000: op = rv_op_srli; break;
 +                case 0b00101: op = rv_op_orc_b; break;
 +                case 0b01000: op = rv_op_srai; break;
 +                case 0b01001: op = rv_op_bexti; break;
 +                case 0b01100: op = rv_op_rori; break;
 +                case 0b01101:
 +                    switch ((inst >> 20) & 0b1111111) {
 +                    case 0b0111000: op = rv_op_rev8; break;
 +                    }
 +                    break;
                  }
                  break;
              case 6: op = rv_op_ori; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 1:
                  switch (((inst >> 25) & 0b1111111)) {
                  case 0: op = rv_op_slliw; break;
 +                case 4: op = rv_op_slli_uw; break;
 +                case 48:
 +                    switch ((inst >> 20) & 0b11111) {
 +                    case 0b00000: op = rv_op_clzw; break;
 +                    case 0b00001: op = rv_op_ctzw; break;
 +                    case 0b00010: op = rv_op_cpopw; break;
 +                    }
 +                    break;
                  }
                  break;
              case 5:
                  switch (((inst >> 25) & 0b1111111)) {
                  case 0: op = rv_op_srliw; break;
                  case 32: op = rv_op_sraiw; break;
 +                case 48: op = rv_op_roriw; break;
                  }
                  break;
              }
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 13: op = rv_op_divu; break;
              case 14: op = rv_op_rem; break;
              case 15: op = rv_op_remu; break;
 +            case 36:
 +                switch ((inst >> 20) & 0b11111) {
 +                case 0: op = rv_op_zext_h; break;
 +                }
 +                break;
 +            case 41: op = rv_op_clmul; break;
 +            case 42: op = rv_op_clmulr; break;
 +            case 43: op = rv_op_clmulh; break;
 +            case 44: op = rv_op_min; break;
 +            case 45: op = rv_op_minu; break;
 +            case 46: op = rv_op_max; break;
 +            case 47: op = rv_op_maxu; break;
 +            case 130: op = rv_op_sh1add; break;
 +            case 132: op = rv_op_sh2add; break;
 +            case 134: op = rv_op_sh3add; break;
 +            case 161: op = rv_op_bset; break;
              case 256: op = rv_op_sub; break;
 +            case 260: op = rv_op_xnor; break;
              case 261: op = rv_op_sra; break;
 +            case 262: op = rv_op_orn; break;
 +            case 263: op = rv_op_andn; break;
 +            case 289: op = rv_op_bclr; break;
 +            case 293: op = rv_op_bext; break;
 +            case 385: op = rv_op_rol; break;
 +            case 386: op = rv_op_ror; break;
 +            case 417: op = rv_op_binv; break;
              }
              break;
          case 13: op = rv_op_lui; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
              case 13: op = rv_op_divuw; break;
              case 14: op = rv_op_remw; break;
              case 15: op = rv_op_remuw; break;
 +            case 32: op = rv_op_add_uw; break;
 +            case 36:
 +                switch ((inst >> 20) & 0b11111) {
 +                case 0: op = rv_op_zext_h; break;
 +                }
 +                break;
 +            case 130: op = rv_op_sh1add_uw; break;
 +            case 132: op = rv_op_sh2add_uw; break;
 +            case 134: op = rv_op_sh3add_uw; break;
              case 256: op = rv_op_subw; break;
              case 261: op = rv_op_sraw; break;
 +            case 385: op = rv_op_rolw; break;
 +            case 389: op = rv_op_rorw; break;
              }
              break;
          case 16:
 --
-.31.1
+.45.1

-[PULL 17/26] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()
+[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
-From: Frank Chang <frank.chang@sifive.com>
+From: Yu-Ming Chang <yumin686@andestech.com>
-When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect.
+Both CSRRS and CSRRC always read the addressed CSR and cause any read side
-Modifying the floating-point state when V=1 causes both fields to
+effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
-be set to 3 (Dirty).
+holding a zero value other than x0, the instruction will still attempt to write
 the unmodified value back to the CSR and will cause any attendant side effects.
-However, it's possible that HS-level sstatus.FS is Clean and VS-level
+So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
-vsstatus.FS is Dirty at the time mark_fs_dirty() is called when V=1.
+a register holding a zero value, an illegal instruction exception should be
-We can't early return for this case because we still need to set
+raised.
 sstatus.FS to Dirty according to spec.
-Signed-off-by: Frank Chang <frank.chang@sifive.com>
+Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
 Reviewed-by: Vincent Chen <vincent.chen@sifive.com>
 Tested-by: Vincent Chen <vincent.chen@sifive.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210921020234.123448-1-frank.chang@sifive.com
+Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/cpu.h       |  4 ++++
- target/riscv/translate.c | 30 +++++++++++++++++-------------
+ target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
-files changed, 21 insertions(+), 13 deletions(-)
+ target/riscv/op_helper.c |  6 ++---
 files changed, 53 insertions(+), 8 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, SEW, 5, 3)
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
- FIELD(TB_FLAGS, VILL, 8, 1)
+ void riscv_cpu_update_mask(CPURISCVState *env);
- /* Is a Hypervisor instruction load/store allowed? */
+ bool riscv_cpu_is_32bit(RISCVCPU *cpu);
- FIELD(TB_FLAGS, HLSX, 9, 1)
-+FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
++                          target_ulong *ret_value);
- bool riscv_cpu_is_32bit(CPURISCVState *env);
+ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
+                            target_ulong *ret_value,
-@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+                            target_ulong new_value, target_ulong write_mask);
-                 get_field(env->hstatus, HSTATUS_HU))) {
+@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
-             flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
+                                           target_ulong new_value,
-         }
+                                           target_ulong write_mask);
 +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
 +                               Int128 *ret_value);
  RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                  Int128 *ret_value,
                                  Int128 new_value, Int128 write_mask);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
  static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                 int csrno,
 -                                               bool write_mask)
 +                                               bool write)
  {
      /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
      bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
      }
      /* read / write check */
 -    if (write_mask && read_only) {
 +    if (write && read_only) {
          return RISCV_EXCP_ILLEGAL_INST;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
 +RISCVException riscv_csrr(CPURISCVState *env, int csrno,
 +                           target_ulong *ret_value)
 +{
 +    RISCVException ret = riscv_csrrw_check(env, csrno, false);
 +    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +
-+        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
++    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
-+                           get_field(env->mstatus_hs, MSTATUS_FS));
++}
 +
  RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                             target_ulong *ret_value,
                             target_ulong new_value, target_ulong write_mask)
  {
 -    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
 +    RISCVException ret = riscv_csrrw_check(env, csrno, true);
      if (ret != RISCV_EXCP_NONE) {
          return ret;
      }
- #endif
+@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
+     return RISCV_EXCP_NONE;
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+ }
 +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
 +                               Int128 *ret_value)
 +{
 +    RISCVException ret;
 +
 +    ret = riscv_csrrw_check(env, csrno, false);
 +    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +
 +    if (csr_ops[csrno].read128) {
 +        return riscv_csrrw_do128(env, csrno, ret_value,
 +                                 int128_zero(), int128_zero());
 +    }
 +
 +    /*
 +     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
 +     * at all defined.
 +     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
 +     * significant), for those, this fallback is correctly handling the
 +     * accesses
 +     */
 +    target_ulong old_value;
 +    ret = riscv_csrrw_do64(env, csrno, &old_value,
 +                           (target_ulong)0,
 +                           (target_ulong)0);
 +    if (ret == RISCV_EXCP_NONE && ret_value) {
 +        *ret_value = int128_make64(old_value);
 +    }
 +    return ret;
 +}
 +
  RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                  Int128 *ret_value,
                                  Int128 new_value, Int128 write_mask)
  {
      RISCVException ret;
 -    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
 +    ret = riscv_csrrw_check(env, csrno, true);
      if (ret != RISCV_EXCP_NONE) {
          return ret;
      }
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/op_helper.c
-+++ b/target/riscv/translate.c
++++ b/target/riscv/op_helper.c
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
-     target_ulong misa;
+     }
-     uint32_t opcode;
-     uint32_t mstatus_fs;
+     target_ulong val = 0;
-+    uint32_t mstatus_hs_fs;
+-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
-     uint32_t mem_idx;
++    RISCVException ret = riscv_csrr(env, csr, &val);
-     /* Remember the rounding mode encoded in the previous fp instruction,
-        which we have already installed into env->fp_status.  Or -1 for
+     if (ret != RISCV_EXCP_NONE) {
-@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
+         riscv_raise_exception(env, ret, GETPC());
- static void mark_fs_dirty(DisasContext *ctx)
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
  target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
  {
-     TCGv tmp;
+     Int128 rv = int128_zero();
--    target_ulong sd;
+-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
-+    target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+-                                          int128_zero(),
+-                                          int128_zero());
--    if (ctx->mstatus_fs == MSTATUS_FS) {
++    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
--        return;
--    }
+     if (ret != RISCV_EXCP_NONE) {
--    /* Remember the state change for the rest of the TB.  */
+         riscv_raise_exception(env, ret, GETPC());
 -    ctx->mstatus_fs = MSTATUS_FS;
 +    if (ctx->mstatus_fs != MSTATUS_FS) {
 +        /* Remember the state change for the rest of the TB. */
 +        ctx->mstatus_fs = MSTATUS_FS;
 -    tmp = tcg_temp_new();
 -    sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
 +        tmp = tcg_temp_new();
 +        tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 +        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
 +        tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 +        tcg_temp_free(tmp);
 +    }
 -    tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 -    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
 -    tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 +    if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
 +        /* Remember the stage change for the rest of the TB. */
 +        ctx->mstatus_hs_fs = MSTATUS_FS;
 -    if (ctx->virt_enabled) {
 +        tmp = tcg_temp_new();
          tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
          tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
          tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
 +        tcg_temp_free(tmp);
      }
 -    tcg_temp_free(tmp);
  }
  #else
  static inline void mark_fs_dirty(DisasContext *ctx) { }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
      ctx->frm = -1;  /* unknown rounding mode */
      ctx->ext_ifencei = cpu->cfg.ext_ifencei;
      ctx->vlen = cpu->cfg.vlen;
 +    ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
      ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
      ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
      ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
 --
-.31.1
+.45.1

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit ca61fa4b803e5d0abaf6f1ceb690f23bb78a4def:

Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211006' into staging (2021-10-06 12:11:14 -0700)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211007

for you to fetch changes up to 9ae6ecd848dcd1b32003526ab65a0d4c644dfb07:

hw/riscv: shakti_c: Mark as not user creatable (2021-10-07 08:41:33 +1000)

----------------------------------------------------------------
Third RISC-V PR for QEMU 6.2

- Add Zb[abcs] instruction support
 - Remove RVB support
 - Bug fix of setting mstatus_hs.[SD|FS] bits
 - Mark some UART devices as 'input'
 - QOMify PolarFire MMUART
 - Fixes for sifive PDMA
 - Mark shakti_c as not user creatable

----------------------------------------------------------------
Alistair Francis (1):
      hw/riscv: shakti_c: Mark as not user creatable

Bin Meng (5):
      hw/char: ibex_uart: Register device in 'input' category
      hw/char: shakti_uart: Register device in 'input' category
      hw/char: sifive_uart: Register device in 'input' category
      hw/dma: sifive_pdma: Fix Control.claim bit detection
      hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed

Frank Chang (1):
      target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()

Philipp Tomsich (16):
      target/riscv: Introduce temporary in gen_add_uw()
      target/riscv: fix clzw implementation to operate on arg1
      target/riscv: clwz must ignore high bits (use shift-left & changed logic)
      target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
      target/riscv: Reassign instructions to the Zba-extension
      target/riscv: Remove the W-form instructions from Zbs
      target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
      target/riscv: Reassign instructions to the Zbs-extension
      target/riscv: Add instructions of the Zbc-extension
      target/riscv: Reassign instructions to the Zbb-extension
      target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
      target/riscv: Add a REQUIRE_32BIT macro
      target/riscv: Add rev8 instruction, removing grev/grevi
      target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
      target/riscv: Remove RVB (replaced by Zb[abcs])
      disas/riscv: Add Zb[abcs] instructions

Philippe Mathieu-Daudé (3):
      hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition
      hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container
      hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

Following the recent changes in translate.c, gen_add_uw() causes
failures on CF3 and SPEC2017 due to the reuse of arg1.  Fix these
regressions by introducing a temporary.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210911140016.834071-2-philipp.tomsich@vrull.eu
Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD_UW(3)
 
 static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
 {
-    tcg_gen_ext32u_tl(arg1, arg1);
-    tcg_gen_add_tl(ret, arg1, arg2);
+    TCGv t = tcg_temp_new();
+    tcg_gen_ext32u_tl(t, arg1);
+    tcg_gen_add_tl(ret, t, arg2);
+    tcg_temp_free(t);
 }
 
 static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The refactored gen_clzw() uses ret as its argument, instead of arg1.
Fix it.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210911140016.834071-3-philipp.tomsich@vrull.eu
Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

Assume clzw being executed on a register that is not sign-extended, such
as for the following sequence that uses (1ULL << 63) | 392 as the operand
to clzw:
	bseti	a2, zero, 63
	addi	a2, a2, 392
	clzw    a3, a2
The correct result of clzw would be 23, but the current implementation
returns -32 (as it performs a 64bit clz, which results in 0 leading zero
bits, and then subtracts 32).

Fix this by changing the implementation to:
 1. shift the original register up by 32
 2. performs a target-length (64bit) clz
 3. return 32 if no bits are set

Marking this instruction as 'w-form' (i.e., setting ctx->w) would not
correctly model the behaviour, as the instruction should not perform
a zero-extensions on the input (after all, it is not a .uw instruction)
and the result is always in the range 0..32 (so neither a sign-extension
nor a zero-extension on the result will ever be needed).  Consequently,
we do not set ctx->w and mark the instruction as EXT_NONE.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Message-id: 20210911140016.834071-4-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(3)
 
 static void gen_clzw(TCGv ret, TCGv arg1)
 {
-    tcg_gen_clzi_tl(ret, arg1, 64);
-    tcg_gen_subi_tl(ret, ret, 32);
+    TCGv t = tcg_temp_new();
+    tcg_gen_shli_tl(t, arg1, 32);
+    tcg_gen_clzi_tl(ret, t, 32);
+    tcg_temp_free(t);
 }
 
 static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
+    return gen_unary(ctx, a, EXT_NONE, gen_clzw);
 }
 
 static void gen_ctzw(TCGv ret, TCGv arg1)
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The bitmanipulation ISA extensions will be ratified as individual
small extension packages instead of a large B-extension.  The first
new instructions through the door (these have completed public review)
are Zb[abcs].

This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
these in target/riscv/cpu.[ch].

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-5-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 4 ++++
 target/riscv/cpu.c | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
         bool ext_u;
         bool ext_h;
         bool ext_v;
+        bool ext_zba;
+        bool ext_zbb;
+        bool ext_zbc;
+        bool ext_zbs;
         bool ext_counters;
         bool ext_ifencei;
         bool ext_icsr;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     /* This is experimental so mark with 'x-' */
     DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
+    DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
+    DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
+    DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
+    DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The following instructions are part of Zba:
 - add.uw (RV64 only)
 - sh[123]add (RV32 and RV64)
 - sh[123]add.uw (RV64-only)
 - slli.uw (RV64-only)

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-6-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              | 20 ++++++++++++--------
 target/riscv/insn_trans/trans_rvb.c.inc | 16 +++++++++++-----
 2 files changed, 23 insertions(+), 13 deletions(-)

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

Zbs 1.0.0 (just as the 0.93 draft-B before) does not provide for W-form
instructions for Zbs (single-bit instructions).  Remove them.

Note that these instructions had already been removed for the 0.93
version of the draft-B extention and have not been present in the
binutils patches circulating in January 2021.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-7-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |  7 ----
 target/riscv/insn_trans/trans_rvb.c.inc | 56 -------------------------
 2 files changed, 63 deletions(-)

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The Zb[abcs] ratification package does not include the proposed
shift-one instructions. There currently is no clear plan to whether
these (or variants of them) will be ratified as Zbo (or a different
extension) or what the timeframe for such a decision could be.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-8-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |  8 ---
 target/riscv/insn_trans/trans_rvb.c.inc | 70 -------------------------
 2 files changed, 78 deletions(-)

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The following instructions are part of Zbs:
 - b{set,clr,ext,inv}
 - b{set,clr,ext,inv}i

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-9-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              | 17 +++++++++--------
 target/riscv/insn_trans/trans_rvb.c.inc | 25 +++++++++++++++----------
 2 files changed, 24 insertions(+), 18 deletions(-)

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The following instructions are part of Zbc:
 - clmul
 - clmulh
 - clmulr

Note that these instructions were already defined in the pre-0.93 and
the 0.93 draft-B proposals, but had not been omitted in the earlier
addition of draft-B to QEmu.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  2 ++
 target/riscv/insn32.decode              |  5 ++++
 target/riscv/bitmanip_helper.c          | 27 +++++++++++++++++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 32 ++++++++++++++++++++++++-
 4 files changed, 65 insertions(+), 1 deletion(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
 /* Special functions */
 DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ roriw      0110000 .......... 101 ..... 0011011 @sh5
 greviw     0110100 .......... 101 ..... 0011011 @sh5
 gorciw     0010100 .......... 101 ..... 0011011 @sh5
 
+# *** RV32 Zbc Standard Extension ***
+clmul      0000101 .......... 001 ..... 0110011 @r
+clmulh     0000101 .......... 011 ..... 0110011 @r
+clmulr     0000101 .......... 010 ..... 0110011 @r
+
 # *** RV32 Zbs Standard Extension ***
 bclr       0100100 .......... 001 ..... 0110011 @r
 bclri      01001. ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@
  *
  * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
  * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
+ * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
 {
     return do_gorc(rs1, rs2, 32);
 }
+
+target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
+{
+    target_ulong result = 0;
+
+    for (int i = 0; i < TARGET_LONG_BITS; i++) {
+        if ((rs2 >> i) & 1) {
+            result ^= (rs1 << i);
+        }
+    }
+
+    return result;
+}
+
+target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
+{
+    target_ulong result = 0;
+
+    for (int i = 0; i < TARGET_LONG_BITS; i++) {
+        if ((rs2 >> i) & 1) {
+            result ^= (rs1 >> (TARGET_LONG_BITS - i - 1));
+        }
+    }
+
+    return result;
+}
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
 /*
- * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
+ * RISC-V translation routines for the Zb[acs] Standard Extension.
  *
  * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
  * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -XXX,XX +XXX,XX @@
     }                                            \
 } while (0)
 
+#define REQUIRE_ZBC(ctx) do {                    \
+    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
+        return false;                            \
+    }                                            \
+} while (0)
+
 #define REQUIRE_ZBS(ctx) do {                    \
     if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) {      \
         return false;                            \
@@ -XXX,XX +XXX,XX @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
     REQUIRE_ZBA(ctx);
     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
 }
+
+static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
+{
+    REQUIRE_ZBC(ctx);
+    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
+}
+
+static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
+{
+     gen_helper_clmulr(dst, src1, src2);
+     tcg_gen_shri_tl(dst, dst, 1);
+}
+
+static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
+{
+    REQUIRE_ZBC(ctx);
+    return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
+}
+
+static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
+{
+    REQUIRE_ZBC(ctx);
+    return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
+}
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

This reassigns the instructions that are part of Zbb into it, with the
notable exceptions of the instructions (rev8, zext.w and orc.b) that
changed due to gorci, grevi and pack not being part of Zb[abcs].

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              | 40 ++++++++++---------
 target/riscv/insn_trans/trans_rvb.c.inc | 51 ++++++++++++++-----------
 2 files changed, 50 insertions(+), 41 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ sh2add_uw  0010000 .......... 100 ..... 0111011 @r
 sh3add_uw  0010000 .......... 110 ..... 0111011 @r
 slli_uw    00001 ............ 001 ..... 0011011 @sh
 
-# *** RV32B Standard Extension ***
+# *** RV32 Zbb Standard Extension ***
+andn       0100000 .......... 111 ..... 0110011 @r
 clz        011000 000000 ..... 001 ..... 0010011 @r2
-ctz        011000 000001 ..... 001 ..... 0010011 @r2
 cpop       011000 000010 ..... 001 ..... 0010011 @r2
+ctz        011000 000001 ..... 001 ..... 0010011 @r2
+max        0000101 .......... 110 ..... 0110011 @r
+maxu       0000101 .......... 111 ..... 0110011 @r
+min        0000101 .......... 100 ..... 0110011 @r
+minu       0000101 .......... 101 ..... 0110011 @r
+orn        0100000 .......... 110 ..... 0110011 @r
+rol        0110000 .......... 001 ..... 0110011 @r
+ror        0110000 .......... 101 ..... 0110011 @r
+rori       01100 ............ 101 ..... 0010011 @sh
 sext_b     011000 000100 ..... 001 ..... 0010011 @r2
 sext_h     011000 000101 ..... 001 ..... 0010011 @r2
-
-andn       0100000 .......... 111 ..... 0110011 @r
-orn        0100000 .......... 110 ..... 0110011 @r
 xnor       0100000 .......... 100 ..... 0110011 @r
+
+# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
+clzw       0110000 00000 ..... 001 ..... 0011011 @r2
+ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
+cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
+rolw       0110000 .......... 001 ..... 0111011 @r
+roriw      0110000 .......... 101 ..... 0011011 @sh5
+rorw       0110000 .......... 101 ..... 0111011 @r
+
+# *** RV32B Standard Extension ***
 pack       0000100 .......... 100 ..... 0110011 @r
 packu      0100100 .......... 100 ..... 0110011 @r
 packh      0000100 .......... 111 ..... 0110011 @r
-min        0000101 .......... 100 ..... 0110011 @r
-minu       0000101 .......... 101 ..... 0110011 @r
-max        0000101 .......... 110 ..... 0110011 @r
-maxu       0000101 .......... 111 ..... 0110011 @r
-ror        0110000 .......... 101 ..... 0110011 @r
-rol        0110000 .......... 001 ..... 0110011 @r
 grev       0110100 .......... 101 ..... 0110011 @r
 gorc       0010100 .......... 101 ..... 0110011 @r
 
-rori       01100. ........... 101 ..... 0010011 @sh
 grevi      01101. ........... 101 ..... 0010011 @sh
 gorci      00101. ........... 101 ..... 0010011 @sh
 
 # *** RV64B Standard Extension (in addition to RV32B) ***
-clzw       0110000 00000 ..... 001 ..... 0011011 @r2
-ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
-cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
-
 packw      0000100 .......... 100 ..... 0111011 @r
 packuw     0100100 .......... 100 ..... 0111011 @r
-rorw       0110000 .......... 101 ..... 0111011 @r
-rolw       0110000 .......... 001 ..... 0111011 @r
 grevw      0110100 .......... 101 ..... 0111011 @r
 gorcw      0010100 .......... 101 ..... 0111011 @r
 
-roriw      0110000 .......... 101 ..... 0011011 @sh5
 greviw     0110100 .......... 101 ..... 0011011 @sh5
 gorciw     0010100 .......... 101 ..... 0011011 @sh5
 
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
 /*
- * RISC-V translation routines for the Zb[acs] Standard Extension.
+ * RISC-V translation routines for the Zb[abcs] Standard Extension.
  *
  * Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
  * Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -XXX,XX +XXX,XX @@
     }                                            \
 } while (0)
 
+#define REQUIRE_ZBB(ctx) do {                    \
+    if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) {      \
+        return false;                            \
+    }                                            \
+} while (0)
+
 #define REQUIRE_ZBC(ctx) do {                    \
     if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) {      \
         return false;                            \
@@ -XXX,XX +XXX,XX @@ static void gen_clz(TCGv ret, TCGv arg1)
 {
     tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
 }
+
 static bool trans_clz(DisasContext *ctx, arg_clz *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_unary(ctx, a, EXT_ZERO, gen_clz);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_ctz(TCGv ret, TCGv arg1)
 
 static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
 }
 
 static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
 }
 
 static bool trans_andn(DisasContext *ctx, arg_andn *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
 }
 
 static bool trans_orn(DisasContext *ctx, arg_orn *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
 }
 
 static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
 
 static bool trans_min(DisasContext *ctx, arg_min *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
 }
 
 static bool trans_max(DisasContext *ctx, arg_max *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
 }
 
 static bool trans_minu(DisasContext *ctx, arg_minu *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
 }
 
 static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
 }
 
 static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
 }
 
 static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
 
 static bool trans_ror(DisasContext *ctx, arg_ror *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
 }
 
 static bool trans_rori(DisasContext *ctx, arg_rori *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
 }
 
 static bool trans_rol(DisasContext *ctx, arg_rol *a)
 {
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_clzw(TCGv ret, TCGv arg1)
 static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_unary(ctx, a, EXT_NONE, gen_clzw);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_ctzw(TCGv ret, TCGv arg1)
 static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
 }
 
 static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     ctx->w = true;
     return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
 }
@@ -XXX,XX +XXX,XX @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
 static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     ctx->w = true;
     return gen_shift(ctx, a, EXT_NONE, gen_rorw);
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
 static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     ctx->w = true;
     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
 }
@@ -XXX,XX +XXX,XX @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
 static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
 {
     REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
+    REQUIRE_ZBB(ctx);
     ctx->w = true;
     return gen_shift(ctx, a, EXT_NONE, gen_rolw);
 }
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The 1.0.0 version of Zbb does not contain gorc/gorci.  Instead, a
orc.b instruction (equivalent to the orc.b pseudo-instruction built on
gorci from pre-0.93 draft-B) is available, mainly targeting
string-processing workloads.

This commit adds the new orc.b instruction and removed gorc/gorci.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-12-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  2 --
 target/riscv/insn32.decode              |  6 +---
 target/riscv/bitmanip_helper.c          | 26 -----------------
 target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++--------------
 4 files changed, 18 insertions(+), 55 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
 /* Bitmanip */
 DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ max        0000101 .......... 110 ..... 0110011 @r
 maxu       0000101 .......... 111 ..... 0110011 @r
 min        0000101 .......... 100 ..... 0110011 @r
 minu       0000101 .......... 101 ..... 0110011 @r
+orc_b      001010 000111 ..... 101 ..... 0010011 @r2
 orn        0100000 .......... 110 ..... 0110011 @r
 rol        0110000 .......... 001 ..... 0110011 @r
 ror        0110000 .......... 101 ..... 0110011 @r
@@ -XXX,XX +XXX,XX @@ pack       0000100 .......... 100 ..... 0110011 @r
 packu      0100100 .......... 100 ..... 0110011 @r
 packh      0000100 .......... 111 ..... 0110011 @r
 grev       0110100 .......... 101 ..... 0110011 @r
-gorc       0010100 .......... 101 ..... 0110011 @r
-
 grevi      01101. ........... 101 ..... 0010011 @sh
-gorci      00101. ........... 101 ..... 0010011 @sh
 
 # *** RV64B Standard Extension (in addition to RV32B) ***
 packw      0000100 .......... 100 ..... 0111011 @r
 packuw     0100100 .......... 100 ..... 0111011 @r
 grevw      0110100 .......... 101 ..... 0111011 @r
-gorcw      0010100 .......... 101 ..... 0111011 @r
 
 greviw     0110100 .......... 101 ..... 0011011 @sh5
-gorciw     0010100 .......... 101 ..... 0011011 @sh5
 
 # *** RV32 Zbc Standard Extension ***
 clmul      0000101 .......... 001 ..... 0110011 @r
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
     return do_grev(rs1, rs2, 32);
 }
 
-static target_ulong do_gorc(target_ulong rs1,
-                            target_ulong rs2,
-                            int bits)
-{
-    target_ulong x = rs1;
-    int i, shift;
-
-    for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
-        if (rs2 & shift) {
-            x |= do_swap(x, adjacent_masks[i], shift);
-        }
-    }
-
-    return x;
-}
-
-target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
-{
-    return do_gorc(rs1, rs2, TARGET_LONG_BITS);
-}
-
-target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
-{
-    return do_gorc(rs1, rs2, 32);
-}
-
 target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
 {
     target_ulong result = 0;
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
 }
 
-static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
+static void gen_orc_b(TCGv ret, TCGv source1)
 {
-    REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
+    TCGv  tmp = tcg_temp_new();
+    TCGv  ones = tcg_constant_tl(dup_const_tl(MO_8, 0x01));
+
+    /* Set lsb in each byte if the byte was zero. */
+    tcg_gen_sub_tl(tmp, source1, ones);
+    tcg_gen_andc_tl(tmp, tmp, source1);
+    tcg_gen_shri_tl(tmp, tmp, 7);
+    tcg_gen_andc_tl(tmp, ones, tmp);
+
+    /* Replicate the lsb of each byte across the byte. */
+    tcg_gen_muli_tl(ret, tmp, 0xff);
+
+    tcg_temp_free(tmp);
 }
 
-static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
+static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
 {
-    REQUIRE_EXT(ctx, RVB);
-    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
+    REQUIRE_ZBB(ctx);
+    return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
 }
 
 #define GEN_SHADD(SHAMT)                                       \
@@ -XXX,XX +XXX,XX @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
     return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
 }
 
-static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
-{
-    REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
-    ctx->w = true;
-    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
-}
-
-static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
-{
-    REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
-    ctx->w = true;
-    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
-}
-
 #define GEN_SHADD_UW(SHAMT)                                       \
 static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
 {                                                                 \
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

With the changes to Zb[abcs], there's some encodings that are
different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,
we'll need a helper macro allowing us to select on RV32, as well.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-13-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ EX_SH(12)
     }                              \
 } while (0)
 
+#define REQUIRE_32BIT(ctx) do { \
+    if (!is_32bit(ctx)) {       \
+        return false;           \
+    }                           \
+} while (0)
+
 #define REQUIRE_64BIT(ctx) do { \
     if (is_32bit(ctx)) {        \
         return false;           \
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The 1.0.0 version of Zbb does not contain grev/grevi.  Instead, a
rev8 instruction (equivalent to the rev8 pseudo-instruction built on
grevi from pre-0.93 draft-B) is available.

This commit adds the new rev8 instruction and removes grev/grevi.

Note that there is no W-form of this instruction (both a
sign-extending and zero-extending 32-bit version can easily be
synthesized by following rev8 with either a srai or srli instruction
on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are
different.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-14-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  2 --
 target/riscv/insn32.decode              | 12 ++++----
 target/riscv/bitmanip_helper.c          | 40 -------------------------
 target/riscv/insn_trans/trans_rvb.c.inc | 40 +++++--------------------
 4 files changed, 15 insertions(+), 79 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
 DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
 
 /* Bitmanip */
-DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
-DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ min        0000101 .......... 100 ..... 0110011 @r
 minu       0000101 .......... 101 ..... 0110011 @r
 orc_b      001010 000111 ..... 101 ..... 0010011 @r2
 orn        0100000 .......... 110 ..... 0110011 @r
+# The encoding for rev8 differs between RV32 and RV64.
+# rev8_32 denotes the RV32 variant.
+rev8_32    011010 011000 ..... 101 ..... 0010011 @r2
 rol        0110000 .......... 001 ..... 0110011 @r
 ror        0110000 .......... 101 ..... 0110011 @r
 rori       01100 ............ 101 ..... 0010011 @sh
@@ -XXX,XX +XXX,XX @@ xnor       0100000 .......... 100 ..... 0110011 @r
 clzw       0110000 00000 ..... 001 ..... 0011011 @r2
 ctzw       0110000 00001 ..... 001 ..... 0011011 @r2
 cpopw      0110000 00010 ..... 001 ..... 0011011 @r2
+# The encoding for rev8 differs between RV32 and RV64.
+# When executing on RV64, the encoding used in RV32 is an illegal
+# instruction, so we use different handler functions to differentiate.
+rev8_64    011010 111000 ..... 101 ..... 0010011 @r2
 rolw       0110000 .......... 001 ..... 0111011 @r
 roriw      0110000 .......... 101 ..... 0011011 @sh5
 rorw       0110000 .......... 101 ..... 0111011 @r
@@ -XXX,XX +XXX,XX @@ rorw       0110000 .......... 101 ..... 0111011 @r
 pack       0000100 .......... 100 ..... 0110011 @r
 packu      0100100 .......... 100 ..... 0110011 @r
 packh      0000100 .......... 111 ..... 0110011 @r
-grev       0110100 .......... 101 ..... 0110011 @r
-grevi      01101. ........... 101 ..... 0010011 @sh
 
 # *** RV64B Standard Extension (in addition to RV32B) ***
 packw      0000100 .......... 100 ..... 0111011 @r
 packuw     0100100 .......... 100 ..... 0111011 @r
-grevw      0110100 .......... 101 ..... 0111011 @r
-
-greviw     0110100 .......... 101 ..... 0011011 @sh5
 
 # *** RV32 Zbc Standard Extension ***
 clmul      0000101 .......... 001 ..... 0110011 @r
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-proto.h"
 #include "tcg/tcg.h"
 
-static const uint64_t adjacent_masks[] = {
-    dup_const(MO_8, 0x55),
-    dup_const(MO_8, 0x33),
-    dup_const(MO_8, 0x0f),
-    dup_const(MO_16, 0xff),
-    dup_const(MO_32, 0xffff),
-    UINT32_MAX
-};
-
-static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
-{
-    return ((x & mask) << shift) | ((x & ~mask) >> shift);
-}
-
-static target_ulong do_grev(target_ulong rs1,
-                            target_ulong rs2,
-                            int bits)
-{
-    target_ulong x = rs1;
-    int i, shift;
-
-    for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
-        if (rs2 & shift) {
-            x = do_swap(x, adjacent_masks[i], shift);
-        }
-    }
-
-    return x;
-}
-
-target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
-{
-    return do_grev(rs1, rs2, TARGET_LONG_BITS);
-}
-
-target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
-{
-    return do_grev(rs1, rs2, 32);
-}
-
 target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
 {
     target_ulong result = 0;
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
     return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
 }
 
-static bool trans_grev(DisasContext *ctx, arg_grev *a)
+static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
 {
-    REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
-}
-
-static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
-{
-    if (shamt == TARGET_LONG_BITS - 8) {
-        /* rev8, byte swaps */
-        tcg_gen_bswap_tl(dest, src);
-    } else {
-        gen_helper_grev(dest, src, tcg_constant_tl(shamt));
-    }
+    REQUIRE_32BIT(ctx);
+    REQUIRE_ZBB(ctx);
+    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
 }
 
-static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
+static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
 {
-    REQUIRE_EXT(ctx, RVB);
-    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
+    REQUIRE_64BIT(ctx);
+    REQUIRE_ZBB(ctx);
+    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
 }
 
 static void gen_orc_b(TCGv ret, TCGv source1)
@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
     return gen_shift(ctx, a, EXT_NONE, gen_rolw);
 }
 
-static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
-{
-    REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
-    ctx->w = true;
-    return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
-}
-
-static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
-{
-    REQUIRE_64BIT(ctx);
-    REQUIRE_EXT(ctx, RVB);
-    ctx->w = true;
-    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
-}
-
 #define GEN_SHADD_UW(SHAMT)                                       \
 static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
 {                                                                 \
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a
zext.h instruction is provided (built on pack/packh from pre-0.93
draft-B) is available.

This commit adds zext.h and removes the pack* instructions.

Note that the encodings for zext.h are different between RV32 and
RV64, which is handled through REQUIRE_32BIT.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-15-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              | 12 ++--
 target/riscv/insn_trans/trans_rvb.c.inc | 86 ++++---------------------
 2 files changed, 21 insertions(+), 77 deletions(-)

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

With everything classified as Zb[abcs] and pre-0.93 draft-B
instructions that are not part of Zb[abcs] removed, we can remove the
remaining support code for RVB.

Note that RVB has been retired for good and misa.B will neither mean
'some' or 'all of' Zb*:
  https://lists.riscv.org/g/tech-bitmanip/message/532

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-16-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 ---
 target/riscv/insn32.decode |  4 ----
 target/riscv/cpu.c         | 26 --------------------------
 3 files changed, 33 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define RVS RV('S')
 #define RVU RV('U')
 #define RVH RV('H')
-#define RVB RV('B')
 
 /* S extension denotes that Supervisor mode exists, however it is possible
    to have a core that support S mode but does not have an MMU and there
@@ -XXX,XX +XXX,XX @@ enum {
 #define PRIV_VERSION_1_10_0 0x00011000
 #define PRIV_VERSION_1_11_0 0x00011100
 
-#define BEXT_VERSION_0_93_0 0x00009300
 #define VEXT_VERSION_0_07_1 0x00000701
 
 enum {
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
         bool ext_f;
         bool ext_d;
         bool ext_c;
-        bool ext_b;
         bool ext_s;
         bool ext_u;
         bool ext_h;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@ rorw       0110000 .......... 101 ..... 0111011 @r
 # instruction, so we use different handler functions to differentiate.
 zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
 
-# *** RV32B Standard Extension ***
-
-# *** RV64B Standard Extension (in addition to RV32B) ***
-
 # *** RV32 Zbc Standard Extension ***
 clmul      0000101 .......... 001 ..... 0110011 @r
 clmulh     0000101 .......... 011 ..... 0110011 @r
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
     env->priv_ver = priv_ver;
 }
 
-static void set_bext_version(CPURISCVState *env, int bext_ver)
-{
-    env->bext_ver = bext_ver;
-}
-
 static void set_vext_version(CPURISCVState *env, int vext_ver)
 {
     env->vext_ver = vext_ver;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         if (cpu->cfg.ext_h) {
             target_misa |= RVH;
         }
-        if (cpu->cfg.ext_b) {
-            int bext_version = BEXT_VERSION_0_93_0;
-            target_misa |= RVB;
-
-            if (cpu->cfg.bext_spec) {
-                if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
-                    bext_version = BEXT_VERSION_0_93_0;
-                } else {
-                    error_setg(errp,
-                           "Unsupported bitmanip spec version '%s'",
-                           cpu->cfg.bext_spec);
-                    return;
-                }
-            } else {
-                qemu_log("bitmanip version is not specified, "
-                         "use the default value v0.93\n");
-            }
-            set_bext_version(env, bext_version);
-        }
         if (cpu->cfg.ext_v) {
             int vext_version = VEXT_VERSION_0_07_1;
             target_misa |= RVV;
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     /* This is experimental so mark with 'x-' */
-    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
     DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
     DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
     DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
-    DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
-- 
2.31.1

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

With the addition of Zb[abcs], we also need to add disassembler
support for these new instructions.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-17-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 157 +++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 154 insertions(+), 3 deletions(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ typedef enum {
     rv_op_fsflags = 316,
     rv_op_fsrmi = 317,
     rv_op_fsflagsi = 318,
+    rv_op_bseti = 319,
+    rv_op_bclri = 320,
+    rv_op_binvi = 321,
+    rv_op_bexti = 322,
+    rv_op_rori = 323,
+    rv_op_clz = 324,
+    rv_op_ctz = 325,
+    rv_op_cpop = 326,
+    rv_op_sext_h = 327,
+    rv_op_sext_b = 328,
+    rv_op_xnor = 329,
+    rv_op_orn = 330,
+    rv_op_andn = 331,
+    rv_op_rol = 332,
+    rv_op_ror = 333,
+    rv_op_sh1add = 334,
+    rv_op_sh2add = 335,
+    rv_op_sh3add = 336,
+    rv_op_sh1add_uw = 337,
+    rv_op_sh2add_uw = 338,
+    rv_op_sh3add_uw = 339,
+    rv_op_clmul = 340,
+    rv_op_clmulr = 341,
+    rv_op_clmulh = 342,
+    rv_op_min = 343,
+    rv_op_minu = 344,
+    rv_op_max = 345,
+    rv_op_maxu = 346,
+    rv_op_clzw = 347,
+    rv_op_ctzw = 348,
+    rv_op_cpopw = 349,
+    rv_op_slli_uw = 350,
+    rv_op_add_uw = 351,
+    rv_op_rolw = 352,
+    rv_op_rorw = 353,
+    rv_op_rev8 = 354,
+    rv_op_zext_h = 355,
+    rv_op_roriw = 356,
+    rv_op_orc_b = 357,
+    rv_op_bset = 358,
+    rv_op_bclr = 359,
+    rv_op_binv = 360,
+    rv_op_bext = 361,
 } rv_op;
 
 /* structures */
@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
     { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
     { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
     { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
+    { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+    { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+    { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+    { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+    { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+    { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+    { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
 };
 
 /* CSR names */
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 0: op = rv_op_addi; break;
             case 1:
                 switch (((inst >> 27) & 0b11111)) {
-                case 0: op = rv_op_slli; break;
+                case 0b00000: op = rv_op_slli; break;
+                case 0b00101: op = rv_op_bseti; break;
+                case 0b01001: op = rv_op_bclri; break;
+                case 0b01101: op = rv_op_binvi; break;
+                case 0b01100:
+                    switch (((inst >> 20) & 0b1111111)) {
+                    case 0b0000000: op = rv_op_clz; break;
+                    case 0b0000001: op = rv_op_ctz; break;
+                    case 0b0000010: op = rv_op_cpop; break;
+                      /* 0b0000011 */
+                    case 0b0000100: op = rv_op_sext_b; break;
+                    case 0b0000101: op = rv_op_sext_h; break;
+                    }
+                    break;
                 }
                 break;
             case 2: op = rv_op_slti; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 4: op = rv_op_xori; break;
             case 5:
                 switch (((inst >> 27) & 0b11111)) {
-                case 0: op = rv_op_srli; break;
-                case 8: op = rv_op_srai; break;
+                case 0b00000: op = rv_op_srli; break;
+                case 0b00101: op = rv_op_orc_b; break;
+                case 0b01000: op = rv_op_srai; break;
+                case 0b01001: op = rv_op_bexti; break;
+                case 0b01100: op = rv_op_rori; break;
+                case 0b01101:
+                    switch ((inst >> 20) & 0b1111111) {
+                    case 0b0111000: op = rv_op_rev8; break;
+                    }
+                    break;
                 }
                 break;
             case 6: op = rv_op_ori; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 1:
                 switch (((inst >> 25) & 0b1111111)) {
                 case 0: op = rv_op_slliw; break;
+                case 4: op = rv_op_slli_uw; break;
+                case 48:
+                    switch ((inst >> 20) & 0b11111) {
+                    case 0b00000: op = rv_op_clzw; break;
+                    case 0b00001: op = rv_op_ctzw; break;
+                    case 0b00010: op = rv_op_cpopw; break;
+                    }
+                    break;
                 }
                 break;
             case 5:
                 switch (((inst >> 25) & 0b1111111)) {
                 case 0: op = rv_op_srliw; break;
                 case 32: op = rv_op_sraiw; break;
+                case 48: op = rv_op_roriw; break;
                 }
                 break;
             }
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 13: op = rv_op_divu; break;
             case 14: op = rv_op_rem; break;
             case 15: op = rv_op_remu; break;
+            case 36:
+                switch ((inst >> 20) & 0b11111) {
+                case 0: op = rv_op_zext_h; break;
+                }
+                break;
+            case 41: op = rv_op_clmul; break;
+            case 42: op = rv_op_clmulr; break;
+            case 43: op = rv_op_clmulh; break;
+            case 44: op = rv_op_min; break;
+            case 45: op = rv_op_minu; break;
+            case 46: op = rv_op_max; break;
+            case 47: op = rv_op_maxu; break;
+            case 130: op = rv_op_sh1add; break;
+            case 132: op = rv_op_sh2add; break;
+            case 134: op = rv_op_sh3add; break;
+            case 161: op = rv_op_bset; break;
             case 256: op = rv_op_sub; break;
+            case 260: op = rv_op_xnor; break;
             case 261: op = rv_op_sra; break;
+            case 262: op = rv_op_orn; break;
+            case 263: op = rv_op_andn; break;
+            case 289: op = rv_op_bclr; break;
+            case 293: op = rv_op_bext; break;
+            case 385: op = rv_op_rol; break;
+            case 386: op = rv_op_ror; break;
+            case 417: op = rv_op_binv; break;
             }
             break;
         case 13: op = rv_op_lui; break;
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 13: op = rv_op_divuw; break;
             case 14: op = rv_op_remw; break;
             case 15: op = rv_op_remuw; break;
+            case 32: op = rv_op_add_uw; break;
+            case 36:
+                switch ((inst >> 20) & 0b11111) {
+                case 0: op = rv_op_zext_h; break;
+                }
+                break;
+            case 130: op = rv_op_sh1add_uw; break;
+            case 132: op = rv_op_sh2add_uw; break;
+            case 134: op = rv_op_sh3add_uw; break;
             case 256: op = rv_op_subw; break;
             case 261: op = rv_op_sraw; break;
+            case 385: op = rv_op_rolw; break;
+            case 389: op = rv_op_rorw; break;
             }
             break;
         case 16:
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect.
Modifying the floating-point state when V=1 causes both fields to
be set to 3 (Dirty).

However, it's possible that HS-level sstatus.FS is Clean and VS-level
vsstatus.FS is Dirty at the time mark_fs_dirty() is called when V=1.
We can't early return for this case because we still need to set
sstatus.FS to Dirty according to spec.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Vincent Chen <vincent.chen@sifive.com>
Tested-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210921020234.123448-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       |  4 ++++
 target/riscv/translate.c | 30 +++++++++++++++++-------------
 2 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, SEW, 5, 3)
 FIELD(TB_FLAGS, VILL, 8, 1)
 /* Is a Hypervisor instruction load/store allowed? */
 FIELD(TB_FLAGS, HLSX, 9, 1)
+FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
 
 bool riscv_cpu_is_32bit(CPURISCVState *env);
 
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                 get_field(env->hstatus, HSTATUS_HU))) {
             flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
         }
+
+        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
+                           get_field(env->mstatus_hs, MSTATUS_FS));
     }
 #endif
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     target_ulong misa;
     uint32_t opcode;
     uint32_t mstatus_fs;
+    uint32_t mstatus_hs_fs;
     uint32_t mem_idx;
     /* Remember the rounding mode encoded in the previous fp instruction,
        which we have already installed into env->fp_status.  Or -1 for
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 static void mark_fs_dirty(DisasContext *ctx)
 {
     TCGv tmp;
-    target_ulong sd;
+    target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
 
-    if (ctx->mstatus_fs == MSTATUS_FS) {
-        return;
-    }
-    /* Remember the state change for the rest of the TB.  */
-    ctx->mstatus_fs = MSTATUS_FS;
+    if (ctx->mstatus_fs != MSTATUS_FS) {
+        /* Remember the state change for the rest of the TB. */
+        ctx->mstatus_fs = MSTATUS_FS;
 
-    tmp = tcg_temp_new();
-    sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+        tmp = tcg_temp_new();
+        tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
+        tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+        tcg_temp_free(tmp);
+    }
 
-    tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
-    tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
-    tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+    if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
+        /* Remember the stage change for the rest of the TB. */
+        ctx->mstatus_hs_fs = MSTATUS_FS;
 
-    if (ctx->virt_enabled) {
+        tmp = tcg_temp_new();
         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
         tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+        tcg_temp_free(tmp);
     }
-    tcg_temp_free(tmp);
 }
 #else
 static inline void mark_fs_dirty(DisasContext *ctx) { }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->frm = -1;  /* unknown rounding mode */
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
     ctx->vlen = cpu->cfg.vlen;
+    ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
     ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
     ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
     ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
-- 
2.31.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The current MCHP_PFSOC_MMUART_REG_SIZE definition represent the
size occupied by all the registers. However all registers are
32-bit wide, and the MemoryRegionOps handlers are restricted to
32-bit:

static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
      .read = mchp_pfsoc_mmuart_read,
      .write = mchp_pfsoc_mmuart_write,
      .impl = {
          .min_access_size = 4,
          .max_access_size = 4,
      },

Avoid being triskaidekaphobic, simplify by using the number of
registers.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210925133407.1259392-2-f4bug@amsat.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/mchp_pfsoc_mmuart.h |  4 ++--
 hw/char/mchp_pfsoc_mmuart.c         | 14 ++++++++------
 2 files changed, 10 insertions(+), 8 deletions(-)

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Our device have 2 different I/O regions:
- a 16550 UART mapped for 32-bit accesses
- 13 extra registers

Instead of mapping each region on the main bus, introduce
a container, map the 2 devices regions on the container,
and map the container on the main bus.

Before:

(qemu) info mtree
    ...
    0000000020100000-000000002010001f (prio 0, i/o): serial
    0000000020100020-000000002010101f (prio 0, i/o): mchp.pfsoc.mmuart
    0000000020102000-000000002010201f (prio 0, i/o): serial
    0000000020102020-000000002010301f (prio 0, i/o): mchp.pfsoc.mmuart
    0000000020104000-000000002010401f (prio 0, i/o): serial
    0000000020104020-000000002010501f (prio 0, i/o): mchp.pfsoc.mmuart
    0000000020106000-000000002010601f (prio 0, i/o): serial
    0000000020106020-000000002010701f (prio 0, i/o): mchp.pfsoc.mmuart

After:

(qemu) info mtree
    ...
    0000000020100000-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart
      0000000020100000-000000002010001f (prio 0, i/o): serial
      0000000020100020-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
    0000000020102000-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart
      0000000020102000-000000002010201f (prio 0, i/o): serial
      0000000020102020-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
    0000000020104000-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart
      0000000020104000-000000002010401f (prio 0, i/o): serial
      0000000020104020-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
    0000000020106000-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart
      0000000020106000-000000002010601f (prio 0, i/o): serial
      0000000020106020-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart.regs

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 20210925133407.1259392-3-f4bug@amsat.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/mchp_pfsoc_mmuart.h |  1 +
 hw/char/mchp_pfsoc_mmuart.c         | 11 ++++++++---
 2 files changed, 9 insertions(+), 3 deletions(-)

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

- Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it
- Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART
- Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize()
- Add DeviceReset() method
- Add vmstate structure for migration
- Register device in 'input' category
- Keep mchp_pfsoc_mmuart_create() behavior

Note, serial_mm_init() calls qdev_set_legacy_instance_id().
This call is only needed for backwards-compatibility of incoming
migration data with old versions of QEMU which implemented migration
of devices with hand-rolled code. Since this device didn't previously
handle migration at all, then it doesn't need to set the legacy
instance ID.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210925133407.1259392-4-f4bug@amsat.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/mchp_pfsoc_mmuart.h | 12 +++-
 hw/char/mchp_pfsoc_mmuart.c         | 97 +++++++++++++++++++++++++----
 2 files changed, 93 insertions(+), 16 deletions(-)

diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/mchp_pfsoc_mmuart.h
+++ b/include/hw/char/mchp_pfsoc_mmuart.h
@@ -XXX,XX +XXX,XX @@
 #ifndef HW_MCHP_PFSOC_MMUART_H
 #define HW_MCHP_PFSOC_MMUART_H
 
+#include "hw/sysbus.h"
 #include "hw/char/serial.h"
 
 #define MCHP_PFSOC_MMUART_REG_COUNT 13
 
+#define TYPE_MCHP_PFSOC_UART "mchp.pfsoc.uart"
+OBJECT_DECLARE_SIMPLE_TYPE(MchpPfSoCMMUartState, MCHP_PFSOC_UART)
+
 typedef struct MchpPfSoCMMUartState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
     MemoryRegion container;
     MemoryRegion iomem;
-    hwaddr base;
-    qemu_irq irq;
 
-    SerialMM *serial;
+    SerialMM serial_mm;
 
     uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT];
 } MchpPfSoCMMUartState;
diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/mchp_pfsoc_mmuart.c
+++ b/hw/char/mchp_pfsoc_mmuart.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "qemu/log.h"
-#include "chardev/char.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
 #include "hw/char/mchp_pfsoc_mmuart.h"
+#include "hw/qdev-properties.h"
 
 #define REGS_OFFSET 0x20
 
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
     },
 };
 
-MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
-    hwaddr base, qemu_irq irq, Chardev *chr)
+static void mchp_pfsoc_mmuart_reset(DeviceState *dev)
+{
+    MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev);
+
+    memset(s->reg, 0, sizeof(s->reg));
+    device_cold_reset(DEVICE(&s->serial_mm));
+}
+
+static void mchp_pfsoc_mmuart_init(Object *obj)
 {
-    MchpPfSoCMMUartState *s;
+    MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(obj);
 
-    s = g_new0(MchpPfSoCMMUartState, 1);
+    object_initialize_child(obj, "serial-mm", &s->serial_mm, TYPE_SERIAL_MM);
+    object_property_add_alias(obj, "chardev", OBJECT(&s->serial_mm), "chardev");
+}
 
-    memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000);
+static void mchp_pfsoc_mmuart_realize(DeviceState *dev, Error **errp)
+{
+    MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev);
 
-    memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
+    qdev_prop_set_uint8(DEVICE(&s->serial_mm), "regshift", 2);
+    qdev_prop_set_uint32(DEVICE(&s->serial_mm), "baudbase", 399193);
+    qdev_prop_set_uint8(DEVICE(&s->serial_mm), "endianness",
+                        DEVICE_LITTLE_ENDIAN);
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->serial_mm), errp)) {
+        return;
+    }
+
+    sysbus_pass_irq(SYS_BUS_DEVICE(dev), SYS_BUS_DEVICE(&s->serial_mm));
+
+    memory_region_init(&s->container, OBJECT(s), "mchp.pfsoc.mmuart", 0x1000);
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
+
+    memory_region_add_subregion(&s->container, 0,
+                    sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial_mm), 0));
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &mchp_pfsoc_mmuart_ops, s,
                           "mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET);
     memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem);
+}
 
-    s->base = base;
-    s->irq = irq;
+static const VMStateDescription mchp_pfsoc_mmuart_vmstate = {
+    .name = "mchp.pfsoc.uart",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(reg, MchpPfSoCMMUartState,
+                             MCHP_PFSOC_MMUART_REG_COUNT),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void mchp_pfsoc_mmuart_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = mchp_pfsoc_mmuart_realize;
+    dc->reset = mchp_pfsoc_mmuart_reset;
+    dc->vmsd = &mchp_pfsoc_mmuart_vmstate;
+    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
+}
+
+static const TypeInfo mchp_pfsoc_mmuart_info = {
+    .name          = TYPE_MCHP_PFSOC_UART,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(MchpPfSoCMMUartState),
+    .instance_init = mchp_pfsoc_mmuart_init,
+    .class_init    = mchp_pfsoc_mmuart_class_init,
+};
+
+static void mchp_pfsoc_mmuart_register_types(void)
+{
+    type_register_static(&mchp_pfsoc_mmuart_info);
+}
+
+type_init(mchp_pfsoc_mmuart_register_types)
+
+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
+                                               hwaddr base,
+                                               qemu_irq irq, Chardev *chr)
+{
+    DeviceState *dev = qdev_new(TYPE_MCHP_PFSOC_UART);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 
-    s->serial = serial_mm_init(&s->container, 0, 2, irq, 399193, chr,
-                               DEVICE_LITTLE_ENDIAN);
+    qdev_prop_set_chr(dev, "chardev", chr);
+    sysbus_realize(sbd, &error_fatal);
 
-    memory_region_add_subregion(sysmem, base, &s->container);
+    memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(sbd, 0));
+    sysbus_connect_irq(sbd, 0, irq);
 
-    return s;
+    return MCHP_PFSOC_UART(dev);
 }
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

At present the codes detect whether the DMA channel is claimed by:

claimed = !!s->chan[ch].control & CONTROL_CLAIM;

As ! has higher precedence over & (bitwise and), this is essentially

claimed = (!!s->chan[ch].control) & CONTROL_CLAIM;

which is wrong, as any non-zero bit set in the control register will
produce a result of a claimed channel.

Fixes: de7c7988d25d ("hw/dma: sifive_pdma: reset Next* registers when Control.claim is set")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210927072124.1564129-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/dma/sifive_pdma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/sifive_pdma.c
+++ b/hw/dma/sifive_pdma.c
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
     offset &= 0xfff;
     switch (offset) {
     case DMA_CONTROL:
-        claimed = !!s->chan[ch].control & CONTROL_CLAIM;
+        claimed = !!(s->chan[ch].control & CONTROL_CLAIM);
 
         if (!claimed && (value & CONTROL_CLAIM)) {
             /* reset Next* registers */
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

If Control.run bit is set while not preserving the Control.claim
bit, the DMA transfer shall not be started.

The following result is PDMA tested in U-Boot on Unleashed board:

=> mw.l 0x3000000 0x0                      <= Disclaim channel 0
=> mw.l 0x3000000 0x1                      <= Claim channel 0
=> mw.l 0x3000004 0x55000000               <= wsize = rsize = 5 (2^5 = 32 bytes)
=> mw.q 0x3000008 0x2                      <= NextBytes = 2
=> mw.q 0x3000010 0x84000000               <= NextDestination = 0x84000000
=> mw.q 0x3000018 0x84001000               <= NextSource = 0x84001000
=> mw.l 0x84000000 0x87654321              <= Fill test data to dst
=> mw.l 0x84001000 0x12345678              <= Fill test data to src
=> md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
84000000: 87654321                               !Ce.
84001000: 12345678                               xV4.
=> md.l 0x3000000 8                        <= Dump PDMA status
03000000: 00000001 55000000 00000002 00000000    .......U........
03000010: 84000000 00000000 84001000 00000000    ................
=> mw.l 0x3000000 0x2                      <= Set channel 0 run bit only
=> md.l 0x3000000 8                        <= Dump PDMA status
03000000: 00000000 55000000 00000002 00000000    .......U........
03000010: 84000000 00000000 84001000 00000000    ................
=> md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
84000000: 87654321                               !Ce.
84001000: 12345678                               xV4.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210927072124.1564129-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/dma/sifive_pdma.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/sifive_pdma.c
+++ b/hw/dma/sifive_pdma.c
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
 {
     SiFivePDMAState *s = opaque;
     int ch = SIFIVE_PDMA_CHAN_NO(offset);
-    bool claimed;
+    bool claimed, run;
 
     if (ch >= SIFIVE_PDMA_CHANS) {
         qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
     switch (offset) {
     case DMA_CONTROL:
         claimed = !!(s->chan[ch].control & CONTROL_CLAIM);
+        run = !!(s->chan[ch].control & CONTROL_RUN);
 
         if (!claimed && (value & CONTROL_CLAIM)) {
             /* reset Next* registers */
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
             s->chan[ch].next_src = 0;
         }
 
+        /* claim bit can only be cleared when run is low */
+        if (run && !(value & CONTROL_CLAIM)) {
+            value |= CONTROL_CLAIM;
+        }
+
         s->chan[ch].control = value;
 
         /*
          * If channel was not claimed before run bit is set,
+         * or if the channel is disclaimed when run was low,
          * DMA won't run.
          */
-        if (!claimed) {
+        if (!claimed || (!run && !(value & CONTROL_CLAIM))) {
             s->chan[ch].control &= ~CONTROL_RUN;
             return;
         }
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

Mark the shakti_c machine as not user creatable.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/639
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <c617a04d4e3dd041a3427b47a1b1d5ab475a2edd.1632871759.git.alistair.francis@wdc.com>
---
 hw/riscv/shakti_c.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
     dc->realize = shakti_c_soc_state_realize;
+    /*
+     * Reasons:
+     *     - Creates CPUS in riscv_hart_realize(), and can create unintended
+     *       CPUs
+     *     - Uses serial_hds in realize function, thus can't be used twice
+     */
+    dc->user_creatable = false;
 }
 
 static void shakti_c_soc_instance_init(Object *obj)
-- 
2.31.1

The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:

Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528

for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:

target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

* APLICs add child earlier than realize
* Fix exposure of Zkr
* Raise exceptions on wrs.nto
* Implement SBI debug console (DBCN) calls for KVM
* Support 64-bit addresses for initrd
* Change RISCV_EXCP_SEMIHOST exception number to 63
* Tolerate KVM disable ext errors
* Set tval in breakpoints
* Add support for Zve32x extension
* Add support for Zve64x extension
* Relax vector register check in RISCV gdbstub
* Fix the element agnostic Vector function problem
* Fix Zvkb extension config
* Implement dynamic establishment of custom decoder
* Add th.sxstatus CSR emulation
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
* Check single width operator for vector fp widen instructions
* Check single width operator for vfncvt.rod.f.f.w
* Remove redudant SEW checking for vector fp narrow/widen instructions
* Prioritize pmp errors in raise_mmu_exception()
* Do not set mtval2 for non guest-page faults
* Remove experimental prefix from "B" extension
* Fixup CBO extension register calculation
* Fix the hart bit setting of AIA
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
* Decode all of the pmpcfg and pmpaddr CSRs
* Raise an exception when CSRRS/CSRRC writes a read-only CSR

----------------------------------------------------------------
Alexei Filippov (1):
      target/riscv: do not set mtval2 for non guest-page faults

Alistair Francis (2):
      target/riscv: rvzicbo: Fixup CBO extension register calculation
      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs

Andrew Jones (2):
      target/riscv/kvm: Fix exposure of Zkr
      target/riscv: Raise exceptions on wrs.nto

Cheng Yang (1):
      hw/riscv/boot.c: Support 64-bit address for initrd

Christoph Müllner (1):
      riscv: thead: Add th.sxstatus CSR emulation

Clément Léger (1):
      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

Daniel Henrique Barboza (6):
      target/riscv/kvm: implement SBI debug console (DBCN) calls
      target/riscv/kvm: tolerate KVM disable ext errors
      target/riscv/debug: set tval=pc in breakpoint exceptions
      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
      target/riscv: prioritize pmp errors in raise_mmu_exception()
      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Huang Tao (2):
      target/riscv: Fix the element agnostic function problem
      target/riscv: Implement dynamic establishment of custom decoder

Jason Chien (3):
      target/riscv: Add support for Zve32x extension
      target/riscv: Add support for Zve64x extension
      target/riscv: Relax vector register check in RISCV gdbstub

Max Chou (4):
      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
      target/riscv: rvv: Check single width operator for vector fp widen instructions
      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions

Rob Bradford (1):
      target/riscv: Remove experimental prefix from "B" extension

Yangyu Chen (1):
      target/riscv/cpu.c: fix Zvkb extension config

Yong-Xuan Wang (1):
      target/riscv/kvm.c: Fix the hart bit setting of AIA

Yu-Ming Chang (1):
      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

yang.zhang (1):
      hw/intc/riscv_aplic: APLICs should add child earlier than realize

From: "yang.zhang" <yang.zhang@hexintek.com>

Since only root APLICs can have hw IRQ lines, aplic->parent should
be initialized first.

Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     qdev_prop_set_bit(dev, "msimode", msimode);
     qdev_prop_set_bit(dev, "mmode", mmode);
 
+    if (parent) {
+        riscv_aplic_add_child(parent, dev);
+    }
+
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
     if (!is_kvm_aia(msimode)) {
         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     }
 
-    if (parent) {
-        riscv_aplic_add_child(parent, dev);
-    }
-
     if (!msimode) {
         for (i = 0; i < num_harts; i++) {
             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

The Zkr extension may only be exposed to KVM guests if the VMM
implements the SEED CSR. Use the same implementation as TCG.

Without this patch, running with a KVM which does not forward the
SEED CSR access to QEMU will result in an ILL exception being
injected into the guest (this results in Linux guests crashing on
boot). And, when running with a KVM which does forward the access,
QEMU will crash, since QEMU doesn't know what to do with the exit.

Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 +++
 target/riscv/csr.c         | 18 ++++++++++++++----
 target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 3 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 
 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask);
+
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
 #endif
 
 /* Crypto Extension */
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-                               target_ulong *ret_value,
-                               target_ulong new_value,
-                               target_ulong write_mask)
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask)
 {
     uint16_t random_v;
     Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
         rval = random_v | SEED_OPST_ES16;
     }
 
+    return rval;
+}
+
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value,
+                               target_ulong write_mask)
+{
+    target_ulong rval;
+
+    rval = riscv_new_csr_seed(new_value, write_mask);
+
     if (ret_value) {
         *ret_value = rval;
     }
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
     return ret;
 }
 
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
+{
+    target_ulong csr_num = run->riscv_csr.csr_num;
+    target_ulong new_value = run->riscv_csr.new_value;
+    target_ulong write_mask = run->riscv_csr.write_mask;
+    int ret = 0;
+
+    switch (csr_num) {
+    case CSR_SEED:
+        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled CSR EXIT for CSR %lx\n",
+                      __func__, csr_num);
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
     case KVM_EXIT_RISCV_SBI:
         ret = kvm_riscv_handle_sbi(cs, run);
         break;
+    case KVM_EXIT_RISCV_CSR:
+        ret = kvm_riscv_handle_csr(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                       __func__, run->exit_reason);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

Implementing wrs.nto to always just return is consistent with the
specification, as the instruction is permitted to terminate the
stall for any reason, but it's not useful for virtualization, where
we'd like the guest to trap to the hypervisor in order to allow
scheduling of the lock holding VCPU. Change to always immediately
raise exceptions when the appropriate conditions are present,
otherwise continue to just return. Note, immediately raising
exceptions is also consistent with the specification since the
time limit that should expire prior to the exception is
implementation-specific.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                       |  1 +
 target/riscv/op_helper.c                    | 11 ++++++++
 target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
 3 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
+DEF_HELPER_1(wrs_nto, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 DEF_HELPER_1(tlb_flush_all, void, env)
 /* Native Debug */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
     }
 }
 
+void helper_wrs_nto(CPURISCVState *env)
+{
+    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
+        get_field(env->hstatus, HSTATUS_VTW) &&
+        !get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+}
+
 void helper_tlb_flush(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static bool trans_wrs(DisasContext *ctx)
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
 {
     if (!ctx->cfg_ptr->ext_zawrs) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
     return true;
 }
 
-#define GEN_TRANS_WRS(insn)                                     \
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
-{                                                               \
-    (void)a;                                                    \
-    return trans_wrs(ctx);                                      \
-}
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
+{
+    if (!ctx->cfg_ptr->ext_zawrs) {
+        return false;
+    }
 
-GEN_TRANS_WRS(wrs_nto)
-GEN_TRANS_WRS(wrs_sto)
+    /*
+     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
+     * should raise an exception when the implementation-specific bounded time
+     * limit has expired. Our time limit is zero, so we either return
+     * immediately, as does our implementation of wrs.sto, or raise an
+     * exception, as handled by the wrs.nto helper.
+     */
+#ifndef CONFIG_USER_ONLY
+    gen_helper_wrs_nto(tcg_env);
+#endif
+
+    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
+    return trans_wrs_sto(ctx, NULL);
+}
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

SBI defines a Debug Console extension "DBCN" that will, in time, replace
the legacy console putchar and getchar SBI extensions.

The appeal of the DBCN extension is that it allows multiple bytes to be
read/written in the SBI console in a single SBI call.

As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
module to userspace. But this will only happens if the KVM module
actually supports this SBI extension and we activate it.

We'll check for DBCN support during init time, checking if get-reg-list
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
kvm_set_one_reg() during kvm_arch_init_vcpu().

Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
SBI_EXT_DBCN, reading and writing as required.

A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
host, takes around 20 seconds to boot without using DBCN. With this
patch we're taking around 14 seconds to boot due to the speed-up in the
terminal output.  There's no change in boot time if the guest isn't
using earlycon.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/sbi_ecall_interface.h |  17 +++++
 target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
 2 files changed, 128 insertions(+)

diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/sbi_ecall_interface.h
+++ b/target/riscv/sbi_ecall_interface.h
@@ -XXX,XX +XXX,XX @@
 
 /* clang-format off */
 
+#define SBI_SUCCESS                      0
+#define SBI_ERR_FAILED                  -1
+#define SBI_ERR_NOT_SUPPORTED           -2
+#define SBI_ERR_INVALID_PARAM           -3
+#define SBI_ERR_DENIED                  -4
+#define SBI_ERR_INVALID_ADDRESS         -5
+#define SBI_ERR_ALREADY_AVAILABLE       -6
+#define SBI_ERR_ALREADY_STARTED         -7
+#define SBI_ERR_ALREADY_STOPPED         -8
+#define SBI_ERR_NO_SHMEM                -9
+
 /* SBI Extension IDs */
 #define SBI_EXT_0_1_SET_TIMER           0x0
 #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_IPI                     0x735049
 #define SBI_EXT_RFENCE                  0x52464E43
 #define SBI_EXT_HSM                     0x48534D
+#define SBI_EXT_DBCN                    0x4442434E
 
 /* SBI function IDs for BASE extension */
 #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_HSM_HART_STOP           0x1
 #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 
+/* SBI function IDs for DBCN extension */
+#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
+#define SBI_EXT_DBCN_CONSOLE_READ       0x1
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
+
 #define SBI_HSM_HART_STATUS_STARTED     0x0
 #define SBI_HSM_HART_STATUS_STOPPED     0x1
 #define SBI_HSM_HART_STATUS_START_PENDING   0x2
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
 };
 
+static KVMCPUConfig kvm_sbi_dbcn = {
+    .name = "sbi_dbcn",
+    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
+                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
+};
+
 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
 {
     CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
     return 0;
 }
 
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
+                                             KVMScratchCPU *kvmcpu,
+                                             struct kvm_reg_list *reglist)
+{
+    struct kvm_reg_list *reg_search;
+
+    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
+                         sizeof(uint64_t), uint64_cmp);
+
+    if (reg_search) {
+        kvm_sbi_dbcn.supported = true;
+    }
+}
+
 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                  struct kvm_reg_list *reglist)
 {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     if (riscv_has_ext(&cpu->env, RVV)) {
         kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
     }
+
+    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
 }
 
 static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
     return ret;
 }
 
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
+{
+    target_ulong reg = 1;
+
+    if (!kvm_sbi_dbcn.supported) {
+        return 0;
+    }
+
+    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
+}
+
 int kvm_arch_init_vcpu(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     kvm_riscv_update_cpu_misa_ext(cpu, cs);
     kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 
+    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
+{
+    g_autofree uint8_t *buf = NULL;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    target_ulong num_bytes;
+    uint64_t addr;
+    unsigned char ch;
+    int ret;
+
+    switch (run->riscv_sbi.function_id) {
+    case SBI_EXT_DBCN_CONSOLE_READ:
+    case SBI_EXT_DBCN_CONSOLE_WRITE:
+        num_bytes = run->riscv_sbi.args[0];
+
+        if (num_bytes == 0) {
+            run->riscv_sbi.ret[0] = SBI_SUCCESS;
+            run->riscv_sbi.ret[1] = 0;
+            break;
+        }
+
+        addr = run->riscv_sbi.args[1];
+
+        /*
+         * Handle the case where a 32 bit CPU is running in a
+         * 64 bit addressing env.
+         */
+        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
+            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
+        }
+
+        buf = g_malloc0(num_bytes);
+
+        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
+            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
+                             "reading chardev");
+                exit(1);
+            }
+
+            cpu_physical_memory_write(addr, buf, ret);
+        } else {
+            cpu_physical_memory_read(addr, buf, num_bytes);
+
+            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
+                             "writing chardev");
+                exit(1);
+            }
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = ret;
+        break;
+    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
+        ch = run->riscv_sbi.args[0];
+        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+
+        if (ret < 0) {
+            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
+                         "writing chardev");
+            exit(1);
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = 0;
+        break;
+    default:
+        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
+    }
+}
+
 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
         }
         ret = 0;
         break;
+    case SBI_EXT_DBCN:
+        kvm_riscv_handle_sbi_dbcn(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP,
                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
-- 
2.45.1

From: Cheng Yang <yangcheng.work@foxmail.com>

Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
     if (fdt) {
         end = start + size;
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
     }
 }
 
-- 
2.45.1

From: Clément Léger <cleger@rivosinc.com>

The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.

Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
-    RISCV_EXCP_SEMIHOST = 0x10,
     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+    RISCV_EXCP_SEMIHOST = 0x3f,
 } RISCVException;
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
enabled, will fail with a kernel oops SIGILL right at the start. The
reason is that we can't expose zkr without implementing the SEED CSR.
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
allow it we'll error out and never boot.

In hindsight this is too strict. If we keep proceeding, despite not
disabling the extension in the KVM vcpu, we'll not add the extension in
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
it's ok to keep booting in this case.

Change our current logic to not error out if we fail to disable an
extension in kvm_set_one_reg(), but show a warning and keep booting. It
is important to throw a warning because we must make the user aware that
the extension is still available in the vcpu, meaning that an
ill-behaved guest can ignore the riscv,isa settings and  use the
extension.

The case we're handling happens with an EINVAL error code. If we fail to
disable the extension in KVM for any other reason, error out.

We'll also keep erroring out when we fail to enable an extension in KVM,
since adding the extension in riscv,isa at this point will cause a guest
malfunction because the extension isn't enabled in the vcpu.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
         ret = kvm_set_one_reg(cs, id, &reg);
         if (ret != 0) {
-            error_report("Unable to %s extension %s in KVM, error %d",
-                         reg ? "enable" : "disable",
-                         multi_ext_cfg->name, ret);
-            exit(EXIT_FAILURE);
+            if (!reg && ret == -EINVAL) {
+                warn_report("KVM cannot disable extension %s",
+                            multi_ext_cfg->name);
+            } else {
+                error_report("Unable to enable extension %s in KVM, error %d",
+                             multi_ext_cfg->name, ret);
+                exit(EXIT_FAILURE);
+            }
         }
     }
 }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":

"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the tval CSR with either
zero or the faulting virtual address. The faulting virtual address for
an mcontrol6 trigger with action = 0 is the address being accessed and
which caused that trigger to fire."

A similar text is also found in the Debug spec section 5.7.11 w.r.t.
mcontrol.

Note that what we're doing ATM is not violating the spec, but it's
simple enough to set mtval/stval and it makes life easier for any
software that relies on this info.

Given that we always use action = 0, save the faulting address for the
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
used as as scratch area for traps with address information. 'tval' is
then set during riscv_cpu_do_interrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 1 +
 target/riscv/debug.c      | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             tval = env->bins;
             break;
         case RISCV_EXCP_BREAKPOINT:
+            tval = env->badaddr;
             if (cs->watchpoint_hit) {
                 tval = cs->watchpoint_hit->hitaddr;
                 cs->watchpoint_hit = NULL;
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
                     /* check U/S/M bit against current privilege level */
                     if ((ctrl >> 3) & BIT(env->priv)) {
+                        env->badaddr = pc;
                         return true;
                     }
                 }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                     if (env->virt_enabled) {
                         /* check VU/VS bit against current privilege level */
                         if ((ctrl >> 23) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     } else {
                         /* check U/S/M bit against current privilege level */
                         if ((ctrl >> 3) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Privileged spec section 4.1.9 mentions:

"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)

If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."

A similar text is found for mtval in section 3.1.16.

Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.

Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     } else {
+        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+                      offsetof(CPURISCVState, badaddr));
         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
     }
     return true;
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/cpu.c                      |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
 target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 6 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zhinx;
     bool ext_zhinxmin;
     bool ext_zve32f;
+    bool ext_zve32x;
     bool ext_zve64f;
     bool ext_zve64d;
     bool ext_zvbb;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
     *cs_base = 0;
 
-    if (cpu->cfg.ext_zve32f) {
+    if (cpu->cfg.ext_zve32x) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_cfg(env)->ext_zve32f) {
+    if (riscv_cpu_cfg(env)->ext_zve32x) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-        return;
+    /* The Zve32f extension depends on the Zve32x extension */
+    if (cpu->cfg.ext_zve32f) {
+        if (!riscv_has_ext(env, RVF)) {
+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+            return;
+        }
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
     }
 
     if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
     }
 
-    /*
-     * In principle Zve*x would also suffice here, were they supported
-     * in qemu
-     */
     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
-         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
+         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
         error_setg(errp,
                    "Vector crypto extensions require V or Zve* extensions");
         return;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h     |  1 +
 target/riscv/cpu.c         |  2 ++
 target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 3 files changed, 14 insertions(+), 6 deletions(-)

From: Jason Chien <jason.chien@sifive.com>

In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
                                  0);
     }
-    if (env->misa_ext & RVV) {
+    if (cpu->cfg.ext_zve32x) {
         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
                                  riscv_gdb_set_vector,
                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.

However, this function can't deal the big endian situation. This patch fixes
the problem by adding handling of such case.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_internals.c
+++ b/target/riscv/vector_internals.c
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
     if (tot - cnt == 0) {
         return ;
     }
+
+    if (HOST_BIG_ENDIAN) {
+        /*
+         * Deal the situation when the elements are insdie
+         * only one uint64 block including setting the
+         * masked-off element.
+         */
+        if (((tot - 1) ^ cnt) < 8) {
+            memset(base + H1(tot - 1), -1, tot - cnt);
+            return;
+        }
+        /*
+         * Otherwise, at least cross two uint64_t blocks.
+         * Set first unaligned block.
+         */
+        if (cnt % 8 != 0) {
+            uint32_t j = ROUND_UP(cnt, 8);
+            memset(base + H1(j - 1), -1, j - cnt);
+            cnt = j;
+        }
+        /* Set other 64bit aligend blocks */
+    }
     memset(base + cnt, -1, tot - cnt);
 }
 
-- 
2.45.1

From: Yangyu Chen <cyy@cyyself.name>

This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Vector cryptography extensions */
     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heterogeneous cpu architectures. As we add decoder in
   RISCVCPU, each cpu can have their own decoder, and the decoders can be
   different due to cpu's features.
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
   can be added to the dynamic_decoder when building up the decoder. Therefore,
   there is no need to run the guard_func when decoding each instruction. It can
   improve the decoding efficiency
3. For vendor or dynamic cpus, it allows them to customize their own decoder
   functions to improve decoding efficiency, especially when vendor-defined
   instruction sets increase. Because of dynamic building up, it can skip the other
   decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
   overhead for users that don't need this particular vendor decoder.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 +
 target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
 target/riscv/cpu.c         |  1 +
 target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
 target/riscv/translate.c   | 31 +++++++++++++++----------------
 5 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
     uint32_t pmu_avail_ctrs;
     /* Mapping of events to counters */
     GHashTable *pmu_event_ctr_map;
+    const GPtrArray *decoders;
 };
 
 /**
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 
+struct DisasContext;
+struct RISCVCPUConfig;
+typedef struct RISCVDecoder {
+    bool (*guard_func)(const struct RISCVCPUConfig *);
+    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+} RISCVDecoder;
+
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+
+extern const size_t decoder_table_size;
+
+extern const RISCVDecoder decoder_table[];
+
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
+
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
             error_propagate(errp, local_err);
             return;
         }
+        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
     } else if (kvm_enabled()) {
         riscv_kvm_cpu_finalize_features(cpu, &local_err);
         if (local_err != NULL) {
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
     }
 }
 
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
+{
+    GPtrArray *dynamic_decoders;
+    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
+    for (size_t i = 0; i < decoder_table_size; ++i) {
+        if (decoder_table[i].guard_func &&
+            decoder_table[i].guard_func(&cpu->cfg)) {
+            g_ptr_array_add(dynamic_decoders,
+                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
+        }
+    }
+
+    cpu->decoders = dynamic_decoders;
+}
+
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
 {
     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-info.c.inc"
 #undef  HELPER_H
 
+#include "tcg/tcg-cpu.h"
+
 /* global register indices */
 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* FRM is known to contain a valid value. */
     bool frm_valid;
     bool insn_start_updated;
+    const GPtrArray *decoders;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
     return (first_word & 3) == 3 ? 4 : 2;
 }
 
+const RISCVDecoder decoder_table[] = {
+    { always_true_p, decode_insn32 },
+    { has_xthead_p, decode_xthead},
+    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
+};
+
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
+
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
-    /*
-     * A table with predicate (i.e., guard) functions and decoder functions
-     * that are tested in-order until a decoder matches onto the opcode.
-     */
-    static const struct {
-        bool (*guard_func)(const RISCVCPUConfig *);
-        bool (*decode_func)(DisasContext *, uint32_t);
-    } decoders[] = {
-        { always_true_p,  decode_insn32 },
-        { has_xthead_p, decode_xthead },
-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
-    };
-
     ctx->virt_inst_excp = false;
     ctx->cur_insn_len = insn_len(opcode);
     /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                              ctx->base.pc_next + 2));
         ctx->opcode = opcode32;
 
-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
-                decoders[i].decode_func(ctx, opcode32)) {
+        for (guint i = 0; i < ctx->decoders->len; ++i) {
+            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
+            if (func(ctx, opcode32)) {
                 return;
             }
         }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
+    ctx->decoders = cpu->decoders;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.45.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc

An important property of this patch is, that the th.sxstatus MAEE field
is not set (indicating that XTheadMae is not available).
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
in PTEs that are marked as reserved. QEMU maintainers prefer to not
implement XTheadMae, so we need give kernels a mechanism to identify
if XTheadMae is available in a system or not. And this patch introduces
this mechanism in QEMU in a way that's compatible with real HW
(i.e., probing the th.sxstatus.MAEE bit).

Further context can be found on the list:
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html

Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS              |  1 +
 target/riscv/cpu.h       |  3 ++
 target/riscv/cpu.c       |  1 +
 target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |  1 +
 5 files changed, 85 insertions(+)
 create mode 100644 target/riscv/th_csr.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/insn_trans/trans_xthead.c.inc
 F: target/riscv/xthead*.decode
+F: target/riscv/th_*
 F: disas/riscv-xthead*
 
 RISC-V XVentanaCondOps extension
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
+/* Implemented in th_csr.c */
+void th_register_custom_csrs(RISCVCPU *cpu);
+
 #endif /* RISCV_CPU_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+    th_register_custom_csrs(cpu);
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/th_csr.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * T-Head-specific CSRs.
+ *
+ * Copyright (c) 2024 VRULL GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpu_vendorid.h"
+
+#define CSR_TH_SXSTATUS 0x5c0
+
+/* TH_SXSTATUS bits */
+#define TH_SXSTATUS_UCME        BIT(16)
+#define TH_SXSTATUS_MAEE        BIT(21)
+#define TH_SXSTATUS_THEADISAEE  BIT(22)
+
+typedef struct {
+    int csrno;
+    int (*insertion_test)(RISCVCPU *cpu);
+    riscv_csr_operations csr_ops;
+} riscv_csr;
+
+static RISCVException smode(CPURISCVState *env, int csrno)
+{
+    if (riscv_has_ext(env, RVS)) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
+
+static int test_thead_mvendorid(RISCVCPU *cpu)
+{
+    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
+        return -1;
+    }
+
+    return 0;
+}
+
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
+                                       target_ulong *val)
+{
+    /* We don't set MAEE here, because QEMU does not implement MAEE. */
+    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
+    return RISCV_EXCP_NONE;
+}
+
+static riscv_csr th_csr_list[] = {
+    {
+        .csrno = CSR_TH_SXSTATUS,
+        .insertion_test = test_thead_mvendorid,
+        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
+    }
+};
+
+void th_register_custom_csrs(RISCVCPU *cpu)
+{
+    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
+        int csrno = th_csr_list[i].csrno;
+        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
+        if (!th_csr_list[i].insertion_test(cpu)) {
+            riscv_set_csr_ops(csrno, csr_ops);
+        }
+    }
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
   'monitor.c',
   'machine.c',
   'pmu.c',
+  'th_csr.c',
   'time_helper.c',
   'riscv-qmp-cmds.c',
 ))
-- 
2.45.1

From: Max Chou <max.chou@sifive.com>

According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of

* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

From: Max Chou <max.chou@sifive.com>

The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.

The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
 1 file changed, 5 insertions(+)

From: Max Chou <max.chou@sifive.com>

If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_ds(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dd(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_widen_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

raise_mmu_exception(), as is today, is prioritizing guest page faults by
checking first if virt_enabled && !first_stage, and then considering the
regular inst/load/store faults.

There's no mention in the spec about guest page fault being a higher
priority that PMP faults. In fact, privileged spec section 3.7.1 says:

"Attempting to fetch an instruction from a PMP region that does not have
execute permissions raises an instruction access-fault exception.
Attempting to execute a load or load-reserved instruction which accesses
a physical address within a PMP region without read permissions raises a
load access-fault exception. Attempting to execute a store,
store-conditional, or AMO instruction which accesses a physical address
within a PMP region without write permissions raises a store
access-fault exception."

So, in fact, we're doing it wrong - PMP faults should always be thrown,
regardless of also being a first or second stage fault.

The way riscv_cpu_tlb_fill() and get_physical_address() work is
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
reflected in the 'pmp_violation' flag. What we need is to change
raise_mmu_exception() to prioritize it.

Reported-by: Joseph Chan <jchan@ventanamicro.com>
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 
     switch (access_type) {
     case MMU_INST_FETCH:
-        if (env->virt_enabled && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
+        } else if (env->virt_enabled && !first_stage) {
             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
         }
         break;
     case MMU_DATA_LOAD:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
         }
         break;
     case MMU_DATA_STORE:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-                RISCV_EXCP_STORE_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
         }
         break;
     default:
-- 
2.45.1

From: Alexei Filippov <alexei.filippov@syntacore.com>

Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation but
failed pmp check.

In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
page-fault is taken into M-mode, mtval2 is written with either zero or guest
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*

Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                               __func__, pa, ret, prot_pmp, tlb_size);
 
                 prot &= prot_pmp;
-            }
-
-            if (ret != TRANSLATE_SUCCESS) {
+            } else {
                 /*
                  * Guest physical address translation failed, this is a HS
                  * level exception
                  */
                 first_stage_error = false;
-                env->guest_phys_fault_addr = (im_address |
-                                              (address &
-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
+                if (ret != TRANSLATE_PMP_FAIL) {
+                    env->guest_phys_fault_addr = (im_address |
+                                                  (address &
+                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
+                }
             }
         }
     } else {
-- 
2.45.1

From: Rob Bradford <rbradford@rivosinc.com>

This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.

Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c         | 2 +-
 target/riscv/tcg/tcg-cpu.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
     MISA_EXT_INFO(RVV, "v", "Vector operations"),
     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
+    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
 };
 
 static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
+    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
         isa_ext_update_enabled(cpu, prop->offset, true);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

When running the instruction

```
    cbo.flush 0(x0)
```

QEMU would segfault.

The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.

In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing pointer mask
calculations on the address specified in rs1.

The pointer masking specificiation specifically states:

"""
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
"""

So this is the correct behaviour and we previously have been incorrectly
not masking the address.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -XXX,XX +XXX,XX @@
 static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_inval(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
 {
     REQUIRE_ZICBOZ(ctx);
-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_zero(tcg_env, src);
     return true;
 }
-- 
2.45.1

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
groups.

However, if the largest hart number among groups is a power of 2, QEMU
will pass an inaccurate hart-index-bit setting to Linux. For example, when
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
to represent 4 harts, but we passes 3 to Linux. The code needs to be
updated to ensure accurate hart-index-bit settings.

Additionally, a Linux patch[1] is necessary to correctly recover the hart
index when the guest OS has only 1 hart, where the hart-index-bit is 0.

[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
         }
     }
 
-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+
+    if (max_hart_per_socket > 1) {
+        max_hart_per_socket--;
+        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+    } else {
+        hart_bits = 0;
+    }
+
     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
                             &hart_bits, true, NULL);
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.

Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.

While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
clarity about what the variable represents. 'bitsize' is also used in
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
gdb_feature_builder_append_reg().

Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
-    int reg_width = cpu->cfg.vlenb;
+    int bitsize = cpu->cfg.vlenb << 3;
     GDBFeatureBuilder builder;
     int i;
 
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
+        int count = bitsize / vec_lanes[i].size;
         gdb_feature_builder_append_tag(
             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
     /* Define vector registers */
     for (i = 0; i < 32; i++) {
         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
-                                       reg_width, i, "riscv_vector", "vector");
+                                       bitsize, i, "riscv_vector", "vector");
     }
 
     gdb_feature_builder_end(&builder);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.

Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Fixes: ea10325917 ("RISC-V Disassembler")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x0383: return "mibound";
     case 0x0384: return "mdbase";
     case 0x0385: return "mdbound";
-    case 0x03a0: return "pmpcfg3";
+    case 0x03a0: return "pmpcfg0";
+    case 0x03a1: return "pmpcfg1";
+    case 0x03a2: return "pmpcfg2";
+    case 0x03a3: return "pmpcfg3";
+    case 0x03a4: return "pmpcfg4";
+    case 0x03a5: return "pmpcfg5";
+    case 0x03a6: return "pmpcfg6";
+    case 0x03a7: return "pmpcfg7";
+    case 0x03a8: return "pmpcfg8";
+    case 0x03a9: return "pmpcfg9";
+    case 0x03aa: return "pmpcfg10";
+    case 0x03ab: return "pmpcfg11";
+    case 0x03ac: return "pmpcfg12";
+    case 0x03ad: return "pmpcfg13";
+    case 0x03ae: return "pmpcfg14";
+    case 0x03af: return "pmpcfg15";
     case 0x03b0: return "pmpaddr0";
     case 0x03b1: return "pmpaddr1";
     case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x03bd: return "pmpaddr13";
     case 0x03be: return "pmpaddr14";
     case 0x03bf: return "pmpaddr15";
+    case 0x03c0: return "pmpaddr16";
+    case 0x03c1: return "pmpaddr17";
+    case 0x03c2: return "pmpaddr18";
+    case 0x03c3: return "pmpaddr19";
+    case 0x03c4: return "pmpaddr20";
+    case 0x03c5: return "pmpaddr21";
+    case 0x03c6: return "pmpaddr22";
+    case 0x03c7: return "pmpaddr23";
+    case 0x03c8: return "pmpaddr24";
+    case 0x03c9: return "pmpaddr25";
+    case 0x03ca: return "pmpaddr26";
+    case 0x03cb: return "pmpaddr27";
+    case 0x03cc: return "pmpaddr28";
+    case 0x03cd: return "pmpaddr29";
+    case 0x03ce: return "pmpaddr30";
+    case 0x03cf: return "pmpaddr31";
+    case 0x03d0: return "pmpaddr32";
+    case 0x03d1: return "pmpaddr33";
+    case 0x03d2: return "pmpaddr34";
+    case 0x03d3: return "pmpaddr35";
+    case 0x03d4: return "pmpaddr36";
+    case 0x03d5: return "pmpaddr37";
+    case 0x03d6: return "pmpaddr38";
+    case 0x03d7: return "pmpaddr39";
+    case 0x03d8: return "pmpaddr40";
+    case 0x03d9: return "pmpaddr41";
+    case 0x03da: return "pmpaddr42";
+    case 0x03db: return "pmpaddr43";
+    case 0x03dc: return "pmpaddr44";
+    case 0x03dd: return "pmpaddr45";
+    case 0x03de: return "pmpaddr46";
+    case 0x03df: return "pmpaddr47";
+    case 0x03e0: return "pmpaddr48";
+    case 0x03e1: return "pmpaddr49";
+    case 0x03e2: return "pmpaddr50";
+    case 0x03e3: return "pmpaddr51";
+    case 0x03e4: return "pmpaddr52";
+    case 0x03e5: return "pmpaddr53";
+    case 0x03e6: return "pmpaddr54";
+    case 0x03e7: return "pmpaddr55";
+    case 0x03e8: return "pmpaddr56";
+    case 0x03e9: return "pmpaddr57";
+    case 0x03ea: return "pmpaddr58";
+    case 0x03eb: return "pmpaddr59";
+    case 0x03ec: return "pmpaddr60";
+    case 0x03ed: return "pmpaddr61";
+    case 0x03ee: return "pmpaddr62";
+    case 0x03ef: return "pmpaddr63";
     case 0x0780: return "mtohost";
     case 0x0781: return "mfromhost";
     case 0x0782: return "mreset";
-- 
2.45.1

From: Yu-Ming Chang <yumin686@andestech.com>

Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
holding a zero value other than x0, the instruction will still attempt to write
the unmodified value back to the CSR and will cause any attendant side effects.

So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
a register holding a zero value, an illegal instruction exception should be
raised.

Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       |  4 ++++
 target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
 target/riscv/op_helper.c |  6 ++---
 3 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
 void riscv_cpu_update_mask(CPURISCVState *env);
 bool riscv_cpu_is_32bit(RISCVCPU *cpu);
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                          target_ulong *ret_value);
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask);
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                           target_ulong new_value,
                                           target_ulong write_mask);
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value);
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 
 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                int csrno,
-                                               bool write_mask)
+                                               bool write)
 {
     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
     bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
     }
 
     /* read / write check */
-    if (write_mask && read_only) {
+    if (write && read_only) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value)
+{
+    RISCVException ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
+}
+
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask)
 {
-    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
+    RISCVException ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value)
+{
+    RISCVException ret;
+
+    ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    if (csr_ops[csrno].read128) {
+        return riscv_csrrw_do128(env, csrno, ret_value,
+                                 int128_zero(), int128_zero());
+    }
+
+    /*
+     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
+     * at all defined.
+     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
+     * significant), for those, this fallback is correctly handling the
+     * accesses
+     */
+    target_ulong old_value;
+    ret = riscv_csrrw_do64(env, csrno, &old_value,
+                           (target_ulong)0,
+                           (target_ulong)0);
+    if (ret == RISCV_EXCP_NONE && ret_value) {
+        *ret_value = int128_make64(old_value);
+    }
+    return ret;
+}
+
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask)
 {
     RISCVException ret;
 
-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
+    ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
     }
 
     target_ulong val = 0;
-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
+    RISCVException ret = riscv_csrr(env, csr, &val);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
 target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
 {
     Int128 rv = int128_zero();
-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
-                                          int128_zero(),
-                                          int128_zero());
+    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
-- 
2.45.1