[PULL 00/26] riscv-to-apply queue
[PULL 0/2] riscv-to-apply queue
1
From: Alistair Francis <alistair.francis@wdc.com>
1
From: Alistair Francis <alistair.francis@wdc.com>
2
2
3
The following changes since commit ca61fa4b803e5d0abaf6f1ceb690f23bb78a4def:
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The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:
4
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5
Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211006' into staging (2021-10-06 12:11:14 -0700)
5
Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)
6
6
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are available in the Git repository at:
7
are available in the Git repository at:
8
8
9
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211007
9
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122
10
10
11
for you to fetch changes up to 9ae6ecd848dcd1b32003526ab65a0d4c644dfb07:
11
for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:
12
12
13
hw/riscv: shakti_c: Mark as not user creatable (2021-10-07 08:41:33 +1000)
13
hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)
14
14
15
----------------------------------------------------------------
15
----------------------------------------------------------------
16
Third RISC-V PR for QEMU 6.2
16
Seventh RISC-V PR for QEMU 6.2
17
17
18
- Add Zb[abcs] instruction support
18
- Deprecate IF_NONE for SiFive OTP
19
- Remove RVB support
19
- Don't reset SiFive OTP content
20
- Bug fix of setting mstatus_hs.[SD|FS] bits
21
- Mark some UART devices as 'input'
22
- QOMify PolarFire MMUART
23
- Fixes for sifive PDMA
24
- Mark shakti_c as not user creatable
25
20
26
----------------------------------------------------------------
21
----------------------------------------------------------------
27
Alistair Francis (1):
22
Philippe Mathieu-Daudé (1):
28
hw/riscv: shakti_c: Mark as not user creatable
23
hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
29
24
30
Bin Meng (5):
25
Thomas Huth (1):
31
hw/char: ibex_uart: Register device in 'input' category
26
hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
32
hw/char: shakti_uart: Register device in 'input' category
33
hw/char: sifive_uart: Register device in 'input' category
34
hw/dma: sifive_pdma: Fix Control.claim bit detection
35
hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed
36
27
37
Frank Chang (1):
28
docs/about/deprecated.rst | 6 ++++++
38
target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()
29
hw/misc/sifive_u_otp.c | 22 +++++++++++++---------
30
2 files changed, 19 insertions(+), 9 deletions(-)
39
31
40
Philipp Tomsich (16):
41
target/riscv: Introduce temporary in gen_add_uw()
42
target/riscv: fix clzw implementation to operate on arg1
43
target/riscv: clwz must ignore high bits (use shift-left & changed logic)
44
target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
45
target/riscv: Reassign instructions to the Zba-extension
46
target/riscv: Remove the W-form instructions from Zbs
47
target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
48
target/riscv: Reassign instructions to the Zbs-extension
49
target/riscv: Add instructions of the Zbc-extension
50
target/riscv: Reassign instructions to the Zbb-extension
51
target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
52
target/riscv: Add a REQUIRE_32BIT macro
53
target/riscv: Add rev8 instruction, removing grev/grevi
54
target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
55
target/riscv: Remove RVB (replaced by Zb[abcs])
56
disas/riscv: Add Zb[abcs] instructions
57
58
Philippe Mathieu-Daudé (3):
59
hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition
60
hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container
61
hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART
62
63
include/hw/char/mchp_pfsoc_mmuart.h | 17 +-
64
target/riscv/cpu.h | 11 +-
65
target/riscv/helper.h | 6 +-
66
target/riscv/insn32.decode | 115 ++++-----
67
disas/riscv.c | 157 +++++++++++-
68
hw/char/ibex_uart.c | 1 +
69
hw/char/mchp_pfsoc_mmuart.c | 116 +++++++--
70
hw/char/shakti_uart.c | 1 +
71
hw/char/sifive_uart.c | 1 +
72
hw/dma/sifive_pdma.c | 13 +-
73
hw/riscv/shakti_c.c | 7 +
74
target/riscv/bitmanip_helper.c | 65 +----
75
target/riscv/cpu.c | 30 +--
76
target/riscv/translate.c | 36 ++-
77
target/riscv/insn_trans/trans_rvb.c.inc | 419 ++++++++++----------------------
78
15 files changed, 516 insertions(+), 479 deletions(-)
79
diff view generated by jsdifflib
[PULL 01/26] target/riscv: Introduce temporary in gen_add_uw()
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
Following the recent changes in translate.c, gen_add_uw() causes
4
failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these
5
regressions by introducing a temporary.
6
7
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20210911140016.834071-2-philipp.tomsich@vrull.eu
12
Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*")
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++--
16
1 file changed, 4 insertions(+), 2 deletions(-)
17
18
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/insn_trans/trans_rvb.c.inc
21
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
22
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD_UW(3)
23
24
static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
25
{
26
- tcg_gen_ext32u_tl(arg1, arg1);
27
- tcg_gen_add_tl(ret, arg1, arg2);
28
+ TCGv t = tcg_temp_new();
29
+ tcg_gen_ext32u_tl(t, arg1);
30
+ tcg_gen_add_tl(ret, t, arg2);
31
+ tcg_temp_free(t);
32
}
33
34
static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
35
--
36
2.31.1
37
38
diff view generated by jsdifflib
[PULL 02/26] target/riscv: fix clzw implementation to operate on arg1
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
The refactored gen_clzw() uses ret as its argument, instead of arg1.
4
Fix it.
5
6
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20210911140016.834071-3-philipp.tomsich@vrull.eu
11
Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary")
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/insn_trans/trans_rvb.c.inc | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/insn_trans/trans_rvb.c.inc
20
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
21
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(3)
22
23
static void gen_clzw(TCGv ret, TCGv arg1)
24
{
25
- tcg_gen_clzi_tl(ret, ret, 64);
26
+ tcg_gen_clzi_tl(ret, arg1, 64);
27
tcg_gen_subi_tl(ret, ret, 32);
28
}
29
30
--
31
2.31.1
32
33
diff view generated by jsdifflib
[PULL 03/26] target/riscv: clwz must ignore high bits (use shift-left & changed logic)
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
Assume clzw being executed on a register that is not sign-extended, such
4
as for the following sequence that uses (1ULL << 63) | 392 as the operand
5
to clzw:
6
    bseti    a2, zero, 63
7
    addi    a2, a2, 392
8
    clzw a3, a2
9
The correct result of clzw would be 23, but the current implementation
10
returns -32 (as it performs a 64bit clz, which results in 0 leading zero
11
bits, and then subtracts 32).
12
13
Fix this by changing the implementation to:
14
1. shift the original register up by 32
15
2. performs a target-length (64bit) clz
16
3. return 32 if no bits are set
17
18
Marking this instruction as 'w-form' (i.e., setting ctx->w) would not
19
correctly model the behaviour, as the instruction should not perform
20
a zero-extensions on the input (after all, it is not a .uw instruction)
21
and the result is always in the range 0..32 (so neither a sign-extension
22
nor a zero-extension on the result will ever be needed). Consequently,
23
we do not set ctx->w and mark the instruction as EXT_NONE.
24
25
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
26
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
27
Message-id: 20210911140016.834071-4-philipp.tomsich@vrull.eu
28
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
29
---
30
target/riscv/insn_trans/trans_rvb.c.inc | 8 +++++---
31
1 file changed, 5 insertions(+), 3 deletions(-)
32
33
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/riscv/insn_trans/trans_rvb.c.inc
36
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
37
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(3)
38
39
static void gen_clzw(TCGv ret, TCGv arg1)
40
{
41
- tcg_gen_clzi_tl(ret, arg1, 64);
42
- tcg_gen_subi_tl(ret, ret, 32);
43
+ TCGv t = tcg_temp_new();
44
+ tcg_gen_shli_tl(t, arg1, 32);
45
+ tcg_gen_clzi_tl(ret, t, 32);
46
+ tcg_temp_free(t);
47
}
48
49
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
50
{
51
REQUIRE_64BIT(ctx);
52
REQUIRE_EXT(ctx, RVB);
53
- return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
54
+ return gen_unary(ctx, a, EXT_NONE, gen_clzw);
55
}
56
57
static void gen_ctzw(TCGv ret, TCGv arg1)
58
--
59
2.31.1
60
61
diff view generated by jsdifflib
[PULL 04/26] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
The bitmanipulation ISA extensions will be ratified as individual
4
small extension packages instead of a large B-extension. The first
5
new instructions through the door (these have completed public review)
6
are Zb[abcs].
7
8
This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
9
these in target/riscv/cpu.[ch].
10
11
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
15
Message-id: 20210911140016.834071-5-philipp.tomsich@vrull.eu
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
18
target/riscv/cpu.h | 4 ++++
19
target/riscv/cpu.c | 4 ++++
20
2 files changed, 8 insertions(+)
21
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu.h
25
+++ b/target/riscv/cpu.h
26
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
27
bool ext_u;
28
bool ext_h;
29
bool ext_v;
30
+ bool ext_zba;
31
+ bool ext_zbb;
32
+ bool ext_zbc;
33
+ bool ext_zbs;
34
bool ext_counters;
35
bool ext_ifencei;
36
bool ext_icsr;
37
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/riscv/cpu.c
40
+++ b/target/riscv/cpu.c
41
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
42
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
43
/* This is experimental so mark with 'x-' */
44
DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
45
+ DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
46
+ DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
47
+ DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
48
+ DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
49
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
50
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
51
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
52
--
53
2.31.1
54
55
diff view generated by jsdifflib
[PULL 05/26] target/riscv: Reassign instructions to the Zba-extension
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
The following instructions are part of Zba:
4
- add.uw (RV64 only)
5
- sh[123]add (RV32 and RV64)
6
- sh[123]add.uw (RV64-only)
7
- slli.uw (RV64-only)
8
9
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Acked-by: Bin Meng <bmeng.cn@gmail.com>
13
Message-id: 20210911140016.834071-6-philipp.tomsich@vrull.eu
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
16
target/riscv/insn32.decode | 20 ++++++++++++--------
17
target/riscv/insn_trans/trans_rvb.c.inc | 16 +++++++++++-----
18
2 files changed, 23 insertions(+), 13 deletions(-)
19
20
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/insn32.decode
23
+++ b/target/riscv/insn32.decode
24
@@ -XXX,XX +XXX,XX @@ vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
25
vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
26
vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
27
28
+# *** RV32 Zba Standard Extension ***
29
+sh1add 0010000 .......... 010 ..... 0110011 @r
30
+sh2add 0010000 .......... 100 ..... 0110011 @r
31
+sh3add 0010000 .......... 110 ..... 0110011 @r
32
+
33
+# *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
34
+add_uw 0000100 .......... 000 ..... 0111011 @r
35
+sh1add_uw 0010000 .......... 010 ..... 0111011 @r
36
+sh2add_uw 0010000 .......... 100 ..... 0111011 @r
37
+sh3add_uw 0010000 .......... 110 ..... 0111011 @r
38
+slli_uw 00001 ............ 001 ..... 0011011 @sh
39
+
40
# *** RV32B Standard Extension ***
41
clz 011000 000000 ..... 001 ..... 0010011 @r2
42
ctz 011000 000001 ..... 001 ..... 0010011 @r2
43
@@ -XXX,XX +XXX,XX @@ ror 0110000 .......... 101 ..... 0110011 @r
44
rol 0110000 .......... 001 ..... 0110011 @r
45
grev 0110100 .......... 101 ..... 0110011 @r
46
gorc 0010100 .......... 101 ..... 0110011 @r
47
-sh1add 0010000 .......... 010 ..... 0110011 @r
48
-sh2add 0010000 .......... 100 ..... 0110011 @r
49
-sh3add 0010000 .......... 110 ..... 0110011 @r
50
51
bseti 00101. ........... 001 ..... 0010011 @sh
52
bclri 01001. ........... 001 ..... 0010011 @sh
53
@@ -XXX,XX +XXX,XX @@ rorw 0110000 .......... 101 ..... 0111011 @r
54
rolw 0110000 .......... 001 ..... 0111011 @r
55
grevw 0110100 .......... 101 ..... 0111011 @r
56
gorcw 0010100 .......... 101 ..... 0111011 @r
57
-sh1add_uw 0010000 .......... 010 ..... 0111011 @r
58
-sh2add_uw 0010000 .......... 100 ..... 0111011 @r
59
-sh3add_uw 0010000 .......... 110 ..... 0111011 @r
60
-add_uw 0000100 .......... 000 ..... 0111011 @r
61
62
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
63
bclriw 0100100 .......... 001 ..... 0011011 @sh5
64
@@ -XXX,XX +XXX,XX @@ roriw 0110000 .......... 101 ..... 0011011 @sh5
65
greviw 0110100 .......... 101 ..... 0011011 @sh5
66
gorciw 0010100 .......... 101 ..... 0011011 @sh5
67
68
-slli_uw 00001. ........... 001 ..... 0011011 @sh
69
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
70
index XXXXXXX..XXXXXXX 100644
71
--- a/target/riscv/insn_trans/trans_rvb.c.inc
72
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
73
@@ -XXX,XX +XXX,XX @@
74
/*
75
- * RISC-V translation routines for the RVB Standard Extension.
76
+ * RISC-V translation routines for the RVB draft and Zba Standard Extension.
77
*
78
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
79
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
80
+ * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
81
*
82
* This program is free software; you can redistribute it and/or modify it
83
* under the terms and conditions of the GNU General Public License,
84
@@ -XXX,XX +XXX,XX @@
85
* this program. If not, see <http://www.gnu.org/licenses/>.
86
*/
87
88
+#define REQUIRE_ZBA(ctx) do { \
89
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) { \
90
+ return false; \
91
+ } \
92
+} while (0)
93
94
static void gen_clz(TCGv ret, TCGv arg1)
95
{
96
@@ -XXX,XX +XXX,XX @@ GEN_SHADD(3)
97
#define GEN_TRANS_SHADD(SHAMT) \
98
static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
99
{ \
100
- REQUIRE_EXT(ctx, RVB); \
101
+ REQUIRE_ZBA(ctx); \
102
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add); \
103
}
104
105
@@ -XXX,XX +XXX,XX @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
106
arg_sh##SHAMT##add_uw *a) \
107
{ \
108
REQUIRE_64BIT(ctx); \
109
- REQUIRE_EXT(ctx, RVB); \
110
+ REQUIRE_ZBA(ctx); \
111
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw); \
112
}
113
114
@@ -XXX,XX +XXX,XX @@ static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
115
static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
116
{
117
REQUIRE_64BIT(ctx);
118
- REQUIRE_EXT(ctx, RVB);
119
+ REQUIRE_ZBA(ctx);
120
return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
121
}
122
123
@@ -XXX,XX +XXX,XX @@ static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
124
static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
125
{
126
REQUIRE_64BIT(ctx);
127
- REQUIRE_EXT(ctx, RVB);
128
+ REQUIRE_ZBA(ctx);
129
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
130
}
131
--
132
2.31.1
133
134
diff view generated by jsdifflib
[PULL 06/26] target/riscv: Remove the W-form instructions from Zbs
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
Zbs 1.0.0 (just as the 0.93 draft-B before) does not provide for W-form
4
instructions for Zbs (single-bit instructions). Remove them.
5
6
Note that these instructions had already been removed for the 0.93
7
version of the draft-B extention and have not been present in the
8
binutils patches circulating in January 2021.
9
10
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Acked-by: Bin Meng <bmeng.cn@gmail.com>
14
Message-id: 20210911140016.834071-7-philipp.tomsich@vrull.eu
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
17
target/riscv/insn32.decode | 7 ----
18
target/riscv/insn_trans/trans_rvb.c.inc | 56 -------------------------
19
2 files changed, 63 deletions(-)
20
21
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/insn32.decode
24
+++ b/target/riscv/insn32.decode
25
@@ -XXX,XX +XXX,XX @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
26
27
packw 0000100 .......... 100 ..... 0111011 @r
28
packuw 0100100 .......... 100 ..... 0111011 @r
29
-bsetw 0010100 .......... 001 ..... 0111011 @r
30
-bclrw 0100100 .......... 001 ..... 0111011 @r
31
-binvw 0110100 .......... 001 ..... 0111011 @r
32
-bextw 0100100 .......... 101 ..... 0111011 @r
33
slow 0010000 .......... 001 ..... 0111011 @r
34
srow 0010000 .......... 101 ..... 0111011 @r
35
rorw 0110000 .......... 101 ..... 0111011 @r
36
@@ -XXX,XX +XXX,XX @@ rolw 0110000 .......... 001 ..... 0111011 @r
37
grevw 0110100 .......... 101 ..... 0111011 @r
38
gorcw 0010100 .......... 101 ..... 0111011 @r
39
40
-bsetiw 0010100 .......... 001 ..... 0011011 @sh5
41
-bclriw 0100100 .......... 001 ..... 0011011 @sh5
42
-binviw 0110100 .......... 001 ..... 0011011 @sh5
43
sloiw 0010000 .......... 001 ..... 0011011 @sh5
44
sroiw 0010000 .......... 101 ..... 0011011 @sh5
45
roriw 0110000 .......... 101 ..... 0011011 @sh5
46
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/riscv/insn_trans/trans_rvb.c.inc
49
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
50
@@ -XXX,XX +XXX,XX @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
51
return gen_arith(ctx, a, EXT_NONE, gen_packuw);
52
}
53
54
-static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
55
-{
56
- REQUIRE_64BIT(ctx);
57
- REQUIRE_EXT(ctx, RVB);
58
- ctx->w = true;
59
- return gen_shift(ctx, a, EXT_NONE, gen_bset);
60
-}
61
-
62
-static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
63
-{
64
- REQUIRE_64BIT(ctx);
65
- REQUIRE_EXT(ctx, RVB);
66
- ctx->w = true;
67
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
68
-}
69
-
70
-static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
71
-{
72
- REQUIRE_64BIT(ctx);
73
- REQUIRE_EXT(ctx, RVB);
74
- ctx->w = true;
75
- return gen_shift(ctx, a, EXT_NONE, gen_bclr);
76
-}
77
-
78
-static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
79
-{
80
- REQUIRE_64BIT(ctx);
81
- REQUIRE_EXT(ctx, RVB);
82
- ctx->w = true;
83
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
84
-}
85
-
86
-static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
87
-{
88
- REQUIRE_64BIT(ctx);
89
- REQUIRE_EXT(ctx, RVB);
90
- ctx->w = true;
91
- return gen_shift(ctx, a, EXT_NONE, gen_binv);
92
-}
93
-
94
-static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
95
-{
96
- REQUIRE_64BIT(ctx);
97
- REQUIRE_EXT(ctx, RVB);
98
- ctx->w = true;
99
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
100
-}
101
-
102
-static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
103
-{
104
- REQUIRE_64BIT(ctx);
105
- REQUIRE_EXT(ctx, RVB);
106
- ctx->w = true;
107
- return gen_shift(ctx, a, EXT_NONE, gen_bext);
108
-}
109
-
110
static bool trans_slow(DisasContext *ctx, arg_slow *a)
111
{
112
REQUIRE_64BIT(ctx);
113
--
114
2.31.1
115
116
diff view generated by jsdifflib
[PULL 07/26] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
The Zb[abcs] ratification package does not include the proposed
4
shift-one instructions. There currently is no clear plan to whether
5
these (or variants of them) will be ratified as Zbo (or a different
6
extension) or what the timeframe for such a decision could be.
7
8
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Acked-by: Bin Meng <bmeng.cn@gmail.com>
12
Message-id: 20210911140016.834071-8-philipp.tomsich@vrull.eu
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
target/riscv/insn32.decode | 8 ---
16
target/riscv/insn_trans/trans_rvb.c.inc | 70 -------------------------
17
2 files changed, 78 deletions(-)
18
19
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/insn32.decode
22
+++ b/target/riscv/insn32.decode
23
@@ -XXX,XX +XXX,XX @@ bset 0010100 .......... 001 ..... 0110011 @r
24
bclr 0100100 .......... 001 ..... 0110011 @r
25
binv 0110100 .......... 001 ..... 0110011 @r
26
bext 0100100 .......... 101 ..... 0110011 @r
27
-slo 0010000 .......... 001 ..... 0110011 @r
28
-sro 0010000 .......... 101 ..... 0110011 @r
29
ror 0110000 .......... 101 ..... 0110011 @r
30
rol 0110000 .......... 001 ..... 0110011 @r
31
grev 0110100 .......... 101 ..... 0110011 @r
32
@@ -XXX,XX +XXX,XX @@ bseti 00101. ........... 001 ..... 0010011 @sh
33
bclri 01001. ........... 001 ..... 0010011 @sh
34
binvi 01101. ........... 001 ..... 0010011 @sh
35
bexti 01001. ........... 101 ..... 0010011 @sh
36
-sloi 00100. ........... 001 ..... 0010011 @sh
37
-sroi 00100. ........... 101 ..... 0010011 @sh
38
rori 01100. ........... 101 ..... 0010011 @sh
39
grevi 01101. ........... 101 ..... 0010011 @sh
40
gorci 00101. ........... 101 ..... 0010011 @sh
41
@@ -XXX,XX +XXX,XX @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
42
43
packw 0000100 .......... 100 ..... 0111011 @r
44
packuw 0100100 .......... 100 ..... 0111011 @r
45
-slow 0010000 .......... 001 ..... 0111011 @r
46
-srow 0010000 .......... 101 ..... 0111011 @r
47
rorw 0110000 .......... 101 ..... 0111011 @r
48
rolw 0110000 .......... 001 ..... 0111011 @r
49
grevw 0110100 .......... 101 ..... 0111011 @r
50
gorcw 0010100 .......... 101 ..... 0111011 @r
51
52
-sloiw 0010000 .......... 001 ..... 0011011 @sh5
53
-sroiw 0010000 .......... 101 ..... 0011011 @sh5
54
roriw 0110000 .......... 101 ..... 0011011 @sh5
55
greviw 0110100 .......... 101 ..... 0011011 @sh5
56
gorciw 0010100 .......... 101 ..... 0011011 @sh5
57
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/riscv/insn_trans/trans_rvb.c.inc
60
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
61
@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
62
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
63
}
64
65
-static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
66
-{
67
- tcg_gen_not_tl(ret, arg1);
68
- tcg_gen_shl_tl(ret, ret, arg2);
69
- tcg_gen_not_tl(ret, ret);
70
-}
71
-
72
-static bool trans_slo(DisasContext *ctx, arg_slo *a)
73
-{
74
- REQUIRE_EXT(ctx, RVB);
75
- return gen_shift(ctx, a, EXT_NONE, gen_slo);
76
-}
77
-
78
-static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
79
-{
80
- REQUIRE_EXT(ctx, RVB);
81
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
82
-}
83
-
84
-static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
85
-{
86
- tcg_gen_not_tl(ret, arg1);
87
- tcg_gen_shr_tl(ret, ret, arg2);
88
- tcg_gen_not_tl(ret, ret);
89
-}
90
-
91
-static bool trans_sro(DisasContext *ctx, arg_sro *a)
92
-{
93
- REQUIRE_EXT(ctx, RVB);
94
- return gen_shift(ctx, a, EXT_ZERO, gen_sro);
95
-}
96
-
97
-static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
98
-{
99
- REQUIRE_EXT(ctx, RVB);
100
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
101
-}
102
-
103
static bool trans_ror(DisasContext *ctx, arg_ror *a)
104
{
105
REQUIRE_EXT(ctx, RVB);
106
@@ -XXX,XX +XXX,XX @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
107
return gen_arith(ctx, a, EXT_NONE, gen_packuw);
108
}
109
110
-static bool trans_slow(DisasContext *ctx, arg_slow *a)
111
-{
112
- REQUIRE_64BIT(ctx);
113
- REQUIRE_EXT(ctx, RVB);
114
- ctx->w = true;
115
- return gen_shift(ctx, a, EXT_NONE, gen_slo);
116
-}
117
-
118
-static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
119
-{
120
- REQUIRE_64BIT(ctx);
121
- REQUIRE_EXT(ctx, RVB);
122
- ctx->w = true;
123
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
124
-}
125
-
126
-static bool trans_srow(DisasContext *ctx, arg_srow *a)
127
-{
128
- REQUIRE_64BIT(ctx);
129
- REQUIRE_EXT(ctx, RVB);
130
- ctx->w = true;
131
- return gen_shift(ctx, a, EXT_ZERO, gen_sro);
132
-}
133
-
134
-static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
135
-{
136
- REQUIRE_64BIT(ctx);
137
- REQUIRE_EXT(ctx, RVB);
138
- ctx->w = true;
139
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
140
-}
141
-
142
static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
143
{
144
TCGv_i32 t1 = tcg_temp_new_i32();
145
--
146
2.31.1
147
148
diff view generated by jsdifflib
[PULL 08/26] target/riscv: Reassign instructions to the Zbs-extension
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
The following instructions are part of Zbs:
4
- b{set,clr,ext,inv}
5
- b{set,clr,ext,inv}i
6
7
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Acked-by: Bin Meng <bmeng.cn@gmail.com>
11
Message-id: 20210911140016.834071-9-philipp.tomsich@vrull.eu
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/insn32.decode | 17 +++++++++--------
15
target/riscv/insn_trans/trans_rvb.c.inc | 25 +++++++++++++++----------
16
2 files changed, 24 insertions(+), 18 deletions(-)
17
18
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/insn32.decode
21
+++ b/target/riscv/insn32.decode
22
@@ -XXX,XX +XXX,XX @@ min 0000101 .......... 100 ..... 0110011 @r
23
minu 0000101 .......... 101 ..... 0110011 @r
24
max 0000101 .......... 110 ..... 0110011 @r
25
maxu 0000101 .......... 111 ..... 0110011 @r
26
-bset 0010100 .......... 001 ..... 0110011 @r
27
-bclr 0100100 .......... 001 ..... 0110011 @r
28
-binv 0110100 .......... 001 ..... 0110011 @r
29
-bext 0100100 .......... 101 ..... 0110011 @r
30
ror 0110000 .......... 101 ..... 0110011 @r
31
rol 0110000 .......... 001 ..... 0110011 @r
32
grev 0110100 .......... 101 ..... 0110011 @r
33
gorc 0010100 .......... 101 ..... 0110011 @r
34
35
-bseti 00101. ........... 001 ..... 0010011 @sh
36
-bclri 01001. ........... 001 ..... 0010011 @sh
37
-binvi 01101. ........... 001 ..... 0010011 @sh
38
-bexti 01001. ........... 101 ..... 0010011 @sh
39
rori 01100. ........... 101 ..... 0010011 @sh
40
grevi 01101. ........... 101 ..... 0010011 @sh
41
gorci 00101. ........... 101 ..... 0010011 @sh
42
@@ -XXX,XX +XXX,XX @@ roriw 0110000 .......... 101 ..... 0011011 @sh5
43
greviw 0110100 .......... 101 ..... 0011011 @sh5
44
gorciw 0010100 .......... 101 ..... 0011011 @sh5
45
46
+# *** RV32 Zbs Standard Extension ***
47
+bclr 0100100 .......... 001 ..... 0110011 @r
48
+bclri 01001. ........... 001 ..... 0010011 @sh
49
+bext 0100100 .......... 101 ..... 0110011 @r
50
+bexti 01001. ........... 101 ..... 0010011 @sh
51
+binv 0110100 .......... 001 ..... 0110011 @r
52
+binvi 01101. ........... 001 ..... 0010011 @sh
53
+bset 0010100 .......... 001 ..... 0110011 @r
54
+bseti 00101. ........... 001 ..... 0010011 @sh
55
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/riscv/insn_trans/trans_rvb.c.inc
58
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
59
@@ -XXX,XX +XXX,XX @@
60
/*
61
- * RISC-V translation routines for the RVB draft and Zba Standard Extension.
62
+ * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
63
*
64
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
65
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
66
@@ -XXX,XX +XXX,XX @@
67
} \
68
} while (0)
69
70
+#define REQUIRE_ZBS(ctx) do { \
71
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
72
+ return false; \
73
+ } \
74
+} while (0)
75
+
76
static void gen_clz(TCGv ret, TCGv arg1)
77
{
78
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
79
}
80
-
81
static bool trans_clz(DisasContext *ctx, arg_clz *a)
82
{
83
REQUIRE_EXT(ctx, RVB);
84
@@ -XXX,XX +XXX,XX @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
85
86
static bool trans_bset(DisasContext *ctx, arg_bset *a)
87
{
88
- REQUIRE_EXT(ctx, RVB);
89
+ REQUIRE_ZBS(ctx);
90
return gen_shift(ctx, a, EXT_NONE, gen_bset);
91
}
92
93
static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
94
{
95
- REQUIRE_EXT(ctx, RVB);
96
+ REQUIRE_ZBS(ctx);
97
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
98
}
99
100
@@ -XXX,XX +XXX,XX @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
101
102
static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
103
{
104
- REQUIRE_EXT(ctx, RVB);
105
+ REQUIRE_ZBS(ctx);
106
return gen_shift(ctx, a, EXT_NONE, gen_bclr);
107
}
108
109
static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
110
{
111
- REQUIRE_EXT(ctx, RVB);
112
+ REQUIRE_ZBS(ctx);
113
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
114
}
115
116
@@ -XXX,XX +XXX,XX @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
117
118
static bool trans_binv(DisasContext *ctx, arg_binv *a)
119
{
120
- REQUIRE_EXT(ctx, RVB);
121
+ REQUIRE_ZBS(ctx);
122
return gen_shift(ctx, a, EXT_NONE, gen_binv);
123
}
124
125
static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
126
{
127
- REQUIRE_EXT(ctx, RVB);
128
+ REQUIRE_ZBS(ctx);
129
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
130
}
131
132
@@ -XXX,XX +XXX,XX @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
133
134
static bool trans_bext(DisasContext *ctx, arg_bext *a)
135
{
136
- REQUIRE_EXT(ctx, RVB);
137
+ REQUIRE_ZBS(ctx);
138
return gen_shift(ctx, a, EXT_NONE, gen_bext);
139
}
140
141
static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
142
{
143
- REQUIRE_EXT(ctx, RVB);
144
+ REQUIRE_ZBS(ctx);
145
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
146
}
147
148
--
149
2.31.1
150
151
diff view generated by jsdifflib
[PULL 09/26] target/riscv: Add instructions of the Zbc-extension
[PULL 1/2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
The following instructions are part of Zbc:
3
Configuring a drive with "if=none" is meant for creation of a backend
4
- clmul
4
only, it should not get automatically assigned to a device frontend.
5
- clmulh
5
Use "if=pflash" for the One-Time-Programmable device instead (like
6
- clmulr
6
it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).
7
7
8
Note that these instructions were already defined in the pre-0.93 and
8
Since the old way of configuring the device has already been published
9
the 0.93 draft-B proposals, but had not been omitted in the earlier
9
with the previous QEMU versions, we cannot remove this immediately, but
10
addition of draft-B to QEmu.
10
have to deprecate it and support it for at least two more releases.
11
11
12
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
12
Signed-off-by: Thomas Huth <thuth@redhat.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Markus Armbruster <armbru@redhat.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu
16
Message-id: 20211119102549.217755-1-thuth@redhat.com
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
18
---
18
target/riscv/helper.h | 2 ++
19
docs/about/deprecated.rst | 6 ++++++
19
target/riscv/insn32.decode | 5 ++++
20
hw/misc/sifive_u_otp.c | 9 ++++++++-
20
target/riscv/bitmanip_helper.c | 27 +++++++++++++++++++++
21
2 files changed, 14 insertions(+), 1 deletion(-)
21
target/riscv/insn_trans/trans_rvb.c.inc | 32 ++++++++++++++++++++++++-
22
4 files changed, 65 insertions(+), 1 deletion(-)
23
22
24
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
23
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
25
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/helper.h
25
--- a/docs/about/deprecated.rst
27
+++ b/target/riscv/helper.h
26
+++ b/docs/about/deprecated.rst
28
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
27
@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
29
DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
28
However, short-form booleans are deprecated and full explicit ``arg_name=on``
30
DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
29
form is preferred.
31
DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
30
32
+DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
31
+``-drive if=none`` for the sifive_u OTP device (since 6.2)
33
+DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
32
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
34
33
+
35
/* Special functions */
34
+Using ``-drive if=none`` to configure the OTP device of the sifive_u
36
DEF_HELPER_2(csrr, tl, env, int)
35
+RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
37
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
36
+
37
38
QEMU Machine Protocol (QMP) commands
39
------------------------------------
40
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
38
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
39
--- a/target/riscv/insn32.decode
42
--- a/hw/misc/sifive_u_otp.c
40
+++ b/target/riscv/insn32.decode
43
+++ b/hw/misc/sifive_u_otp.c
41
@@ -XXX,XX +XXX,XX @@ roriw 0110000 .......... 101 ..... 0011011 @sh5
44
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
42
greviw 0110100 .......... 101 ..... 0011011 @sh5
45
TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
43
gorciw 0010100 .......... 101 ..... 0011011 @sh5
46
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
44
47
45
+# *** RV32 Zbc Standard Extension ***
48
- dinfo = drive_get_next(IF_NONE);
46
+clmul 0000101 .......... 001 ..... 0110011 @r
49
+ dinfo = drive_get_next(IF_PFLASH);
47
+clmulh 0000101 .......... 011 ..... 0110011 @r
50
+ if (!dinfo) {
48
+clmulr 0000101 .......... 010 ..... 0110011 @r
51
+ dinfo = drive_get_next(IF_NONE);
49
+
52
+ if (dinfo) {
50
# *** RV32 Zbs Standard Extension ***
53
+ warn_report("using \"-drive if=none\" for the OTP is deprecated, "
51
bclr 0100100 .......... 001 ..... 0110011 @r
54
+ "use \"-drive if=pflash\" instead.");
52
bclri 01001. ........... 001 ..... 0010011 @sh
53
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/riscv/bitmanip_helper.c
56
+++ b/target/riscv/bitmanip_helper.c
57
@@ -XXX,XX +XXX,XX @@
58
*
59
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
60
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
61
+ * Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
62
*
63
* This program is free software; you can redistribute it and/or modify it
64
* under the terms and conditions of the GNU General Public License,
65
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
66
{
67
return do_gorc(rs1, rs2, 32);
68
}
69
+
70
+target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
71
+{
72
+ target_ulong result = 0;
73
+
74
+ for (int i = 0; i < TARGET_LONG_BITS; i++) {
75
+ if ((rs2 >> i) & 1) {
76
+ result ^= (rs1 << i);
77
+ }
55
+ }
78
+ }
56
+ }
79
+
57
if (dinfo) {
80
+ return result;
58
int ret;
81
+}
59
uint64_t perm;
82
+
83
+target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
84
+{
85
+ target_ulong result = 0;
86
+
87
+ for (int i = 0; i < TARGET_LONG_BITS; i++) {
88
+ if ((rs2 >> i) & 1) {
89
+ result ^= (rs1 >> (TARGET_LONG_BITS - i - 1));
90
+ }
91
+ }
92
+
93
+ return result;
94
+}
95
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
96
index XXXXXXX..XXXXXXX 100644
97
--- a/target/riscv/insn_trans/trans_rvb.c.inc
98
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
99
@@ -XXX,XX +XXX,XX @@
100
/*
101
- * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
102
+ * RISC-V translation routines for the Zb[acs] Standard Extension.
103
*
104
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
105
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
106
@@ -XXX,XX +XXX,XX @@
107
} \
108
} while (0)
109
110
+#define REQUIRE_ZBC(ctx) do { \
111
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \
112
+ return false; \
113
+ } \
114
+} while (0)
115
+
116
#define REQUIRE_ZBS(ctx) do { \
117
if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
118
return false; \
119
@@ -XXX,XX +XXX,XX @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
120
REQUIRE_ZBA(ctx);
121
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
122
}
123
+
124
+static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
125
+{
126
+ REQUIRE_ZBC(ctx);
127
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
128
+}
129
+
130
+static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
131
+{
132
+ gen_helper_clmulr(dst, src1, src2);
133
+ tcg_gen_shri_tl(dst, dst, 1);
134
+}
135
+
136
+static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
137
+{
138
+ REQUIRE_ZBC(ctx);
139
+ return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
140
+}
141
+
142
+static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
143
+{
144
+ REQUIRE_ZBC(ctx);
145
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
146
+}
147
--
60
--
148
2.31.1
61
2.31.1
149
62
150
63
diff view generated by jsdifflib
[PULL 10/26] target/riscv: Reassign instructions to the Zbb-extension
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
This reassigns the instructions that are part of Zbb into it, with the
4
notable exceptions of the instructions (rev8, zext.w and orc.b) that
5
changed due to gorci, grevi and pack not being part of Zb[abcs].
6
7
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Acked-by: Bin Meng <bmeng.cn@gmail.com>
11
Message-id: 20210911140016.834071-11-philipp.tomsich@vrull.eu
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/insn32.decode | 40 ++++++++++---------
15
target/riscv/insn_trans/trans_rvb.c.inc | 51 ++++++++++++++-----------
16
2 files changed, 50 insertions(+), 41 deletions(-)
17
18
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/insn32.decode
21
+++ b/target/riscv/insn32.decode
22
@@ -XXX,XX +XXX,XX @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r
23
sh3add_uw 0010000 .......... 110 ..... 0111011 @r
24
slli_uw 00001 ............ 001 ..... 0011011 @sh
25
26
-# *** RV32B Standard Extension ***
27
+# *** RV32 Zbb Standard Extension ***
28
+andn 0100000 .......... 111 ..... 0110011 @r
29
clz 011000 000000 ..... 001 ..... 0010011 @r2
30
-ctz 011000 000001 ..... 001 ..... 0010011 @r2
31
cpop 011000 000010 ..... 001 ..... 0010011 @r2
32
+ctz 011000 000001 ..... 001 ..... 0010011 @r2
33
+max 0000101 .......... 110 ..... 0110011 @r
34
+maxu 0000101 .......... 111 ..... 0110011 @r
35
+min 0000101 .......... 100 ..... 0110011 @r
36
+minu 0000101 .......... 101 ..... 0110011 @r
37
+orn 0100000 .......... 110 ..... 0110011 @r
38
+rol 0110000 .......... 001 ..... 0110011 @r
39
+ror 0110000 .......... 101 ..... 0110011 @r
40
+rori 01100 ............ 101 ..... 0010011 @sh
41
sext_b 011000 000100 ..... 001 ..... 0010011 @r2
42
sext_h 011000 000101 ..... 001 ..... 0010011 @r2
43
-
44
-andn 0100000 .......... 111 ..... 0110011 @r
45
-orn 0100000 .......... 110 ..... 0110011 @r
46
xnor 0100000 .......... 100 ..... 0110011 @r
47
+
48
+# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
49
+clzw 0110000 00000 ..... 001 ..... 0011011 @r2
50
+ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
51
+cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
52
+rolw 0110000 .......... 001 ..... 0111011 @r
53
+roriw 0110000 .......... 101 ..... 0011011 @sh5
54
+rorw 0110000 .......... 101 ..... 0111011 @r
55
+
56
+# *** RV32B Standard Extension ***
57
pack 0000100 .......... 100 ..... 0110011 @r
58
packu 0100100 .......... 100 ..... 0110011 @r
59
packh 0000100 .......... 111 ..... 0110011 @r
60
-min 0000101 .......... 100 ..... 0110011 @r
61
-minu 0000101 .......... 101 ..... 0110011 @r
62
-max 0000101 .......... 110 ..... 0110011 @r
63
-maxu 0000101 .......... 111 ..... 0110011 @r
64
-ror 0110000 .......... 101 ..... 0110011 @r
65
-rol 0110000 .......... 001 ..... 0110011 @r
66
grev 0110100 .......... 101 ..... 0110011 @r
67
gorc 0010100 .......... 101 ..... 0110011 @r
68
69
-rori 01100. ........... 101 ..... 0010011 @sh
70
grevi 01101. ........... 101 ..... 0010011 @sh
71
gorci 00101. ........... 101 ..... 0010011 @sh
72
73
# *** RV64B Standard Extension (in addition to RV32B) ***
74
-clzw 0110000 00000 ..... 001 ..... 0011011 @r2
75
-ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
76
-cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
77
-
78
packw 0000100 .......... 100 ..... 0111011 @r
79
packuw 0100100 .......... 100 ..... 0111011 @r
80
-rorw 0110000 .......... 101 ..... 0111011 @r
81
-rolw 0110000 .......... 001 ..... 0111011 @r
82
grevw 0110100 .......... 101 ..... 0111011 @r
83
gorcw 0010100 .......... 101 ..... 0111011 @r
84
85
-roriw 0110000 .......... 101 ..... 0011011 @sh5
86
greviw 0110100 .......... 101 ..... 0011011 @sh5
87
gorciw 0010100 .......... 101 ..... 0011011 @sh5
88
89
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/riscv/insn_trans/trans_rvb.c.inc
92
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
93
@@ -XXX,XX +XXX,XX @@
94
/*
95
- * RISC-V translation routines for the Zb[acs] Standard Extension.
96
+ * RISC-V translation routines for the Zb[abcs] Standard Extension.
97
*
98
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
99
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
100
@@ -XXX,XX +XXX,XX @@
101
} \
102
} while (0)
103
104
+#define REQUIRE_ZBB(ctx) do { \
105
+ if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) { \
106
+ return false; \
107
+ } \
108
+} while (0)
109
+
110
#define REQUIRE_ZBC(ctx) do { \
111
if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \
112
return false; \
113
@@ -XXX,XX +XXX,XX @@ static void gen_clz(TCGv ret, TCGv arg1)
114
{
115
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
116
}
117
+
118
static bool trans_clz(DisasContext *ctx, arg_clz *a)
119
{
120
- REQUIRE_EXT(ctx, RVB);
121
+ REQUIRE_ZBB(ctx);
122
return gen_unary(ctx, a, EXT_ZERO, gen_clz);
123
}
124
125
@@ -XXX,XX +XXX,XX @@ static void gen_ctz(TCGv ret, TCGv arg1)
126
127
static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
128
{
129
- REQUIRE_EXT(ctx, RVB);
130
+ REQUIRE_ZBB(ctx);
131
return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
132
}
133
134
static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
135
{
136
- REQUIRE_EXT(ctx, RVB);
137
+ REQUIRE_ZBB(ctx);
138
return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
139
}
140
141
static bool trans_andn(DisasContext *ctx, arg_andn *a)
142
{
143
- REQUIRE_EXT(ctx, RVB);
144
+ REQUIRE_ZBB(ctx);
145
return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
146
}
147
148
static bool trans_orn(DisasContext *ctx, arg_orn *a)
149
{
150
- REQUIRE_EXT(ctx, RVB);
151
+ REQUIRE_ZBB(ctx);
152
return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
153
}
154
155
static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
156
{
157
- REQUIRE_EXT(ctx, RVB);
158
+ REQUIRE_ZBB(ctx);
159
return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
160
}
161
162
@@ -XXX,XX +XXX,XX @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
163
164
static bool trans_min(DisasContext *ctx, arg_min *a)
165
{
166
- REQUIRE_EXT(ctx, RVB);
167
+ REQUIRE_ZBB(ctx);
168
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
169
}
170
171
static bool trans_max(DisasContext *ctx, arg_max *a)
172
{
173
- REQUIRE_EXT(ctx, RVB);
174
+ REQUIRE_ZBB(ctx);
175
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
176
}
177
178
static bool trans_minu(DisasContext *ctx, arg_minu *a)
179
{
180
- REQUIRE_EXT(ctx, RVB);
181
+ REQUIRE_ZBB(ctx);
182
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
183
}
184
185
static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
186
{
187
- REQUIRE_EXT(ctx, RVB);
188
+ REQUIRE_ZBB(ctx);
189
return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
190
}
191
192
static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
193
{
194
- REQUIRE_EXT(ctx, RVB);
195
+ REQUIRE_ZBB(ctx);
196
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
197
}
198
199
static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
200
{
201
- REQUIRE_EXT(ctx, RVB);
202
+ REQUIRE_ZBB(ctx);
203
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
204
}
205
206
@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
207
208
static bool trans_ror(DisasContext *ctx, arg_ror *a)
209
{
210
- REQUIRE_EXT(ctx, RVB);
211
+ REQUIRE_ZBB(ctx);
212
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
213
}
214
215
static bool trans_rori(DisasContext *ctx, arg_rori *a)
216
{
217
- REQUIRE_EXT(ctx, RVB);
218
+ REQUIRE_ZBB(ctx);
219
return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
220
}
221
222
static bool trans_rol(DisasContext *ctx, arg_rol *a)
223
{
224
- REQUIRE_EXT(ctx, RVB);
225
+ REQUIRE_ZBB(ctx);
226
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
227
}
228
229
@@ -XXX,XX +XXX,XX @@ static void gen_clzw(TCGv ret, TCGv arg1)
230
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
231
{
232
REQUIRE_64BIT(ctx);
233
- REQUIRE_EXT(ctx, RVB);
234
+ REQUIRE_ZBB(ctx);
235
return gen_unary(ctx, a, EXT_NONE, gen_clzw);
236
}
237
238
@@ -XXX,XX +XXX,XX @@ static void gen_ctzw(TCGv ret, TCGv arg1)
239
static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
240
{
241
REQUIRE_64BIT(ctx);
242
- REQUIRE_EXT(ctx, RVB);
243
+ REQUIRE_ZBB(ctx);
244
return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
245
}
246
247
static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
248
{
249
REQUIRE_64BIT(ctx);
250
- REQUIRE_EXT(ctx, RVB);
251
+ REQUIRE_ZBB(ctx);
252
ctx->w = true;
253
return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
254
}
255
@@ -XXX,XX +XXX,XX @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
256
static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
257
{
258
REQUIRE_64BIT(ctx);
259
- REQUIRE_EXT(ctx, RVB);
260
+ REQUIRE_ZBB(ctx);
261
ctx->w = true;
262
return gen_shift(ctx, a, EXT_NONE, gen_rorw);
263
}
264
@@ -XXX,XX +XXX,XX @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
265
static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
266
{
267
REQUIRE_64BIT(ctx);
268
- REQUIRE_EXT(ctx, RVB);
269
+ REQUIRE_ZBB(ctx);
270
ctx->w = true;
271
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
272
}
273
@@ -XXX,XX +XXX,XX @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
274
static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
275
{
276
REQUIRE_64BIT(ctx);
277
- REQUIRE_EXT(ctx, RVB);
278
+ REQUIRE_ZBB(ctx);
279
ctx->w = true;
280
return gen_shift(ctx, a, EXT_NONE, gen_rolw);
281
}
282
--
283
2.31.1
284
285
diff view generated by jsdifflib
[PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a
4
orc.b instruction (equivalent to the orc.b pseudo-instruction built on
5
gorci from pre-0.93 draft-B) is available, mainly targeting
6
string-processing workloads.
7
8
This commit adds the new orc.b instruction and removed gorc/gorci.
9
10
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20210911140016.834071-12-philipp.tomsich@vrull.eu
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
16
target/riscv/helper.h | 2 --
17
target/riscv/insn32.decode | 6 +---
18
target/riscv/bitmanip_helper.c | 26 -----------------
19
target/riscv/insn_trans/trans_rvb.c.inc | 39 +++++++++++--------------
20
4 files changed, 18 insertions(+), 55 deletions(-)
21
22
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/helper.h
25
+++ b/target/riscv/helper.h
26
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
27
/* Bitmanip */
28
DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
29
DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
30
-DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
31
-DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
32
DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
33
DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
34
35
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/riscv/insn32.decode
38
+++ b/target/riscv/insn32.decode
39
@@ -XXX,XX +XXX,XX @@ max 0000101 .......... 110 ..... 0110011 @r
40
maxu 0000101 .......... 111 ..... 0110011 @r
41
min 0000101 .......... 100 ..... 0110011 @r
42
minu 0000101 .......... 101 ..... 0110011 @r
43
+orc_b 001010 000111 ..... 101 ..... 0010011 @r2
44
orn 0100000 .......... 110 ..... 0110011 @r
45
rol 0110000 .......... 001 ..... 0110011 @r
46
ror 0110000 .......... 101 ..... 0110011 @r
47
@@ -XXX,XX +XXX,XX @@ pack 0000100 .......... 100 ..... 0110011 @r
48
packu 0100100 .......... 100 ..... 0110011 @r
49
packh 0000100 .......... 111 ..... 0110011 @r
50
grev 0110100 .......... 101 ..... 0110011 @r
51
-gorc 0010100 .......... 101 ..... 0110011 @r
52
-
53
grevi 01101. ........... 101 ..... 0010011 @sh
54
-gorci 00101. ........... 101 ..... 0010011 @sh
55
56
# *** RV64B Standard Extension (in addition to RV32B) ***
57
packw 0000100 .......... 100 ..... 0111011 @r
58
packuw 0100100 .......... 100 ..... 0111011 @r
59
grevw 0110100 .......... 101 ..... 0111011 @r
60
-gorcw 0010100 .......... 101 ..... 0111011 @r
61
62
greviw 0110100 .......... 101 ..... 0011011 @sh5
63
-gorciw 0010100 .......... 101 ..... 0011011 @sh5
64
65
# *** RV32 Zbc Standard Extension ***
66
clmul 0000101 .......... 001 ..... 0110011 @r
67
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/riscv/bitmanip_helper.c
70
+++ b/target/riscv/bitmanip_helper.c
71
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
72
return do_grev(rs1, rs2, 32);
73
}
74
75
-static target_ulong do_gorc(target_ulong rs1,
76
- target_ulong rs2,
77
- int bits)
78
-{
79
- target_ulong x = rs1;
80
- int i, shift;
81
-
82
- for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
83
- if (rs2 & shift) {
84
- x |= do_swap(x, adjacent_masks[i], shift);
85
- }
86
- }
87
-
88
- return x;
89
-}
90
-
91
-target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
92
-{
93
- return do_gorc(rs1, rs2, TARGET_LONG_BITS);
94
-}
95
-
96
-target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
97
-{
98
- return do_gorc(rs1, rs2, 32);
99
-}
100
-
101
target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
102
{
103
target_ulong result = 0;
104
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
105
index XXXXXXX..XXXXXXX 100644
106
--- a/target/riscv/insn_trans/trans_rvb.c.inc
107
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
108
@@ -XXX,XX +XXX,XX @@ static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
109
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
110
}
111
112
-static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
113
+static void gen_orc_b(TCGv ret, TCGv source1)
114
{
115
- REQUIRE_EXT(ctx, RVB);
116
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
117
+ TCGv tmp = tcg_temp_new();
118
+ TCGv ones = tcg_constant_tl(dup_const_tl(MO_8, 0x01));
119
+
120
+ /* Set lsb in each byte if the byte was zero. */
121
+ tcg_gen_sub_tl(tmp, source1, ones);
122
+ tcg_gen_andc_tl(tmp, tmp, source1);
123
+ tcg_gen_shri_tl(tmp, tmp, 7);
124
+ tcg_gen_andc_tl(tmp, ones, tmp);
125
+
126
+ /* Replicate the lsb of each byte across the byte. */
127
+ tcg_gen_muli_tl(ret, tmp, 0xff);
128
+
129
+ tcg_temp_free(tmp);
130
}
131
132
-static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
133
+static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
134
{
135
- REQUIRE_EXT(ctx, RVB);
136
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
137
+ REQUIRE_ZBB(ctx);
138
+ return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
139
}
140
141
#define GEN_SHADD(SHAMT) \
142
@@ -XXX,XX +XXX,XX @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
143
return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
144
}
145
146
-static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
147
-{
148
- REQUIRE_64BIT(ctx);
149
- REQUIRE_EXT(ctx, RVB);
150
- ctx->w = true;
151
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
152
-}
153
-
154
-static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
155
-{
156
- REQUIRE_64BIT(ctx);
157
- REQUIRE_EXT(ctx, RVB);
158
- ctx->w = true;
159
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
160
-}
161
-
162
#define GEN_SHADD_UW(SHAMT) \
163
static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
164
{ \
165
--
166
2.31.1
167
168
diff view generated by jsdifflib
[PULL 12/26] target/riscv: Add a REQUIRE_32BIT macro
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
With the changes to Zb[abcs], there's some encodings that are
4
different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,
5
we'll need a helper macro allowing us to select on RV32, as well.
6
7
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
11
Message-id: 20210911140016.834071-13-philipp.tomsich@vrull.eu
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/translate.c | 6 ++++++
15
1 file changed, 6 insertions(+)
16
17
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/translate.c
20
+++ b/target/riscv/translate.c
21
@@ -XXX,XX +XXX,XX @@ EX_SH(12)
22
} \
23
} while (0)
24
25
+#define REQUIRE_32BIT(ctx) do { \
26
+ if (!is_32bit(ctx)) { \
27
+ return false; \
28
+ } \
29
+} while (0)
30
+
31
#define REQUIRE_64BIT(ctx) do { \
32
if (is_32bit(ctx)) { \
33
return false; \
34
--
35
2.31.1
36
37
diff view generated by jsdifflib
[PULL 13/26] target/riscv: Add rev8 instruction, removing grev/grevi
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
The 1.0.0 version of Zbb does not contain grev/grevi. Instead, a
4
rev8 instruction (equivalent to the rev8 pseudo-instruction built on
5
grevi from pre-0.93 draft-B) is available.
6
7
This commit adds the new rev8 instruction and removes grev/grevi.
8
9
Note that there is no W-form of this instruction (both a
10
sign-extending and zero-extending 32-bit version can easily be
11
synthesized by following rev8 with either a srai or srli instruction
12
on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are
13
different.
14
15
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
18
Message-id: 20210911140016.834071-14-philipp.tomsich@vrull.eu
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20
---
21
target/riscv/helper.h | 2 --
22
target/riscv/insn32.decode | 12 ++++----
23
target/riscv/bitmanip_helper.c | 40 -------------------------
24
target/riscv/insn_trans/trans_rvb.c.inc | 40 +++++--------------------
25
4 files changed, 15 insertions(+), 79 deletions(-)
26
27
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/riscv/helper.h
30
+++ b/target/riscv/helper.h
31
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl)
32
DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
33
34
/* Bitmanip */
35
-DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
36
-DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
37
DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
38
DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
39
40
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/riscv/insn32.decode
43
+++ b/target/riscv/insn32.decode
44
@@ -XXX,XX +XXX,XX @@ min 0000101 .......... 100 ..... 0110011 @r
45
minu 0000101 .......... 101 ..... 0110011 @r
46
orc_b 001010 000111 ..... 101 ..... 0010011 @r2
47
orn 0100000 .......... 110 ..... 0110011 @r
48
+# The encoding for rev8 differs between RV32 and RV64.
49
+# rev8_32 denotes the RV32 variant.
50
+rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
51
rol 0110000 .......... 001 ..... 0110011 @r
52
ror 0110000 .......... 101 ..... 0110011 @r
53
rori 01100 ............ 101 ..... 0010011 @sh
54
@@ -XXX,XX +XXX,XX @@ xnor 0100000 .......... 100 ..... 0110011 @r
55
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
56
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
57
cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
58
+# The encoding for rev8 differs between RV32 and RV64.
59
+# When executing on RV64, the encoding used in RV32 is an illegal
60
+# instruction, so we use different handler functions to differentiate.
61
+rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
62
rolw 0110000 .......... 001 ..... 0111011 @r
63
roriw 0110000 .......... 101 ..... 0011011 @sh5
64
rorw 0110000 .......... 101 ..... 0111011 @r
65
@@ -XXX,XX +XXX,XX @@ rorw 0110000 .......... 101 ..... 0111011 @r
66
pack 0000100 .......... 100 ..... 0110011 @r
67
packu 0100100 .......... 100 ..... 0110011 @r
68
packh 0000100 .......... 111 ..... 0110011 @r
69
-grev 0110100 .......... 101 ..... 0110011 @r
70
-grevi 01101. ........... 101 ..... 0010011 @sh
71
72
# *** RV64B Standard Extension (in addition to RV32B) ***
73
packw 0000100 .......... 100 ..... 0111011 @r
74
packuw 0100100 .......... 100 ..... 0111011 @r
75
-grevw 0110100 .......... 101 ..... 0111011 @r
76
-
77
-greviw 0110100 .......... 101 ..... 0011011 @sh5
78
79
# *** RV32 Zbc Standard Extension ***
80
clmul 0000101 .......... 001 ..... 0110011 @r
81
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/riscv/bitmanip_helper.c
84
+++ b/target/riscv/bitmanip_helper.c
85
@@ -XXX,XX +XXX,XX @@
86
#include "exec/helper-proto.h"
87
#include "tcg/tcg.h"
88
89
-static const uint64_t adjacent_masks[] = {
90
- dup_const(MO_8, 0x55),
91
- dup_const(MO_8, 0x33),
92
- dup_const(MO_8, 0x0f),
93
- dup_const(MO_16, 0xff),
94
- dup_const(MO_32, 0xffff),
95
- UINT32_MAX
96
-};
97
-
98
-static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
99
-{
100
- return ((x & mask) << shift) | ((x & ~mask) >> shift);
101
-}
102
-
103
-static target_ulong do_grev(target_ulong rs1,
104
- target_ulong rs2,
105
- int bits)
106
-{
107
- target_ulong x = rs1;
108
- int i, shift;
109
-
110
- for (i = 0, shift = 1; shift < bits; i++, shift <<= 1) {
111
- if (rs2 & shift) {
112
- x = do_swap(x, adjacent_masks[i], shift);
113
- }
114
- }
115
-
116
- return x;
117
-}
118
-
119
-target_ulong HELPER(grev)(target_ulong rs1, target_ulong rs2)
120
-{
121
- return do_grev(rs1, rs2, TARGET_LONG_BITS);
122
-}
123
-
124
-target_ulong HELPER(grevw)(target_ulong rs1, target_ulong rs2)
125
-{
126
- return do_grev(rs1, rs2, 32);
127
-}
128
-
129
target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
130
{
131
target_ulong result = 0;
132
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
133
index XXXXXXX..XXXXXXX 100644
134
--- a/target/riscv/insn_trans/trans_rvb.c.inc
135
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
136
@@ -XXX,XX +XXX,XX @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
137
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
138
}
139
140
-static bool trans_grev(DisasContext *ctx, arg_grev *a)
141
+static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
142
{
143
- REQUIRE_EXT(ctx, RVB);
144
- return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
145
-}
146
-
147
-static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
148
-{
149
- if (shamt == TARGET_LONG_BITS - 8) {
150
- /* rev8, byte swaps */
151
- tcg_gen_bswap_tl(dest, src);
152
- } else {
153
- gen_helper_grev(dest, src, tcg_constant_tl(shamt));
154
- }
155
+ REQUIRE_32BIT(ctx);
156
+ REQUIRE_ZBB(ctx);
157
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
158
}
159
160
-static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
161
+static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
162
{
163
- REQUIRE_EXT(ctx, RVB);
164
- return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
165
+ REQUIRE_64BIT(ctx);
166
+ REQUIRE_ZBB(ctx);
167
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
168
}
169
170
static void gen_orc_b(TCGv ret, TCGv source1)
171
@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
172
return gen_shift(ctx, a, EXT_NONE, gen_rolw);
173
}
174
175
-static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
176
-{
177
- REQUIRE_64BIT(ctx);
178
- REQUIRE_EXT(ctx, RVB);
179
- ctx->w = true;
180
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
181
-}
182
-
183
-static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
184
-{
185
- REQUIRE_64BIT(ctx);
186
- REQUIRE_EXT(ctx, RVB);
187
- ctx->w = true;
188
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
189
-}
190
-
191
#define GEN_SHADD_UW(SHAMT) \
192
static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
193
{ \
194
--
195
2.31.1
196
197
diff view generated by jsdifflib
[PULL 14/26] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a
4
zext.h instruction is provided (built on pack/packh from pre-0.93
5
draft-B) is available.
6
7
This commit adds zext.h and removes the pack* instructions.
8
9
Note that the encodings for zext.h are different between RV32 and
10
RV64, which is handled through REQUIRE_32BIT.
11
12
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-id: 20210911140016.834071-15-philipp.tomsich@vrull.eu
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
18
target/riscv/insn32.decode | 12 ++--
19
target/riscv/insn_trans/trans_rvb.c.inc | 86 ++++---------------------
20
2 files changed, 21 insertions(+), 77 deletions(-)
21
22
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/insn32.decode
25
+++ b/target/riscv/insn32.decode
26
@@ -XXX,XX +XXX,XX @@ rori 01100 ............ 101 ..... 0010011 @sh
27
sext_b 011000 000100 ..... 001 ..... 0010011 @r2
28
sext_h 011000 000101 ..... 001 ..... 0010011 @r2
29
xnor 0100000 .......... 100 ..... 0110011 @r
30
+# The encoding for zext.h differs between RV32 and RV64.
31
+# zext_h_32 denotes the RV32 variant.
32
+zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
33
34
# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
35
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
36
@@ -XXX,XX +XXX,XX @@ rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
37
rolw 0110000 .......... 001 ..... 0111011 @r
38
roriw 0110000 .......... 101 ..... 0011011 @sh5
39
rorw 0110000 .......... 101 ..... 0111011 @r
40
+# The encoding for zext.h differs between RV32 and RV64.
41
+# When executing on RV64, the encoding used in RV32 is an illegal
42
+# instruction, so we use different handler functions to differentiate.
43
+zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
44
45
# *** RV32B Standard Extension ***
46
-pack 0000100 .......... 100 ..... 0110011 @r
47
-packu 0100100 .......... 100 ..... 0110011 @r
48
-packh 0000100 .......... 111 ..... 0110011 @r
49
50
# *** RV64B Standard Extension (in addition to RV32B) ***
51
-packw 0000100 .......... 100 ..... 0111011 @r
52
-packuw 0100100 .......... 100 ..... 0111011 @r
53
54
# *** RV32 Zbc Standard Extension ***
55
clmul 0000101 .......... 001 ..... 0110011 @r
56
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/riscv/insn_trans/trans_rvb.c.inc
59
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
60
@@ -XXX,XX +XXX,XX @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
61
return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
62
}
63
64
-static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
65
-{
66
- tcg_gen_deposit_tl(ret, arg1, arg2,
67
- TARGET_LONG_BITS / 2,
68
- TARGET_LONG_BITS / 2);
69
-}
70
-
71
-static bool trans_pack(DisasContext *ctx, arg_pack *a)
72
-{
73
- REQUIRE_EXT(ctx, RVB);
74
- return gen_arith(ctx, a, EXT_NONE, gen_pack);
75
-}
76
-
77
-static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
78
-{
79
- TCGv t = tcg_temp_new();
80
- tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
81
- tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
82
- tcg_temp_free(t);
83
-}
84
-
85
-static bool trans_packu(DisasContext *ctx, arg_packu *a)
86
-{
87
- REQUIRE_EXT(ctx, RVB);
88
- return gen_arith(ctx, a, EXT_NONE, gen_packu);
89
-}
90
-
91
-static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
92
-{
93
- TCGv t = tcg_temp_new();
94
- tcg_gen_ext8u_tl(t, arg2);
95
- tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
96
- tcg_temp_free(t);
97
-}
98
-
99
-static bool trans_packh(DisasContext *ctx, arg_packh *a)
100
-{
101
- REQUIRE_EXT(ctx, RVB);
102
- return gen_arith(ctx, a, EXT_NONE, gen_packh);
103
-}
104
-
105
static bool trans_min(DisasContext *ctx, arg_min *a)
106
{
107
REQUIRE_ZBB(ctx);
108
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(1)
109
GEN_TRANS_SHADD(2)
110
GEN_TRANS_SHADD(3)
111
112
+static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a)
113
+{
114
+ REQUIRE_32BIT(ctx);
115
+ REQUIRE_ZBB(ctx);
116
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
117
+}
118
+
119
+static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
120
+{
121
+ REQUIRE_64BIT(ctx);
122
+ REQUIRE_ZBB(ctx);
123
+ return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
124
+}
125
+
126
static void gen_clzw(TCGv ret, TCGv arg1)
127
{
128
TCGv t = tcg_temp_new();
129
@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
130
return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
131
}
132
133
-static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
134
-{
135
- TCGv t = tcg_temp_new();
136
- tcg_gen_ext16s_tl(t, arg2);
137
- tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
138
- tcg_temp_free(t);
139
-}
140
-
141
-static bool trans_packw(DisasContext *ctx, arg_packw *a)
142
-{
143
- REQUIRE_64BIT(ctx);
144
- REQUIRE_EXT(ctx, RVB);
145
- return gen_arith(ctx, a, EXT_NONE, gen_packw);
146
-}
147
-
148
-static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
149
-{
150
- TCGv t = tcg_temp_new();
151
- tcg_gen_shri_tl(t, arg1, 16);
152
- tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
153
- tcg_gen_ext32s_tl(ret, ret);
154
- tcg_temp_free(t);
155
-}
156
-
157
-static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
158
-{
159
- REQUIRE_64BIT(ctx);
160
- REQUIRE_EXT(ctx, RVB);
161
- return gen_arith(ctx, a, EXT_NONE, gen_packuw);
162
-}
163
-
164
static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
165
{
166
TCGv_i32 t1 = tcg_temp_new_i32();
167
--
168
2.31.1
169
170
diff view generated by jsdifflib
[PULL 15/26] target/riscv: Remove RVB (replaced by Zb[abcs])
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
With everything classified as Zb[abcs] and pre-0.93 draft-B
4
instructions that are not part of Zb[abcs] removed, we can remove the
5
remaining support code for RVB.
6
7
Note that RVB has been retired for good and misa.B will neither mean
8
'some' or 'all of' Zb*:
9
https://lists.riscv.org/g/tech-bitmanip/message/532
10
11
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
15
Message-id: 20210911140016.834071-16-philipp.tomsich@vrull.eu
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
18
target/riscv/cpu.h | 3 ---
19
target/riscv/insn32.decode | 4 ----
20
target/riscv/cpu.c | 26 --------------------------
21
3 files changed, 33 deletions(-)
22
23
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/riscv/cpu.h
26
+++ b/target/riscv/cpu.h
27
@@ -XXX,XX +XXX,XX @@
28
#define RVS RV('S')
29
#define RVU RV('U')
30
#define RVH RV('H')
31
-#define RVB RV('B')
32
33
/* S extension denotes that Supervisor mode exists, however it is possible
34
to have a core that support S mode but does not have an MMU and there
35
@@ -XXX,XX +XXX,XX @@ enum {
36
#define PRIV_VERSION_1_10_0 0x00011000
37
#define PRIV_VERSION_1_11_0 0x00011100
38
39
-#define BEXT_VERSION_0_93_0 0x00009300
40
#define VEXT_VERSION_0_07_1 0x00000701
41
42
enum {
43
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
44
bool ext_f;
45
bool ext_d;
46
bool ext_c;
47
- bool ext_b;
48
bool ext_s;
49
bool ext_u;
50
bool ext_h;
51
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/riscv/insn32.decode
54
+++ b/target/riscv/insn32.decode
55
@@ -XXX,XX +XXX,XX @@ rorw 0110000 .......... 101 ..... 0111011 @r
56
# instruction, so we use different handler functions to differentiate.
57
zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
58
59
-# *** RV32B Standard Extension ***
60
-
61
-# *** RV64B Standard Extension (in addition to RV32B) ***
62
-
63
# *** RV32 Zbc Standard Extension ***
64
clmul 0000101 .......... 001 ..... 0110011 @r
65
clmulh 0000101 .......... 011 ..... 0110011 @r
66
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/riscv/cpu.c
69
+++ b/target/riscv/cpu.c
70
@@ -XXX,XX +XXX,XX @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
71
env->priv_ver = priv_ver;
72
}
73
74
-static void set_bext_version(CPURISCVState *env, int bext_ver)
75
-{
76
- env->bext_ver = bext_ver;
77
-}
78
-
79
static void set_vext_version(CPURISCVState *env, int vext_ver)
80
{
81
env->vext_ver = vext_ver;
82
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
83
if (cpu->cfg.ext_h) {
84
target_misa |= RVH;
85
}
86
- if (cpu->cfg.ext_b) {
87
- int bext_version = BEXT_VERSION_0_93_0;
88
- target_misa |= RVB;
89
-
90
- if (cpu->cfg.bext_spec) {
91
- if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
92
- bext_version = BEXT_VERSION_0_93_0;
93
- } else {
94
- error_setg(errp,
95
- "Unsupported bitmanip spec version '%s'",
96
- cpu->cfg.bext_spec);
97
- return;
98
- }
99
- } else {
100
- qemu_log("bitmanip version is not specified, "
101
- "use the default value v0.93\n");
102
- }
103
- set_bext_version(env, bext_version);
104
- }
105
if (cpu->cfg.ext_v) {
106
int vext_version = VEXT_VERSION_0_07_1;
107
target_misa |= RVV;
108
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
109
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
110
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
111
/* This is experimental so mark with 'x-' */
112
- DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
113
DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
114
DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
115
DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
116
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
117
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
118
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
119
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
120
- DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
121
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
122
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
123
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
124
--
125
2.31.1
126
127
diff view generated by jsdifflib
[PULL 16/26] disas/riscv: Add Zb[abcs] instructions
Deleted patch
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
1
3
With the addition of Zb[abcs], we also need to add disassembler
4
support for these new instructions.
5
6
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
7
Acked-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210911140016.834071-17-philipp.tomsich@vrull.eu
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
disas/riscv.c | 157 +++++++++++++++++++++++++++++++++++++++++++++++++-
12
1 file changed, 154 insertions(+), 3 deletions(-)
13
14
diff --git a/disas/riscv.c b/disas/riscv.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/disas/riscv.c
17
+++ b/disas/riscv.c
18
@@ -XXX,XX +XXX,XX @@ typedef enum {
19
rv_op_fsflags = 316,
20
rv_op_fsrmi = 317,
21
rv_op_fsflagsi = 318,
22
+ rv_op_bseti = 319,
23
+ rv_op_bclri = 320,
24
+ rv_op_binvi = 321,
25
+ rv_op_bexti = 322,
26
+ rv_op_rori = 323,
27
+ rv_op_clz = 324,
28
+ rv_op_ctz = 325,
29
+ rv_op_cpop = 326,
30
+ rv_op_sext_h = 327,
31
+ rv_op_sext_b = 328,
32
+ rv_op_xnor = 329,
33
+ rv_op_orn = 330,
34
+ rv_op_andn = 331,
35
+ rv_op_rol = 332,
36
+ rv_op_ror = 333,
37
+ rv_op_sh1add = 334,
38
+ rv_op_sh2add = 335,
39
+ rv_op_sh3add = 336,
40
+ rv_op_sh1add_uw = 337,
41
+ rv_op_sh2add_uw = 338,
42
+ rv_op_sh3add_uw = 339,
43
+ rv_op_clmul = 340,
44
+ rv_op_clmulr = 341,
45
+ rv_op_clmulh = 342,
46
+ rv_op_min = 343,
47
+ rv_op_minu = 344,
48
+ rv_op_max = 345,
49
+ rv_op_maxu = 346,
50
+ rv_op_clzw = 347,
51
+ rv_op_ctzw = 348,
52
+ rv_op_cpopw = 349,
53
+ rv_op_slli_uw = 350,
54
+ rv_op_add_uw = 351,
55
+ rv_op_rolw = 352,
56
+ rv_op_rorw = 353,
57
+ rv_op_rev8 = 354,
58
+ rv_op_zext_h = 355,
59
+ rv_op_roriw = 356,
60
+ rv_op_orc_b = 357,
61
+ rv_op_bset = 358,
62
+ rv_op_bclr = 359,
63
+ rv_op_binv = 360,
64
+ rv_op_bext = 361,
65
} rv_op;
66
67
/* structures */
68
@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
69
{ "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
70
{ "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
71
{ "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
72
+ { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
73
+ { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
74
+ { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
75
+ { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
76
+ { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
77
+ { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
78
+ { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
79
+ { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
80
+ { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
81
+ { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
82
+ { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
83
+ { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
84
+ { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
85
+ { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
86
+ { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
87
+ { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
88
+ { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
89
+ { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
90
+ { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
91
+ { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
92
+ { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
93
+ { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
94
+ { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
95
+ { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
96
+ { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
97
+ { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
98
+ { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
99
+ { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
100
+ { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
101
+ { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
102
+ { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
103
+ { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
104
+ { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
105
+ { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
106
+ { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
107
+ { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
108
+ { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
109
+ { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
110
+ { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
111
+ { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
112
+ { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
113
+ { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
114
+ { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
115
};
116
117
/* CSR names */
118
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
119
case 0: op = rv_op_addi; break;
120
case 1:
121
switch (((inst >> 27) & 0b11111)) {
122
- case 0: op = rv_op_slli; break;
123
+ case 0b00000: op = rv_op_slli; break;
124
+ case 0b00101: op = rv_op_bseti; break;
125
+ case 0b01001: op = rv_op_bclri; break;
126
+ case 0b01101: op = rv_op_binvi; break;
127
+ case 0b01100:
128
+ switch (((inst >> 20) & 0b1111111)) {
129
+ case 0b0000000: op = rv_op_clz; break;
130
+ case 0b0000001: op = rv_op_ctz; break;
131
+ case 0b0000010: op = rv_op_cpop; break;
132
+ /* 0b0000011 */
133
+ case 0b0000100: op = rv_op_sext_b; break;
134
+ case 0b0000101: op = rv_op_sext_h; break;
135
+ }
136
+ break;
137
}
138
break;
139
case 2: op = rv_op_slti; break;
140
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
141
case 4: op = rv_op_xori; break;
142
case 5:
143
switch (((inst >> 27) & 0b11111)) {
144
- case 0: op = rv_op_srli; break;
145
- case 8: op = rv_op_srai; break;
146
+ case 0b00000: op = rv_op_srli; break;
147
+ case 0b00101: op = rv_op_orc_b; break;
148
+ case 0b01000: op = rv_op_srai; break;
149
+ case 0b01001: op = rv_op_bexti; break;
150
+ case 0b01100: op = rv_op_rori; break;
151
+ case 0b01101:
152
+ switch ((inst >> 20) & 0b1111111) {
153
+ case 0b0111000: op = rv_op_rev8; break;
154
+ }
155
+ break;
156
}
157
break;
158
case 6: op = rv_op_ori; break;
159
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
160
case 1:
161
switch (((inst >> 25) & 0b1111111)) {
162
case 0: op = rv_op_slliw; break;
163
+ case 4: op = rv_op_slli_uw; break;
164
+ case 48:
165
+ switch ((inst >> 20) & 0b11111) {
166
+ case 0b00000: op = rv_op_clzw; break;
167
+ case 0b00001: op = rv_op_ctzw; break;
168
+ case 0b00010: op = rv_op_cpopw; break;
169
+ }
170
+ break;
171
}
172
break;
173
case 5:
174
switch (((inst >> 25) & 0b1111111)) {
175
case 0: op = rv_op_srliw; break;
176
case 32: op = rv_op_sraiw; break;
177
+ case 48: op = rv_op_roriw; break;
178
}
179
break;
180
}
181
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
182
case 13: op = rv_op_divu; break;
183
case 14: op = rv_op_rem; break;
184
case 15: op = rv_op_remu; break;
185
+ case 36:
186
+ switch ((inst >> 20) & 0b11111) {
187
+ case 0: op = rv_op_zext_h; break;
188
+ }
189
+ break;
190
+ case 41: op = rv_op_clmul; break;
191
+ case 42: op = rv_op_clmulr; break;
192
+ case 43: op = rv_op_clmulh; break;
193
+ case 44: op = rv_op_min; break;
194
+ case 45: op = rv_op_minu; break;
195
+ case 46: op = rv_op_max; break;
196
+ case 47: op = rv_op_maxu; break;
197
+ case 130: op = rv_op_sh1add; break;
198
+ case 132: op = rv_op_sh2add; break;
199
+ case 134: op = rv_op_sh3add; break;
200
+ case 161: op = rv_op_bset; break;
201
case 256: op = rv_op_sub; break;
202
+ case 260: op = rv_op_xnor; break;
203
case 261: op = rv_op_sra; break;
204
+ case 262: op = rv_op_orn; break;
205
+ case 263: op = rv_op_andn; break;
206
+ case 289: op = rv_op_bclr; break;
207
+ case 293: op = rv_op_bext; break;
208
+ case 385: op = rv_op_rol; break;
209
+ case 386: op = rv_op_ror; break;
210
+ case 417: op = rv_op_binv; break;
211
}
212
break;
213
case 13: op = rv_op_lui; break;
214
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
215
case 13: op = rv_op_divuw; break;
216
case 14: op = rv_op_remw; break;
217
case 15: op = rv_op_remuw; break;
218
+ case 32: op = rv_op_add_uw; break;
219
+ case 36:
220
+ switch ((inst >> 20) & 0b11111) {
221
+ case 0: op = rv_op_zext_h; break;
222
+ }
223
+ break;
224
+ case 130: op = rv_op_sh1add_uw; break;
225
+ case 132: op = rv_op_sh2add_uw; break;
226
+ case 134: op = rv_op_sh3add_uw; break;
227
case 256: op = rv_op_subw; break;
228
case 261: op = rv_op_sraw; break;
229
+ case 385: op = rv_op_rolw; break;
230
+ case 389: op = rv_op_rorw; break;
231
}
232
break;
233
case 16:
234
--
235
2.31.1
236
237
diff view generated by jsdifflib
[PULL 17/26] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()
Deleted patch
1
From: Frank Chang <frank.chang@sifive.com>
2
1
3
When V=1, both vsstauts.FS and HS-level sstatus.FS are in effect.
4
Modifying the floating-point state when V=1 causes both fields to
5
be set to 3 (Dirty).
6
7
However, it's possible that HS-level sstatus.FS is Clean and VS-level
8
vsstatus.FS is Dirty at the time mark_fs_dirty() is called when V=1.
9
We can't early return for this case because we still need to set
10
sstatus.FS to Dirty according to spec.
11
12
Signed-off-by: Frank Chang <frank.chang@sifive.com>
13
Reviewed-by: Vincent Chen <vincent.chen@sifive.com>
14
Tested-by: Vincent Chen <vincent.chen@sifive.com>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Message-id: 20210921020234.123448-1-frank.chang@sifive.com
18
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
---
20
target/riscv/cpu.h | 4 ++++
21
target/riscv/translate.c | 30 +++++++++++++++++-------------
22
2 files changed, 21 insertions(+), 13 deletions(-)
23
24
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/riscv/cpu.h
27
+++ b/target/riscv/cpu.h
28
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, SEW, 5, 3)
29
FIELD(TB_FLAGS, VILL, 8, 1)
30
/* Is a Hypervisor instruction load/store allowed? */
31
FIELD(TB_FLAGS, HLSX, 9, 1)
32
+FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
33
34
bool riscv_cpu_is_32bit(CPURISCVState *env);
35
36
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
37
get_field(env->hstatus, HSTATUS_HU))) {
38
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
39
}
40
+
41
+ flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
42
+ get_field(env->mstatus_hs, MSTATUS_FS));
43
}
44
#endif
45
46
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/riscv/translate.c
49
+++ b/target/riscv/translate.c
50
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
51
target_ulong misa;
52
uint32_t opcode;
53
uint32_t mstatus_fs;
54
+ uint32_t mstatus_hs_fs;
55
uint32_t mem_idx;
56
/* Remember the rounding mode encoded in the previous fp instruction,
57
which we have already installed into env->fp_status. Or -1 for
58
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
59
static void mark_fs_dirty(DisasContext *ctx)
60
{
61
TCGv tmp;
62
- target_ulong sd;
63
+ target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
64
65
- if (ctx->mstatus_fs == MSTATUS_FS) {
66
- return;
67
- }
68
- /* Remember the state change for the rest of the TB. */
69
- ctx->mstatus_fs = MSTATUS_FS;
70
+ if (ctx->mstatus_fs != MSTATUS_FS) {
71
+ /* Remember the state change for the rest of the TB. */
72
+ ctx->mstatus_fs = MSTATUS_FS;
73
74
- tmp = tcg_temp_new();
75
- sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
76
+ tmp = tcg_temp_new();
77
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
78
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
79
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
80
+ tcg_temp_free(tmp);
81
+ }
82
83
- tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
84
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
85
- tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
86
+ if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
87
+ /* Remember the stage change for the rest of the TB. */
88
+ ctx->mstatus_hs_fs = MSTATUS_FS;
89
90
- if (ctx->virt_enabled) {
91
+ tmp = tcg_temp_new();
92
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
93
tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
94
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
95
+ tcg_temp_free(tmp);
96
}
97
- tcg_temp_free(tmp);
98
}
99
#else
100
static inline void mark_fs_dirty(DisasContext *ctx) { }
101
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
102
ctx->frm = -1; /* unknown rounding mode */
103
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
104
ctx->vlen = cpu->cfg.vlen;
105
+ ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
106
ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
107
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
108
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
109
--
110
2.31.1
111
112
diff view generated by jsdifflib
[PULL 18/26] hw/char: ibex_uart: Register device in 'input' category
Deleted patch
1
From: Bin Meng <bmeng.cn@gmail.com>
2
1
3
The category of ibex_uart device is not set. Put it into the
4
'input' category.
5
6
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210926105003.2716-1-bmeng.cn@gmail.com
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
hw/char/ibex_uart.c | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/char/ibex_uart.c
18
+++ b/hw/char/ibex_uart.c
19
@@ -XXX,XX +XXX,XX @@ static void ibex_uart_class_init(ObjectClass *klass, void *data)
20
dc->realize = ibex_uart_realize;
21
dc->vmsd = &vmstate_ibex_uart;
22
device_class_set_props(dc, ibex_uart_properties);
23
+ set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
24
}
25
26
static const TypeInfo ibex_uart_info = {
27
--
28
2.31.1
29
30
diff view generated by jsdifflib
[PULL 19/26] hw/char: shakti_uart: Register device in 'input' category
Deleted patch
1
From: Bin Meng <bmeng.cn@gmail.com>
2
1
3
The category of shakti_uart device is not set. Put it into the
4
'input' category.
5
6
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210926105003.2716-2-bmeng.cn@gmail.com
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
hw/char/shakti_uart.c | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/char/shakti_uart.c
18
+++ b/hw/char/shakti_uart.c
19
@@ -XXX,XX +XXX,XX @@ static void shakti_uart_class_init(ObjectClass *klass, void *data)
20
dc->reset = shakti_uart_reset;
21
dc->realize = shakti_uart_realize;
22
device_class_set_props(dc, shakti_uart_properties);
23
+ set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
24
}
25
26
static const TypeInfo shakti_uart_info = {
27
--
28
2.31.1
29
30
diff view generated by jsdifflib
[PULL 20/26] hw/char: sifive_uart: Register device in 'input' category
Deleted patch
1
From: Bin Meng <bmeng.cn@gmail.com>
2
1
3
The category of sifive_uart device is not set. Put it into the
4
'input' category.
5
6
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20210926105003.2716-3-bmeng.cn@gmail.com
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
hw/char/sifive_uart.c | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/char/sifive_uart.c
18
+++ b/hw/char/sifive_uart.c
19
@@ -XXX,XX +XXX,XX @@ static void sifive_uart_class_init(ObjectClass *oc, void *data)
20
rc->phases.enter = sifive_uart_reset_enter;
21
rc->phases.hold = sifive_uart_reset_hold;
22
device_class_set_props(dc, sifive_uart_properties);
23
+ set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
24
}
25
26
static const TypeInfo sifive_uart_info = {
27
--
28
2.31.1
29
30
diff view generated by jsdifflib
[PULL 21/26] hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition
[PULL 2/2] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
The current MCHP_PFSOC_MMUART_REG_SIZE definition represent the
3
Once a "One Time Programmable" is programmed, it shouldn't be reset.
4
size occupied by all the registers. However all registers are
5
32-bit wide, and the MemoryRegionOps handlers are restricted to
6
32-bit:
7
4
8
static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
5
Do not re-initialize the OTP content in the DeviceReset handler,
9
.read = mchp_pfsoc_mmuart_read,
6
initialize it once in the DeviceRealize one.
10
.write = mchp_pfsoc_mmuart_write,
11
.impl = {
12
.min_access_size = 4,
13
.max_access_size = 4,
14
},
15
7
16
Avoid being triskaidekaphobic, simplify by using the number of
8
Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
17
registers.
18
19
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Reviewed-by: Bin Meng <bin.meng@windriver.com>
21
Tested-by: Bin Meng <bin.meng@windriver.com>
22
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
23
Message-id: 20210925133407.1259392-2-f4bug@amsat.org
11
Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
25
---
13
---
26
include/hw/char/mchp_pfsoc_mmuart.h | 4 ++--
14
hw/misc/sifive_u_otp.c | 13 +++++--------
27
hw/char/mchp_pfsoc_mmuart.c | 14 ++++++++------
15
1 file changed, 5 insertions(+), 8 deletions(-)
28
2 files changed, 10 insertions(+), 8 deletions(-)
29
16
30
diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
17
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
31
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
32
--- a/include/hw/char/mchp_pfsoc_mmuart.h
19
--- a/hw/misc/sifive_u_otp.c
33
+++ b/include/hw/char/mchp_pfsoc_mmuart.h
20
+++ b/hw/misc/sifive_u_otp.c
34
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
35
22
36
#include "hw/char/serial.h"
23
if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
37
24
error_setg(errp, "failed to read the initial flash content");
38
-#define MCHP_PFSOC_MMUART_REG_SIZE 52
25
+ return;
39
+#define MCHP_PFSOC_MMUART_REG_COUNT 13
26
}
40
27
}
41
typedef struct MchpPfSoCMMUartState {
42
MemoryRegion iomem;
43
@@ -XXX,XX +XXX,XX @@ typedef struct MchpPfSoCMMUartState {
44
45
SerialMM *serial;
46
47
- uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
48
+ uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT];
49
} MchpPfSoCMMUartState;
50
51
/**
52
diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/char/mchp_pfsoc_mmuart.c
55
+++ b/hw/char/mchp_pfsoc_mmuart.c
56
@@ -XXX,XX +XXX,XX @@ static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
57
{
58
MchpPfSoCMMUartState *s = opaque;
59
60
- if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
61
+ addr >>= 2;
62
+ if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
63
qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
64
- __func__, addr);
65
+ __func__, addr << 2);
66
return 0;
67
}
28
}
68
29
-}
69
- return s->reg[addr / sizeof(uint32_t)];
30
-
70
+ return s->reg[addr];
31
-static void sifive_u_otp_reset(DeviceState *dev)
32
-{
33
- SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
34
35
/* Initialize all fuses' initial value to 0xFFs */
36
memset(s->fuse, 0xff, sizeof(s->fuse));
37
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
38
serial_data = s->serial;
39
if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
40
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
41
- error_report("write error index<%d>", index);
42
+ error_setg(errp, "failed to write index<%d>", index);
43
+ return;
44
}
45
46
serial_data = ~(s->serial);
47
if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
48
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
49
- error_report("write error index<%d>", index + 1);
50
+ error_setg(errp, "failed to write index<%d>", index + 1);
51
+ return;
52
}
53
}
54
55
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
56
57
device_class_set_props(dc, sifive_u_otp_properties);
58
dc->realize = sifive_u_otp_realize;
59
- dc->reset = sifive_u_otp_reset;
71
}
60
}
72
61
73
static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
62
static const TypeInfo sifive_u_otp_info = {
74
@@ -XXX,XX +XXX,XX @@ static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
75
MchpPfSoCMMUartState *s = opaque;
76
uint32_t val32 = (uint32_t)value;
77
78
- if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
79
+ addr >>= 2;
80
+ if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
81
qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
82
- " v=0x%x\n", __func__, addr, val32);
83
+ " v=0x%x\n", __func__, addr << 2, val32);
84
return;
85
}
86
87
- s->reg[addr / sizeof(uint32_t)] = val32;
88
+ s->reg[addr] = val32;
89
}
90
91
static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
92
--
63
--
93
2.31.1
64
2.31.1
94
65
95
66
diff view generated by jsdifflib
[PULL 22/26] hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Our device have 2 different I/O regions:
4
- a 16550 UART mapped for 32-bit accesses
5
- 13 extra registers
6
7
Instead of mapping each region on the main bus, introduce
8
a container, map the 2 devices regions on the container,
9
and map the container on the main bus.
10
11
Before:
12
13
(qemu) info mtree
14
...
15
0000000020100000-000000002010001f (prio 0, i/o): serial
16
0000000020100020-000000002010101f (prio 0, i/o): mchp.pfsoc.mmuart
17
0000000020102000-000000002010201f (prio 0, i/o): serial
18
0000000020102020-000000002010301f (prio 0, i/o): mchp.pfsoc.mmuart
19
0000000020104000-000000002010401f (prio 0, i/o): serial
20
0000000020104020-000000002010501f (prio 0, i/o): mchp.pfsoc.mmuart
21
0000000020106000-000000002010601f (prio 0, i/o): serial
22
0000000020106020-000000002010701f (prio 0, i/o): mchp.pfsoc.mmuart
23
24
After:
25
26
(qemu) info mtree
27
...
28
0000000020100000-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart
29
0000000020100000-000000002010001f (prio 0, i/o): serial
30
0000000020100020-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
31
0000000020102000-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart
32
0000000020102000-000000002010201f (prio 0, i/o): serial
33
0000000020102020-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
34
0000000020104000-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart
35
0000000020104000-000000002010401f (prio 0, i/o): serial
36
0000000020104020-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
37
0000000020106000-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart
38
0000000020106000-000000002010601f (prio 0, i/o): serial
39
0000000020106020-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
40
41
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
42
Reviewed-by: Bin Meng <bin.meng@windriver.com>
43
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
44
Tested-by: Bin Meng <bin.meng@windriver.com>
45
Message-id: 20210925133407.1259392-3-f4bug@amsat.org
46
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
47
---
48
include/hw/char/mchp_pfsoc_mmuart.h | 1 +
49
hw/char/mchp_pfsoc_mmuart.c | 11 ++++++++---
50
2 files changed, 9 insertions(+), 3 deletions(-)
51
52
diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/include/hw/char/mchp_pfsoc_mmuart.h
55
+++ b/include/hw/char/mchp_pfsoc_mmuart.h
56
@@ -XXX,XX +XXX,XX @@
57
#define MCHP_PFSOC_MMUART_REG_COUNT 13
58
59
typedef struct MchpPfSoCMMUartState {
60
+ MemoryRegion container;
61
MemoryRegion iomem;
62
hwaddr base;
63
qemu_irq irq;
64
diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/hw/char/mchp_pfsoc_mmuart.c
67
+++ b/hw/char/mchp_pfsoc_mmuart.c
68
@@ -XXX,XX +XXX,XX @@
69
#include "chardev/char.h"
70
#include "hw/char/mchp_pfsoc_mmuart.h"
71
72
+#define REGS_OFFSET 0x20
73
+
74
static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
75
{
76
MchpPfSoCMMUartState *s = opaque;
77
@@ -XXX,XX +XXX,XX @@ MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
78
79
s = g_new0(MchpPfSoCMMUartState, 1);
80
81
+ memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000);
82
+
83
memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
84
- "mchp.pfsoc.mmuart", 0x1000);
85
+ "mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET);
86
+ memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem);
87
88
s->base = base;
89
s->irq = irq;
90
91
- s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
92
+ s->serial = serial_mm_init(&s->container, 0, 2, irq, 399193, chr,
93
DEVICE_LITTLE_ENDIAN);
94
95
- memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
96
+ memory_region_add_subregion(sysmem, base, &s->container);
97
98
return s;
99
}
100
--
101
2.31.1
102
103
diff view generated by jsdifflib
[PULL 23/26] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
- Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it
4
- Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART
5
- Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize()
6
- Add DeviceReset() method
7
- Add vmstate structure for migration
8
- Register device in 'input' category
9
- Keep mchp_pfsoc_mmuart_create() behavior
10
11
Note, serial_mm_init() calls qdev_set_legacy_instance_id().
12
This call is only needed for backwards-compatibility of incoming
13
migration data with old versions of QEMU which implemented migration
14
of devices with hand-rolled code. Since this device didn't previously
15
handle migration at all, then it doesn't need to set the legacy
16
instance ID.
17
18
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Reviewed-by: Bin Meng <bin.meng@windriver.com>
20
Tested-by: Bin Meng <bin.meng@windriver.com>
21
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
22
Message-id: 20210925133407.1259392-4-f4bug@amsat.org
23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
---
25
include/hw/char/mchp_pfsoc_mmuart.h | 12 +++-
26
hw/char/mchp_pfsoc_mmuart.c | 97 +++++++++++++++++++++++++----
27
2 files changed, 93 insertions(+), 16 deletions(-)
28
29
diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/include/hw/char/mchp_pfsoc_mmuart.h
32
+++ b/include/hw/char/mchp_pfsoc_mmuart.h
33
@@ -XXX,XX +XXX,XX @@
34
#ifndef HW_MCHP_PFSOC_MMUART_H
35
#define HW_MCHP_PFSOC_MMUART_H
36
37
+#include "hw/sysbus.h"
38
#include "hw/char/serial.h"
39
40
#define MCHP_PFSOC_MMUART_REG_COUNT 13
41
42
+#define TYPE_MCHP_PFSOC_UART "mchp.pfsoc.uart"
43
+OBJECT_DECLARE_SIMPLE_TYPE(MchpPfSoCMMUartState, MCHP_PFSOC_UART)
44
+
45
typedef struct MchpPfSoCMMUartState {
46
+ /*< private >*/
47
+ SysBusDevice parent_obj;
48
+
49
+ /*< public >*/
50
MemoryRegion container;
51
MemoryRegion iomem;
52
- hwaddr base;
53
- qemu_irq irq;
54
55
- SerialMM *serial;
56
+ SerialMM serial_mm;
57
58
uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT];
59
} MchpPfSoCMMUartState;
60
diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/char/mchp_pfsoc_mmuart.c
63
+++ b/hw/char/mchp_pfsoc_mmuart.c
64
@@ -XXX,XX +XXX,XX @@
65
66
#include "qemu/osdep.h"
67
#include "qemu/log.h"
68
-#include "chardev/char.h"
69
+#include "qapi/error.h"
70
+#include "migration/vmstate.h"
71
#include "hw/char/mchp_pfsoc_mmuart.h"
72
+#include "hw/qdev-properties.h"
73
74
#define REGS_OFFSET 0x20
75
76
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
77
},
78
};
79
80
-MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
81
- hwaddr base, qemu_irq irq, Chardev *chr)
82
+static void mchp_pfsoc_mmuart_reset(DeviceState *dev)
83
+{
84
+ MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev);
85
+
86
+ memset(s->reg, 0, sizeof(s->reg));
87
+ device_cold_reset(DEVICE(&s->serial_mm));
88
+}
89
+
90
+static void mchp_pfsoc_mmuart_init(Object *obj)
91
{
92
- MchpPfSoCMMUartState *s;
93
+ MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(obj);
94
95
- s = g_new0(MchpPfSoCMMUartState, 1);
96
+ object_initialize_child(obj, "serial-mm", &s->serial_mm, TYPE_SERIAL_MM);
97
+ object_property_add_alias(obj, "chardev", OBJECT(&s->serial_mm), "chardev");
98
+}
99
100
- memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000);
101
+static void mchp_pfsoc_mmuart_realize(DeviceState *dev, Error **errp)
102
+{
103
+ MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev);
104
105
- memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
106
+ qdev_prop_set_uint8(DEVICE(&s->serial_mm), "regshift", 2);
107
+ qdev_prop_set_uint32(DEVICE(&s->serial_mm), "baudbase", 399193);
108
+ qdev_prop_set_uint8(DEVICE(&s->serial_mm), "endianness",
109
+ DEVICE_LITTLE_ENDIAN);
110
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->serial_mm), errp)) {
111
+ return;
112
+ }
113
+
114
+ sysbus_pass_irq(SYS_BUS_DEVICE(dev), SYS_BUS_DEVICE(&s->serial_mm));
115
+
116
+ memory_region_init(&s->container, OBJECT(s), "mchp.pfsoc.mmuart", 0x1000);
117
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
118
+
119
+ memory_region_add_subregion(&s->container, 0,
120
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial_mm), 0));
121
+
122
+ memory_region_init_io(&s->iomem, OBJECT(s), &mchp_pfsoc_mmuart_ops, s,
123
"mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET);
124
memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem);
125
+}
126
127
- s->base = base;
128
- s->irq = irq;
129
+static const VMStateDescription mchp_pfsoc_mmuart_vmstate = {
130
+ .name = "mchp.pfsoc.uart",
131
+ .version_id = 0,
132
+ .minimum_version_id = 0,
133
+ .fields = (VMStateField[]) {
134
+ VMSTATE_UINT32_ARRAY(reg, MchpPfSoCMMUartState,
135
+ MCHP_PFSOC_MMUART_REG_COUNT),
136
+ VMSTATE_END_OF_LIST()
137
+ }
138
+};
139
+
140
+static void mchp_pfsoc_mmuart_class_init(ObjectClass *oc, void *data)
141
+{
142
+ DeviceClass *dc = DEVICE_CLASS(oc);
143
+
144
+ dc->realize = mchp_pfsoc_mmuart_realize;
145
+ dc->reset = mchp_pfsoc_mmuart_reset;
146
+ dc->vmsd = &mchp_pfsoc_mmuart_vmstate;
147
+ set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
148
+}
149
+
150
+static const TypeInfo mchp_pfsoc_mmuart_info = {
151
+ .name = TYPE_MCHP_PFSOC_UART,
152
+ .parent = TYPE_SYS_BUS_DEVICE,
153
+ .instance_size = sizeof(MchpPfSoCMMUartState),
154
+ .instance_init = mchp_pfsoc_mmuart_init,
155
+ .class_init = mchp_pfsoc_mmuart_class_init,
156
+};
157
+
158
+static void mchp_pfsoc_mmuart_register_types(void)
159
+{
160
+ type_register_static(&mchp_pfsoc_mmuart_info);
161
+}
162
+
163
+type_init(mchp_pfsoc_mmuart_register_types)
164
+
165
+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
166
+ hwaddr base,
167
+ qemu_irq irq, Chardev *chr)
168
+{
169
+ DeviceState *dev = qdev_new(TYPE_MCHP_PFSOC_UART);
170
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
171
172
- s->serial = serial_mm_init(&s->container, 0, 2, irq, 399193, chr,
173
- DEVICE_LITTLE_ENDIAN);
174
+ qdev_prop_set_chr(dev, "chardev", chr);
175
+ sysbus_realize(sbd, &error_fatal);
176
177
- memory_region_add_subregion(sysmem, base, &s->container);
178
+ memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(sbd, 0));
179
+ sysbus_connect_irq(sbd, 0, irq);
180
181
- return s;
182
+ return MCHP_PFSOC_UART(dev);
183
}
184
--
185
2.31.1
186
187
diff view generated by jsdifflib
[PULL 24/26] hw/dma: sifive_pdma: Fix Control.claim bit detection
Deleted patch
1
From: Bin Meng <bmeng.cn@gmail.com>
2
1
3
At present the codes detect whether the DMA channel is claimed by:
4
5
claimed = !!s->chan[ch].control & CONTROL_CLAIM;
6
7
As ! has higher precedence over & (bitwise and), this is essentially
8
9
claimed = (!!s->chan[ch].control) & CONTROL_CLAIM;
10
11
which is wrong, as any non-zero bit set in the control register will
12
produce a result of a claimed channel.
13
14
Fixes: de7c7988d25d ("hw/dma: sifive_pdma: reset Next* registers when Control.claim is set")
15
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20210927072124.1564129-1-bmeng.cn@gmail.com
18
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
---
20
hw/dma/sifive_pdma.c | 2 +-
21
1 file changed, 1 insertion(+), 1 deletion(-)
22
23
diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/dma/sifive_pdma.c
26
+++ b/hw/dma/sifive_pdma.c
27
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
28
offset &= 0xfff;
29
switch (offset) {
30
case DMA_CONTROL:
31
- claimed = !!s->chan[ch].control & CONTROL_CLAIM;
32
+ claimed = !!(s->chan[ch].control & CONTROL_CLAIM);
33
34
if (!claimed && (value & CONTROL_CLAIM)) {
35
/* reset Next* registers */
36
--
37
2.31.1
38
39
diff view generated by jsdifflib
[PULL 25/26] hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed
Deleted patch
1
From: Bin Meng <bmeng.cn@gmail.com>
2
1
3
If Control.run bit is set while not preserving the Control.claim
4
bit, the DMA transfer shall not be started.
5
6
The following result is PDMA tested in U-Boot on Unleashed board:
7
8
=> mw.l 0x3000000 0x0 <= Disclaim channel 0
9
=> mw.l 0x3000000 0x1 <= Claim channel 0
10
=> mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32 bytes)
11
=> mw.q 0x3000008 0x2 <= NextBytes = 2
12
=> mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000
13
=> mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000
14
=> mw.l 0x84000000 0x87654321 <= Fill test data to dst
15
=> mw.l 0x84001000 0x12345678 <= Fill test data to src
16
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
17
84000000: 87654321 !Ce.
18
84001000: 12345678 xV4.
19
=> md.l 0x3000000 8 <= Dump PDMA status
20
03000000: 00000001 55000000 00000002 00000000 .......U........
21
03000010: 84000000 00000000 84001000 00000000 ................
22
=> mw.l 0x3000000 0x2 <= Set channel 0 run bit only
23
=> md.l 0x3000000 8 <= Dump PDMA status
24
03000000: 00000000 55000000 00000002 00000000 .......U........
25
03000010: 84000000 00000000 84001000 00000000 ................
26
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
27
84000000: 87654321 !Ce.
28
84001000: 12345678 xV4.
29
30
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
31
Acked-by: Alistair Francis <alistair.francis@wdc.com>
32
Message-id: 20210927072124.1564129-2-bmeng.cn@gmail.com
33
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
34
---
35
hw/dma/sifive_pdma.c | 11 +++++++++--
36
1 file changed, 9 insertions(+), 2 deletions(-)
37
38
diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/dma/sifive_pdma.c
41
+++ b/hw/dma/sifive_pdma.c
42
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
43
{
44
SiFivePDMAState *s = opaque;
45
int ch = SIFIVE_PDMA_CHAN_NO(offset);
46
- bool claimed;
47
+ bool claimed, run;
48
49
if (ch >= SIFIVE_PDMA_CHANS) {
50
qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
51
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
52
switch (offset) {
53
case DMA_CONTROL:
54
claimed = !!(s->chan[ch].control & CONTROL_CLAIM);
55
+ run = !!(s->chan[ch].control & CONTROL_RUN);
56
57
if (!claimed && (value & CONTROL_CLAIM)) {
58
/* reset Next* registers */
59
@@ -XXX,XX +XXX,XX @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
60
s->chan[ch].next_src = 0;
61
}
62
63
+ /* claim bit can only be cleared when run is low */
64
+ if (run && !(value & CONTROL_CLAIM)) {
65
+ value |= CONTROL_CLAIM;
66
+ }
67
+
68
s->chan[ch].control = value;
69
70
/*
71
* If channel was not claimed before run bit is set,
72
+ * or if the channel is disclaimed when run was low,
73
* DMA won't run.
74
*/
75
- if (!claimed) {
76
+ if (!claimed || (!run && !(value & CONTROL_CLAIM))) {
77
s->chan[ch].control &= ~CONTROL_RUN;
78
return;
79
}
80
--
81
2.31.1
82
83
diff view generated by jsdifflib
[PULL 26/26] hw/riscv: shakti_c: Mark as not user creatable
Deleted patch
1
From: Alistair Francis <alistair.francis@wdc.com>
2
1
3
Mark the shakti_c machine as not user creatable.
4
5
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/639
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-Id: <c617a04d4e3dd041a3427b47a1b1d5ab475a2edd.1632871759.git.alistair.francis@wdc.com>
11
---
12
hw/riscv/shakti_c.c | 7 +++++++
13
1 file changed, 7 insertions(+)
14
15
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/shakti_c.c
18
+++ b/hw/riscv/shakti_c.c
19
@@ -XXX,XX +XXX,XX @@ static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
20
{
21
DeviceClass *dc = DEVICE_CLASS(klass);
22
dc->realize = shakti_c_soc_state_realize;
23
+ /*
24
+ * Reasons:
25
+ * - Creates CPUS in riscv_hart_realize(), and can create unintended
26
+ * CPUs
27
+ * - Uses serial_hds in realize function, thus can't be used twice
28
+ */
29
+ dc->user_creatable = false;
30
}
31
32
static void shakti_c_soc_instance_init(Object *obj)
33
--
34
2.31.1
35
36
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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