[PULL 00/22] target-arm queue
[PULL 00/14] target-arm queue
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Nothing too exciting in this lot :-)
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The following changes since commit 8f6330a807f2642dc2a3cdf33347aa28a4c00a87:
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The following changes since commit ba0fa56bc06e563de68d2a2bf3ddb0cfea1be4f9:
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Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-06 16:56:20 +0000)
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Merge remote-tracking branch 'remotes/vivier/tags/q800-for-6.2-pull-request' into staging (2021-09-29 21:20:49 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210930
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240308
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8
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for you to fetch changes up to 1f4b2ec701b9d73d3fa7bb90c8b4376bc7d3c42b:
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for you to fetch changes up to bbf6c6dbead82292a20951eb1204442a6b838de9:
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hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19 (2021-09-30 13:44:13 +0100)
11
target/arm: Move v7m-related code from cpu32.c into a separate file (2024-03-08 14:45:03 +0000)
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15
----------------------------------------------------------------
13
----------------------------------------------------------------
16
target-arm queue:
14
target-arm queue:
17
* allwinner-h3: Switch to SMC as PSCI conduit
15
* Implement FEAT_ECV
18
* arm: tcg: Adhere to SMCCC 1.3 section 5.2
16
* STM32L4x5: Implement GPIO device
19
* xlnx-zcu102, xlnx-versal-virt: Support BBRAM and eFUSE devices
17
* Fix 32-bit SMOPA
20
* gdbstub related code cleanups
18
* Refactor v7m related code from cpu32.c into its own file
21
* Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML
19
* hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
22
* Use _init vs _new convention in bus creation function names
23
* sabrelite: Connect SPI flash CS line to GPIO3_19
24
20
25
----------------------------------------------------------------
21
----------------------------------------------------------------
26
Alexander Graf (2):
22
Inès Varhol (3):
27
allwinner-h3: Switch to SMC as PSCI conduit
23
hw/gpio: Implement STM32L4x5 GPIO
28
arm: tcg: Adhere to SMCCC 1.3 section 5.2
24
hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
25
tests/qtest: Add STM32L4x5 GPIO QTest testcase
29
26
30
Peter Maydell (10):
27
Peter Maydell (9):
31
configs: Don't include 32-bit-only GDB XML in aarch64 linux configs
28
target/arm: Move some register related defines to internals.h
32
target/arm: Fix coding style issues in gdbstub code in helper.c
29
target/arm: Timer _EL02 registers UNDEF for E2H == 0
33
target/arm: Move gdbstub related code out of helper.c
30
target/arm: use FIELD macro for CNTHCTL bit definitions
34
target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML
31
target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written
35
scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named()
32
target/arm: Implement new FEAT_ECV trap bits
36
ipack: Rename ipack_bus_new_inplace() to ipack_bus_init()
33
target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
37
pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init()
34
target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
38
qbus: Rename qbus_create_inplace() to qbus_init()
35
target/arm: Enable FEAT_ECV for 'max' CPU
39
qbus: Rename qbus_create() to qbus_new()
36
hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
40
ide: Rename ide_bus_new() to ide_bus_init()
41
37
42
Tong Ho (9):
38
Richard Henderson (1):
43
hw/nvram: Introduce Xilinx eFuse QOM
39
target/arm: Fix 32-bit SMOPA
44
hw/nvram: Introduce Xilinx Versal eFuse device
45
hw/nvram: Introduce Xilinx ZynqMP eFuse device
46
hw/nvram: Introduce Xilinx battery-backed ram
47
hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device
48
hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device
49
hw/arm: xlnx-zcu102: Add Xilinx BBRAM device
50
hw/arm: xlnx-zcu102: Add Xilinx eFUSE device
51
docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage
52
40
53
Xuzhou Cheng (1):
41
Thomas Huth (1):
54
hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19
42
target/arm: Move v7m-related code from cpu32.c into a separate file
55
43
56
docs/system/arm/xlnx-versal-virt.rst | 49 ++
44
MAINTAINERS | 1 +
57
configs/targets/aarch64-linux-user.mak | 2 +-
45
docs/system/arm/b-l475e-iot01a.rst | 2 +-
58
configs/targets/aarch64-softmmu.mak | 2 +-
46
docs/system/arm/emulation.rst | 1 +
59
configs/targets/aarch64_be-linux-user.mak | 2 +-
47
include/hw/arm/stm32l4x5_soc.h | 2 +
60
configs/targets/arm-linux-user.mak | 2 +-
48
include/hw/gpio/stm32l4x5_gpio.h | 71 +++++
61
configs/targets/arm-softmmu.mak | 2 +-
49
include/hw/misc/stm32l4x5_syscfg.h | 3 +-
62
configs/targets/armeb-linux-user.mak | 2 +-
50
include/hw/rtc/sun4v-rtc.h | 2 +-
63
include/hw/arm/xlnx-versal.h | 15 +
51
target/arm/cpu-features.h | 10 +
64
include/hw/arm/xlnx-zynqmp.h | 5 +
52
target/arm/cpu.h | 129 +--------
65
include/hw/ide/internal.h | 4 +-
53
target/arm/internals.h | 151 ++++++++++
66
include/hw/ipack/ipack.h | 8 +-
54
hw/arm/stm32l4x5_soc.c | 71 ++++-
67
include/hw/nvram/xlnx-bbram.h | 54 ++
55
hw/gpio/stm32l4x5_gpio.c | 477 ++++++++++++++++++++++++++++++++
68
include/hw/nvram/xlnx-efuse.h | 132 +++++
56
hw/misc/stm32l4x5_syscfg.c | 1 +
69
include/hw/nvram/xlnx-versal-efuse.h | 68 +++
57
hw/rtc/sun4v-rtc.c | 2 +-
70
include/hw/nvram/xlnx-zynqmp-efuse.h | 44 ++
58
target/arm/helper.c | 189 ++++++++++++-
71
include/hw/pci/pci.h | 10 +-
59
target/arm/tcg/cpu-v7m.c | 290 +++++++++++++++++++
72
include/hw/qdev-core.h | 6 +-
60
target/arm/tcg/cpu32.c | 261 ------------------
73
include/hw/scsi/scsi.h | 30 +-
61
target/arm/tcg/cpu64.c | 1 +
74
target/arm/internals.h | 7 +
62
target/arm/tcg/sme_helper.c | 77 +++---
75
hw/arm/allwinner-h3.c | 2 +-
63
tests/qtest/stm32l4x5_gpio-test.c | 551 +++++++++++++++++++++++++++++++++++++
76
hw/arm/sabrelite.c | 2 +-
64
tests/tcg/aarch64/sme-smopa-1.c | 47 ++++
77
hw/arm/xlnx-versal-virt.c | 88 +++
65
tests/tcg/aarch64/sme-smopa-2.c | 54 ++++
78
hw/arm/xlnx-versal.c | 57 ++
66
hw/arm/Kconfig | 3 +-
79
hw/arm/xlnx-zcu102.c | 30 ++
67
hw/gpio/Kconfig | 3 +
80
hw/arm/xlnx-zynqmp.c | 49 ++
68
hw/gpio/meson.build | 1 +
81
hw/audio/intel-hda.c | 2 +-
69
hw/gpio/trace-events | 6 +
82
hw/block/fdc.c | 2 +-
70
target/arm/meson.build | 3 +
83
hw/block/swim.c | 3 +-
71
target/arm/tcg/meson.build | 3 +
84
hw/char/virtio-serial-bus.c | 4 +-
72
target/arm/trace-events | 1 +
85
hw/core/bus.c | 13 +-
73
tests/qtest/meson.build | 3 +-
86
hw/core/sysbus.c | 10 +-
74
tests/tcg/aarch64/Makefile.target | 2 +-
87
hw/gpio/bcm2835_gpio.c | 3 +-
75
31 files changed, 1962 insertions(+), 456 deletions(-)
88
hw/hyperv/vmbus.c | 2 +-
76
create mode 100644 include/hw/gpio/stm32l4x5_gpio.h
89
hw/i2c/core.c | 2 +-
77
create mode 100644 hw/gpio/stm32l4x5_gpio.c
90
hw/ide/ahci.c | 2 +-
78
create mode 100644 target/arm/tcg/cpu-v7m.c
91
hw/ide/cmd646.c | 2 +-
79
create mode 100644 tests/qtest/stm32l4x5_gpio-test.c
92
hw/ide/isa.c | 2 +-
80
create mode 100644 tests/tcg/aarch64/sme-smopa-1.c
93
hw/ide/macio.c | 2 +-
81
create mode 100644 tests/tcg/aarch64/sme-smopa-2.c
94
hw/ide/microdrive.c | 2 +-
95
hw/ide/mmio.c | 2 +-
96
hw/ide/piix.c | 2 +-
97
hw/ide/qdev.c | 4 +-
98
hw/ide/sii3112.c | 2 +-
99
hw/ide/via.c | 2 +-
100
hw/ipack/ipack.c | 10 +-
101
hw/ipack/tpci200.c | 4 +-
102
hw/isa/isa-bus.c | 2 +-
103
hw/misc/auxbus.c | 2 +-
104
hw/misc/mac_via.c | 4 +-
105
hw/misc/macio/cuda.c | 4 +-
106
hw/misc/macio/macio.c | 4 +-
107
hw/misc/macio/pmu.c | 4 +-
108
hw/nubus/nubus-bridge.c | 2 +-
109
hw/nvme/ctrl.c | 4 +-
110
hw/nvme/subsys.c | 3 +-
111
hw/nvram/xlnx-bbram.c | 545 +++++++++++++++++++
112
hw/nvram/xlnx-efuse-crc.c | 119 +++++
113
hw/nvram/xlnx-efuse.c | 280 ++++++++++
114
hw/nvram/xlnx-versal-efuse-cache.c | 114 ++++
115
hw/nvram/xlnx-versal-efuse-ctrl.c | 783 +++++++++++++++++++++++++++
116
hw/nvram/xlnx-zynqmp-efuse.c | 855 ++++++++++++++++++++++++++++++
117
hw/pci-host/raven.c | 4 +-
118
hw/pci-host/versatile.c | 6 +-
119
hw/pci/pci.c | 30 +-
120
hw/pci/pci_bridge.c | 4 +-
121
hw/ppc/spapr_vio.c | 2 +-
122
hw/s390x/ap-bridge.c | 2 +-
123
hw/s390x/css-bridge.c | 2 +-
124
hw/s390x/event-facility.c | 4 +-
125
hw/s390x/s390-pci-bus.c | 2 +-
126
hw/s390x/virtio-ccw.c | 3 +-
127
hw/scsi/esp-pci.c | 2 +-
128
hw/scsi/esp.c | 2 +-
129
hw/scsi/lsi53c895a.c | 2 +-
130
hw/scsi/megasas.c | 3 +-
131
hw/scsi/mptsas.c | 2 +-
132
hw/scsi/scsi-bus.c | 6 +-
133
hw/scsi/spapr_vscsi.c | 3 +-
134
hw/scsi/virtio-scsi.c | 4 +-
135
hw/scsi/vmw_pvscsi.c | 3 +-
136
hw/sd/allwinner-sdhost.c | 4 +-
137
hw/sd/bcm2835_sdhost.c | 4 +-
138
hw/sd/pl181.c | 3 +-
139
hw/sd/pxa2xx_mmci.c | 4 +-
140
hw/sd/sdhci.c | 3 +-
141
hw/sd/ssi-sd.c | 3 +-
142
hw/ssi/ssi.c | 2 +-
143
hw/usb/bus.c | 2 +-
144
hw/usb/dev-smartcard-reader.c | 3 +-
145
hw/usb/dev-storage-bot.c | 3 +-
146
hw/usb/dev-storage-classic.c | 4 +-
147
hw/usb/dev-uas.c | 3 +-
148
hw/virtio/virtio-mmio.c | 3 +-
149
hw/virtio/virtio-pci.c | 3 +-
150
hw/xen/xen-bus.c | 2 +-
151
hw/xen/xen-legacy-backend.c | 2 +-
152
target/arm/gdbstub.c | 154 ++++++
153
target/arm/gdbstub64.c | 140 +++++
154
target/arm/helper.c | 262 ---------
155
target/arm/psci.c | 35 +-
156
gdb-xml/arm-neon.xml | 2 -
157
gdb-xml/arm-vfp-sysregs.xml | 17 +
158
gdb-xml/arm-vfp.xml | 2 -
159
gdb-xml/arm-vfp3.xml | 2 -
160
hw/Kconfig | 2 +
161
hw/arm/Kconfig | 2 +
162
hw/nvram/Kconfig | 19 +
163
hw/nvram/meson.build | 8 +
164
108 files changed, 3806 insertions(+), 447 deletions(-)
165
create mode 100644 include/hw/nvram/xlnx-bbram.h
166
create mode 100644 include/hw/nvram/xlnx-efuse.h
167
create mode 100644 include/hw/nvram/xlnx-versal-efuse.h
168
create mode 100644 include/hw/nvram/xlnx-zynqmp-efuse.h
169
create mode 100644 hw/nvram/xlnx-bbram.c
170
create mode 100644 hw/nvram/xlnx-efuse-crc.c
171
create mode 100644 hw/nvram/xlnx-efuse.c
172
create mode 100644 hw/nvram/xlnx-versal-efuse-cache.c
173
create mode 100644 hw/nvram/xlnx-versal-efuse-ctrl.c
174
create mode 100644 hw/nvram/xlnx-zynqmp-efuse.c
175
create mode 100644 gdb-xml/arm-vfp-sysregs.xml
176
82
diff view generated by jsdifflib
[PULL 01/22] allwinner-h3: Switch to SMC as PSCI conduit
Deleted patch
1
From: Alexander Graf <agraf@csgraf.de>
2
1
3
The Allwinner H3 SoC uses Cortex-A7 cores which support virtualization.
4
However, today we are configuring QEMU to use HVC as PSCI conduit.
5
6
That means HVC calls get trapped into QEMU instead of the guest's own
7
emulated CPU and thus break the guest's ability to execute virtualization.
8
9
Fix this by moving to SMC as conduit, freeing up HYP completely to the VM.
10
11
Signed-off-by: Alexander Graf <agraf@csgraf.de>
12
Message-id: 20210920203931.66527-1-agraf@csgraf.de
13
Fixes: 740dafc0ba0 ("hw/arm: add Allwinner H3 System-on-Chip")
14
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
15
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
hw/arm/allwinner-h3.c | 2 +-
21
1 file changed, 1 insertion(+), 1 deletion(-)
22
23
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/allwinner-h3.c
26
+++ b/hw/arm/allwinner-h3.c
27
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
28
29
/* Provide Power State Coordination Interface */
30
qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
31
- QEMU_PSCI_CONDUIT_HVC);
32
+ QEMU_PSCI_CONDUIT_SMC);
33
34
/* Disable secondary CPUs */
35
qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
[PULL 02/22] arm: tcg: Adhere to SMCCC 1.3 section 5.2
Deleted patch
1
From: Alexander Graf <agraf@csgraf.de>
2
1
3
The SMCCC 1.3 spec section 5.2 says
4
5
The Unknown SMC Function Identifier is a sign-extended value of (-1)
6
that is returned in the R0, W0 or X0 registers. An implementation must
7
return this error code when it receives:
8
9
* An SMC or HVC call with an unknown Function Identifier
10
* An SMC or HVC call for a removed Function Identifier
11
* An SMC64/HVC64 call from AArch32 state
12
13
To comply with these statements, let's always return -1 when we encounter
14
an unknown HVC or SMC call.
15
16
Signed-off-by: Alexander Graf <agraf@csgraf.de>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
target/arm/psci.c | 35 ++++++-----------------------------
21
1 file changed, 6 insertions(+), 29 deletions(-)
22
23
diff --git a/target/arm/psci.c b/target/arm/psci.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/psci.c
26
+++ b/target/arm/psci.c
27
@@ -XXX,XX +XXX,XX @@
28
29
bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
30
{
31
- /* Return true if the r0/x0 value indicates a PSCI call and
32
- * the exception type matches the configured PSCI conduit. This is
33
- * called before the SMC/HVC instruction is executed, to decide whether
34
- * we should treat it as a PSCI call or with the architecturally
35
+ /*
36
+ * Return true if the exception type matches the configured PSCI conduit.
37
+ * This is called before the SMC/HVC instruction is executed, to decide
38
+ * whether we should treat it as a PSCI call or with the architecturally
39
* defined behaviour for an SMC or HVC (which might be UNDEF or trap
40
* to EL2 or to EL3).
41
*/
42
- CPUARMState *env = &cpu->env;
43
- uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0];
44
45
switch (excp_type) {
46
case EXCP_HVC:
47
@@ -XXX,XX +XXX,XX @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
48
return false;
49
}
50
51
- switch (param) {
52
- case QEMU_PSCI_0_2_FN_PSCI_VERSION:
53
- case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
54
- case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
55
- case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
56
- case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
57
- case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
58
- case QEMU_PSCI_0_1_FN_CPU_ON:
59
- case QEMU_PSCI_0_2_FN_CPU_ON:
60
- case QEMU_PSCI_0_2_FN64_CPU_ON:
61
- case QEMU_PSCI_0_1_FN_CPU_OFF:
62
- case QEMU_PSCI_0_2_FN_CPU_OFF:
63
- case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
64
- case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
65
- case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
66
- case QEMU_PSCI_0_1_FN_MIGRATE:
67
- case QEMU_PSCI_0_2_FN_MIGRATE:
68
- return true;
69
- default:
70
- return false;
71
- }
72
+ return true;
73
}
74
75
void arm_handle_psci_call(ARMCPU *cpu)
76
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
77
break;
78
case QEMU_PSCI_0_1_FN_MIGRATE:
79
case QEMU_PSCI_0_2_FN_MIGRATE:
80
+ default:
81
ret = QEMU_PSCI_RET_NOT_SUPPORTED;
82
break;
83
- default:
84
- g_assert_not_reached();
85
}
86
87
err:
88
--
89
2.20.1
90
91
diff view generated by jsdifflib
[PULL 21/22] ide: Rename ide_bus_new() to ide_bus_init()
[PULL 01/14] target/arm: Move some register related defines to internals.h
1
The function ide_bus_new() does an in-place initialization. Rename
1
cpu.h has a lot of #defines relating to CPU register fields.
2
it to ide_bus_init() to follow our _init vs _new convention.
2
Most of these aren't actually used outside target/arm code,
3
so there's no point in cluttering up the cpu.h file with them.
4
Move some easy ones to internals.h.
3
5
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Corey Minyard <cminyard@mvista.com>
9
Message-id: 20240301183219.2424889-2-peter.maydell@linaro.org
8
Reviewed-by: John Snow <jsnow@redhat.com>
9
Acked-by: John Snow <jsnow@redhat.com> (Feel free to merge.)
10
Message-id: 20210923121153.23754-7-peter.maydell@linaro.org
11
---
10
---
12
include/hw/ide/internal.h | 4 ++--
11
target/arm/cpu.h | 128 -----------------------------------------
13
hw/ide/ahci.c | 2 +-
12
target/arm/internals.h | 128 +++++++++++++++++++++++++++++++++++++++++
14
hw/ide/cmd646.c | 2 +-
13
2 files changed, 128 insertions(+), 128 deletions(-)
15
hw/ide/isa.c | 2 +-
16
hw/ide/macio.c | 2 +-
17
hw/ide/microdrive.c | 2 +-
18
hw/ide/mmio.c | 2 +-
19
hw/ide/piix.c | 2 +-
20
hw/ide/qdev.c | 2 +-
21
hw/ide/sii3112.c | 2 +-
22
hw/ide/via.c | 2 +-
23
11 files changed, 12 insertions(+), 12 deletions(-)
24
14
25
diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
26
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/ide/internal.h
17
--- a/target/arm/cpu.h
28
+++ b/include/hw/ide/internal.h
18
+++ b/target/arm/cpu.h
29
@@ -XXX,XX +XXX,XX @@ void ide_atapi_cmd(IDEState *s);
19
@@ -XXX,XX +XXX,XX @@ typedef struct ARMGenericTimer {
30
void ide_atapi_cmd_reply_end(IDEState *s);
20
uint64_t ctl; /* Timer Control register */
31
21
} ARMGenericTimer;
32
/* hw/ide/qdev.c */
22
33
-void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
23
-#define VTCR_NSW (1u << 29)
34
- int bus_id, int max_units);
24
-#define VTCR_NSA (1u << 30)
35
+void ide_bus_init(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
25
-#define VSTCR_SW VTCR_NSW
36
+ int bus_id, int max_units);
26
-#define VSTCR_SA VTCR_NSA
37
IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive);
27
-
38
28
/* Define a maximum sized vector register.
39
int ide_handle_rw_error(IDEState *s, int error, int op);
29
* For 32-bit, this is a 128-bit NEON/AdvSIMD register.
40
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
30
* For 64-bit, this is a 2048-bit SVE register.
31
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
32
#define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
33
#define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */
34
35
-/* Bit definitions for CPACR (AArch32 only) */
36
-FIELD(CPACR, CP10, 20, 2)
37
-FIELD(CPACR, CP11, 22, 2)
38
-FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */
39
-FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */
40
-FIELD(CPACR, ASEDIS, 31, 1)
41
-
42
-/* Bit definitions for CPACR_EL1 (AArch64 only) */
43
-FIELD(CPACR_EL1, ZEN, 16, 2)
44
-FIELD(CPACR_EL1, FPEN, 20, 2)
45
-FIELD(CPACR_EL1, SMEN, 24, 2)
46
-FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */
47
-
48
-/* Bit definitions for HCPTR (AArch32 only) */
49
-FIELD(HCPTR, TCP10, 10, 1)
50
-FIELD(HCPTR, TCP11, 11, 1)
51
-FIELD(HCPTR, TASE, 15, 1)
52
-FIELD(HCPTR, TTA, 20, 1)
53
-FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */
54
-FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */
55
-
56
-/* Bit definitions for CPTR_EL2 (AArch64 only) */
57
-FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */
58
-FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */
59
-FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */
60
-FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */
61
-FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */
62
-FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */
63
-FIELD(CPTR_EL2, TTA, 28, 1)
64
-FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */
65
-FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */
66
-
67
-/* Bit definitions for CPTR_EL3 (AArch64 only) */
68
-FIELD(CPTR_EL3, EZ, 8, 1)
69
-FIELD(CPTR_EL3, TFP, 10, 1)
70
-FIELD(CPTR_EL3, ESM, 12, 1)
71
-FIELD(CPTR_EL3, TTA, 20, 1)
72
-FIELD(CPTR_EL3, TAM, 30, 1)
73
-FIELD(CPTR_EL3, TCPAC, 31, 1)
74
-
75
-#define MDCR_MTPME (1U << 28)
76
-#define MDCR_TDCC (1U << 27)
77
-#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
78
-#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
79
-#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
80
-#define MDCR_EPMAD (1U << 21)
81
-#define MDCR_EDAD (1U << 20)
82
-#define MDCR_TTRF (1U << 19)
83
-#define MDCR_STE (1U << 18) /* MDCR_EL3 */
84
-#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
85
-#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
86
-#define MDCR_SDD (1U << 16)
87
-#define MDCR_SPD (3U << 14)
88
-#define MDCR_TDRA (1U << 11)
89
-#define MDCR_TDOSA (1U << 10)
90
-#define MDCR_TDA (1U << 9)
91
-#define MDCR_TDE (1U << 8)
92
-#define MDCR_HPME (1U << 7)
93
-#define MDCR_TPM (1U << 6)
94
-#define MDCR_TPMCR (1U << 5)
95
-#define MDCR_HPMN (0x1fU)
96
-
97
-/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
98
-#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
99
- MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
100
- MDCR_STE | MDCR_SPME | MDCR_SPD)
101
-
102
#define CPSR_M (0x1fU)
103
#define CPSR_T (1U << 5)
104
#define CPSR_F (1U << 6)
105
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
106
#define XPSR_NZCV CPSR_NZCV
107
#define XPSR_IT CPSR_IT
108
109
-#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
110
-#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
111
-#define TTBCR_PD0 (1U << 4)
112
-#define TTBCR_PD1 (1U << 5)
113
-#define TTBCR_EPD0 (1U << 7)
114
-#define TTBCR_IRGN0 (3U << 8)
115
-#define TTBCR_ORGN0 (3U << 10)
116
-#define TTBCR_SH0 (3U << 12)
117
-#define TTBCR_T1SZ (3U << 16)
118
-#define TTBCR_A1 (1U << 22)
119
-#define TTBCR_EPD1 (1U << 23)
120
-#define TTBCR_IRGN1 (3U << 24)
121
-#define TTBCR_ORGN1 (3U << 26)
122
-#define TTBCR_SH1 (1U << 28)
123
-#define TTBCR_EAE (1U << 31)
124
-
125
-FIELD(VTCR, T0SZ, 0, 6)
126
-FIELD(VTCR, SL0, 6, 2)
127
-FIELD(VTCR, IRGN0, 8, 2)
128
-FIELD(VTCR, ORGN0, 10, 2)
129
-FIELD(VTCR, SH0, 12, 2)
130
-FIELD(VTCR, TG0, 14, 2)
131
-FIELD(VTCR, PS, 16, 3)
132
-FIELD(VTCR, VS, 19, 1)
133
-FIELD(VTCR, HA, 21, 1)
134
-FIELD(VTCR, HD, 22, 1)
135
-FIELD(VTCR, HWU59, 25, 1)
136
-FIELD(VTCR, HWU60, 26, 1)
137
-FIELD(VTCR, HWU61, 27, 1)
138
-FIELD(VTCR, HWU62, 28, 1)
139
-FIELD(VTCR, NSW, 29, 1)
140
-FIELD(VTCR, NSA, 30, 1)
141
-FIELD(VTCR, DS, 32, 1)
142
-FIELD(VTCR, SL2, 33, 1)
143
-
144
/* Bit definitions for ARMv8 SPSR (PSTATE) format.
145
* Only these are valid when in AArch64 mode; in
146
* AArch32 mode SPSRs are basically CPSR-format.
147
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
148
#define HCR_TWEDEN (1ULL << 59)
149
#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
150
151
-#define HCRX_ENAS0 (1ULL << 0)
152
-#define HCRX_ENALS (1ULL << 1)
153
-#define HCRX_ENASR (1ULL << 2)
154
-#define HCRX_FNXS (1ULL << 3)
155
-#define HCRX_FGTNXS (1ULL << 4)
156
-#define HCRX_SMPME (1ULL << 5)
157
-#define HCRX_TALLINT (1ULL << 6)
158
-#define HCRX_VINMI (1ULL << 7)
159
-#define HCRX_VFNMI (1ULL << 8)
160
-#define HCRX_CMOW (1ULL << 9)
161
-#define HCRX_MCE2 (1ULL << 10)
162
-#define HCRX_MSCEN (1ULL << 11)
163
-
164
-#define HPFAR_NS (1ULL << 63)
165
-
166
#define SCR_NS (1ULL << 0)
167
#define SCR_IRQ (1ULL << 1)
168
#define SCR_FIQ (1ULL << 2)
169
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
170
#define SCR_GPF (1ULL << 48)
171
#define SCR_NSE (1ULL << 62)
172
173
-#define HSTR_TTEE (1 << 16)
174
-#define HSTR_TJDBX (1 << 17)
175
-
176
-#define CNTHCTL_CNTVMASK (1 << 18)
177
-#define CNTHCTL_CNTPMASK (1 << 19)
178
-
179
/* Return the current FPSCR value. */
180
uint32_t vfp_get_fpscr(CPUARMState *env);
181
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
182
diff --git a/target/arm/internals.h b/target/arm/internals.h
41
index XXXXXXX..XXXXXXX 100644
183
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/ide/ahci.c
184
--- a/target/arm/internals.h
43
+++ b/hw/ide/ahci.c
185
+++ b/target/arm/internals.h
44
@@ -XXX,XX +XXX,XX @@ void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
186
@@ -XXX,XX +XXX,XX @@ FIELD(DBGWCR, WT, 20, 1)
45
for (i = 0; i < s->ports; i++) {
187
FIELD(DBGWCR, MASK, 24, 5)
46
AHCIDevice *ad = &s->dev[i];
188
FIELD(DBGWCR, SSCE, 29, 1)
47
189
48
- ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1);
190
+#define VTCR_NSW (1u << 29)
49
+ ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1);
191
+#define VTCR_NSA (1u << 30)
50
ide_init2(&ad->port, irqs[i]);
192
+#define VSTCR_SW VTCR_NSW
51
193
+#define VSTCR_SA VTCR_NSA
52
ad->hba = s;
194
+
53
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
195
+/* Bit definitions for CPACR (AArch32 only) */
54
index XXXXXXX..XXXXXXX 100644
196
+FIELD(CPACR, CP10, 20, 2)
55
--- a/hw/ide/cmd646.c
197
+FIELD(CPACR, CP11, 22, 2)
56
+++ b/hw/ide/cmd646.c
198
+FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */
57
@@ -XXX,XX +XXX,XX @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
199
+FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */
58
200
+FIELD(CPACR, ASEDIS, 31, 1)
59
qdev_init_gpio_in(ds, cmd646_set_irq, 2);
201
+
60
for (i = 0; i < 2; i++) {
202
+/* Bit definitions for CPACR_EL1 (AArch64 only) */
61
- ide_bus_new(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
203
+FIELD(CPACR_EL1, ZEN, 16, 2)
62
+ ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
204
+FIELD(CPACR_EL1, FPEN, 20, 2)
63
ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i));
205
+FIELD(CPACR_EL1, SMEN, 24, 2)
64
206
+FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */
65
bmdma_init(&d->bus[i], &d->bmdma[i], d);
207
+
66
diff --git a/hw/ide/isa.c b/hw/ide/isa.c
208
+/* Bit definitions for HCPTR (AArch32 only) */
67
index XXXXXXX..XXXXXXX 100644
209
+FIELD(HCPTR, TCP10, 10, 1)
68
--- a/hw/ide/isa.c
210
+FIELD(HCPTR, TCP11, 11, 1)
69
+++ b/hw/ide/isa.c
211
+FIELD(HCPTR, TASE, 15, 1)
70
@@ -XXX,XX +XXX,XX @@ static void isa_ide_realizefn(DeviceState *dev, Error **errp)
212
+FIELD(HCPTR, TTA, 20, 1)
71
ISADevice *isadev = ISA_DEVICE(dev);
213
+FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */
72
ISAIDEState *s = ISA_IDE(dev);
214
+FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */
73
215
+
74
- ide_bus_new(&s->bus, sizeof(s->bus), dev, 0, 2);
216
+/* Bit definitions for CPTR_EL2 (AArch64 only) */
75
+ ide_bus_init(&s->bus, sizeof(s->bus), dev, 0, 2);
217
+FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */
76
ide_init_ioport(&s->bus, isadev, s->iobase, s->iobase2);
218
+FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */
77
isa_init_irq(isadev, &s->irq, s->isairq);
219
+FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */
78
ide_init2(&s->bus, s->irq);
220
+FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */
79
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
221
+FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */
80
index XXXXXXX..XXXXXXX 100644
222
+FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */
81
--- a/hw/ide/macio.c
223
+FIELD(CPTR_EL2, TTA, 28, 1)
82
+++ b/hw/ide/macio.c
224
+FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */
83
@@ -XXX,XX +XXX,XX @@ static void macio_ide_initfn(Object *obj)
225
+FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */
84
SysBusDevice *d = SYS_BUS_DEVICE(obj);
226
+
85
MACIOIDEState *s = MACIO_IDE(obj);
227
+/* Bit definitions for CPTR_EL3 (AArch64 only) */
86
228
+FIELD(CPTR_EL3, EZ, 8, 1)
87
- ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
229
+FIELD(CPTR_EL3, TFP, 10, 1)
88
+ ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
230
+FIELD(CPTR_EL3, ESM, 12, 1)
89
memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
231
+FIELD(CPTR_EL3, TTA, 20, 1)
90
sysbus_init_mmio(d, &s->mem);
232
+FIELD(CPTR_EL3, TAM, 30, 1)
91
sysbus_init_irq(d, &s->real_ide_irq);
233
+FIELD(CPTR_EL3, TCPAC, 31, 1)
92
diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c
234
+
93
index XXXXXXX..XXXXXXX 100644
235
+#define MDCR_MTPME (1U << 28)
94
--- a/hw/ide/microdrive.c
236
+#define MDCR_TDCC (1U << 27)
95
+++ b/hw/ide/microdrive.c
237
+#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
96
@@ -XXX,XX +XXX,XX @@ static void microdrive_init(Object *obj)
238
+#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
97
{
239
+#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
98
MicroDriveState *md = MICRODRIVE(obj);
240
+#define MDCR_EPMAD (1U << 21)
99
241
+#define MDCR_EDAD (1U << 20)
100
- ide_bus_new(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
242
+#define MDCR_TTRF (1U << 19)
101
+ ide_bus_init(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
243
+#define MDCR_STE (1U << 18) /* MDCR_EL3 */
102
}
244
+#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
103
245
+#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
104
static void microdrive_class_init(ObjectClass *oc, void *data)
246
+#define MDCR_SDD (1U << 16)
105
diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c
247
+#define MDCR_SPD (3U << 14)
106
index XXXXXXX..XXXXXXX 100644
248
+#define MDCR_TDRA (1U << 11)
107
--- a/hw/ide/mmio.c
249
+#define MDCR_TDOSA (1U << 10)
108
+++ b/hw/ide/mmio.c
250
+#define MDCR_TDA (1U << 9)
109
@@ -XXX,XX +XXX,XX @@ static void mmio_ide_initfn(Object *obj)
251
+#define MDCR_TDE (1U << 8)
110
SysBusDevice *d = SYS_BUS_DEVICE(obj);
252
+#define MDCR_HPME (1U << 7)
111
MMIOState *s = MMIO_IDE(obj);
253
+#define MDCR_TPM (1U << 6)
112
254
+#define MDCR_TPMCR (1U << 5)
113
- ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
255
+#define MDCR_HPMN (0x1fU)
114
+ ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
256
+
115
sysbus_init_irq(d, &s->irq);
257
+/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
116
}
258
+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
117
259
+ MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
118
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
260
+ MDCR_STE | MDCR_SPME | MDCR_SPD)
119
index XXXXXXX..XXXXXXX 100644
261
+
120
--- a/hw/ide/piix.c
262
+#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
121
+++ b/hw/ide/piix.c
263
+#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
122
@@ -XXX,XX +XXX,XX @@ static int pci_piix_init_ports(PCIIDEState *d)
264
+#define TTBCR_PD0 (1U << 4)
123
int i, ret;
265
+#define TTBCR_PD1 (1U << 5)
124
266
+#define TTBCR_EPD0 (1U << 7)
125
for (i = 0; i < 2; i++) {
267
+#define TTBCR_IRGN0 (3U << 8)
126
- ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
268
+#define TTBCR_ORGN0 (3U << 10)
127
+ ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
269
+#define TTBCR_SH0 (3U << 12)
128
ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
270
+#define TTBCR_T1SZ (3U << 16)
129
port_info[i].iobase2);
271
+#define TTBCR_A1 (1U << 22)
130
if (ret) {
272
+#define TTBCR_EPD1 (1U << 23)
131
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
273
+#define TTBCR_IRGN1 (3U << 24)
132
index XXXXXXX..XXXXXXX 100644
274
+#define TTBCR_ORGN1 (3U << 26)
133
--- a/hw/ide/qdev.c
275
+#define TTBCR_SH1 (1U << 28)
134
+++ b/hw/ide/qdev.c
276
+#define TTBCR_EAE (1U << 31)
135
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ide_bus_info = {
277
+
136
.class_init = ide_bus_class_init,
278
+FIELD(VTCR, T0SZ, 0, 6)
137
};
279
+FIELD(VTCR, SL0, 6, 2)
138
280
+FIELD(VTCR, IRGN0, 8, 2)
139
-void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
281
+FIELD(VTCR, ORGN0, 10, 2)
140
+void ide_bus_init(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
282
+FIELD(VTCR, SH0, 12, 2)
141
int bus_id, int max_units)
283
+FIELD(VTCR, TG0, 14, 2)
142
{
284
+FIELD(VTCR, PS, 16, 3)
143
qbus_init(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL);
285
+FIELD(VTCR, VS, 19, 1)
144
diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c
286
+FIELD(VTCR, HA, 21, 1)
145
index XXXXXXX..XXXXXXX 100644
287
+FIELD(VTCR, HD, 22, 1)
146
--- a/hw/ide/sii3112.c
288
+FIELD(VTCR, HWU59, 25, 1)
147
+++ b/hw/ide/sii3112.c
289
+FIELD(VTCR, HWU60, 26, 1)
148
@@ -XXX,XX +XXX,XX @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp)
290
+FIELD(VTCR, HWU61, 27, 1)
149
291
+FIELD(VTCR, HWU62, 28, 1)
150
qdev_init_gpio_in(ds, sii3112_set_irq, 2);
292
+FIELD(VTCR, NSW, 29, 1)
151
for (i = 0; i < 2; i++) {
293
+FIELD(VTCR, NSA, 30, 1)
152
- ide_bus_new(&s->bus[i], sizeof(s->bus[i]), ds, i, 1);
294
+FIELD(VTCR, DS, 32, 1)
153
+ ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1);
295
+FIELD(VTCR, SL2, 33, 1)
154
ide_init2(&s->bus[i], qdev_get_gpio_in(ds, i));
296
+
155
297
+#define HCRX_ENAS0 (1ULL << 0)
156
bmdma_init(&s->bus[i], &s->bmdma[i], s);
298
+#define HCRX_ENALS (1ULL << 1)
157
diff --git a/hw/ide/via.c b/hw/ide/via.c
299
+#define HCRX_ENASR (1ULL << 2)
158
index XXXXXXX..XXXXXXX 100644
300
+#define HCRX_FNXS (1ULL << 3)
159
--- a/hw/ide/via.c
301
+#define HCRX_FGTNXS (1ULL << 4)
160
+++ b/hw/ide/via.c
302
+#define HCRX_SMPME (1ULL << 5)
161
@@ -XXX,XX +XXX,XX @@ static void via_ide_realize(PCIDevice *dev, Error **errp)
303
+#define HCRX_TALLINT (1ULL << 6)
162
304
+#define HCRX_VINMI (1ULL << 7)
163
qdev_init_gpio_in(ds, via_ide_set_irq, 2);
305
+#define HCRX_VFNMI (1ULL << 8)
164
for (i = 0; i < 2; i++) {
306
+#define HCRX_CMOW (1ULL << 9)
165
- ide_bus_new(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
307
+#define HCRX_MCE2 (1ULL << 10)
166
+ ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
308
+#define HCRX_MSCEN (1ULL << 11)
167
ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i));
309
+
168
310
+#define HPFAR_NS (1ULL << 63)
169
bmdma_init(&d->bus[i], &d->bmdma[i], d);
311
+
312
+#define HSTR_TTEE (1 << 16)
313
+#define HSTR_TJDBX (1 << 17)
314
+
315
+#define CNTHCTL_CNTVMASK (1 << 18)
316
+#define CNTHCTL_CNTPMASK (1 << 19)
317
+
318
/* We use a few fake FSR values for internal purposes in M profile.
319
* M profile cores don't have A/R format FSRs, but currently our
320
* get_phys_addr() code assumes A/R profile and reports failures via
170
--
321
--
171
2.20.1
322
2.34.1
172
323
173
324
diff view generated by jsdifflib
[PULL 15/22] target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML
[PULL 02/14] target/arm: Timer _EL02 registers UNDEF for E2H == 0
1
Currently we send VFP XML which includes D0..D15 or D0..D31, plus
1
The timer _EL02 registers should UNDEF for invalid accesses from EL2
2
FPSID, FPSCR and FPEXC. The upstream GDB tolerates this, but its
2
or EL3 when HCR_EL2.E2H == 0, not take a cp access trap. We were
3
definition of this XML feature does not include FPSID or FPEXC. In
3
delivering the exception to EL2 with the wrong syndrome.
4
particular, for M-profile cores there are no FPSID or FPEXC
5
registers, so advertising those is wrong.
6
7
Move FPSID and FPEXC into their own bit of XML which we only send for
8
A and R profile cores. This brings our definition of the XML
9
org.gnu.gdb.arm.vfp feature into line with GDB's own (at least for
10
non-Neon cores...) and means we don't claim to have FPSID and FPEXC
11
on M-profile.
12
13
(It seems unlikely to me that any gdbstub users really care about
14
being able to look at FPEXC and FPSID; but we've supplied them to gdb
15
for a decade and it's not hard to keep doing so.)
16
4
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20210921162901.17508-5-peter.maydell@linaro.org
7
Message-id: 20240301183219.2424889-3-peter.maydell@linaro.org
20
---
8
---
21
configs/targets/aarch64-softmmu.mak | 2 +-
9
target/arm/helper.c | 2 +-
22
configs/targets/arm-linux-user.mak | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
23
configs/targets/arm-softmmu.mak | 2 +-
24
configs/targets/armeb-linux-user.mak | 2 +-
25
target/arm/gdbstub.c | 56 ++++++++++++++++++++--------
26
gdb-xml/arm-neon.xml | 2 -
27
gdb-xml/arm-vfp-sysregs.xml | 17 +++++++++
28
gdb-xml/arm-vfp.xml | 2 -
29
gdb-xml/arm-vfp3.xml | 2 -
30
9 files changed, 61 insertions(+), 26 deletions(-)
31
create mode 100644 gdb-xml/arm-vfp-sysregs.xml
32
11
33
diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
34
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
35
--- a/configs/targets/aarch64-softmmu.mak
14
--- a/target/arm/helper.c
36
+++ b/configs/targets/aarch64-softmmu.mak
15
+++ b/target/arm/helper.c
37
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
38
TARGET_ARCH=aarch64
17
return CP_ACCESS_OK;
39
TARGET_BASE_ARCH=arm
40
TARGET_SUPPORTS_MTTCG=y
41
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
42
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
43
TARGET_NEED_FDT=y
44
diff --git a/configs/targets/arm-linux-user.mak b/configs/targets/arm-linux-user.mak
45
index XXXXXXX..XXXXXXX 100644
46
--- a/configs/targets/arm-linux-user.mak
47
+++ b/configs/targets/arm-linux-user.mak
48
@@ -XXX,XX +XXX,XX @@
49
TARGET_ARCH=arm
50
TARGET_SYSTBL_ABI=common,oabi
51
TARGET_SYSTBL=syscall.tbl
52
-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
53
+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
54
TARGET_HAS_BFLT=y
55
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
56
diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.mak
57
index XXXXXXX..XXXXXXX 100644
58
--- a/configs/targets/arm-softmmu.mak
59
+++ b/configs/targets/arm-softmmu.mak
60
@@ -XXX,XX +XXX,XX @@
61
TARGET_ARCH=arm
62
TARGET_SUPPORTS_MTTCG=y
63
-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
64
+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
65
TARGET_NEED_FDT=y
66
diff --git a/configs/targets/armeb-linux-user.mak b/configs/targets/armeb-linux-user.mak
67
index XXXXXXX..XXXXXXX 100644
68
--- a/configs/targets/armeb-linux-user.mak
69
+++ b/configs/targets/armeb-linux-user.mak
70
@@ -XXX,XX +XXX,XX @@ TARGET_ARCH=arm
71
TARGET_SYSTBL_ABI=common,oabi
72
TARGET_SYSTBL=syscall.tbl
73
TARGET_WORDS_BIGENDIAN=y
74
-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
75
+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
76
TARGET_HAS_BFLT=y
77
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
78
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/target/arm/gdbstub.c
81
+++ b/target/arm/gdbstub.c
82
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
83
}
18
}
84
switch (reg - nregs) {
19
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
85
case 0:
20
- return CP_ACCESS_TRAP;
86
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
21
+ return CP_ACCESS_TRAP_UNCATEGORIZED;
87
- case 1:
88
return gdb_get_reg32(buf, vfp_get_fpscr(env));
89
- case 2:
90
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
91
}
22
}
92
return 0;
23
return CP_ACCESS_OK;
93
}
24
}
94
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
95
}
96
}
97
switch (reg - nregs) {
98
+ case 0:
99
+ vfp_set_fpscr(env, ldl_p(buf));
100
+ return 4;
101
+ }
102
+ return 0;
103
+}
104
+
105
+static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
106
+{
107
+ switch (reg) {
108
+ case 0:
109
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
110
+ case 1:
111
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
112
+ }
113
+ return 0;
114
+}
115
+
116
+static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
117
+{
118
+ switch (reg) {
119
case 0:
120
env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
121
return 4;
122
case 1:
123
- vfp_set_fpscr(env, ldl_p(buf));
124
- return 4;
125
- case 2:
126
env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
127
return 4;
128
}
129
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
130
34, "aarch64-fpu.xml", 0);
131
}
132
#endif
133
- } else if (arm_feature(env, ARM_FEATURE_NEON)) {
134
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
135
- 51, "arm-neon.xml", 0);
136
- } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
137
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
138
- 35, "arm-vfp3.xml", 0);
139
- } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
140
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
141
- 19, "arm-vfp.xml", 0);
142
+ } else {
143
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
144
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
145
+ 49, "arm-neon.xml", 0);
146
+ } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
147
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
148
+ 33, "arm-vfp3.xml", 0);
149
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
150
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
151
+ 17, "arm-vfp.xml", 0);
152
+ }
153
+ if (!arm_feature(env, ARM_FEATURE_M)) {
154
+ /*
155
+ * A and R profile have FP sysregs FPEXC and FPSID that we
156
+ * expose to gdb.
157
+ */
158
+ gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_sysreg,
159
+ 2, "arm-vfp-sysregs.xml", 0);
160
+ }
161
}
162
gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
163
arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
164
diff --git a/gdb-xml/arm-neon.xml b/gdb-xml/arm-neon.xml
165
index XXXXXXX..XXXXXXX 100644
166
--- a/gdb-xml/arm-neon.xml
167
+++ b/gdb-xml/arm-neon.xml
168
@@ -XXX,XX +XXX,XX @@
169
<reg name="q14" bitsize="128" type="neon_q"/>
170
<reg name="q15" bitsize="128" type="neon_q"/>
171
172
- <reg name="fpsid" bitsize="32" type="int" group="float"/>
173
<reg name="fpscr" bitsize="32" type="int" group="float"/>
174
- <reg name="fpexc" bitsize="32" type="int" group="float"/>
175
</feature>
176
diff --git a/gdb-xml/arm-vfp-sysregs.xml b/gdb-xml/arm-vfp-sysregs.xml
177
new file mode 100644
178
index XXXXXXX..XXXXXXX
179
--- /dev/null
180
+++ b/gdb-xml/arm-vfp-sysregs.xml
181
@@ -XXX,XX +XXX,XX @@
182
+<?xml version="1.0"?>
183
+<!-- Copyright (C) 2021 Linaro Ltd.
184
+
185
+ Copying and distribution of this file, with or without modification,
186
+ are permitted in any medium without royalty provided the copyright
187
+ notice and this notice are preserved.
188
+
189
+ These are A/R profile VFP system registers. Debugger users probably
190
+ don't really care about these, but because we used to (incorrectly)
191
+ provide them to gdb in the org.gnu.gdb.arm.vfp XML we continue
192
+ to do so via this separate XML.
193
+ -->
194
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
195
+<feature name="org.qemu.gdb.arm.vfp-sysregs">
196
+ <reg name="fpsid" bitsize="32" type="int" group="float"/>
197
+ <reg name="fpexc" bitsize="32" type="int" group="float"/>
198
+</feature>
199
diff --git a/gdb-xml/arm-vfp.xml b/gdb-xml/arm-vfp.xml
200
index XXXXXXX..XXXXXXX 100644
201
--- a/gdb-xml/arm-vfp.xml
202
+++ b/gdb-xml/arm-vfp.xml
203
@@ -XXX,XX +XXX,XX @@
204
<reg name="d14" bitsize="64" type="float"/>
205
<reg name="d15" bitsize="64" type="float"/>
206
207
- <reg name="fpsid" bitsize="32" type="int" group="float"/>
208
<reg name="fpscr" bitsize="32" type="int" group="float"/>
209
- <reg name="fpexc" bitsize="32" type="int" group="float"/>
210
</feature>
211
diff --git a/gdb-xml/arm-vfp3.xml b/gdb-xml/arm-vfp3.xml
212
index XXXXXXX..XXXXXXX 100644
213
--- a/gdb-xml/arm-vfp3.xml
214
+++ b/gdb-xml/arm-vfp3.xml
215
@@ -XXX,XX +XXX,XX @@
216
<reg name="d30" bitsize="64" type="float"/>
217
<reg name="d31" bitsize="64" type="float"/>
218
219
- <reg name="fpsid" bitsize="32" type="int" group="float"/>
220
<reg name="fpscr" bitsize="32" type="int" group="float"/>
221
- <reg name="fpexc" bitsize="32" type="int" group="float"/>
222
</feature>
223
--
25
--
224
2.20.1
26
2.34.1
225
226
diff view generated by jsdifflib
[PULL 14/22] target/arm: Move gdbstub related code out of helper.c
[PULL 03/14] target/arm: use FIELD macro for CNTHCTL bit definitions
1
Currently helper.c includes some code which is part of the arm
1
We prefer the FIELD macro over ad-hoc #defines for register bits;
2
target's gdbstub support. This code has a better home: in gdbstub.c
2
switch CNTHCTL to that style before we add any more bits.
3
and gdbstub64.c. Move it there.
4
5
Because aarch64_fpu_gdb_get_reg() and aarch64_fpu_gdb_set_reg() move
6
into gdbstub64.c, this means that they're now compiled only for
7
TARGET_AARCH64 rather than always. That is the only case when they
8
would ever be used, but it does mean that the ifdef in
9
arm_cpu_register_gdb_regs_for_features() needs to be adjusted to
10
match.
11
3
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20210921162901.17508-4-peter.maydell@linaro.org
7
Message-id: 20240301183219.2424889-4-peter.maydell@linaro.org
16
---
8
---
17
target/arm/internals.h | 7 ++
9
target/arm/internals.h | 27 +++++++++++++++++++++++++--
18
target/arm/gdbstub.c | 130 ++++++++++++++++++++
10
target/arm/helper.c | 9 ++++-----
19
target/arm/gdbstub64.c | 140 +++++++++++++++++++++
11
2 files changed, 29 insertions(+), 7 deletions(-)
20
target/arm/helper.c | 271 -----------------------------------------
21
4 files changed, 277 insertions(+), 271 deletions(-)
22
12
23
diff --git a/target/arm/internals.h b/target/arm/internals.h
13
diff --git a/target/arm/internals.h b/target/arm/internals.h
24
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/internals.h
15
--- a/target/arm/internals.h
26
+++ b/target/arm/internals.h
16
+++ b/target/arm/internals.h
27
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
17
@@ -XXX,XX +XXX,XX @@ FIELD(VTCR, SL2, 33, 1)
28
return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
18
#define HSTR_TTEE (1 << 16)
29
}
19
#define HSTR_TJDBX (1 << 17)
30
20
31
+#ifdef TARGET_AARCH64
21
-#define CNTHCTL_CNTVMASK (1 << 18)
32
+int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);
22
-#define CNTHCTL_CNTPMASK (1 << 19)
33
+int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);
23
+/*
34
+int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
24
+ * Depending on the value of HCR_EL2.E2H, bits 0 and 1
35
+int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
25
+ * have different bit definitions, and EL1PCTEN might be
36
+#endif
26
+ * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to
37
+
27
+ * disambiguate if necessary.
38
#endif
39
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/gdbstub.c
42
+++ b/target/arm/gdbstub.c
43
@@ -XXX,XX +XXX,XX @@
44
*/
45
#include "qemu/osdep.h"
46
#include "cpu.h"
47
+#include "internals.h"
48
#include "exec/gdbstub.h"
49
50
typedef struct RegisterSysregXmlParam {
51
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
52
return 0;
53
}
54
55
+static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
56
+{
57
+ ARMCPU *cpu = env_archcpu(env);
58
+ int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
59
+
60
+ /* VFP data registers are always little-endian. */
61
+ if (reg < nregs) {
62
+ return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));
63
+ }
64
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
65
+ /* Aliases for Q regs. */
66
+ nregs += 16;
67
+ if (reg < nregs) {
68
+ uint64_t *q = aa32_vfp_qreg(env, reg - 32);
69
+ return gdb_get_reg128(buf, q[0], q[1]);
70
+ }
71
+ }
72
+ switch (reg - nregs) {
73
+ case 0:
74
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
75
+ case 1:
76
+ return gdb_get_reg32(buf, vfp_get_fpscr(env));
77
+ case 2:
78
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
79
+ }
80
+ return 0;
81
+}
82
+
83
+static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
84
+{
85
+ ARMCPU *cpu = env_archcpu(env);
86
+ int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
87
+
88
+ if (reg < nregs) {
89
+ *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
90
+ return 8;
91
+ }
92
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
93
+ nregs += 16;
94
+ if (reg < nregs) {
95
+ uint64_t *q = aa32_vfp_qreg(env, reg - 32);
96
+ q[0] = ldq_le_p(buf);
97
+ q[1] = ldq_le_p(buf + 8);
98
+ return 16;
99
+ }
100
+ }
101
+ switch (reg - nregs) {
102
+ case 0:
103
+ env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
104
+ return 4;
105
+ case 1:
106
+ vfp_set_fpscr(env, ldl_p(buf));
107
+ return 4;
108
+ case 2:
109
+ env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
110
+ return 4;
111
+ }
112
+ return 0;
113
+}
114
+
115
+/**
116
+ * arm_get/set_gdb_*: get/set a gdb register
117
+ * @env: the CPU state
118
+ * @buf: a buffer to copy to/from
119
+ * @reg: register number (offset from start of group)
120
+ *
121
+ * We return the number of bytes copied
122
+ */
28
+ */
123
+
29
+FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1)
124
+static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
30
+FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1)
125
+{
31
+FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1)
126
+ ARMCPU *cpu = env_archcpu(env);
32
+FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1)
127
+ const ARMCPRegInfo *ri;
33
+FIELD(CNTHCTL, EVNTEN, 2, 1)
128
+ uint32_t key;
34
+FIELD(CNTHCTL, EVNTDIR, 3, 1)
129
+
35
+FIELD(CNTHCTL, EVNTI, 4, 4)
130
+ key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];
36
+FIELD(CNTHCTL, EL0VTEN, 8, 1)
131
+ ri = get_arm_cp_reginfo(cpu->cp_regs, key);
37
+FIELD(CNTHCTL, EL0PTEN, 9, 1)
132
+ if (ri) {
38
+FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1)
133
+ if (cpreg_field_is_64bit(ri)) {
39
+FIELD(CNTHCTL, EL1PTEN, 11, 1)
134
+ return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
40
+FIELD(CNTHCTL, ECV, 12, 1)
135
+ } else {
41
+FIELD(CNTHCTL, EL1TVT, 13, 1)
136
+ return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
42
+FIELD(CNTHCTL, EL1TVCT, 14, 1)
137
+ }
43
+FIELD(CNTHCTL, EL1NVPCT, 15, 1)
138
+ }
44
+FIELD(CNTHCTL, EL1NVVCT, 16, 1)
139
+ return 0;
45
+FIELD(CNTHCTL, EVNTIS, 17, 1)
140
+}
46
+FIELD(CNTHCTL, CNTVMASK, 18, 1)
141
+
47
+FIELD(CNTHCTL, CNTPMASK, 19, 1)
142
+static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
48
143
+{
49
/* We use a few fake FSR values for internal purposes in M profile.
144
+ return 0;
50
* M profile cores don't have A/R format FSRs, but currently our
145
+}
146
+
147
static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
148
ARMCPRegInfo *ri, uint32_t ri_key,
149
int bitsize, int regnum)
150
@@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
151
}
152
return NULL;
153
}
154
+
155
+void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
156
+{
157
+ CPUState *cs = CPU(cpu);
158
+ CPUARMState *env = &cpu->env;
159
+
160
+ if (arm_feature(env, ARM_FEATURE_AARCH64)) {
161
+ /*
162
+ * The lower part of each SVE register aliases to the FPU
163
+ * registers so we don't need to include both.
164
+ */
165
+#ifdef TARGET_AARCH64
166
+ if (isar_feature_aa64_sve(&cpu->isar)) {
167
+ gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
168
+ arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
169
+ "sve-registers.xml", 0);
170
+ } else {
171
+ gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
172
+ aarch64_fpu_gdb_set_reg,
173
+ 34, "aarch64-fpu.xml", 0);
174
+ }
175
+#endif
176
+ } else if (arm_feature(env, ARM_FEATURE_NEON)) {
177
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
178
+ 51, "arm-neon.xml", 0);
179
+ } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
180
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
181
+ 35, "arm-vfp3.xml", 0);
182
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
183
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
184
+ 19, "arm-vfp.xml", 0);
185
+ }
186
+ gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
187
+ arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
188
+ "system-registers.xml", 0);
189
+
190
+}
191
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
192
index XXXXXXX..XXXXXXX 100644
193
--- a/target/arm/gdbstub64.c
194
+++ b/target/arm/gdbstub64.c
195
@@ -XXX,XX +XXX,XX @@
196
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
197
*/
198
#include "qemu/osdep.h"
199
+#include "qemu/log.h"
200
#include "cpu.h"
201
+#include "internals.h"
202
#include "exec/gdbstub.h"
203
204
int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
205
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
206
/* Unknown register. */
207
return 0;
208
}
209
+
210
+int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
211
+{
212
+ switch (reg) {
213
+ case 0 ... 31:
214
+ {
215
+ /* 128 bit FP register - quads are in LE order */
216
+ uint64_t *q = aa64_vfp_qreg(env, reg);
217
+ return gdb_get_reg128(buf, q[1], q[0]);
218
+ }
219
+ case 32:
220
+ /* FPSR */
221
+ return gdb_get_reg32(buf, vfp_get_fpsr(env));
222
+ case 33:
223
+ /* FPCR */
224
+ return gdb_get_reg32(buf, vfp_get_fpcr(env));
225
+ default:
226
+ return 0;
227
+ }
228
+}
229
+
230
+int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
231
+{
232
+ switch (reg) {
233
+ case 0 ... 31:
234
+ /* 128 bit FP register */
235
+ {
236
+ uint64_t *q = aa64_vfp_qreg(env, reg);
237
+ q[0] = ldq_le_p(buf);
238
+ q[1] = ldq_le_p(buf + 8);
239
+ return 16;
240
+ }
241
+ case 32:
242
+ /* FPSR */
243
+ vfp_set_fpsr(env, ldl_p(buf));
244
+ return 4;
245
+ case 33:
246
+ /* FPCR */
247
+ vfp_set_fpcr(env, ldl_p(buf));
248
+ return 4;
249
+ default:
250
+ return 0;
251
+ }
252
+}
253
+
254
+int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
255
+{
256
+ ARMCPU *cpu = env_archcpu(env);
257
+
258
+ switch (reg) {
259
+ /* The first 32 registers are the zregs */
260
+ case 0 ... 31:
261
+ {
262
+ int vq, len = 0;
263
+ for (vq = 0; vq < cpu->sve_max_vq; vq++) {
264
+ len += gdb_get_reg128(buf,
265
+ env->vfp.zregs[reg].d[vq * 2 + 1],
266
+ env->vfp.zregs[reg].d[vq * 2]);
267
+ }
268
+ return len;
269
+ }
270
+ case 32:
271
+ return gdb_get_reg32(buf, vfp_get_fpsr(env));
272
+ case 33:
273
+ return gdb_get_reg32(buf, vfp_get_fpcr(env));
274
+ /* then 16 predicates and the ffr */
275
+ case 34 ... 50:
276
+ {
277
+ int preg = reg - 34;
278
+ int vq, len = 0;
279
+ for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
280
+ len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
281
+ }
282
+ return len;
283
+ }
284
+ case 51:
285
+ {
286
+ /*
287
+ * We report in Vector Granules (VG) which is 64bit in a Z reg
288
+ * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
289
+ */
290
+ int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
291
+ return gdb_get_reg64(buf, vq * 2);
292
+ }
293
+ default:
294
+ /* gdbstub asked for something out our range */
295
+ qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
296
+ break;
297
+ }
298
+
299
+ return 0;
300
+}
301
+
302
+int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
303
+{
304
+ ARMCPU *cpu = env_archcpu(env);
305
+
306
+ /* The first 32 registers are the zregs */
307
+ switch (reg) {
308
+ /* The first 32 registers are the zregs */
309
+ case 0 ... 31:
310
+ {
311
+ int vq, len = 0;
312
+ uint64_t *p = (uint64_t *) buf;
313
+ for (vq = 0; vq < cpu->sve_max_vq; vq++) {
314
+ env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
315
+ env->vfp.zregs[reg].d[vq * 2] = *p++;
316
+ len += 16;
317
+ }
318
+ return len;
319
+ }
320
+ case 32:
321
+ vfp_set_fpsr(env, *(uint32_t *)buf);
322
+ return 4;
323
+ case 33:
324
+ vfp_set_fpcr(env, *(uint32_t *)buf);
325
+ return 4;
326
+ case 34 ... 50:
327
+ {
328
+ int preg = reg - 34;
329
+ int vq, len = 0;
330
+ uint64_t *p = (uint64_t *) buf;
331
+ for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
332
+ env->vfp.pregs[preg].p[vq / 4] = *p++;
333
+ len += 8;
334
+ }
335
+ return len;
336
+ }
337
+ case 51:
338
+ /* cannot set vg via gdbstub */
339
+ return 0;
340
+ default:
341
+ /* gdbstub asked for something out our range */
342
+ break;
343
+ }
344
+
345
+ return 0;
346
+}
347
diff --git a/target/arm/helper.c b/target/arm/helper.c
51
diff --git a/target/arm/helper.c b/target/arm/helper.c
348
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
349
--- a/target/arm/helper.c
53
--- a/target/arm/helper.c
350
+++ b/target/arm/helper.c
54
+++ b/target/arm/helper.c
351
@@ -XXX,XX +XXX,XX @@
55
@@ -XXX,XX +XXX,XX @@ static void gt_update_irq(ARMCPU *cpu, int timeridx)
352
#include "trace.h"
56
* It is RES0 in Secure and NonSecure state.
353
#include "cpu.h"
57
*/
354
#include "internals.h"
58
if ((ss == ARMSS_Root || ss == ARMSS_Realm) &&
355
-#include "exec/gdbstub.h"
59
- ((timeridx == GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) ||
356
#include "exec/helper-proto.h"
60
- (timeridx == GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) {
357
#include "qemu/host-utils.h"
61
+ ((timeridx == GTIMER_VIRT && (cnthctl & R_CNTHCTL_CNTVMASK_MASK)) ||
358
#include "qemu/main-loop.h"
62
+ (timeridx == GTIMER_PHYS && (cnthctl & R_CNTHCTL_CNTPMASK_MASK)))) {
359
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
63
irqstate = 0;
360
static void switch_mode(CPUARMState *env, int mode);
64
}
361
static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
65
362
66
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
363
-static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
67
{
364
-{
68
ARMCPU *cpu = env_archcpu(env);
365
- ARMCPU *cpu = env_archcpu(env);
69
uint32_t oldval = env->cp15.cnthctl_el2;
366
- int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
367
-
70
-
368
- /* VFP data registers are always little-endian. */
71
raw_write(env, ri, value);
369
- if (reg < nregs) {
72
370
- return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));
73
- if ((oldval ^ value) & CNTHCTL_CNTVMASK) {
371
- }
74
+ if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {
372
- if (arm_feature(env, ARM_FEATURE_NEON)) {
75
gt_update_irq(cpu, GTIMER_VIRT);
373
- /* Aliases for Q regs. */
76
- } else if ((oldval ^ value) & CNTHCTL_CNTPMASK) {
374
- nregs += 16;
77
+ } else if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) {
375
- if (reg < nregs) {
78
gt_update_irq(cpu, GTIMER_PHYS);
376
- uint64_t *q = aa32_vfp_qreg(env, reg - 32);
377
- return gdb_get_reg128(buf, q[0], q[1]);
378
- }
379
- }
380
- switch (reg - nregs) {
381
- case 0:
382
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
383
- case 1:
384
- return gdb_get_reg32(buf, vfp_get_fpscr(env));
385
- case 2:
386
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
387
- }
388
- return 0;
389
-}
390
-
391
-static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
392
-{
393
- ARMCPU *cpu = env_archcpu(env);
394
- int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
395
-
396
- if (reg < nregs) {
397
- *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
398
- return 8;
399
- }
400
- if (arm_feature(env, ARM_FEATURE_NEON)) {
401
- nregs += 16;
402
- if (reg < nregs) {
403
- uint64_t *q = aa32_vfp_qreg(env, reg - 32);
404
- q[0] = ldq_le_p(buf);
405
- q[1] = ldq_le_p(buf + 8);
406
- return 16;
407
- }
408
- }
409
- switch (reg - nregs) {
410
- case 0:
411
- env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
412
- return 4;
413
- case 1:
414
- vfp_set_fpscr(env, ldl_p(buf));
415
- return 4;
416
- case 2:
417
- env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
418
- return 4;
419
- }
420
- return 0;
421
-}
422
-
423
-static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
424
-{
425
- switch (reg) {
426
- case 0 ... 31:
427
- {
428
- /* 128 bit FP register - quads are in LE order */
429
- uint64_t *q = aa64_vfp_qreg(env, reg);
430
- return gdb_get_reg128(buf, q[1], q[0]);
431
- }
432
- case 32:
433
- /* FPSR */
434
- return gdb_get_reg32(buf, vfp_get_fpsr(env));
435
- case 33:
436
- /* FPCR */
437
- return gdb_get_reg32(buf, vfp_get_fpcr(env));
438
- default:
439
- return 0;
440
- }
441
-}
442
-
443
-static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
444
-{
445
- switch (reg) {
446
- case 0 ... 31:
447
- /* 128 bit FP register */
448
- {
449
- uint64_t *q = aa64_vfp_qreg(env, reg);
450
- q[0] = ldq_le_p(buf);
451
- q[1] = ldq_le_p(buf + 8);
452
- return 16;
453
- }
454
- case 32:
455
- /* FPSR */
456
- vfp_set_fpsr(env, ldl_p(buf));
457
- return 4;
458
- case 33:
459
- /* FPCR */
460
- vfp_set_fpcr(env, ldl_p(buf));
461
- return 4;
462
- default:
463
- return 0;
464
- }
465
-}
466
-
467
static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
468
{
469
assert(ri->fieldoffset);
470
@@ -XXX,XX +XXX,XX @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
471
}
79
}
472
}
80
}
473
474
-/**
475
- * arm_get/set_gdb_*: get/set a gdb register
476
- * @env: the CPU state
477
- * @buf: a buffer to copy to/from
478
- * @reg: register number (offset from start of group)
479
- *
480
- * We return the number of bytes copied
481
- */
482
-
483
-static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
484
-{
485
- ARMCPU *cpu = env_archcpu(env);
486
- const ARMCPRegInfo *ri;
487
- uint32_t key;
488
-
489
- key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];
490
- ri = get_arm_cp_reginfo(cpu->cp_regs, key);
491
- if (ri) {
492
- if (cpreg_field_is_64bit(ri)) {
493
- return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
494
- } else {
495
- return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
496
- }
497
- }
498
- return 0;
499
-}
500
-
501
-static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
502
-{
503
- return 0;
504
-}
505
-
506
-#ifdef TARGET_AARCH64
507
-static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
508
-{
509
- ARMCPU *cpu = env_archcpu(env);
510
-
511
- switch (reg) {
512
- /* The first 32 registers are the zregs */
513
- case 0 ... 31:
514
- {
515
- int vq, len = 0;
516
- for (vq = 0; vq < cpu->sve_max_vq; vq++) {
517
- len += gdb_get_reg128(buf,
518
- env->vfp.zregs[reg].d[vq * 2 + 1],
519
- env->vfp.zregs[reg].d[vq * 2]);
520
- }
521
- return len;
522
- }
523
- case 32:
524
- return gdb_get_reg32(buf, vfp_get_fpsr(env));
525
- case 33:
526
- return gdb_get_reg32(buf, vfp_get_fpcr(env));
527
- /* then 16 predicates and the ffr */
528
- case 34 ... 50:
529
- {
530
- int preg = reg - 34;
531
- int vq, len = 0;
532
- for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
533
- len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
534
- }
535
- return len;
536
- }
537
- case 51:
538
- {
539
- /*
540
- * We report in Vector Granules (VG) which is 64bit in a Z reg
541
- * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
542
- */
543
- int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
544
- return gdb_get_reg64(buf, vq * 2);
545
- }
546
- default:
547
- /* gdbstub asked for something out our range */
548
- qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
549
- break;
550
- }
551
-
552
- return 0;
553
-}
554
-
555
-static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
556
-{
557
- ARMCPU *cpu = env_archcpu(env);
558
-
559
- /* The first 32 registers are the zregs */
560
- switch (reg) {
561
- /* The first 32 registers are the zregs */
562
- case 0 ... 31:
563
- {
564
- int vq, len = 0;
565
- uint64_t *p = (uint64_t *) buf;
566
- for (vq = 0; vq < cpu->sve_max_vq; vq++) {
567
- env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
568
- env->vfp.zregs[reg].d[vq * 2] = *p++;
569
- len += 16;
570
- }
571
- return len;
572
- }
573
- case 32:
574
- vfp_set_fpsr(env, *(uint32_t *)buf);
575
- return 4;
576
- case 33:
577
- vfp_set_fpcr(env, *(uint32_t *)buf);
578
- return 4;
579
- case 34 ... 50:
580
- {
581
- int preg = reg - 34;
582
- int vq, len = 0;
583
- uint64_t *p = (uint64_t *) buf;
584
- for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
585
- env->vfp.pregs[preg].p[vq / 4] = *p++;
586
- len += 8;
587
- }
588
- return len;
589
- }
590
- case 51:
591
- /* cannot set vg via gdbstub */
592
- return 0;
593
- default:
594
- /* gdbstub asked for something out our range */
595
- break;
596
- }
597
-
598
- return 0;
599
-}
600
-#endif /* TARGET_AARCH64 */
601
-
602
static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
603
{
604
/* Return true if the regdef would cause an assertion if you called
605
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
606
#endif
607
}
608
609
-void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
610
-{
611
- CPUState *cs = CPU(cpu);
612
- CPUARMState *env = &cpu->env;
613
-
614
- if (arm_feature(env, ARM_FEATURE_AARCH64)) {
615
- /*
616
- * The lower part of each SVE register aliases to the FPU
617
- * registers so we don't need to include both.
618
- */
619
-#ifdef TARGET_AARCH64
620
- if (isar_feature_aa64_sve(&cpu->isar)) {
621
- gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
622
- arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
623
- "sve-registers.xml", 0);
624
- } else
625
-#endif
626
- {
627
- gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
628
- aarch64_fpu_gdb_set_reg,
629
- 34, "aarch64-fpu.xml", 0);
630
- }
631
- } else if (arm_feature(env, ARM_FEATURE_NEON)) {
632
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
633
- 51, "arm-neon.xml", 0);
634
- } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
635
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
636
- 35, "arm-vfp3.xml", 0);
637
- } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
638
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
639
- 19, "arm-vfp.xml", 0);
640
- }
641
- gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
642
- arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
643
- "system-registers.xml", 0);
644
-
645
-}
646
-
647
/* Sort alphabetically by type name, except for "any". */
648
static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
649
{
650
--
81
--
651
2.20.1
82
2.34.1
652
83
653
84
diff view generated by jsdifflib
[PULL 13/22] target/arm: Fix coding style issues in gdbstub code in helper.c
[PULL 04/14] target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written
1
We're going to move this code to a different file; fix the coding
1
Don't allow the guest to write CNTHCTL_EL2 bits which don't exist.
2
style first so checkpatch doesn't complain. This includes deleting
2
This is not strictly architecturally required, but it is how we've
3
the spurious 'break' statements after returns in the
3
tended to implement registers more recently.
4
vfp_gdb_get_reg() function.
4
5
In particular, bits [19:18] are only present with FEAT_RME,
6
and bits [17:12] will only be present with FEAT_ECV.
5
7
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210921162901.17508-3-peter.maydell@linaro.org
10
Message-id: 20240301183219.2424889-5-peter.maydell@linaro.org
10
---
11
---
11
target/arm/helper.c | 23 ++++++++++++++++-------
12
target/arm/helper.c | 18 ++++++++++++++++++
12
1 file changed, 16 insertions(+), 7 deletions(-)
13
1 file changed, 18 insertions(+)
13
14
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
17
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
18
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
19
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
19
}
20
{
20
}
21
ARMCPU *cpu = env_archcpu(env);
21
switch (reg - nregs) {
22
uint32_t oldval = env->cp15.cnthctl_el2;
22
- case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); break;
23
+ uint32_t valid_mask =
23
- case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break;
24
+ R_CNTHCTL_EL0PCTEN_E2H1_MASK |
24
- case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); break;
25
+ R_CNTHCTL_EL0VCTEN_E2H1_MASK |
25
+ case 0:
26
+ R_CNTHCTL_EVNTEN_MASK |
26
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
27
+ R_CNTHCTL_EVNTDIR_MASK |
27
+ case 1:
28
+ R_CNTHCTL_EVNTI_MASK |
28
+ return gdb_get_reg32(buf, vfp_get_fpscr(env));
29
+ R_CNTHCTL_EL0VTEN_MASK |
29
+ case 2:
30
+ R_CNTHCTL_EL0PTEN_MASK |
30
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
31
+ R_CNTHCTL_EL1PCTEN_E2H1_MASK |
31
}
32
+ R_CNTHCTL_EL1PTEN_MASK;
32
return 0;
33
+
33
}
34
+ if (cpu_isar_feature(aa64_rme, cpu)) {
34
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
35
+ valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK;
35
}
36
+ }
36
}
37
+
37
switch (reg - nregs) {
38
+ /* Clear RES0 bits */
38
- case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
39
+ value &= valid_mask;
39
- case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
40
+
40
- case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
41
raw_write(env, ri, value);
41
+ case 0:
42
42
+ env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
43
if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {
43
+ return 4;
44
+ case 1:
45
+ vfp_set_fpscr(env, ldl_p(buf));
46
+ return 4;
47
+ case 2:
48
+ env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
49
+ return 4;
50
}
51
return 0;
52
}
53
@@ -XXX,XX +XXX,XX @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
54
return gdb_get_reg32(buf, vfp_get_fpsr(env));
55
case 33:
56
/* FPCR */
57
- return gdb_get_reg32(buf,vfp_get_fpcr(env));
58
+ return gdb_get_reg32(buf, vfp_get_fpcr(env));
59
default:
60
return 0;
61
}
62
--
44
--
63
2.20.1
45
2.34.1
64
65
diff view generated by jsdifflib
[PULL 10/22] hw/arm: xlnx-zcu102: Add Xilinx eFUSE device
[PULL 05/14] target/arm: Implement new FEAT_ECV trap bits
1
From: Tong Ho <tong.ho@xilinx.com>
1
The functionality defined by ID_AA64MMFR0_EL1.ECV == 1 is:
2
* four new trap bits for various counter and timer registers
3
* the CNTHCTL_EL2.EVNTIS and CNTKCTL_EL1.EVNTIS bits which control
4
scaling of the event stream. This is a no-op for us, because we don't
5
implement the event stream (our WFE is a NOP): all we need to do is
6
allow CNTHCTL_EL2.ENVTIS to be read and written.
7
* extensions to PMSCR_EL1.PCT, PMSCR_EL2.PCT, TRFCR_EL1.TS and
8
TRFCR_EL2.TS: these are all no-ops for us, because we don't implement
9
FEAT_SPE or FEAT_TRF.
10
* new registers CNTPCTSS_EL0 and NCTVCTSS_EL0 which are
11
"self-sychronizing" views of the CNTPCT_EL0 and CNTVCT_EL0, meaning
12
that no barriers are needed around their accesses. For us these
13
are just the same as the normal views, because all our sysregs are
14
inherently self-sychronizing.
2
15
3
Connect the support for ZynqMP eFUSE one-time field-programmable
16
In this commit we implement the trap handling and permit the new
4
bit array.
17
CNTHCTL_EL2 bits to be written.
5
18
6
The command argument:
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
-drive if=pflash,index=3,...
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Can be used to optionally connect the bit array to a
21
Message-id: 20240301183219.2424889-6-peter.maydell@linaro.org
9
backend storage, such that field-programmed values
22
---
10
in one invocation can be made available to next
23
target/arm/cpu-features.h | 5 ++++
11
invocation.
24
target/arm/helper.c | 51 +++++++++++++++++++++++++++++++++++----
25
2 files changed, 51 insertions(+), 5 deletions(-)
12
26
13
The backend storage must be a seekable binary file, and
27
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
14
its size must be 768 bytes or larger. A file with all
15
binary 0's is a 'blank'.
16
17
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
18
Message-id: 20210917052400.1249094-9-tong.ho@xilinx.com
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
include/hw/arm/xlnx-zynqmp.h | 3 +++
23
hw/arm/xlnx-zcu102.c | 15 +++++++++++++++
24
hw/arm/xlnx-zynqmp.c | 29 +++++++++++++++++++++++++++++
25
hw/Kconfig | 1 +
26
4 files changed, 48 insertions(+)
27
28
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
29
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/xlnx-zynqmp.h
29
--- a/target/arm/cpu-features.h
31
+++ b/include/hw/arm/xlnx-zynqmp.h
30
+++ b/target/arm/cpu-features.h
32
@@ -XXX,XX +XXX,XX @@
31
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
33
#include "net/can_emu.h"
32
return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
34
#include "hw/dma/xlnx_csu_dma.h"
35
#include "hw/nvram/xlnx-bbram.h"
36
+#include "hw/nvram/xlnx-zynqmp-efuse.h"
37
38
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
39
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
40
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
41
MemoryRegion *ddr_ram;
42
MemoryRegion ddr_ram_low, ddr_ram_high;
43
XlnxBBRam bbram;
44
+ XlnxEFuse efuse;
45
+ XlnxZynqMPEFuse efuse_ctrl;
46
47
MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
48
49
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/hw/arm/xlnx-zcu102.c
52
+++ b/hw/arm/xlnx-zcu102.c
53
@@ -XXX,XX +XXX,XX @@ static void bbram_attach_drive(XlnxBBRam *dev)
54
}
55
}
33
}
56
34
57
+static void efuse_attach_drive(XlnxEFuse *dev)
35
+static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)
58
+{
36
+{
59
+ DriveInfo *dinfo;
37
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;
60
+ BlockBackend *blk;
61
+
62
+ dinfo = drive_get_by_index(IF_PFLASH, 3);
63
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
64
+ if (blk) {
65
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
66
+ }
67
+}
38
+}
68
+
39
+
69
static void xlnx_zcu102_init(MachineState *machine)
40
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
70
{
41
{
71
XlnxZCU102 *s = ZCU102_MACHINE(machine);
42
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
72
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
43
diff --git a/target/arm/helper.c b/target/arm/helper.c
73
/* Attach bbram backend, if given */
74
bbram_attach_drive(&s->soc.bbram);
75
76
+ /* Attach efuse backend, if given */
77
+ efuse_attach_drive(&s->soc.efuse);
78
+
79
/* Create and plug in the SD cards */
80
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
81
BusState *bus;
82
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
83
index XXXXXXX..XXXXXXX 100644
44
index XXXXXXX..XXXXXXX 100644
84
--- a/hw/arm/xlnx-zynqmp.c
45
--- a/target/arm/helper.c
85
+++ b/hw/arm/xlnx-zynqmp.c
46
+++ b/target/arm/helper.c
86
@@ -XXX,XX +XXX,XX @@
47
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
87
#define BBRAM_ADDR 0xffcd0000
48
: !extract32(env->cp15.cnthctl_el2, 0, 1))) {
88
#define BBRAM_IRQ 11
49
return CP_ACCESS_TRAP_EL2;
89
50
}
90
+#define EFUSE_ADDR 0xffcc0000
51
+ if (has_el2 && timeridx == GTIMER_VIRT) {
91
+#define EFUSE_IRQ 87
52
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVCT)) {
92
+
53
+ return CP_ACCESS_TRAP_EL2;
93
#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
54
+ }
94
55
+ }
95
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
56
break;
96
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
57
}
97
sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
58
return CP_ACCESS_OK;
59
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
60
}
61
}
62
}
63
+ if (has_el2 && timeridx == GTIMER_VIRT) {
64
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVT)) {
65
+ return CP_ACCESS_TRAP_EL2;
66
+ }
67
+ }
68
break;
69
}
70
return CP_ACCESS_OK;
71
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
72
if (cpu_isar_feature(aa64_rme, cpu)) {
73
valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK;
74
}
75
+ if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
76
+ valid_mask |=
77
+ R_CNTHCTL_EL1TVT_MASK |
78
+ R_CNTHCTL_EL1TVCT_MASK |
79
+ R_CNTHCTL_EL1NVPCT_MASK |
80
+ R_CNTHCTL_EL1NVVCT_MASK |
81
+ R_CNTHCTL_EVNTIS_MASK;
82
+ }
83
84
/* Clear RES0 bits */
85
value &= valid_mask;
86
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
87
{
88
if (arm_current_el(env) == 1) {
89
/* This must be a FEAT_NV access */
90
- /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */
91
return CP_ACCESS_OK;
92
}
93
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
94
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
95
return CP_ACCESS_OK;
98
}
96
}
99
97
100
+static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
98
+static CPAccessResult access_el1nvpct(CPUARMState *env, const ARMCPRegInfo *ri,
99
+ bool isread)
101
+{
100
+{
102
+ Object *bits = OBJECT(&s->efuse);
101
+ if (arm_current_el(env) == 1) {
103
+ Object *ctrl = OBJECT(&s->efuse_ctrl);
102
+ /* This must be a FEAT_NV access with NVx == 101 */
104
+ SysBusDevice *sbd;
103
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVPCT)) {
105
+
104
+ return CP_ACCESS_TRAP_EL2;
106
+ object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl,
105
+ }
107
+ TYPE_XLNX_ZYNQMP_EFUSE);
106
+ }
108
+
107
+ return e2h_access(env, ri, isread);
109
+ object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits,
110
+ sizeof(s->efuse),
111
+ TYPE_XLNX_EFUSE, &error_abort,
112
+ "efuse-nr", "3",
113
+ "efuse-size", "2048",
114
+ NULL);
115
+
116
+ qdev_realize(DEVICE(bits), NULL, &error_abort);
117
+ object_property_set_link(ctrl, "efuse", bits, &error_abort);
118
+
119
+ sbd = SYS_BUS_DEVICE(ctrl);
120
+ sysbus_realize(sbd, &error_abort);
121
+ sysbus_mmio_map(sbd, 0, EFUSE_ADDR);
122
+ sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
123
+}
108
+}
124
+
109
+
125
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
110
+static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo *ri,
111
+ bool isread)
112
+{
113
+ if (arm_current_el(env) == 1) {
114
+ /* This must be a FEAT_NV access with NVx == 101 */
115
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVVCT)) {
116
+ return CP_ACCESS_TRAP_EL2;
117
+ }
118
+ }
119
+ return e2h_access(env, ri, isread);
120
+}
121
+
122
/* Test if system register redirection is to occur in the current state. */
123
static bool redirect_for_e2h(CPUARMState *env)
126
{
124
{
127
static const struct UnimpInfo {
125
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
128
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
126
{ .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64,
129
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
127
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1,
130
128
.type = ARM_CP_IO | ARM_CP_ALIAS,
131
xlnx_zynqmp_create_bbram(s, gic_spi);
129
- .access = PL2_RW, .accessfn = e2h_access,
132
+ xlnx_zynqmp_create_efuse(s, gic_spi);
130
+ .access = PL2_RW, .accessfn = access_el1nvpct,
133
xlnx_zynqmp_create_unimp_mmio(s);
131
.nv2_redirect_offset = 0x180 | NV2_REDIR_NO_NV1,
134
132
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
135
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
133
.writefn = gt_phys_ctl_write, .raw_writefn = raw_write },
136
diff --git a/hw/Kconfig b/hw/Kconfig
134
{ .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64,
137
index XXXXXXX..XXXXXXX 100644
135
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1,
138
--- a/hw/Kconfig
136
.type = ARM_CP_IO | ARM_CP_ALIAS,
139
+++ b/hw/Kconfig
137
- .access = PL2_RW, .accessfn = e2h_access,
140
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP
138
+ .access = PL2_RW, .accessfn = access_el1nvvct,
141
select CAN_BUS
139
.nv2_redirect_offset = 0x170 | NV2_REDIR_NO_NV1,
142
select PTIMER
140
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
143
select XLNX_BBRAM
141
.writefn = gt_virt_ctl_write, .raw_writefn = raw_write },
144
+ select XLNX_EFUSE_ZYNQMP
142
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
143
.type = ARM_CP_IO | ARM_CP_ALIAS,
144
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
145
.nv2_redirect_offset = 0x178 | NV2_REDIR_NO_NV1,
146
- .access = PL2_RW, .accessfn = e2h_access,
147
+ .access = PL2_RW, .accessfn = access_el1nvpct,
148
.writefn = gt_phys_cval_write, .raw_writefn = raw_write },
149
{ .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64,
150
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2,
151
.type = ARM_CP_IO | ARM_CP_ALIAS,
152
.nv2_redirect_offset = 0x168 | NV2_REDIR_NO_NV1,
153
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
154
- .access = PL2_RW, .accessfn = e2h_access,
155
+ .access = PL2_RW, .accessfn = access_el1nvvct,
156
.writefn = gt_virt_cval_write, .raw_writefn = raw_write },
157
#endif
158
};
145
--
159
--
146
2.20.1
160
2.34.1
147
148
diff view generated by jsdifflib
[PULL 06/22] hw/nvram: Introduce Xilinx battery-backed ram
[PULL 06/14] target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
1
From: Tong Ho <tong.ho@xilinx.com>
1
For FEAT_ECV, new registers CNTPCTSS_EL0 and CNTVCTSS_EL0 are
2
defined, which are "self-synchronized" views of the physical and
3
virtual counts as seen in the CNTPCT_EL0 and CNTVCT_EL0 registers
4
(meaning that no barriers are needed around accesses to them to
5
ensure that reads of them do not occur speculatively and out-of-order
6
with other instructions).
2
7
3
This device is present in Versal and ZynqMP product
8
For QEMU, all our system registers are self-synchronized, so we can
4
families to store a 256-bit encryption key.
9
simply copy the existing implementation of CNTPCT_EL0 and CNTVCT_EL0
10
to the new register encodings.
5
11
6
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
12
This means we now implement all the functionality required for
7
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
13
ID_AA64MMFR0_EL1.ECV == 0b0001.
8
14
9
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
11
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
12
Message-id: 20210917052400.1249094-5-tong.ho@xilinx.com
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20240301183219.2424889-7-peter.maydell@linaro.org
15
---
18
---
16
include/hw/nvram/xlnx-bbram.h | 54 ++++
19
target/arm/helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++
17
hw/nvram/xlnx-bbram.c | 545 ++++++++++++++++++++++++++++++++++
20
1 file changed, 43 insertions(+)
18
hw/nvram/Kconfig | 4 +
19
hw/nvram/meson.build | 1 +
20
4 files changed, 604 insertions(+)
21
create mode 100644 include/hw/nvram/xlnx-bbram.h
22
create mode 100644 hw/nvram/xlnx-bbram.c
23
21
24
diff --git a/include/hw/nvram/xlnx-bbram.h b/include/hw/nvram/xlnx-bbram.h
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
25
new file mode 100644
23
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX
24
--- a/target/arm/helper.c
27
--- /dev/null
25
+++ b/target/arm/helper.c
28
+++ b/include/hw/nvram/xlnx-bbram.h
26
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
29
@@ -XXX,XX +XXX,XX @@
27
},
28
};
29
30
+/*
30
+/*
31
+ * QEMU model of the Xilinx BBRAM Battery Backed RAM
31
+ * FEAT_ECV adds extra views of CNTVCT_EL0 and CNTPCT_EL0 which
32
+ *
32
+ * are "self-synchronizing". For QEMU all sysregs are self-synchronizing,
33
+ * Copyright (c) 2015-2021 Xilinx Inc.
33
+ * so our implementations here are identical to the normal registers.
34
+ *
35
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
36
+ *
37
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
38
+ * of this software and associated documentation files (the "Software"), to deal
39
+ * in the Software without restriction, including without limitation the rights
40
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
41
+ * copies of the Software, and to permit persons to whom the Software is
42
+ * furnished to do so, subject to the following conditions:
43
+ *
44
+ * The above copyright notice and this permission notice shall be included in
45
+ * all copies or substantial portions of the Software.
46
+ *
47
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
48
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
49
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
50
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
51
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
52
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
53
+ * THE SOFTWARE.
54
+ */
34
+ */
55
+#ifndef XLNX_BBRAM_H
35
+static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
56
+#define XLNX_BBRAM_H
36
+ { .name = "CNTVCTSS", .cp = 15, .crm = 14, .opc1 = 9,
57
+
37
+ .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
58
+#include "sysemu/block-backend.h"
38
+ .accessfn = gt_vct_access,
59
+#include "hw/qdev-core.h"
39
+ .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
60
+#include "hw/irq.h"
40
+ },
61
+#include "hw/sysbus.h"
41
+ { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64,
62
+#include "hw/register.h"
42
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6,
63
+
43
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
64
+#define RMAX_XLNX_BBRAM ((0x4c / 4) + 1)
44
+ .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
65
+
45
+ },
66
+#define TYPE_XLNX_BBRAM "xlnx,bbram-ctrl"
46
+ { .name = "CNTPCTSS", .cp = 15, .crm = 14, .opc1 = 8,
67
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxBBRam, XLNX_BBRAM);
47
+ .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
68
+
48
+ .accessfn = gt_pct_access,
69
+struct XlnxBBRam {
49
+ .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
70
+ SysBusDevice parent_obj;
50
+ },
71
+ qemu_irq irq_bbram;
51
+ { .name = "CNTPCTSS_EL0", .state = ARM_CP_STATE_AA64,
72
+
52
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 5,
73
+ BlockBackend *blk;
53
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
74
+
54
+ .accessfn = gt_pct_access, .readfn = gt_cnt_read,
75
+ uint32_t crc_zpads;
76
+ bool bbram8_wo;
77
+ bool blk_ro;
78
+
79
+ uint32_t regs[RMAX_XLNX_BBRAM];
80
+ RegisterInfo regs_info[RMAX_XLNX_BBRAM];
81
+};
82
+
83
+#endif
84
diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c
85
new file mode 100644
86
index XXXXXXX..XXXXXXX
87
--- /dev/null
88
+++ b/hw/nvram/xlnx-bbram.c
89
@@ -XXX,XX +XXX,XX @@
90
+/*
91
+ * QEMU model of the Xilinx BBRAM Battery Backed RAM
92
+ *
93
+ * Copyright (c) 2014-2021 Xilinx Inc.
94
+ *
95
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
96
+ * of this software and associated documentation files (the "Software"), to deal
97
+ * in the Software without restriction, including without limitation the rights
98
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
99
+ * copies of the Software, and to permit persons to whom the Software is
100
+ * furnished to do so, subject to the following conditions:
101
+ *
102
+ * The above copyright notice and this permission notice shall be included in
103
+ * all copies or substantial portions of the Software.
104
+ *
105
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
106
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
107
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
108
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
109
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
110
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
111
+ * THE SOFTWARE.
112
+ */
113
+
114
+#include "qemu/osdep.h"
115
+#include "hw/nvram/xlnx-bbram.h"
116
+
117
+#include "qemu/error-report.h"
118
+#include "qemu/log.h"
119
+#include "qapi/error.h"
120
+#include "sysemu/blockdev.h"
121
+#include "migration/vmstate.h"
122
+#include "hw/qdev-properties.h"
123
+#include "hw/qdev-properties-system.h"
124
+#include "hw/nvram/xlnx-efuse.h"
125
+
126
+#ifndef XLNX_BBRAM_ERR_DEBUG
127
+#define XLNX_BBRAM_ERR_DEBUG 0
128
+#endif
129
+
130
+REG32(BBRAM_STATUS, 0x0)
131
+ FIELD(BBRAM_STATUS, AES_CRC_PASS, 9, 1)
132
+ FIELD(BBRAM_STATUS, AES_CRC_DONE, 8, 1)
133
+ FIELD(BBRAM_STATUS, BBRAM_ZEROIZED, 4, 1)
134
+ FIELD(BBRAM_STATUS, PGM_MODE, 0, 1)
135
+REG32(BBRAM_CTRL, 0x4)
136
+ FIELD(BBRAM_CTRL, ZEROIZE, 0, 1)
137
+REG32(PGM_MODE, 0x8)
138
+REG32(BBRAM_AES_CRC, 0xc)
139
+REG32(BBRAM_0, 0x10)
140
+REG32(BBRAM_1, 0x14)
141
+REG32(BBRAM_2, 0x18)
142
+REG32(BBRAM_3, 0x1c)
143
+REG32(BBRAM_4, 0x20)
144
+REG32(BBRAM_5, 0x24)
145
+REG32(BBRAM_6, 0x28)
146
+REG32(BBRAM_7, 0x2c)
147
+REG32(BBRAM_8, 0x30)
148
+REG32(BBRAM_SLVERR, 0x34)
149
+ FIELD(BBRAM_SLVERR, ENABLE, 0, 1)
150
+REG32(BBRAM_ISR, 0x38)
151
+ FIELD(BBRAM_ISR, APB_SLVERR, 0, 1)
152
+REG32(BBRAM_IMR, 0x3c)
153
+ FIELD(BBRAM_IMR, APB_SLVERR, 0, 1)
154
+REG32(BBRAM_IER, 0x40)
155
+ FIELD(BBRAM_IER, APB_SLVERR, 0, 1)
156
+REG32(BBRAM_IDR, 0x44)
157
+ FIELD(BBRAM_IDR, APB_SLVERR, 0, 1)
158
+REG32(BBRAM_MSW_LOCK, 0x4c)
159
+ FIELD(BBRAM_MSW_LOCK, VAL, 0, 1)
160
+
161
+#define R_MAX (R_BBRAM_MSW_LOCK + 1)
162
+
163
+#define RAM_MAX (A_BBRAM_8 + 4 - A_BBRAM_0)
164
+
165
+#define BBRAM_PGM_MAGIC 0x757bdf0d
166
+
167
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxBBRam *)0)->regs));
168
+
169
+static bool bbram_msw_locked(XlnxBBRam *s)
170
+{
171
+ return ARRAY_FIELD_EX32(s->regs, BBRAM_MSW_LOCK, VAL) != 0;
172
+}
173
+
174
+static bool bbram_pgm_enabled(XlnxBBRam *s)
175
+{
176
+ return ARRAY_FIELD_EX32(s->regs, BBRAM_STATUS, PGM_MODE) != 0;
177
+}
178
+
179
+static void bbram_bdrv_error(XlnxBBRam *s, int rc, gchar *detail)
180
+{
181
+ Error *errp;
182
+
183
+ error_setg_errno(&errp, -rc, "%s: BBRAM backstore %s failed.",
184
+ blk_name(s->blk), detail);
185
+ error_report("%s", error_get_pretty(errp));
186
+ error_free(errp);
187
+
188
+ g_free(detail);
189
+}
190
+
191
+static void bbram_bdrv_read(XlnxBBRam *s, Error **errp)
192
+{
193
+ uint32_t *ram = &s->regs[R_BBRAM_0];
194
+ int nr = RAM_MAX;
195
+
196
+ if (!s->blk) {
197
+ return;
198
+ }
199
+
200
+ s->blk_ro = !blk_supports_write_perm(s->blk);
201
+ if (!s->blk_ro) {
202
+ int rc;
203
+
204
+ rc = blk_set_perm(s->blk,
205
+ (BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE),
206
+ BLK_PERM_ALL, NULL);
207
+ if (rc) {
208
+ s->blk_ro = true;
209
+ }
210
+ }
211
+ if (s->blk_ro) {
212
+ warn_report("%s: Skip saving updates to read-only BBRAM backstore.",
213
+ blk_name(s->blk));
214
+ }
215
+
216
+ if (blk_pread(s->blk, 0, ram, nr) < 0) {
217
+ error_setg(errp,
218
+ "%s: Failed to read %u bytes from BBRAM backstore.",
219
+ blk_name(s->blk), nr);
220
+ return;
221
+ }
222
+
223
+ /* Convert from little-endian backstore for each 32-bit word */
224
+ nr /= 4;
225
+ while (nr--) {
226
+ ram[nr] = le32_to_cpu(ram[nr]);
227
+ }
228
+}
229
+
230
+static void bbram_bdrv_sync(XlnxBBRam *s, uint64_t hwaddr)
231
+{
232
+ uint32_t le32;
233
+ unsigned offset;
234
+ int rc;
235
+
236
+ assert(A_BBRAM_0 <= hwaddr && hwaddr <= A_BBRAM_8);
237
+
238
+ /* Backstore is always in little-endian */
239
+ le32 = cpu_to_le32(s->regs[hwaddr / 4]);
240
+
241
+ /* Update zeroized flag */
242
+ if (le32 && (hwaddr != A_BBRAM_8 || s->bbram8_wo)) {
243
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 0);
244
+ }
245
+
246
+ if (!s->blk || s->blk_ro) {
247
+ return;
248
+ }
249
+
250
+ offset = hwaddr - A_BBRAM_0;
251
+ rc = blk_pwrite(s->blk, offset, &le32, 4, 0);
252
+ if (rc < 0) {
253
+ bbram_bdrv_error(s, rc, g_strdup_printf("write to offset %u", offset));
254
+ }
255
+}
256
+
257
+static void bbram_bdrv_zero(XlnxBBRam *s)
258
+{
259
+ int rc;
260
+
261
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 1);
262
+
263
+ if (!s->blk || s->blk_ro) {
264
+ return;
265
+ }
266
+
267
+ rc = blk_make_zero(s->blk, 0);
268
+ if (rc < 0) {
269
+ bbram_bdrv_error(s, rc, g_strdup("zeroizing"));
270
+ }
271
+
272
+ /* Restore bbram8 if it is non-zero */
273
+ if (s->regs[R_BBRAM_8]) {
274
+ bbram_bdrv_sync(s, A_BBRAM_8);
275
+ }
276
+}
277
+
278
+static void bbram_zeroize(XlnxBBRam *s)
279
+{
280
+ int nr = RAM_MAX - (s->bbram8_wo ? 0 : 4); /* only wo bbram8 is cleared */
281
+
282
+ memset(&s->regs[R_BBRAM_0], 0, nr);
283
+ bbram_bdrv_zero(s);
284
+}
285
+
286
+static void bbram_update_irq(XlnxBBRam *s)
287
+{
288
+ bool pending = s->regs[R_BBRAM_ISR] & ~s->regs[R_BBRAM_IMR];
289
+
290
+ qemu_set_irq(s->irq_bbram, pending);
291
+}
292
+
293
+static void bbram_ctrl_postw(RegisterInfo *reg, uint64_t val64)
294
+{
295
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
296
+ uint32_t val = val64;
297
+
298
+ if (val & R_BBRAM_CTRL_ZEROIZE_MASK) {
299
+ bbram_zeroize(s);
300
+ /* The bit is self clearing */
301
+ s->regs[R_BBRAM_CTRL] &= ~R_BBRAM_CTRL_ZEROIZE_MASK;
302
+ }
303
+}
304
+
305
+static void bbram_pgm_mode_postw(RegisterInfo *reg, uint64_t val64)
306
+{
307
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
308
+ uint32_t val = val64;
309
+
310
+ if (val == BBRAM_PGM_MAGIC) {
311
+ bbram_zeroize(s);
312
+
313
+ /* The status bit is cleared only by POR */
314
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, PGM_MODE, 1);
315
+ }
316
+}
317
+
318
+static void bbram_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
319
+{
320
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
321
+ uint32_t calc_crc;
322
+
323
+ if (!bbram_pgm_enabled(s)) {
324
+ /* We are not in programming mode, don't do anything */
325
+ return;
326
+ }
327
+
328
+ /* Perform the AES integrity check */
329
+ s->regs[R_BBRAM_STATUS] |= R_BBRAM_STATUS_AES_CRC_DONE_MASK;
330
+
331
+ /*
332
+ * Set check status.
333
+ *
334
+ * ZynqMP BBRAM check has a zero-u32 prepended; see:
335
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_bbramps_zynqmp.c#L311
336
+ */
337
+ calc_crc = xlnx_efuse_calc_crc(&s->regs[R_BBRAM_0],
338
+ (R_BBRAM_8 - R_BBRAM_0), s->crc_zpads);
339
+
340
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, AES_CRC_PASS,
341
+ (s->regs[R_BBRAM_AES_CRC] == calc_crc));
342
+}
343
+
344
+static uint64_t bbram_key_prew(RegisterInfo *reg, uint64_t val64)
345
+{
346
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
347
+ uint32_t original_data = *(uint32_t *) reg->data;
348
+
349
+ if (bbram_pgm_enabled(s)) {
350
+ return val64;
351
+ } else {
352
+ /* We are not in programming mode, don't do anything */
353
+ qemu_log_mask(LOG_GUEST_ERROR,
354
+ "Not in programming mode, dropping the write\n");
355
+ return original_data;
356
+ }
357
+}
358
+
359
+static void bbram_key_postw(RegisterInfo *reg, uint64_t val64)
360
+{
361
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
362
+
363
+ bbram_bdrv_sync(s, reg->access->addr);
364
+}
365
+
366
+static uint64_t bbram_wo_postr(RegisterInfo *reg, uint64_t val)
367
+{
368
+ return 0;
369
+}
370
+
371
+static uint64_t bbram_r8_postr(RegisterInfo *reg, uint64_t val)
372
+{
373
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
374
+
375
+ return s->bbram8_wo ? bbram_wo_postr(reg, val) : val;
376
+}
377
+
378
+static bool bbram_r8_readonly(XlnxBBRam *s)
379
+{
380
+ return !bbram_pgm_enabled(s) || bbram_msw_locked(s);
381
+}
382
+
383
+static uint64_t bbram_r8_prew(RegisterInfo *reg, uint64_t val64)
384
+{
385
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
386
+
387
+ if (bbram_r8_readonly(s)) {
388
+ val64 = *(uint32_t *)reg->data;
389
+ }
390
+
391
+ return val64;
392
+}
393
+
394
+static void bbram_r8_postw(RegisterInfo *reg, uint64_t val64)
395
+{
396
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
397
+
398
+ if (!bbram_r8_readonly(s)) {
399
+ bbram_bdrv_sync(s, A_BBRAM_8);
400
+ }
401
+}
402
+
403
+static uint64_t bbram_msw_lock_prew(RegisterInfo *reg, uint64_t val64)
404
+{
405
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
406
+
407
+ /* Never lock if bbram8 is wo; and, only POR can clear the lock */
408
+ if (s->bbram8_wo) {
409
+ val64 = 0;
410
+ } else {
411
+ val64 |= s->regs[R_BBRAM_MSW_LOCK];
412
+ }
413
+
414
+ return val64;
415
+}
416
+
417
+static void bbram_isr_postw(RegisterInfo *reg, uint64_t val64)
418
+{
419
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
420
+
421
+ bbram_update_irq(s);
422
+}
423
+
424
+static uint64_t bbram_ier_prew(RegisterInfo *reg, uint64_t val64)
425
+{
426
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
427
+ uint32_t val = val64;
428
+
429
+ s->regs[R_BBRAM_IMR] &= ~val;
430
+ bbram_update_irq(s);
431
+ return 0;
432
+}
433
+
434
+static uint64_t bbram_idr_prew(RegisterInfo *reg, uint64_t val64)
435
+{
436
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
437
+ uint32_t val = val64;
438
+
439
+ s->regs[R_BBRAM_IMR] |= val;
440
+ bbram_update_irq(s);
441
+ return 0;
442
+}
443
+
444
+static RegisterAccessInfo bbram_ctrl_regs_info[] = {
445
+ { .name = "BBRAM_STATUS", .addr = A_BBRAM_STATUS,
446
+ .rsvd = 0xee,
447
+ .ro = 0x3ff,
448
+ },{ .name = "BBRAM_CTRL", .addr = A_BBRAM_CTRL,
449
+ .post_write = bbram_ctrl_postw,
450
+ },{ .name = "PGM_MODE", .addr = A_PGM_MODE,
451
+ .post_write = bbram_pgm_mode_postw,
452
+ },{ .name = "BBRAM_AES_CRC", .addr = A_BBRAM_AES_CRC,
453
+ .post_write = bbram_aes_crc_postw,
454
+ .post_read = bbram_wo_postr,
455
+ },{ .name = "BBRAM_0", .addr = A_BBRAM_0,
456
+ .pre_write = bbram_key_prew,
457
+ .post_write = bbram_key_postw,
458
+ .post_read = bbram_wo_postr,
459
+ },{ .name = "BBRAM_1", .addr = A_BBRAM_1,
460
+ .pre_write = bbram_key_prew,
461
+ .post_write = bbram_key_postw,
462
+ .post_read = bbram_wo_postr,
463
+ },{ .name = "BBRAM_2", .addr = A_BBRAM_2,
464
+ .pre_write = bbram_key_prew,
465
+ .post_write = bbram_key_postw,
466
+ .post_read = bbram_wo_postr,
467
+ },{ .name = "BBRAM_3", .addr = A_BBRAM_3,
468
+ .pre_write = bbram_key_prew,
469
+ .post_write = bbram_key_postw,
470
+ .post_read = bbram_wo_postr,
471
+ },{ .name = "BBRAM_4", .addr = A_BBRAM_4,
472
+ .pre_write = bbram_key_prew,
473
+ .post_write = bbram_key_postw,
474
+ .post_read = bbram_wo_postr,
475
+ },{ .name = "BBRAM_5", .addr = A_BBRAM_5,
476
+ .pre_write = bbram_key_prew,
477
+ .post_write = bbram_key_postw,
478
+ .post_read = bbram_wo_postr,
479
+ },{ .name = "BBRAM_6", .addr = A_BBRAM_6,
480
+ .pre_write = bbram_key_prew,
481
+ .post_write = bbram_key_postw,
482
+ .post_read = bbram_wo_postr,
483
+ },{ .name = "BBRAM_7", .addr = A_BBRAM_7,
484
+ .pre_write = bbram_key_prew,
485
+ .post_write = bbram_key_postw,
486
+ .post_read = bbram_wo_postr,
487
+ },{ .name = "BBRAM_8", .addr = A_BBRAM_8,
488
+ .pre_write = bbram_r8_prew,
489
+ .post_write = bbram_r8_postw,
490
+ .post_read = bbram_r8_postr,
491
+ },{ .name = "BBRAM_SLVERR", .addr = A_BBRAM_SLVERR,
492
+ .rsvd = ~1,
493
+ },{ .name = "BBRAM_ISR", .addr = A_BBRAM_ISR,
494
+ .w1c = 0x1,
495
+ .post_write = bbram_isr_postw,
496
+ },{ .name = "BBRAM_IMR", .addr = A_BBRAM_IMR,
497
+ .ro = 0x1,
498
+ },{ .name = "BBRAM_IER", .addr = A_BBRAM_IER,
499
+ .pre_write = bbram_ier_prew,
500
+ },{ .name = "BBRAM_IDR", .addr = A_BBRAM_IDR,
501
+ .pre_write = bbram_idr_prew,
502
+ },{ .name = "BBRAM_MSW_LOCK", .addr = A_BBRAM_MSW_LOCK,
503
+ .pre_write = bbram_msw_lock_prew,
504
+ .ro = ~R_BBRAM_MSW_LOCK_VAL_MASK,
505
+ }
506
+};
507
+
508
+static void bbram_ctrl_reset(DeviceState *dev)
509
+{
510
+ XlnxBBRam *s = XLNX_BBRAM(dev);
511
+ unsigned int i;
512
+
513
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
514
+ if (i < R_BBRAM_0 || i > R_BBRAM_8) {
515
+ register_reset(&s->regs_info[i]);
516
+ }
517
+ }
518
+
519
+ bbram_update_irq(s);
520
+}
521
+
522
+static const MemoryRegionOps bbram_ctrl_ops = {
523
+ .read = register_read_memory,
524
+ .write = register_write_memory,
525
+ .endianness = DEVICE_LITTLE_ENDIAN,
526
+ .valid = {
527
+ .min_access_size = 4,
528
+ .max_access_size = 4,
529
+ },
55
+ },
530
+};
56
+};
531
+
57
+
532
+static void bbram_ctrl_realize(DeviceState *dev, Error **errp)
58
#else
533
+{
59
534
+ XlnxBBRam *s = XLNX_BBRAM(dev);
60
/*
535
+
61
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
536
+ if (s->crc_zpads) {
62
},
537
+ s->bbram8_wo = true;
63
};
538
+ }
64
539
+
65
+/*
540
+ bbram_bdrv_read(s, errp);
66
+ * CNTVCTSS_EL0 has the same trap conditions as CNTVCT_EL0, so it also
541
+}
67
+ * is exposed to userspace by Linux.
542
+
68
+ */
543
+static void bbram_ctrl_init(Object *obj)
69
+static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
544
+{
70
+ { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64,
545
+ XlnxBBRam *s = XLNX_BBRAM(obj);
71
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6,
546
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
72
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
547
+ RegisterInfoArray *reg_array;
73
+ .readfn = gt_virt_cnt_read,
548
+
74
+ },
549
+ reg_array =
550
+ register_init_block32(DEVICE(obj), bbram_ctrl_regs_info,
551
+ ARRAY_SIZE(bbram_ctrl_regs_info),
552
+ s->regs_info, s->regs,
553
+ &bbram_ctrl_ops,
554
+ XLNX_BBRAM_ERR_DEBUG,
555
+ R_MAX * 4);
556
+
557
+ sysbus_init_mmio(sbd, &reg_array->mem);
558
+ sysbus_init_irq(sbd, &s->irq_bbram);
559
+}
560
+
561
+static void bbram_prop_set_drive(Object *obj, Visitor *v, const char *name,
562
+ void *opaque, Error **errp)
563
+{
564
+ DeviceState *dev = DEVICE(obj);
565
+
566
+ qdev_prop_drive.set(obj, v, name, opaque, errp);
567
+
568
+ /* Fill initial data if backend is attached after realized */
569
+ if (dev->realized) {
570
+ bbram_bdrv_read(XLNX_BBRAM(obj), errp);
571
+ }
572
+}
573
+
574
+static void bbram_prop_get_drive(Object *obj, Visitor *v, const char *name,
575
+ void *opaque, Error **errp)
576
+{
577
+ qdev_prop_drive.get(obj, v, name, opaque, errp);
578
+}
579
+
580
+static void bbram_prop_release_drive(Object *obj, const char *name,
581
+ void *opaque)
582
+{
583
+ qdev_prop_drive.release(obj, name, opaque);
584
+}
585
+
586
+static const PropertyInfo bbram_prop_drive = {
587
+ .name = "str",
588
+ .description = "Node name or ID of a block device to use as BBRAM backend",
589
+ .realized_set_allowed = true,
590
+ .get = bbram_prop_get_drive,
591
+ .set = bbram_prop_set_drive,
592
+ .release = bbram_prop_release_drive,
593
+};
75
+};
594
+
76
+
595
+static const VMStateDescription vmstate_bbram_ctrl = {
77
#endif
596
+ .name = TYPE_XLNX_BBRAM,
78
597
+ .version_id = 1,
79
static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
598
+ .minimum_version_id = 1,
80
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
599
+ .fields = (VMStateField[]) {
81
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
600
+ VMSTATE_UINT32_ARRAY(regs, XlnxBBRam, R_MAX),
82
define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
601
+ VMSTATE_END_OF_LIST(),
83
}
84
+ if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
85
+ define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo);
602
+ }
86
+ }
603
+};
87
if (arm_feature(env, ARM_FEATURE_VAPA)) {
604
+
88
ARMCPRegInfo vapa_cp_reginfo[] = {
605
+static Property bbram_ctrl_props[] = {
89
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
606
+ DEFINE_PROP("drive", XlnxBBRam, blk, bbram_prop_drive, BlockBackend *),
607
+ DEFINE_PROP_UINT32("crc-zpads", XlnxBBRam, crc_zpads, 1),
608
+ DEFINE_PROP_END_OF_LIST(),
609
+};
610
+
611
+static void bbram_ctrl_class_init(ObjectClass *klass, void *data)
612
+{
613
+ DeviceClass *dc = DEVICE_CLASS(klass);
614
+
615
+ dc->reset = bbram_ctrl_reset;
616
+ dc->realize = bbram_ctrl_realize;
617
+ dc->vmsd = &vmstate_bbram_ctrl;
618
+ device_class_set_props(dc, bbram_ctrl_props);
619
+}
620
+
621
+static const TypeInfo bbram_ctrl_info = {
622
+ .name = TYPE_XLNX_BBRAM,
623
+ .parent = TYPE_SYS_BUS_DEVICE,
624
+ .instance_size = sizeof(XlnxBBRam),
625
+ .class_init = bbram_ctrl_class_init,
626
+ .instance_init = bbram_ctrl_init,
627
+};
628
+
629
+static void bbram_ctrl_register_types(void)
630
+{
631
+ type_register_static(&bbram_ctrl_info);
632
+}
633
+
634
+type_init(bbram_ctrl_register_types)
635
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
636
index XXXXXXX..XXXXXXX 100644
637
--- a/hw/nvram/Kconfig
638
+++ b/hw/nvram/Kconfig
639
@@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE_VERSAL
640
config XLNX_EFUSE_ZYNQMP
641
bool
642
select XLNX_EFUSE
643
+
644
+config XLNX_BBRAM
645
+ bool
646
+ select XLNX_EFUSE_CRC
647
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
648
index XXXXXXX..XXXXXXX 100644
649
--- a/hw/nvram/meson.build
650
+++ b/hw/nvram/meson.build
651
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
652
'xlnx-versal-efuse-ctrl.c'))
653
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files(
654
'xlnx-zynqmp-efuse.c'))
655
+softmmu_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
656
657
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
658
--
90
--
659
2.20.1
91
2.34.1
660
661
diff view generated by jsdifflib
[PULL 08/22] hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device
[PULL 07/14] target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
1
From: Tong Ho <tong.ho@xilinx.com>
1
When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is
2
implemented. This is similar to the existing CNTVOFF_EL2, except
3
that it controls a hypervisor-adjustable offset made to the physical
4
counter and timer.
2
5
3
Connect the support for Versal eFUSE one-time field-programmable
6
Implement the handling for this register, which includes control/trap
4
bit array.
7
bits in SCR_EL3 and CNTHCTL_EL2.
5
8
6
The command argument:
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
-drive if=pflash,index=1,...
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Can be used to optionally connect the bit array to a
11
Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org
9
backend storage, such that field-programmed values
12
---
10
in one invocation can be made available to next
13
target/arm/cpu-features.h | 5 +++
11
invocation.
14
target/arm/cpu.h | 1 +
15
target/arm/helper.c | 68 +++++++++++++++++++++++++++++++++++++--
16
target/arm/trace-events | 1 +
17
4 files changed, 73 insertions(+), 2 deletions(-)
12
18
13
The backend storage must be a seekable binary file, and
19
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
14
its size must be 3072 bytes or larger. A file with all
15
binary 0's is a 'blank'.
16
17
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
18
Message-id: 20210917052400.1249094-7-tong.ho@xilinx.com
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
include/hw/arm/xlnx-versal.h | 10 +++++++
23
hw/arm/xlnx-versal-virt.c | 52 ++++++++++++++++++++++++++++++++++++
24
hw/arm/xlnx-versal.c | 39 +++++++++++++++++++++++++++
25
hw/arm/Kconfig | 1 +
26
4 files changed, 102 insertions(+)
27
28
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
29
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/xlnx-versal.h
21
--- a/target/arm/cpu-features.h
31
+++ b/include/hw/arm/xlnx-versal.h
22
+++ b/target/arm/cpu-features.h
32
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)
33
#include "hw/usb/xlnx-usb-subsystem.h"
24
return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;
34
#include "hw/misc/xlnx-versal-xramc.h"
35
#include "hw/nvram/xlnx-bbram.h"
36
+#include "hw/nvram/xlnx-versal-efuse.h"
37
38
#define TYPE_XLNX_VERSAL "xlnx-versal"
39
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
40
@@ -XXX,XX +XXX,XX @@ struct Versal {
41
42
XlnxZynqMPRTC rtc;
43
XlnxBBRam bbram;
44
+ XlnxEFuse efuse;
45
+ XlnxVersalEFuseCtrl efuse_ctrl;
46
+ XlnxVersalEFuseCache efuse_cache;
47
} pmc;
48
49
struct {
50
@@ -XXX,XX +XXX,XX @@ struct Versal {
51
#define VERSAL_BBRAM_APB_IRQ_0 121
52
#define VERSAL_RTC_APB_ERR_IRQ 121
53
#define VERSAL_SD0_IRQ_0 126
54
+#define VERSAL_EFUSE_IRQ 139
55
#define VERSAL_RTC_ALARM_IRQ 142
56
#define VERSAL_RTC_SECONDS_IRQ 143
57
58
@@ -XXX,XX +XXX,XX @@ struct Versal {
59
#define MM_PMC_SD0_SIZE 0x10000
60
#define MM_PMC_BBRAM_CTRL 0xf11f0000
61
#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
62
+#define MM_PMC_EFUSE_CTRL 0xf1240000
63
+#define MM_PMC_EFUSE_CTRL_SIZE 0x00104
64
+#define MM_PMC_EFUSE_CACHE 0xf1250000
65
+#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00
66
+
67
#define MM_PMC_CRP 0xf1260000U
68
#define MM_PMC_CRP_SIZE 0x10000
69
#define MM_PMC_RTC 0xf12a0000
70
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/xlnx-versal-virt.c
73
+++ b/hw/arm/xlnx-versal-virt.c
74
@@ -XXX,XX +XXX,XX @@ static void fdt_add_bbram_node(VersalVirt *s)
75
g_free(name);
76
}
25
}
77
26
78
+static void fdt_add_efuse_ctrl_node(VersalVirt *s)
27
+static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id)
79
+{
28
+{
80
+ const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CTRL;
29
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1;
81
+ const char interrupt_names[] = "pmc_efuse";
82
+ char *name = g_strdup_printf("/pmc_efuse@%x", MM_PMC_EFUSE_CTRL);
83
+
84
+ qemu_fdt_add_subnode(s->fdt, name);
85
+
86
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
87
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_EFUSE_IRQ,
88
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
89
+ qemu_fdt_setprop(s->fdt, name, "interrupt-names",
90
+ interrupt_names, sizeof(interrupt_names));
91
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
92
+ 2, MM_PMC_EFUSE_CTRL,
93
+ 2, MM_PMC_EFUSE_CTRL_SIZE);
94
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
95
+ g_free(name);
96
+}
30
+}
97
+
31
+
98
+static void fdt_add_efuse_cache_node(VersalVirt *s)
32
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
33
{
34
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
35
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/cpu.h
38
+++ b/target/arm/cpu.h
39
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
40
uint64_t c14_cntkctl; /* Timer Control register */
41
uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */
42
uint64_t cntvoff_el2; /* Counter Virtual Offset register */
43
+ uint64_t cntpoff_el2; /* Counter Physical Offset register */
44
ARMGenericTimer c14_timer[NUM_GTIMERS];
45
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
46
uint32_t c15_ticonfig; /* TI925T configuration byte. */
47
diff --git a/target/arm/helper.c b/target/arm/helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/helper.c
50
+++ b/target/arm/helper.c
51
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
52
if (cpu_isar_feature(aa64_rme, cpu)) {
53
valid_mask |= SCR_NSE | SCR_GPF;
54
}
55
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
56
+ valid_mask |= SCR_ECVEN;
57
+ }
58
} else {
59
valid_mask &= ~(SCR_RW | SCR_ST);
60
if (cpu_isar_feature(aa32_ras, cpu)) {
61
@@ -XXX,XX +XXX,XX @@ void gt_rme_post_el_change(ARMCPU *cpu, void *ignored)
62
gt_update_irq(cpu, GTIMER_PHYS);
63
}
64
65
+static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
99
+{
66
+{
100
+ const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CACHE;
67
+ if ((env->cp15.scr_el3 & SCR_ECVEN) &&
101
+ char *name = g_strdup_printf("/xlnx_pmc_efuse_cache@%x",
68
+ FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) &&
102
+ MM_PMC_EFUSE_CACHE);
69
+ arm_is_el2_enabled(env) &&
103
+
70
+ (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
104
+ qemu_fdt_add_subnode(s->fdt, name);
71
+ return env->cp15.cntpoff_el2;
105
+
72
+ }
106
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
73
+ return 0;
107
+ 2, MM_PMC_EFUSE_CACHE,
108
+ 2, MM_PMC_EFUSE_CACHE_SIZE);
109
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
110
+ g_free(name);
111
+}
74
+}
112
+
75
+
113
static void fdt_nop_memory_nodes(void *fdt, Error **errp)
76
+static uint64_t gt_phys_cnt_offset(CPUARMState *env)
114
{
115
Error *err = NULL;
116
@@ -XXX,XX +XXX,XX @@ static void bbram_attach_drive(XlnxBBRam *dev)
117
}
118
}
119
120
+static void efuse_attach_drive(XlnxEFuse *dev)
121
+{
77
+{
122
+ DriveInfo *dinfo;
78
+ if (arm_current_el(env) >= 2) {
123
+ BlockBackend *blk;
79
+ return 0;
124
+
125
+ dinfo = drive_get_by_index(IF_PFLASH, 1);
126
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
127
+ if (blk) {
128
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
129
+ }
80
+ }
81
+ return gt_phys_raw_cnt_offset(env);
130
+}
82
+}
131
+
83
+
132
static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
84
static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
133
{
85
{
134
BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
86
ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
135
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
87
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
136
fdt_add_sd_nodes(s);
88
* reset timer to when ISTATUS next has to change
137
fdt_add_rtc_node(s);
89
*/
138
fdt_add_bbram_node(s);
90
uint64_t offset = timeridx == GTIMER_VIRT ?
139
+ fdt_add_efuse_ctrl_node(s);
91
- cpu->env.cp15.cntvoff_el2 : 0;
140
+ fdt_add_efuse_cache_node(s);
92
+ cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env);
141
fdt_add_cpu_nodes(s, psci_conduit);
93
uint64_t count = gt_get_countervalue(&cpu->env);
142
fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
94
/* Note that this must be unsigned 64 bit arithmetic: */
143
fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
95
int istatus = count - offset >= gt->cval;
144
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
96
@@ -XXX,XX +XXX,XX @@ static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
145
/* Attach bbram backend, if given */
97
146
bbram_attach_drive(&s->soc.pmc.bbram);
98
static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
147
99
{
148
+ /* Attach efuse backend, if given */
100
- return gt_get_countervalue(env);
149
+ efuse_attach_drive(&s->soc.pmc.efuse);
101
+ return gt_get_countervalue(env) - gt_phys_cnt_offset(env);
150
+
151
/* Plugin SD cards. */
152
for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
153
sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
154
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
155
index XXXXXXX..XXXXXXX 100644
156
--- a/hw/arm/xlnx-versal.c
157
+++ b/hw/arm/xlnx-versal.c
158
@@ -XXX,XX +XXX,XX @@ static void versal_create_bbram(Versal *s, qemu_irq *pic)
159
sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]);
160
}
102
}
161
103
162
+static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base)
104
static uint64_t gt_virt_cnt_offset(CPUARMState *env)
105
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
106
case GTIMER_HYPVIRT:
107
offset = gt_virt_cnt_offset(env);
108
break;
109
+ case GTIMER_PHYS:
110
+ offset = gt_phys_cnt_offset(env);
111
+ break;
112
}
113
114
return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
115
@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
116
case GTIMER_HYPVIRT:
117
offset = gt_virt_cnt_offset(env);
118
break;
119
+ case GTIMER_PHYS:
120
+ offset = gt_phys_cnt_offset(env);
121
+ break;
122
}
123
124
trace_arm_gt_tval_write(timeridx, value);
125
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
126
R_CNTHCTL_EL1NVVCT_MASK |
127
R_CNTHCTL_EVNTIS_MASK;
128
}
129
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
130
+ valid_mask |= R_CNTHCTL_ECV_MASK;
131
+ }
132
133
/* Clear RES0 bits */
134
value &= valid_mask;
135
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
136
},
137
};
138
139
+static CPAccessResult gt_cntpoff_access(CPUARMState *env,
140
+ const ARMCPRegInfo *ri,
141
+ bool isread)
163
+{
142
+{
164
+ SysBusDevice *part = SYS_BUS_DEVICE(dev);
143
+ if (arm_current_el(env) == 2 && !(env->cp15.scr_el3 & SCR_ECVEN)) {
165
+
144
+ return CP_ACCESS_TRAP_EL3;
166
+ object_property_set_link(OBJECT(part), "efuse",
145
+ }
167
+ OBJECT(&s->pmc.efuse), &error_abort);
146
+ return CP_ACCESS_OK;
168
+
169
+ sysbus_realize(part, &error_abort);
170
+ memory_region_add_subregion(&s->mr_ps, base,
171
+ sysbus_mmio_get_region(part, 0));
172
+}
147
+}
173
+
148
+
174
+static void versal_create_efuse(Versal *s, qemu_irq *pic)
149
+static void gt_cntpoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
150
+ uint64_t value)
175
+{
151
+{
176
+ Object *bits = OBJECT(&s->pmc.efuse);
152
+ ARMCPU *cpu = env_archcpu(env);
177
+ Object *ctrl = OBJECT(&s->pmc.efuse_ctrl);
178
+ Object *cache = OBJECT(&s->pmc.efuse_cache);
179
+
153
+
180
+ object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl,
154
+ trace_arm_gt_cntpoff_write(value);
181
+ TYPE_XLNX_VERSAL_EFUSE_CTRL);
155
+ raw_write(env, ri, value);
182
+
156
+ gt_recalc_timer(cpu, GTIMER_PHYS);
183
+ object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache,
184
+ TYPE_XLNX_VERSAL_EFUSE_CACHE);
185
+
186
+ object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits,
187
+ sizeof(s->pmc.efuse),
188
+ TYPE_XLNX_EFUSE, &error_abort,
189
+ "efuse-nr", "3",
190
+ "efuse-size", "8192",
191
+ NULL);
192
+
193
+ qdev_realize(DEVICE(bits), NULL, &error_abort);
194
+ versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL);
195
+ versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE);
196
+
197
+ sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]);
198
+}
157
+}
199
+
158
+
200
/* This takes the board allocated linear DDR memory and creates aliases
159
+static const ARMCPRegInfo gen_timer_cntpoff_reginfo = {
201
* for each split DDR range/aperture on the Versal address map.
160
+ .name = "CNTPOFF_EL2", .state = ARM_CP_STATE_AA64,
202
*/
161
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 6,
203
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
162
+ .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
204
versal_create_rtc(s, pic);
163
+ .accessfn = gt_cntpoff_access, .writefn = gt_cntpoff_write,
205
versal_create_xrams(s, pic);
164
+ .nv2_redirect_offset = 0x1a8,
206
versal_create_bbram(s, pic);
165
+ .fieldoffset = offsetof(CPUARMState, cp15.cntpoff_el2),
207
+ versal_create_efuse(s, pic);
166
+};
208
versal_map_ddr(s);
167
#else
209
versal_unimp(s);
168
210
169
/*
211
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
170
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
171
if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
172
define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo);
173
}
174
+#ifndef CONFIG_USER_ONLY
175
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
176
+ define_one_arm_cp_reg(cpu, &gen_timer_cntpoff_reginfo);
177
+ }
178
+#endif
179
if (arm_feature(env, ARM_FEATURE_VAPA)) {
180
ARMCPRegInfo vapa_cp_reginfo[] = {
181
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
182
diff --git a/target/arm/trace-events b/target/arm/trace-events
212
index XXXXXXX..XXXXXXX 100644
183
index XXXXXXX..XXXXXXX 100644
213
--- a/hw/arm/Kconfig
184
--- a/target/arm/trace-events
214
+++ b/hw/arm/Kconfig
185
+++ b/target/arm/trace-events
215
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
186
@@ -XXX,XX +XXX,XX @@ arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value 0x%"
216
select XLNX_ZYNQMP
187
arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value 0x%" PRIx64
217
select OR_IRQ
188
arm_gt_imask_toggle(int timer) "gt_ctl_write: timer %d IMASK toggle"
218
select XLNX_BBRAM
189
arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64
219
+ select XLNX_EFUSE_VERSAL
190
+arm_gt_cntpoff_write(uint64_t value) "gt_cntpoff_write: value 0x%" PRIx64
220
191
arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d"
221
config NPCM7XX
192
222
bool
193
# kvm.c
223
--
194
--
224
2.20.1
195
2.34.1
225
226
diff view generated by jsdifflib
[PULL 20/22] qbus: Rename qbus_create() to qbus_new()
[PULL 08/14] target/arm: Enable FEAT_ECV for 'max' CPU
1
Rename the "allocate and return" qbus creation function to
1
Enable all FEAT_ECV features on the 'max' CPU.
2
qbus_new(), to bring it into line with our _init vs _new convention.
3
2
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Corey Minyard <cminyard@mvista.com>
6
Message-id: 20240301183219.2424889-9-peter.maydell@linaro.org
8
Message-id: 20210923121153.23754-6-peter.maydell@linaro.org
9
---
7
---
10
include/hw/qdev-core.h | 2 +-
8
docs/system/arm/emulation.rst | 1 +
11
hw/core/bus.c | 2 +-
9
target/arm/tcg/cpu64.c | 1 +
12
hw/hyperv/vmbus.c | 2 +-
10
2 files changed, 2 insertions(+)
13
hw/i2c/core.c | 2 +-
14
hw/isa/isa-bus.c | 2 +-
15
hw/misc/auxbus.c | 2 +-
16
hw/pci/pci.c | 2 +-
17
hw/ppc/spapr_vio.c | 2 +-
18
hw/s390x/ap-bridge.c | 2 +-
19
hw/s390x/css-bridge.c | 2 +-
20
hw/s390x/s390-pci-bus.c | 2 +-
21
hw/ssi/ssi.c | 2 +-
22
hw/xen/xen-bus.c | 2 +-
23
hw/xen/xen-legacy-backend.c | 2 +-
24
14 files changed, 14 insertions(+), 14 deletions(-)
25
11
26
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
12
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
27
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/qdev-core.h
14
--- a/docs/system/arm/emulation.rst
29
+++ b/include/hw/qdev-core.h
15
+++ b/docs/system/arm/emulation.rst
30
@@ -XXX,XX +XXX,XX @@ typedef int (qdev_walkerfn)(DeviceState *dev, void *opaque);
16
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
31
17
- FEAT_DotProd (Advanced SIMD dot product instructions)
32
void qbus_init(void *bus, size_t size, const char *typename,
18
- FEAT_DoubleFault (Double Fault Extension)
33
DeviceState *parent, const char *name);
19
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
34
-BusState *qbus_create(const char *typename, DeviceState *parent, const char *name);
20
+- FEAT_ECV (Enhanced Counter Virtualization)
35
+BusState *qbus_new(const char *typename, DeviceState *parent, const char *name);
21
- FEAT_EPAC (Enhanced pointer authentication)
36
bool qbus_realize(BusState *bus, Error **errp);
22
- FEAT_ETS (Enhanced Translation Synchronization)
37
void qbus_unrealize(BusState *bus);
23
- FEAT_EVT (Enhanced Virtualization Traps)
38
24
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
39
diff --git a/hw/core/bus.c b/hw/core/bus.c
40
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/core/bus.c
26
--- a/target/arm/tcg/cpu64.c
42
+++ b/hw/core/bus.c
27
+++ b/target/arm/tcg/cpu64.c
43
@@ -XXX,XX +XXX,XX @@ void qbus_init(void *bus, size_t size, const char *typename,
28
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
44
qbus_init_internal(bus, parent, name);
29
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
45
}
30
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
46
31
t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
47
-BusState *qbus_create(const char *typename, DeviceState *parent, const char *name)
32
+ t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */
48
+BusState *qbus_new(const char *typename, DeviceState *parent, const char *name)
33
cpu->isar.id_aa64mmfr0 = t;
49
{
34
50
BusState *bus;
35
t = cpu->isar.id_aa64mmfr1;
51
52
diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/hyperv/vmbus.c
55
+++ b/hw/hyperv/vmbus.c
56
@@ -XXX,XX +XXX,XX @@ static void vmbus_bridge_realize(DeviceState *dev, Error **errp)
57
return;
58
}
59
60
- bridge->bus = VMBUS(qbus_create(TYPE_VMBUS, dev, "vmbus"));
61
+ bridge->bus = VMBUS(qbus_new(TYPE_VMBUS, dev, "vmbus"));
62
}
63
64
static char *vmbus_bridge_ofw_unit_address(const SysBusDevice *dev)
65
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/hw/i2c/core.c
68
+++ b/hw/i2c/core.c
69
@@ -XXX,XX +XXX,XX @@ I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
70
{
71
I2CBus *bus;
72
73
- bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name));
74
+ bus = I2C_BUS(qbus_new(TYPE_I2C_BUS, parent, name));
75
QLIST_INIT(&bus->current_devs);
76
vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_i2c_bus, bus);
77
return bus;
78
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/hw/isa/isa-bus.c
81
+++ b/hw/isa/isa-bus.c
82
@@ -XXX,XX +XXX,XX @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion* address_space,
83
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
84
}
85
86
- isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL));
87
+ isabus = ISA_BUS(qbus_new(TYPE_ISA_BUS, dev, NULL));
88
isabus->address_space = address_space;
89
isabus->address_space_io = address_space_io;
90
return isabus;
91
diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/hw/misc/auxbus.c
94
+++ b/hw/misc/auxbus.c
95
@@ -XXX,XX +XXX,XX @@ AUXBus *aux_bus_init(DeviceState *parent, const char *name)
96
AUXBus *bus;
97
Object *auxtoi2c;
98
99
- bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
100
+ bus = AUX_BUS(qbus_new(TYPE_AUX_BUS, parent, name));
101
auxtoi2c = object_new_with_props(TYPE_AUXTOI2C, OBJECT(bus), "i2c",
102
&error_abort, NULL);
103
104
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/hw/pci/pci.c
107
+++ b/hw/pci/pci.c
108
@@ -XXX,XX +XXX,XX @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
109
{
110
PCIBus *bus;
111
112
- bus = PCI_BUS(qbus_create(typename, parent, name));
113
+ bus = PCI_BUS(qbus_new(typename, parent, name));
114
pci_root_bus_internal_init(bus, parent, address_space_mem,
115
address_space_io, devfn_min);
116
return bus;
117
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/hw/ppc/spapr_vio.c
120
+++ b/hw/ppc/spapr_vio.c
121
@@ -XXX,XX +XXX,XX @@ SpaprVioBus *spapr_vio_bus_init(void)
122
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
123
124
/* Create bus on bridge device */
125
- qbus = qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");
126
+ qbus = qbus_new(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");
127
bus = SPAPR_VIO_BUS(qbus);
128
bus->next_reg = SPAPR_VIO_REG_BASE;
129
130
diff --git a/hw/s390x/ap-bridge.c b/hw/s390x/ap-bridge.c
131
index XXXXXXX..XXXXXXX 100644
132
--- a/hw/s390x/ap-bridge.c
133
+++ b/hw/s390x/ap-bridge.c
134
@@ -XXX,XX +XXX,XX @@ void s390_init_ap(void)
135
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
136
137
/* Create bus on bridge device */
138
- bus = qbus_create(TYPE_AP_BUS, dev, TYPE_AP_BUS);
139
+ bus = qbus_new(TYPE_AP_BUS, dev, TYPE_AP_BUS);
140
141
/* Enable hotplugging */
142
qbus_set_hotplug_handler(bus, OBJECT(dev));
143
diff --git a/hw/s390x/css-bridge.c b/hw/s390x/css-bridge.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/hw/s390x/css-bridge.c
146
+++ b/hw/s390x/css-bridge.c
147
@@ -XXX,XX +XXX,XX @@ VirtualCssBus *virtual_css_bus_init(void)
148
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
149
150
/* Create bus on bridge device */
151
- bus = qbus_create(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css");
152
+ bus = qbus_new(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css");
153
cbus = VIRTUAL_CSS_BUS(bus);
154
155
/* Enable hotplugging */
156
diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c
157
index XXXXXXX..XXXXXXX 100644
158
--- a/hw/s390x/s390-pci-bus.c
159
+++ b/hw/s390x/s390-pci-bus.c
160
@@ -XXX,XX +XXX,XX @@ static void s390_pcihost_realize(DeviceState *dev, Error **errp)
161
qbus_set_hotplug_handler(bus, OBJECT(dev));
162
phb->bus = b;
163
164
- s->bus = S390_PCI_BUS(qbus_create(TYPE_S390_PCI_BUS, dev, NULL));
165
+ s->bus = S390_PCI_BUS(qbus_new(TYPE_S390_PCI_BUS, dev, NULL));
166
qbus_set_hotplug_handler(BUS(s->bus), OBJECT(dev));
167
168
s->iommu_table = g_hash_table_new_full(g_int64_hash, g_int64_equal,
169
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
170
index XXXXXXX..XXXXXXX 100644
171
--- a/hw/ssi/ssi.c
172
+++ b/hw/ssi/ssi.c
173
@@ -XXX,XX +XXX,XX @@ DeviceState *ssi_create_peripheral(SSIBus *bus, const char *name)
174
SSIBus *ssi_create_bus(DeviceState *parent, const char *name)
175
{
176
BusState *bus;
177
- bus = qbus_create(TYPE_SSI_BUS, parent, name);
178
+ bus = qbus_new(TYPE_SSI_BUS, parent, name);
179
return SSI_BUS(bus);
180
}
181
182
diff --git a/hw/xen/xen-bus.c b/hw/xen/xen-bus.c
183
index XXXXXXX..XXXXXXX 100644
184
--- a/hw/xen/xen-bus.c
185
+++ b/hw/xen/xen-bus.c
186
@@ -XXX,XX +XXX,XX @@ type_init(xen_register_types)
187
void xen_bus_init(void)
188
{
189
DeviceState *dev = qdev_new(TYPE_XEN_BRIDGE);
190
- BusState *bus = qbus_create(TYPE_XEN_BUS, dev, NULL);
191
+ BusState *bus = qbus_new(TYPE_XEN_BUS, dev, NULL);
192
193
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
194
qbus_set_bus_hotplug_handler(bus);
195
diff --git a/hw/xen/xen-legacy-backend.c b/hw/xen/xen-legacy-backend.c
196
index XXXXXXX..XXXXXXX 100644
197
--- a/hw/xen/xen-legacy-backend.c
198
+++ b/hw/xen/xen-legacy-backend.c
199
@@ -XXX,XX +XXX,XX @@ int xen_be_init(void)
200
201
xen_sysdev = qdev_new(TYPE_XENSYSDEV);
202
sysbus_realize_and_unref(SYS_BUS_DEVICE(xen_sysdev), &error_fatal);
203
- xen_sysbus = qbus_create(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus");
204
+ xen_sysbus = qbus_new(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus");
205
qbus_set_bus_hotplug_handler(xen_sysbus);
206
207
return 0;
208
--
36
--
209
2.20.1
37
2.34.1
210
38
211
39
diff view generated by jsdifflib
[PULL 05/22] hw/nvram: Introduce Xilinx ZynqMP eFuse device
[PULL 09/14] hw/gpio: Implement STM32L4x5 GPIO
1
From: Tong Ho <tong.ho@xilinx.com>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
This implements the Xilinx ZynqMP eFuse, an one-time
3
Features supported :
4
field-programmable non-volatile storage device. There is
4
- the 8 STM32L4x5 GPIOs are initialized with their reset values
5
only one such device in the Xilinx ZynqMP product family.
5
(except IDR, see below)
6
- input mode : setting a pin in input mode "externally" (using input
7
irqs) results in an out irq (transmitted to SYSCFG)
8
- output mode : setting a bit in ODR sets the corresponding out irq
9
(if this line is configured in output mode)
10
- pull-up, pull-down
11
- push-pull, open-drain
6
12
7
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
13
Difference with the real GPIOs :
8
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
14
- Alternate Function and Analog mode aren't implemented :
15
pins in AF/Analog behave like pins in input mode
16
- floating pins stay at their last value
17
- register IDR reset values differ from the real one :
18
values are coherent with the other registers reset values
19
and the fact that AF/Analog modes aren't implemented
20
- setting I/O output speed isn't supported
21
- locking port bits isn't supported
22
- ADC function isn't supported
23
- GPIOH has 16 pins instead of 2 pins
24
- writing to registers LCKR, AFRL, AFRH and ASCR is ineffective
9
25
10
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
26
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
11
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
27
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
12
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Message-id: 20210917052400.1249094-4-tong.ho@xilinx.com
29
Acked-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
30
Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
32
---
17
include/hw/nvram/xlnx-zynqmp-efuse.h | 44 ++
33
MAINTAINERS | 1 +
18
hw/nvram/xlnx-zynqmp-efuse.c | 855 +++++++++++++++++++++++++++
34
docs/system/arm/b-l475e-iot01a.rst | 2 +-
19
hw/nvram/Kconfig | 4 +
35
include/hw/gpio/stm32l4x5_gpio.h | 70 +++++
20
hw/nvram/meson.build | 2 +
36
hw/gpio/stm32l4x5_gpio.c | 477 +++++++++++++++++++++++++++++
21
4 files changed, 905 insertions(+)
37
hw/gpio/Kconfig | 3 +
22
create mode 100644 include/hw/nvram/xlnx-zynqmp-efuse.h
38
hw/gpio/meson.build | 1 +
23
create mode 100644 hw/nvram/xlnx-zynqmp-efuse.c
39
hw/gpio/trace-events | 6 +
40
7 files changed, 559 insertions(+), 1 deletion(-)
41
create mode 100644 include/hw/gpio/stm32l4x5_gpio.h
42
create mode 100644 hw/gpio/stm32l4x5_gpio.c
24
43
25
diff --git a/include/hw/nvram/xlnx-zynqmp-efuse.h b/include/hw/nvram/xlnx-zynqmp-efuse.h
44
diff --git a/MAINTAINERS b/MAINTAINERS
45
index XXXXXXX..XXXXXXX 100644
46
--- a/MAINTAINERS
47
+++ b/MAINTAINERS
48
@@ -XXX,XX +XXX,XX @@ F: hw/arm/stm32l4x5_soc.c
49
F: hw/misc/stm32l4x5_exti.c
50
F: hw/misc/stm32l4x5_syscfg.c
51
F: hw/misc/stm32l4x5_rcc.c
52
+F: hw/gpio/stm32l4x5_gpio.c
53
F: include/hw/*/stm32l4x5_*.h
54
55
B-L475E-IOT01A IoT Node
56
diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst
57
index XXXXXXX..XXXXXXX 100644
58
--- a/docs/system/arm/b-l475e-iot01a.rst
59
+++ b/docs/system/arm/b-l475e-iot01a.rst
60
@@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices:
61
- STM32L4x5 EXTI (Extended interrupts and events controller)
62
- STM32L4x5 SYSCFG (System configuration controller)
63
- STM32L4x5 RCC (Reset and clock control)
64
+- STM32L4x5 GPIOs (General-purpose I/Os)
65
66
Missing devices
67
"""""""""""""""
68
@@ -XXX,XX +XXX,XX @@ Missing devices
69
The B-L475E-IOT01A does *not* support the following devices:
70
71
- Serial ports (UART)
72
-- General-purpose I/Os (GPIO)
73
- Analog to Digital Converter (ADC)
74
- SPI controller
75
- Timer controller (TIMER)
76
diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h
26
new file mode 100644
77
new file mode 100644
27
index XXXXXXX..XXXXXXX
78
index XXXXXXX..XXXXXXX
28
--- /dev/null
79
--- /dev/null
29
+++ b/include/hw/nvram/xlnx-zynqmp-efuse.h
80
+++ b/include/hw/gpio/stm32l4x5_gpio.h
30
@@ -XXX,XX +XXX,XX @@
81
@@ -XXX,XX +XXX,XX @@
31
+/*
82
+/*
32
+ * Copyright (c) 2021 Xilinx Inc.
83
+ * STM32L4x5 GPIO (General Purpose Input/Ouput)
33
+ *
84
+ *
34
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
85
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
35
+ * of this software and associated documentation files (the "Software"), to deal
86
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
36
+ * in the Software without restriction, including without limitation the rights
37
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
38
+ * copies of the Software, and to permit persons to whom the Software is
39
+ * furnished to do so, subject to the following conditions:
40
+ *
87
+ *
41
+ * The above copyright notice and this permission notice shall be included in
88
+ * SPDX-License-Identifier: GPL-2.0-or-later
42
+ * all copies or substantial portions of the Software.
43
+ *
89
+ *
44
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
90
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
45
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
91
+ * See the COPYING file in the top-level directory.
46
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
47
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
48
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
49
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
50
+ * THE SOFTWARE.
51
+ */
92
+ */
52
+#ifndef XLNX_ZYNQMP_EFUSE_H
93
+
53
+#define XLNX_ZYNQMP_EFUSE_H
94
+/*
54
+
95
+ * The reference used is the STMicroElectronics RM0351 Reference manual
55
+#include "hw/irq.h"
96
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
97
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
98
+ */
99
+
100
+#ifndef HW_STM32L4X5_GPIO_H
101
+#define HW_STM32L4X5_GPIO_H
102
+
56
+#include "hw/sysbus.h"
103
+#include "hw/sysbus.h"
57
+#include "hw/register.h"
104
+#include "qom/object.h"
58
+#include "hw/nvram/xlnx-efuse.h"
105
+
59
+
106
+#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
60
+#define XLNX_ZYNQMP_EFUSE_R_MAX ((0x10fc / 4) + 1)
107
+OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
61
+
108
+
62
+#define TYPE_XLNX_ZYNQMP_EFUSE "xlnx,zynqmp-efuse"
109
+#define GPIO_NUM_PINS 16
63
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPEFuse, XLNX_ZYNQMP_EFUSE);
110
+
64
+
111
+struct Stm32l4x5GpioState {
65
+struct XlnxZynqMPEFuse {
66
+ SysBusDevice parent_obj;
112
+ SysBusDevice parent_obj;
67
+ qemu_irq irq;
113
+
68
+
114
+ MemoryRegion mmio;
69
+ XlnxEFuse *efuse;
115
+
70
+ uint32_t regs[XLNX_ZYNQMP_EFUSE_R_MAX];
116
+ /* GPIO registers */
71
+ RegisterInfo regs_info[XLNX_ZYNQMP_EFUSE_R_MAX];
117
+ uint32_t moder;
118
+ uint32_t otyper;
119
+ uint32_t ospeedr;
120
+ uint32_t pupdr;
121
+ uint32_t idr;
122
+ uint32_t odr;
123
+ uint32_t lckr;
124
+ uint32_t afrl;
125
+ uint32_t afrh;
126
+ uint32_t ascr;
127
+
128
+ /* GPIO registers reset values */
129
+ uint32_t moder_reset;
130
+ uint32_t ospeedr_reset;
131
+ uint32_t pupdr_reset;
132
+
133
+ /*
134
+ * External driving of pins.
135
+ * The pins can be set externally through the device
136
+ * anonymous input GPIOs lines under certain conditions.
137
+ * The pin must not be in push-pull output mode,
138
+ * and can't be set high in open-drain mode.
139
+ * Pins driven externally and configured to
140
+ * output mode will in general be "disconnected"
141
+ * (see `get_gpio_pinmask_to_disconnect()`)
142
+ */
143
+ uint16_t disconnected_pins;
144
+ uint16_t pins_connected_high;
145
+
146
+ char *name;
147
+ Clock *clk;
148
+ qemu_irq pin[GPIO_NUM_PINS];
72
+};
149
+};
73
+
150
+
74
+#endif
151
+#endif
75
diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c
152
diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c
76
new file mode 100644
153
new file mode 100644
77
index XXXXXXX..XXXXXXX
154
index XXXXXXX..XXXXXXX
78
--- /dev/null
155
--- /dev/null
79
+++ b/hw/nvram/xlnx-zynqmp-efuse.c
156
+++ b/hw/gpio/stm32l4x5_gpio.c
80
@@ -XXX,XX +XXX,XX @@
157
@@ -XXX,XX +XXX,XX @@
81
+/*
158
+/*
82
+ * QEMU model of the ZynqMP eFuse
159
+ * STM32L4x5 GPIO (General Purpose Input/Ouput)
83
+ *
160
+ *
84
+ * Copyright (c) 2015 Xilinx Inc.
161
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
162
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
85
+ *
163
+ *
86
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
164
+ * SPDX-License-Identifier: GPL-2.0-or-later
87
+ *
165
+ *
88
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
166
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
89
+ * of this software and associated documentation files (the "Software"), to deal
167
+ * See the COPYING file in the top-level directory.
90
+ * in the Software without restriction, including without limitation the rights
91
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
92
+ * copies of the Software, and to permit persons to whom the Software is
93
+ * furnished to do so, subject to the following conditions:
94
+ *
95
+ * The above copyright notice and this permission notice shall be included in
96
+ * all copies or substantial portions of the Software.
97
+ *
98
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
99
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
100
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
101
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
102
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
103
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
104
+ * THE SOFTWARE.
105
+ */
168
+ */
106
+
169
+
170
+/*
171
+ * The reference used is the STMicroElectronics RM0351 Reference manual
172
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
173
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
174
+ */
175
+
107
+#include "qemu/osdep.h"
176
+#include "qemu/osdep.h"
108
+#include "hw/nvram/xlnx-zynqmp-efuse.h"
109
+
110
+#include "qemu/log.h"
177
+#include "qemu/log.h"
178
+#include "hw/gpio/stm32l4x5_gpio.h"
179
+#include "hw/irq.h"
180
+#include "hw/qdev-clock.h"
181
+#include "hw/qdev-properties.h"
182
+#include "qapi/visitor.h"
111
+#include "qapi/error.h"
183
+#include "qapi/error.h"
112
+#include "migration/vmstate.h"
184
+#include "migration/vmstate.h"
113
+#include "hw/qdev-properties.h"
185
+#include "trace.h"
114
+
186
+
115
+#ifndef ZYNQMP_EFUSE_ERR_DEBUG
187
+#define GPIO_MODER 0x00
116
+#define ZYNQMP_EFUSE_ERR_DEBUG 0
188
+#define GPIO_OTYPER 0x04
117
+#endif
189
+#define GPIO_OSPEEDR 0x08
118
+
190
+#define GPIO_PUPDR 0x0C
119
+REG32(WR_LOCK, 0x0)
191
+#define GPIO_IDR 0x10
120
+ FIELD(WR_LOCK, LOCK, 0, 16)
192
+#define GPIO_ODR 0x14
121
+REG32(CFG, 0x4)
193
+#define GPIO_BSRR 0x18
122
+ FIELD(CFG, SLVERR_ENABLE, 5, 1)
194
+#define GPIO_LCKR 0x1C
123
+ FIELD(CFG, MARGIN_RD, 2, 2)
195
+#define GPIO_AFRL 0x20
124
+ FIELD(CFG, PGM_EN, 1, 1)
196
+#define GPIO_AFRH 0x24
125
+ FIELD(CFG, EFUSE_CLK_SEL, 0, 1)
197
+#define GPIO_BRR 0x28
126
+REG32(STATUS, 0x8)
198
+#define GPIO_ASCR 0x2C
127
+ FIELD(STATUS, AES_CRC_PASS, 7, 1)
199
+
128
+ FIELD(STATUS, AES_CRC_DONE, 6, 1)
200
+/* 0b11111111_11111111_00000000_00000000 */
129
+ FIELD(STATUS, CACHE_DONE, 5, 1)
201
+#define RESERVED_BITS_MASK 0xFFFF0000
130
+ FIELD(STATUS, CACHE_LOAD, 4, 1)
202
+
131
+ FIELD(STATUS, EFUSE_3_TBIT, 2, 1)
203
+static void update_gpio_idr(Stm32l4x5GpioState *s);
132
+ FIELD(STATUS, EFUSE_2_TBIT, 1, 1)
204
+
133
+ FIELD(STATUS, EFUSE_0_TBIT, 0, 1)
205
+static bool is_pull_up(Stm32l4x5GpioState *s, unsigned pin)
134
+REG32(EFUSE_PGM_ADDR, 0xc)
206
+{
135
+ FIELD(EFUSE_PGM_ADDR, EFUSE, 11, 2)
207
+ return extract32(s->pupdr, 2 * pin, 2) == 1;
136
+ FIELD(EFUSE_PGM_ADDR, ROW, 5, 6)
208
+}
137
+ FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5)
209
+
138
+REG32(EFUSE_RD_ADDR, 0x10)
210
+static bool is_pull_down(Stm32l4x5GpioState *s, unsigned pin)
139
+ FIELD(EFUSE_RD_ADDR, EFUSE, 11, 2)
211
+{
140
+ FIELD(EFUSE_RD_ADDR, ROW, 5, 6)
212
+ return extract32(s->pupdr, 2 * pin, 2) == 2;
141
+REG32(EFUSE_RD_DATA, 0x14)
213
+}
142
+REG32(TPGM, 0x18)
214
+
143
+ FIELD(TPGM, VALUE, 0, 16)
215
+static bool is_output(Stm32l4x5GpioState *s, unsigned pin)
144
+REG32(TRD, 0x1c)
216
+{
145
+ FIELD(TRD, VALUE, 0, 8)
217
+ return extract32(s->moder, 2 * pin, 2) == 1;
146
+REG32(TSU_H_PS, 0x20)
218
+}
147
+ FIELD(TSU_H_PS, VALUE, 0, 8)
219
+
148
+REG32(TSU_H_PS_CS, 0x24)
220
+static bool is_open_drain(Stm32l4x5GpioState *s, unsigned pin)
149
+ FIELD(TSU_H_PS_CS, VALUE, 0, 8)
221
+{
150
+REG32(TSU_H_CS, 0x2c)
222
+ return extract32(s->otyper, pin, 1) == 1;
151
+ FIELD(TSU_H_CS, VALUE, 0, 4)
223
+}
152
+REG32(EFUSE_ISR, 0x30)
224
+
153
+ FIELD(EFUSE_ISR, APB_SLVERR, 31, 1)
225
+static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin)
154
+ FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1)
226
+{
155
+ FIELD(EFUSE_ISR, RD_ERROR, 3, 1)
227
+ return extract32(s->otyper, pin, 1) == 0;
156
+ FIELD(EFUSE_ISR, RD_DONE, 2, 1)
228
+}
157
+ FIELD(EFUSE_ISR, PGM_ERROR, 1, 1)
229
+
158
+ FIELD(EFUSE_ISR, PGM_DONE, 0, 1)
230
+static void stm32l4x5_gpio_reset_hold(Object *obj)
159
+REG32(EFUSE_IMR, 0x34)
231
+{
160
+ FIELD(EFUSE_IMR, APB_SLVERR, 31, 1)
232
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
161
+ FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1)
233
+
162
+ FIELD(EFUSE_IMR, RD_ERROR, 3, 1)
234
+ s->moder = s->moder_reset;
163
+ FIELD(EFUSE_IMR, RD_DONE, 2, 1)
235
+ s->otyper = 0x00000000;
164
+ FIELD(EFUSE_IMR, PGM_ERROR, 1, 1)
236
+ s->ospeedr = s->ospeedr_reset;
165
+ FIELD(EFUSE_IMR, PGM_DONE, 0, 1)
237
+ s->pupdr = s->pupdr_reset;
166
+REG32(EFUSE_IER, 0x38)
238
+ s->idr = 0x00000000;
167
+ FIELD(EFUSE_IER, APB_SLVERR, 31, 1)
239
+ s->odr = 0x00000000;
168
+ FIELD(EFUSE_IER, CACHE_ERROR, 4, 1)
240
+ s->lckr = 0x00000000;
169
+ FIELD(EFUSE_IER, RD_ERROR, 3, 1)
241
+ s->afrl = 0x00000000;
170
+ FIELD(EFUSE_IER, RD_DONE, 2, 1)
242
+ s->afrh = 0x00000000;
171
+ FIELD(EFUSE_IER, PGM_ERROR, 1, 1)
243
+ s->ascr = 0x00000000;
172
+ FIELD(EFUSE_IER, PGM_DONE, 0, 1)
244
+
173
+REG32(EFUSE_IDR, 0x3c)
245
+ s->disconnected_pins = 0xFFFF;
174
+ FIELD(EFUSE_IDR, APB_SLVERR, 31, 1)
246
+ s->pins_connected_high = 0x0000;
175
+ FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1)
247
+ update_gpio_idr(s);
176
+ FIELD(EFUSE_IDR, RD_ERROR, 3, 1)
248
+}
177
+ FIELD(EFUSE_IDR, RD_DONE, 2, 1)
249
+
178
+ FIELD(EFUSE_IDR, PGM_ERROR, 1, 1)
250
+static void stm32l4x5_gpio_set(void *opaque, int line, int level)
179
+ FIELD(EFUSE_IDR, PGM_DONE, 0, 1)
251
+{
180
+REG32(EFUSE_CACHE_LOAD, 0x40)
252
+ Stm32l4x5GpioState *s = opaque;
181
+ FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1)
253
+ /*
182
+REG32(EFUSE_PGM_LOCK, 0x44)
254
+ * The pin isn't set if line is configured in output mode
183
+ FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1)
255
+ * except if level is 0 and the output is open-drain.
184
+REG32(EFUSE_AES_CRC, 0x48)
256
+ * This way there will be no short-circuit prone situations.
185
+REG32(EFUSE_TBITS_PRGRMG_EN, 0x100)
257
+ */
186
+ FIELD(EFUSE_TBITS_PRGRMG_EN, TBITS_PRGRMG_EN, 3, 1)
258
+ if (is_output(s, line) && !(is_open_drain(s, line) && (level == 0))) {
187
+REG32(DNA_0, 0x100c)
259
+ qemu_log_mask(LOG_GUEST_ERROR, "Line %d can't be driven externally\n",
188
+REG32(DNA_1, 0x1010)
260
+ line);
189
+REG32(DNA_2, 0x1014)
261
+ return;
190
+REG32(IPDISABLE, 0x1018)
262
+ }
191
+ FIELD(IPDISABLE, VCU_DIS, 8, 1)
263
+
192
+ FIELD(IPDISABLE, GPU_DIS, 5, 1)
264
+ s->disconnected_pins &= ~(1 << line);
193
+ FIELD(IPDISABLE, APU3_DIS, 3, 1)
265
+ if (level) {
194
+ FIELD(IPDISABLE, APU2_DIS, 2, 1)
266
+ s->pins_connected_high |= (1 << line);
195
+ FIELD(IPDISABLE, APU1_DIS, 1, 1)
267
+ } else {
196
+ FIELD(IPDISABLE, APU0_DIS, 0, 1)
268
+ s->pins_connected_high &= ~(1 << line);
197
+REG32(SYSOSC_CTRL, 0x101c)
269
+ }
198
+ FIELD(SYSOSC_CTRL, SYSOSC_EN, 0, 1)
270
+ trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
199
+REG32(USER_0, 0x1020)
271
+ s->pins_connected_high);
200
+REG32(USER_1, 0x1024)
272
+ update_gpio_idr(s);
201
+REG32(USER_2, 0x1028)
273
+}
202
+REG32(USER_3, 0x102c)
274
+
203
+REG32(USER_4, 0x1030)
275
+
204
+REG32(USER_5, 0x1034)
276
+static void update_gpio_idr(Stm32l4x5GpioState *s)
205
+REG32(USER_6, 0x1038)
277
+{
206
+REG32(USER_7, 0x103c)
278
+ uint32_t new_idr_mask = 0;
207
+REG32(MISC_USER_CTRL, 0x1040)
279
+ uint32_t new_idr = s->odr;
208
+ FIELD(MISC_USER_CTRL, FPD_SC_EN_0, 14, 1)
280
+ uint32_t old_idr = s->idr;
209
+ FIELD(MISC_USER_CTRL, LPD_SC_EN_0, 11, 1)
281
+ int new_pin_state, old_pin_state;
210
+ FIELD(MISC_USER_CTRL, LBIST_EN, 10, 1)
282
+
211
+ FIELD(MISC_USER_CTRL, USR_WRLK_7, 7, 1)
283
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
212
+ FIELD(MISC_USER_CTRL, USR_WRLK_6, 6, 1)
284
+ if (is_output(s, i)) {
213
+ FIELD(MISC_USER_CTRL, USR_WRLK_5, 5, 1)
285
+ if (is_push_pull(s, i)) {
214
+ FIELD(MISC_USER_CTRL, USR_WRLK_4, 4, 1)
286
+ new_idr_mask |= (1 << i);
215
+ FIELD(MISC_USER_CTRL, USR_WRLK_3, 3, 1)
287
+ } else if (!(s->odr & (1 << i))) {
216
+ FIELD(MISC_USER_CTRL, USR_WRLK_2, 2, 1)
288
+ /* open-drain ODR 0 */
217
+ FIELD(MISC_USER_CTRL, USR_WRLK_1, 1, 1)
289
+ new_idr_mask |= (1 << i);
218
+ FIELD(MISC_USER_CTRL, USR_WRLK_0, 0, 1)
290
+ /* open-drain ODR 1 */
219
+REG32(ROM_RSVD, 0x1044)
291
+ } else if (!(s->disconnected_pins & (1 << i)) &&
220
+ FIELD(ROM_RSVD, PBR_BOOT_ERROR, 0, 3)
292
+ !(s->pins_connected_high & (1 << i))) {
221
+REG32(PUF_CHASH, 0x1050)
293
+ /* open-drain ODR 1 with pin connected low */
222
+REG32(PUF_MISC, 0x1054)
294
+ new_idr_mask |= (1 << i);
223
+ FIELD(PUF_MISC, REGISTER_DIS, 31, 1)
295
+ new_idr &= ~(1 << i);
224
+ FIELD(PUF_MISC, SYN_WRLK, 30, 1)
296
+ /* open-drain ODR 1 with unactive pin */
225
+ FIELD(PUF_MISC, SYN_INVLD, 29, 1)
297
+ } else if (is_pull_up(s, i)) {
226
+ FIELD(PUF_MISC, TEST2_DIS, 28, 1)
298
+ new_idr_mask |= (1 << i);
227
+ FIELD(PUF_MISC, UNUSED27, 27, 1)
299
+ } else if (is_pull_down(s, i)) {
228
+ FIELD(PUF_MISC, UNUSED26, 26, 1)
300
+ new_idr_mask |= (1 << i);
229
+ FIELD(PUF_MISC, UNUSED25, 25, 1)
301
+ new_idr &= ~(1 << i);
230
+ FIELD(PUF_MISC, UNUSED24, 24, 1)
302
+ }
231
+ FIELD(PUF_MISC, AUX, 0, 24)
303
+ /*
232
+REG32(SEC_CTRL, 0x1058)
304
+ * The only case left is for open-drain ODR 1
233
+ FIELD(SEC_CTRL, PPK1_INVLD, 30, 2)
305
+ * with unactive pin without pull-up or pull-down :
234
+ FIELD(SEC_CTRL, PPK1_WRLK, 29, 1)
306
+ * the value is floating.
235
+ FIELD(SEC_CTRL, PPK0_INVLD, 27, 2)
307
+ */
236
+ FIELD(SEC_CTRL, PPK0_WRLK, 26, 1)
308
+ /* input or analog mode with connected pin */
237
+ FIELD(SEC_CTRL, RSA_EN, 11, 15)
309
+ } else if (!(s->disconnected_pins & (1 << i))) {
238
+ FIELD(SEC_CTRL, SEC_LOCK, 10, 1)
310
+ if (s->pins_connected_high & (1 << i)) {
239
+ FIELD(SEC_CTRL, PROG_GATE_2, 9, 1)
311
+ /* pin high */
240
+ FIELD(SEC_CTRL, PROG_GATE_1, 8, 1)
312
+ new_idr_mask |= (1 << i);
241
+ FIELD(SEC_CTRL, PROG_GATE_0, 7, 1)
313
+ new_idr |= (1 << i);
242
+ FIELD(SEC_CTRL, DFT_DIS, 6, 1)
314
+ } else {
243
+ FIELD(SEC_CTRL, JTAG_DIS, 5, 1)
315
+ /* pin low */
244
+ FIELD(SEC_CTRL, ERROR_DIS, 4, 1)
316
+ new_idr_mask |= (1 << i);
245
+ FIELD(SEC_CTRL, BBRAM_DIS, 3, 1)
317
+ new_idr &= ~(1 << i);
246
+ FIELD(SEC_CTRL, ENC_ONLY, 2, 1)
318
+ }
247
+ FIELD(SEC_CTRL, AES_WRLK, 1, 1)
319
+ /* input or analog mode with disconnected pin */
248
+ FIELD(SEC_CTRL, AES_RDLK, 0, 1)
320
+ } else {
249
+REG32(SPK_ID, 0x105c)
321
+ if (is_pull_up(s, i)) {
250
+REG32(PPK0_0, 0x10a0)
322
+ /* pull-up */
251
+REG32(PPK0_1, 0x10a4)
323
+ new_idr_mask |= (1 << i);
252
+REG32(PPK0_2, 0x10a8)
324
+ new_idr |= (1 << i);
253
+REG32(PPK0_3, 0x10ac)
325
+ } else if (is_pull_down(s, i)) {
254
+REG32(PPK0_4, 0x10b0)
326
+ /* pull-down */
255
+REG32(PPK0_5, 0x10b4)
327
+ new_idr_mask |= (1 << i);
256
+REG32(PPK0_6, 0x10b8)
328
+ new_idr &= ~(1 << i);
257
+REG32(PPK0_7, 0x10bc)
329
+ }
258
+REG32(PPK0_8, 0x10c0)
330
+ /*
259
+REG32(PPK0_9, 0x10c4)
331
+ * The only case left is for a disconnected pin
260
+REG32(PPK0_10, 0x10c8)
332
+ * without pull-up or pull-down :
261
+REG32(PPK0_11, 0x10cc)
333
+ * the value is floating.
262
+REG32(PPK1_0, 0x10d0)
334
+ */
263
+REG32(PPK1_1, 0x10d4)
335
+ }
264
+REG32(PPK1_2, 0x10d8)
336
+ }
265
+REG32(PPK1_3, 0x10dc)
337
+
266
+REG32(PPK1_4, 0x10e0)
338
+ s->idr = (old_idr & ~new_idr_mask) | (new_idr & new_idr_mask);
267
+REG32(PPK1_5, 0x10e4)
339
+ trace_stm32l4x5_gpio_update_idr(s->name, old_idr, s->idr);
268
+REG32(PPK1_6, 0x10e8)
340
+
269
+REG32(PPK1_7, 0x10ec)
341
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
270
+REG32(PPK1_8, 0x10f0)
342
+ if (new_idr_mask & (1 << i)) {
271
+REG32(PPK1_9, 0x10f4)
343
+ new_pin_state = (new_idr & (1 << i)) > 0;
272
+REG32(PPK1_10, 0x10f8)
344
+ old_pin_state = (old_idr & (1 << i)) > 0;
273
+REG32(PPK1_11, 0x10fc)
345
+ if (new_pin_state > old_pin_state) {
274
+
346
+ qemu_irq_raise(s->pin[i]);
275
+#define BIT_POS(ROW, COLUMN) (ROW * 32 + COLUMN)
347
+ } else if (new_pin_state < old_pin_state) {
276
+#define R_MAX (R_PPK1_11 + 1)
348
+ qemu_irq_lower(s->pin[i]);
277
+
349
+ }
278
+/* #define EFUSE_XOSC 26 */
350
+ }
351
+ }
352
+}
279
+
353
+
280
+/*
354
+/*
281
+ * eFUSE layout references:
355
+ * Return mask of pins that are both configured in output
282
+ * ZynqMP: UG1085 (v2.1) August 21, 2019, p.277, Table 12-13
356
+ * mode and externally driven (except pins in open-drain
357
+ * mode externally set to 0).
283
+ */
358
+ */
284
+#define EFUSE_AES_RDLK BIT_POS(22, 0)
359
+static uint32_t get_gpio_pinmask_to_disconnect(Stm32l4x5GpioState *s)
285
+#define EFUSE_AES_WRLK BIT_POS(22, 1)
360
+{
286
+#define EFUSE_ENC_ONLY BIT_POS(22, 2)
361
+ uint32_t pins_to_disconnect = 0;
287
+#define EFUSE_BBRAM_DIS BIT_POS(22, 3)
362
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
288
+#define EFUSE_ERROR_DIS BIT_POS(22, 4)
363
+ /* for each connected pin in output mode */
289
+#define EFUSE_JTAG_DIS BIT_POS(22, 5)
364
+ if (!(s->disconnected_pins & (1 << i)) && is_output(s, i)) {
290
+#define EFUSE_DFT_DIS BIT_POS(22, 6)
365
+ /* if either push-pull or high level */
291
+#define EFUSE_PROG_GATE_0 BIT_POS(22, 7)
366
+ if (is_push_pull(s, i) || s->pins_connected_high & (1 << i)) {
292
+#define EFUSE_PROG_GATE_1 BIT_POS(22, 7)
367
+ pins_to_disconnect |= (1 << i);
293
+#define EFUSE_PROG_GATE_2 BIT_POS(22, 9)
368
+ qemu_log_mask(LOG_GUEST_ERROR,
294
+#define EFUSE_SEC_LOCK BIT_POS(22, 10)
369
+ "Line %d can't be driven externally\n",
295
+#define EFUSE_RSA_EN BIT_POS(22, 11)
370
+ i);
296
+#define EFUSE_RSA_EN14 BIT_POS(22, 25)
371
+ }
297
+#define EFUSE_PPK0_WRLK BIT_POS(22, 26)
298
+#define EFUSE_PPK0_INVLD BIT_POS(22, 27)
299
+#define EFUSE_PPK0_INVLD_1 BIT_POS(22, 28)
300
+#define EFUSE_PPK1_WRLK BIT_POS(22, 29)
301
+#define EFUSE_PPK1_INVLD BIT_POS(22, 30)
302
+#define EFUSE_PPK1_INVLD_1 BIT_POS(22, 31)
303
+
304
+/* Areas. */
305
+#define EFUSE_TRIM_START BIT_POS(1, 0)
306
+#define EFUSE_TRIM_END BIT_POS(1, 30)
307
+#define EFUSE_DNA_START BIT_POS(3, 0)
308
+#define EFUSE_DNA_END BIT_POS(5, 31)
309
+#define EFUSE_AES_START BIT_POS(24, 0)
310
+#define EFUSE_AES_END BIT_POS(31, 31)
311
+#define EFUSE_ROM_START BIT_POS(17, 0)
312
+#define EFUSE_ROM_END BIT_POS(17, 31)
313
+#define EFUSE_IPDIS_START BIT_POS(6, 0)
314
+#define EFUSE_IPDIS_END BIT_POS(6, 31)
315
+#define EFUSE_USER_START BIT_POS(8, 0)
316
+#define EFUSE_USER_END BIT_POS(15, 31)
317
+#define EFUSE_BISR_START BIT_POS(32, 0)
318
+#define EFUSE_BISR_END BIT_POS(39, 31)
319
+
320
+#define EFUSE_USER_CTRL_START BIT_POS(16, 0)
321
+#define EFUSE_USER_CTRL_END BIT_POS(16, 16)
322
+#define EFUSE_USER_CTRL_MASK ((uint32_t)MAKE_64BIT_MASK(0, 17))
323
+
324
+#define EFUSE_PUF_CHASH_START BIT_POS(20, 0)
325
+#define EFUSE_PUF_CHASH_END BIT_POS(20, 31)
326
+#define EFUSE_PUF_MISC_START BIT_POS(21, 0)
327
+#define EFUSE_PUF_MISC_END BIT_POS(21, 31)
328
+#define EFUSE_PUF_SYN_WRLK BIT_POS(21, 30)
329
+
330
+#define EFUSE_SPK_START BIT_POS(23, 0)
331
+#define EFUSE_SPK_END BIT_POS(23, 31)
332
+
333
+#define EFUSE_PPK0_START BIT_POS(40, 0)
334
+#define EFUSE_PPK0_END BIT_POS(51, 31)
335
+#define EFUSE_PPK1_START BIT_POS(52, 0)
336
+#define EFUSE_PPK1_END BIT_POS(63, 31)
337
+
338
+#define EFUSE_CACHE_FLD(s, reg, field) \
339
+ ARRAY_FIELD_DP32((s)->regs, reg, field, \
340
+ (xlnx_efuse_get_row((s->efuse), EFUSE_ ## field) \
341
+ >> (EFUSE_ ## field % 32)))
342
+
343
+#define EFUSE_CACHE_BIT(s, reg, field) \
344
+ ARRAY_FIELD_DP32((s)->regs, reg, field, xlnx_efuse_get_bit((s->efuse), \
345
+ EFUSE_ ## field))
346
+
347
+#define FBIT_UNKNOWN (~0)
348
+
349
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxZynqMPEFuse *)0)->regs));
350
+
351
+static void update_tbit_status(XlnxZynqMPEFuse *s)
352
+{
353
+ unsigned int check = xlnx_efuse_tbits_check(s->efuse);
354
+ uint32_t val = s->regs[R_STATUS];
355
+
356
+ val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0)));
357
+ val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 1)));
358
+ val = FIELD_DP32(val, STATUS, EFUSE_3_TBIT, !!(check & (1 << 2)));
359
+
360
+ s->regs[R_STATUS] = val;
361
+}
362
+
363
+/* Update the u32 array from efuse bits. Slow but simple approach. */
364
+static void cache_sync_u32(XlnxZynqMPEFuse *s, unsigned int r_start,
365
+ unsigned int f_start, unsigned int f_end,
366
+ unsigned int f_written)
367
+{
368
+ uint32_t *u32 = &s->regs[r_start];
369
+ unsigned int fbit, wbits = 0, u32_off = 0;
370
+
371
+ /* Avoid working on bits that are not relevant. */
372
+ if (f_written != FBIT_UNKNOWN
373
+ && (f_written < f_start || f_written > f_end)) {
374
+ return;
375
+ }
376
+
377
+ for (fbit = f_start; fbit <= f_end; fbit++, wbits++) {
378
+ if (wbits == 32) {
379
+ /* Update the key offset. */
380
+ u32_off += 1;
381
+ wbits = 0;
382
+ }
372
+ }
383
+ u32[u32_off] |= xlnx_efuse_get_bit(s->efuse, fbit) << wbits;
373
+ }
384
+ }
374
+ return pins_to_disconnect;
385
+}
375
+}
386
+
376
+
387
+/*
377
+/*
388
+ * Keep the syncs in bit order so we can bail out for the
378
+ * Set field `disconnected_pins` and call `update_gpio_idr()`
389
+ * slower ones.
390
+ */
379
+ */
391
+static void zynqmp_efuse_sync_cache(XlnxZynqMPEFuse *s, unsigned int bit)
380
+static void disconnect_gpio_pins(Stm32l4x5GpioState *s, uint16_t lines)
392
+{
381
+{
393
+ EFUSE_CACHE_BIT(s, SEC_CTRL, AES_RDLK);
382
+ s->disconnected_pins |= lines;
394
+ EFUSE_CACHE_BIT(s, SEC_CTRL, AES_WRLK);
383
+ trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
395
+ EFUSE_CACHE_BIT(s, SEC_CTRL, ENC_ONLY);
384
+ s->pins_connected_high);
396
+ EFUSE_CACHE_BIT(s, SEC_CTRL, BBRAM_DIS);
385
+ update_gpio_idr(s);
397
+ EFUSE_CACHE_BIT(s, SEC_CTRL, ERROR_DIS);
386
+}
398
+ EFUSE_CACHE_BIT(s, SEC_CTRL, JTAG_DIS);
387
+
399
+ EFUSE_CACHE_BIT(s, SEC_CTRL, DFT_DIS);
388
+static void disconnected_pins_set(Object *obj, Visitor *v,
400
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_0);
389
+ const char *name, void *opaque, Error **errp)
401
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_1);
390
+{
402
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_2);
391
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
403
+ EFUSE_CACHE_BIT(s, SEC_CTRL, SEC_LOCK);
392
+ uint16_t value;
404
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PPK0_WRLK);
393
+ if (!visit_type_uint16(v, name, &value, errp)) {
405
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PPK1_WRLK);
394
+ return;
406
+
395
+ }
407
+ EFUSE_CACHE_FLD(s, SEC_CTRL, RSA_EN);
396
+ disconnect_gpio_pins(s, value);
408
+ EFUSE_CACHE_FLD(s, SEC_CTRL, PPK0_INVLD);
397
+}
409
+ EFUSE_CACHE_FLD(s, SEC_CTRL, PPK1_INVLD);
398
+
410
+
399
+static void disconnected_pins_get(Object *obj, Visitor *v,
411
+ /* Update the tbits. */
400
+ const char *name, void *opaque, Error **errp)
412
+ update_tbit_status(s);
401
+{
413
+
402
+ visit_type_uint16(v, name, (uint16_t *)opaque, errp);
414
+ /* Sync the various areas. */
403
+}
415
+ s->regs[R_MISC_USER_CTRL] = xlnx_efuse_get_row(s->efuse,
404
+
416
+ EFUSE_USER_CTRL_START)
405
+static void clock_freq_get(Object *obj, Visitor *v,
417
+ & EFUSE_USER_CTRL_MASK;
406
+ const char *name, void *opaque, Error **errp)
418
+ s->regs[R_PUF_CHASH] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_CHASH_START);
407
+{
419
+ s->regs[R_PUF_MISC] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_MISC_START);
408
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
420
+
409
+ uint32_t clock_freq_hz = clock_get_hz(s->clk);
421
+ cache_sync_u32(s, R_DNA_0, EFUSE_DNA_START, EFUSE_DNA_END, bit);
410
+ visit_type_uint32(v, name, &clock_freq_hz, errp);
422
+
411
+}
423
+ if (bit < EFUSE_AES_START) {
412
+
424
+ return;
413
+static void stm32l4x5_gpio_write(void *opaque, hwaddr addr,
425
+ }
414
+ uint64_t val64, unsigned int size)
426
+
415
+{
427
+ cache_sync_u32(s, R_ROM_RSVD, EFUSE_ROM_START, EFUSE_ROM_END, bit);
416
+ Stm32l4x5GpioState *s = opaque;
428
+ cache_sync_u32(s, R_IPDISABLE, EFUSE_IPDIS_START, EFUSE_IPDIS_END, bit);
417
+
429
+ cache_sync_u32(s, R_USER_0, EFUSE_USER_START, EFUSE_USER_END, bit);
418
+ uint32_t value = val64;
430
+ cache_sync_u32(s, R_SPK_ID, EFUSE_SPK_START, EFUSE_SPK_END, bit);
419
+ trace_stm32l4x5_gpio_write(s->name, addr, val64);
431
+ cache_sync_u32(s, R_PPK0_0, EFUSE_PPK0_START, EFUSE_PPK0_END, bit);
420
+
432
+ cache_sync_u32(s, R_PPK1_0, EFUSE_PPK1_START, EFUSE_PPK1_END, bit);
421
+ switch (addr) {
433
+}
422
+ case GPIO_MODER:
434
+
423
+ s->moder = value;
435
+static void zynqmp_efuse_update_irq(XlnxZynqMPEFuse *s)
424
+ disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
436
+{
425
+ qemu_log_mask(LOG_UNIMP,
437
+ bool pending = s->regs[R_EFUSE_ISR] & s->regs[R_EFUSE_IMR];
426
+ "%s: Analog and AF modes aren't supported\n\
438
+ qemu_set_irq(s->irq, pending);
427
+ Analog and AF mode behave like input mode\n",
439
+}
428
+ __func__);
440
+
429
+ return;
441
+static void zynqmp_efuse_isr_postw(RegisterInfo *reg, uint64_t val64)
430
+ case GPIO_OTYPER:
442
+{
431
+ s->otyper = value & ~RESERVED_BITS_MASK;
443
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
432
+ disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
444
+ zynqmp_efuse_update_irq(s);
433
+ return;
445
+}
434
+ case GPIO_OSPEEDR:
446
+
435
+ qemu_log_mask(LOG_UNIMP,
447
+static uint64_t zynqmp_efuse_ier_prew(RegisterInfo *reg, uint64_t val64)
436
+ "%s: Changing I/O output speed isn't supported\n\
448
+{
437
+ I/O speed is already maximal\n",
449
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
438
+ __func__);
450
+ uint32_t val = val64;
439
+ s->ospeedr = value;
451
+
440
+ return;
452
+ s->regs[R_EFUSE_IMR] |= val;
441
+ case GPIO_PUPDR:
453
+ zynqmp_efuse_update_irq(s);
442
+ s->pupdr = value;
454
+ return 0;
443
+ update_gpio_idr(s);
455
+}
444
+ return;
456
+
445
+ case GPIO_IDR:
457
+static uint64_t zynqmp_efuse_idr_prew(RegisterInfo *reg, uint64_t val64)
446
+ qemu_log_mask(LOG_UNIMP,
458
+{
447
+ "%s: GPIO->IDR is read-only\n",
459
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
448
+ __func__);
460
+ uint32_t val = val64;
449
+ return;
461
+
450
+ case GPIO_ODR:
462
+ s->regs[R_EFUSE_IMR] &= ~val;
451
+ s->odr = value & ~RESERVED_BITS_MASK;
463
+ zynqmp_efuse_update_irq(s);
452
+ update_gpio_idr(s);
464
+ return 0;
453
+ return;
465
+}
454
+ case GPIO_BSRR: {
466
+
455
+ uint32_t bits_to_reset = (value & RESERVED_BITS_MASK) >> GPIO_NUM_PINS;
467
+static void zynqmp_efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64)
456
+ uint32_t bits_to_set = value & ~RESERVED_BITS_MASK;
468
+{
457
+ /* If both BSx and BRx are set, BSx has priority.*/
469
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
458
+ s->odr &= ~bits_to_reset;
470
+ unsigned bit = val64;
459
+ s->odr |= bits_to_set;
471
+ unsigned page = FIELD_EX32(bit, EFUSE_PGM_ADDR, EFUSE);
460
+ update_gpio_idr(s);
472
+ bool puf_prot = false;
461
+ return;
473
+ const char *errmsg = NULL;
462
+ }
474
+
463
+ case GPIO_LCKR:
475
+ /* Allow only valid array, and adjust for skipped array 1 */
464
+ qemu_log_mask(LOG_UNIMP,
476
+ switch (page) {
465
+ "%s: Locking port bits configuration isn't supported\n",
477
+ case 0:
466
+ __func__);
478
+ break;
467
+ s->lckr = value & ~RESERVED_BITS_MASK;
479
+ case 2 ... 3:
468
+ return;
480
+ bit = FIELD_DP32(bit, EFUSE_PGM_ADDR, EFUSE, page - 1);
469
+ case GPIO_AFRL:
481
+ puf_prot = xlnx_efuse_get_bit(s->efuse, EFUSE_PUF_SYN_WRLK);
470
+ qemu_log_mask(LOG_UNIMP,
482
+ break;
471
+ "%s: Alternate functions aren't supported\n",
472
+ __func__);
473
+ s->afrl = value;
474
+ return;
475
+ case GPIO_AFRH:
476
+ qemu_log_mask(LOG_UNIMP,
477
+ "%s: Alternate functions aren't supported\n",
478
+ __func__);
479
+ s->afrh = value;
480
+ return;
481
+ case GPIO_BRR: {
482
+ uint32_t bits_to_reset = value & ~RESERVED_BITS_MASK;
483
+ s->odr &= ~bits_to_reset;
484
+ update_gpio_idr(s);
485
+ return;
486
+ }
487
+ case GPIO_ASCR:
488
+ qemu_log_mask(LOG_UNIMP,
489
+ "%s: ADC function isn't supported\n",
490
+ __func__);
491
+ s->ascr = value & ~RESERVED_BITS_MASK;
492
+ return;
483
+ default:
493
+ default:
484
+ errmsg = "Invalid address";
485
+ goto pgm_done;
486
+ }
487
+
488
+ if (ARRAY_FIELD_EX32(s->regs, WR_LOCK, LOCK)) {
489
+ errmsg = "Array write-locked";
490
+ goto pgm_done;
491
+ }
492
+
493
+ if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) {
494
+ errmsg = "Array pgm-disabled";
495
+ goto pgm_done;
496
+ }
497
+
498
+ if (puf_prot) {
499
+ errmsg = "PUF_HD-store write-locked";
500
+ goto pgm_done;
501
+ }
502
+
503
+ if (ARRAY_FIELD_EX32(s->regs, SEC_CTRL, AES_WRLK)
504
+ && bit >= EFUSE_AES_START && bit <= EFUSE_AES_END) {
505
+ errmsg = "AES key-store Write-locked";
506
+ goto pgm_done;
507
+ }
508
+
509
+ if (!xlnx_efuse_set_bit(s->efuse, bit)) {
510
+ errmsg = "Write failed";
511
+ }
512
+
513
+ pgm_done:
514
+ if (!errmsg) {
515
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 0);
516
+ } else {
517
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1);
518
+ qemu_log_mask(LOG_GUEST_ERROR,
494
+ qemu_log_mask(LOG_GUEST_ERROR,
519
+ "%s - eFuse write error: %s; addr=0x%x\n",
495
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
520
+ object_get_canonical_path(OBJECT(s)),
496
+ }
521
+ errmsg, (unsigned)val64);
497
+}
522
+ }
498
+
523
+
499
+static uint64_t stm32l4x5_gpio_read(void *opaque, hwaddr addr,
524
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1);
500
+ unsigned int size)
525
+ zynqmp_efuse_update_irq(s);
501
+{
526
+}
502
+ Stm32l4x5GpioState *s = opaque;
527
+
503
+
528
+static void zynqmp_efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64)
504
+ trace_stm32l4x5_gpio_read(s->name, addr);
529
+{
505
+
530
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
506
+ switch (addr) {
531
+
507
+ case GPIO_MODER:
532
+ /*
508
+ return s->moder;
533
+ * Grant reads only to allowed bits; reference sources:
509
+ case GPIO_OTYPER:
534
+ * 1/ XilSKey - XilSKey_ZynqMp_EfusePs_ReadRow()
510
+ return s->otyper;
535
+ * 2/ UG1085, v2.0, table 12-13
511
+ case GPIO_OSPEEDR:
536
+ * (note: enumerates the masks as <first, last> per described in
512
+ return s->ospeedr;
537
+ * references to avoid mental translation).
513
+ case GPIO_PUPDR:
538
+ */
514
+ return s->pupdr;
539
+#define COL_MASK(L_, H_) \
515
+ case GPIO_IDR:
540
+ ((uint32_t)MAKE_64BIT_MASK((L_), (1 + (H_) - (L_))))
516
+ return s->idr;
541
+
517
+ case GPIO_ODR:
542
+ static const uint32_t ary0_col_mask[] = {
518
+ return s->odr;
543
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_TBITS_ROW */
519
+ case GPIO_BSRR:
544
+ [0] = COL_MASK(28, 31),
520
+ return 0;
545
+
521
+ case GPIO_LCKR:
546
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_USR{0:7}_FUSE_ROW */
522
+ return s->lckr;
547
+ [8] = COL_MASK(0, 31), [9] = COL_MASK(0, 31),
523
+ case GPIO_AFRL:
548
+ [10] = COL_MASK(0, 31), [11] = COL_MASK(0, 31),
524
+ return s->afrl;
549
+ [12] = COL_MASK(0, 31), [13] = COL_MASK(0, 31),
525
+ case GPIO_AFRH:
550
+ [14] = COL_MASK(0, 31), [15] = COL_MASK(0, 31),
526
+ return s->afrh;
551
+
527
+ case GPIO_BRR:
552
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_MISC_USR_CTRL_ROW */
528
+ return 0;
553
+ [16] = COL_MASK(0, 7) | COL_MASK(10, 16),
529
+ case GPIO_ASCR:
554
+
530
+ return s->ascr;
555
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_ROW */
556
+ [17] = COL_MASK(0, 2),
557
+
558
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_CHASH_ROW */
559
+ [20] = COL_MASK(0, 31),
560
+
561
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_AUX_ROW */
562
+ [21] = COL_MASK(0, 23) | COL_MASK(29, 31),
563
+
564
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW */
565
+ [22] = COL_MASK(0, 31),
566
+
567
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW */
568
+ [23] = COL_MASK(0, 31),
569
+
570
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW */
571
+ [40] = COL_MASK(0, 31), [41] = COL_MASK(0, 31),
572
+ [42] = COL_MASK(0, 31), [43] = COL_MASK(0, 31),
573
+ [44] = COL_MASK(0, 31), [45] = COL_MASK(0, 31),
574
+ [46] = COL_MASK(0, 31), [47] = COL_MASK(0, 31),
575
+ [48] = COL_MASK(0, 31), [49] = COL_MASK(0, 31),
576
+ [50] = COL_MASK(0, 31), [51] = COL_MASK(0, 31),
577
+
578
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW */
579
+ [52] = COL_MASK(0, 31), [53] = COL_MASK(0, 31),
580
+ [54] = COL_MASK(0, 31), [55] = COL_MASK(0, 31),
581
+ [56] = COL_MASK(0, 31), [57] = COL_MASK(0, 31),
582
+ [58] = COL_MASK(0, 31), [59] = COL_MASK(0, 31),
583
+ [60] = COL_MASK(0, 31), [61] = COL_MASK(0, 31),
584
+ [62] = COL_MASK(0, 31), [63] = COL_MASK(0, 31),
585
+ };
586
+
587
+ uint32_t col_mask = COL_MASK(0, 31);
588
+#undef COL_MASK
589
+
590
+ uint32_t efuse_idx = s->regs[R_EFUSE_RD_ADDR];
591
+ uint32_t efuse_ary = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, EFUSE);
592
+ uint32_t efuse_row = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, ROW);
593
+
594
+ switch (efuse_ary) {
595
+ case 0: /* Various */
596
+ if (efuse_row >= ARRAY_SIZE(ary0_col_mask)) {
597
+ goto denied;
598
+ }
599
+
600
+ col_mask = ary0_col_mask[efuse_row];
601
+ if (!col_mask) {
602
+ goto denied;
603
+ }
604
+ break;
605
+ case 2: /* PUF helper data, adjust for skipped array 1 */
606
+ case 3:
607
+ val64 = FIELD_DP32(efuse_idx, EFUSE_RD_ADDR, EFUSE, efuse_ary - 1);
608
+ break;
609
+ default:
531
+ default:
610
+ goto denied;
611
+ }
612
+
613
+ s->regs[R_EFUSE_RD_DATA] = xlnx_efuse_get_row(s->efuse, val64) & col_mask;
614
+
615
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 0);
616
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1);
617
+ zynqmp_efuse_update_irq(s);
618
+ return;
619
+
620
+ denied:
621
+ qemu_log_mask(LOG_GUEST_ERROR,
622
+ "%s: Denied efuse read from array %u, row %u\n",
623
+ object_get_canonical_path(OBJECT(s)),
624
+ efuse_ary, efuse_row);
625
+
626
+ s->regs[R_EFUSE_RD_DATA] = 0;
627
+
628
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1);
629
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 0);
630
+ zynqmp_efuse_update_irq(s);
631
+}
632
+
633
+static void zynqmp_efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
634
+{
635
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
636
+ bool ok;
637
+
638
+ ok = xlnx_efuse_k256_check(s->efuse, (uint32_t)val64, EFUSE_AES_START);
639
+
640
+ ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_PASS, (ok ? 1 : 0));
641
+ ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_DONE, 1);
642
+
643
+ s->regs[R_EFUSE_AES_CRC] = 0; /* crc value is write-only */
644
+}
645
+
646
+static uint64_t zynqmp_efuse_cache_load_prew(RegisterInfo *reg,
647
+ uint64_t valu64)
648
+{
649
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
650
+
651
+ if (valu64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) {
652
+ zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN);
653
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
654
+ zynqmp_efuse_update_irq(s);
655
+ }
656
+
657
+ return 0;
658
+}
659
+
660
+static uint64_t zynqmp_efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val)
661
+{
662
+ return val == 0xDF0D ? 0 : 1;
663
+}
664
+
665
+static RegisterAccessInfo zynqmp_efuse_regs_info[] = {
666
+ { .name = "WR_LOCK", .addr = A_WR_LOCK,
667
+ .reset = 0x1,
668
+ .pre_write = zynqmp_efuse_wr_lock_prew,
669
+ },{ .name = "CFG", .addr = A_CFG,
670
+ },{ .name = "STATUS", .addr = A_STATUS,
671
+ .rsvd = 0x8,
672
+ .ro = 0xff,
673
+ },{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR,
674
+ .post_write = zynqmp_efuse_pgm_addr_postw
675
+ },{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR,
676
+ .rsvd = 0x1f,
677
+ .post_write = zynqmp_efuse_rd_addr_postw,
678
+ },{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA,
679
+ .ro = 0xffffffff,
680
+ },{ .name = "TPGM", .addr = A_TPGM,
681
+ },{ .name = "TRD", .addr = A_TRD,
682
+ .reset = 0x1b,
683
+ },{ .name = "TSU_H_PS", .addr = A_TSU_H_PS,
684
+ .reset = 0xff,
685
+ },{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS,
686
+ .reset = 0xb,
687
+ },{ .name = "TSU_H_CS", .addr = A_TSU_H_CS,
688
+ .reset = 0x7,
689
+ },{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR,
690
+ .rsvd = 0x7fffffe0,
691
+ .w1c = 0x8000001f,
692
+ .post_write = zynqmp_efuse_isr_postw,
693
+ },{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR,
694
+ .reset = 0x8000001f,
695
+ .rsvd = 0x7fffffe0,
696
+ .ro = 0xffffffff,
697
+ },{ .name = "EFUSE_IER", .addr = A_EFUSE_IER,
698
+ .rsvd = 0x7fffffe0,
699
+ .pre_write = zynqmp_efuse_ier_prew,
700
+ },{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR,
701
+ .rsvd = 0x7fffffe0,
702
+ .pre_write = zynqmp_efuse_idr_prew,
703
+ },{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD,
704
+ .pre_write = zynqmp_efuse_cache_load_prew,
705
+ },{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK,
706
+ },{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC,
707
+ .post_write = zynqmp_efuse_aes_crc_postw,
708
+ },{ .name = "EFUSE_TBITS_PRGRMG_EN", .addr = A_EFUSE_TBITS_PRGRMG_EN,
709
+ .reset = R_EFUSE_TBITS_PRGRMG_EN_TBITS_PRGRMG_EN_MASK,
710
+ },{ .name = "DNA_0", .addr = A_DNA_0,
711
+ .ro = 0xffffffff,
712
+ },{ .name = "DNA_1", .addr = A_DNA_1,
713
+ .ro = 0xffffffff,
714
+ },{ .name = "DNA_2", .addr = A_DNA_2,
715
+ .ro = 0xffffffff,
716
+ },{ .name = "IPDISABLE", .addr = A_IPDISABLE,
717
+ .ro = 0xffffffff,
718
+ },{ .name = "SYSOSC_CTRL", .addr = A_SYSOSC_CTRL,
719
+ .ro = 0xffffffff,
720
+ },{ .name = "USER_0", .addr = A_USER_0,
721
+ .ro = 0xffffffff,
722
+ },{ .name = "USER_1", .addr = A_USER_1,
723
+ .ro = 0xffffffff,
724
+ },{ .name = "USER_2", .addr = A_USER_2,
725
+ .ro = 0xffffffff,
726
+ },{ .name = "USER_3", .addr = A_USER_3,
727
+ .ro = 0xffffffff,
728
+ },{ .name = "USER_4", .addr = A_USER_4,
729
+ .ro = 0xffffffff,
730
+ },{ .name = "USER_5", .addr = A_USER_5,
731
+ .ro = 0xffffffff,
732
+ },{ .name = "USER_6", .addr = A_USER_6,
733
+ .ro = 0xffffffff,
734
+ },{ .name = "USER_7", .addr = A_USER_7,
735
+ .ro = 0xffffffff,
736
+ },{ .name = "MISC_USER_CTRL", .addr = A_MISC_USER_CTRL,
737
+ .ro = 0xffffffff,
738
+ },{ .name = "ROM_RSVD", .addr = A_ROM_RSVD,
739
+ .ro = 0xffffffff,
740
+ },{ .name = "PUF_CHASH", .addr = A_PUF_CHASH,
741
+ .ro = 0xffffffff,
742
+ },{ .name = "PUF_MISC", .addr = A_PUF_MISC,
743
+ .ro = 0xffffffff,
744
+ },{ .name = "SEC_CTRL", .addr = A_SEC_CTRL,
745
+ .ro = 0xffffffff,
746
+ },{ .name = "SPK_ID", .addr = A_SPK_ID,
747
+ .ro = 0xffffffff,
748
+ },{ .name = "PPK0_0", .addr = A_PPK0_0,
749
+ .ro = 0xffffffff,
750
+ },{ .name = "PPK0_1", .addr = A_PPK0_1,
751
+ .ro = 0xffffffff,
752
+ },{ .name = "PPK0_2", .addr = A_PPK0_2,
753
+ .ro = 0xffffffff,
754
+ },{ .name = "PPK0_3", .addr = A_PPK0_3,
755
+ .ro = 0xffffffff,
756
+ },{ .name = "PPK0_4", .addr = A_PPK0_4,
757
+ .ro = 0xffffffff,
758
+ },{ .name = "PPK0_5", .addr = A_PPK0_5,
759
+ .ro = 0xffffffff,
760
+ },{ .name = "PPK0_6", .addr = A_PPK0_6,
761
+ .ro = 0xffffffff,
762
+ },{ .name = "PPK0_7", .addr = A_PPK0_7,
763
+ .ro = 0xffffffff,
764
+ },{ .name = "PPK0_8", .addr = A_PPK0_8,
765
+ .ro = 0xffffffff,
766
+ },{ .name = "PPK0_9", .addr = A_PPK0_9,
767
+ .ro = 0xffffffff,
768
+ },{ .name = "PPK0_10", .addr = A_PPK0_10,
769
+ .ro = 0xffffffff,
770
+ },{ .name = "PPK0_11", .addr = A_PPK0_11,
771
+ .ro = 0xffffffff,
772
+ },{ .name = "PPK1_0", .addr = A_PPK1_0,
773
+ .ro = 0xffffffff,
774
+ },{ .name = "PPK1_1", .addr = A_PPK1_1,
775
+ .ro = 0xffffffff,
776
+ },{ .name = "PPK1_2", .addr = A_PPK1_2,
777
+ .ro = 0xffffffff,
778
+ },{ .name = "PPK1_3", .addr = A_PPK1_3,
779
+ .ro = 0xffffffff,
780
+ },{ .name = "PPK1_4", .addr = A_PPK1_4,
781
+ .ro = 0xffffffff,
782
+ },{ .name = "PPK1_5", .addr = A_PPK1_5,
783
+ .ro = 0xffffffff,
784
+ },{ .name = "PPK1_6", .addr = A_PPK1_6,
785
+ .ro = 0xffffffff,
786
+ },{ .name = "PPK1_7", .addr = A_PPK1_7,
787
+ .ro = 0xffffffff,
788
+ },{ .name = "PPK1_8", .addr = A_PPK1_8,
789
+ .ro = 0xffffffff,
790
+ },{ .name = "PPK1_9", .addr = A_PPK1_9,
791
+ .ro = 0xffffffff,
792
+ },{ .name = "PPK1_10", .addr = A_PPK1_10,
793
+ .ro = 0xffffffff,
794
+ },{ .name = "PPK1_11", .addr = A_PPK1_11,
795
+ .ro = 0xffffffff,
796
+ }
797
+};
798
+
799
+static void zynqmp_efuse_reg_write(void *opaque, hwaddr addr,
800
+ uint64_t data, unsigned size)
801
+{
802
+ RegisterInfoArray *reg_array = opaque;
803
+ XlnxZynqMPEFuse *s;
804
+ Object *dev;
805
+
806
+ assert(reg_array != NULL);
807
+
808
+ dev = reg_array->mem.owner;
809
+ assert(dev);
810
+
811
+ s = XLNX_ZYNQMP_EFUSE(dev);
812
+
813
+ if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {
814
+ qemu_log_mask(LOG_GUEST_ERROR,
532
+ qemu_log_mask(LOG_GUEST_ERROR,
815
+ "%s[reg_0x%02lx]: Attempt to write locked register.\n",
533
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
816
+ object_get_canonical_path(OBJECT(s)), (long)addr);
534
+ return 0;
817
+ } else {
535
+ }
818
+ register_write_memory(opaque, addr, data, size);
536
+}
819
+ }
537
+
820
+}
538
+static const MemoryRegionOps stm32l4x5_gpio_ops = {
821
+
539
+ .read = stm32l4x5_gpio_read,
822
+static const MemoryRegionOps zynqmp_efuse_ops = {
540
+ .write = stm32l4x5_gpio_write,
823
+ .read = register_read_memory,
541
+ .endianness = DEVICE_NATIVE_ENDIAN,
824
+ .write = zynqmp_efuse_reg_write,
542
+ .impl = {
825
+ .endianness = DEVICE_LITTLE_ENDIAN,
543
+ .min_access_size = 4,
544
+ .max_access_size = 4,
545
+ .unaligned = false,
546
+ },
826
+ .valid = {
547
+ .valid = {
827
+ .min_access_size = 4,
548
+ .min_access_size = 4,
828
+ .max_access_size = 4,
549
+ .max_access_size = 4,
550
+ .unaligned = false,
829
+ },
551
+ },
830
+};
552
+};
831
+
553
+
832
+static void zynqmp_efuse_register_reset(RegisterInfo *reg)
554
+static void stm32l4x5_gpio_init(Object *obj)
833
+{
555
+{
834
+ if (!reg->data || !reg->access) {
556
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
835
+ return;
557
+
836
+ }
558
+ memory_region_init_io(&s->mmio, obj, &stm32l4x5_gpio_ops, s,
837
+
559
+ TYPE_STM32L4X5_GPIO, 0x400);
838
+ /* Reset must not trigger some registers' writers */
560
+
839
+ switch (reg->access->addr) {
561
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
840
+ case A_EFUSE_AES_CRC:
562
+
841
+ *(uint32_t *)reg->data = reg->access->reset;
563
+ qdev_init_gpio_out(DEVICE(obj), s->pin, GPIO_NUM_PINS);
842
+ return;
564
+ qdev_init_gpio_in(DEVICE(obj), stm32l4x5_gpio_set, GPIO_NUM_PINS);
843
+ }
565
+
844
+
566
+ s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0);
845
+ register_reset(reg);
567
+
846
+}
568
+ object_property_add(obj, "disconnected-pins", "uint16",
847
+
569
+ disconnected_pins_get, disconnected_pins_set,
848
+static void zynqmp_efuse_reset(DeviceState *dev)
570
+ NULL, &s->disconnected_pins);
849
+{
571
+ object_property_add(obj, "clock-freq-hz", "uint32",
850
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
572
+ clock_freq_get, NULL, NULL, NULL);
851
+ unsigned int i;
573
+}
852
+
574
+
853
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
575
+static void stm32l4x5_gpio_realize(DeviceState *dev, Error **errp)
854
+ zynqmp_efuse_register_reset(&s->regs_info[i]);
576
+{
855
+ }
577
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(dev);
856
+
578
+ if (!clock_has_source(s->clk)) {
857
+ zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN);
579
+ error_setg(errp, "GPIO: clk input must be connected");
858
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
580
+ return;
859
+ zynqmp_efuse_update_irq(s);
581
+ }
860
+}
582
+}
861
+
583
+
862
+static void zynqmp_efuse_realize(DeviceState *dev, Error **errp)
584
+static const VMStateDescription vmstate_stm32l4x5_gpio = {
863
+{
585
+ .name = TYPE_STM32L4X5_GPIO,
864
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
865
+
866
+ if (!s->efuse) {
867
+ error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE",
868
+ object_get_canonical_path(OBJECT(dev)));
869
+ return;
870
+ }
871
+
872
+ s->efuse->dev = dev;
873
+}
874
+
875
+static void zynqmp_efuse_init(Object *obj)
876
+{
877
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj);
878
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
879
+ RegisterInfoArray *reg_array;
880
+
881
+ reg_array =
882
+ register_init_block32(DEVICE(obj), zynqmp_efuse_regs_info,
883
+ ARRAY_SIZE(zynqmp_efuse_regs_info),
884
+ s->regs_info, s->regs,
885
+ &zynqmp_efuse_ops,
886
+ ZYNQMP_EFUSE_ERR_DEBUG,
887
+ R_MAX * 4);
888
+
889
+ sysbus_init_mmio(sbd, &reg_array->mem);
890
+ sysbus_init_irq(sbd, &s->irq);
891
+}
892
+
893
+static const VMStateDescription vmstate_efuse = {
894
+ .name = TYPE_XLNX_ZYNQMP_EFUSE,
895
+ .version_id = 1,
586
+ .version_id = 1,
896
+ .minimum_version_id = 1,
587
+ .minimum_version_id = 1,
897
+ .fields = (VMStateField[]) {
588
+ .fields = (VMStateField[]){
898
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPEFuse, R_MAX),
589
+ VMSTATE_UINT32(moder, Stm32l4x5GpioState),
899
+ VMSTATE_END_OF_LIST(),
590
+ VMSTATE_UINT32(otyper, Stm32l4x5GpioState),
591
+ VMSTATE_UINT32(ospeedr, Stm32l4x5GpioState),
592
+ VMSTATE_UINT32(pupdr, Stm32l4x5GpioState),
593
+ VMSTATE_UINT32(idr, Stm32l4x5GpioState),
594
+ VMSTATE_UINT32(odr, Stm32l4x5GpioState),
595
+ VMSTATE_UINT32(lckr, Stm32l4x5GpioState),
596
+ VMSTATE_UINT32(afrl, Stm32l4x5GpioState),
597
+ VMSTATE_UINT32(afrh, Stm32l4x5GpioState),
598
+ VMSTATE_UINT32(ascr, Stm32l4x5GpioState),
599
+ VMSTATE_UINT16(disconnected_pins, Stm32l4x5GpioState),
600
+ VMSTATE_UINT16(pins_connected_high, Stm32l4x5GpioState),
601
+ VMSTATE_END_OF_LIST()
900
+ }
602
+ }
901
+};
603
+};
902
+
604
+
903
+static Property zynqmp_efuse_props[] = {
605
+static Property stm32l4x5_gpio_properties[] = {
904
+ DEFINE_PROP_LINK("efuse",
606
+ DEFINE_PROP_STRING("name", Stm32l4x5GpioState, name),
905
+ XlnxZynqMPEFuse, efuse,
607
+ DEFINE_PROP_UINT32("mode-reset", Stm32l4x5GpioState, moder_reset, 0),
906
+ TYPE_XLNX_EFUSE, XlnxEFuse *),
608
+ DEFINE_PROP_UINT32("ospeed-reset", Stm32l4x5GpioState, ospeedr_reset, 0),
907
+
609
+ DEFINE_PROP_UINT32("pupd-reset", Stm32l4x5GpioState, pupdr_reset, 0),
908
+ DEFINE_PROP_END_OF_LIST(),
610
+ DEFINE_PROP_END_OF_LIST(),
909
+};
611
+};
910
+
612
+
911
+static void zynqmp_efuse_class_init(ObjectClass *klass, void *data)
613
+static void stm32l4x5_gpio_class_init(ObjectClass *klass, void *data)
912
+{
614
+{
913
+ DeviceClass *dc = DEVICE_CLASS(klass);
615
+ DeviceClass *dc = DEVICE_CLASS(klass);
914
+
616
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
915
+ dc->reset = zynqmp_efuse_reset;
617
+
916
+ dc->realize = zynqmp_efuse_realize;
618
+ device_class_set_props(dc, stm32l4x5_gpio_properties);
917
+ dc->vmsd = &vmstate_efuse;
619
+ dc->vmsd = &vmstate_stm32l4x5_gpio;
918
+ device_class_set_props(dc, zynqmp_efuse_props);
620
+ dc->realize = stm32l4x5_gpio_realize;
919
+}
621
+ rc->phases.hold = stm32l4x5_gpio_reset_hold;
920
+
622
+}
921
+
623
+
922
+static const TypeInfo efuse_info = {
624
+static const TypeInfo stm32l4x5_gpio_types[] = {
923
+ .name = TYPE_XLNX_ZYNQMP_EFUSE,
625
+ {
924
+ .parent = TYPE_SYS_BUS_DEVICE,
626
+ .name = TYPE_STM32L4X5_GPIO,
925
+ .instance_size = sizeof(XlnxZynqMPEFuse),
627
+ .parent = TYPE_SYS_BUS_DEVICE,
926
+ .class_init = zynqmp_efuse_class_init,
628
+ .instance_size = sizeof(Stm32l4x5GpioState),
927
+ .instance_init = zynqmp_efuse_init,
629
+ .instance_init = stm32l4x5_gpio_init,
630
+ .class_init = stm32l4x5_gpio_class_init,
631
+ },
928
+};
632
+};
929
+
633
+
930
+static void efuse_register_types(void)
634
+DEFINE_TYPES(stm32l4x5_gpio_types)
931
+{
635
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
932
+ type_register_static(&efuse_info);
933
+}
934
+
935
+type_init(efuse_register_types)
936
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
937
index XXXXXXX..XXXXXXX 100644
636
index XXXXXXX..XXXXXXX 100644
938
--- a/hw/nvram/Kconfig
637
--- a/hw/gpio/Kconfig
939
+++ b/hw/nvram/Kconfig
638
+++ b/hw/gpio/Kconfig
940
@@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE
639
@@ -XXX,XX +XXX,XX @@ config GPIO_PWR
941
config XLNX_EFUSE_VERSAL
640
641
config SIFIVE_GPIO
942
bool
642
bool
943
select XLNX_EFUSE
643
+
944
+
644
+config STM32L4X5_GPIO
945
+config XLNX_EFUSE_ZYNQMP
946
+ bool
645
+ bool
947
+ select XLNX_EFUSE
646
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
948
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
949
index XXXXXXX..XXXXXXX 100644
647
index XXXXXXX..XXXXXXX 100644
950
--- a/hw/nvram/meson.build
648
--- a/hw/gpio/meson.build
951
+++ b/hw/nvram/meson.build
649
+++ b/hw/gpio/meson.build
952
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
650
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files(
953
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
651
'bcm2835_gpio.c',
954
'xlnx-versal-efuse-cache.c',
652
'bcm2838_gpio.c'
955
'xlnx-versal-efuse-ctrl.c'))
653
))
956
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files(
654
+system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio.c'))
957
+ 'xlnx-zynqmp-efuse.c'))
655
system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
958
656
system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
959
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
657
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
658
index XXXXXXX..XXXXXXX 100644
659
--- a/hw/gpio/trace-events
660
+++ b/hw/gpio/trace-events
661
@@ -XXX,XX +XXX,XX @@ sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " val
662
# aspeed_gpio.c
663
aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
664
aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
665
+
666
+# stm32l4x5_gpio.c
667
+stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 " "
668
+stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
669
+stm32l4x5_gpio_update_idr(char *gpio, uint32_t old_idr, uint32_t new_idr) "GPIO%s from: 0x%x to: 0x%x"
670
+stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPIO%s disconnected pins: 0x%x levels: 0x%x"
960
--
671
--
961
2.20.1
672
2.34.1
962
673
963
674
diff view generated by jsdifflib
[PULL 07/22] hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device
[PULL 10/14] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
1
From: Tong Ho <tong.ho@xilinx.com>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
Connect the support for Versal Battery-Backed RAM (BBRAM)
3
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
4
4
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
5
The command argument:
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
-drive if=pflash,index=0,...
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
7
Can be used to optionally connect the bbram to a backend
7
Message-id: 20240305210444.310665-3-ines.varhol@telecom-paris.fr
8
storage, such that field-programmed values in one
9
invocation can be made available to next invocation.
10
11
The backend storage must be a seekable binary file, and
12
its size must be 36 bytes or larger. A file with all
13
binary 0's is a 'blank'.
14
15
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
16
Message-id: 20210917052400.1249094-6-tong.ho@xilinx.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
9
---
20
include/hw/arm/xlnx-versal.h | 5 +++++
10
include/hw/arm/stm32l4x5_soc.h | 2 +
21
hw/arm/xlnx-versal-virt.c | 36 ++++++++++++++++++++++++++++++++++++
11
include/hw/gpio/stm32l4x5_gpio.h | 1 +
22
hw/arm/xlnx-versal.c | 18 ++++++++++++++++++
12
include/hw/misc/stm32l4x5_syscfg.h | 3 +-
23
hw/arm/Kconfig | 1 +
13
hw/arm/stm32l4x5_soc.c | 71 +++++++++++++++++++++++-------
24
4 files changed, 60 insertions(+)
14
hw/misc/stm32l4x5_syscfg.c | 1 +
25
15
hw/arm/Kconfig | 3 +-
26
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
16
6 files changed, 63 insertions(+), 18 deletions(-)
27
index XXXXXXX..XXXXXXX 100644
17
28
--- a/include/hw/arm/xlnx-versal.h
18
diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
29
+++ b/include/hw/arm/xlnx-versal.h
19
index XXXXXXX..XXXXXXX 100644
30
@@ -XXX,XX +XXX,XX @@
20
--- a/include/hw/arm/stm32l4x5_soc.h
21
+++ b/include/hw/arm/stm32l4x5_soc.h
22
@@ -XXX,XX +XXX,XX @@
23
#include "hw/misc/stm32l4x5_syscfg.h"
24
#include "hw/misc/stm32l4x5_exti.h"
25
#include "hw/misc/stm32l4x5_rcc.h"
26
+#include "hw/gpio/stm32l4x5_gpio.h"
31
#include "qom/object.h"
27
#include "qom/object.h"
32
#include "hw/usb/xlnx-usb-subsystem.h"
28
33
#include "hw/misc/xlnx-versal-xramc.h"
29
#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
34
+#include "hw/nvram/xlnx-bbram.h"
30
@@ -XXX,XX +XXX,XX @@ struct Stm32l4x5SocState {
35
31
OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];
36
#define TYPE_XLNX_VERSAL "xlnx-versal"
32
Stm32l4x5SyscfgState syscfg;
37
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
33
Stm32l4x5RccState rcc;
38
@@ -XXX,XX +XXX,XX @@ struct Versal {
34
+ Stm32l4x5GpioState gpio[NUM_GPIOS];
39
} iou;
35
40
36
MemoryRegion sram1;
41
XlnxZynqMPRTC rtc;
37
MemoryRegion sram2;
42
+ XlnxBBRam bbram;
38
diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h
43
} pmc;
39
index XXXXXXX..XXXXXXX 100644
44
40
--- a/include/hw/gpio/stm32l4x5_gpio.h
45
struct {
41
+++ b/include/hw/gpio/stm32l4x5_gpio.h
46
@@ -XXX,XX +XXX,XX @@ struct Versal {
42
@@ -XXX,XX +XXX,XX @@
47
#define VERSAL_GEM1_WAKE_IRQ_0 59
43
#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
48
#define VERSAL_ADMA_IRQ_0 60
44
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
49
#define VERSAL_XRAM_IRQ_0 79
45
50
+#define VERSAL_BBRAM_APB_IRQ_0 121
46
+#define NUM_GPIOS 8
51
#define VERSAL_RTC_APB_ERR_IRQ 121
47
#define GPIO_NUM_PINS 16
52
#define VERSAL_SD0_IRQ_0 126
48
53
#define VERSAL_RTC_ALARM_IRQ 142
49
struct Stm32l4x5GpioState {
54
@@ -XXX,XX +XXX,XX @@ struct Versal {
50
diff --git a/include/hw/misc/stm32l4x5_syscfg.h b/include/hw/misc/stm32l4x5_syscfg.h
55
51
index XXXXXXX..XXXXXXX 100644
56
#define MM_PMC_SD0 0xf1040000U
52
--- a/include/hw/misc/stm32l4x5_syscfg.h
57
#define MM_PMC_SD0_SIZE 0x10000
53
+++ b/include/hw/misc/stm32l4x5_syscfg.h
58
+#define MM_PMC_BBRAM_CTRL 0xf11f0000
54
@@ -XXX,XX +XXX,XX @@
59
+#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
55
60
#define MM_PMC_CRP 0xf1260000U
56
#include "hw/sysbus.h"
61
#define MM_PMC_CRP_SIZE 0x10000
57
#include "qom/object.h"
62
#define MM_PMC_RTC 0xf12a0000
58
+#include "hw/gpio/stm32l4x5_gpio.h"
63
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
59
64
index XXXXXXX..XXXXXXX 100644
60
#define TYPE_STM32L4X5_SYSCFG "stm32l4x5-syscfg"
65
--- a/hw/arm/xlnx-versal-virt.c
61
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5SyscfgState, STM32L4X5_SYSCFG)
66
+++ b/hw/arm/xlnx-versal-virt.c
62
67
@@ -XXX,XX +XXX,XX @@ static void fdt_add_rtc_node(VersalVirt *s)
63
-#define NUM_GPIOS 8
68
g_free(name);
64
-#define GPIO_NUM_PINS 16
65
#define SYSCFG_NUM_EXTICR 4
66
67
struct Stm32l4x5SyscfgState {
68
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/stm32l4x5_soc.c
71
+++ b/hw/arm/stm32l4x5_soc.c
72
@@ -XXX,XX +XXX,XX @@
73
#include "sysemu/sysemu.h"
74
#include "hw/or-irq.h"
75
#include "hw/arm/stm32l4x5_soc.h"
76
+#include "hw/gpio/stm32l4x5_gpio.h"
77
#include "hw/qdev-clock.h"
78
#include "hw/misc/unimp.h"
79
80
@@ -XXX,XX +XXX,XX @@ static const int exti_or_gate1_lines_in[EXTI_OR_GATE1_NUM_LINES_IN] = {
81
16, 35, 36, 37, 38,
82
};
83
84
+static const struct {
85
+ uint32_t addr;
86
+ uint32_t moder_reset;
87
+ uint32_t ospeedr_reset;
88
+ uint32_t pupdr_reset;
89
+} stm32l4x5_gpio_cfg[NUM_GPIOS] = {
90
+ { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
91
+ { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
92
+ { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
93
+ { 0x48000C00, 0xFFFFFFFF, 0x00000000, 0x00000000 },
94
+ { 0x48001000, 0xFFFFFFFF, 0x00000000, 0x00000000 },
95
+ { 0x48001400, 0xFFFFFFFF, 0x00000000, 0x00000000 },
96
+ { 0x48001800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
97
+ { 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 },
98
+};
99
+
100
static void stm32l4x5_soc_initfn(Object *obj)
101
{
102
Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
103
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_initfn(Object *obj)
104
}
105
object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG);
106
object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32L4X5_RCC);
107
+
108
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
109
+ g_autofree char *name = g_strdup_printf("gpio%c", 'a' + i);
110
+ object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPIO);
111
+ }
69
}
112
}
70
113
71
+static void fdt_add_bbram_node(VersalVirt *s)
114
static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
72
+{
115
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
73
+ const char compat[] = TYPE_XLNX_BBRAM;
116
Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc);
74
+ const char interrupt_names[] = "bbram-error";
117
const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc);
75
+ char *name = g_strdup_printf("/bbram@%x", MM_PMC_BBRAM_CTRL);
118
MemoryRegion *system_memory = get_system_memory();
76
+
119
- DeviceState *armv7m;
77
+ qemu_fdt_add_subnode(s->fdt, name);
120
+ DeviceState *armv7m, *dev;
78
+
121
SysBusDevice *busdev;
79
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
122
+ uint32_t pin_index;
80
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_BBRAM_APB_IRQ_0,
123
81
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
124
if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash",
82
+ qemu_fdt_setprop(s->fdt, name, "interrupt-names",
125
sc->flash_size, errp)) {
83
+ interrupt_names, sizeof(interrupt_names));
126
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
84
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
127
return;
85
+ 2, MM_PMC_BBRAM_CTRL,
128
}
86
+ 2, MM_PMC_BBRAM_CTRL_SIZE);
129
87
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
130
+ /* GPIOs */
88
+ g_free(name);
131
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
89
+}
132
+ g_autofree char *name = g_strdup_printf("%c", 'A' + i);
90
+
133
+ dev = DEVICE(&s->gpio[i]);
91
static void fdt_nop_memory_nodes(void *fdt, Error **errp)
134
+ qdev_prop_set_string(dev, "name", name);
92
{
135
+ qdev_prop_set_uint32(dev, "mode-reset",
93
Error *err = NULL;
136
+ stm32l4x5_gpio_cfg[i].moder_reset);
94
@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
137
+ qdev_prop_set_uint32(dev, "ospeed-reset",
95
}
138
+ stm32l4x5_gpio_cfg[i].ospeedr_reset);
96
}
139
+ qdev_prop_set_uint32(dev, "pupd-reset",
97
140
+ stm32l4x5_gpio_cfg[i].pupdr_reset);
98
+static void bbram_attach_drive(XlnxBBRam *dev)
141
+ busdev = SYS_BUS_DEVICE(&s->gpio[i]);
99
+{
142
+ g_free(name);
100
+ DriveInfo *dinfo;
143
+ name = g_strdup_printf("gpio%c-out", 'a' + i);
101
+ BlockBackend *blk;
144
+ qdev_connect_clock_in(DEVICE(&s->gpio[i]), "clk",
102
+
145
+ qdev_get_clock_out(DEVICE(&(s->rcc)), name));
103
+ dinfo = drive_get_by_index(IF_PFLASH, 0);
146
+ if (!sysbus_realize(busdev, errp)) {
104
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
147
+ return;
105
+ if (blk) {
148
+ }
106
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
149
+ sysbus_mmio_map(busdev, 0, stm32l4x5_gpio_cfg[i].addr);
107
+ }
150
+ }
108
+}
151
+
109
+
152
/* System configuration controller */
110
static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
153
busdev = SYS_BUS_DEVICE(&s->syscfg);
111
{
154
if (!sysbus_realize(busdev, errp)) {
112
BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
155
return;
113
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
156
}
114
fdt_add_usb_xhci_nodes(s);
157
sysbus_mmio_map(busdev, 0, SYSCFG_ADDR);
115
fdt_add_sd_nodes(s);
158
- /*
116
fdt_add_rtc_node(s);
159
- * TODO: when the GPIO device is implemented, connect it
117
+ fdt_add_bbram_node(s);
160
- * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and
118
fdt_add_cpu_nodes(s, psci_conduit);
161
- * GPIO_NUM_PINS.
119
fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
162
- */
120
fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
163
+
121
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
164
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
122
memory_region_add_subregion_overlap(get_system_memory(),
165
+ for (unsigned j = 0; j < GPIO_NUM_PINS; j++) {
123
0, &s->soc.fpd.apu.mr, 0);
166
+ pin_index = GPIO_NUM_PINS * i + j;
124
167
+ qdev_connect_gpio_out(DEVICE(&s->gpio[i]), j,
125
+ /* Attach bbram backend, if given */
168
+ qdev_get_gpio_in(DEVICE(&s->syscfg),
126
+ bbram_attach_drive(&s->soc.pmc.bbram);
169
+ pin_index));
127
+
170
+ }
128
/* Plugin SD cards. */
171
+ }
129
for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
172
130
sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
173
/* EXTI device */
131
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
174
busdev = SYS_BUS_DEVICE(&s->exti);
132
index XXXXXXX..XXXXXXX 100644
175
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
133
--- a/hw/arm/xlnx-versal.c
176
}
134
+++ b/hw/arm/xlnx-versal.c
177
}
135
@@ -XXX,XX +XXX,XX @@ static void versal_create_xrams(Versal *s, qemu_irq *pic)
178
136
}
179
- for (unsigned i = 0; i < 16; i++) {
137
}
180
+ for (unsigned i = 0; i < GPIO_NUM_PINS; i++) {
138
181
qdev_connect_gpio_out(DEVICE(&s->syscfg), i,
139
+static void versal_create_bbram(Versal *s, qemu_irq *pic)
182
qdev_get_gpio_in(DEVICE(&s->exti), i));
140
+{
183
}
141
+ SysBusDevice *sbd;
184
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
142
+
185
/* RESERVED: 0x40024400, 0x7FDBC00 */
143
+ object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram,
186
144
+ sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM,
187
/* AHB2 BUS */
145
+ &error_fatal,
188
- create_unimplemented_device("GPIOA", 0x48000000, 0x400);
146
+ "crc-zpads", "0",
189
- create_unimplemented_device("GPIOB", 0x48000400, 0x400);
147
+ NULL);
190
- create_unimplemented_device("GPIOC", 0x48000800, 0x400);
148
+ sbd = SYS_BUS_DEVICE(&s->pmc.bbram);
191
- create_unimplemented_device("GPIOD", 0x48000C00, 0x400);
149
+
192
- create_unimplemented_device("GPIOE", 0x48001000, 0x400);
150
+ sysbus_realize(sbd, &error_fatal);
193
- create_unimplemented_device("GPIOF", 0x48001400, 0x400);
151
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL,
194
- create_unimplemented_device("GPIOG", 0x48001800, 0x400);
152
+ sysbus_mmio_get_region(sbd, 0));
195
- create_unimplemented_device("GPIOH", 0x48001C00, 0x400);
153
+ sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]);
196
/* RESERVED: 0x48002000, 0x7FDBC00 */
154
+}
197
create_unimplemented_device("OTG_FS", 0x50000000, 0x40000);
155
+
198
create_unimplemented_device("ADC", 0x50040000, 0x400);
156
/* This takes the board allocated linear DDR memory and creates aliases
199
diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c
157
* for each split DDR range/aperture on the Versal address map.
200
index XXXXXXX..XXXXXXX 100644
158
*/
201
--- a/hw/misc/stm32l4x5_syscfg.c
159
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
202
+++ b/hw/misc/stm32l4x5_syscfg.c
160
versal_create_sds(s, pic);
203
@@ -XXX,XX +XXX,XX @@
161
versal_create_rtc(s, pic);
204
#include "hw/irq.h"
162
versal_create_xrams(s, pic);
205
#include "migration/vmstate.h"
163
+ versal_create_bbram(s, pic);
206
#include "hw/misc/stm32l4x5_syscfg.h"
164
versal_map_ddr(s);
207
+#include "hw/gpio/stm32l4x5_gpio.h"
165
versal_unimp(s);
208
166
209
#define SYSCFG_MEMRMP 0x00
210
#define SYSCFG_CFGR1 0x04
167
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
211
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
168
index XXXXXXX..XXXXXXX 100644
212
index XXXXXXX..XXXXXXX 100644
169
--- a/hw/arm/Kconfig
213
--- a/hw/arm/Kconfig
170
+++ b/hw/arm/Kconfig
214
+++ b/hw/arm/Kconfig
171
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
215
@@ -XXX,XX +XXX,XX @@ config STM32L4X5_SOC
172
select XLNX_ZDMA
216
bool
173
select XLNX_ZYNQMP
217
select ARM_V7M
174
select OR_IRQ
218
select OR_IRQ
175
+ select XLNX_BBRAM
219
- select STM32L4X5_SYSCFG
176
220
select STM32L4X5_EXTI
177
config NPCM7XX
221
+ select STM32L4X5_SYSCFG
222
select STM32L4X5_RCC
223
+ select STM32L4X5_GPIO
224
225
config XLNX_ZYNQMP_ARM
178
bool
226
bool
179
--
227
--
180
2.20.1
228
2.34.1
181
229
182
230
diff view generated by jsdifflib
[PULL 04/22] hw/nvram: Introduce Xilinx Versal eFuse device
[PULL 11/14] tests/qtest: Add STM32L4x5 GPIO QTest testcase
1
From: Tong Ho <tong.ho@xilinx.com>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
This implements the Xilinx Versal eFuse, an one-time
3
The testcase contains :
4
field-programmable non-volatile storage device. There is
4
- `test_idr_reset_value()` :
5
only one such device in the Xilinx Versal product family.
5
Checks the reset values of MODER, OTYPER, PUPDR, ODR and IDR.
6
- `test_gpio_output_mode()` :
7
Checks that writing a bit in register ODR results in the corresponding
8
pin rising or lowering, if this pin is configured in output mode.
9
- `test_gpio_input_mode()` :
10
Checks that a input pin set high or low externally results
11
in the pin rising and lowering.
12
- `test_pull_up_pull_down()` :
13
Checks that a floating pin in pull-up/down mode is actually high/down.
14
- `test_push_pull()` :
15
Checks that a pin set externally is disconnected when configured in
16
push-pull output mode, and can't be set externally while in this mode.
17
- `test_open_drain()` :
18
Checks that a pin set externally high is disconnected when configured
19
in open-drain output mode, and can't be set high while in this mode.
20
- `test_bsrr_brr()` :
21
Checks that writing to BSRR and BRR has the desired result in ODR.
22
- `test_clock_enable()` :
23
Checks that GPIO clock is at the right frequency after enabling it.
6
24
7
This device has two separate mmio interfaces, a controller
25
Acked-by: Thomas Huth <thuth@redhat.com>
8
and a flatten readback.
26
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
9
27
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
10
The controller provides interfaces for field-programming,
28
Message-id: 20240305210444.310665-4-ines.varhol@telecom-paris.fr
11
configuration, control, and status.
12
13
The flatten readback is a cache to provide a byte-accessible
14
read-only interface to efficiently read efuse array.
15
16
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
17
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
18
19
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
20
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
21
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
22
Message-id: 20210917052400.1249094-3-tong.ho@xilinx.com
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
30
---
26
include/hw/nvram/xlnx-versal-efuse.h | 68 +++
31
tests/qtest/stm32l4x5_gpio-test.c | 551 ++++++++++++++++++++++++++++++
27
hw/nvram/xlnx-versal-efuse-cache.c | 114 ++++
32
tests/qtest/meson.build | 3 +-
28
hw/nvram/xlnx-versal-efuse-ctrl.c | 783 +++++++++++++++++++++++++++
33
2 files changed, 553 insertions(+), 1 deletion(-)
29
hw/nvram/Kconfig | 4 +
34
create mode 100644 tests/qtest/stm32l4x5_gpio-test.c
30
hw/nvram/meson.build | 3 +
31
5 files changed, 972 insertions(+)
32
create mode 100644 include/hw/nvram/xlnx-versal-efuse.h
33
create mode 100644 hw/nvram/xlnx-versal-efuse-cache.c
34
create mode 100644 hw/nvram/xlnx-versal-efuse-ctrl.c
35
35
36
diff --git a/include/hw/nvram/xlnx-versal-efuse.h b/include/hw/nvram/xlnx-versal-efuse.h
36
diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c
37
new file mode 100644
37
new file mode 100644
38
index XXXXXXX..XXXXXXX
38
index XXXXXXX..XXXXXXX
39
--- /dev/null
39
--- /dev/null
40
+++ b/include/hw/nvram/xlnx-versal-efuse.h
40
+++ b/tests/qtest/stm32l4x5_gpio-test.c
41
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@
42
+/*
42
+/*
43
+ * Copyright (c) 2020 Xilinx Inc.
43
+ * QTest testcase for STM32L4x5_GPIO
44
+ *
44
+ *
45
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
45
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
46
+ * of this software and associated documentation files (the "Software"), to deal
46
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
47
+ * in the Software without restriction, including without limitation the rights
48
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
49
+ * copies of the Software, and to permit persons to whom the Software is
50
+ * furnished to do so, subject to the following conditions:
51
+ *
47
+ *
52
+ * The above copyright notice and this permission notice shall be included in
48
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
53
+ * all copies or substantial portions of the Software.
49
+ * See the COPYING file in the top-level directory.
54
+ *
55
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
56
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
57
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
58
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
59
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
60
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
61
+ * THE SOFTWARE.
62
+ */
50
+ */
63
+#ifndef XLNX_VERSAL_EFUSE_H
51
+
64
+#define XLNX_VERSAL_EFUSE_H
52
+#include "qemu/osdep.h"
65
+
53
+#include "libqtest-single.h"
66
+#include "hw/irq.h"
54
+
67
+#include "hw/sysbus.h"
55
+#define GPIO_BASE_ADDR 0x48000000
68
+#include "hw/register.h"
56
+#define GPIO_SIZE 0x400
69
+#include "hw/nvram/xlnx-efuse.h"
57
+#define NUM_GPIOS 8
70
+
58
+#define NUM_GPIO_PINS 16
71
+#define XLNX_VERSAL_EFUSE_CTRL_R_MAX ((0x100 / 4) + 1)
59
+
72
+
60
+#define GPIO_A 0x48000000
73
+#define TYPE_XLNX_VERSAL_EFUSE_CTRL "xlnx,versal-efuse"
61
+#define GPIO_B 0x48000400
74
+#define TYPE_XLNX_VERSAL_EFUSE_CACHE "xlnx,pmc-efuse-cache"
62
+#define GPIO_C 0x48000800
75
+
63
+#define GPIO_D 0x48000C00
76
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCtrl, XLNX_VERSAL_EFUSE_CTRL);
64
+#define GPIO_E 0x48001000
77
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCache, XLNX_VERSAL_EFUSE_CACHE);
65
+#define GPIO_F 0x48001400
78
+
66
+#define GPIO_G 0x48001800
79
+struct XlnxVersalEFuseCtrl {
67
+#define GPIO_H 0x48001C00
80
+ SysBusDevice parent_obj;
68
+
81
+ qemu_irq irq_efuse_imr;
69
+#define MODER 0x00
82
+
70
+#define OTYPER 0x04
83
+ XlnxEFuse *efuse;
71
+#define PUPDR 0x0C
84
+
72
+#define IDR 0x10
85
+ void *extra_pg0_lock_spec; /* Opaque property */
73
+#define ODR 0x14
86
+ uint32_t extra_pg0_lock_n16;
74
+#define BSRR 0x18
87
+
75
+#define BRR 0x28
88
+ uint32_t regs[XLNX_VERSAL_EFUSE_CTRL_R_MAX];
76
+
89
+ RegisterInfo regs_info[XLNX_VERSAL_EFUSE_CTRL_R_MAX];
77
+#define MODER_INPUT 0
78
+#define MODER_OUTPUT 1
79
+
80
+#define PUPDR_NONE 0
81
+#define PUPDR_PULLUP 1
82
+#define PUPDR_PULLDOWN 2
83
+
84
+#define OTYPER_PUSH_PULL 0
85
+#define OTYPER_OPEN_DRAIN 1
86
+
87
+const uint32_t moder_reset[NUM_GPIOS] = {
88
+ 0xABFFFFFF,
89
+ 0xFFFFFEBF,
90
+ 0xFFFFFFFF,
91
+ 0xFFFFFFFF,
92
+ 0xFFFFFFFF,
93
+ 0xFFFFFFFF,
94
+ 0xFFFFFFFF,
95
+ 0x0000000F
90
+};
96
+};
91
+
97
+
92
+struct XlnxVersalEFuseCache {
98
+const uint32_t pupdr_reset[NUM_GPIOS] = {
93
+ SysBusDevice parent_obj;
99
+ 0x64000000,
94
+ MemoryRegion iomem;
100
+ 0x00000100,
95
+
101
+ 0x00000000,
96
+ XlnxEFuse *efuse;
102
+ 0x00000000,
103
+ 0x00000000,
104
+ 0x00000000,
105
+ 0x00000000,
106
+ 0x00000000
97
+};
107
+};
98
+
108
+
99
+/**
109
+const uint32_t idr_reset[NUM_GPIOS] = {
100
+ * xlnx_versal_efuse_read_row:
110
+ 0x0000A000,
101
+ * @s: the efuse object
111
+ 0x00000010,
102
+ * @bit: the bit-address within the 32-bit row to be read
112
+ 0x00000000,
103
+ * @denied: if non-NULL, to receive true if the row is write-only
113
+ 0x00000000,
104
+ *
114
+ 0x00000000,
105
+ * Returns: the 32-bit word containing address @bit; 0 if @denies is true
115
+ 0x00000000,
106
+ */
116
+ 0x00000000,
107
+uint32_t xlnx_versal_efuse_read_row(XlnxEFuse *s, uint32_t bit, bool *denied);
117
+ 0x00000000
108
+
118
+};
109
+#endif
119
+
110
diff --git a/hw/nvram/xlnx-versal-efuse-cache.c b/hw/nvram/xlnx-versal-efuse-cache.c
120
+static uint32_t gpio_readl(unsigned int gpio, unsigned int offset)
111
new file mode 100644
121
+{
112
index XXXXXXX..XXXXXXX
122
+ return readl(gpio + offset);
113
--- /dev/null
123
+}
114
+++ b/hw/nvram/xlnx-versal-efuse-cache.c
124
+
115
@@ -XXX,XX +XXX,XX @@
125
+static void gpio_writel(unsigned int gpio, unsigned int offset, uint32_t value)
116
+/*
126
+{
117
+ * QEMU model of the EFuse_Cache
127
+ writel(gpio + offset, value);
118
+ *
128
+}
119
+ * Copyright (c) 2017 Xilinx Inc.
129
+
120
+ *
130
+static void gpio_set_bit(unsigned int gpio, unsigned int reg,
121
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
131
+ unsigned int pin, uint32_t value)
122
+ * of this software and associated documentation files (the "Software"), to deal
132
+{
123
+ * in the Software without restriction, including without limitation the rights
133
+ uint32_t mask = 0xFFFFFFFF & ~(0x1 << pin);
124
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
134
+ gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << pin);
125
+ * copies of the Software, and to permit persons to whom the Software is
135
+}
126
+ * furnished to do so, subject to the following conditions:
136
+
127
+ *
137
+static void gpio_set_2bits(unsigned int gpio, unsigned int reg,
128
+ * The above copyright notice and this permission notice shall be included in
138
+ unsigned int pin, uint32_t value)
129
+ * all copies or substantial portions of the Software.
139
+{
130
+ *
140
+ uint32_t offset = 2 * pin;
131
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
141
+ uint32_t mask = 0xFFFFFFFF & ~(0x3 << offset);
132
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
142
+ gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << offset);
133
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
143
+}
134
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
144
+
135
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
145
+static unsigned int get_gpio_id(uint32_t gpio_addr)
136
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
146
+{
137
+ * THE SOFTWARE.
147
+ return (gpio_addr - GPIO_BASE_ADDR) / GPIO_SIZE;
138
+ */
148
+}
139
+
149
+
140
+#include "qemu/osdep.h"
150
+static void gpio_set_irq(unsigned int gpio, int num, int level)
141
+#include "hw/nvram/xlnx-versal-efuse.h"
151
+{
142
+
152
+ g_autofree char *name = g_strdup_printf("/machine/soc/gpio%c",
143
+#include "qemu/log.h"
153
+ get_gpio_id(gpio) + 'a');
144
+#include "hw/qdev-properties.h"
154
+ qtest_set_irq_in(global_qtest, name, NULL, num, level);
145
+
155
+}
146
+#define MR_SIZE 0xC00
156
+
147
+
157
+static void disconnect_all_pins(unsigned int gpio)
148
+static uint64_t efuse_cache_read(void *opaque, hwaddr addr, unsigned size)
158
+{
149
+{
159
+ g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c",
150
+ XlnxVersalEFuseCache *s = XLNX_VERSAL_EFUSE_CACHE(opaque);
160
+ get_gpio_id(gpio) + 'a');
151
+ unsigned int w0 = QEMU_ALIGN_DOWN(addr * 8, 32);
161
+ QDict *r;
152
+ unsigned int w1 = QEMU_ALIGN_DOWN((addr + size - 1) * 8, 32);
162
+
153
+
163
+ r = qtest_qmp(global_qtest, "{ 'execute': 'qom-set', 'arguments': "
154
+ uint64_t ret;
164
+ "{ 'path': %s, 'property': 'disconnected-pins', 'value': %d } }",
155
+
165
+ path, 0xFFFF);
156
+ assert(w0 == w1 || (w0 + 32) == w1);
166
+ g_assert_false(qdict_haskey(r, "error"));
157
+
167
+ qobject_unref(r);
158
+ ret = xlnx_versal_efuse_read_row(s->efuse, w1, NULL);
168
+}
159
+ if (w0 < w1) {
169
+
160
+ ret <<= 32;
170
+static uint32_t get_disconnected_pins(unsigned int gpio)
161
+ ret |= xlnx_versal_efuse_read_row(s->efuse, w0, NULL);
171
+{
172
+ g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c",
173
+ get_gpio_id(gpio) + 'a');
174
+ uint32_t disconnected_pins = 0;
175
+ QDict *r;
176
+
177
+ r = qtest_qmp(global_qtest, "{ 'execute': 'qom-get', 'arguments':"
178
+ " { 'path': %s, 'property': 'disconnected-pins'} }", path);
179
+ g_assert_false(qdict_haskey(r, "error"));
180
+ disconnected_pins = qdict_get_int(r, "return");
181
+ qobject_unref(r);
182
+ return disconnected_pins;
183
+}
184
+
185
+static uint32_t reset(uint32_t gpio, unsigned int offset)
186
+{
187
+ switch (offset) {
188
+ case MODER:
189
+ return moder_reset[get_gpio_id(gpio)];
190
+ case PUPDR:
191
+ return pupdr_reset[get_gpio_id(gpio)];
192
+ case IDR:
193
+ return idr_reset[get_gpio_id(gpio)];
162
+ }
194
+ }
163
+
195
+ return 0x0;
164
+ /* If 'addr' unaligned, the guest is always assumed to be little-endian. */
196
+}
165
+ addr &= 3;
197
+
166
+ if (addr) {
198
+static void system_reset(void)
167
+ ret >>= 8 * addr;
199
+{
168
+ }
200
+ QDict *r;
201
+ r = qtest_qmp(global_qtest, "{'execute': 'system_reset'}");
202
+ g_assert_false(qdict_haskey(r, "error"));
203
+ qobject_unref(r);
204
+}
205
+
206
+static void test_idr_reset_value(void)
207
+{
208
+ /*
209
+ * Checks that the values in MODER, OTYPER, PUPDR and ODR
210
+ * after reset are correct, and that the value in IDR is
211
+ * coherent.
212
+ * Since AF and analog modes aren't implemented, IDR reset
213
+ * values aren't the same as with a real board.
214
+ *
215
+ * Register IDR contains the actual values of all GPIO pins.
216
+ * Its value depends on the pins' configuration
217
+ * (intput/output/analog : register MODER, push-pull/open-drain :
218
+ * register OTYPER, pull-up/pull-down/none : register PUPDR)
219
+ * and on the values stored in register ODR
220
+ * (in case the pin is in output mode).
221
+ */
222
+
223
+ gpio_writel(GPIO_A, MODER, 0xDEADBEEF);
224
+ gpio_writel(GPIO_A, ODR, 0xDEADBEEF);
225
+ gpio_writel(GPIO_A, OTYPER, 0xDEADBEEF);
226
+ gpio_writel(GPIO_A, PUPDR, 0xDEADBEEF);
227
+
228
+ gpio_writel(GPIO_B, MODER, 0xDEADBEEF);
229
+ gpio_writel(GPIO_B, ODR, 0xDEADBEEF);
230
+ gpio_writel(GPIO_B, OTYPER, 0xDEADBEEF);
231
+ gpio_writel(GPIO_B, PUPDR, 0xDEADBEEF);
232
+
233
+ gpio_writel(GPIO_C, MODER, 0xDEADBEEF);
234
+ gpio_writel(GPIO_C, ODR, 0xDEADBEEF);
235
+ gpio_writel(GPIO_C, OTYPER, 0xDEADBEEF);
236
+ gpio_writel(GPIO_C, PUPDR, 0xDEADBEEF);
237
+
238
+ gpio_writel(GPIO_H, MODER, 0xDEADBEEF);
239
+ gpio_writel(GPIO_H, ODR, 0xDEADBEEF);
240
+ gpio_writel(GPIO_H, OTYPER, 0xDEADBEEF);
241
+ gpio_writel(GPIO_H, PUPDR, 0xDEADBEEF);
242
+
243
+ system_reset();
244
+
245
+ uint32_t moder = gpio_readl(GPIO_A, MODER);
246
+ uint32_t odr = gpio_readl(GPIO_A, ODR);
247
+ uint32_t otyper = gpio_readl(GPIO_A, OTYPER);
248
+ uint32_t pupdr = gpio_readl(GPIO_A, PUPDR);
249
+ uint32_t idr = gpio_readl(GPIO_A, IDR);
250
+ /* 15: AF, 14: AF, 13: AF, 12: Analog ... */
251
+ /* here AF is the same as Analog and Input mode */
252
+ g_assert_cmphex(moder, ==, reset(GPIO_A, MODER));
253
+ g_assert_cmphex(odr, ==, reset(GPIO_A, ODR));
254
+ g_assert_cmphex(otyper, ==, reset(GPIO_A, OTYPER));
255
+ /* 15: pull-up, 14: pull-down, 13: pull-up, 12: neither ... */
256
+ g_assert_cmphex(pupdr, ==, reset(GPIO_A, PUPDR));
257
+ /* 15 : 1, 14: 0, 13: 1, 12 : reset value ... */
258
+ g_assert_cmphex(idr, ==, reset(GPIO_A, IDR));
259
+
260
+ moder = gpio_readl(GPIO_B, MODER);
261
+ odr = gpio_readl(GPIO_B, ODR);
262
+ otyper = gpio_readl(GPIO_B, OTYPER);
263
+ pupdr = gpio_readl(GPIO_B, PUPDR);
264
+ idr = gpio_readl(GPIO_B, IDR);
265
+ /* ... 5: Analog, 4: AF, 3: AF, 2: Analog ... */
266
+ /* here AF is the same as Analog and Input mode */
267
+ g_assert_cmphex(moder, ==, reset(GPIO_B, MODER));
268
+ g_assert_cmphex(odr, ==, reset(GPIO_B, ODR));
269
+ g_assert_cmphex(otyper, ==, reset(GPIO_B, OTYPER));
270
+ /* ... 5: neither, 4: pull-up, 3: neither ... */
271
+ g_assert_cmphex(pupdr, ==, reset(GPIO_B, PUPDR));
272
+ /* ... 5 : reset value, 4 : 1, 3 : reset value ... */
273
+ g_assert_cmphex(idr, ==, reset(GPIO_B, IDR));
274
+
275
+ moder = gpio_readl(GPIO_C, MODER);
276
+ odr = gpio_readl(GPIO_C, ODR);
277
+ otyper = gpio_readl(GPIO_C, OTYPER);
278
+ pupdr = gpio_readl(GPIO_C, PUPDR);
279
+ idr = gpio_readl(GPIO_C, IDR);
280
+ /* Analog, same as Input mode*/
281
+ g_assert_cmphex(moder, ==, reset(GPIO_C, MODER));
282
+ g_assert_cmphex(odr, ==, reset(GPIO_C, ODR));
283
+ g_assert_cmphex(otyper, ==, reset(GPIO_C, OTYPER));
284
+ /* no pull-up or pull-down */
285
+ g_assert_cmphex(pupdr, ==, reset(GPIO_C, PUPDR));
286
+ /* reset value */
287
+ g_assert_cmphex(idr, ==, reset(GPIO_C, IDR));
288
+
289
+ moder = gpio_readl(GPIO_H, MODER);
290
+ odr = gpio_readl(GPIO_H, ODR);
291
+ otyper = gpio_readl(GPIO_H, OTYPER);
292
+ pupdr = gpio_readl(GPIO_H, PUPDR);
293
+ idr = gpio_readl(GPIO_H, IDR);
294
+ /* Analog, same as Input mode */
295
+ g_assert_cmphex(moder, ==, reset(GPIO_H, MODER));
296
+ g_assert_cmphex(odr, ==, reset(GPIO_H, ODR));
297
+ g_assert_cmphex(otyper, ==, reset(GPIO_H, OTYPER));
298
+ /* no pull-up or pull-down */
299
+ g_assert_cmphex(pupdr, ==, reset(GPIO_H, PUPDR));
300
+ /* reset value */
301
+ g_assert_cmphex(idr, ==, reset(GPIO_H, IDR));
302
+}
303
+
304
+static void test_gpio_output_mode(const void *data)
305
+{
306
+ /*
307
+ * Checks that setting a bit in ODR sets the corresponding
308
+ * GPIO line high : it should set the right bit in IDR
309
+ * and send an irq to syscfg.
310
+ * Additionally, it checks that values written to ODR
311
+ * when not in output mode are stored and not discarded.
312
+ */
313
+ unsigned int pin = ((uint64_t)data) & 0xF;
314
+ uint32_t gpio = ((uint64_t)data) >> 32;
315
+ unsigned int gpio_id = get_gpio_id(gpio);
316
+
317
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
318
+
319
+ /* Set a bit in ODR and check nothing happens */
320
+ gpio_set_bit(gpio, ODR, pin, 1);
321
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
322
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
323
+
324
+ /* Configure the relevant line as output and check the pin is high */
325
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
326
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
327
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
328
+
329
+ /* Reset the bit in ODR and check the pin is low */
330
+ gpio_set_bit(gpio, ODR, pin, 0);
331
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
332
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
333
+
334
+ /* Clean the test */
335
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
336
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
337
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
338
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
339
+}
340
+
341
+static void test_gpio_input_mode(const void *data)
342
+{
343
+ /*
344
+ * Test that setting a line high/low externally sets the
345
+ * corresponding GPIO line high/low : it should set the
346
+ * right bit in IDR and send an irq to syscfg.
347
+ */
348
+ unsigned int pin = ((uint64_t)data) & 0xF;
349
+ uint32_t gpio = ((uint64_t)data) >> 32;
350
+ unsigned int gpio_id = get_gpio_id(gpio);
351
+
352
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
353
+
354
+ /* Configure a line as input, raise it, and check that the pin is high */
355
+ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
356
+ gpio_set_irq(gpio, pin, 1);
357
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
358
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
359
+
360
+ /* Lower the line and check that the pin is low */
361
+ gpio_set_irq(gpio, pin, 0);
362
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
363
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
364
+
365
+ /* Clean the test */
366
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
367
+ disconnect_all_pins(gpio);
368
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
369
+}
370
+
371
+static void test_pull_up_pull_down(const void *data)
372
+{
373
+ /*
374
+ * Test that a floating pin with pull-up sets the pin
375
+ * high and vice-versa.
376
+ */
377
+ unsigned int pin = ((uint64_t)data) & 0xF;
378
+ uint32_t gpio = ((uint64_t)data) >> 32;
379
+ unsigned int gpio_id = get_gpio_id(gpio);
380
+
381
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
382
+
383
+ /* Configure a line as input with pull-up, check the line is set high */
384
+ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
385
+ gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLUP);
386
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
387
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
388
+
389
+ /* Configure the line with pull-down, check the line is low */
390
+ gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLDOWN);
391
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
392
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
393
+
394
+ /* Clean the test */
395
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
396
+ gpio_writel(gpio, PUPDR, reset(gpio, PUPDR));
397
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
398
+}
399
+
400
+static void test_push_pull(const void *data)
401
+{
402
+ /*
403
+ * Test that configuring a line in push-pull output mode
404
+ * disconnects the pin, that the pin can't be set or reset
405
+ * externally afterwards.
406
+ */
407
+ unsigned int pin = ((uint64_t)data) & 0xF;
408
+ uint32_t gpio = ((uint64_t)data) >> 32;
409
+ uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
410
+
411
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
412
+
413
+ /* Setting a line high externally, configuring it in push-pull output */
414
+ /* And checking the pin was disconnected */
415
+ gpio_set_irq(gpio, pin, 1);
416
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
417
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
418
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
419
+
420
+ /* Setting a line low externally, configuring it in push-pull output */
421
+ /* And checking the pin was disconnected */
422
+ gpio_set_irq(gpio2, pin, 0);
423
+ gpio_set_bit(gpio2, ODR, pin, 1);
424
+ gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT);
425
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF);
426
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin));
427
+
428
+ /* Trying to set a push-pull output pin, checking it doesn't work */
429
+ gpio_set_irq(gpio, pin, 1);
430
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
431
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
432
+
433
+ /* Trying to reset a push-pull output pin, checking it doesn't work */
434
+ gpio_set_irq(gpio2, pin, 0);
435
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF);
436
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin));
437
+
438
+ /* Clean the test */
439
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
440
+ gpio_writel(gpio2, ODR, reset(gpio2, ODR));
441
+ gpio_writel(gpio2, MODER, reset(gpio2, MODER));
442
+}
443
+
444
+static void test_open_drain(const void *data)
445
+{
446
+ /*
447
+ * Test that configuring a line in open-drain output mode
448
+ * disconnects a pin set high externally and that the pin
449
+ * can't be set high externally while configured in open-drain.
450
+ *
451
+ * However a pin set low externally shouldn't be disconnected,
452
+ * and it can be set low externally when in open-drain mode.
453
+ */
454
+ unsigned int pin = ((uint64_t)data) & 0xF;
455
+ uint32_t gpio = ((uint64_t)data) >> 32;
456
+ uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
457
+
458
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
459
+
460
+ /* Setting a line high externally, configuring it in open-drain output */
461
+ /* And checking the pin was disconnected */
462
+ gpio_set_irq(gpio, pin, 1);
463
+ gpio_set_bit(gpio, OTYPER, pin, OTYPER_OPEN_DRAIN);
464
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
465
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
466
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
467
+
468
+ /* Setting a line low externally, configuring it in open-drain output */
469
+ /* And checking the pin wasn't disconnected */
470
+ gpio_set_irq(gpio2, pin, 0);
471
+ gpio_set_bit(gpio2, ODR, pin, 1);
472
+ gpio_set_bit(gpio2, OTYPER, pin, OTYPER_OPEN_DRAIN);
473
+ gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT);
474
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin));
475
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==,
476
+ reset(gpio2, IDR) & ~(1 << pin));
477
+
478
+ /* Trying to set a open-drain output pin, checking it doesn't work */
479
+ gpio_set_irq(gpio, pin, 1);
480
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
481
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
482
+
483
+ /* Trying to reset a open-drain output pin, checking it works */
484
+ gpio_set_bit(gpio, ODR, pin, 1);
485
+ gpio_set_irq(gpio, pin, 0);
486
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin));
487
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==,
488
+ reset(gpio2, IDR) & ~(1 << pin));
489
+
490
+ /* Clean the test */
491
+ disconnect_all_pins(gpio2);
492
+ gpio_writel(gpio2, OTYPER, reset(gpio2, OTYPER));
493
+ gpio_writel(gpio2, ODR, reset(gpio2, ODR));
494
+ gpio_writel(gpio2, MODER, reset(gpio2, MODER));
495
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR));
496
+ disconnect_all_pins(gpio);
497
+ gpio_writel(gpio, OTYPER, reset(gpio, OTYPER));
498
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
499
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
500
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
501
+}
502
+
503
+static void test_bsrr_brr(const void *data)
504
+{
505
+ /*
506
+ * Test that writing a '1' in BSS and BSRR
507
+ * has the desired effect on ODR.
508
+ * In BSRR, BSx has priority over BRx.
509
+ */
510
+ unsigned int pin = ((uint64_t)data) & 0xF;
511
+ uint32_t gpio = ((uint64_t)data) >> 32;
512
+
513
+ gpio_writel(gpio, BSRR, (1 << pin));
514
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
515
+
516
+ gpio_writel(gpio, BSRR, (1 << (pin + NUM_GPIO_PINS)));
517
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
518
+
519
+ gpio_writel(gpio, BSRR, (1 << pin));
520
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
521
+
522
+ gpio_writel(gpio, BRR, (1 << pin));
523
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
524
+
525
+ /* BSx should have priority over BRx */
526
+ gpio_writel(gpio, BSRR, (1 << pin) | (1 << (pin + NUM_GPIO_PINS)));
527
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
528
+
529
+ gpio_writel(gpio, BRR, (1 << pin));
530
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
531
+
532
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
533
+}
534
+
535
+int main(int argc, char **argv)
536
+{
537
+ int ret;
538
+
539
+ g_test_init(&argc, &argv, NULL);
540
+ g_test_set_nonfatal_assertions();
541
+ qtest_add_func("stm32l4x5/gpio/test_idr_reset_value",
542
+ test_idr_reset_value);
543
+ /*
544
+ * The inputs for the tests (gpio and pin) can be changed,
545
+ * but the tests don't work for pins that are high at reset
546
+ * (GPIOA15, GPIO13 and GPIOB5).
547
+ * Specifically, rising the pin then checking `get_irq()`
548
+ * is problematic since the pin was already high.
549
+ */
550
+ qtest_add_data_func("stm32l4x5/gpio/test_gpioc5_output_mode",
551
+ (void *)((uint64_t)GPIO_C << 32 | 5),
552
+ test_gpio_output_mode);
553
+ qtest_add_data_func("stm32l4x5/gpio/test_gpioh3_output_mode",
554
+ (void *)((uint64_t)GPIO_H << 32 | 3),
555
+ test_gpio_output_mode);
556
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode1",
557
+ (void *)((uint64_t)GPIO_D << 32 | 6),
558
+ test_gpio_input_mode);
559
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode2",
560
+ (void *)((uint64_t)GPIO_C << 32 | 10),
561
+ test_gpio_input_mode);
562
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down1",
563
+ (void *)((uint64_t)GPIO_B << 32 | 5),
564
+ test_pull_up_pull_down);
565
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down2",
566
+ (void *)((uint64_t)GPIO_F << 32 | 1),
567
+ test_pull_up_pull_down);
568
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull1",
569
+ (void *)((uint64_t)GPIO_G << 32 | 6),
570
+ test_push_pull);
571
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull2",
572
+ (void *)((uint64_t)GPIO_H << 32 | 3),
573
+ test_push_pull);
574
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain1",
575
+ (void *)((uint64_t)GPIO_C << 32 | 4),
576
+ test_open_drain);
577
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain2",
578
+ (void *)((uint64_t)GPIO_E << 32 | 11),
579
+ test_open_drain);
580
+ qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr1",
581
+ (void *)((uint64_t)GPIO_A << 32 | 12),
582
+ test_bsrr_brr);
583
+ qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2",
584
+ (void *)((uint64_t)GPIO_D << 32 | 0),
585
+ test_bsrr_brr);
586
+
587
+ qtest_start("-machine b-l475e-iot01a");
588
+ ret = g_test_run();
589
+ qtest_end();
169
+
590
+
170
+ return ret;
591
+ return ret;
171
+}
592
+}
172
+
593
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
173
+static void efuse_cache_write(void *opaque, hwaddr addr, uint64_t value,
174
+ unsigned size)
175
+{
176
+ /* No Register Writes allowed */
177
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: efuse cache registers are read-only",
178
+ __func__);
179
+}
180
+
181
+static const MemoryRegionOps efuse_cache_ops = {
182
+ .read = efuse_cache_read,
183
+ .write = efuse_cache_write,
184
+ .endianness = DEVICE_LITTLE_ENDIAN,
185
+ .valid = {
186
+ .min_access_size = 1,
187
+ .max_access_size = 4,
188
+ },
189
+};
190
+
191
+static void efuse_cache_init(Object *obj)
192
+{
193
+ XlnxVersalEFuseCache *s = XLNX_VERSAL_EFUSE_CACHE(obj);
194
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
195
+
196
+ memory_region_init_io(&s->iomem, obj, &efuse_cache_ops, s,
197
+ TYPE_XLNX_VERSAL_EFUSE_CACHE, MR_SIZE);
198
+ sysbus_init_mmio(sbd, &s->iomem);
199
+}
200
+
201
+static Property efuse_cache_props[] = {
202
+ DEFINE_PROP_LINK("efuse",
203
+ XlnxVersalEFuseCache, efuse,
204
+ TYPE_XLNX_EFUSE, XlnxEFuse *),
205
+
206
+ DEFINE_PROP_END_OF_LIST(),
207
+};
208
+
209
+static void efuse_cache_class_init(ObjectClass *klass, void *data)
210
+{
211
+ DeviceClass *dc = DEVICE_CLASS(klass);
212
+
213
+ device_class_set_props(dc, efuse_cache_props);
214
+}
215
+
216
+static const TypeInfo efuse_cache_info = {
217
+ .name = TYPE_XLNX_VERSAL_EFUSE_CACHE,
218
+ .parent = TYPE_SYS_BUS_DEVICE,
219
+ .instance_size = sizeof(XlnxVersalEFuseCache),
220
+ .class_init = efuse_cache_class_init,
221
+ .instance_init = efuse_cache_init,
222
+};
223
+
224
+static void efuse_cache_register_types(void)
225
+{
226
+ type_register_static(&efuse_cache_info);
227
+}
228
+
229
+type_init(efuse_cache_register_types)
230
diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c
231
new file mode 100644
232
index XXXXXXX..XXXXXXX
233
--- /dev/null
234
+++ b/hw/nvram/xlnx-versal-efuse-ctrl.c
235
@@ -XXX,XX +XXX,XX @@
236
+/*
237
+ * QEMU model of the Versal eFuse controller
238
+ *
239
+ * Copyright (c) 2020 Xilinx Inc.
240
+ *
241
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
242
+ * of this software and associated documentation files (the "Software"), to deal
243
+ * in the Software without restriction, including without limitation the rights
244
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
245
+ * copies of the Software, and to permit persons to whom the Software is
246
+ * furnished to do so, subject to the following conditions:
247
+ *
248
+ * The above copyright notice and this permission notice shall be included in
249
+ * all copies or substantial portions of the Software.
250
+ *
251
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
252
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
253
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
254
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
255
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
256
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
257
+ * THE SOFTWARE.
258
+ */
259
+
260
+#include "qemu/osdep.h"
261
+#include "hw/nvram/xlnx-versal-efuse.h"
262
+
263
+#include "qemu/log.h"
264
+#include "qapi/error.h"
265
+#include "migration/vmstate.h"
266
+#include "hw/qdev-properties.h"
267
+
268
+#ifndef XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG
269
+#define XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG 0
270
+#endif
271
+
272
+REG32(WR_LOCK, 0x0)
273
+ FIELD(WR_LOCK, LOCK, 0, 16)
274
+REG32(CFG, 0x4)
275
+ FIELD(CFG, SLVERR_ENABLE, 5, 1)
276
+ FIELD(CFG, MARGIN_RD, 2, 1)
277
+ FIELD(CFG, PGM_EN, 1, 1)
278
+REG32(STATUS, 0x8)
279
+ FIELD(STATUS, AES_USER_KEY_1_CRC_PASS, 11, 1)
280
+ FIELD(STATUS, AES_USER_KEY_1_CRC_DONE, 10, 1)
281
+ FIELD(STATUS, AES_USER_KEY_0_CRC_PASS, 9, 1)
282
+ FIELD(STATUS, AES_USER_KEY_0_CRC_DONE, 8, 1)
283
+ FIELD(STATUS, AES_CRC_PASS, 7, 1)
284
+ FIELD(STATUS, AES_CRC_DONE, 6, 1)
285
+ FIELD(STATUS, CACHE_DONE, 5, 1)
286
+ FIELD(STATUS, CACHE_LOAD, 4, 1)
287
+ FIELD(STATUS, EFUSE_2_TBIT, 2, 1)
288
+ FIELD(STATUS, EFUSE_1_TBIT, 1, 1)
289
+ FIELD(STATUS, EFUSE_0_TBIT, 0, 1)
290
+REG32(EFUSE_PGM_ADDR, 0xc)
291
+ FIELD(EFUSE_PGM_ADDR, PAGE, 13, 4)
292
+ FIELD(EFUSE_PGM_ADDR, ROW, 5, 8)
293
+ FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5)
294
+REG32(EFUSE_RD_ADDR, 0x10)
295
+ FIELD(EFUSE_RD_ADDR, PAGE, 13, 4)
296
+ FIELD(EFUSE_RD_ADDR, ROW, 5, 8)
297
+REG32(EFUSE_RD_DATA, 0x14)
298
+REG32(TPGM, 0x18)
299
+ FIELD(TPGM, VALUE, 0, 16)
300
+REG32(TRD, 0x1c)
301
+ FIELD(TRD, VALUE, 0, 8)
302
+REG32(TSU_H_PS, 0x20)
303
+ FIELD(TSU_H_PS, VALUE, 0, 8)
304
+REG32(TSU_H_PS_CS, 0x24)
305
+ FIELD(TSU_H_PS_CS, VALUE, 0, 8)
306
+REG32(TRDM, 0x28)
307
+ FIELD(TRDM, VALUE, 0, 8)
308
+REG32(TSU_H_CS, 0x2c)
309
+ FIELD(TSU_H_CS, VALUE, 0, 8)
310
+REG32(EFUSE_ISR, 0x30)
311
+ FIELD(EFUSE_ISR, APB_SLVERR, 31, 1)
312
+ FIELD(EFUSE_ISR, CACHE_PARITY_E2, 14, 1)
313
+ FIELD(EFUSE_ISR, CACHE_PARITY_E1, 13, 1)
314
+ FIELD(EFUSE_ISR, CACHE_PARITY_E0S, 12, 1)
315
+ FIELD(EFUSE_ISR, CACHE_PARITY_E0R, 11, 1)
316
+ FIELD(EFUSE_ISR, CACHE_APB_SLVERR, 10, 1)
317
+ FIELD(EFUSE_ISR, CACHE_REQ_ERROR, 9, 1)
318
+ FIELD(EFUSE_ISR, MAIN_REQ_ERROR, 8, 1)
319
+ FIELD(EFUSE_ISR, READ_ON_CACHE_LD, 7, 1)
320
+ FIELD(EFUSE_ISR, CACHE_FSM_ERROR, 6, 1)
321
+ FIELD(EFUSE_ISR, MAIN_FSM_ERROR, 5, 1)
322
+ FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1)
323
+ FIELD(EFUSE_ISR, RD_ERROR, 3, 1)
324
+ FIELD(EFUSE_ISR, RD_DONE, 2, 1)
325
+ FIELD(EFUSE_ISR, PGM_ERROR, 1, 1)
326
+ FIELD(EFUSE_ISR, PGM_DONE, 0, 1)
327
+REG32(EFUSE_IMR, 0x34)
328
+ FIELD(EFUSE_IMR, APB_SLVERR, 31, 1)
329
+ FIELD(EFUSE_IMR, CACHE_PARITY_E2, 14, 1)
330
+ FIELD(EFUSE_IMR, CACHE_PARITY_E1, 13, 1)
331
+ FIELD(EFUSE_IMR, CACHE_PARITY_E0S, 12, 1)
332
+ FIELD(EFUSE_IMR, CACHE_PARITY_E0R, 11, 1)
333
+ FIELD(EFUSE_IMR, CACHE_APB_SLVERR, 10, 1)
334
+ FIELD(EFUSE_IMR, CACHE_REQ_ERROR, 9, 1)
335
+ FIELD(EFUSE_IMR, MAIN_REQ_ERROR, 8, 1)
336
+ FIELD(EFUSE_IMR, READ_ON_CACHE_LD, 7, 1)
337
+ FIELD(EFUSE_IMR, CACHE_FSM_ERROR, 6, 1)
338
+ FIELD(EFUSE_IMR, MAIN_FSM_ERROR, 5, 1)
339
+ FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1)
340
+ FIELD(EFUSE_IMR, RD_ERROR, 3, 1)
341
+ FIELD(EFUSE_IMR, RD_DONE, 2, 1)
342
+ FIELD(EFUSE_IMR, PGM_ERROR, 1, 1)
343
+ FIELD(EFUSE_IMR, PGM_DONE, 0, 1)
344
+REG32(EFUSE_IER, 0x38)
345
+ FIELD(EFUSE_IER, APB_SLVERR, 31, 1)
346
+ FIELD(EFUSE_IER, CACHE_PARITY_E2, 14, 1)
347
+ FIELD(EFUSE_IER, CACHE_PARITY_E1, 13, 1)
348
+ FIELD(EFUSE_IER, CACHE_PARITY_E0S, 12, 1)
349
+ FIELD(EFUSE_IER, CACHE_PARITY_E0R, 11, 1)
350
+ FIELD(EFUSE_IER, CACHE_APB_SLVERR, 10, 1)
351
+ FIELD(EFUSE_IER, CACHE_REQ_ERROR, 9, 1)
352
+ FIELD(EFUSE_IER, MAIN_REQ_ERROR, 8, 1)
353
+ FIELD(EFUSE_IER, READ_ON_CACHE_LD, 7, 1)
354
+ FIELD(EFUSE_IER, CACHE_FSM_ERROR, 6, 1)
355
+ FIELD(EFUSE_IER, MAIN_FSM_ERROR, 5, 1)
356
+ FIELD(EFUSE_IER, CACHE_ERROR, 4, 1)
357
+ FIELD(EFUSE_IER, RD_ERROR, 3, 1)
358
+ FIELD(EFUSE_IER, RD_DONE, 2, 1)
359
+ FIELD(EFUSE_IER, PGM_ERROR, 1, 1)
360
+ FIELD(EFUSE_IER, PGM_DONE, 0, 1)
361
+REG32(EFUSE_IDR, 0x3c)
362
+ FIELD(EFUSE_IDR, APB_SLVERR, 31, 1)
363
+ FIELD(EFUSE_IDR, CACHE_PARITY_E2, 14, 1)
364
+ FIELD(EFUSE_IDR, CACHE_PARITY_E1, 13, 1)
365
+ FIELD(EFUSE_IDR, CACHE_PARITY_E0S, 12, 1)
366
+ FIELD(EFUSE_IDR, CACHE_PARITY_E0R, 11, 1)
367
+ FIELD(EFUSE_IDR, CACHE_APB_SLVERR, 10, 1)
368
+ FIELD(EFUSE_IDR, CACHE_REQ_ERROR, 9, 1)
369
+ FIELD(EFUSE_IDR, MAIN_REQ_ERROR, 8, 1)
370
+ FIELD(EFUSE_IDR, READ_ON_CACHE_LD, 7, 1)
371
+ FIELD(EFUSE_IDR, CACHE_FSM_ERROR, 6, 1)
372
+ FIELD(EFUSE_IDR, MAIN_FSM_ERROR, 5, 1)
373
+ FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1)
374
+ FIELD(EFUSE_IDR, RD_ERROR, 3, 1)
375
+ FIELD(EFUSE_IDR, RD_DONE, 2, 1)
376
+ FIELD(EFUSE_IDR, PGM_ERROR, 1, 1)
377
+ FIELD(EFUSE_IDR, PGM_DONE, 0, 1)
378
+REG32(EFUSE_CACHE_LOAD, 0x40)
379
+ FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1)
380
+REG32(EFUSE_PGM_LOCK, 0x44)
381
+ FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1)
382
+REG32(EFUSE_AES_CRC, 0x48)
383
+REG32(EFUSE_AES_USR_KEY0_CRC, 0x4c)
384
+REG32(EFUSE_AES_USR_KEY1_CRC, 0x50)
385
+REG32(EFUSE_PD, 0x54)
386
+REG32(EFUSE_ANLG_OSC_SW_1LP, 0x60)
387
+REG32(EFUSE_TEST_CTRL, 0x100)
388
+
389
+#define R_MAX (R_EFUSE_TEST_CTRL + 1)
390
+
391
+#define R_WR_LOCK_UNLOCK_PASSCODE (0xDF0D)
392
+
393
+/*
394
+ * eFuse layout references:
395
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilnvm/src/xnvm_efuse_hw.h
396
+ */
397
+#define BIT_POS_OF(A_) \
398
+ ((uint32_t)((A_) & (R_EFUSE_PGM_ADDR_ROW_MASK | \
399
+ R_EFUSE_PGM_ADDR_COLUMN_MASK)))
400
+
401
+#define BIT_POS(R_, C_) \
402
+ ((uint32_t)((R_EFUSE_PGM_ADDR_ROW_MASK \
403
+ & ((R_) << R_EFUSE_PGM_ADDR_ROW_SHIFT)) \
404
+ | \
405
+ (R_EFUSE_PGM_ADDR_COLUMN_MASK \
406
+ & ((C_) << R_EFUSE_PGM_ADDR_COLUMN_SHIFT))))
407
+
408
+#define EFUSE_TBIT_POS(A_) (BIT_POS_OF(A_) >= BIT_POS(0, 28))
409
+
410
+#define EFUSE_ANCHOR_ROW (0)
411
+#define EFUSE_ANCHOR_3_COL (27)
412
+#define EFUSE_ANCHOR_1_COL (1)
413
+
414
+#define EFUSE_AES_KEY_START BIT_POS(12, 0)
415
+#define EFUSE_AES_KEY_END BIT_POS(19, 31)
416
+#define EFUSE_USER_KEY_0_START BIT_POS(20, 0)
417
+#define EFUSE_USER_KEY_0_END BIT_POS(27, 31)
418
+#define EFUSE_USER_KEY_1_START BIT_POS(28, 0)
419
+#define EFUSE_USER_KEY_1_END BIT_POS(35, 31)
420
+
421
+#define EFUSE_RD_BLOCKED_START EFUSE_AES_KEY_START
422
+#define EFUSE_RD_BLOCKED_END EFUSE_USER_KEY_1_END
423
+
424
+#define EFUSE_GLITCH_DET_WR_LK BIT_POS(4, 31)
425
+#define EFUSE_PPK0_WR_LK BIT_POS(43, 6)
426
+#define EFUSE_PPK1_WR_LK BIT_POS(43, 7)
427
+#define EFUSE_PPK2_WR_LK BIT_POS(43, 8)
428
+#define EFUSE_AES_WR_LK BIT_POS(43, 11)
429
+#define EFUSE_USER_KEY_0_WR_LK BIT_POS(43, 13)
430
+#define EFUSE_USER_KEY_1_WR_LK BIT_POS(43, 15)
431
+#define EFUSE_PUF_SYN_LK BIT_POS(43, 16)
432
+#define EFUSE_DNA_WR_LK BIT_POS(43, 27)
433
+#define EFUSE_BOOT_ENV_WR_LK BIT_POS(43, 28)
434
+
435
+#define EFUSE_PGM_LOCKED_START BIT_POS(44, 0)
436
+#define EFUSE_PGM_LOCKED_END BIT_POS(51, 31)
437
+
438
+#define EFUSE_PUF_PAGE (2)
439
+#define EFUSE_PUF_SYN_START BIT_POS(129, 0)
440
+#define EFUSE_PUF_SYN_END BIT_POS(255, 27)
441
+
442
+#define EFUSE_KEY_CRC_LK_ROW (43)
443
+#define EFUSE_AES_KEY_CRC_LK_MASK ((1U << 9) | (1U << 10))
444
+#define EFUSE_USER_KEY_0_CRC_LK_MASK (1U << 12)
445
+#define EFUSE_USER_KEY_1_CRC_LK_MASK (1U << 14)
446
+
447
+/*
448
+ * A handy macro to return value of an array element,
449
+ * or a specific default if given index is out of bound.
450
+ */
451
+#define ARRAY_GET(A_, I_, D_) \
452
+ ((unsigned int)(I_) < ARRAY_SIZE(A_) ? (A_)[I_] : (D_))
453
+
454
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxVersalEFuseCtrl *)0)->regs));
455
+
456
+typedef struct XlnxEFuseLkSpec {
457
+ uint16_t row;
458
+ uint16_t lk_bit;
459
+} XlnxEFuseLkSpec;
460
+
461
+static void efuse_imr_update_irq(XlnxVersalEFuseCtrl *s)
462
+{
463
+ bool pending = s->regs[R_EFUSE_ISR] & ~s->regs[R_EFUSE_IMR];
464
+ qemu_set_irq(s->irq_efuse_imr, pending);
465
+}
466
+
467
+static void efuse_isr_postw(RegisterInfo *reg, uint64_t val64)
468
+{
469
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
470
+ efuse_imr_update_irq(s);
471
+}
472
+
473
+static uint64_t efuse_ier_prew(RegisterInfo *reg, uint64_t val64)
474
+{
475
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
476
+ uint32_t val = val64;
477
+
478
+ s->regs[R_EFUSE_IMR] &= ~val;
479
+ efuse_imr_update_irq(s);
480
+ return 0;
481
+}
482
+
483
+static uint64_t efuse_idr_prew(RegisterInfo *reg, uint64_t val64)
484
+{
485
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
486
+ uint32_t val = val64;
487
+
488
+ s->regs[R_EFUSE_IMR] |= val;
489
+ efuse_imr_update_irq(s);
490
+ return 0;
491
+}
492
+
493
+static void efuse_status_tbits_sync(XlnxVersalEFuseCtrl *s)
494
+{
495
+ uint32_t check = xlnx_efuse_tbits_check(s->efuse);
496
+ uint32_t val = s->regs[R_STATUS];
497
+
498
+ val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0)));
499
+ val = FIELD_DP32(val, STATUS, EFUSE_1_TBIT, !!(check & (1 << 1)));
500
+ val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 2)));
501
+
502
+ s->regs[R_STATUS] = val;
503
+}
504
+
505
+static void efuse_anchor_bits_check(XlnxVersalEFuseCtrl *s)
506
+{
507
+ unsigned page;
508
+
509
+ if (!s->efuse || !s->efuse->init_tbits) {
510
+ return;
511
+ }
512
+
513
+ for (page = 0; page < s->efuse->efuse_nr; page++) {
514
+ uint32_t row = 0, bit;
515
+
516
+ row = FIELD_DP32(row, EFUSE_PGM_ADDR, PAGE, page);
517
+ row = FIELD_DP32(row, EFUSE_PGM_ADDR, ROW, EFUSE_ANCHOR_ROW);
518
+
519
+ bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_3_COL);
520
+ if (!xlnx_efuse_get_bit(s->efuse, bit)) {
521
+ xlnx_efuse_set_bit(s->efuse, bit);
522
+ }
523
+
524
+ bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_1_COL);
525
+ if (!xlnx_efuse_get_bit(s->efuse, bit)) {
526
+ xlnx_efuse_set_bit(s->efuse, bit);
527
+ }
528
+ }
529
+}
530
+
531
+static void efuse_key_crc_check(RegisterInfo *reg, uint32_t crc,
532
+ uint32_t pass_mask, uint32_t done_mask,
533
+ unsigned first, uint32_t lk_mask)
534
+{
535
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
536
+ uint32_t r, lk_bits;
537
+
538
+ /*
539
+ * To start, assume both DONE and PASS, and clear PASS by xor
540
+ * if CRC-check fails or CRC-check disabled by lock fuse.
541
+ */
542
+ r = s->regs[R_STATUS] | done_mask | pass_mask;
543
+
544
+ lk_bits = xlnx_efuse_get_row(s->efuse, EFUSE_KEY_CRC_LK_ROW) & lk_mask;
545
+ if (lk_bits == 0 && xlnx_efuse_k256_check(s->efuse, crc, first)) {
546
+ pass_mask = 0;
547
+ }
548
+
549
+ s->regs[R_STATUS] = r ^ pass_mask;
550
+}
551
+
552
+static void efuse_data_sync(XlnxVersalEFuseCtrl *s)
553
+{
554
+ efuse_status_tbits_sync(s);
555
+}
556
+
557
+static int efuse_lk_spec_cmp(const void *a, const void *b)
558
+{
559
+ uint16_t r1 = ((const XlnxEFuseLkSpec *)a)->row;
560
+ uint16_t r2 = ((const XlnxEFuseLkSpec *)b)->row;
561
+
562
+ return (r1 > r2) - (r1 < r2);
563
+}
564
+
565
+static void efuse_lk_spec_sort(XlnxVersalEFuseCtrl *s)
566
+{
567
+ XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec;
568
+ const uint32_t n8 = s->extra_pg0_lock_n16 * 2;
569
+ const uint32_t sz = sizeof(ary[0]);
570
+ const uint32_t cnt = n8 / sz;
571
+
572
+ if (ary && cnt) {
573
+ qsort(ary, cnt, sz, efuse_lk_spec_cmp);
574
+ }
575
+}
576
+
577
+static uint32_t efuse_lk_spec_find(XlnxVersalEFuseCtrl *s, uint32_t row)
578
+{
579
+ const XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec;
580
+ const uint32_t n8 = s->extra_pg0_lock_n16 * 2;
581
+ const uint32_t sz = sizeof(ary[0]);
582
+ const uint32_t cnt = n8 / sz;
583
+ const XlnxEFuseLkSpec *item = NULL;
584
+
585
+ if (ary && cnt) {
586
+ XlnxEFuseLkSpec k = { .row = row, };
587
+
588
+ item = bsearch(&k, ary, cnt, sz, efuse_lk_spec_cmp);
589
+ }
590
+
591
+ return item ? item->lk_bit : 0;
592
+}
593
+
594
+static uint32_t efuse_bit_locked(XlnxVersalEFuseCtrl *s, uint32_t bit)
595
+{
596
+ /* Hard-coded locks */
597
+ static const uint16_t pg0_hard_lock[] = {
598
+ [4] = EFUSE_GLITCH_DET_WR_LK,
599
+ [37] = EFUSE_BOOT_ENV_WR_LK,
600
+
601
+ [8 ... 11] = EFUSE_DNA_WR_LK,
602
+ [12 ... 19] = EFUSE_AES_WR_LK,
603
+ [20 ... 27] = EFUSE_USER_KEY_0_WR_LK,
604
+ [28 ... 35] = EFUSE_USER_KEY_1_WR_LK,
605
+ [64 ... 71] = EFUSE_PPK0_WR_LK,
606
+ [72 ... 79] = EFUSE_PPK1_WR_LK,
607
+ [80 ... 87] = EFUSE_PPK2_WR_LK,
608
+ };
609
+
610
+ uint32_t row = FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW);
611
+ uint32_t lk_bit = ARRAY_GET(pg0_hard_lock, row, 0);
612
+
613
+ return lk_bit ? lk_bit : efuse_lk_spec_find(s, row);
614
+}
615
+
616
+static bool efuse_pgm_locked(XlnxVersalEFuseCtrl *s, unsigned int bit)
617
+{
618
+
619
+ unsigned int lock = 1;
620
+
621
+ /* Global lock */
622
+ if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) {
623
+ goto ret_lock;
624
+ }
625
+
626
+ /* Row lock */
627
+ switch (FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE)) {
628
+ case 0:
629
+ if (ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK) &&
630
+ bit >= EFUSE_PGM_LOCKED_START && bit <= EFUSE_PGM_LOCKED_END) {
631
+ goto ret_lock;
632
+ }
633
+
634
+ lock = efuse_bit_locked(s, bit);
635
+ break;
636
+ case EFUSE_PUF_PAGE:
637
+ if (bit < EFUSE_PUF_SYN_START || bit > EFUSE_PUF_SYN_END) {
638
+ lock = 0;
639
+ goto ret_lock;
640
+ }
641
+
642
+ lock = EFUSE_PUF_SYN_LK;
643
+ break;
644
+ default:
645
+ lock = 0;
646
+ goto ret_lock;
647
+ }
648
+
649
+ /* Row lock by an efuse bit */
650
+ if (lock) {
651
+ lock = xlnx_efuse_get_bit(s->efuse, lock);
652
+ }
653
+
654
+ ret_lock:
655
+ return lock != 0;
656
+}
657
+
658
+static void efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64)
659
+{
660
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
661
+ unsigned bit = val64;
662
+ bool ok = false;
663
+
664
+ /* Always zero out PGM_ADDR because it is write-only */
665
+ s->regs[R_EFUSE_PGM_ADDR] = 0;
666
+
667
+ /*
668
+ * Indicate error if bit is write-protected (or read-only
669
+ * as guarded by efuse_set_bit()).
670
+ *
671
+ * Keep it simple by not modeling program timing.
672
+ *
673
+ * Note: model must NEVER clear the PGM_ERROR bit; it is
674
+ * up to guest to do so (or by reset).
675
+ */
676
+ if (efuse_pgm_locked(s, bit)) {
677
+ qemu_log_mask(LOG_GUEST_ERROR,
678
+ "%s: Denied setting of efuse<%u, %u, %u>\n",
679
+ object_get_canonical_path(OBJECT(s)),
680
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE),
681
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW),
682
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, COLUMN));
683
+ } else if (xlnx_efuse_set_bit(s->efuse, bit)) {
684
+ ok = true;
685
+ if (EFUSE_TBIT_POS(bit)) {
686
+ efuse_status_tbits_sync(s);
687
+ }
688
+ }
689
+
690
+ if (!ok) {
691
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1);
692
+ }
693
+
694
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1);
695
+ efuse_imr_update_irq(s);
696
+}
697
+
698
+static void efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64)
699
+{
700
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
701
+ unsigned bit = val64;
702
+ bool denied;
703
+
704
+ /* Always zero out RD_ADDR because it is write-only */
705
+ s->regs[R_EFUSE_RD_ADDR] = 0;
706
+
707
+ /*
708
+ * Indicate error if row is read-blocked.
709
+ *
710
+ * Note: model must NEVER clear the RD_ERROR bit; it is
711
+ * up to guest to do so (or by reset).
712
+ */
713
+ s->regs[R_EFUSE_RD_DATA] = xlnx_versal_efuse_read_row(s->efuse,
714
+ bit, &denied);
715
+ if (denied) {
716
+ qemu_log_mask(LOG_GUEST_ERROR,
717
+ "%s: Denied reading of efuse<%u, %u>\n",
718
+ object_get_canonical_path(OBJECT(s)),
719
+ FIELD_EX32(bit, EFUSE_RD_ADDR, PAGE),
720
+ FIELD_EX32(bit, EFUSE_RD_ADDR, ROW));
721
+
722
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1);
723
+ }
724
+
725
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1);
726
+ efuse_imr_update_irq(s);
727
+ return;
728
+}
729
+
730
+static uint64_t efuse_cache_load_prew(RegisterInfo *reg, uint64_t val64)
731
+{
732
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
733
+
734
+ if (val64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) {
735
+ efuse_data_sync(s);
736
+
737
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
738
+ efuse_imr_update_irq(s);
739
+ }
740
+
741
+ return 0;
742
+}
743
+
744
+static uint64_t efuse_pgm_lock_prew(RegisterInfo *reg, uint64_t val64)
745
+{
746
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
747
+
748
+ /* Ignore all other bits */
749
+ val64 = FIELD_EX32(val64, EFUSE_PGM_LOCK, SPK_ID_LOCK);
750
+
751
+ /* Once the bit is written 1, only reset will clear it to 0 */
752
+ val64 |= ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK);
753
+
754
+ return val64;
755
+}
756
+
757
+static void efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
758
+{
759
+ efuse_key_crc_check(reg, val64,
760
+ R_STATUS_AES_CRC_PASS_MASK,
761
+ R_STATUS_AES_CRC_DONE_MASK,
762
+ EFUSE_AES_KEY_START,
763
+ EFUSE_AES_KEY_CRC_LK_MASK);
764
+}
765
+
766
+static void efuse_aes_u0_crc_postw(RegisterInfo *reg, uint64_t val64)
767
+{
768
+ efuse_key_crc_check(reg, val64,
769
+ R_STATUS_AES_USER_KEY_0_CRC_PASS_MASK,
770
+ R_STATUS_AES_USER_KEY_0_CRC_DONE_MASK,
771
+ EFUSE_USER_KEY_0_START,
772
+ EFUSE_USER_KEY_0_CRC_LK_MASK);
773
+}
774
+
775
+static void efuse_aes_u1_crc_postw(RegisterInfo *reg, uint64_t val64)
776
+{
777
+ efuse_key_crc_check(reg, val64,
778
+ R_STATUS_AES_USER_KEY_1_CRC_PASS_MASK,
779
+ R_STATUS_AES_USER_KEY_1_CRC_DONE_MASK,
780
+ EFUSE_USER_KEY_1_START,
781
+ EFUSE_USER_KEY_1_CRC_LK_MASK);
782
+}
783
+
784
+static uint64_t efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val)
785
+{
786
+ return val != R_WR_LOCK_UNLOCK_PASSCODE;
787
+}
788
+
789
+static const RegisterAccessInfo efuse_ctrl_regs_info[] = {
790
+ { .name = "WR_LOCK", .addr = A_WR_LOCK,
791
+ .reset = 0x1,
792
+ .pre_write = efuse_wr_lock_prew,
793
+ },{ .name = "CFG", .addr = A_CFG,
794
+ .rsvd = 0x9,
795
+ },{ .name = "STATUS", .addr = A_STATUS,
796
+ .rsvd = 0x8,
797
+ .ro = 0xfff,
798
+ },{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR,
799
+ .post_write = efuse_pgm_addr_postw,
800
+ },{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR,
801
+ .rsvd = 0x1f,
802
+ .post_write = efuse_rd_addr_postw,
803
+ },{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA,
804
+ .ro = 0xffffffff,
805
+ },{ .name = "TPGM", .addr = A_TPGM,
806
+ },{ .name = "TRD", .addr = A_TRD,
807
+ .reset = 0x19,
808
+ },{ .name = "TSU_H_PS", .addr = A_TSU_H_PS,
809
+ .reset = 0xff,
810
+ },{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS,
811
+ .reset = 0x11,
812
+ },{ .name = "TRDM", .addr = A_TRDM,
813
+ .reset = 0x3a,
814
+ },{ .name = "TSU_H_CS", .addr = A_TSU_H_CS,
815
+ .reset = 0x16,
816
+ },{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR,
817
+ .rsvd = 0x7fff8000,
818
+ .w1c = 0x80007fff,
819
+ .post_write = efuse_isr_postw,
820
+ },{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR,
821
+ .reset = 0x80007fff,
822
+ .rsvd = 0x7fff8000,
823
+ .ro = 0xffffffff,
824
+ },{ .name = "EFUSE_IER", .addr = A_EFUSE_IER,
825
+ .rsvd = 0x7fff8000,
826
+ .pre_write = efuse_ier_prew,
827
+ },{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR,
828
+ .rsvd = 0x7fff8000,
829
+ .pre_write = efuse_idr_prew,
830
+ },{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD,
831
+ .pre_write = efuse_cache_load_prew,
832
+ },{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK,
833
+ .pre_write = efuse_pgm_lock_prew,
834
+ },{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC,
835
+ .post_write = efuse_aes_crc_postw,
836
+ },{ .name = "EFUSE_AES_USR_KEY0_CRC", .addr = A_EFUSE_AES_USR_KEY0_CRC,
837
+ .post_write = efuse_aes_u0_crc_postw,
838
+ },{ .name = "EFUSE_AES_USR_KEY1_CRC", .addr = A_EFUSE_AES_USR_KEY1_CRC,
839
+ .post_write = efuse_aes_u1_crc_postw,
840
+ },{ .name = "EFUSE_PD", .addr = A_EFUSE_PD,
841
+ .ro = 0xfffffffe,
842
+ },{ .name = "EFUSE_ANLG_OSC_SW_1LP", .addr = A_EFUSE_ANLG_OSC_SW_1LP,
843
+ },{ .name = "EFUSE_TEST_CTRL", .addr = A_EFUSE_TEST_CTRL,
844
+ .reset = 0x8,
845
+ }
846
+};
847
+
848
+static void efuse_ctrl_reg_write(void *opaque, hwaddr addr,
849
+ uint64_t data, unsigned size)
850
+{
851
+ RegisterInfoArray *reg_array = opaque;
852
+ XlnxVersalEFuseCtrl *s;
853
+ Object *dev;
854
+
855
+ assert(reg_array != NULL);
856
+
857
+ dev = reg_array->mem.owner;
858
+ assert(dev);
859
+
860
+ s = XLNX_VERSAL_EFUSE_CTRL(dev);
861
+
862
+ if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {
863
+ qemu_log_mask(LOG_GUEST_ERROR,
864
+ "%s[reg_0x%02lx]: Attempt to write locked register.\n",
865
+ object_get_canonical_path(OBJECT(s)), (long)addr);
866
+ } else {
867
+ register_write_memory(opaque, addr, data, size);
868
+ }
869
+}
870
+
871
+static void efuse_ctrl_register_reset(RegisterInfo *reg)
872
+{
873
+ if (!reg->data || !reg->access) {
874
+ return;
875
+ }
876
+
877
+ /* Reset must not trigger some registers' writers */
878
+ switch (reg->access->addr) {
879
+ case A_EFUSE_AES_CRC:
880
+ case A_EFUSE_AES_USR_KEY0_CRC:
881
+ case A_EFUSE_AES_USR_KEY1_CRC:
882
+ *(uint32_t *)reg->data = reg->access->reset;
883
+ return;
884
+ }
885
+
886
+ register_reset(reg);
887
+}
888
+
889
+static void efuse_ctrl_reset(DeviceState *dev)
890
+{
891
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev);
892
+ unsigned int i;
893
+
894
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
895
+ efuse_ctrl_register_reset(&s->regs_info[i]);
896
+ }
897
+
898
+ efuse_anchor_bits_check(s);
899
+ efuse_data_sync(s);
900
+ efuse_imr_update_irq(s);
901
+}
902
+
903
+static const MemoryRegionOps efuse_ctrl_ops = {
904
+ .read = register_read_memory,
905
+ .write = efuse_ctrl_reg_write,
906
+ .endianness = DEVICE_LITTLE_ENDIAN,
907
+ .valid = {
908
+ .min_access_size = 4,
909
+ .max_access_size = 4,
910
+ },
911
+};
912
+
913
+static void efuse_ctrl_realize(DeviceState *dev, Error **errp)
914
+{
915
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev);
916
+ const uint32_t lks_sz = sizeof(XlnxEFuseLkSpec) / 2;
917
+
918
+ if (!s->efuse) {
919
+ error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE",
920
+ object_get_canonical_path(OBJECT(dev)));
921
+ return;
922
+ }
923
+
924
+ /* Sort property-defined pgm-locks for bsearch lookup */
925
+ if ((s->extra_pg0_lock_n16 % lks_sz) != 0) {
926
+ error_setg(errp,
927
+ "%s.pg0-lock: array property item-count not multiple of %u",
928
+ object_get_canonical_path(OBJECT(dev)), lks_sz);
929
+ return;
930
+ }
931
+
932
+ efuse_lk_spec_sort(s);
933
+}
934
+
935
+static void efuse_ctrl_init(Object *obj)
936
+{
937
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj);
938
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
939
+ RegisterInfoArray *reg_array;
940
+
941
+ reg_array =
942
+ register_init_block32(DEVICE(obj), efuse_ctrl_regs_info,
943
+ ARRAY_SIZE(efuse_ctrl_regs_info),
944
+ s->regs_info, s->regs,
945
+ &efuse_ctrl_ops,
946
+ XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG,
947
+ R_MAX * 4);
948
+
949
+ sysbus_init_mmio(sbd, &reg_array->mem);
950
+ sysbus_init_irq(sbd, &s->irq_efuse_imr);
951
+}
952
+
953
+static const VMStateDescription vmstate_efuse_ctrl = {
954
+ .name = TYPE_XLNX_VERSAL_EFUSE_CTRL,
955
+ .version_id = 1,
956
+ .minimum_version_id = 1,
957
+ .fields = (VMStateField[]) {
958
+ VMSTATE_UINT32_ARRAY(regs, XlnxVersalEFuseCtrl, R_MAX),
959
+ VMSTATE_END_OF_LIST(),
960
+ }
961
+};
962
+
963
+static Property efuse_ctrl_props[] = {
964
+ DEFINE_PROP_LINK("efuse",
965
+ XlnxVersalEFuseCtrl, efuse,
966
+ TYPE_XLNX_EFUSE, XlnxEFuse *),
967
+ DEFINE_PROP_ARRAY("pg0-lock",
968
+ XlnxVersalEFuseCtrl, extra_pg0_lock_n16,
969
+ extra_pg0_lock_spec, qdev_prop_uint16, uint16_t),
970
+
971
+ DEFINE_PROP_END_OF_LIST(),
972
+};
973
+
974
+static void efuse_ctrl_class_init(ObjectClass *klass, void *data)
975
+{
976
+ DeviceClass *dc = DEVICE_CLASS(klass);
977
+
978
+ dc->reset = efuse_ctrl_reset;
979
+ dc->realize = efuse_ctrl_realize;
980
+ dc->vmsd = &vmstate_efuse_ctrl;
981
+ device_class_set_props(dc, efuse_ctrl_props);
982
+}
983
+
984
+static const TypeInfo efuse_ctrl_info = {
985
+ .name = TYPE_XLNX_VERSAL_EFUSE_CTRL,
986
+ .parent = TYPE_SYS_BUS_DEVICE,
987
+ .instance_size = sizeof(XlnxVersalEFuseCtrl),
988
+ .class_init = efuse_ctrl_class_init,
989
+ .instance_init = efuse_ctrl_init,
990
+};
991
+
992
+static void efuse_ctrl_register_types(void)
993
+{
994
+ type_register_static(&efuse_ctrl_info);
995
+}
996
+
997
+type_init(efuse_ctrl_register_types)
998
+
999
+/*
1000
+ * Retrieve a row, with unreadable bits returned as 0.
1001
+ */
1002
+uint32_t xlnx_versal_efuse_read_row(XlnxEFuse *efuse,
1003
+ uint32_t bit, bool *denied)
1004
+{
1005
+ bool dummy;
1006
+
1007
+ if (!denied) {
1008
+ denied = &dummy;
1009
+ }
1010
+
1011
+ if (bit >= EFUSE_RD_BLOCKED_START && bit <= EFUSE_RD_BLOCKED_END) {
1012
+ *denied = true;
1013
+ return 0;
1014
+ }
1015
+
1016
+ *denied = false;
1017
+ return xlnx_efuse_get_row(efuse, bit);
1018
+}
1019
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
1020
index XXXXXXX..XXXXXXX 100644
594
index XXXXXXX..XXXXXXX 100644
1021
--- a/hw/nvram/Kconfig
595
--- a/tests/qtest/meson.build
1022
+++ b/hw/nvram/Kconfig
596
+++ b/tests/qtest/meson.build
1023
@@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE_CRC
597
@@ -XXX,XX +XXX,XX @@ qtests_aspeed = \
1024
config XLNX_EFUSE
598
qtests_stm32l4x5 = \
1025
bool
599
['stm32l4x5_exti-test',
1026
select XLNX_EFUSE_CRC
600
'stm32l4x5_syscfg-test',
1027
+
601
- 'stm32l4x5_rcc-test']
1028
+config XLNX_EFUSE_VERSAL
602
+ 'stm32l4x5_rcc-test',
1029
+ bool
603
+ 'stm32l4x5_gpio-test']
1030
+ select XLNX_EFUSE
604
1031
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
605
qtests_arm = \
1032
index XXXXXXX..XXXXXXX 100644
606
(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
1033
--- a/hw/nvram/meson.build
1034
+++ b/hw/nvram/meson.build
1035
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
1036
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
1037
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c'))
1038
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
1039
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
1040
+ 'xlnx-versal-efuse-cache.c',
1041
+ 'xlnx-versal-efuse-ctrl.c'))
1042
1043
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
1044
--
607
--
1045
2.20.1
608
2.34.1
1046
609
1047
610
diff view generated by jsdifflib
[PULL 09/22] hw/arm: xlnx-zcu102: Add Xilinx BBRAM device
[PULL 12/14] target/arm: Fix 32-bit SMOPA
1
From: Tong Ho <tong.ho@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM)
3
While the 8-bit input elements are sequential in the input vector,
4
4
the 32-bit output elements are not sequential in the output matrix.
5
The command argument:
5
Do not attempt to compute 2 32-bit outputs at the same time.
6
-drive if=pflash,index=2,...
6
7
Can be used to optionally connect the bbram to a backend
7
Cc: qemu-stable@nongnu.org
8
storage, such that field-programmed values in one
8
Fixes: 23a5e3859f5 ("target/arm: Implement SME integer outer product")
9
invocation can be made available to next invocation.
9
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2083
10
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
The backend storage must be a seekable binary file, and
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
its size must be 36 bytes or larger. A file with all
12
Message-id: 20240305163931.242795-1-richard.henderson@linaro.org
13
binary 0's is a 'blank'.
14
15
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
16
Message-id: 20210917052400.1249094-8-tong.ho@xilinx.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
14
---
20
include/hw/arm/xlnx-zynqmp.h | 2 ++
15
target/arm/tcg/sme_helper.c | 77 ++++++++++++++++++-------------
21
hw/arm/xlnx-zcu102.c | 15 +++++++++++++++
16
tests/tcg/aarch64/sme-smopa-1.c | 47 +++++++++++++++++++
22
hw/arm/xlnx-zynqmp.c | 20 ++++++++++++++++++++
17
tests/tcg/aarch64/sme-smopa-2.c | 54 ++++++++++++++++++++++
23
hw/Kconfig | 1 +
18
tests/tcg/aarch64/Makefile.target | 2 +-
24
4 files changed, 38 insertions(+)
19
4 files changed, 147 insertions(+), 33 deletions(-)
25
20
create mode 100644 tests/tcg/aarch64/sme-smopa-1.c
26
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
21
create mode 100644 tests/tcg/aarch64/sme-smopa-2.c
22
23
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
27
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/xlnx-zynqmp.h
25
--- a/target/arm/tcg/sme_helper.c
29
+++ b/include/hw/arm/xlnx-zynqmp.h
26
+++ b/target/arm/tcg/sme_helper.c
30
@@ -XXX,XX +XXX,XX @@
27
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
31
#include "qom/object.h"
32
#include "net/can_emu.h"
33
#include "hw/dma/xlnx_csu_dma.h"
34
+#include "hw/nvram/xlnx-bbram.h"
35
36
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
37
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
38
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
39
40
MemoryRegion *ddr_ram;
41
MemoryRegion ddr_ram_low, ddr_ram_high;
42
+ XlnxBBRam bbram;
43
44
MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
45
46
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/xlnx-zcu102.c
49
+++ b/hw/arm/xlnx-zcu102.c
50
@@ -XXX,XX +XXX,XX @@ static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt)
51
}
28
}
52
}
29
}
53
30
54
+static void bbram_attach_drive(XlnxBBRam *dev)
31
-typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool);
32
+typedef uint32_t IMOPFn32(uint32_t, uint32_t, uint32_t, uint8_t, bool);
33
+static inline void do_imopa_s(uint32_t *za, uint32_t *zn, uint32_t *zm,
34
+ uint8_t *pn, uint8_t *pm,
35
+ uint32_t desc, IMOPFn32 *fn)
55
+{
36
+{
56
+ DriveInfo *dinfo;
37
+ intptr_t row, col, oprsz = simd_oprsz(desc) / 4;
57
+ BlockBackend *blk;
38
+ bool neg = simd_data(desc);
58
+
39
59
+ dinfo = drive_get_by_index(IF_PFLASH, 2);
40
-static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm,
60
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
41
- uint8_t *pn, uint8_t *pm,
61
+ if (blk) {
42
- uint32_t desc, IMOPFn *fn)
62
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
43
+ for (row = 0; row < oprsz; ++row) {
44
+ uint8_t pa = (pn[H1(row >> 1)] >> ((row & 1) * 4)) & 0xf;
45
+ uint32_t *za_row = &za[tile_vslice_index(row)];
46
+ uint32_t n = zn[H4(row)];
47
+
48
+ for (col = 0; col < oprsz; ++col) {
49
+ uint8_t pb = pm[H1(col >> 1)] >> ((col & 1) * 4);
50
+ uint32_t *a = &za_row[H4(col)];
51
+
52
+ *a = fn(n, zm[H4(col)], *a, pa & pb, neg);
53
+ }
63
+ }
54
+ }
64
+}
55
+}
65
+
56
+
66
static void xlnx_zcu102_init(MachineState *machine)
57
+typedef uint64_t IMOPFn64(uint64_t, uint64_t, uint64_t, uint8_t, bool);
58
+static inline void do_imopa_d(uint64_t *za, uint64_t *zn, uint64_t *zm,
59
+ uint8_t *pn, uint8_t *pm,
60
+ uint32_t desc, IMOPFn64 *fn)
67
{
61
{
68
XlnxZCU102 *s = ZCU102_MACHINE(machine);
62
intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
69
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
63
bool neg = simd_data(desc);
70
64
@@ -XXX,XX +XXX,XX @@ static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm,
71
qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
65
}
72
66
73
+ /* Attach bbram backend, if given */
67
#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \
74
+ bbram_attach_drive(&s->soc.bbram);
68
-static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \
75
+
69
+static uint32_t NAME(uint32_t n, uint32_t m, uint32_t a, uint8_t p, bool neg) \
76
/* Create and plug in the SD cards */
70
{ \
77
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
71
- uint32_t sum0 = 0, sum1 = 0; \
78
BusState *bus;
72
+ uint32_t sum = 0; \
79
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
73
/* Apply P to N as a mask, making the inactive elements 0. */ \
74
n &= expand_pred_b(p); \
75
- sum0 += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
76
- sum0 += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \
77
- sum0 += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
78
- sum0 += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \
79
- sum1 += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \
80
- sum1 += (NTYPE)(n >> 40) * (MTYPE)(m >> 40); \
81
- sum1 += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \
82
- sum1 += (NTYPE)(n >> 56) * (MTYPE)(m >> 56); \
83
- if (neg) { \
84
- sum0 = (uint32_t)a - sum0, sum1 = (uint32_t)(a >> 32) - sum1; \
85
- } else { \
86
- sum0 = (uint32_t)a + sum0, sum1 = (uint32_t)(a >> 32) + sum1; \
87
- } \
88
- return ((uint64_t)sum1 << 32) | sum0; \
89
+ sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
90
+ sum += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \
91
+ sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
92
+ sum += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \
93
+ return neg ? a - sum : a + sum; \
94
}
95
96
#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \
97
@@ -XXX,XX +XXX,XX @@ DEF_IMOP_64(umopa_d, uint16_t, uint16_t)
98
DEF_IMOP_64(sumopa_d, int16_t, uint16_t)
99
DEF_IMOP_64(usmopa_d, uint16_t, int16_t)
100
101
-#define DEF_IMOPH(NAME) \
102
- void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, \
103
- void *vpm, uint32_t desc) \
104
- { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); }
105
+#define DEF_IMOPH(NAME, S) \
106
+ void HELPER(sme_##NAME##_##S)(void *vza, void *vzn, void *vzm, \
107
+ void *vpn, void *vpm, uint32_t desc) \
108
+ { do_imopa_##S(vza, vzn, vzm, vpn, vpm, desc, NAME##_##S); }
109
110
-DEF_IMOPH(smopa_s)
111
-DEF_IMOPH(umopa_s)
112
-DEF_IMOPH(sumopa_s)
113
-DEF_IMOPH(usmopa_s)
114
-DEF_IMOPH(smopa_d)
115
-DEF_IMOPH(umopa_d)
116
-DEF_IMOPH(sumopa_d)
117
-DEF_IMOPH(usmopa_d)
118
+DEF_IMOPH(smopa, s)
119
+DEF_IMOPH(umopa, s)
120
+DEF_IMOPH(sumopa, s)
121
+DEF_IMOPH(usmopa, s)
122
+
123
+DEF_IMOPH(smopa, d)
124
+DEF_IMOPH(umopa, d)
125
+DEF_IMOPH(sumopa, d)
126
+DEF_IMOPH(usmopa, d)
127
diff --git a/tests/tcg/aarch64/sme-smopa-1.c b/tests/tcg/aarch64/sme-smopa-1.c
128
new file mode 100644
129
index XXXXXXX..XXXXXXX
130
--- /dev/null
131
+++ b/tests/tcg/aarch64/sme-smopa-1.c
132
@@ -XXX,XX +XXX,XX @@
133
+#include <stdio.h>
134
+#include <string.h>
135
+
136
+int main()
137
+{
138
+ static const int cmp[4][4] = {
139
+ { 110, 134, 158, 182 },
140
+ { 390, 478, 566, 654 },
141
+ { 670, 822, 974, 1126 },
142
+ { 950, 1166, 1382, 1598 }
143
+ };
144
+ int dst[4][4];
145
+ int *tmp = &dst[0][0];
146
+
147
+ asm volatile(
148
+ ".arch armv8-r+sme\n\t"
149
+ "smstart\n\t"
150
+ "index z0.b, #0, #1\n\t"
151
+ "movprfx z1, z0\n\t"
152
+ "add z1.b, z1.b, #16\n\t"
153
+ "ptrue p0.b\n\t"
154
+ "smopa za0.s, p0/m, p0/m, z0.b, z1.b\n\t"
155
+ "ptrue p0.s, vl4\n\t"
156
+ "mov w12, #0\n\t"
157
+ "st1w { za0h.s[w12, #0] }, p0, [%0]\n\t"
158
+ "add %0, %0, #16\n\t"
159
+ "st1w { za0h.s[w12, #1] }, p0, [%0]\n\t"
160
+ "add %0, %0, #16\n\t"
161
+ "st1w { za0h.s[w12, #2] }, p0, [%0]\n\t"
162
+ "add %0, %0, #16\n\t"
163
+ "st1w { za0h.s[w12, #3] }, p0, [%0]\n\t"
164
+ "smstop"
165
+ : "+r"(tmp) : : "memory");
166
+
167
+ if (memcmp(cmp, dst, sizeof(dst)) == 0) {
168
+ return 0;
169
+ }
170
+
171
+ /* See above for correct results. */
172
+ for (int i = 0; i < 4; ++i) {
173
+ for (int j = 0; j < 4; ++j) {
174
+ printf("%6d", dst[i][j]);
175
+ }
176
+ printf("\n");
177
+ }
178
+ return 1;
179
+}
180
diff --git a/tests/tcg/aarch64/sme-smopa-2.c b/tests/tcg/aarch64/sme-smopa-2.c
181
new file mode 100644
182
index XXXXXXX..XXXXXXX
183
--- /dev/null
184
+++ b/tests/tcg/aarch64/sme-smopa-2.c
185
@@ -XXX,XX +XXX,XX @@
186
+#include <stdio.h>
187
+#include <string.h>
188
+
189
+int main()
190
+{
191
+ static const long cmp[4][4] = {
192
+ { 110, 134, 158, 182 },
193
+ { 390, 478, 566, 654 },
194
+ { 670, 822, 974, 1126 },
195
+ { 950, 1166, 1382, 1598 }
196
+ };
197
+ long dst[4][4];
198
+ long *tmp = &dst[0][0];
199
+ long svl;
200
+
201
+ /* Validate that we have a wide enough vector for 4 elements. */
202
+ asm(".arch armv8-r+sme-i64\n\trdsvl %0, #1" : "=r"(svl));
203
+ if (svl < 32) {
204
+ return 0;
205
+ }
206
+
207
+ asm volatile(
208
+ "smstart\n\t"
209
+ "index z0.h, #0, #1\n\t"
210
+ "movprfx z1, z0\n\t"
211
+ "add z1.h, z1.h, #16\n\t"
212
+ "ptrue p0.b\n\t"
213
+ "smopa za0.d, p0/m, p0/m, z0.h, z1.h\n\t"
214
+ "ptrue p0.d, vl4\n\t"
215
+ "mov w12, #0\n\t"
216
+ "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
217
+ "add %0, %0, #32\n\t"
218
+ "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
219
+ "mov w12, #2\n\t"
220
+ "add %0, %0, #32\n\t"
221
+ "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
222
+ "add %0, %0, #32\n\t"
223
+ "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
224
+ "smstop"
225
+ : "+r"(tmp) : : "memory");
226
+
227
+ if (memcmp(cmp, dst, sizeof(dst)) == 0) {
228
+ return 0;
229
+ }
230
+
231
+ /* See above for correct results. */
232
+ for (int i = 0; i < 4; ++i) {
233
+ for (int j = 0; j < 4; ++j) {
234
+ printf("%6ld", dst[i][j]);
235
+ }
236
+ printf("\n");
237
+ }
238
+ return 1;
239
+}
240
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
80
index XXXXXXX..XXXXXXX 100644
241
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/arm/xlnx-zynqmp.c
242
--- a/tests/tcg/aarch64/Makefile.target
82
+++ b/hw/arm/xlnx-zynqmp.c
243
+++ b/tests/tcg/aarch64/Makefile.target
83
@@ -XXX,XX +XXX,XX @@
244
@@ -XXX,XX +XXX,XX @@ endif
84
#define RTC_ADDR 0xffa60000
245
85
#define RTC_IRQ 26
246
# SME Tests
86
247
ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
87
+#define BBRAM_ADDR 0xffcd0000
248
-AARCH64_TESTS += sme-outprod1
88
+#define BBRAM_IRQ 11
249
+AARCH64_TESTS += sme-outprod1 sme-smopa-1 sme-smopa-2
89
+
250
endif
90
#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
251
91
252
# System Registers Tests
92
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
93
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
94
qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
95
}
96
97
+static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
98
+{
99
+ SysBusDevice *sbd;
100
+
101
+ object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram,
102
+ sizeof(s->bbram), TYPE_XLNX_BBRAM,
103
+ &error_fatal,
104
+ "crc-zpads", "1",
105
+ NULL);
106
+ sbd = SYS_BUS_DEVICE(&s->bbram);
107
+
108
+ sysbus_realize(sbd, &error_fatal);
109
+ sysbus_mmio_map(sbd, 0, BBRAM_ADDR);
110
+ sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
111
+}
112
+
113
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
114
{
115
static const struct UnimpInfo {
116
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
117
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
118
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
119
120
+ xlnx_zynqmp_create_bbram(s, gic_spi);
121
xlnx_zynqmp_create_unimp_mmio(s);
122
123
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
124
diff --git a/hw/Kconfig b/hw/Kconfig
125
index XXXXXXX..XXXXXXX 100644
126
--- a/hw/Kconfig
127
+++ b/hw/Kconfig
128
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP
129
select REGISTER
130
select CAN_BUS
131
select PTIMER
132
+ select XLNX_BBRAM
133
--
253
--
134
2.20.1
254
2.34.1
135
255
136
256
diff view generated by jsdifflib
[PULL 22/22] hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19
[PULL 13/14] hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
1
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
1
The sun4v RTC device model added under commit a0e893039cf2ce0 in 2016
2
was unfortunately added with a license of GPL-v3-or-later, which is
3
not compatible with other QEMU code which has a GPL-v2-only license.
2
4
3
The Linux spi-imx driver does not work on QEMU. The reason is that the
5
Relicense the code in the .c and the .h file to GPL-v2-or-later,
4
state of m25p80 loops in STATE_READING_DATA state after receiving
6
to make it compatible with the rest of QEMU.
5
RDSR command, the new command is ignored. Before sending a new command,
6
CS line should be pulled high to make the state of m25p80 back to IDLE.
7
7
8
Currently the SPI flash CS line is connected to the SPI controller, but
8
Cc: qemu-stable@nongnu.org
9
on the real board, it's connected to GPIO3_19. This matches the ecspi1
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
device node in the board dts.
10
Signed-off-by: Paolo Bonzini (for Red Hat) <pbonzini@redhat.com>
11
11
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
12
ecspi1 node in imx6qdl-sabrelite.dtsi:
12
Signed-off-by: Markus Armbruster <armbru@redhat.com>
13
&ecspi1 {
13
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
14
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
pinctrl-names = "default";
15
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
16
pinctrl-0 = <&pinctrl_ecspi1>;
16
Acked-by: Alex Bennée <alex.bennee@linaro.org>
17
status = "okay";
17
Message-id: 20240223161300.938542-1-peter.maydell@linaro.org
18
19
flash: m25p80@0 {
20
compatible = "sst,sst25vf016b", "jedec,spi-nor";
21
spi-max-frequency = <20000000>;
22
reg = <0>;
23
};
24
};
25
26
Should connect the SSI_GPIO_CS to GPIO3_19 when adding a spi-nor to
27
spi1 on sabrelite machine.
28
29
Verified this patch on Linux v5.14.
30
31
Logs:
32
# echo "01234567899876543210" > test
33
# mtd_debug erase /dev/mtd0 0x0 0x1000
34
Erased 4096 bytes from address 0x00000000 in flash
35
# mtd_debug write /dev/mtdblock0 0x0 20 test
36
Copied 20 bytes from test to address 0x00000000 in flash
37
# mtd_debug read /dev/mtdblock0 0x0 20 test_out
38
Copied 20 bytes from address 0x00000000 in flash to test_out
39
# cat test_out
40
01234567899876543210#
41
42
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
43
Reported-by: Guenter Roeck <linux@roeck-us.net>
44
Reviewed-by: Bin Meng <bin.meng@windriver.com>
45
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
46
Message-id: 20210927142825.491-1-xchengl.cn@gmail.com
47
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
---
19
---
49
hw/arm/sabrelite.c | 2 +-
20
include/hw/rtc/sun4v-rtc.h | 2 +-
50
1 file changed, 1 insertion(+), 1 deletion(-)
21
hw/rtc/sun4v-rtc.c | 2 +-
22
2 files changed, 2 insertions(+), 2 deletions(-)
51
23
52
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
24
diff --git a/include/hw/rtc/sun4v-rtc.h b/include/hw/rtc/sun4v-rtc.h
53
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/arm/sabrelite.c
26
--- a/include/hw/rtc/sun4v-rtc.h
55
+++ b/hw/arm/sabrelite.c
27
+++ b/include/hw/rtc/sun4v-rtc.h
56
@@ -XXX,XX +XXX,XX @@ static void sabrelite_init(MachineState *machine)
28
@@ -XXX,XX +XXX,XX @@
57
qdev_realize_and_unref(flash_dev, BUS(spi_bus), &error_fatal);
29
*
58
30
* Copyright (c) 2016 Artyom Tarasenko
59
cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
31
*
60
- sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line);
32
- * This code is licensed under the GNU GPL v3 or (at your option) any later
61
+ qdev_connect_gpio_out(DEVICE(&s->gpio[2]), 19, cs_line);
33
+ * This code is licensed under the GNU GPL v2 or (at your option) any later
62
}
34
* version.
63
}
35
*/
64
}
36
37
diff --git a/hw/rtc/sun4v-rtc.c b/hw/rtc/sun4v-rtc.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/rtc/sun4v-rtc.c
40
+++ b/hw/rtc/sun4v-rtc.c
41
@@ -XXX,XX +XXX,XX @@
42
*
43
* Copyright (c) 2016 Artyom Tarasenko
44
*
45
- * This code is licensed under the GNU GPL v3 or (at your option) any later
46
+ * This code is licensed under the GNU GPL v2 or (at your option) any later
47
* version.
48
*/
49
65
--
50
--
66
2.20.1
51
2.34.1
67
52
68
53
diff view generated by jsdifflib
[PULL 03/22] hw/nvram: Introduce Xilinx eFuse QOM
[PULL 14/14] target/arm: Move v7m-related code from cpu32.c into a separate file
1
From: Tong Ho <tong.ho@xilinx.com>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
This introduces the QOM for Xilinx eFuse, an one-time
3
Move the code to a separate file so that we do not have to compile
4
field-programmable storage bit array.
4
it anymore if CONFIG_ARM_V7M is not set.
5
5
6
The actual mmio interface to the array varies by device
6
Signed-off-by: Thomas Huth <thuth@redhat.com>
7
families and will be provided in different change-sets.
7
Message-id: 20240308141051.536599-2-thuth@redhat.com
8
9
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
11
12
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
13
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
14
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
15
Message-id: 20210917052400.1249094-2-tong.ho@xilinx.com
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
10
---
19
include/hw/nvram/xlnx-efuse.h | 132 ++++++++++++++++
11
target/arm/tcg/cpu-v7m.c | 290 +++++++++++++++++++++++++++++++++++++
20
hw/nvram/xlnx-efuse-crc.c | 119 +++++++++++++++
12
target/arm/tcg/cpu32.c | 261 ---------------------------------
21
hw/nvram/xlnx-efuse.c | 280 ++++++++++++++++++++++++++++++++++
13
target/arm/meson.build | 3 +
22
hw/nvram/Kconfig | 7 +
14
target/arm/tcg/meson.build | 3 +
23
hw/nvram/meson.build | 2 +
15
4 files changed, 296 insertions(+), 261 deletions(-)
24
5 files changed, 540 insertions(+)
16
create mode 100644 target/arm/tcg/cpu-v7m.c
25
create mode 100644 include/hw/nvram/xlnx-efuse.h
26
create mode 100644 hw/nvram/xlnx-efuse-crc.c
27
create mode 100644 hw/nvram/xlnx-efuse.c
28
17
29
diff --git a/include/hw/nvram/xlnx-efuse.h b/include/hw/nvram/xlnx-efuse.h
18
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
30
new file mode 100644
19
new file mode 100644
31
index XXXXXXX..XXXXXXX
20
index XXXXXXX..XXXXXXX
32
--- /dev/null
21
--- /dev/null
33
+++ b/include/hw/nvram/xlnx-efuse.h
22
+++ b/target/arm/tcg/cpu-v7m.c
34
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@
35
+/*
24
+/*
36
+ * QEMU model of the Xilinx eFuse core
25
+ * QEMU ARMv7-M TCG-only CPUs.
37
+ *
26
+ *
38
+ * Copyright (c) 2015 Xilinx Inc.
27
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
39
+ *
28
+ *
40
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
29
+ * This code is licensed under the GNU GPL v2 or later.
41
+ *
30
+ *
42
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
31
+ * SPDX-License-Identifier: GPL-2.0-or-later
43
+ * of this software and associated documentation files (the "Software"), to deal
44
+ * in the Software without restriction, including without limitation the rights
45
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
46
+ * copies of the Software, and to permit persons to whom the Software is
47
+ * furnished to do so, subject to the following conditions:
48
+ *
49
+ * The above copyright notice and this permission notice shall be included in
50
+ * all copies or substantial portions of the Software.
51
+ *
52
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
53
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
54
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
55
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
56
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
57
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
58
+ * THE SOFTWARE.
59
+ */
32
+ */
60
+
33
+
61
+#ifndef XLNX_EFUSE_H
34
+#include "qemu/osdep.h"
62
+#define XLNX_EFUSE_H
35
+#include "cpu.h"
63
+
36
+#include "hw/core/tcg-cpu-ops.h"
64
+#include "sysemu/block-backend.h"
37
+#include "internals.h"
65
+#include "hw/qdev-core.h"
38
+
66
+
39
+#if !defined(CONFIG_USER_ONLY)
67
+#define TYPE_XLNX_EFUSE "xlnx,efuse"
40
+
68
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxEFuse, XLNX_EFUSE);
41
+#include "hw/intc/armv7m_nvic.h"
69
+
42
+
70
+struct XlnxEFuse {
43
+static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
71
+ DeviceState parent_obj;
44
+{
72
+ BlockBackend *blk;
45
+ CPUClass *cc = CPU_GET_CLASS(cs);
73
+ bool blk_ro;
46
+ ARMCPU *cpu = ARM_CPU(cs);
74
+ uint32_t *fuse32;
47
+ CPUARMState *env = &cpu->env;
75
+
48
+ bool ret = false;
76
+ DeviceState *dev;
49
+
77
+
50
+ /*
78
+ bool init_tbits;
51
+ * ARMv7-M interrupt masking works differently than -A or -R.
79
+
52
+ * There is no FIQ/IRQ distinction. Instead of I and F bits
80
+ uint8_t efuse_nr;
53
+ * masking FIQ and IRQ interrupts, an exception is taken only
81
+ uint32_t efuse_size;
54
+ * if it is higher priority than the current execution priority
82
+
55
+ * (which depends on state like BASEPRI, FAULTMASK and the
83
+ uint32_t *ro_bits;
56
+ * currently active exception).
84
+ uint32_t ro_bits_cnt;
57
+ */
58
+ if (interrupt_request & CPU_INTERRUPT_HARD
59
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
60
+ cs->exception_index = EXCP_IRQ;
61
+ cc->tcg_ops->do_interrupt(cs);
62
+ ret = true;
63
+ }
64
+ return ret;
65
+}
66
+
67
+#endif /* !CONFIG_USER_ONLY */
68
+
69
+static void cortex_m0_initfn(Object *obj)
70
+{
71
+ ARMCPU *cpu = ARM_CPU(obj);
72
+ set_feature(&cpu->env, ARM_FEATURE_V6);
73
+ set_feature(&cpu->env, ARM_FEATURE_M);
74
+
75
+ cpu->midr = 0x410cc200;
76
+
77
+ /*
78
+ * These ID register values are not guest visible, because
79
+ * we do not implement the Main Extension. They must be set
80
+ * to values corresponding to the Cortex-M0's implemented
81
+ * features, because QEMU generally controls its emulation
82
+ * by looking at ID register fields. We use the same values as
83
+ * for the M3.
84
+ */
85
+ cpu->isar.id_pfr0 = 0x00000030;
86
+ cpu->isar.id_pfr1 = 0x00000200;
87
+ cpu->isar.id_dfr0 = 0x00100000;
88
+ cpu->id_afr0 = 0x00000000;
89
+ cpu->isar.id_mmfr0 = 0x00000030;
90
+ cpu->isar.id_mmfr1 = 0x00000000;
91
+ cpu->isar.id_mmfr2 = 0x00000000;
92
+ cpu->isar.id_mmfr3 = 0x00000000;
93
+ cpu->isar.id_isar0 = 0x01141110;
94
+ cpu->isar.id_isar1 = 0x02111000;
95
+ cpu->isar.id_isar2 = 0x21112231;
96
+ cpu->isar.id_isar3 = 0x01111110;
97
+ cpu->isar.id_isar4 = 0x01310102;
98
+ cpu->isar.id_isar5 = 0x00000000;
99
+ cpu->isar.id_isar6 = 0x00000000;
100
+}
101
+
102
+static void cortex_m3_initfn(Object *obj)
103
+{
104
+ ARMCPU *cpu = ARM_CPU(obj);
105
+ set_feature(&cpu->env, ARM_FEATURE_V7);
106
+ set_feature(&cpu->env, ARM_FEATURE_M);
107
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
108
+ cpu->midr = 0x410fc231;
109
+ cpu->pmsav7_dregion = 8;
110
+ cpu->isar.id_pfr0 = 0x00000030;
111
+ cpu->isar.id_pfr1 = 0x00000200;
112
+ cpu->isar.id_dfr0 = 0x00100000;
113
+ cpu->id_afr0 = 0x00000000;
114
+ cpu->isar.id_mmfr0 = 0x00000030;
115
+ cpu->isar.id_mmfr1 = 0x00000000;
116
+ cpu->isar.id_mmfr2 = 0x00000000;
117
+ cpu->isar.id_mmfr3 = 0x00000000;
118
+ cpu->isar.id_isar0 = 0x01141110;
119
+ cpu->isar.id_isar1 = 0x02111000;
120
+ cpu->isar.id_isar2 = 0x21112231;
121
+ cpu->isar.id_isar3 = 0x01111110;
122
+ cpu->isar.id_isar4 = 0x01310102;
123
+ cpu->isar.id_isar5 = 0x00000000;
124
+ cpu->isar.id_isar6 = 0x00000000;
125
+}
126
+
127
+static void cortex_m4_initfn(Object *obj)
128
+{
129
+ ARMCPU *cpu = ARM_CPU(obj);
130
+
131
+ set_feature(&cpu->env, ARM_FEATURE_V7);
132
+ set_feature(&cpu->env, ARM_FEATURE_M);
133
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
134
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
135
+ cpu->midr = 0x410fc240; /* r0p0 */
136
+ cpu->pmsav7_dregion = 8;
137
+ cpu->isar.mvfr0 = 0x10110021;
138
+ cpu->isar.mvfr1 = 0x11000011;
139
+ cpu->isar.mvfr2 = 0x00000000;
140
+ cpu->isar.id_pfr0 = 0x00000030;
141
+ cpu->isar.id_pfr1 = 0x00000200;
142
+ cpu->isar.id_dfr0 = 0x00100000;
143
+ cpu->id_afr0 = 0x00000000;
144
+ cpu->isar.id_mmfr0 = 0x00000030;
145
+ cpu->isar.id_mmfr1 = 0x00000000;
146
+ cpu->isar.id_mmfr2 = 0x00000000;
147
+ cpu->isar.id_mmfr3 = 0x00000000;
148
+ cpu->isar.id_isar0 = 0x01141110;
149
+ cpu->isar.id_isar1 = 0x02111000;
150
+ cpu->isar.id_isar2 = 0x21112231;
151
+ cpu->isar.id_isar3 = 0x01111110;
152
+ cpu->isar.id_isar4 = 0x01310102;
153
+ cpu->isar.id_isar5 = 0x00000000;
154
+ cpu->isar.id_isar6 = 0x00000000;
155
+}
156
+
157
+static void cortex_m7_initfn(Object *obj)
158
+{
159
+ ARMCPU *cpu = ARM_CPU(obj);
160
+
161
+ set_feature(&cpu->env, ARM_FEATURE_V7);
162
+ set_feature(&cpu->env, ARM_FEATURE_M);
163
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
164
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
165
+ cpu->midr = 0x411fc272; /* r1p2 */
166
+ cpu->pmsav7_dregion = 8;
167
+ cpu->isar.mvfr0 = 0x10110221;
168
+ cpu->isar.mvfr1 = 0x12000011;
169
+ cpu->isar.mvfr2 = 0x00000040;
170
+ cpu->isar.id_pfr0 = 0x00000030;
171
+ cpu->isar.id_pfr1 = 0x00000200;
172
+ cpu->isar.id_dfr0 = 0x00100000;
173
+ cpu->id_afr0 = 0x00000000;
174
+ cpu->isar.id_mmfr0 = 0x00100030;
175
+ cpu->isar.id_mmfr1 = 0x00000000;
176
+ cpu->isar.id_mmfr2 = 0x01000000;
177
+ cpu->isar.id_mmfr3 = 0x00000000;
178
+ cpu->isar.id_isar0 = 0x01101110;
179
+ cpu->isar.id_isar1 = 0x02112000;
180
+ cpu->isar.id_isar2 = 0x20232231;
181
+ cpu->isar.id_isar3 = 0x01111131;
182
+ cpu->isar.id_isar4 = 0x01310132;
183
+ cpu->isar.id_isar5 = 0x00000000;
184
+ cpu->isar.id_isar6 = 0x00000000;
185
+}
186
+
187
+static void cortex_m33_initfn(Object *obj)
188
+{
189
+ ARMCPU *cpu = ARM_CPU(obj);
190
+
191
+ set_feature(&cpu->env, ARM_FEATURE_V8);
192
+ set_feature(&cpu->env, ARM_FEATURE_M);
193
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
194
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
195
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
196
+ cpu->midr = 0x410fd213; /* r0p3 */
197
+ cpu->pmsav7_dregion = 16;
198
+ cpu->sau_sregion = 8;
199
+ cpu->isar.mvfr0 = 0x10110021;
200
+ cpu->isar.mvfr1 = 0x11000011;
201
+ cpu->isar.mvfr2 = 0x00000040;
202
+ cpu->isar.id_pfr0 = 0x00000030;
203
+ cpu->isar.id_pfr1 = 0x00000210;
204
+ cpu->isar.id_dfr0 = 0x00200000;
205
+ cpu->id_afr0 = 0x00000000;
206
+ cpu->isar.id_mmfr0 = 0x00101F40;
207
+ cpu->isar.id_mmfr1 = 0x00000000;
208
+ cpu->isar.id_mmfr2 = 0x01000000;
209
+ cpu->isar.id_mmfr3 = 0x00000000;
210
+ cpu->isar.id_isar0 = 0x01101110;
211
+ cpu->isar.id_isar1 = 0x02212000;
212
+ cpu->isar.id_isar2 = 0x20232232;
213
+ cpu->isar.id_isar3 = 0x01111131;
214
+ cpu->isar.id_isar4 = 0x01310132;
215
+ cpu->isar.id_isar5 = 0x00000000;
216
+ cpu->isar.id_isar6 = 0x00000000;
217
+ cpu->clidr = 0x00000000;
218
+ cpu->ctr = 0x8000c000;
219
+}
220
+
221
+static void cortex_m55_initfn(Object *obj)
222
+{
223
+ ARMCPU *cpu = ARM_CPU(obj);
224
+
225
+ set_feature(&cpu->env, ARM_FEATURE_V8);
226
+ set_feature(&cpu->env, ARM_FEATURE_V8_1M);
227
+ set_feature(&cpu->env, ARM_FEATURE_M);
228
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
229
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
230
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
231
+ cpu->midr = 0x410fd221; /* r0p1 */
232
+ cpu->revidr = 0;
233
+ cpu->pmsav7_dregion = 16;
234
+ cpu->sau_sregion = 8;
235
+ /* These are the MVFR* values for the FPU + full MVE configuration */
236
+ cpu->isar.mvfr0 = 0x10110221;
237
+ cpu->isar.mvfr1 = 0x12100211;
238
+ cpu->isar.mvfr2 = 0x00000040;
239
+ cpu->isar.id_pfr0 = 0x20000030;
240
+ cpu->isar.id_pfr1 = 0x00000230;
241
+ cpu->isar.id_dfr0 = 0x10200000;
242
+ cpu->id_afr0 = 0x00000000;
243
+ cpu->isar.id_mmfr0 = 0x00111040;
244
+ cpu->isar.id_mmfr1 = 0x00000000;
245
+ cpu->isar.id_mmfr2 = 0x01000000;
246
+ cpu->isar.id_mmfr3 = 0x00000011;
247
+ cpu->isar.id_isar0 = 0x01103110;
248
+ cpu->isar.id_isar1 = 0x02212000;
249
+ cpu->isar.id_isar2 = 0x20232232;
250
+ cpu->isar.id_isar3 = 0x01111131;
251
+ cpu->isar.id_isar4 = 0x01310132;
252
+ cpu->isar.id_isar5 = 0x00000000;
253
+ cpu->isar.id_isar6 = 0x00000000;
254
+ cpu->clidr = 0x00000000; /* caches not implemented */
255
+ cpu->ctr = 0x8303c003;
256
+}
257
+
258
+static const TCGCPUOps arm_v7m_tcg_ops = {
259
+ .initialize = arm_translate_init,
260
+ .synchronize_from_tb = arm_cpu_synchronize_from_tb,
261
+ .debug_excp_handler = arm_debug_excp_handler,
262
+ .restore_state_to_opc = arm_restore_state_to_opc,
263
+
264
+#ifdef CONFIG_USER_ONLY
265
+ .record_sigsegv = arm_cpu_record_sigsegv,
266
+ .record_sigbus = arm_cpu_record_sigbus,
267
+#else
268
+ .tlb_fill = arm_cpu_tlb_fill,
269
+ .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
270
+ .do_interrupt = arm_v7m_cpu_do_interrupt,
271
+ .do_transaction_failed = arm_cpu_do_transaction_failed,
272
+ .do_unaligned_access = arm_cpu_do_unaligned_access,
273
+ .adjust_watchpoint_address = arm_adjust_watchpoint_address,
274
+ .debug_check_watchpoint = arm_debug_check_watchpoint,
275
+ .debug_check_breakpoint = arm_debug_check_breakpoint,
276
+#endif /* !CONFIG_USER_ONLY */
85
+};
277
+};
86
+
278
+
87
+/**
279
+static void arm_v7m_class_init(ObjectClass *oc, void *data)
88
+ * xlnx_efuse_calc_crc:
280
+{
89
+ * @data: an array of 32-bit words for which the CRC should be computed
281
+ ARMCPUClass *acc = ARM_CPU_CLASS(oc);
90
+ * @u32_cnt: the array size in number of 32-bit words
282
+ CPUClass *cc = CPU_CLASS(oc);
91
+ * @zpads: the number of 32-bit zeros prepended to @data before computation
283
+
92
+ *
284
+ acc->info = data;
93
+ * This function is used to compute the CRC for an array of 32-bit words,
285
+ cc->tcg_ops = &arm_v7m_tcg_ops;
94
+ * using a Xilinx-specific data padding.
286
+ cc->gdb_core_xml_file = "arm-m-profile.xml";
95
+ *
287
+}
96
+ * Returns: the computed 32-bit CRC
288
+
97
+ */
289
+static const ARMCPUInfo arm_v7m_cpus[] = {
98
+uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt,
290
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
99
+ unsigned zpads);
291
+ .class_init = arm_v7m_class_init },
100
+
292
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn,
101
+/**
293
+ .class_init = arm_v7m_class_init },
102
+ * xlnx_efuse_get_bit:
294
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
103
+ * @s: the efuse object
295
+ .class_init = arm_v7m_class_init },
104
+ * @bit: the efuse bit-address to read the data
296
+ { .name = "cortex-m7", .initfn = cortex_m7_initfn,
105
+ *
297
+ .class_init = arm_v7m_class_init },
106
+ * Returns: the bit, 0 or 1, at @bit of object @s
298
+ { .name = "cortex-m33", .initfn = cortex_m33_initfn,
107
+ */
299
+ .class_init = arm_v7m_class_init },
108
+bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit);
300
+ { .name = "cortex-m55", .initfn = cortex_m55_initfn,
109
+
301
+ .class_init = arm_v7m_class_init },
110
+/**
302
+};
111
+ * xlnx_efuse_set_bit:
303
+
112
+ * @s: the efuse object
304
+static void arm_v7m_cpu_register_types(void)
113
+ * @bit: the efuse bit-address to be written a value of 1
305
+{
114
+ *
306
+ size_t i;
115
+ * Returns: true on success, false on failure
307
+
116
+ */
308
+ for (i = 0; i < ARRAY_SIZE(arm_v7m_cpus); ++i) {
117
+bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit);
309
+ arm_cpu_register(&arm_v7m_cpus[i]);
118
+
119
+/**
120
+ * xlnx_efuse_k256_check:
121
+ * @s: the efuse object
122
+ * @crc: the 32-bit CRC to be compared with
123
+ * @start: the efuse bit-address (which must be multiple of 32) of the
124
+ * start of a 256-bit array
125
+ *
126
+ * This function computes the CRC of a 256-bit array starting at @start
127
+ * then compares to the given @crc
128
+ *
129
+ * Returns: true of @crc == computed, false otherwise
130
+ */
131
+bool xlnx_efuse_k256_check(XlnxEFuse *s, uint32_t crc, unsigned start);
132
+
133
+/**
134
+ * xlnx_efuse_tbits_check:
135
+ * @s: the efuse object
136
+ *
137
+ * This function inspects a number of efuse bits at specific addresses
138
+ * to see if they match a validation pattern. Each pattern is a group
139
+ * of 4 bits, and there are 3 groups.
140
+ *
141
+ * Returns: a 3-bit mask, where a bit of '1' means the corresponding
142
+ * group has a valid pattern.
143
+ */
144
+uint32_t xlnx_efuse_tbits_check(XlnxEFuse *s);
145
+
146
+/**
147
+ * xlnx_efuse_get_row:
148
+ * @s: the efuse object
149
+ * @bit: the efuse bit address for which a 32-bit value is read
150
+ *
151
+ * Returns: the entire 32 bits of the efuse, starting at a bit
152
+ * address that is multiple of 32 and contains the bit at @bit
153
+ */
154
+static inline uint32_t xlnx_efuse_get_row(XlnxEFuse *s, unsigned int bit)
155
+{
156
+ if (!(s->fuse32)) {
157
+ return 0;
158
+ } else {
159
+ unsigned int row_idx = bit / 32;
160
+
161
+ assert(row_idx < (s->efuse_size * s->efuse_nr / 32));
162
+ return s->fuse32[row_idx];
163
+ }
310
+ }
164
+}
311
+}
165
+
312
+
166
+#endif
313
+type_init(arm_v7m_cpu_register_types)
167
diff --git a/hw/nvram/xlnx-efuse-crc.c b/hw/nvram/xlnx-efuse-crc.c
314
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
168
new file mode 100644
315
index XXXXXXX..XXXXXXX 100644
169
index XXXXXXX..XXXXXXX
316
--- a/target/arm/tcg/cpu32.c
170
--- /dev/null
317
+++ b/target/arm/tcg/cpu32.c
171
+++ b/hw/nvram/xlnx-efuse-crc.c
172
@@ -XXX,XX +XXX,XX @@
318
@@ -XXX,XX +XXX,XX @@
173
+/*
319
#include "hw/boards.h"
174
+ * Xilinx eFuse/bbram CRC calculator
320
#endif
175
+ *
321
#include "cpregs.h"
176
+ * Copyright (c) 2021 Xilinx Inc.
322
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
177
+ *
323
-#include "hw/intc/armv7m_nvic.h"
178
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
324
-#endif
179
+ * of this software and associated documentation files (the "Software"), to deal
325
180
+ * in the Software without restriction, including without limitation the rights
326
181
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
327
/* Share AArch32 -cpu max features with AArch64. */
182
+ * copies of the Software, and to permit persons to whom the Software is
328
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
183
+ * furnished to do so, subject to the following conditions:
329
/* CPU models. These are not needed for the AArch64 linux-user build. */
184
+ *
330
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
185
+ * The above copyright notice and this permission notice shall be included in
331
186
+ * all copies or substantial portions of the Software.
332
-#if !defined(CONFIG_USER_ONLY)
187
+ *
333
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
188
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
334
-{
189
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
335
- CPUClass *cc = CPU_GET_CLASS(cs);
190
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
336
- ARMCPU *cpu = ARM_CPU(cs);
191
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
337
- CPUARMState *env = &cpu->env;
192
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
338
- bool ret = false;
193
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
339
-
194
+ * THE SOFTWARE.
340
- /*
195
+ */
341
- * ARMv7-M interrupt masking works differently than -A or -R.
196
+#include "qemu/osdep.h"
342
- * There is no FIQ/IRQ distinction. Instead of I and F bits
197
+#include "hw/nvram/xlnx-efuse.h"
343
- * masking FIQ and IRQ interrupts, an exception is taken only
198
+
344
- * if it is higher priority than the current execution priority
199
+static uint32_t xlnx_efuse_u37_crc(uint32_t prev_crc, uint32_t data,
345
- * (which depends on state like BASEPRI, FAULTMASK and the
200
+ uint32_t addr)
346
- * currently active exception).
201
+{
347
- */
202
+ /* A table for 7-bit slicing */
348
- if (interrupt_request & CPU_INTERRUPT_HARD
203
+ static const uint32_t crc_tab[128] = {
349
- && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
204
+ 0x00000000, 0xe13b70f7, 0xc79a971f, 0x26a1e7e8,
350
- cs->exception_index = EXCP_IRQ;
205
+ 0x8ad958cf, 0x6be22838, 0x4d43cfd0, 0xac78bf27,
351
- cc->tcg_ops->do_interrupt(cs);
206
+ 0x105ec76f, 0xf165b798, 0xd7c45070, 0x36ff2087,
352
- ret = true;
207
+ 0x9a879fa0, 0x7bbcef57, 0x5d1d08bf, 0xbc267848,
353
- }
208
+ 0x20bd8ede, 0xc186fe29, 0xe72719c1, 0x061c6936,
354
- return ret;
209
+ 0xaa64d611, 0x4b5fa6e6, 0x6dfe410e, 0x8cc531f9,
355
-}
210
+ 0x30e349b1, 0xd1d83946, 0xf779deae, 0x1642ae59,
356
-#endif /* !CONFIG_USER_ONLY */
211
+ 0xba3a117e, 0x5b016189, 0x7da08661, 0x9c9bf696,
357
-
212
+ 0x417b1dbc, 0xa0406d4b, 0x86e18aa3, 0x67dafa54,
358
static void arm926_initfn(Object *obj)
213
+ 0xcba24573, 0x2a993584, 0x0c38d26c, 0xed03a29b,
359
{
214
+ 0x5125dad3, 0xb01eaa24, 0x96bf4dcc, 0x77843d3b,
360
ARMCPU *cpu = ARM_CPU(obj);
215
+ 0xdbfc821c, 0x3ac7f2eb, 0x1c661503, 0xfd5d65f4,
361
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
216
+ 0x61c69362, 0x80fde395, 0xa65c047d, 0x4767748a,
362
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
217
+ 0xeb1fcbad, 0x0a24bb5a, 0x2c855cb2, 0xcdbe2c45,
363
}
218
+ 0x7198540d, 0x90a324fa, 0xb602c312, 0x5739b3e5,
364
219
+ 0xfb410cc2, 0x1a7a7c35, 0x3cdb9bdd, 0xdde0eb2a,
365
-static void cortex_m0_initfn(Object *obj)
220
+ 0x82f63b78, 0x63cd4b8f, 0x456cac67, 0xa457dc90,
366
-{
221
+ 0x082f63b7, 0xe9141340, 0xcfb5f4a8, 0x2e8e845f,
367
- ARMCPU *cpu = ARM_CPU(obj);
222
+ 0x92a8fc17, 0x73938ce0, 0x55326b08, 0xb4091bff,
368
- set_feature(&cpu->env, ARM_FEATURE_V6);
223
+ 0x1871a4d8, 0xf94ad42f, 0xdfeb33c7, 0x3ed04330,
369
- set_feature(&cpu->env, ARM_FEATURE_M);
224
+ 0xa24bb5a6, 0x4370c551, 0x65d122b9, 0x84ea524e,
370
-
225
+ 0x2892ed69, 0xc9a99d9e, 0xef087a76, 0x0e330a81,
371
- cpu->midr = 0x410cc200;
226
+ 0xb21572c9, 0x532e023e, 0x758fe5d6, 0x94b49521,
372
-
227
+ 0x38cc2a06, 0xd9f75af1, 0xff56bd19, 0x1e6dcdee,
373
- /*
228
+ 0xc38d26c4, 0x22b65633, 0x0417b1db, 0xe52cc12c,
374
- * These ID register values are not guest visible, because
229
+ 0x49547e0b, 0xa86f0efc, 0x8ecee914, 0x6ff599e3,
375
- * we do not implement the Main Extension. They must be set
230
+ 0xd3d3e1ab, 0x32e8915c, 0x144976b4, 0xf5720643,
376
- * to values corresponding to the Cortex-M0's implemented
231
+ 0x590ab964, 0xb831c993, 0x9e902e7b, 0x7fab5e8c,
377
- * features, because QEMU generally controls its emulation
232
+ 0xe330a81a, 0x020bd8ed, 0x24aa3f05, 0xc5914ff2,
378
- * by looking at ID register fields. We use the same values as
233
+ 0x69e9f0d5, 0x88d28022, 0xae7367ca, 0x4f48173d,
379
- * for the M3.
234
+ 0xf36e6f75, 0x12551f82, 0x34f4f86a, 0xd5cf889d,
380
- */
235
+ 0x79b737ba, 0x988c474d, 0xbe2da0a5, 0x5f16d052
381
- cpu->isar.id_pfr0 = 0x00000030;
236
+ };
382
- cpu->isar.id_pfr1 = 0x00000200;
237
+
383
- cpu->isar.id_dfr0 = 0x00100000;
238
+ /*
384
- cpu->id_afr0 = 0x00000000;
239
+ * eFuse calculation is shown here:
385
- cpu->isar.id_mmfr0 = 0x00000030;
240
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1496
386
- cpu->isar.id_mmfr1 = 0x00000000;
241
+ *
387
- cpu->isar.id_mmfr2 = 0x00000000;
242
+ * Each u32 word is appended a 5-bit value, for a total of 37 bits; see:
388
- cpu->isar.id_mmfr3 = 0x00000000;
243
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1356
389
- cpu->isar.id_isar0 = 0x01141110;
244
+ */
390
- cpu->isar.id_isar1 = 0x02111000;
245
+ uint32_t crc = prev_crc;
391
- cpu->isar.id_isar2 = 0x21112231;
246
+ const unsigned rshf = 7;
392
- cpu->isar.id_isar3 = 0x01111110;
247
+ const uint32_t im = (1 << rshf) - 1;
393
- cpu->isar.id_isar4 = 0x01310102;
248
+ const uint32_t rm = (1 << (32 - rshf)) - 1;
394
- cpu->isar.id_isar5 = 0x00000000;
249
+ const uint32_t i2 = (1 << 2) - 1;
395
- cpu->isar.id_isar6 = 0x00000000;
250
+ const uint32_t r2 = (1 << 30) - 1;
396
-}
251
+
397
-
252
+ unsigned j;
398
-static void cortex_m3_initfn(Object *obj)
253
+ uint32_t i, r;
399
-{
254
+ uint64_t w;
400
- ARMCPU *cpu = ARM_CPU(obj);
255
+
401
- set_feature(&cpu->env, ARM_FEATURE_V7);
256
+ w = (uint64_t)(addr) << 32;
402
- set_feature(&cpu->env, ARM_FEATURE_M);
257
+ w |= data;
403
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
258
+
404
- cpu->midr = 0x410fc231;
259
+ /* Feed 35 bits, in 5 rounds, each a slice of 7 bits */
405
- cpu->pmsav7_dregion = 8;
260
+ for (j = 0; j < 5; j++) {
406
- cpu->isar.id_pfr0 = 0x00000030;
261
+ r = rm & (crc >> rshf);
407
- cpu->isar.id_pfr1 = 0x00000200;
262
+ i = im & (crc ^ w);
408
- cpu->isar.id_dfr0 = 0x00100000;
263
+ crc = crc_tab[i] ^ r;
409
- cpu->id_afr0 = 0x00000000;
264
+
410
- cpu->isar.id_mmfr0 = 0x00000030;
265
+ w >>= rshf;
411
- cpu->isar.id_mmfr1 = 0x00000000;
266
+ }
412
- cpu->isar.id_mmfr2 = 0x00000000;
267
+
413
- cpu->isar.id_mmfr3 = 0x00000000;
268
+ /* Feed the remaining 2 bits */
414
- cpu->isar.id_isar0 = 0x01141110;
269
+ r = r2 & (crc >> 2);
415
- cpu->isar.id_isar1 = 0x02111000;
270
+ i = i2 & (crc ^ w);
416
- cpu->isar.id_isar2 = 0x21112231;
271
+ crc = crc_tab[i << (rshf - 2)] ^ r;
417
- cpu->isar.id_isar3 = 0x01111110;
272
+
418
- cpu->isar.id_isar4 = 0x01310102;
273
+ return crc;
419
- cpu->isar.id_isar5 = 0x00000000;
274
+}
420
- cpu->isar.id_isar6 = 0x00000000;
275
+
421
-}
276
+uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt,
422
-
277
+ unsigned zpads)
423
-static void cortex_m4_initfn(Object *obj)
278
+{
424
-{
279
+ uint32_t crc = 0;
425
- ARMCPU *cpu = ARM_CPU(obj);
280
+ unsigned index;
426
-
281
+
427
- set_feature(&cpu->env, ARM_FEATURE_V7);
282
+ for (index = zpads; index; index--) {
428
- set_feature(&cpu->env, ARM_FEATURE_M);
283
+ crc = xlnx_efuse_u37_crc(crc, 0, (index + u32_cnt));
429
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
284
+ }
430
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
285
+
431
- cpu->midr = 0x410fc240; /* r0p0 */
286
+ for (index = u32_cnt; index; index--) {
432
- cpu->pmsav7_dregion = 8;
287
+ crc = xlnx_efuse_u37_crc(crc, data[index - 1], index);
433
- cpu->isar.mvfr0 = 0x10110021;
288
+ }
434
- cpu->isar.mvfr1 = 0x11000011;
289
+
435
- cpu->isar.mvfr2 = 0x00000000;
290
+ return crc;
436
- cpu->isar.id_pfr0 = 0x00000030;
291
+}
437
- cpu->isar.id_pfr1 = 0x00000200;
292
diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
438
- cpu->isar.id_dfr0 = 0x00100000;
293
new file mode 100644
439
- cpu->id_afr0 = 0x00000000;
294
index XXXXXXX..XXXXXXX
440
- cpu->isar.id_mmfr0 = 0x00000030;
295
--- /dev/null
441
- cpu->isar.id_mmfr1 = 0x00000000;
296
+++ b/hw/nvram/xlnx-efuse.c
442
- cpu->isar.id_mmfr2 = 0x00000000;
297
@@ -XXX,XX +XXX,XX @@
443
- cpu->isar.id_mmfr3 = 0x00000000;
298
+/*
444
- cpu->isar.id_isar0 = 0x01141110;
299
+ * QEMU model of the EFUSE eFuse
445
- cpu->isar.id_isar1 = 0x02111000;
300
+ *
446
- cpu->isar.id_isar2 = 0x21112231;
301
+ * Copyright (c) 2015 Xilinx Inc.
447
- cpu->isar.id_isar3 = 0x01111110;
302
+ *
448
- cpu->isar.id_isar4 = 0x01310102;
303
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
449
- cpu->isar.id_isar5 = 0x00000000;
304
+ *
450
- cpu->isar.id_isar6 = 0x00000000;
305
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
451
-}
306
+ * of this software and associated documentation files (the "Software"), to deal
452
-
307
+ * in the Software without restriction, including without limitation the rights
453
-static void cortex_m7_initfn(Object *obj)
308
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
454
-{
309
+ * copies of the Software, and to permit persons to whom the Software is
455
- ARMCPU *cpu = ARM_CPU(obj);
310
+ * furnished to do so, subject to the following conditions:
456
-
311
+ *
457
- set_feature(&cpu->env, ARM_FEATURE_V7);
312
+ * The above copyright notice and this permission notice shall be included in
458
- set_feature(&cpu->env, ARM_FEATURE_M);
313
+ * all copies or substantial portions of the Software.
459
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
314
+ *
460
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
315
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
461
- cpu->midr = 0x411fc272; /* r1p2 */
316
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
462
- cpu->pmsav7_dregion = 8;
317
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
463
- cpu->isar.mvfr0 = 0x10110221;
318
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
464
- cpu->isar.mvfr1 = 0x12000011;
319
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
465
- cpu->isar.mvfr2 = 0x00000040;
320
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
466
- cpu->isar.id_pfr0 = 0x00000030;
321
+ * THE SOFTWARE.
467
- cpu->isar.id_pfr1 = 0x00000200;
322
+ */
468
- cpu->isar.id_dfr0 = 0x00100000;
323
+
469
- cpu->id_afr0 = 0x00000000;
324
+#include "qemu/osdep.h"
470
- cpu->isar.id_mmfr0 = 0x00100030;
325
+#include "hw/nvram/xlnx-efuse.h"
471
- cpu->isar.id_mmfr1 = 0x00000000;
326
+
472
- cpu->isar.id_mmfr2 = 0x01000000;
327
+#include "qemu/error-report.h"
473
- cpu->isar.id_mmfr3 = 0x00000000;
328
+#include "qemu/log.h"
474
- cpu->isar.id_isar0 = 0x01101110;
329
+#include "qapi/error.h"
475
- cpu->isar.id_isar1 = 0x02112000;
330
+#include "sysemu/blockdev.h"
476
- cpu->isar.id_isar2 = 0x20232231;
331
+#include "hw/qdev-properties.h"
477
- cpu->isar.id_isar3 = 0x01111131;
332
+#include "hw/qdev-properties-system.h"
478
- cpu->isar.id_isar4 = 0x01310132;
333
+
479
- cpu->isar.id_isar5 = 0x00000000;
334
+#define TBIT0_OFFSET 28
480
- cpu->isar.id_isar6 = 0x00000000;
335
+#define TBIT1_OFFSET 29
481
-}
336
+#define TBIT2_OFFSET 30
482
-
337
+#define TBIT3_OFFSET 31
483
-static void cortex_m33_initfn(Object *obj)
338
+#define TBITS_PATTERN (0x0AU << TBIT0_OFFSET)
484
-{
339
+#define TBITS_MASK (0x0FU << TBIT0_OFFSET)
485
- ARMCPU *cpu = ARM_CPU(obj);
340
+
486
-
341
+bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit)
487
- set_feature(&cpu->env, ARM_FEATURE_V8);
342
+{
488
- set_feature(&cpu->env, ARM_FEATURE_M);
343
+ bool b = s->fuse32[bit / 32] & (1 << (bit % 32));
489
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
344
+ return b;
490
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
345
+}
491
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
346
+
492
- cpu->midr = 0x410fd213; /* r0p3 */
347
+static int efuse_bytes(XlnxEFuse *s)
493
- cpu->pmsav7_dregion = 16;
348
+{
494
- cpu->sau_sregion = 8;
349
+ return ROUND_UP((s->efuse_nr * s->efuse_size) / 8, 4);
495
- cpu->isar.mvfr0 = 0x10110021;
350
+}
496
- cpu->isar.mvfr1 = 0x11000011;
351
+
497
- cpu->isar.mvfr2 = 0x00000040;
352
+static int efuse_bdrv_read(XlnxEFuse *s, Error **errp)
498
- cpu->isar.id_pfr0 = 0x00000030;
353
+{
499
- cpu->isar.id_pfr1 = 0x00000210;
354
+ uint32_t *ram = s->fuse32;
500
- cpu->isar.id_dfr0 = 0x00200000;
355
+ int nr = efuse_bytes(s);
501
- cpu->id_afr0 = 0x00000000;
356
+
502
- cpu->isar.id_mmfr0 = 0x00101F40;
357
+ if (!s->blk) {
503
- cpu->isar.id_mmfr1 = 0x00000000;
358
+ return 0;
504
- cpu->isar.id_mmfr2 = 0x01000000;
359
+ }
505
- cpu->isar.id_mmfr3 = 0x00000000;
360
+
506
- cpu->isar.id_isar0 = 0x01101110;
361
+ s->blk_ro = !blk_supports_write_perm(s->blk);
507
- cpu->isar.id_isar1 = 0x02212000;
362
+ if (!s->blk_ro) {
508
- cpu->isar.id_isar2 = 0x20232232;
363
+ int rc;
509
- cpu->isar.id_isar3 = 0x01111131;
364
+
510
- cpu->isar.id_isar4 = 0x01310132;
365
+ rc = blk_set_perm(s->blk,
511
- cpu->isar.id_isar5 = 0x00000000;
366
+ (BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE),
512
- cpu->isar.id_isar6 = 0x00000000;
367
+ BLK_PERM_ALL, NULL);
513
- cpu->clidr = 0x00000000;
368
+ if (rc) {
514
- cpu->ctr = 0x8000c000;
369
+ s->blk_ro = true;
515
-}
370
+ }
516
-
371
+ }
517
-static void cortex_m55_initfn(Object *obj)
372
+ if (s->blk_ro) {
518
-{
373
+ warn_report("%s: Skip saving updates to read-only eFUSE backstore.",
519
- ARMCPU *cpu = ARM_CPU(obj);
374
+ blk_name(s->blk));
520
-
375
+ }
521
- set_feature(&cpu->env, ARM_FEATURE_V8);
376
+
522
- set_feature(&cpu->env, ARM_FEATURE_V8_1M);
377
+ if (blk_pread(s->blk, 0, ram, nr) < 0) {
523
- set_feature(&cpu->env, ARM_FEATURE_M);
378
+ error_setg(errp, "%s: Failed to read %u bytes from eFUSE backstore.",
524
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
379
+ blk_name(s->blk), nr);
525
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
380
+ return -1;
526
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
381
+ }
527
- cpu->midr = 0x410fd221; /* r0p1 */
382
+
528
- cpu->revidr = 0;
383
+ /* Convert from little-endian backstore for each 32-bit row */
529
- cpu->pmsav7_dregion = 16;
384
+ nr /= 4;
530
- cpu->sau_sregion = 8;
385
+ while (nr--) {
531
- /* These are the MVFR* values for the FPU + full MVE configuration */
386
+ ram[nr] = le32_to_cpu(ram[nr]);
532
- cpu->isar.mvfr0 = 0x10110221;
387
+ }
533
- cpu->isar.mvfr1 = 0x12100211;
388
+
534
- cpu->isar.mvfr2 = 0x00000040;
389
+ return 0;
535
- cpu->isar.id_pfr0 = 0x20000030;
390
+}
536
- cpu->isar.id_pfr1 = 0x00000230;
391
+
537
- cpu->isar.id_dfr0 = 0x10200000;
392
+static void efuse_bdrv_sync(XlnxEFuse *s, unsigned int bit)
538
- cpu->id_afr0 = 0x00000000;
393
+{
539
- cpu->isar.id_mmfr0 = 0x00111040;
394
+ unsigned int row_offset;
540
- cpu->isar.id_mmfr1 = 0x00000000;
395
+ uint32_t le32;
541
- cpu->isar.id_mmfr2 = 0x01000000;
396
+
542
- cpu->isar.id_mmfr3 = 0x00000011;
397
+ if (!s->blk || s->blk_ro) {
543
- cpu->isar.id_isar0 = 0x01103110;
398
+ return; /* Silent on read-only backend to avoid message flood */
544
- cpu->isar.id_isar1 = 0x02212000;
399
+ }
545
- cpu->isar.id_isar2 = 0x20232232;
400
+
546
- cpu->isar.id_isar3 = 0x01111131;
401
+ /* Backstore is always in little-endian */
547
- cpu->isar.id_isar4 = 0x01310132;
402
+ le32 = cpu_to_le32(xlnx_efuse_get_row(s, bit));
548
- cpu->isar.id_isar5 = 0x00000000;
403
+
549
- cpu->isar.id_isar6 = 0x00000000;
404
+ row_offset = (bit / 32) * 4;
550
- cpu->clidr = 0x00000000; /* caches not implemented */
405
+ if (blk_pwrite(s->blk, row_offset, &le32, 4, 0) < 0) {
551
- cpu->ctr = 0x8303c003;
406
+ error_report("%s: Failed to write offset %u of eFUSE backstore.",
552
-}
407
+ blk_name(s->blk), row_offset);
553
-
408
+ }
554
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
409
+}
555
/* Dummy the TCM region regs for the moment */
410
+
556
{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
411
+static int efuse_ro_bits_cmp(const void *a, const void *b)
557
@@ -XXX,XX +XXX,XX @@ static void pxa270c5_initfn(Object *obj)
412
+{
558
cpu->reset_sctlr = 0x00000078;
413
+ uint32_t i = *(const uint32_t *)a;
559
}
414
+ uint32_t j = *(const uint32_t *)b;
560
415
+
561
-static const TCGCPUOps arm_v7m_tcg_ops = {
416
+ return (i > j) - (i < j);
562
- .initialize = arm_translate_init,
417
+}
563
- .synchronize_from_tb = arm_cpu_synchronize_from_tb,
418
+
564
- .debug_excp_handler = arm_debug_excp_handler,
419
+static void efuse_ro_bits_sort(XlnxEFuse *s)
565
- .restore_state_to_opc = arm_restore_state_to_opc,
420
+{
566
-
421
+ uint32_t *ary = s->ro_bits;
567
-#ifdef CONFIG_USER_ONLY
422
+ const uint32_t cnt = s->ro_bits_cnt;
568
- .record_sigsegv = arm_cpu_record_sigsegv,
423
+
569
- .record_sigbus = arm_cpu_record_sigbus,
424
+ if (ary && cnt > 1) {
570
-#else
425
+ qsort(ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp);
571
- .tlb_fill = arm_cpu_tlb_fill,
426
+ }
572
- .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
427
+}
573
- .do_interrupt = arm_v7m_cpu_do_interrupt,
428
+
574
- .do_transaction_failed = arm_cpu_do_transaction_failed,
429
+static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k)
575
- .do_unaligned_access = arm_cpu_do_unaligned_access,
430
+{
576
- .adjust_watchpoint_address = arm_adjust_watchpoint_address,
431
+ const uint32_t *ary = s->ro_bits;
577
- .debug_check_watchpoint = arm_debug_check_watchpoint,
432
+ const uint32_t cnt = s->ro_bits_cnt;
578
- .debug_check_breakpoint = arm_debug_check_breakpoint,
433
+
579
-#endif /* !CONFIG_USER_ONLY */
434
+ if (!ary || !cnt) {
580
-};
435
+ return false;
581
-
436
+ }
582
-static void arm_v7m_class_init(ObjectClass *oc, void *data)
437
+
583
-{
438
+ return bsearch(&k, ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp) != NULL;
584
- ARMCPUClass *acc = ARM_CPU_CLASS(oc);
439
+}
585
- CPUClass *cc = CPU_CLASS(oc);
440
+
586
-
441
+bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
587
- acc->info = data;
442
+{
588
- cc->tcg_ops = &arm_v7m_tcg_ops;
443
+ if (efuse_ro_bits_find(s, bit)) {
589
- cc->gdb_core_xml_file = "arm-m-profile.xml";
444
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: WARN: "
590
-}
445
+ "Ignored setting of readonly efuse bit<%u,%u>!\n",
591
-
446
+ object_get_canonical_path(OBJECT(s)),
592
#ifndef TARGET_AARCH64
447
+ (bit / 32), (bit % 32));
593
/*
448
+ return false;
594
* -cpu max: a CPU with as many features enabled as our emulation supports.
449
+ }
595
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {
450
+
596
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
451
+ s->fuse32[bit / 32] |= 1 << (bit % 32);
597
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
452
+ efuse_bdrv_sync(s, bit);
598
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
453
+ return true;
599
- { .name = "cortex-m0", .initfn = cortex_m0_initfn,
454
+}
600
- .class_init = arm_v7m_class_init },
455
+
601
- { .name = "cortex-m3", .initfn = cortex_m3_initfn,
456
+bool xlnx_efuse_k256_check(XlnxEFuse *s, uint32_t crc, unsigned start)
602
- .class_init = arm_v7m_class_init },
457
+{
603
- { .name = "cortex-m4", .initfn = cortex_m4_initfn,
458
+ uint32_t calc;
604
- .class_init = arm_v7m_class_init },
459
+
605
- { .name = "cortex-m7", .initfn = cortex_m7_initfn,
460
+ /* A key always occupies multiple of whole rows */
606
- .class_init = arm_v7m_class_init },
461
+ assert((start % 32) == 0);
607
- { .name = "cortex-m33", .initfn = cortex_m33_initfn,
462
+
608
- .class_init = arm_v7m_class_init },
463
+ calc = xlnx_efuse_calc_crc(&s->fuse32[start / 32], (256 / 32), 0);
609
- { .name = "cortex-m55", .initfn = cortex_m55_initfn,
464
+ return calc == crc;
610
- .class_init = arm_v7m_class_init },
465
+}
611
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
466
+
612
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
467
+uint32_t xlnx_efuse_tbits_check(XlnxEFuse *s)
613
{ .name = "cortex-r52", .initfn = cortex_r52_initfn },
468
+{
614
diff --git a/target/arm/meson.build b/target/arm/meson.build
469
+ int nr;
470
+ uint32_t check = 0;
471
+
472
+ for (nr = s->efuse_nr; nr-- > 0; ) {
473
+ int efuse_start_row_num = (s->efuse_size * nr) / 32;
474
+ uint32_t data = s->fuse32[efuse_start_row_num];
475
+
476
+ /*
477
+ * If the option is on, auto-init blank T-bits.
478
+ * (non-blank will still be reported as '0' in the check, e.g.,
479
+ * for error-injection tests)
480
+ */
481
+ if ((data & TBITS_MASK) == 0 && s->init_tbits) {
482
+ data |= TBITS_PATTERN;
483
+
484
+ s->fuse32[efuse_start_row_num] = data;
485
+ efuse_bdrv_sync(s, (efuse_start_row_num * 32 + TBIT0_OFFSET));
486
+ }
487
+
488
+ check = (check << 1) | ((data & TBITS_MASK) == TBITS_PATTERN);
489
+ }
490
+
491
+ return check;
492
+}
493
+
494
+static void efuse_realize(DeviceState *dev, Error **errp)
495
+{
496
+ XlnxEFuse *s = XLNX_EFUSE(dev);
497
+
498
+ /* Sort readonly-list for bsearch lookup */
499
+ efuse_ro_bits_sort(s);
500
+
501
+ if ((s->efuse_size % 32) != 0) {
502
+ error_setg(errp,
503
+ "%s.efuse-size: %u: property value not multiple of 32.",
504
+ object_get_canonical_path(OBJECT(dev)), s->efuse_size);
505
+ return;
506
+ }
507
+
508
+ s->fuse32 = g_malloc0(efuse_bytes(s));
509
+ if (efuse_bdrv_read(s, errp)) {
510
+ g_free(s->fuse32);
511
+ }
512
+}
513
+
514
+static void efuse_prop_set_drive(Object *obj, Visitor *v, const char *name,
515
+ void *opaque, Error **errp)
516
+{
517
+ DeviceState *dev = DEVICE(obj);
518
+
519
+ qdev_prop_drive.set(obj, v, name, opaque, errp);
520
+
521
+ /* Fill initial data if backend is attached after realized */
522
+ if (dev->realized) {
523
+ efuse_bdrv_read(XLNX_EFUSE(obj), errp);
524
+ }
525
+}
526
+
527
+static void efuse_prop_get_drive(Object *obj, Visitor *v, const char *name,
528
+ void *opaque, Error **errp)
529
+{
530
+ qdev_prop_drive.get(obj, v, name, opaque, errp);
531
+}
532
+
533
+static void efuse_prop_release_drive(Object *obj, const char *name,
534
+ void *opaque)
535
+{
536
+ qdev_prop_drive.release(obj, name, opaque);
537
+}
538
+
539
+static const PropertyInfo efuse_prop_drive = {
540
+ .name = "str",
541
+ .description = "Node name or ID of a block device to use as eFUSE backend",
542
+ .realized_set_allowed = true,
543
+ .get = efuse_prop_get_drive,
544
+ .set = efuse_prop_set_drive,
545
+ .release = efuse_prop_release_drive,
546
+};
547
+
548
+static Property efuse_properties[] = {
549
+ DEFINE_PROP("drive", XlnxEFuse, blk, efuse_prop_drive, BlockBackend *),
550
+ DEFINE_PROP_UINT8("efuse-nr", XlnxEFuse, efuse_nr, 3),
551
+ DEFINE_PROP_UINT32("efuse-size", XlnxEFuse, efuse_size, 64 * 32),
552
+ DEFINE_PROP_BOOL("init-factory-tbits", XlnxEFuse, init_tbits, true),
553
+ DEFINE_PROP_ARRAY("read-only", XlnxEFuse, ro_bits_cnt, ro_bits,
554
+ qdev_prop_uint32, uint32_t),
555
+ DEFINE_PROP_END_OF_LIST(),
556
+};
557
+
558
+static void efuse_class_init(ObjectClass *klass, void *data)
559
+{
560
+ DeviceClass *dc = DEVICE_CLASS(klass);
561
+
562
+ dc->realize = efuse_realize;
563
+ device_class_set_props(dc, efuse_properties);
564
+}
565
+
566
+static const TypeInfo efuse_info = {
567
+ .name = TYPE_XLNX_EFUSE,
568
+ .parent = TYPE_DEVICE,
569
+ .instance_size = sizeof(XlnxEFuse),
570
+ .class_init = efuse_class_init,
571
+};
572
+
573
+static void efuse_register_types(void)
574
+{
575
+ type_register_static(&efuse_info);
576
+}
577
+type_init(efuse_register_types)
578
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
579
index XXXXXXX..XXXXXXX 100644
615
index XXXXXXX..XXXXXXX 100644
580
--- a/hw/nvram/Kconfig
616
--- a/target/arm/meson.build
581
+++ b/hw/nvram/Kconfig
617
+++ b/target/arm/meson.build
582
@@ -XXX,XX +XXX,XX @@ config NMC93XX_EEPROM
618
@@ -XXX,XX +XXX,XX @@ arm_system_ss.add(files(
583
619
'ptw.c',
584
config CHRP_NVRAM
620
))
585
bool
621
586
+
622
+arm_user_ss = ss.source_set()
587
+config XLNX_EFUSE_CRC
623
+
588
+ bool
624
subdir('hvf')
589
+
625
590
+config XLNX_EFUSE
626
if 'CONFIG_TCG' in config_all_accel
591
+ bool
627
@@ -XXX,XX +XXX,XX @@ endif
592
+ select XLNX_EFUSE_CRC
628
593
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
629
target_arch += {'arm': arm_ss}
630
target_system_arch += {'arm': arm_system_ss}
631
+target_user_arch += {'arm': arm_user_ss}
632
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
594
index XXXXXXX..XXXXXXX 100644
633
index XXXXXXX..XXXXXXX 100644
595
--- a/hw/nvram/meson.build
634
--- a/target/arm/tcg/meson.build
596
+++ b/hw/nvram/meson.build
635
+++ b/target/arm/tcg/meson.build
597
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_AT24C', if_true: files('eeprom_at24c.c'))
636
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
598
softmmu_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c'))
637
arm_system_ss.add(files(
599
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
638
'psci.c',
600
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
639
))
601
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c'))
640
+
602
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
641
+arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c'))
603
642
+arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c'))
604
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
605
--
643
--
606
2.20.1
644
2.34.1
607
608
diff view generated by jsdifflib
[PULL 11/22] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage
Deleted patch
1
From: Tong Ho <tong.ho@xilinx.com>
2
1
3
Add BBRAM and eFUSE usage to the Xilinx Versal Virt board
4
document.
5
6
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
7
Message-id: 20210917052400.1249094-10-tong.ho@xilinx.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
docs/system/arm/xlnx-versal-virt.rst | 49 ++++++++++++++++++++++++++++
12
1 file changed, 49 insertions(+)
13
14
diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/xlnx-versal-virt.rst
17
+++ b/docs/system/arm/xlnx-versal-virt.rst
18
@@ -XXX,XX +XXX,XX @@ Implemented devices:
19
- OCM (256KB of On Chip Memory)
20
- XRAM (4MB of on chip Accelerator RAM)
21
- DDR memory
22
+- BBRAM (36 bytes of Battery-backed RAM)
23
+- eFUSE (3072 bytes of one-time field-programmable bit array)
24
25
QEMU does not yet model any other devices, including the PL and the AI Engine.
26
27
@@ -XXX,XX +XXX,XX @@ Run the following at the U-Boot prompt:
28
fdt set /chosen/dom0 reg <0x00000000 0x40000000 0x0 0x03100000>
29
booti 30000000 - 20000000
30
31
+BBRAM File Backend
32
+""""""""""""""""""
33
+BBRAM can have an optional file backend, which must be a seekable
34
+binary file with a size of 36 bytes or larger. A file with all
35
+binary 0s is a 'blank'.
36
+
37
+To add a file-backend for the BBRAM:
38
+
39
+.. code-block:: bash
40
+
41
+ -drive if=pflash,index=0,file=versal-bbram.bin,format=raw
42
+
43
+To use a different index value, N, from default of 0, add:
44
+
45
+.. code-block:: bash
46
+
47
+ -global xlnx,bbram-ctrl.drive-index=N
48
+
49
+eFUSE File Backend
50
+""""""""""""""""""
51
+eFUSE can have an optional file backend, which must be a seekable
52
+binary file with a size of 3072 bytes or larger. A file with all
53
+binary 0s is a 'blank'.
54
+
55
+To add a file-backend for the eFUSE:
56
+
57
+.. code-block:: bash
58
+
59
+ -drive if=pflash,index=1,file=versal-efuse.bin,format=raw
60
+
61
+To use a different index value, N, from default of 1, add:
62
+
63
+.. code-block:: bash
64
+
65
+ -global xlnx,efuse.drive-index=N
66
+
67
+.. warning::
68
+ In actual physical Versal, BBRAM and eFUSE contain sensitive data.
69
+ The QEMU device models do **not** encrypt nor obfuscate any data
70
+ when holding them in models' memory or when writing them to their
71
+ file backends.
72
+
73
+ Thus, a file backend should be used with caution, and 'format=luks'
74
+ is highly recommended (albeit with usage complexity).
75
+
76
+ Better yet, do not use actual product data when running guest image
77
+ on this Xilinx Versal Virt board.
78
--
79
2.20.1
80
81
diff view generated by jsdifflib
[PULL 12/22] configs: Don't include 32-bit-only GDB XML in aarch64 linux configs
Deleted patch
1
The aarch64-linux QEMU usermode binaries can never run 32-bit
2
code, so they do not need to include the GDB XML for it.
3
(arm_cpu_register_gdb_regs_for_features() will not use these
4
XML files if the CPU has ARM_FEATURE_AARCH64, so we will not
5
advertise to gdb that we have them.)
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210921162901.17508-2-peter.maydell@linaro.org
10
---
11
configs/targets/aarch64-linux-user.mak | 2 +-
12
configs/targets/aarch64_be-linux-user.mak | 2 +-
13
2 files changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak
16
index XXXXXXX..XXXXXXX 100644
17
--- a/configs/targets/aarch64-linux-user.mak
18
+++ b/configs/targets/aarch64-linux-user.mak
19
@@ -XXX,XX +XXX,XX @@
20
TARGET_ARCH=aarch64
21
TARGET_BASE_ARCH=arm
22
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
23
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
24
TARGET_HAS_BFLT=y
25
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
26
diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak
27
index XXXXXXX..XXXXXXX 100644
28
--- a/configs/targets/aarch64_be-linux-user.mak
29
+++ b/configs/targets/aarch64_be-linux-user.mak
30
@@ -XXX,XX +XXX,XX @@
31
TARGET_ARCH=aarch64
32
TARGET_BASE_ARCH=arm
33
TARGET_WORDS_BIGENDIAN=y
34
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
35
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
36
TARGET_HAS_BFLT=y
37
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
38
--
39
2.20.1
40
41
diff view generated by jsdifflib
[PULL 16/22] scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named()
Deleted patch
1
The function scsi_bus_new() creates a new SCSI bus; callers can
2
either pass in a name argument to specify the name of the new bus, or
3
they can pass in NULL to allow the bus to be given an automatically
4
generated unique name. Almost all callers want to use the
5
autogenerated name; the only exception is the virtio-scsi device.
6
1
7
Taking a name argument that should almost always be NULL is an
8
easy-to-misuse API design -- it encourages callers to think perhaps
9
they should pass in some standard name like "scsi" or "scsi-bus". We
10
don't do this anywhere for SCSI, but we do (incorrectly) do it for
11
other bus types such as i2c.
12
13
The function name also implies that it will return a newly allocated
14
object, when it in fact does in-place allocation. We more commonly
15
name such functions foo_init(), with foo_new() being the
16
allocate-and-return variant.
17
18
Replace all the scsi_bus_new() callsites with either:
19
* scsi_bus_init() for the usual case where the caller wants
20
an autogenerated bus name
21
* scsi_bus_init_named() for the rare case where the caller
22
needs to specify the bus name
23
24
and document that for the _named() version it's then the caller's
25
responsibility to think about uniqueness of bus names.
26
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
29
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
30
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
31
Message-id: 20210923121153.23754-2-peter.maydell@linaro.org
32
---
33
include/hw/scsi/scsi.h | 30 ++++++++++++++++++++++++++++--
34
hw/scsi/esp-pci.c | 2 +-
35
hw/scsi/esp.c | 2 +-
36
hw/scsi/lsi53c895a.c | 2 +-
37
hw/scsi/megasas.c | 3 +--
38
hw/scsi/mptsas.c | 2 +-
39
hw/scsi/scsi-bus.c | 4 ++--
40
hw/scsi/spapr_vscsi.c | 3 +--
41
hw/scsi/virtio-scsi.c | 4 ++--
42
hw/scsi/vmw_pvscsi.c | 3 +--
43
hw/usb/dev-storage-bot.c | 3 +--
44
hw/usb/dev-storage-classic.c | 4 ++--
45
hw/usb/dev-uas.c | 3 +--
46
13 files changed, 43 insertions(+), 22 deletions(-)
47
48
diff --git a/include/hw/scsi/scsi.h b/include/hw/scsi/scsi.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/scsi/scsi.h
51
+++ b/include/hw/scsi/scsi.h
52
@@ -XXX,XX +XXX,XX @@ struct SCSIBus {
53
const SCSIBusInfo *info;
54
};
55
56
-void scsi_bus_new(SCSIBus *bus, size_t bus_size, DeviceState *host,
57
- const SCSIBusInfo *info, const char *bus_name);
58
+/**
59
+ * scsi_bus_init_named: Initialize a SCSI bus with the specified name
60
+ * @bus: SCSIBus object to initialize
61
+ * @bus_size: size of @bus object
62
+ * @host: Device which owns the bus (generally the SCSI controller)
63
+ * @info: structure defining callbacks etc for the controller
64
+ * @bus_name: Name to use for this bus
65
+ *
66
+ * This in-place initializes @bus as a new SCSI bus with a name
67
+ * provided by the caller. It is the caller's responsibility to make
68
+ * sure that name does not clash with the name of any other bus in the
69
+ * system. Unless you need the new bus to have a specific name, you
70
+ * should use scsi_bus_new() instead.
71
+ */
72
+void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host,
73
+ const SCSIBusInfo *info, const char *bus_name);
74
+
75
+/**
76
+ * scsi_bus_init: Initialize a SCSI bus
77
+ *
78
+ * This in-place-initializes @bus as a new SCSI bus and gives it
79
+ * an automatically generated unique name.
80
+ */
81
+static inline void scsi_bus_init(SCSIBus *bus, size_t bus_size,
82
+ DeviceState *host, const SCSIBusInfo *info)
83
+{
84
+ scsi_bus_init_named(bus, bus_size, host, info, NULL);
85
+}
86
87
static inline SCSIBus *scsi_bus_from_device(SCSIDevice *d)
88
{
89
diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/hw/scsi/esp-pci.c
92
+++ b/hw/scsi/esp-pci.c
93
@@ -XXX,XX +XXX,XX @@ static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp)
94
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
95
s->irq = pci_allocate_irq(dev);
96
97
- scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL);
98
+ scsi_bus_init(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info);
99
}
100
101
static void esp_pci_scsi_exit(PCIDevice *d)
102
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/hw/scsi/esp.c
105
+++ b/hw/scsi/esp.c
106
@@ -XXX,XX +XXX,XX @@ static void sysbus_esp_realize(DeviceState *dev, Error **errp)
107
108
qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
109
110
- scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
111
+ scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info);
112
}
113
114
static void sysbus_esp_hard_reset(DeviceState *dev)
115
diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
116
index XXXXXXX..XXXXXXX 100644
117
--- a/hw/scsi/lsi53c895a.c
118
+++ b/hw/scsi/lsi53c895a.c
119
@@ -XXX,XX +XXX,XX @@ static void lsi_scsi_realize(PCIDevice *dev, Error **errp)
120
pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_io);
121
QTAILQ_INIT(&s->queue);
122
123
- scsi_bus_new(&s->bus, sizeof(s->bus), d, &lsi_scsi_info, NULL);
124
+ scsi_bus_init(&s->bus, sizeof(s->bus), d, &lsi_scsi_info);
125
}
126
127
static void lsi_scsi_exit(PCIDevice *dev)
128
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/hw/scsi/megasas.c
131
+++ b/hw/scsi/megasas.c
132
@@ -XXX,XX +XXX,XX @@ static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
133
s->frames[i].state = s;
134
}
135
136
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
137
- &megasas_scsi_info, NULL);
138
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &megasas_scsi_info);
139
}
140
141
static Property megasas_properties_gen1[] = {
142
diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c
143
index XXXXXXX..XXXXXXX 100644
144
--- a/hw/scsi/mptsas.c
145
+++ b/hw/scsi/mptsas.c
146
@@ -XXX,XX +XXX,XX @@ static void mptsas_scsi_realize(PCIDevice *dev, Error **errp)
147
148
s->request_bh = qemu_bh_new(mptsas_fetch_requests, s);
149
150
- scsi_bus_new(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info, NULL);
151
+ scsi_bus_init(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info);
152
}
153
154
static void mptsas_scsi_uninit(PCIDevice *dev)
155
diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c
156
index XXXXXXX..XXXXXXX 100644
157
--- a/hw/scsi/scsi-bus.c
158
+++ b/hw/scsi/scsi-bus.c
159
@@ -XXX,XX +XXX,XX @@ void scsi_device_unit_attention_reported(SCSIDevice *s)
160
}
161
162
/* Create a scsi bus, and attach devices to it. */
163
-void scsi_bus_new(SCSIBus *bus, size_t bus_size, DeviceState *host,
164
- const SCSIBusInfo *info, const char *bus_name)
165
+void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host,
166
+ const SCSIBusInfo *info, const char *bus_name)
167
{
168
qbus_create_inplace(bus, bus_size, TYPE_SCSI_BUS, host, bus_name);
169
bus->busnr = next_scsi_bus++;
170
diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c
171
index XXXXXXX..XXXXXXX 100644
172
--- a/hw/scsi/spapr_vscsi.c
173
+++ b/hw/scsi/spapr_vscsi.c
174
@@ -XXX,XX +XXX,XX @@ static void spapr_vscsi_realize(SpaprVioDevice *dev, Error **errp)
175
176
dev->crq.SendFunc = vscsi_do_crq;
177
178
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
179
- &vscsi_scsi_info, NULL);
180
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &vscsi_scsi_info);
181
182
/* ibmvscsi SCSI bus does not allow hotplug. */
183
qbus_set_hotplug_handler(BUS(&s->bus), NULL);
184
diff --git a/hw/scsi/virtio-scsi.c b/hw/scsi/virtio-scsi.c
185
index XXXXXXX..XXXXXXX 100644
186
--- a/hw/scsi/virtio-scsi.c
187
+++ b/hw/scsi/virtio-scsi.c
188
@@ -XXX,XX +XXX,XX @@ static void virtio_scsi_device_realize(DeviceState *dev, Error **errp)
189
return;
190
}
191
192
- scsi_bus_new(&s->bus, sizeof(s->bus), dev,
193
- &virtio_scsi_scsi_info, vdev->bus_name);
194
+ scsi_bus_init_named(&s->bus, sizeof(s->bus), dev,
195
+ &virtio_scsi_scsi_info, vdev->bus_name);
196
/* override default SCSI bus hotplug-handler, with virtio-scsi's one */
197
qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(dev));
198
199
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/hw/scsi/vmw_pvscsi.c
202
+++ b/hw/scsi/vmw_pvscsi.c
203
@@ -XXX,XX +XXX,XX @@ pvscsi_realizefn(PCIDevice *pci_dev, Error **errp)
204
205
s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s);
206
207
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
208
- &pvscsi_scsi_info, NULL);
209
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev), &pvscsi_scsi_info);
210
/* override default SCSI bus hotplug-handler, with pvscsi's one */
211
qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(s));
212
pvscsi_reset_state(s);
213
diff --git a/hw/usb/dev-storage-bot.c b/hw/usb/dev-storage-bot.c
214
index XXXXXXX..XXXXXXX 100644
215
--- a/hw/usb/dev-storage-bot.c
216
+++ b/hw/usb/dev-storage-bot.c
217
@@ -XXX,XX +XXX,XX @@ static void usb_msd_bot_realize(USBDevice *dev, Error **errp)
218
s->dev.auto_attach = 0;
219
}
220
221
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
222
- &usb_msd_scsi_info_bot, NULL);
223
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &usb_msd_scsi_info_bot);
224
usb_msd_handle_reset(dev);
225
}
226
227
diff --git a/hw/usb/dev-storage-classic.c b/hw/usb/dev-storage-classic.c
228
index XXXXXXX..XXXXXXX 100644
229
--- a/hw/usb/dev-storage-classic.c
230
+++ b/hw/usb/dev-storage-classic.c
231
@@ -XXX,XX +XXX,XX @@ static void usb_msd_storage_realize(USBDevice *dev, Error **errp)
232
usb_desc_create_serial(dev);
233
usb_desc_init(dev);
234
dev->flags |= (1 << USB_DEV_FLAG_IS_SCSI_STORAGE);
235
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
236
- &usb_msd_scsi_info_storage, NULL);
237
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev),
238
+ &usb_msd_scsi_info_storage);
239
scsi_dev = scsi_bus_legacy_add_drive(&s->bus, blk, 0, !!s->removable,
240
s->conf.bootindex, s->conf.share_rw,
241
s->conf.rerror, s->conf.werror,
242
diff --git a/hw/usb/dev-uas.c b/hw/usb/dev-uas.c
243
index XXXXXXX..XXXXXXX 100644
244
--- a/hw/usb/dev-uas.c
245
+++ b/hw/usb/dev-uas.c
246
@@ -XXX,XX +XXX,XX @@ static void usb_uas_realize(USBDevice *dev, Error **errp)
247
uas->status_bh = qemu_bh_new(usb_uas_send_status_bh, uas);
248
249
dev->flags |= (1 << USB_DEV_FLAG_IS_SCSI_STORAGE);
250
- scsi_bus_new(&uas->bus, sizeof(uas->bus), DEVICE(dev),
251
- &usb_uas_scsi_info, NULL);
252
+ scsi_bus_init(&uas->bus, sizeof(uas->bus), DEVICE(dev), &usb_uas_scsi_info);
253
}
254
255
static const VMStateDescription vmstate_usb_uas = {
256
--
257
2.20.1
258
259
diff view generated by jsdifflib
[PULL 17/22] ipack: Rename ipack_bus_new_inplace() to ipack_bus_init()
Deleted patch
1
Rename ipack_bus_new_inplace() to ipack_bus_init(), to bring it in to
2
line with a "_init for in-place init, _new for allocate-and-return"
3
convention. Drop the 'name' argument, because the only caller does
4
not pass in a name. If a future caller does need to specify the bus
5
name, we should create an ipack_bus_init_named() function at that
6
point.
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
11
Message-id: 20210923121153.23754-3-peter.maydell@linaro.org
12
---
13
include/hw/ipack/ipack.h | 8 ++++----
14
hw/ipack/ipack.c | 10 +++++-----
15
hw/ipack/tpci200.c | 4 ++--
16
3 files changed, 11 insertions(+), 11 deletions(-)
17
18
diff --git a/include/hw/ipack/ipack.h b/include/hw/ipack/ipack.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/ipack/ipack.h
21
+++ b/include/hw/ipack/ipack.h
22
@@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ipack_device;
23
VMSTATE_STRUCT(_field, _state, 1, vmstate_ipack_device, IPackDevice)
24
25
IPackDevice *ipack_device_find(IPackBus *bus, int32_t slot);
26
-void ipack_bus_new_inplace(IPackBus *bus, size_t bus_size,
27
- DeviceState *parent,
28
- const char *name, uint8_t n_slots,
29
- qemu_irq_handler handler);
30
+void ipack_bus_init(IPackBus *bus, size_t bus_size,
31
+ DeviceState *parent,
32
+ uint8_t n_slots,
33
+ qemu_irq_handler handler);
34
35
#endif
36
diff --git a/hw/ipack/ipack.c b/hw/ipack/ipack.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/ipack/ipack.c
39
+++ b/hw/ipack/ipack.c
40
@@ -XXX,XX +XXX,XX @@ IPackDevice *ipack_device_find(IPackBus *bus, int32_t slot)
41
return NULL;
42
}
43
44
-void ipack_bus_new_inplace(IPackBus *bus, size_t bus_size,
45
- DeviceState *parent,
46
- const char *name, uint8_t n_slots,
47
- qemu_irq_handler handler)
48
+void ipack_bus_init(IPackBus *bus, size_t bus_size,
49
+ DeviceState *parent,
50
+ uint8_t n_slots,
51
+ qemu_irq_handler handler)
52
{
53
- qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, name);
54
+ qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, NULL);
55
bus->n_slots = n_slots;
56
bus->set_irq = handler;
57
}
58
diff --git a/hw/ipack/tpci200.c b/hw/ipack/tpci200.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/hw/ipack/tpci200.c
61
+++ b/hw/ipack/tpci200.c
62
@@ -XXX,XX +XXX,XX @@ static void tpci200_realize(PCIDevice *pci_dev, Error **errp)
63
pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las2);
64
pci_register_bar(&s->dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las3);
65
66
- ipack_bus_new_inplace(&s->bus, sizeof(s->bus), DEVICE(pci_dev), NULL,
67
- N_MODULES, tpci200_set_irq);
68
+ ipack_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
69
+ N_MODULES, tpci200_set_irq);
70
}
71
72
static const VMStateDescription vmstate_tpci200 = {
73
--
74
2.20.1
75
76
diff view generated by jsdifflib
[PULL 18/22] pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init()
Deleted patch
1
Rename the pci_root_bus_new_inplace() function to
2
pci_root_bus_init(); this brings the bus type in to line with a
3
"_init for in-place init, _new for allocate-and-return" convention.
4
To do this we need to rename the implementation-internal function
5
that was using the pci_root_bus_init() name to
6
pci_root_bus_internal_init().
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
11
Message-id: 20210923121153.23754-4-peter.maydell@linaro.org
12
---
13
include/hw/pci/pci.h | 10 +++++-----
14
hw/pci-host/raven.c | 4 ++--
15
hw/pci-host/versatile.c | 6 +++---
16
hw/pci/pci.c | 26 +++++++++++++-------------
17
4 files changed, 23 insertions(+), 23 deletions(-)
18
19
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/pci/pci.h
22
+++ b/include/hw/pci/pci.h
23
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
24
25
bool pci_bus_is_express(PCIBus *bus);
26
27
-void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
28
- const char *name,
29
- MemoryRegion *address_space_mem,
30
- MemoryRegion *address_space_io,
31
- uint8_t devfn_min, const char *typename);
32
+void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
33
+ const char *name,
34
+ MemoryRegion *address_space_mem,
35
+ MemoryRegion *address_space_io,
36
+ uint8_t devfn_min, const char *typename);
37
PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
38
MemoryRegion *address_space_mem,
39
MemoryRegion *address_space_io,
40
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/pci-host/raven.c
43
+++ b/hw/pci-host/raven.c
44
@@ -XXX,XX +XXX,XX @@ static void raven_pcihost_initfn(Object *obj)
45
memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR,
46
&s->pci_io_non_contiguous, 1);
47
memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
48
- pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
49
- &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
50
+ pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
51
+ &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
52
53
/* Bus master address space */
54
memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB);
55
diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/pci-host/versatile.c
58
+++ b/hw/pci-host/versatile.c
59
@@ -XXX,XX +XXX,XX @@ static void pci_vpb_realize(DeviceState *dev, Error **errp)
60
memory_region_init(&s->pci_io_space, OBJECT(s), "pci_io", 4 * GiB);
61
memory_region_init(&s->pci_mem_space, OBJECT(s), "pci_mem", 4 * GiB);
62
63
- pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), dev, "pci",
64
- &s->pci_mem_space, &s->pci_io_space,
65
- PCI_DEVFN(11, 0), TYPE_PCI_BUS);
66
+ pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), dev, "pci",
67
+ &s->pci_mem_space, &s->pci_io_space,
68
+ PCI_DEVFN(11, 0), TYPE_PCI_BUS);
69
h->bus = &s->pci_bus;
70
71
object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_VERSATILE_PCI_HOST);
72
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/pci/pci.c
75
+++ b/hw/pci/pci.c
76
@@ -XXX,XX +XXX,XX @@ bool pci_bus_bypass_iommu(PCIBus *bus)
77
return host_bridge->bypass_iommu;
78
}
79
80
-static void pci_root_bus_init(PCIBus *bus, DeviceState *parent,
81
- MemoryRegion *address_space_mem,
82
- MemoryRegion *address_space_io,
83
- uint8_t devfn_min)
84
+static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent,
85
+ MemoryRegion *address_space_mem,
86
+ MemoryRegion *address_space_io,
87
+ uint8_t devfn_min)
88
{
89
assert(PCI_FUNC(devfn_min) == 0);
90
bus->devfn_min = devfn_min;
91
@@ -XXX,XX +XXX,XX @@ bool pci_bus_is_express(PCIBus *bus)
92
return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
93
}
94
95
-void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
96
- const char *name,
97
- MemoryRegion *address_space_mem,
98
- MemoryRegion *address_space_io,
99
- uint8_t devfn_min, const char *typename)
100
+void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
101
+ const char *name,
102
+ MemoryRegion *address_space_mem,
103
+ MemoryRegion *address_space_io,
104
+ uint8_t devfn_min, const char *typename)
105
{
106
qbus_create_inplace(bus, bus_size, typename, parent, name);
107
- pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
108
- devfn_min);
109
+ pci_root_bus_internal_init(bus, parent, address_space_mem,
110
+ address_space_io, devfn_min);
111
}
112
113
PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
114
@@ -XXX,XX +XXX,XX @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
115
PCIBus *bus;
116
117
bus = PCI_BUS(qbus_create(typename, parent, name));
118
- pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
119
- devfn_min);
120
+ pci_root_bus_internal_init(bus, parent, address_space_mem,
121
+ address_space_io, devfn_min);
122
return bus;
123
}
124
125
--
126
2.20.1
127
128
diff view generated by jsdifflib
[PULL 19/22] qbus: Rename qbus_create_inplace() to qbus_init()
Deleted patch
1
Rename qbus_create_inplace() to qbus_init(); this is more in line
2
with our usual naming convention for functions that in-place
3
initialize objects.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
8
Message-id: 20210923121153.23754-5-peter.maydell@linaro.org
9
---
10
include/hw/qdev-core.h | 4 ++--
11
hw/audio/intel-hda.c | 2 +-
12
hw/block/fdc.c | 2 +-
13
hw/block/swim.c | 3 +--
14
hw/char/virtio-serial-bus.c | 4 ++--
15
hw/core/bus.c | 11 ++++++-----
16
hw/core/sysbus.c | 10 ++++++----
17
hw/gpio/bcm2835_gpio.c | 3 +--
18
hw/ide/qdev.c | 2 +-
19
hw/ipack/ipack.c | 2 +-
20
hw/misc/mac_via.c | 4 ++--
21
hw/misc/macio/cuda.c | 4 ++--
22
hw/misc/macio/macio.c | 4 ++--
23
hw/misc/macio/pmu.c | 4 ++--
24
hw/nubus/nubus-bridge.c | 2 +-
25
hw/nvme/ctrl.c | 4 ++--
26
hw/nvme/subsys.c | 3 +--
27
hw/pci/pci.c | 2 +-
28
hw/pci/pci_bridge.c | 4 ++--
29
hw/s390x/event-facility.c | 4 ++--
30
hw/s390x/virtio-ccw.c | 3 +--
31
hw/scsi/scsi-bus.c | 2 +-
32
hw/sd/allwinner-sdhost.c | 4 ++--
33
hw/sd/bcm2835_sdhost.c | 4 ++--
34
hw/sd/pl181.c | 3 +--
35
hw/sd/pxa2xx_mmci.c | 4 ++--
36
hw/sd/sdhci.c | 3 +--
37
hw/sd/ssi-sd.c | 3 +--
38
hw/usb/bus.c | 2 +-
39
hw/usb/dev-smartcard-reader.c | 3 +--
40
hw/virtio/virtio-mmio.c | 3 +--
41
hw/virtio/virtio-pci.c | 3 +--
42
32 files changed, 54 insertions(+), 61 deletions(-)
43
44
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/qdev-core.h
47
+++ b/include/hw/qdev-core.h
48
@@ -XXX,XX +XXX,XX @@ DeviceState *qdev_find_recursive(BusState *bus, const char *id);
49
typedef int (qbus_walkerfn)(BusState *bus, void *opaque);
50
typedef int (qdev_walkerfn)(DeviceState *dev, void *opaque);
51
52
-void qbus_create_inplace(void *bus, size_t size, const char *typename,
53
- DeviceState *parent, const char *name);
54
+void qbus_init(void *bus, size_t size, const char *typename,
55
+ DeviceState *parent, const char *name);
56
BusState *qbus_create(const char *typename, DeviceState *parent, const char *name);
57
bool qbus_realize(BusState *bus, Error **errp);
58
void qbus_unrealize(BusState *bus);
59
diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/audio/intel-hda.c
62
+++ b/hw/audio/intel-hda.c
63
@@ -XXX,XX +XXX,XX @@ void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
64
hda_codec_response_func response,
65
hda_codec_xfer_func xfer)
66
{
67
- qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
68
+ qbus_init(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
69
bus->response = response;
70
bus->xfer = xfer;
71
}
72
diff --git a/hw/block/fdc.c b/hw/block/fdc.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/block/fdc.c
75
+++ b/hw/block/fdc.c
76
@@ -XXX,XX +XXX,XX @@ static const TypeInfo floppy_bus_info = {
77
78
static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev)
79
{
80
- qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
81
+ qbus_init(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
82
bus->fdc = fdc;
83
}
84
85
diff --git a/hw/block/swim.c b/hw/block/swim.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/hw/block/swim.c
88
+++ b/hw/block/swim.c
89
@@ -XXX,XX +XXX,XX @@ static void sysbus_swim_realize(DeviceState *dev, Error **errp)
90
Swim *sys = SWIM(dev);
91
SWIMCtrl *swimctrl = &sys->ctrl;
92
93
- qbus_create_inplace(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev,
94
- NULL);
95
+ qbus_init(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev, NULL);
96
swimctrl->bus.ctrl = swimctrl;
97
}
98
99
diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/hw/char/virtio-serial-bus.c
102
+++ b/hw/char/virtio-serial-bus.c
103
@@ -XXX,XX +XXX,XX @@ static void virtio_serial_device_realize(DeviceState *dev, Error **errp)
104
config_size);
105
106
/* Spawn a new virtio-serial bus on which the ports will ride as devices */
107
- qbus_create_inplace(&vser->bus, sizeof(vser->bus), TYPE_VIRTIO_SERIAL_BUS,
108
- dev, vdev->bus_name);
109
+ qbus_init(&vser->bus, sizeof(vser->bus), TYPE_VIRTIO_SERIAL_BUS,
110
+ dev, vdev->bus_name);
111
qbus_set_hotplug_handler(BUS(&vser->bus), OBJECT(vser));
112
vser->bus.vser = vser;
113
QTAILQ_INIT(&vser->ports);
114
diff --git a/hw/core/bus.c b/hw/core/bus.c
115
index XXXXXXX..XXXXXXX 100644
116
--- a/hw/core/bus.c
117
+++ b/hw/core/bus.c
118
@@ -XXX,XX +XXX,XX @@ static void bus_reset_child_foreach(Object *obj, ResettableChildCallback cb,
119
}
120
}
121
122
-static void qbus_init(BusState *bus, DeviceState *parent, const char *name)
123
+static void qbus_init_internal(BusState *bus, DeviceState *parent,
124
+ const char *name)
125
{
126
const char *typename = object_get_typename(OBJECT(bus));
127
BusClass *bc;
128
@@ -XXX,XX +XXX,XX @@ static void bus_unparent(Object *obj)
129
bus->parent = NULL;
130
}
131
132
-void qbus_create_inplace(void *bus, size_t size, const char *typename,
133
- DeviceState *parent, const char *name)
134
+void qbus_init(void *bus, size_t size, const char *typename,
135
+ DeviceState *parent, const char *name)
136
{
137
object_initialize(bus, size, typename);
138
- qbus_init(bus, parent, name);
139
+ qbus_init_internal(bus, parent, name);
140
}
141
142
BusState *qbus_create(const char *typename, DeviceState *parent, const char *name)
143
@@ -XXX,XX +XXX,XX @@ BusState *qbus_create(const char *typename, DeviceState *parent, const char *nam
144
BusState *bus;
145
146
bus = BUS(object_new(typename));
147
- qbus_init(bus, parent, name);
148
+ qbus_init_internal(bus, parent, name);
149
150
return bus;
151
}
152
diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c
153
index XXXXXXX..XXXXXXX 100644
154
--- a/hw/core/sysbus.c
155
+++ b/hw/core/sysbus.c
156
@@ -XXX,XX +XXX,XX @@ static BusState *main_system_bus;
157
158
static void main_system_bus_create(void)
159
{
160
- /* assign main_system_bus before qbus_create_inplace()
161
- * in order to make "if (bus != sysbus_get_default())" work */
162
+ /*
163
+ * assign main_system_bus before qbus_init()
164
+ * in order to make "if (bus != sysbus_get_default())" work
165
+ */
166
main_system_bus = g_malloc0(system_bus_info.instance_size);
167
- qbus_create_inplace(main_system_bus, system_bus_info.instance_size,
168
- TYPE_SYSTEM_BUS, NULL, "main-system-bus");
169
+ qbus_init(main_system_bus, system_bus_info.instance_size,
170
+ TYPE_SYSTEM_BUS, NULL, "main-system-bus");
171
OBJECT(main_system_bus)->free = g_free;
172
}
173
174
diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c
175
index XXXXXXX..XXXXXXX 100644
176
--- a/hw/gpio/bcm2835_gpio.c
177
+++ b/hw/gpio/bcm2835_gpio.c
178
@@ -XXX,XX +XXX,XX @@ static void bcm2835_gpio_init(Object *obj)
179
DeviceState *dev = DEVICE(obj);
180
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
181
182
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
183
- TYPE_SD_BUS, DEVICE(s), "sd-bus");
184
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(s), "sd-bus");
185
186
memory_region_init_io(&s->iomem, obj,
187
&bcm2835_gpio_ops, s, "bcm2835_gpio", 0x1000);
188
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
189
index XXXXXXX..XXXXXXX 100644
190
--- a/hw/ide/qdev.c
191
+++ b/hw/ide/qdev.c
192
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ide_bus_info = {
193
void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
194
int bus_id, int max_units)
195
{
196
- qbus_create_inplace(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL);
197
+ qbus_init(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL);
198
idebus->bus_id = bus_id;
199
idebus->max_units = max_units;
200
}
201
diff --git a/hw/ipack/ipack.c b/hw/ipack/ipack.c
202
index XXXXXXX..XXXXXXX 100644
203
--- a/hw/ipack/ipack.c
204
+++ b/hw/ipack/ipack.c
205
@@ -XXX,XX +XXX,XX @@ void ipack_bus_init(IPackBus *bus, size_t bus_size,
206
uint8_t n_slots,
207
qemu_irq_handler handler)
208
{
209
- qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, NULL);
210
+ qbus_init(bus, bus_size, TYPE_IPACK_BUS, parent, NULL);
211
bus->n_slots = n_slots;
212
bus->set_irq = handler;
213
}
214
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
215
index XXXXXXX..XXXXXXX 100644
216
--- a/hw/misc/mac_via.c
217
+++ b/hw/misc/mac_via.c
218
@@ -XXX,XX +XXX,XX @@ static void mos6522_q800_via1_init(Object *obj)
219
sysbus_init_mmio(sbd, &v1s->via_mem);
220
221
/* ADB */
222
- qbus_create_inplace((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus),
223
- TYPE_ADB_BUS, DEVICE(v1s), "adb.0");
224
+ qbus_init((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus),
225
+ TYPE_ADB_BUS, DEVICE(v1s), "adb.0");
226
227
qdev_init_gpio_in(DEVICE(obj), via1_irq_request, VIA1_IRQ_NB);
228
}
229
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c
230
index XXXXXXX..XXXXXXX 100644
231
--- a/hw/misc/macio/cuda.c
232
+++ b/hw/misc/macio/cuda.c
233
@@ -XXX,XX +XXX,XX @@ static void cuda_init(Object *obj)
234
memory_region_init_io(&s->mem, obj, &mos6522_cuda_ops, s, "cuda", 0x2000);
235
sysbus_init_mmio(sbd, &s->mem);
236
237
- qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
238
- DEVICE(obj), "adb.0");
239
+ qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
240
+ DEVICE(obj), "adb.0");
241
}
242
243
static Property cuda_properties[] = {
244
diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
245
index XXXXXXX..XXXXXXX 100644
246
--- a/hw/misc/macio/macio.c
247
+++ b/hw/misc/macio/macio.c
248
@@ -XXX,XX +XXX,XX @@ static void macio_instance_init(Object *obj)
249
250
memory_region_init(&s->bar, obj, "macio", 0x80000);
251
252
- qbus_create_inplace(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS,
253
- DEVICE(obj), "macio.0");
254
+ qbus_init(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS,
255
+ DEVICE(obj), "macio.0");
256
257
object_initialize_child(OBJECT(s), "dbdma", &s->dbdma, TYPE_MAC_DBDMA);
258
259
diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c
260
index XXXXXXX..XXXXXXX 100644
261
--- a/hw/misc/macio/pmu.c
262
+++ b/hw/misc/macio/pmu.c
263
@@ -XXX,XX +XXX,XX @@ static void pmu_realize(DeviceState *dev, Error **errp)
264
timer_mod(s->one_sec_timer, s->one_sec_target);
265
266
if (s->has_adb) {
267
- qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
268
- dev, "adb.0");
269
+ qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
270
+ dev, "adb.0");
271
adb_register_autopoll_callback(adb_bus, pmu_adb_poll, s);
272
}
273
}
274
diff --git a/hw/nubus/nubus-bridge.c b/hw/nubus/nubus-bridge.c
275
index XXXXXXX..XXXXXXX 100644
276
--- a/hw/nubus/nubus-bridge.c
277
+++ b/hw/nubus/nubus-bridge.c
278
@@ -XXX,XX +XXX,XX @@ static void nubus_bridge_init(Object *obj)
279
NubusBridge *s = NUBUS_BRIDGE(obj);
280
NubusBus *bus = &s->bus;
281
282
- qbus_create_inplace(bus, sizeof(s->bus), TYPE_NUBUS_BUS, DEVICE(s), NULL);
283
+ qbus_init(bus, sizeof(s->bus), TYPE_NUBUS_BUS, DEVICE(s), NULL);
284
285
qdev_init_gpio_out(DEVICE(s), bus->irqs, NUBUS_IRQS);
286
}
287
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
288
index XXXXXXX..XXXXXXX 100644
289
--- a/hw/nvme/ctrl.c
290
+++ b/hw/nvme/ctrl.c
291
@@ -XXX,XX +XXX,XX @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
292
return;
293
}
294
295
- qbus_create_inplace(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS,
296
- &pci_dev->qdev, n->parent_obj.qdev.id);
297
+ qbus_init(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS,
298
+ &pci_dev->qdev, n->parent_obj.qdev.id);
299
300
nvme_init_state(n);
301
if (nvme_init_pci(n, pci_dev, errp)) {
302
diff --git a/hw/nvme/subsys.c b/hw/nvme/subsys.c
303
index XXXXXXX..XXXXXXX 100644
304
--- a/hw/nvme/subsys.c
305
+++ b/hw/nvme/subsys.c
306
@@ -XXX,XX +XXX,XX @@ static void nvme_subsys_realize(DeviceState *dev, Error **errp)
307
{
308
NvmeSubsystem *subsys = NVME_SUBSYS(dev);
309
310
- qbus_create_inplace(&subsys->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev,
311
- dev->id);
312
+ qbus_init(&subsys->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev, dev->id);
313
314
nvme_subsys_setup(subsys);
315
}
316
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
317
index XXXXXXX..XXXXXXX 100644
318
--- a/hw/pci/pci.c
319
+++ b/hw/pci/pci.c
320
@@ -XXX,XX +XXX,XX @@ void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
321
MemoryRegion *address_space_io,
322
uint8_t devfn_min, const char *typename)
323
{
324
- qbus_create_inplace(bus, bus_size, typename, parent, name);
325
+ qbus_init(bus, bus_size, typename, parent, name);
326
pci_root_bus_internal_init(bus, parent, address_space_mem,
327
address_space_io, devfn_min);
328
}
329
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
330
index XXXXXXX..XXXXXXX 100644
331
--- a/hw/pci/pci_bridge.c
332
+++ b/hw/pci/pci_bridge.c
333
@@ -XXX,XX +XXX,XX @@ void pci_bridge_initfn(PCIDevice *dev, const char *typename)
334
br->bus_name = dev->qdev.id;
335
}
336
337
- qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
338
- br->bus_name);
339
+ qbus_init(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
340
+ br->bus_name);
341
sec_bus->parent_dev = dev;
342
sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
343
sec_bus->address_space_mem = &br->address_space_mem;
344
diff --git a/hw/s390x/event-facility.c b/hw/s390x/event-facility.c
345
index XXXXXXX..XXXXXXX 100644
346
--- a/hw/s390x/event-facility.c
347
+++ b/hw/s390x/event-facility.c
348
@@ -XXX,XX +XXX,XX @@ static void init_event_facility(Object *obj)
349
sclp_event_set_allow_all_mask_sizes);
350
351
/* Spawn a new bus for SCLP events */
352
- qbus_create_inplace(&event_facility->sbus, sizeof(event_facility->sbus),
353
- TYPE_SCLP_EVENTS_BUS, sdev, NULL);
354
+ qbus_init(&event_facility->sbus, sizeof(event_facility->sbus),
355
+ TYPE_SCLP_EVENTS_BUS, sdev, NULL);
356
357
object_initialize_child(obj, TYPE_SCLP_QUIESCE,
358
&event_facility->quiesce,
359
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
360
index XXXXXXX..XXXXXXX 100644
361
--- a/hw/s390x/virtio-ccw.c
362
+++ b/hw/s390x/virtio-ccw.c
363
@@ -XXX,XX +XXX,XX @@ static void virtio_ccw_bus_new(VirtioBusState *bus, size_t bus_size,
364
DeviceState *qdev = DEVICE(dev);
365
char virtio_bus_name[] = "virtio-bus";
366
367
- qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_CCW_BUS,
368
- qdev, virtio_bus_name);
369
+ qbus_init(bus, bus_size, TYPE_VIRTIO_CCW_BUS, qdev, virtio_bus_name);
370
}
371
372
static void virtio_ccw_bus_class_init(ObjectClass *klass, void *data)
373
diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c
374
index XXXXXXX..XXXXXXX 100644
375
--- a/hw/scsi/scsi-bus.c
376
+++ b/hw/scsi/scsi-bus.c
377
@@ -XXX,XX +XXX,XX @@ void scsi_device_unit_attention_reported(SCSIDevice *s)
378
void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host,
379
const SCSIBusInfo *info, const char *bus_name)
380
{
381
- qbus_create_inplace(bus, bus_size, TYPE_SCSI_BUS, host, bus_name);
382
+ qbus_init(bus, bus_size, TYPE_SCSI_BUS, host, bus_name);
383
bus->busnr = next_scsi_bus++;
384
bus->info = info;
385
qbus_set_bus_hotplug_handler(BUS(bus));
386
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
387
index XXXXXXX..XXXXXXX 100644
388
--- a/hw/sd/allwinner-sdhost.c
389
+++ b/hw/sd/allwinner-sdhost.c
390
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_init(Object *obj)
391
{
392
AwSdHostState *s = AW_SDHOST(obj);
393
394
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
395
- TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
396
+ qbus_init(&s->sdbus, sizeof(s->sdbus),
397
+ TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
398
399
memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
400
TYPE_AW_SDHOST, 4 * KiB);
401
diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c
402
index XXXXXXX..XXXXXXX 100644
403
--- a/hw/sd/bcm2835_sdhost.c
404
+++ b/hw/sd/bcm2835_sdhost.c
405
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_init(Object *obj)
406
{
407
BCM2835SDHostState *s = BCM2835_SDHOST(obj);
408
409
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
410
- TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus");
411
+ qbus_init(&s->sdbus, sizeof(s->sdbus),
412
+ TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus");
413
414
memory_region_init_io(&s->iomem, obj, &bcm2835_sdhost_ops, s,
415
TYPE_BCM2835_SDHOST, 0x1000);
416
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
417
index XXXXXXX..XXXXXXX 100644
418
--- a/hw/sd/pl181.c
419
+++ b/hw/sd/pl181.c
420
@@ -XXX,XX +XXX,XX @@ static void pl181_init(Object *obj)
421
qdev_init_gpio_out_named(dev, &s->card_readonly, "card-read-only", 1);
422
qdev_init_gpio_out_named(dev, &s->card_inserted, "card-inserted", 1);
423
424
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
425
- TYPE_PL181_BUS, dev, "sd-bus");
426
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_PL181_BUS, dev, "sd-bus");
427
}
428
429
static void pl181_class_init(ObjectClass *klass, void *data)
430
diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c
431
index XXXXXXX..XXXXXXX 100644
432
--- a/hw/sd/pxa2xx_mmci.c
433
+++ b/hw/sd/pxa2xx_mmci.c
434
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_mmci_instance_init(Object *obj)
435
qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
436
qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);
437
438
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
439
- TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
440
+ qbus_init(&s->sdbus, sizeof(s->sdbus),
441
+ TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
442
}
443
444
static void pxa2xx_mmci_class_init(ObjectClass *klass, void *data)
445
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
446
index XXXXXXX..XXXXXXX 100644
447
--- a/hw/sd/sdhci.c
448
+++ b/hw/sd/sdhci.c
449
@@ -XXX,XX +XXX,XX @@ static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
450
451
void sdhci_initfn(SDHCIState *s)
452
{
453
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
454
- TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
455
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
456
457
s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
458
s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
459
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
460
index XXXXXXX..XXXXXXX 100644
461
--- a/hw/sd/ssi-sd.c
462
+++ b/hw/sd/ssi-sd.c
463
@@ -XXX,XX +XXX,XX @@ static void ssi_sd_realize(SSIPeripheral *d, Error **errp)
464
DeviceState *carddev;
465
DriveInfo *dinfo;
466
467
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
468
- DEVICE(d), "sd-bus");
469
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(d), "sd-bus");
470
471
/* Create and plug in the sd card */
472
/* FIXME use a qdev drive property instead of drive_get_next() */
473
diff --git a/hw/usb/bus.c b/hw/usb/bus.c
474
index XXXXXXX..XXXXXXX 100644
475
--- a/hw/usb/bus.c
476
+++ b/hw/usb/bus.c
477
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_usb_device = {
478
void usb_bus_new(USBBus *bus, size_t bus_size,
479
USBBusOps *ops, DeviceState *host)
480
{
481
- qbus_create_inplace(bus, bus_size, TYPE_USB_BUS, host, NULL);
482
+ qbus_init(bus, bus_size, TYPE_USB_BUS, host, NULL);
483
qbus_set_bus_hotplug_handler(BUS(bus));
484
bus->ops = ops;
485
bus->busnr = next_usb_bus++;
486
diff --git a/hw/usb/dev-smartcard-reader.c b/hw/usb/dev-smartcard-reader.c
487
index XXXXXXX..XXXXXXX 100644
488
--- a/hw/usb/dev-smartcard-reader.c
489
+++ b/hw/usb/dev-smartcard-reader.c
490
@@ -XXX,XX +XXX,XX @@ static void ccid_realize(USBDevice *dev, Error **errp)
491
492
usb_desc_create_serial(dev);
493
usb_desc_init(dev);
494
- qbus_create_inplace(&s->bus, sizeof(s->bus), TYPE_CCID_BUS, DEVICE(dev),
495
- NULL);
496
+ qbus_init(&s->bus, sizeof(s->bus), TYPE_CCID_BUS, DEVICE(dev), NULL);
497
qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(dev));
498
s->intr = usb_ep_get(dev, USB_TOKEN_IN, CCID_INT_IN_EP);
499
s->bulk = usb_ep_get(dev, USB_TOKEN_IN, CCID_BULK_IN_EP);
500
diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c
501
index XXXXXXX..XXXXXXX 100644
502
--- a/hw/virtio/virtio-mmio.c
503
+++ b/hw/virtio/virtio-mmio.c
504
@@ -XXX,XX +XXX,XX @@ static void virtio_mmio_realizefn(DeviceState *d, Error **errp)
505
VirtIOMMIOProxy *proxy = VIRTIO_MMIO(d);
506
SysBusDevice *sbd = SYS_BUS_DEVICE(d);
507
508
- qbus_create_inplace(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS,
509
- d, NULL);
510
+ qbus_init(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS, d, NULL);
511
sysbus_init_irq(sbd, &proxy->irq);
512
513
if (!kvm_eventfds_enabled()) {
514
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
515
index XXXXXXX..XXXXXXX 100644
516
--- a/hw/virtio/virtio-pci.c
517
+++ b/hw/virtio/virtio-pci.c
518
@@ -XXX,XX +XXX,XX @@ static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size,
519
DeviceState *qdev = DEVICE(dev);
520
char virtio_bus_name[] = "virtio-bus";
521
522
- qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev,
523
- virtio_bus_name);
524
+ qbus_init(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev, virtio_bus_name);
525
}
526
527
static void virtio_pci_bus_class_init(ObjectClass *klass, void *data)
528
--
529
2.20.1
530
531
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