Nothing too exciting in this lot :-)

The following changes since commit ba0fa56bc06e563de68d2a2bf3ddb0cfea1be4f9:

Merge remote-tracking branch 'remotes/vivier/tags/q800-for-6.2-pull-request' into staging (2021-09-29 21:20:49 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210930

for you to fetch changes up to 1f4b2ec701b9d73d3fa7bb90c8b4376bc7d3c42b:

hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19 (2021-09-30 13:44:13 +0100)

* allwinner-h3: Switch to SMC as PSCI conduit

* arm: tcg: Adhere to SMCCC 1.3 section 5.2

* xlnx-zcu102, xlnx-versal-virt: Support BBRAM and eFUSE devices

* gdbstub related code cleanups

* Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML

* Use _init vs _new convention in bus creation function names

* sabrelite: Connect SPI flash CS line to GPIO3_19

Alexander Graf (2):

allwinner-h3: Switch to SMC as PSCI conduit

arm: tcg: Adhere to SMCCC 1.3 section 5.2

Peter Maydell (10):

configs: Don't include 32-bit-only GDB XML in aarch64 linux configs

target/arm: Fix coding style issues in gdbstub code in helper.c

target/arm: Move gdbstub related code out of helper.c

target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML

scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named()

ipack: Rename ipack_bus_new_inplace() to ipack_bus_init()

pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init()

qbus: Rename qbus_create_inplace() to qbus_init()

qbus: Rename qbus_create() to qbus_new()

ide: Rename ide_bus_new() to ide_bus_init()

Tong Ho (9):

hw/nvram: Introduce Xilinx eFuse QOM

hw/nvram: Introduce Xilinx Versal eFuse device

hw/nvram: Introduce Xilinx ZynqMP eFuse device

hw/nvram: Introduce Xilinx battery-backed ram

hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device

hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device

hw/arm: xlnx-zcu102: Add Xilinx BBRAM device

hw/arm: xlnx-zcu102: Add Xilinx eFUSE device

docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage

Xuzhou Cheng (1):

hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19

docs/system/arm/xlnx-versal-virt.rst | 49 ++

configs/targets/aarch64-linux-user.mak | 2 +-

configs/targets/aarch64-softmmu.mak | 2 +-

configs/targets/aarch64_be-linux-user.mak | 2 +-

configs/targets/arm-linux-user.mak | 2 +-

configs/targets/arm-softmmu.mak | 2 +-

configs/targets/armeb-linux-user.mak | 2 +-

include/hw/arm/xlnx-versal.h | 15 +

include/hw/arm/xlnx-zynqmp.h | 5 +

include/hw/ide/internal.h | 4 +-

include/hw/ipack/ipack.h | 8 +-

include/hw/nvram/xlnx-bbram.h | 54 ++

include/hw/nvram/xlnx-efuse.h | 132 +++++

include/hw/nvram/xlnx-versal-efuse.h | 68 +++

include/hw/nvram/xlnx-zynqmp-efuse.h | 44 ++

include/hw/pci/pci.h | 10 +-

include/hw/qdev-core.h | 6 +-

include/hw/scsi/scsi.h | 30 +-

target/arm/internals.h | 7 +

hw/arm/allwinner-h3.c | 2 +-

hw/arm/sabrelite.c | 2 +-

hw/arm/xlnx-versal-virt.c | 88 +++

hw/arm/xlnx-versal.c | 57 ++

hw/arm/xlnx-zcu102.c | 30 ++

hw/arm/xlnx-zynqmp.c | 49 ++

hw/audio/intel-hda.c | 2 +-

hw/block/fdc.c | 2 +-

hw/block/swim.c | 3 +-

hw/char/virtio-serial-bus.c | 4 +-

hw/core/bus.c | 13 +-

hw/core/sysbus.c | 10 +-

hw/gpio/bcm2835_gpio.c | 3 +-

hw/hyperv/vmbus.c | 2 +-

hw/i2c/core.c | 2 +-

hw/ide/ahci.c | 2 +-

hw/ide/cmd646.c | 2 +-

hw/ide/isa.c | 2 +-

hw/ide/macio.c | 2 +-

hw/ide/microdrive.c | 2 +-

hw/ide/mmio.c | 2 +-

hw/ide/piix.c | 2 +-

hw/ide/qdev.c | 4 +-

hw/ide/sii3112.c | 2 +-

hw/ide/via.c | 2 +-

hw/ipack/ipack.c | 10 +-

hw/ipack/tpci200.c | 4 +-

hw/isa/isa-bus.c | 2 +-

hw/misc/auxbus.c | 2 +-

hw/misc/mac_via.c | 4 +-

hw/misc/macio/cuda.c | 4 +-

hw/misc/macio/macio.c | 4 +-

hw/misc/macio/pmu.c | 4 +-

hw/nubus/nubus-bridge.c | 2 +-

hw/nvme/ctrl.c | 4 +-

hw/nvme/subsys.c | 3 +-

hw/nvram/xlnx-bbram.c | 545 +++++++++++++++++++

hw/nvram/xlnx-efuse-crc.c | 119 +++++

hw/nvram/xlnx-efuse.c | 280 ++++++++++

hw/nvram/xlnx-versal-efuse-cache.c | 114 ++++

hw/nvram/xlnx-versal-efuse-ctrl.c | 783 +++++++++++++++++++++++++++

hw/nvram/xlnx-zynqmp-efuse.c | 855 ++++++++++++++++++++++++++++++

hw/pci-host/raven.c | 4 +-

hw/pci-host/versatile.c | 6 +-

hw/pci/pci.c | 30 +-

hw/pci/pci_bridge.c | 4 +-

hw/ppc/spapr_vio.c | 2 +-

hw/s390x/ap-bridge.c | 2 +-

hw/s390x/css-bridge.c | 2 +-

hw/s390x/event-facility.c | 4 +-

hw/s390x/s390-pci-bus.c | 2 +-

hw/s390x/virtio-ccw.c | 3 +-

hw/scsi/esp-pci.c | 2 +-

hw/scsi/esp.c | 2 +-

hw/scsi/lsi53c895a.c | 2 +-

hw/scsi/megasas.c | 3 +-

hw/scsi/mptsas.c | 2 +-

hw/scsi/scsi-bus.c | 6 +-

hw/scsi/spapr_vscsi.c | 3 +-

hw/scsi/virtio-scsi.c | 4 +-

hw/scsi/vmw_pvscsi.c | 3 +-

hw/sd/allwinner-sdhost.c | 4 +-

hw/sd/bcm2835_sdhost.c | 4 +-

hw/sd/pl181.c | 3 +-

hw/sd/pxa2xx_mmci.c | 4 +-

hw/sd/sdhci.c | 3 +-

hw/sd/ssi-sd.c | 3 +-

hw/ssi/ssi.c | 2 +-

hw/usb/bus.c | 2 +-

hw/usb/dev-smartcard-reader.c | 3 +-

hw/usb/dev-storage-bot.c | 3 +-

hw/usb/dev-storage-classic.c | 4 +-

hw/usb/dev-uas.c | 3 +-

hw/virtio/virtio-mmio.c | 3 +-

hw/virtio/virtio-pci.c | 3 +-

hw/xen/xen-bus.c | 2 +-

hw/xen/xen-legacy-backend.c | 2 +-

target/arm/gdbstub.c | 154 ++++++

target/arm/gdbstub64.c | 140 +++++

target/arm/helper.c | 262 ---------

target/arm/psci.c | 35 +-

gdb-xml/arm-neon.xml | 2 -

gdb-xml/arm-vfp-sysregs.xml | 17 +

gdb-xml/arm-vfp.xml | 2 -

gdb-xml/arm-vfp3.xml | 2 -

hw/Kconfig | 2 +

hw/arm/Kconfig | 2 +

hw/nvram/Kconfig | 19 +

hw/nvram/meson.build | 8 +

108 files changed, 3806 insertions(+), 447 deletions(-)

create mode 100644 include/hw/nvram/xlnx-bbram.h

create mode 100644 include/hw/nvram/xlnx-efuse.h

create mode 100644 include/hw/nvram/xlnx-versal-efuse.h

create mode 100644 include/hw/nvram/xlnx-zynqmp-efuse.h

create mode 100644 hw/nvram/xlnx-bbram.c

create mode 100644 hw/nvram/xlnx-efuse-crc.c

create mode 100644 hw/nvram/xlnx-efuse.c

create mode 100644 hw/nvram/xlnx-versal-efuse-cache.c

create mode 100644 hw/nvram/xlnx-versal-efuse-ctrl.c

create mode 100644 hw/nvram/xlnx-zynqmp-efuse.c

create mode 100644 gdb-xml/arm-vfp-sysregs.xml

From: Tong Ho <tong.ho@xilinx.com>

Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM)

The command argument:

-drive if=pflash,index=2,...

Can be used to optionally connect the bbram to a backend

storage, such that field-programmed values in one

invocation can be made available to next invocation.

The backend storage must be a seekable binary file, and

its size must be 36 bytes or larger. A file with all

binary 0's is a 'blank'.

Signed-off-by: Tong Ho <tong.ho@xilinx.com>

Message-id: 20210917052400.1249094-8-tong.ho@xilinx.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

include/hw/arm/xlnx-zynqmp.h | 2 ++

hw/arm/xlnx-zcu102.c | 15 +++++++++++++++

hw/arm/xlnx-zynqmp.c | 20 ++++++++++++++++++++

hw/Kconfig | 1 +

4 files changed, 38 insertions(+)

diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h

--- a/include/hw/arm/xlnx-zynqmp.h

+++ b/include/hw/arm/xlnx-zynqmp.h

#include "net/can_emu.h"

#include "hw/dma/xlnx_csu_dma.h"

+#include "hw/nvram/xlnx-bbram.h"

#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"

OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)

@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {

MemoryRegion *ddr_ram;

MemoryRegion ddr_ram_low, ddr_ram_high;

+ XlnxBBRam bbram;

MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];

diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/xlnx-zcu102.c

+++ b/hw/arm/xlnx-zcu102.c

@@ -XXX,XX +XXX,XX @@ static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt)

}

}

+static void bbram_attach_drive(XlnxBBRam *dev)

+{

+ DriveInfo *dinfo;

+ BlockBackend *blk;

+

+ dinfo = drive_get_by_index(IF_PFLASH, 2);

+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;

+ if (blk) {

+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);

+ }

+}

+

static void xlnx_zcu102_init(MachineState *machine)

{

XlnxZCU102 *s = ZCU102_MACHINE(machine);

@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)

qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);

+ /* Attach bbram backend, if given */

+ bbram_attach_drive(&s->soc.bbram);

+

/* Create and plug in the SD cards */

for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {

BusState *bus;

diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/xlnx-zynqmp.c

+++ b/hw/arm/xlnx-zynqmp.c

@@ -XXX,XX +XXX,XX @@

#define RTC_ADDR 0xffa60000

#define RTC_IRQ 26

+#define BBRAM_ADDR 0xffcd0000

+#define BBRAM_IRQ 11

+

#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */

static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {

@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,

qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);

}

+static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)

+{

+ SysBusDevice *sbd;

+

+ object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram,

+ sizeof(s->bbram), TYPE_XLNX_BBRAM,

+ &error_fatal,

+ "crc-zpads", "1",

+ NULL);

+ sbd = SYS_BUS_DEVICE(&s->bbram);

+

+ sysbus_realize(sbd, &error_fatal);

+ sysbus_mmio_map(sbd, 0, BBRAM_ADDR);

+ sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);

+}

+

static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)

{

static const struct UnimpInfo {

@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)

sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);

sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);

+ xlnx_zynqmp_create_bbram(s, gic_spi);

xlnx_zynqmp_create_unimp_mmio(s);

for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {

diff --git a/hw/Kconfig b/hw/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/Kconfig

+++ b/hw/Kconfig

@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP

select REGISTER

select CAN_BUS

select PTIMER

+ select XLNX_BBRAM

2.20.1

Currently we send VFP XML which includes D0..D15 or D0..D31, plus

FPSID, FPSCR and FPEXC. The upstream GDB tolerates this, but its

definition of this XML feature does not include FPSID or FPEXC. In

particular, for M-profile cores there are no FPSID or FPEXC

registers, so advertising those is wrong.

Move FPSID and FPEXC into their own bit of XML which we only send for

A and R profile cores. This brings our definition of the XML

org.gnu.gdb.arm.vfp feature into line with GDB's own (at least for

non-Neon cores...) and means we don't claim to have FPSID and FPEXC

on M-profile.

(It seems unlikely to me that any gdbstub users really care about

being able to look at FPEXC and FPSID; but we've supplied them to gdb

for a decade and it's not hard to keep doing so.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210921162901.17508-5-peter.maydell@linaro.org

---

configs/targets/aarch64-softmmu.mak | 2 +-

configs/targets/arm-linux-user.mak | 2 +-

configs/targets/arm-softmmu.mak | 2 +-

configs/targets/armeb-linux-user.mak | 2 +-

target/arm/gdbstub.c | 56 ++++++++++++++++++++--------

gdb-xml/arm-neon.xml | 2 -

gdb-xml/arm-vfp-sysregs.xml | 17 +++++++++

gdb-xml/arm-vfp.xml | 2 -

gdb-xml/arm-vfp3.xml | 2 -

9 files changed, 61 insertions(+), 26 deletions(-)

create mode 100644 gdb-xml/arm-vfp-sysregs.xml

diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak

--- a/configs/targets/aarch64-softmmu.mak

+++ b/configs/targets/aarch64-softmmu.mak

@@ -XXX,XX +XXX,XX @@

TARGET_ARCH=aarch64

TARGET_BASE_ARCH=arm

TARGET_SUPPORTS_MTTCG=y

-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml

+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml

TARGET_NEED_FDT=y

diff --git a/configs/targets/arm-linux-user.mak b/configs/targets/arm-linux-user.mak

index XXXXXXX..XXXXXXX 100644

--- a/configs/targets/arm-linux-user.mak

+++ b/configs/targets/arm-linux-user.mak

@@ -XXX,XX +XXX,XX @@

TARGET_ARCH=arm

TARGET_SYSTBL_ABI=common,oabi

TARGET_SYSTBL=syscall.tbl

-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml

+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml

TARGET_HAS_BFLT=y

CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y

diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.mak

index XXXXXXX..XXXXXXX 100644

--- a/configs/targets/arm-softmmu.mak

+++ b/configs/targets/arm-softmmu.mak

@@ -XXX,XX +XXX,XX @@

TARGET_ARCH=arm

TARGET_SUPPORTS_MTTCG=y

-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml

+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml

TARGET_NEED_FDT=y

diff --git a/configs/targets/armeb-linux-user.mak b/configs/targets/armeb-linux-user.mak

index XXXXXXX..XXXXXXX 100644

--- a/configs/targets/armeb-linux-user.mak

+++ b/configs/targets/armeb-linux-user.mak

@@ -XXX,XX +XXX,XX @@ TARGET_ARCH=arm

TARGET_SYSTBL_ABI=common,oabi

TARGET_SYSTBL=syscall.tbl

TARGET_WORDS_BIGENDIAN=y

-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml

+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml

TARGET_HAS_BFLT=y

CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y

diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/gdbstub.c

+++ b/target/arm/gdbstub.c

@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)

}

switch (reg - nregs) {

case 0:

- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);

- case 1:

return gdb_get_reg32(buf, vfp_get_fpscr(env));

- case 2:

- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);

}

@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)

}

}

switch (reg - nregs) {

+ case 0:

+ vfp_set_fpscr(env, ldl_p(buf));

+ return 4;

+ }

+ return 0;

+static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)

+{

+ switch (reg) {

+ case 0:

+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);

+ case 1:

+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);

+ }

+ return 0;

+}

+static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)

+{

+ switch (reg) {

case 0:

env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);

return 4;

case 1:

- vfp_set_fpscr(env, ldl_p(buf));

- return 4;

- case 2:

env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);

return 4;

}

@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)

34, "aarch64-fpu.xml", 0);

}

#endif

- } else if (arm_feature(env, ARM_FEATURE_NEON)) {

- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,

- 51, "arm-neon.xml", 0);

- } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {

- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,

- 35, "arm-vfp3.xml", 0);

- } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {

- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,

- 19, "arm-vfp.xml", 0);

+ } else {

+ if (arm_feature(env, ARM_FEATURE_NEON)) {

+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,

+ 49, "arm-neon.xml", 0);

+ } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {

+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,

+ 33, "arm-vfp3.xml", 0);

+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {

+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,

+ 17, "arm-vfp.xml", 0);

+ }

+ if (!arm_feature(env, ARM_FEATURE_M)) {

+ /*

+ * A and R profile have FP sysregs FPEXC and FPSID that we

+ * expose to gdb.

+ */

+ gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_sysreg,

+ 2, "arm-vfp-sysregs.xml", 0);

+ }

}

gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,

arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),

diff --git a/gdb-xml/arm-neon.xml b/gdb-xml/arm-neon.xml

index XXXXXXX..XXXXXXX 100644

--- a/gdb-xml/arm-neon.xml

+++ b/gdb-xml/arm-neon.xml

@@ -XXX,XX +XXX,XX @@

<reg name="q14" bitsize="128" type="neon_q"/>

<reg name="q15" bitsize="128" type="neon_q"/>

- <reg name="fpsid" bitsize="32" type="int" group="float"/>

<reg name="fpscr" bitsize="32" type="int" group="float"/>

- <reg name="fpexc" bitsize="32" type="int" group="float"/>

</feature>

diff --git a/gdb-xml/arm-vfp-sysregs.xml b/gdb-xml/arm-vfp-sysregs.xml

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/gdb-xml/arm-vfp-sysregs.xml

@@ -XXX,XX +XXX,XX @@

+<?xml version="1.0"?>

+<!-- Copyright (C) 2021 Linaro Ltd.

+

+ Copying and distribution of this file, with or without modification,

+ are permitted in any medium without royalty provided the copyright

+ notice and this notice are preserved.

+

+ These are A/R profile VFP system registers. Debugger users probably

+ don't really care about these, but because we used to (incorrectly)

+ provide them to gdb in the org.gnu.gdb.arm.vfp XML we continue

+ to do so via this separate XML.

+ -->

+<!DOCTYPE feature SYSTEM "gdb-target.dtd">

+<feature name="org.qemu.gdb.arm.vfp-sysregs">

+ <reg name="fpsid" bitsize="32" type="int" group="float"/>

+ <reg name="fpexc" bitsize="32" type="int" group="float"/>

+</feature>

diff --git a/gdb-xml/arm-vfp.xml b/gdb-xml/arm-vfp.xml

index XXXXXXX..XXXXXXX 100644

--- a/gdb-xml/arm-vfp.xml

+++ b/gdb-xml/arm-vfp.xml

@@ -XXX,XX +XXX,XX @@

<reg name="d14" bitsize="64" type="float"/>

<reg name="d15" bitsize="64" type="float"/>

- <reg name="fpsid" bitsize="32" type="int" group="float"/>

<reg name="fpscr" bitsize="32" type="int" group="float"/>

- <reg name="fpexc" bitsize="32" type="int" group="float"/>

</feature>

diff --git a/gdb-xml/arm-vfp3.xml b/gdb-xml/arm-vfp3.xml

index XXXXXXX..XXXXXXX 100644

--- a/gdb-xml/arm-vfp3.xml

+++ b/gdb-xml/arm-vfp3.xml

@@ -XXX,XX +XXX,XX @@

<reg name="d30" bitsize="64" type="float"/>

<reg name="d31" bitsize="64" type="float"/>

- <reg name="fpsid" bitsize="32" type="int" group="float"/>

<reg name="fpscr" bitsize="32" type="int" group="float"/>

- <reg name="fpexc" bitsize="32" type="int" group="float"/>

</feature>

2.20.1

Currently helper.c includes some code which is part of the arm

target's gdbstub support. This code has a better home: in gdbstub.c

and gdbstub64.c. Move it there.

Because aarch64_fpu_gdb_get_reg() and aarch64_fpu_gdb_set_reg() move

into gdbstub64.c, this means that they're now compiled only for

TARGET_AARCH64 rather than always. That is the only case when they

would ever be used, but it does mean that the ifdef in

arm_cpu_register_gdb_regs_for_features() needs to be adjusted to

match.

target/arm/internals.h | 7 ++

target/arm/gdbstub.c | 130 ++++++++++++++++++++

target/arm/gdbstub64.c | 140 +++++++++++++++++++++

target/arm/helper.c | 271 -----------------------------------------

4 files changed, 277 insertions(+), 271 deletions(-)

@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)

return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);

}

+#ifdef TARGET_AARCH64

+int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);

+int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);

+int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);

+int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);

+#endif

#endif

diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/gdbstub.c

+++ b/target/arm/gdbstub.c

@@ -XXX,XX +XXX,XX @@

*/

#include "qemu/osdep.h"

#include "cpu.h"

+#include "internals.h"

#include "exec/gdbstub.h"

typedef struct RegisterSysregXmlParam {

@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)

return 0;

}

+static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)

+{

+ ARMCPU *cpu = env_archcpu(env);

+ int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;

+ /* VFP data registers are always little-endian. */

+ if (reg < nregs) {

+ return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));

+ if (arm_feature(env, ARM_FEATURE_NEON)) {

+ /* Aliases for Q regs. */

+ nregs += 16;

+ if (reg < nregs) {

+ uint64_t *q = aa32_vfp_qreg(env, reg - 32);

+ return gdb_get_reg128(buf, q[0], q[1]);

+ }

+ switch (reg - nregs) {

+ case 0:

+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);

+ case 1:

+ return gdb_get_reg32(buf, vfp_get_fpscr(env));

+ case 2:

+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);

+ }

+ return 0;

+static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)

+ ARMCPU *cpu = env_archcpu(env);

+ int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;

+ if (reg < nregs) {

+ *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);

+ return 8;

+ }

+ if (arm_feature(env, ARM_FEATURE_NEON)) {

+ nregs += 16;

+ if (reg < nregs) {

+ uint64_t *q = aa32_vfp_qreg(env, reg - 32);

+ q[0] = ldq_le_p(buf);

+ q[1] = ldq_le_p(buf + 8);

+ return 16;

+ }

+ }

+ switch (reg - nregs) {

+ case 0:

+ env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);

+ return 4;

+ case 1:

+ vfp_set_fpscr(env, ldl_p(buf));

+ return 4;

+ case 2:

+ env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);

+ return 4;

+ }

+ return 0;

+/**

+ * arm_get/set_gdb_*: get/set a gdb register

+ * @env: the CPU state

+ * @buf: a buffer to copy to/from

+ * @reg: register number (offset from start of group)

+ *

+ * We return the number of bytes copied

+ */

+static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)

+{

+ ARMCPU *cpu = env_archcpu(env);

+ const ARMCPRegInfo *ri;

+ uint32_t key;

+

+ key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];

+ ri = get_arm_cp_reginfo(cpu->cp_regs, key);

+ if (ri) {

+ if (cpreg_field_is_64bit(ri)) {

+ return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));

+ } else {

+ return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));

+ }

+ }

+ return 0;

+static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)

+{

+ return 0;

+}

+

static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,

ARMCPRegInfo *ri, uint32_t ri_key,

int bitsize, int regnum)

@@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)

}

return NULL;

+

+void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)

+{

+ CPUState *cs = CPU(cpu);

+ CPUARMState *env = &cpu->env;

+

+ if (arm_feature(env, ARM_FEATURE_AARCH64)) {

+ /*

+ * The lower part of each SVE register aliases to the FPU

+ * registers so we don't need to include both.

+ */

+#ifdef TARGET_AARCH64

+ if (isar_feature_aa64_sve(&cpu->isar)) {

+ gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,

+ arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),

+ "sve-registers.xml", 0);

+ } else {

+ gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,

+ aarch64_fpu_gdb_set_reg,

+ 34, "aarch64-fpu.xml", 0);

+ }

+#endif

+ } else if (arm_feature(env, ARM_FEATURE_NEON)) {

+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,

+ 51, "arm-neon.xml", 0);

+ } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {

+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,

+ 35, "arm-vfp3.xml", 0);

+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {

+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,

+ 19, "arm-vfp.xml", 0);

+ }

+ gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,

+ arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),

+ "system-registers.xml", 0);

+

+}

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/gdbstub64.c

+++ b/target/arm/gdbstub64.c

@@ -XXX,XX +XXX,XX @@

* License along with this library; if not, see <http://www.gnu.org/licenses/>.

*/

#include "qemu/osdep.h"

+#include "qemu/log.h"

#include "cpu.h"

+#include "internals.h"

#include "exec/gdbstub.h"

int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)

@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)

/* Unknown register. */

return 0;

}

+

+int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)

+{

+ switch (reg) {

+ case 0 ... 31:

+ {

+ /* 128 bit FP register - quads are in LE order */

+ uint64_t *q = aa64_vfp_qreg(env, reg);

+ return gdb_get_reg128(buf, q[1], q[0]);

+ }

+ case 32:

+ /* FPSR */

+ return gdb_get_reg32(buf, vfp_get_fpsr(env));

+ case 33:

+ /* FPCR */

+ return gdb_get_reg32(buf, vfp_get_fpcr(env));

+ default:

+ return 0;

+ }

+}

+

+int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)

+{

+ switch (reg) {

+ case 0 ... 31:

+ /* 128 bit FP register */

+ {

+ uint64_t *q = aa64_vfp_qreg(env, reg);

+ q[0] = ldq_le_p(buf);

+ q[1] = ldq_le_p(buf + 8);

+ return 16;

+ }

+ case 32:

+ /* FPSR */

+ vfp_set_fpsr(env, ldl_p(buf));

+ return 4;

+ case 33:

+ /* FPCR */

+ vfp_set_fpcr(env, ldl_p(buf));

+ return 4;

+ default:

+ return 0;

+ }

+}

+

+int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)

+{

+ ARMCPU *cpu = env_archcpu(env);

+

+ switch (reg) {

+ /* The first 32 registers are the zregs */

+ case 0 ... 31:

+ {

+ int vq, len = 0;

+ for (vq = 0; vq < cpu->sve_max_vq; vq++) {

+ len += gdb_get_reg128(buf,

+ env->vfp.zregs[reg].d[vq * 2 + 1],

+ env->vfp.zregs[reg].d[vq * 2]);

+ }

+ return len;

+ }

+ case 32:

+ return gdb_get_reg32(buf, vfp_get_fpsr(env));

+ case 33:

+ return gdb_get_reg32(buf, vfp_get_fpcr(env));

+ /* then 16 predicates and the ffr */

+ case 34 ... 50:

+ {

+ int preg = reg - 34;

+ int vq, len = 0;

+ for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {

+ len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);

+ }

+ return len;

+ }

+ case 51:

+ {

+ /*

+ * We report in Vector Granules (VG) which is 64bit in a Z reg

+ * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.

+ */

+ int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;

+ return gdb_get_reg64(buf, vq * 2);

+ }

+ default:

+ /* gdbstub asked for something out our range */

+ qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);

+ break;

+ }

+

+ return 0;

+}

+

+int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)

+{

+ ARMCPU *cpu = env_archcpu(env);

+

+ /* The first 32 registers are the zregs */

+ switch (reg) {

+ /* The first 32 registers are the zregs */

+ case 0 ... 31:

+ {

+ int vq, len = 0;

+ uint64_t *p = (uint64_t *) buf;

+ for (vq = 0; vq < cpu->sve_max_vq; vq++) {

+ env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;

+ env->vfp.zregs[reg].d[vq * 2] = *p++;

+ len += 16;

+ }

+ return len;

+ }

+ case 32:

+ vfp_set_fpsr(env, *(uint32_t *)buf);

+ return 4;

+ case 33:

+ vfp_set_fpcr(env, *(uint32_t *)buf);

+ return 4;

+ case 34 ... 50:

+ {

+ int preg = reg - 34;

+ int vq, len = 0;

+ uint64_t *p = (uint64_t *) buf;

+ for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {

+ env->vfp.pregs[preg].p[vq / 4] = *p++;

+ len += 8;

+ }

+ return len;

+ }

+ case 51:

+ /* cannot set vg via gdbstub */

+ return 0;

+ default:

+ /* gdbstub asked for something out our range */

+ break;

+ }

+

+ return 0;

+}

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@

#include "trace.h"

#include "cpu.h"

#include "internals.h"

-#include "exec/gdbstub.h"

#include "exec/helper-proto.h"

#include "qemu/host-utils.h"

#include "qemu/main-loop.h"

@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,

static void switch_mode(CPUARMState *env, int mode);

static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);

-static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)

- ARMCPU *cpu = env_archcpu(env);

- int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;

- /* VFP data registers are always little-endian. */

- if (reg < nregs) {

- return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));

- if (arm_feature(env, ARM_FEATURE_NEON)) {

- /* Aliases for Q regs. */

- nregs += 16;

- if (reg < nregs) {

- uint64_t *q = aa32_vfp_qreg(env, reg - 32);

- return gdb_get_reg128(buf, q[0], q[1]);

- }

- switch (reg - nregs) {

- case 0:

- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);

- case 1:

- return gdb_get_reg32(buf, vfp_get_fpscr(env));

- case 2:

- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);

- return 0;

-static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)

- ARMCPU *cpu = env_archcpu(env);

- int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;

- if (reg < nregs) {

- *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);

- return 8;

- }

- if (arm_feature(env, ARM_FEATURE_NEON)) {

- nregs += 16;

- if (reg < nregs) {

- uint64_t *q = aa32_vfp_qreg(env, reg - 32);

- q[0] = ldq_le_p(buf);

- q[1] = ldq_le_p(buf + 8);

- return 16;

- }

- }

- switch (reg - nregs) {

- case 0:

- env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);

- return 4;

- case 1:

- vfp_set_fpscr(env, ldl_p(buf));

- return 4;

- case 2:

- env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);

- return 4;

- }

- return 0;

-static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)

- switch (reg) {

- case 0 ... 31:

- {

- /* 128 bit FP register - quads are in LE order */

- uint64_t *q = aa64_vfp_qreg(env, reg);

- return gdb_get_reg128(buf, q[1], q[0]);

- }

- case 32:

- /* FPSR */

- return gdb_get_reg32(buf, vfp_get_fpsr(env));

- case 33:

- /* FPCR */

- return gdb_get_reg32(buf, vfp_get_fpcr(env));

- default:

- return 0;

- }

-static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)

-{

- switch (reg) {

- case 0 ... 31:

- /* 128 bit FP register */

- {

- uint64_t *q = aa64_vfp_qreg(env, reg);

- q[0] = ldq_le_p(buf);

- q[1] = ldq_le_p(buf + 8);

- return 16;

- }

- case 32:

- /* FPSR */

- vfp_set_fpsr(env, ldl_p(buf));

- return 4;

- case 33:

- /* FPCR */

- vfp_set_fpcr(env, ldl_p(buf));

- return 4;

- default:

- return 0;

- }

-}

-

static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)

{

assert(ri->fieldoffset);

@@ -XXX,XX +XXX,XX @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,

}

}

-/**

- * arm_get/set_gdb_*: get/set a gdb register

- * @env: the CPU state

- * @buf: a buffer to copy to/from

- * @reg: register number (offset from start of group)

- *

- * We return the number of bytes copied

- */

-

-static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)

-{

- ARMCPU *cpu = env_archcpu(env);

- const ARMCPRegInfo *ri;

- uint32_t key;

-

- key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];

- ri = get_arm_cp_reginfo(cpu->cp_regs, key);

- if (ri) {

- if (cpreg_field_is_64bit(ri)) {

- return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));

- } else {

- return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));

- }

- }

- return 0;

-}

-

-static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)

-{

- return 0;

-}

-

-#ifdef TARGET_AARCH64

-static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)

-{

- ARMCPU *cpu = env_archcpu(env);

-

- switch (reg) {

- /* The first 32 registers are the zregs */

- case 0 ... 31:

- {

- int vq, len = 0;

- for (vq = 0; vq < cpu->sve_max_vq; vq++) {

- len += gdb_get_reg128(buf,

- env->vfp.zregs[reg].d[vq * 2 + 1],

- env->vfp.zregs[reg].d[vq * 2]);

- }

- return len;

- }

- case 32:

- return gdb_get_reg32(buf, vfp_get_fpsr(env));

- case 33:

- return gdb_get_reg32(buf, vfp_get_fpcr(env));

- /* then 16 predicates and the ffr */

- case 34 ... 50:

- {

- int preg = reg - 34;

- int vq, len = 0;

- for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {

- len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);

- }

- return len;

- }

- case 51:

- {

- /*

- * We report in Vector Granules (VG) which is 64bit in a Z reg

- * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.

- */

- int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;

- return gdb_get_reg64(buf, vq * 2);

- }

- default:

- /* gdbstub asked for something out our range */

- qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);

- break;

- }

-

- return 0;

-}

-

-static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)

-{

- ARMCPU *cpu = env_archcpu(env);

-

- /* The first 32 registers are the zregs */

- switch (reg) {

- /* The first 32 registers are the zregs */

- case 0 ... 31:

- {

- int vq, len = 0;

- uint64_t *p = (uint64_t *) buf;

- for (vq = 0; vq < cpu->sve_max_vq; vq++) {

- env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;

- env->vfp.zregs[reg].d[vq * 2] = *p++;

- len += 16;

- }

- return len;

- }

- case 32:

- vfp_set_fpsr(env, *(uint32_t *)buf);

- return 4;

- case 33:

- vfp_set_fpcr(env, *(uint32_t *)buf);

- return 4;

- case 34 ... 50:

- {

- int preg = reg - 34;

- int vq, len = 0;

- uint64_t *p = (uint64_t *) buf;

- for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {

- env->vfp.pregs[preg].p[vq / 4] = *p++;

- len += 8;

- }

- return len;

- }

- case 51:

- /* cannot set vg via gdbstub */

- return 0;

- default:

- /* gdbstub asked for something out our range */

- break;

- }

-

- return 0;

-}

-#endif /* TARGET_AARCH64 */

-

static bool raw_accessors_invalid(const ARMCPRegInfo *ri)

{

/* Return true if the regdef would cause an assertion if you called

@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)

#endif

}

-void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)

-{

- CPUState *cs = CPU(cpu);

- CPUARMState *env = &cpu->env;

-

- if (arm_feature(env, ARM_FEATURE_AARCH64)) {

- /*

- * The lower part of each SVE register aliases to the FPU

- * registers so we don't need to include both.

- */

-#ifdef TARGET_AARCH64

- if (isar_feature_aa64_sve(&cpu->isar)) {

- gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,

- arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),

- "sve-registers.xml", 0);

- } else

-#endif

- {

- gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,

- aarch64_fpu_gdb_set_reg,

- 34, "aarch64-fpu.xml", 0);

- }

- } else if (arm_feature(env, ARM_FEATURE_NEON)) {

- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,

- 51, "arm-neon.xml", 0);

- } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {

- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,

- 35, "arm-vfp3.xml", 0);

- } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {

- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,

- 19, "arm-vfp.xml", 0);

- }

- gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,