[PULL 00/22] target-arm queue
[PULL 00/34] target-arm queue
1
Nothing too exciting in this lot :-)
1
Some arm patches; my to-review queue is by no means empty, but
2
this is a big enough set of patches to be getting on with...
2
3
3
The following changes since commit ba0fa56bc06e563de68d2a2bf3ddb0cfea1be4f9:
4
-- PMM
4
5
5
Merge remote-tracking branch 'remotes/vivier/tags/q800-for-6.2-pull-request' into staging (2021-09-29 21:20:49 +0100)
6
The following changes since commit cb9c6a8e5ad6a1f0ce164d352e3102df46986e22:
7
8
.gitlab-ci.d/windows: Work-around timeout and OpenGL problems of the MSYS2 jobs (2023-01-04 18:58:33 +0000)
6
9
7
are available in the Git repository at:
10
are available in the Git repository at:
8
11
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210930
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230105
10
13
11
for you to fetch changes up to 1f4b2ec701b9d73d3fa7bb90c8b4376bc7d3c42b:
14
for you to fetch changes up to 93c9678de9dc7d2e68f9e8477da072bac30ef132:
12
15
13
hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19 (2021-09-30 13:44:13 +0100)
16
hw/net: Fix read of uninitialized memory in imx_fec. (2023-01-05 15:33:00 +0000)
14
17
15
----------------------------------------------------------------
18
----------------------------------------------------------------
16
target-arm queue:
19
target-arm queue:
17
* allwinner-h3: Switch to SMC as PSCI conduit
20
* Implement AArch32 ARMv8-R support
18
* arm: tcg: Adhere to SMCCC 1.3 section 5.2
21
* Add Cortex-R52 CPU
19
* xlnx-zcu102, xlnx-versal-virt: Support BBRAM and eFUSE devices
22
* fix handling of HLT semihosting in system mode
20
* gdbstub related code cleanups
23
* hw/timer/ixm_epit: cleanup and fix bug in compare handling
21
* Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML
24
* target/arm: Coding style fixes
22
* Use _init vs _new convention in bus creation function names
25
* target/arm: Clean up includes
23
* sabrelite: Connect SPI flash CS line to GPIO3_19
26
* nseries: minor code cleanups
27
* target/arm: align exposed ID registers with Linux
28
* hw/arm/smmu-common: remove unnecessary inlines
29
* i.MX7D: Handle GPT timers
30
* i.MX7D: Connect IRQs to GPIO devices
31
* i.MX6UL: Add a specific GPT timer instance
32
* hw/net: Fix read of uninitialized memory in imx_fec
24
33
25
----------------------------------------------------------------
34
----------------------------------------------------------------
26
Alexander Graf (2):
35
Alex Bennée (1):
27
allwinner-h3: Switch to SMC as PSCI conduit
36
target/arm: fix handling of HLT semihosting in system mode
28
arm: tcg: Adhere to SMCCC 1.3 section 5.2
29
37
30
Peter Maydell (10):
38
Axel Heider (8):
31
configs: Don't include 32-bit-only GDB XML in aarch64 linux configs
39
hw/timer/imx_epit: improve comments
32
target/arm: Fix coding style issues in gdbstub code in helper.c
40
hw/timer/imx_epit: cleanup CR defines
33
target/arm: Move gdbstub related code out of helper.c
41
hw/timer/imx_epit: define SR_OCIF
34
target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML
42
hw/timer/imx_epit: update interrupt state on CR write access
35
scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named()
43
hw/timer/imx_epit: hard reset initializes CR with 0
36
ipack: Rename ipack_bus_new_inplace() to ipack_bus_init()
44
hw/timer/imx_epit: factor out register write handlers
37
pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init()
45
hw/timer/imx_epit: remove explicit fields cnt and freq
38
qbus: Rename qbus_create_inplace() to qbus_init()
46
hw/timer/imx_epit: fix compare timer handling
39
qbus: Rename qbus_create() to qbus_new()
40
ide: Rename ide_bus_new() to ide_bus_init()
41
47
42
Tong Ho (9):
48
Claudio Fontana (1):
43
hw/nvram: Introduce Xilinx eFuse QOM
49
target/arm: cleanup cpu includes
44
hw/nvram: Introduce Xilinx Versal eFuse device
45
hw/nvram: Introduce Xilinx ZynqMP eFuse device
46
hw/nvram: Introduce Xilinx battery-backed ram
47
hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device
48
hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device
49
hw/arm: xlnx-zcu102: Add Xilinx BBRAM device
50
hw/arm: xlnx-zcu102: Add Xilinx eFUSE device
51
docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage
52
50
53
Xuzhou Cheng (1):
51
Fabiano Rosas (5):
54
hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19
52
target/arm: Fix checkpatch comment style warnings in helper.c
53
target/arm: Fix checkpatch space errors in helper.c
54
target/arm: Fix checkpatch brace errors in helper.c
55
target/arm: Remove unused includes from m_helper.c
56
target/arm: Remove unused includes from helper.c
55
57
56
docs/system/arm/xlnx-versal-virt.rst | 49 ++
58
Jean-Christophe Dubois (4):
57
configs/targets/aarch64-linux-user.mak | 2 +-
59
i.MX7D: Connect GPT timers to IRQ
58
configs/targets/aarch64-softmmu.mak | 2 +-
60
i.MX7D: Compute clock frequency for the fixed frequency clocks.
59
configs/targets/aarch64_be-linux-user.mak | 2 +-
61
i.MX6UL: Add a specific GPT timer instance for the i.MX6UL
60
configs/targets/arm-linux-user.mak | 2 +-
62
i.MX7D: Connect IRQs to GPIO devices.
61
configs/targets/arm-softmmu.mak | 2 +-
62
configs/targets/armeb-linux-user.mak | 2 +-
63
include/hw/arm/xlnx-versal.h | 15 +
64
include/hw/arm/xlnx-zynqmp.h | 5 +
65
include/hw/ide/internal.h | 4 +-
66
include/hw/ipack/ipack.h | 8 +-
67
include/hw/nvram/xlnx-bbram.h | 54 ++
68
include/hw/nvram/xlnx-efuse.h | 132 +++++
69
include/hw/nvram/xlnx-versal-efuse.h | 68 +++
70
include/hw/nvram/xlnx-zynqmp-efuse.h | 44 ++
71
include/hw/pci/pci.h | 10 +-
72
include/hw/qdev-core.h | 6 +-
73
include/hw/scsi/scsi.h | 30 +-
74
target/arm/internals.h | 7 +
75
hw/arm/allwinner-h3.c | 2 +-
76
hw/arm/sabrelite.c | 2 +-
77
hw/arm/xlnx-versal-virt.c | 88 +++
78
hw/arm/xlnx-versal.c | 57 ++
79
hw/arm/xlnx-zcu102.c | 30 ++
80
hw/arm/xlnx-zynqmp.c | 49 ++
81
hw/audio/intel-hda.c | 2 +-
82
hw/block/fdc.c | 2 +-
83
hw/block/swim.c | 3 +-
84
hw/char/virtio-serial-bus.c | 4 +-
85
hw/core/bus.c | 13 +-
86
hw/core/sysbus.c | 10 +-
87
hw/gpio/bcm2835_gpio.c | 3 +-
88
hw/hyperv/vmbus.c | 2 +-
89
hw/i2c/core.c | 2 +-
90
hw/ide/ahci.c | 2 +-
91
hw/ide/cmd646.c | 2 +-
92
hw/ide/isa.c | 2 +-
93
hw/ide/macio.c | 2 +-
94
hw/ide/microdrive.c | 2 +-
95
hw/ide/mmio.c | 2 +-
96
hw/ide/piix.c | 2 +-
97
hw/ide/qdev.c | 4 +-
98
hw/ide/sii3112.c | 2 +-
99
hw/ide/via.c | 2 +-
100
hw/ipack/ipack.c | 10 +-
101
hw/ipack/tpci200.c | 4 +-
102
hw/isa/isa-bus.c | 2 +-
103
hw/misc/auxbus.c | 2 +-
104
hw/misc/mac_via.c | 4 +-
105
hw/misc/macio/cuda.c | 4 +-
106
hw/misc/macio/macio.c | 4 +-
107
hw/misc/macio/pmu.c | 4 +-
108
hw/nubus/nubus-bridge.c | 2 +-
109
hw/nvme/ctrl.c | 4 +-
110
hw/nvme/subsys.c | 3 +-
111
hw/nvram/xlnx-bbram.c | 545 +++++++++++++++++++
112
hw/nvram/xlnx-efuse-crc.c | 119 +++++
113
hw/nvram/xlnx-efuse.c | 280 ++++++++++
114
hw/nvram/xlnx-versal-efuse-cache.c | 114 ++++
115
hw/nvram/xlnx-versal-efuse-ctrl.c | 783 +++++++++++++++++++++++++++
116
hw/nvram/xlnx-zynqmp-efuse.c | 855 ++++++++++++++++++++++++++++++
117
hw/pci-host/raven.c | 4 +-
118
hw/pci-host/versatile.c | 6 +-
119
hw/pci/pci.c | 30 +-
120
hw/pci/pci_bridge.c | 4 +-
121
hw/ppc/spapr_vio.c | 2 +-
122
hw/s390x/ap-bridge.c | 2 +-
123
hw/s390x/css-bridge.c | 2 +-
124
hw/s390x/event-facility.c | 4 +-
125
hw/s390x/s390-pci-bus.c | 2 +-
126
hw/s390x/virtio-ccw.c | 3 +-
127
hw/scsi/esp-pci.c | 2 +-
128
hw/scsi/esp.c | 2 +-
129
hw/scsi/lsi53c895a.c | 2 +-
130
hw/scsi/megasas.c | 3 +-
131
hw/scsi/mptsas.c | 2 +-
132
hw/scsi/scsi-bus.c | 6 +-
133
hw/scsi/spapr_vscsi.c | 3 +-
134
hw/scsi/virtio-scsi.c | 4 +-
135
hw/scsi/vmw_pvscsi.c | 3 +-
136
hw/sd/allwinner-sdhost.c | 4 +-
137
hw/sd/bcm2835_sdhost.c | 4 +-
138
hw/sd/pl181.c | 3 +-
139
hw/sd/pxa2xx_mmci.c | 4 +-
140
hw/sd/sdhci.c | 3 +-
141
hw/sd/ssi-sd.c | 3 +-
142
hw/ssi/ssi.c | 2 +-
143
hw/usb/bus.c | 2 +-
144
hw/usb/dev-smartcard-reader.c | 3 +-
145
hw/usb/dev-storage-bot.c | 3 +-
146
hw/usb/dev-storage-classic.c | 4 +-
147
hw/usb/dev-uas.c | 3 +-
148
hw/virtio/virtio-mmio.c | 3 +-
149
hw/virtio/virtio-pci.c | 3 +-
150
hw/xen/xen-bus.c | 2 +-
151
hw/xen/xen-legacy-backend.c | 2 +-
152
target/arm/gdbstub.c | 154 ++++++
153
target/arm/gdbstub64.c | 140 +++++
154
target/arm/helper.c | 262 ---------
155
target/arm/psci.c | 35 +-
156
gdb-xml/arm-neon.xml | 2 -
157
gdb-xml/arm-vfp-sysregs.xml | 17 +
158
gdb-xml/arm-vfp.xml | 2 -
159
gdb-xml/arm-vfp3.xml | 2 -
160
hw/Kconfig | 2 +
161
hw/arm/Kconfig | 2 +
162
hw/nvram/Kconfig | 19 +
163
hw/nvram/meson.build | 8 +
164
108 files changed, 3806 insertions(+), 447 deletions(-)
165
create mode 100644 include/hw/nvram/xlnx-bbram.h
166
create mode 100644 include/hw/nvram/xlnx-efuse.h
167
create mode 100644 include/hw/nvram/xlnx-versal-efuse.h
168
create mode 100644 include/hw/nvram/xlnx-zynqmp-efuse.h
169
create mode 100644 hw/nvram/xlnx-bbram.c
170
create mode 100644 hw/nvram/xlnx-efuse-crc.c
171
create mode 100644 hw/nvram/xlnx-efuse.c
172
create mode 100644 hw/nvram/xlnx-versal-efuse-cache.c
173
create mode 100644 hw/nvram/xlnx-versal-efuse-ctrl.c
174
create mode 100644 hw/nvram/xlnx-zynqmp-efuse.c
175
create mode 100644 gdb-xml/arm-vfp-sysregs.xml
176
63
64
Peter Maydell (1):
65
target/arm:Set lg_page_size to 0 if either S1 or S2 asks for it
66
67
Philippe Mathieu-Daudé (5):
68
hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg
69
hw/arm/nseries: Constify various read-only arrays
70
hw/arm/nseries: Silent -Wmissing-field-initializers warning
71
hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope
72
hw/arm/smmu-common: Avoid using inlined functions with external linkage
73
74
Stephen Longfield (1):
75
hw/net: Fix read of uninitialized memory in imx_fec.
76
77
Tobias Röhmel (7):
78
target/arm: Don't add all MIDR aliases for cores that implement PMSA
79
target/arm: Make RVBAR available for all ARMv8 CPUs
80
target/arm: Make stage_2_format for cache attributes optional
81
target/arm: Enable TTBCR_EAE for ARMv8-R AArch32
82
target/arm: Add PMSAv8r registers
83
target/arm: Add PMSAv8r functionality
84
target/arm: Add ARM Cortex-R52 CPU
85
86
Zhuojia Shen (1):
87
target/arm: align exposed ID registers with Linux
88
89
include/hw/arm/fsl-imx7.h | 20 +
90
include/hw/arm/smmu-common.h | 3 -
91
include/hw/input/tsc2xxx.h | 4 +-
92
include/hw/timer/imx_epit.h | 8 +-
93
include/hw/timer/imx_gpt.h | 1 +
94
target/arm/cpu.h | 6 +
95
target/arm/internals.h | 4 +
96
hw/arm/fsl-imx6ul.c | 2 +-
97
hw/arm/fsl-imx7.c | 41 +-
98
hw/arm/nseries.c | 28 +-
99
hw/arm/smmu-common.c | 15 +-
100
hw/input/tsc2005.c | 2 +-
101
hw/input/tsc210x.c | 3 +-
102
hw/misc/imx6ul_ccm.c | 6 -
103
hw/misc/imx7_ccm.c | 49 ++-
104
hw/net/imx_fec.c | 8 +-
105
hw/timer/imx_epit.c | 376 +++++++++-------
106
hw/timer/imx_gpt.c | 25 ++
107
target/arm/cpu.c | 35 +-
108
target/arm/cpu64.c | 6 -
109
target/arm/cpu_tcg.c | 42 ++
110
target/arm/debug_helper.c | 3 +
111
target/arm/helper.c | 871 +++++++++++++++++++++++++++++---------
112
target/arm/m_helper.c | 16 -
113
target/arm/machine.c | 28 ++
114
target/arm/ptw.c | 152 +++++--
115
target/arm/tlb_helper.c | 4 +
116
target/arm/translate.c | 2 +-
117
tests/tcg/aarch64/sysregs.c | 24 +-
118
tests/tcg/aarch64/Makefile.target | 7 +-
119
30 files changed, 1330 insertions(+), 461 deletions(-)
120
diff view generated by jsdifflib
New patch
[PULL 01/34] target/arm:Set lg_page_size to 0 if either S1 or S2 asks for it
1
In get_phys_addr_twostage() we set the lg_page_size of the result to
2
the maximum of the stage 1 and stage 2 page sizes. This works for
3
the case where we do want to create a TLB entry, because we know the
4
common TLB code only creates entries of the TARGET_PAGE_SIZE and
5
asking for a size larger than that only means that invalidations
6
invalidate the whole larger area. However, if lg_page_size is
7
smaller than TARGET_PAGE_SIZE this effectively means "don't create a
8
TLB entry"; in this case if either S1 or S2 said "this covers less
9
than a page and can't go in a TLB" then the final result also should
10
be marked that way. Set the resulting page size to 0 if either
11
stage asked for a less-than-a-page entry, and expand the comment
12
to explain what's going on.
1
13
14
This has no effect for VMSA because currently the VMSA lookup always
15
returns results that cover at least TARGET_PAGE_SIZE; however when we
16
add v8R support it will reuse this code path, and for v8R the S1 and
17
S2 results can be smaller than TARGET_PAGE_SIZE.
18
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20221212142708.610090-1-peter.maydell@linaro.org
22
---
23
target/arm/ptw.c | 16 +++++++++++++---
24
1 file changed, 13 insertions(+), 3 deletions(-)
25
26
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/ptw.c
29
+++ b/target/arm/ptw.c
30
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
31
}
32
33
/*
34
- * Use the maximum of the S1 & S2 page size, so that invalidation
35
- * of pages > TARGET_PAGE_SIZE works correctly.
36
+ * If either S1 or S2 returned a result smaller than TARGET_PAGE_SIZE,
37
+ * this means "don't put this in the TLB"; in this case, return a
38
+ * result with lg_page_size == 0 to achieve that. Otherwise,
39
+ * use the maximum of the S1 & S2 page size, so that invalidation
40
+ * of pages > TARGET_PAGE_SIZE works correctly. (This works even though
41
+ * we know the combined result permissions etc only cover the minimum
42
+ * of the S1 and S2 page size, because we know that the common TLB code
43
+ * never actually creates TLB entries bigger than TARGET_PAGE_SIZE,
44
+ * and passing a larger page size value only affects invalidations.)
45
*/
46
- if (result->f.lg_page_size < s1_lgpgsz) {
47
+ if (result->f.lg_page_size < TARGET_PAGE_BITS ||
48
+ s1_lgpgsz < TARGET_PAGE_BITS) {
49
+ result->f.lg_page_size = 0;
50
+ } else if (result->f.lg_page_size < s1_lgpgsz) {
51
result->f.lg_page_size = s1_lgpgsz;
52
}
53
54
--
55
2.25.1
diff view generated by jsdifflib
[PULL 13/22] target/arm: Fix coding style issues in gdbstub code in helper.c
[PULL 02/34] target/arm: Don't add all MIDR aliases for cores that implement PMSA
1
We're going to move this code to a different file; fix the coding
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
style first so checkpatch doesn't complain. This includes deleting
3
the spurious 'break' statements after returns in the
4
vfp_gdb_get_reg() function.
5
2
3
Cores with PMSA have the MPUIR register which has the
4
same encoding as the MIDR alias with opc2=4. So we only
5
add that alias if we are not realizing a core that
6
implements PMSA.
7
8
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20221206102504.165775-2-tobias.roehmel@rwth-aachen.de
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210921162901.17508-3-peter.maydell@linaro.org
10
---
13
---
11
target/arm/helper.c | 23 ++++++++++++++++-------
14
target/arm/helper.c | 13 +++++++++----
12
1 file changed, 16 insertions(+), 7 deletions(-)
15
1 file changed, 9 insertions(+), 4 deletions(-)
13
16
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
19
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
20
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
21
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
22
.access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
23
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
24
.readfn = midr_read },
25
- /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
26
- { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
27
- .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
28
- .access = PL1_R, .resetvalue = cpu->midr },
29
+ /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
30
{ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
31
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
32
.access = PL1_R, .resetvalue = cpu->midr },
33
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
34
.accessfn = access_aa64_tid1,
35
.type = ARM_CP_CONST, .resetvalue = cpu->revidr },
36
};
37
+ ARMCPRegInfo id_v8_midr_alias_cp_reginfo = {
38
+ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
39
+ .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
40
+ .access = PL1_R, .resetvalue = cpu->midr
41
+ };
42
ARMCPRegInfo id_cp_reginfo[] = {
43
/* These are common to v8 and pre-v8 */
44
{ .name = "CTR",
45
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
19
}
46
}
20
}
47
if (arm_feature(env, ARM_FEATURE_V8)) {
21
switch (reg - nregs) {
48
define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
22
- case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); break;
49
+ if (!arm_feature(env, ARM_FEATURE_PMSA)) {
23
- case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break;
50
+ define_one_arm_cp_reg(cpu, &id_v8_midr_alias_cp_reginfo);
24
- case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); break;
51
+ }
25
+ case 0:
52
} else {
26
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
53
define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
27
+ case 1:
28
+ return gdb_get_reg32(buf, vfp_get_fpscr(env));
29
+ case 2:
30
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
31
}
32
return 0;
33
}
34
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
35
}
54
}
36
}
37
switch (reg - nregs) {
38
- case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
39
- case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
40
- case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
41
+ case 0:
42
+ env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
43
+ return 4;
44
+ case 1:
45
+ vfp_set_fpscr(env, ldl_p(buf));
46
+ return 4;
47
+ case 2:
48
+ env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
49
+ return 4;
50
}
51
return 0;
52
}
53
@@ -XXX,XX +XXX,XX @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
54
return gdb_get_reg32(buf, vfp_get_fpsr(env));
55
case 33:
56
/* FPCR */
57
- return gdb_get_reg32(buf,vfp_get_fpcr(env));
58
+ return gdb_get_reg32(buf, vfp_get_fpcr(env));
59
default:
60
return 0;
61
}
62
--
55
--
63
2.20.1
56
2.25.1
64
57
65
58
diff view generated by jsdifflib
[PULL 22/22] hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19
[PULL 03/34] target/arm: Make RVBAR available for all ARMv8 CPUs
1
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
The Linux spi-imx driver does not work on QEMU. The reason is that the
3
RVBAR shadows RVBAR_ELx where x is the highest exception
4
state of m25p80 loops in STATE_READING_DATA state after receiving
4
level if the highest EL is not EL3. This patch also allows
5
RDSR command, the new command is ignored. Before sending a new command,
5
ARMv8 CPUs to change the reset address with
6
CS line should be pulled high to make the state of m25p80 back to IDLE.
6
the rvbar property.
7
7
8
Currently the SPI flash CS line is connected to the SPI controller, but
8
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
9
on the real board, it's connected to GPIO3_19. This matches the ecspi1
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
device node in the board dts.
10
Message-id: 20221206102504.165775-3-tobias.roehmel@rwth-aachen.de
11
12
ecspi1 node in imx6qdl-sabrelite.dtsi:
13
&ecspi1 {
14
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
15
pinctrl-names = "default";
16
pinctrl-0 = <&pinctrl_ecspi1>;
17
status = "okay";
18
19
flash: m25p80@0 {
20
compatible = "sst,sst25vf016b", "jedec,spi-nor";
21
spi-max-frequency = <20000000>;
22
reg = <0>;
23
};
24
};
25
26
Should connect the SSI_GPIO_CS to GPIO3_19 when adding a spi-nor to
27
spi1 on sabrelite machine.
28
29
Verified this patch on Linux v5.14.
30
31
Logs:
32
# echo "01234567899876543210" > test
33
# mtd_debug erase /dev/mtd0 0x0 0x1000
34
Erased 4096 bytes from address 0x00000000 in flash
35
# mtd_debug write /dev/mtdblock0 0x0 20 test
36
Copied 20 bytes from test to address 0x00000000 in flash
37
# mtd_debug read /dev/mtdblock0 0x0 20 test_out
38
Copied 20 bytes from address 0x00000000 in flash to test_out
39
# cat test_out
40
01234567899876543210#
41
42
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
43
Reported-by: Guenter Roeck <linux@roeck-us.net>
44
Reviewed-by: Bin Meng <bin.meng@windriver.com>
45
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
46
Message-id: 20210927142825.491-1-xchengl.cn@gmail.com
47
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
---
12
---
49
hw/arm/sabrelite.c | 2 +-
13
target/arm/cpu.c | 6 +++++-
50
1 file changed, 1 insertion(+), 1 deletion(-)
14
target/arm/helper.c | 21 ++++++++++++++-------
15
2 files changed, 19 insertions(+), 8 deletions(-)
51
16
52
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
17
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
53
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/arm/sabrelite.c
19
--- a/target/arm/cpu.c
55
+++ b/hw/arm/sabrelite.c
20
+++ b/target/arm/cpu.c
56
@@ -XXX,XX +XXX,XX @@ static void sabrelite_init(MachineState *machine)
21
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
57
qdev_realize_and_unref(flash_dev, BUS(spi_bus), &error_fatal);
22
env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
58
23
CPACR, CP11, 3);
59
cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
24
#endif
60
- sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line);
25
+ if (arm_feature(env, ARM_FEATURE_V8)) {
61
+ qdev_connect_gpio_out(DEVICE(&s->gpio[2]), 19, cs_line);
26
+ env->cp15.rvbar = cpu->rvbar_prop;
62
}
27
+ env->regs[15] = cpu->rvbar_prop;
28
+ }
29
}
30
31
#if defined(CONFIG_USER_ONLY)
32
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
33
qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
34
}
35
36
- if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
37
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
38
object_property_add_uint64_ptr(obj, "rvbar",
39
&cpu->rvbar_prop,
40
OBJ_PROP_FLAG_READWRITE);
41
diff --git a/target/arm/helper.c b/target/arm/helper.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/helper.c
44
+++ b/target/arm/helper.c
45
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
46
if (!arm_feature(env, ARM_FEATURE_EL3) &&
47
!arm_feature(env, ARM_FEATURE_EL2)) {
48
ARMCPRegInfo rvbar = {
49
- .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
50
+ .name = "RVBAR_EL1", .state = ARM_CP_STATE_BOTH,
51
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
52
.access = PL1_R,
53
.fieldoffset = offsetof(CPUARMState, cp15.rvbar),
54
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
55
}
56
/* RVBAR_EL2 is only implemented if EL2 is the highest EL */
57
if (!arm_feature(env, ARM_FEATURE_EL3)) {
58
- ARMCPRegInfo rvbar = {
59
- .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
60
- .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
61
- .access = PL2_R,
62
- .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
63
+ ARMCPRegInfo rvbar[] = {
64
+ {
65
+ .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
66
+ .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
67
+ .access = PL2_R,
68
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
69
+ },
70
+ { .name = "RVBAR", .type = ARM_CP_ALIAS,
71
+ .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
72
+ .access = PL2_R,
73
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
74
+ },
75
};
76
- define_one_arm_cp_reg(cpu, &rvbar);
77
+ define_arm_cp_regs(cpu, rvbar);
63
}
78
}
64
}
79
}
80
65
--
81
--
66
2.20.1
82
2.25.1
67
83
68
84
diff view generated by jsdifflib
[PULL 11/22] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage
[PULL 04/34] target/arm: Make stage_2_format for cache attributes optional
1
From: Tong Ho <tong.ho@xilinx.com>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
Add BBRAM and eFUSE usage to the Xilinx Versal Virt board
3
The v8R PMSAv8 has a two-stage MPU translation process, but, unlike
4
document.
4
VMSAv8, the stage 2 attributes are in the same format as the stage 1
5
attributes (8-bit MAIR format). Rather than converting the MAIR
6
format to the format used for VMSA stage 2 (bits [5:2] of a VMSA
7
stage 2 descriptor) and then converting back to do the attribute
8
combination, allow combined_attrs_nofwb() to accept s2 attributes
9
that are already in the MAIR format.
5
10
6
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
11
We move the assert() to combined_attrs_fwb(), because that function
7
Message-id: 20210917052400.1249094-10-tong.ho@xilinx.com
12
really does require a VMSA stage 2 attribute format. (We will never
13
get there for v8R, because PMSAv8 does not implement FEAT_S2FWB.)
14
15
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20221206102504.165775-4-tobias.roehmel@rwth-aachen.de
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
19
---
11
docs/system/arm/xlnx-versal-virt.rst | 49 ++++++++++++++++++++++++++++
20
target/arm/ptw.c | 10 ++++++++--
12
1 file changed, 49 insertions(+)
21
1 file changed, 8 insertions(+), 2 deletions(-)
13
22
14
diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst
23
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/xlnx-versal-virt.rst
25
--- a/target/arm/ptw.c
17
+++ b/docs/system/arm/xlnx-versal-virt.rst
26
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ Implemented devices:
27
@@ -XXX,XX +XXX,XX @@ static uint8_t combined_attrs_nofwb(uint64_t hcr,
19
- OCM (256KB of On Chip Memory)
28
{
20
- XRAM (4MB of on chip Accelerator RAM)
29
uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
21
- DDR memory
30
22
+- BBRAM (36 bytes of Battery-backed RAM)
31
- s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
23
+- eFUSE (3072 bytes of one-time field-programmable bit array)
32
+ if (s2.is_s2_format) {
24
33
+ s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
25
QEMU does not yet model any other devices, including the PL and the AI Engine.
34
+ } else {
26
35
+ s2_mair_attrs = s2.attrs;
27
@@ -XXX,XX +XXX,XX @@ Run the following at the U-Boot prompt:
36
+ }
28
fdt set /chosen/dom0 reg <0x00000000 0x40000000 0x0 0x03100000>
37
29
booti 30000000 - 20000000
38
s1lo = extract32(s1.attrs, 0, 4);
30
39
s2lo = extract32(s2_mair_attrs, 0, 4);
31
+BBRAM File Backend
40
@@ -XXX,XX +XXX,XX @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
32
+""""""""""""""""""
41
*/
33
+BBRAM can have an optional file backend, which must be a seekable
42
static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2)
34
+binary file with a size of 36 bytes or larger. A file with all
43
{
35
+binary 0s is a 'blank'.
44
+ assert(s2.is_s2_format && !s1.is_s2_format);
36
+
45
+
37
+To add a file-backend for the BBRAM:
46
switch (s2.attrs) {
38
+
47
case 7:
39
+.. code-block:: bash
48
/* Use stage 1 attributes */
40
+
49
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
41
+ -drive if=pflash,index=0,file=versal-bbram.bin,format=raw
50
ARMCacheAttrs ret;
42
+
51
bool tagged = false;
43
+To use a different index value, N, from default of 0, add:
52
44
+
53
- assert(s2.is_s2_format && !s1.is_s2_format);
45
+.. code-block:: bash
54
+ assert(!s1.is_s2_format);
46
+
55
ret.is_s2_format = false;
47
+ -global xlnx,bbram-ctrl.drive-index=N
56
48
+
57
if (s1.attrs == 0xf0) {
49
+eFUSE File Backend
50
+""""""""""""""""""
51
+eFUSE can have an optional file backend, which must be a seekable
52
+binary file with a size of 3072 bytes or larger. A file with all
53
+binary 0s is a 'blank'.
54
+
55
+To add a file-backend for the eFUSE:
56
+
57
+.. code-block:: bash
58
+
59
+ -drive if=pflash,index=1,file=versal-efuse.bin,format=raw
60
+
61
+To use a different index value, N, from default of 1, add:
62
+
63
+.. code-block:: bash
64
+
65
+ -global xlnx,efuse.drive-index=N
66
+
67
+.. warning::
68
+ In actual physical Versal, BBRAM and eFUSE contain sensitive data.
69
+ The QEMU device models do **not** encrypt nor obfuscate any data
70
+ when holding them in models' memory or when writing them to their
71
+ file backends.
72
+
73
+ Thus, a file backend should be used with caution, and 'format=luks'
74
+ is highly recommended (albeit with usage complexity).
75
+
76
+ Better yet, do not use actual product data when running guest image
77
+ on this Xilinx Versal Virt board.
78
--
58
--
79
2.20.1
59
2.25.1
80
60
81
61
diff view generated by jsdifflib
[PULL 12/22] configs: Don't include 32-bit-only GDB XML in aarch64 linux configs
[PULL 05/34] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32
1
The aarch64-linux QEMU usermode binaries can never run 32-bit
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
code, so they do not need to include the GDB XML for it.
3
(arm_cpu_register_gdb_regs_for_features() will not use these
4
XML files if the CPU has ARM_FEATURE_AARCH64, so we will not
5
advertise to gdb that we have them.)
6
2
3
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
4
tough they don't have the TTBCR register.
5
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
6
AArch32 architecture profile Version:A.c section C1.2.
7
8
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20221206102504.165775-5-tobias.roehmel@rwth-aachen.de
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210921162901.17508-2-peter.maydell@linaro.org
10
---
12
---
11
configs/targets/aarch64-linux-user.mak | 2 +-
13
target/arm/internals.h | 4 ++++
12
configs/targets/aarch64_be-linux-user.mak | 2 +-
14
target/arm/debug_helper.c | 3 +++
13
2 files changed, 2 insertions(+), 2 deletions(-)
15
target/arm/tlb_helper.c | 4 ++++
16
3 files changed, 11 insertions(+)
14
17
15
diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/configs/targets/aarch64-linux-user.mak
20
--- a/target/arm/internals.h
18
+++ b/configs/targets/aarch64-linux-user.mak
21
+++ b/target/arm/internals.h
19
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ unsigned int arm_pamax(ARMCPU *cpu);
20
TARGET_ARCH=aarch64
23
static inline bool extended_addresses_enabled(CPUARMState *env)
21
TARGET_BASE_ARCH=arm
24
{
22
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
25
uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
23
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
26
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
24
TARGET_HAS_BFLT=y
27
+ arm_feature(env, ARM_FEATURE_V8)) {
25
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
28
+ return true;
26
diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak
29
+ }
30
return arm_el_is_aa64(env, 1) ||
31
(arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE));
32
}
33
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
27
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
28
--- a/configs/targets/aarch64_be-linux-user.mak
35
--- a/target/arm/debug_helper.c
29
+++ b/configs/targets/aarch64_be-linux-user.mak
36
+++ b/target/arm/debug_helper.c
30
@@ -XXX,XX +XXX,XX @@
37
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env)
31
TARGET_ARCH=aarch64
38
32
TARGET_BASE_ARCH=arm
39
if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
33
TARGET_WORDS_BIGENDIAN=y
40
using_lpae = true;
34
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
41
+ } else if (arm_feature(env, ARM_FEATURE_PMSA) &&
35
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
42
+ arm_feature(env, ARM_FEATURE_V8)) {
36
TARGET_HAS_BFLT=y
43
+ using_lpae = true;
37
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
44
} else {
45
if (arm_feature(env, ARM_FEATURE_LPAE) &&
46
(env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
47
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/tlb_helper.c
50
+++ b/target/arm/tlb_helper.c
51
@@ -XXX,XX +XXX,XX @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
52
if (el == 2 || arm_el_is_aa64(env, el)) {
53
return true;
54
}
55
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
56
+ arm_feature(env, ARM_FEATURE_V8)) {
57
+ return true;
58
+ }
59
if (arm_feature(env, ARM_FEATURE_LPAE)
60
&& (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
61
return true;
38
--
62
--
39
2.20.1
63
2.25.1
40
64
41
65
diff view generated by jsdifflib
[PULL 06/22] hw/nvram: Introduce Xilinx battery-backed ram
[PULL 06/34] target/arm: Add PMSAv8r registers
1
From: Tong Ho <tong.ho@xilinx.com>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
This device is present in Versal and ZynqMP product
3
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
4
families to store a 256-bit encryption key.
4
Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de
5
6
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
8
9
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
11
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
12
Message-id: 20210917052400.1249094-5-tong.ho@xilinx.com
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
6
---
16
include/hw/nvram/xlnx-bbram.h | 54 ++++
7
target/arm/cpu.h | 6 +
17
hw/nvram/xlnx-bbram.c | 545 ++++++++++++++++++++++++++++++++++
8
target/arm/cpu.c | 28 +++-
18
hw/nvram/Kconfig | 4 +
9
target/arm/helper.c | 302 +++++++++++++++++++++++++++++++++++++++++++
19
hw/nvram/meson.build | 1 +
10
target/arm/machine.c | 28 ++++
20
4 files changed, 604 insertions(+)
11
4 files changed, 360 insertions(+), 4 deletions(-)
21
create mode 100644 include/hw/nvram/xlnx-bbram.h
22
create mode 100644 hw/nvram/xlnx-bbram.c
23
12
24
diff --git a/include/hw/nvram/xlnx-bbram.h b/include/hw/nvram/xlnx-bbram.h
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
25
new file mode 100644
14
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX
15
--- a/target/arm/cpu.h
27
--- /dev/null
16
+++ b/target/arm/cpu.h
28
+++ b/include/hw/nvram/xlnx-bbram.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
29
@@ -XXX,XX +XXX,XX @@
18
};
30
+/*
19
uint64_t sctlr_el[4];
31
+ * QEMU model of the Xilinx BBRAM Battery Backed RAM
20
};
32
+ *
21
+ uint64_t vsctlr; /* Virtualization System control register. */
33
+ * Copyright (c) 2015-2021 Xilinx Inc.
22
uint64_t cpacr_el1; /* Architectural feature access control register */
34
+ *
23
uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
35
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
24
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
36
+ *
25
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
37
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
26
*/
38
+ * of this software and associated documentation files (the "Software"), to deal
27
uint32_t *rbar[M_REG_NUM_BANKS];
39
+ * in the Software without restriction, including without limitation the rights
28
uint32_t *rlar[M_REG_NUM_BANKS];
40
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
29
+ uint32_t *hprbar;
41
+ * copies of the Software, and to permit persons to whom the Software is
30
+ uint32_t *hprlar;
42
+ * furnished to do so, subject to the following conditions:
31
uint32_t mair0[M_REG_NUM_BANKS];
43
+ *
32
uint32_t mair1[M_REG_NUM_BANKS];
44
+ * The above copyright notice and this permission notice shall be included in
33
+ uint32_t hprselr;
45
+ * all copies or substantial portions of the Software.
34
} pmsav8;
46
+ *
35
47
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
36
/* v8M SAU */
48
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
37
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
49
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
38
bool has_mpu;
50
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
39
/* PMSAv7 MPU number of supported regions */
51
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
40
uint32_t pmsav7_dregion;
52
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
41
+ /* PMSAv8 MPU number of supported hyp regions */
53
+ * THE SOFTWARE.
42
+ uint32_t pmsav8r_hdregion;
54
+ */
43
/* v8M SAU number of supported regions */
55
+#ifndef XLNX_BBRAM_H
44
uint32_t sau_sregion;
56
+#define XLNX_BBRAM_H
45
57
+
46
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
58
+#include "sysemu/block-backend.h"
47
index XXXXXXX..XXXXXXX 100644
59
+#include "hw/qdev-core.h"
48
--- a/target/arm/cpu.c
60
+#include "hw/irq.h"
49
+++ b/target/arm/cpu.c
61
+#include "hw/sysbus.h"
50
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
62
+#include "hw/register.h"
51
sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
63
+
52
}
64
+#define RMAX_XLNX_BBRAM ((0x4c / 4) + 1)
53
}
65
+
54
+
66
+#define TYPE_XLNX_BBRAM "xlnx,bbram-ctrl"
55
+ if (cpu->pmsav8r_hdregion > 0) {
67
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxBBRam, XLNX_BBRAM);
56
+ memset(env->pmsav8.hprbar, 0,
68
+
57
+ sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion);
69
+struct XlnxBBRam {
58
+ memset(env->pmsav8.hprlar, 0,
70
+ SysBusDevice parent_obj;
59
+ sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion);
71
+ qemu_irq irq_bbram;
60
+ }
72
+
61
+
73
+ BlockBackend *blk;
62
env->pmsav7.rnr[M_REG_NS] = 0;
74
+
63
env->pmsav7.rnr[M_REG_S] = 0;
75
+ uint32_t crc_zpads;
64
env->pmsav8.mair0[M_REG_NS] = 0;
76
+ bool bbram8_wo;
65
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
77
+ bool blk_ro;
66
/* MPU can be configured out of a PMSA CPU either by setting has-mpu
78
+
67
* to false or by setting pmsav7-dregion to 0.
79
+ uint32_t regs[RMAX_XLNX_BBRAM];
68
*/
80
+ RegisterInfo regs_info[RMAX_XLNX_BBRAM];
69
- if (!cpu->has_mpu) {
70
- cpu->pmsav7_dregion = 0;
71
- }
72
- if (cpu->pmsav7_dregion == 0) {
73
+ if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) {
74
cpu->has_mpu = false;
75
+ cpu->pmsav7_dregion = 0;
76
+ cpu->pmsav8r_hdregion = 0;
77
}
78
79
if (arm_feature(env, ARM_FEATURE_PMSA) &&
80
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
81
env->pmsav7.dracr = g_new0(uint32_t, nr);
82
}
83
}
84
+
85
+ if (cpu->pmsav8r_hdregion > 0xff) {
86
+ error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32,
87
+ cpu->pmsav8r_hdregion);
88
+ return;
89
+ }
90
+
91
+ if (cpu->pmsav8r_hdregion) {
92
+ env->pmsav8.hprbar = g_new0(uint32_t,
93
+ cpu->pmsav8r_hdregion);
94
+ env->pmsav8.hprlar = g_new0(uint32_t,
95
+ cpu->pmsav8r_hdregion);
96
+ }
97
}
98
99
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
100
diff --git a/target/arm/helper.c b/target/arm/helper.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/helper.c
103
+++ b/target/arm/helper.c
104
@@ -XXX,XX +XXX,XX @@ static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
105
raw_write(env, ri, value);
106
}
107
108
+static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
109
+ uint64_t value)
110
+{
111
+ ARMCPU *cpu = env_archcpu(env);
112
+
113
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
114
+ env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value;
115
+}
116
+
117
+static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri)
118
+{
119
+ return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]];
120
+}
121
+
122
+static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri,
123
+ uint64_t value)
124
+{
125
+ ARMCPU *cpu = env_archcpu(env);
126
+
127
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
128
+ env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value;
129
+}
130
+
131
+static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri)
132
+{
133
+ return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]];
134
+}
135
+
136
+static void prselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
137
+ uint64_t value)
138
+{
139
+ ARMCPU *cpu = env_archcpu(env);
140
+
141
+ /*
142
+ * Ignore writes that would select not implemented region.
143
+ * This is architecturally UNPREDICTABLE.
144
+ */
145
+ if (value >= cpu->pmsav7_dregion) {
146
+ return;
147
+ }
148
+
149
+ env->pmsav7.rnr[M_REG_NS] = value;
150
+}
151
+
152
+static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
153
+ uint64_t value)
154
+{
155
+ ARMCPU *cpu = env_archcpu(env);
156
+
157
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
158
+ env->pmsav8.hprbar[env->pmsav8.hprselr] = value;
159
+}
160
+
161
+static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri)
162
+{
163
+ return env->pmsav8.hprbar[env->pmsav8.hprselr];
164
+}
165
+
166
+static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri,
167
+ uint64_t value)
168
+{
169
+ ARMCPU *cpu = env_archcpu(env);
170
+
171
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
172
+ env->pmsav8.hprlar[env->pmsav8.hprselr] = value;
173
+}
174
+
175
+static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri)
176
+{
177
+ return env->pmsav8.hprlar[env->pmsav8.hprselr];
178
+}
179
+
180
+static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
181
+ uint64_t value)
182
+{
183
+ uint32_t n;
184
+ uint32_t bit;
185
+ ARMCPU *cpu = env_archcpu(env);
186
+
187
+ /* Ignore writes to unimplemented regions */
188
+ int rmax = MIN(cpu->pmsav8r_hdregion, 32);
189
+ value &= MAKE_64BIT_MASK(0, rmax);
190
+
191
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
192
+
193
+ /* Register alias is only valid for first 32 indexes */
194
+ for (n = 0; n < rmax; ++n) {
195
+ bit = extract32(value, n, 1);
196
+ env->pmsav8.hprlar[n] = deposit32(
197
+ env->pmsav8.hprlar[n], 0, 1, bit);
198
+ }
199
+}
200
+
201
+static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri)
202
+{
203
+ uint32_t n;
204
+ uint32_t result = 0x0;
205
+ ARMCPU *cpu = env_archcpu(env);
206
+
207
+ /* Register alias is only valid for first 32 indexes */
208
+ for (n = 0; n < MIN(cpu->pmsav8r_hdregion, 32); ++n) {
209
+ if (env->pmsav8.hprlar[n] & 0x1) {
210
+ result |= (0x1 << n);
211
+ }
212
+ }
213
+ return result;
214
+}
215
+
216
+static void hprselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
217
+ uint64_t value)
218
+{
219
+ ARMCPU *cpu = env_archcpu(env);
220
+
221
+ /*
222
+ * Ignore writes that would select not implemented region.
223
+ * This is architecturally UNPREDICTABLE.
224
+ */
225
+ if (value >= cpu->pmsav8r_hdregion) {
226
+ return;
227
+ }
228
+
229
+ env->pmsav8.hprselr = value;
230
+}
231
+
232
+static void pmsav8r_regn_write(CPUARMState *env, const ARMCPRegInfo *ri,
233
+ uint64_t value)
234
+{
235
+ ARMCPU *cpu = env_archcpu(env);
236
+ uint8_t index = (extract32(ri->opc0, 0, 1) << 4) |
237
+ (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1);
238
+
239
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
240
+
241
+ if (ri->opc1 & 4) {
242
+ if (index >= cpu->pmsav8r_hdregion) {
243
+ return;
244
+ }
245
+ if (ri->opc2 & 0x1) {
246
+ env->pmsav8.hprlar[index] = value;
247
+ } else {
248
+ env->pmsav8.hprbar[index] = value;
249
+ }
250
+ } else {
251
+ if (index >= cpu->pmsav7_dregion) {
252
+ return;
253
+ }
254
+ if (ri->opc2 & 0x1) {
255
+ env->pmsav8.rlar[M_REG_NS][index] = value;
256
+ } else {
257
+ env->pmsav8.rbar[M_REG_NS][index] = value;
258
+ }
259
+ }
260
+}
261
+
262
+static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri)
263
+{
264
+ ARMCPU *cpu = env_archcpu(env);
265
+ uint8_t index = (extract32(ri->opc0, 0, 1) << 4) |
266
+ (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1);
267
+
268
+ if (ri->opc1 & 4) {
269
+ if (index >= cpu->pmsav8r_hdregion) {
270
+ return 0x0;
271
+ }
272
+ if (ri->opc2 & 0x1) {
273
+ return env->pmsav8.hprlar[index];
274
+ } else {
275
+ return env->pmsav8.hprbar[index];
276
+ }
277
+ } else {
278
+ if (index >= cpu->pmsav7_dregion) {
279
+ return 0x0;
280
+ }
281
+ if (ri->opc2 & 0x1) {
282
+ return env->pmsav8.rlar[M_REG_NS][index];
283
+ } else {
284
+ return env->pmsav8.rbar[M_REG_NS][index];
285
+ }
286
+ }
287
+}
288
+
289
+static const ARMCPRegInfo pmsav8r_cp_reginfo[] = {
290
+ { .name = "PRBAR",
291
+ .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 0,
292
+ .access = PL1_RW, .type = ARM_CP_NO_RAW,
293
+ .accessfn = access_tvm_trvm,
294
+ .readfn = prbar_read, .writefn = prbar_write },
295
+ { .name = "PRLAR",
296
+ .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 1,
297
+ .access = PL1_RW, .type = ARM_CP_NO_RAW,
298
+ .accessfn = access_tvm_trvm,
299
+ .readfn = prlar_read, .writefn = prlar_write },
300
+ { .name = "PRSELR", .resetvalue = 0,
301
+ .cp = 15, .opc1 = 0, .crn = 6, .crm = 2, .opc2 = 1,
302
+ .access = PL1_RW, .accessfn = access_tvm_trvm,
303
+ .writefn = prselr_write,
304
+ .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]) },
305
+ { .name = "HPRBAR", .resetvalue = 0,
306
+ .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 0,
307
+ .access = PL2_RW, .type = ARM_CP_NO_RAW,
308
+ .readfn = hprbar_read, .writefn = hprbar_write },
309
+ { .name = "HPRLAR",
310
+ .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 1,
311
+ .access = PL2_RW, .type = ARM_CP_NO_RAW,
312
+ .readfn = hprlar_read, .writefn = hprlar_write },
313
+ { .name = "HPRSELR", .resetvalue = 0,
314
+ .cp = 15, .opc1 = 4, .crn = 6, .crm = 2, .opc2 = 1,
315
+ .access = PL2_RW,
316
+ .writefn = hprselr_write,
317
+ .fieldoffset = offsetof(CPUARMState, pmsav8.hprselr) },
318
+ { .name = "HPRENR",
319
+ .cp = 15, .opc1 = 4, .crn = 6, .crm = 1, .opc2 = 1,
320
+ .access = PL2_RW, .type = ARM_CP_NO_RAW,
321
+ .readfn = hprenr_read, .writefn = hprenr_write },
81
+};
322
+};
82
+
323
+
83
+#endif
324
static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
84
diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c
325
/* Reset for all these registers is handled in arm_cpu_reset(),
85
new file mode 100644
326
* because the PMSAv7 is also used by M-profile CPUs, which do
86
index XXXXXXX..XXXXXXX
327
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
87
--- /dev/null
328
.access = PL1_R, .type = ARM_CP_CONST,
88
+++ b/hw/nvram/xlnx-bbram.c
329
.resetvalue = cpu->pmsav7_dregion << 8
89
@@ -XXX,XX +XXX,XX @@
330
};
90
+/*
331
+ /* HMPUIR is specific to PMSA V8 */
91
+ * QEMU model of the Xilinx BBRAM Battery Backed RAM
332
+ ARMCPRegInfo id_hmpuir_reginfo = {
92
+ *
333
+ .name = "HMPUIR",
93
+ * Copyright (c) 2014-2021 Xilinx Inc.
334
+ .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 4,
94
+ *
335
+ .access = PL2_R, .type = ARM_CP_CONST,
95
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
336
+ .resetvalue = cpu->pmsav8r_hdregion
96
+ * of this software and associated documentation files (the "Software"), to deal
337
+ };
97
+ * in the Software without restriction, including without limitation the rights
338
static const ARMCPRegInfo crn0_wi_reginfo = {
98
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
339
.name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
99
+ * copies of the Software, and to permit persons to whom the Software is
340
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
100
+ * furnished to do so, subject to the following conditions:
341
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
101
+ *
342
define_arm_cp_regs(cpu, id_cp_reginfo);
102
+ * The above copyright notice and this permission notice shall be included in
343
if (!arm_feature(env, ARM_FEATURE_PMSA)) {
103
+ * all copies or substantial portions of the Software.
344
define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
104
+ *
345
+ } else if (arm_feature(env, ARM_FEATURE_PMSA) &&
105
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
346
+ arm_feature(env, ARM_FEATURE_V8)) {
106
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
347
+ uint32_t i = 0;
107
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
348
+ char *tmp_string;
108
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
349
+
109
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
350
+ define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
110
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
351
+ define_one_arm_cp_reg(cpu, &id_hmpuir_reginfo);
111
+ * THE SOFTWARE.
352
+ define_arm_cp_regs(cpu, pmsav8r_cp_reginfo);
112
+ */
353
+
113
+
354
+ /* Register alias is only valid for first 32 indexes */
114
+#include "qemu/osdep.h"
355
+ for (i = 0; i < MIN(cpu->pmsav7_dregion, 32); ++i) {
115
+#include "hw/nvram/xlnx-bbram.h"
356
+ uint8_t crm = 0b1000 | extract32(i, 1, 3);
116
+
357
+ uint8_t opc1 = extract32(i, 4, 1);
117
+#include "qemu/error-report.h"
358
+ uint8_t opc2 = extract32(i, 0, 1) << 2;
118
+#include "qemu/log.h"
359
+
119
+#include "qapi/error.h"
360
+ tmp_string = g_strdup_printf("PRBAR%u", i);
120
+#include "sysemu/blockdev.h"
361
+ ARMCPRegInfo tmp_prbarn_reginfo = {
121
+#include "migration/vmstate.h"
362
+ .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW,
122
+#include "hw/qdev-properties.h"
363
+ .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
123
+#include "hw/qdev-properties-system.h"
364
+ .access = PL1_RW, .resetvalue = 0,
124
+#include "hw/nvram/xlnx-efuse.h"
365
+ .accessfn = access_tvm_trvm,
125
+
366
+ .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
126
+#ifndef XLNX_BBRAM_ERR_DEBUG
367
+ };
127
+#define XLNX_BBRAM_ERR_DEBUG 0
368
+ define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo);
128
+#endif
369
+ g_free(tmp_string);
129
+
370
+
130
+REG32(BBRAM_STATUS, 0x0)
371
+ opc2 = extract32(i, 0, 1) << 2 | 0x1;
131
+ FIELD(BBRAM_STATUS, AES_CRC_PASS, 9, 1)
372
+ tmp_string = g_strdup_printf("PRLAR%u", i);
132
+ FIELD(BBRAM_STATUS, AES_CRC_DONE, 8, 1)
373
+ ARMCPRegInfo tmp_prlarn_reginfo = {
133
+ FIELD(BBRAM_STATUS, BBRAM_ZEROIZED, 4, 1)
374
+ .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW,
134
+ FIELD(BBRAM_STATUS, PGM_MODE, 0, 1)
375
+ .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
135
+REG32(BBRAM_CTRL, 0x4)
376
+ .access = PL1_RW, .resetvalue = 0,
136
+ FIELD(BBRAM_CTRL, ZEROIZE, 0, 1)
377
+ .accessfn = access_tvm_trvm,
137
+REG32(PGM_MODE, 0x8)
378
+ .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
138
+REG32(BBRAM_AES_CRC, 0xc)
379
+ };
139
+REG32(BBRAM_0, 0x10)
380
+ define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo);
140
+REG32(BBRAM_1, 0x14)
381
+ g_free(tmp_string);
141
+REG32(BBRAM_2, 0x18)
382
+ }
142
+REG32(BBRAM_3, 0x1c)
383
+
143
+REG32(BBRAM_4, 0x20)
384
+ /* Register alias is only valid for first 32 indexes */
144
+REG32(BBRAM_5, 0x24)
385
+ for (i = 0; i < MIN(cpu->pmsav8r_hdregion, 32); ++i) {
145
+REG32(BBRAM_6, 0x28)
386
+ uint8_t crm = 0b1000 | extract32(i, 1, 3);
146
+REG32(BBRAM_7, 0x2c)
387
+ uint8_t opc1 = 0b100 | extract32(i, 4, 1);
147
+REG32(BBRAM_8, 0x30)
388
+ uint8_t opc2 = extract32(i, 0, 1) << 2;
148
+REG32(BBRAM_SLVERR, 0x34)
389
+
149
+ FIELD(BBRAM_SLVERR, ENABLE, 0, 1)
390
+ tmp_string = g_strdup_printf("HPRBAR%u", i);
150
+REG32(BBRAM_ISR, 0x38)
391
+ ARMCPRegInfo tmp_hprbarn_reginfo = {
151
+ FIELD(BBRAM_ISR, APB_SLVERR, 0, 1)
392
+ .name = tmp_string,
152
+REG32(BBRAM_IMR, 0x3c)
393
+ .type = ARM_CP_NO_RAW,
153
+ FIELD(BBRAM_IMR, APB_SLVERR, 0, 1)
394
+ .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
154
+REG32(BBRAM_IER, 0x40)
395
+ .access = PL2_RW, .resetvalue = 0,
155
+ FIELD(BBRAM_IER, APB_SLVERR, 0, 1)
396
+ .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
156
+REG32(BBRAM_IDR, 0x44)
397
+ };
157
+ FIELD(BBRAM_IDR, APB_SLVERR, 0, 1)
398
+ define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo);
158
+REG32(BBRAM_MSW_LOCK, 0x4c)
399
+ g_free(tmp_string);
159
+ FIELD(BBRAM_MSW_LOCK, VAL, 0, 1)
400
+
160
+
401
+ opc2 = extract32(i, 0, 1) << 2 | 0x1;
161
+#define R_MAX (R_BBRAM_MSW_LOCK + 1)
402
+ tmp_string = g_strdup_printf("HPRLAR%u", i);
162
+
403
+ ARMCPRegInfo tmp_hprlarn_reginfo = {
163
+#define RAM_MAX (A_BBRAM_8 + 4 - A_BBRAM_0)
404
+ .name = tmp_string,
164
+
405
+ .type = ARM_CP_NO_RAW,
165
+#define BBRAM_PGM_MAGIC 0x757bdf0d
406
+ .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
166
+
407
+ .access = PL2_RW, .resetvalue = 0,
167
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxBBRam *)0)->regs));
408
+ .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
168
+
409
+ };
169
+static bool bbram_msw_locked(XlnxBBRam *s)
410
+ define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo);
170
+{
411
+ g_free(tmp_string);
171
+ return ARRAY_FIELD_EX32(s->regs, BBRAM_MSW_LOCK, VAL) != 0;
412
+ }
172
+}
413
} else if (arm_feature(env, ARM_FEATURE_V7)) {
173
+
414
define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
174
+static bool bbram_pgm_enabled(XlnxBBRam *s)
415
}
175
+{
416
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
176
+ return ARRAY_FIELD_EX32(s->regs, BBRAM_STATUS, PGM_MODE) != 0;
417
sctlr.type |= ARM_CP_SUPPRESS_TB_END;
177
+}
418
}
178
+
419
define_one_arm_cp_reg(cpu, &sctlr);
179
+static void bbram_bdrv_error(XlnxBBRam *s, int rc, gchar *detail)
420
+
180
+{
421
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
181
+ Error *errp;
422
+ arm_feature(env, ARM_FEATURE_V8)) {
182
+
423
+ ARMCPRegInfo vsctlr = {
183
+ error_setg_errno(&errp, -rc, "%s: BBRAM backstore %s failed.",
424
+ .name = "VSCTLR", .state = ARM_CP_STATE_AA32,
184
+ blk_name(s->blk), detail);
425
+ .cp = 15, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
185
+ error_report("%s", error_get_pretty(errp));
426
+ .access = PL2_RW, .resetvalue = 0x0,
186
+ error_free(errp);
427
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.vsctlr),
187
+
428
+ };
188
+ g_free(detail);
429
+ define_one_arm_cp_reg(cpu, &vsctlr);
189
+}
430
+ }
190
+
431
}
191
+static void bbram_bdrv_read(XlnxBBRam *s, Error **errp)
432
192
+{
433
if (cpu_isar_feature(aa64_lor, cpu)) {
193
+ uint32_t *ram = &s->regs[R_BBRAM_0];
434
diff --git a/target/arm/machine.c b/target/arm/machine.c
194
+ int nr = RAM_MAX;
435
index XXXXXXX..XXXXXXX 100644
195
+
436
--- a/target/arm/machine.c
196
+ if (!s->blk) {
437
+++ b/target/arm/machine.c
197
+ return;
438
@@ -XXX,XX +XXX,XX @@ static bool pmsav8_needed(void *opaque)
198
+ }
439
arm_feature(env, ARM_FEATURE_V8);
199
+
440
}
200
+ s->blk_ro = !blk_supports_write_perm(s->blk);
441
201
+ if (!s->blk_ro) {
442
+static bool pmsav8r_needed(void *opaque)
202
+ int rc;
443
+{
203
+
444
+ ARMCPU *cpu = opaque;
204
+ rc = blk_set_perm(s->blk,
445
+ CPUARMState *env = &cpu->env;
205
+ (BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE),
446
+
206
+ BLK_PERM_ALL, NULL);
447
+ return arm_feature(env, ARM_FEATURE_PMSA) &&
207
+ if (rc) {
448
+ arm_feature(env, ARM_FEATURE_V8) &&
208
+ s->blk_ro = true;
449
+ !arm_feature(env, ARM_FEATURE_M);
209
+ }
450
+}
210
+ }
451
+
211
+ if (s->blk_ro) {
452
+static const VMStateDescription vmstate_pmsav8r = {
212
+ warn_report("%s: Skip saving updates to read-only BBRAM backstore.",
453
+ .name = "cpu/pmsav8/pmsav8r",
213
+ blk_name(s->blk));
454
+ .version_id = 1,
214
+ }
455
+ .minimum_version_id = 1,
215
+
456
+ .needed = pmsav8r_needed,
216
+ if (blk_pread(s->blk, 0, ram, nr) < 0) {
457
+ .fields = (VMStateField[]) {
217
+ error_setg(errp,
458
+ VMSTATE_VARRAY_UINT32(env.pmsav8.hprbar, ARMCPU,
218
+ "%s: Failed to read %u bytes from BBRAM backstore.",
459
+ pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t),
219
+ blk_name(s->blk), nr);
460
+ VMSTATE_VARRAY_UINT32(env.pmsav8.hprlar, ARMCPU,
220
+ return;
461
+ pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t),
221
+ }
462
+ VMSTATE_END_OF_LIST()
222
+
223
+ /* Convert from little-endian backstore for each 32-bit word */
224
+ nr /= 4;
225
+ while (nr--) {
226
+ ram[nr] = le32_to_cpu(ram[nr]);
227
+ }
228
+}
229
+
230
+static void bbram_bdrv_sync(XlnxBBRam *s, uint64_t hwaddr)
231
+{
232
+ uint32_t le32;
233
+ unsigned offset;
234
+ int rc;
235
+
236
+ assert(A_BBRAM_0 <= hwaddr && hwaddr <= A_BBRAM_8);
237
+
238
+ /* Backstore is always in little-endian */
239
+ le32 = cpu_to_le32(s->regs[hwaddr / 4]);
240
+
241
+ /* Update zeroized flag */
242
+ if (le32 && (hwaddr != A_BBRAM_8 || s->bbram8_wo)) {
243
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 0);
244
+ }
245
+
246
+ if (!s->blk || s->blk_ro) {
247
+ return;
248
+ }
249
+
250
+ offset = hwaddr - A_BBRAM_0;
251
+ rc = blk_pwrite(s->blk, offset, &le32, 4, 0);
252
+ if (rc < 0) {
253
+ bbram_bdrv_error(s, rc, g_strdup_printf("write to offset %u", offset));
254
+ }
255
+}
256
+
257
+static void bbram_bdrv_zero(XlnxBBRam *s)
258
+{
259
+ int rc;
260
+
261
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 1);
262
+
263
+ if (!s->blk || s->blk_ro) {
264
+ return;
265
+ }
266
+
267
+ rc = blk_make_zero(s->blk, 0);
268
+ if (rc < 0) {
269
+ bbram_bdrv_error(s, rc, g_strdup("zeroizing"));
270
+ }
271
+
272
+ /* Restore bbram8 if it is non-zero */
273
+ if (s->regs[R_BBRAM_8]) {
274
+ bbram_bdrv_sync(s, A_BBRAM_8);
275
+ }
276
+}
277
+
278
+static void bbram_zeroize(XlnxBBRam *s)
279
+{
280
+ int nr = RAM_MAX - (s->bbram8_wo ? 0 : 4); /* only wo bbram8 is cleared */
281
+
282
+ memset(&s->regs[R_BBRAM_0], 0, nr);
283
+ bbram_bdrv_zero(s);
284
+}
285
+
286
+static void bbram_update_irq(XlnxBBRam *s)
287
+{
288
+ bool pending = s->regs[R_BBRAM_ISR] & ~s->regs[R_BBRAM_IMR];
289
+
290
+ qemu_set_irq(s->irq_bbram, pending);
291
+}
292
+
293
+static void bbram_ctrl_postw(RegisterInfo *reg, uint64_t val64)
294
+{
295
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
296
+ uint32_t val = val64;
297
+
298
+ if (val & R_BBRAM_CTRL_ZEROIZE_MASK) {
299
+ bbram_zeroize(s);
300
+ /* The bit is self clearing */
301
+ s->regs[R_BBRAM_CTRL] &= ~R_BBRAM_CTRL_ZEROIZE_MASK;
302
+ }
303
+}
304
+
305
+static void bbram_pgm_mode_postw(RegisterInfo *reg, uint64_t val64)
306
+{
307
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
308
+ uint32_t val = val64;
309
+
310
+ if (val == BBRAM_PGM_MAGIC) {
311
+ bbram_zeroize(s);
312
+
313
+ /* The status bit is cleared only by POR */
314
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, PGM_MODE, 1);
315
+ }
316
+}
317
+
318
+static void bbram_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
319
+{
320
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
321
+ uint32_t calc_crc;
322
+
323
+ if (!bbram_pgm_enabled(s)) {
324
+ /* We are not in programming mode, don't do anything */
325
+ return;
326
+ }
327
+
328
+ /* Perform the AES integrity check */
329
+ s->regs[R_BBRAM_STATUS] |= R_BBRAM_STATUS_AES_CRC_DONE_MASK;
330
+
331
+ /*
332
+ * Set check status.
333
+ *
334
+ * ZynqMP BBRAM check has a zero-u32 prepended; see:
335
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_bbramps_zynqmp.c#L311
336
+ */
337
+ calc_crc = xlnx_efuse_calc_crc(&s->regs[R_BBRAM_0],
338
+ (R_BBRAM_8 - R_BBRAM_0), s->crc_zpads);
339
+
340
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, AES_CRC_PASS,
341
+ (s->regs[R_BBRAM_AES_CRC] == calc_crc));
342
+}
343
+
344
+static uint64_t bbram_key_prew(RegisterInfo *reg, uint64_t val64)
345
+{
346
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
347
+ uint32_t original_data = *(uint32_t *) reg->data;
348
+
349
+ if (bbram_pgm_enabled(s)) {
350
+ return val64;
351
+ } else {
352
+ /* We are not in programming mode, don't do anything */
353
+ qemu_log_mask(LOG_GUEST_ERROR,
354
+ "Not in programming mode, dropping the write\n");
355
+ return original_data;
356
+ }
357
+}
358
+
359
+static void bbram_key_postw(RegisterInfo *reg, uint64_t val64)
360
+{
361
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
362
+
363
+ bbram_bdrv_sync(s, reg->access->addr);
364
+}
365
+
366
+static uint64_t bbram_wo_postr(RegisterInfo *reg, uint64_t val)
367
+{
368
+ return 0;
369
+}
370
+
371
+static uint64_t bbram_r8_postr(RegisterInfo *reg, uint64_t val)
372
+{
373
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
374
+
375
+ return s->bbram8_wo ? bbram_wo_postr(reg, val) : val;
376
+}
377
+
378
+static bool bbram_r8_readonly(XlnxBBRam *s)
379
+{
380
+ return !bbram_pgm_enabled(s) || bbram_msw_locked(s);
381
+}
382
+
383
+static uint64_t bbram_r8_prew(RegisterInfo *reg, uint64_t val64)
384
+{
385
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
386
+
387
+ if (bbram_r8_readonly(s)) {
388
+ val64 = *(uint32_t *)reg->data;
389
+ }
390
+
391
+ return val64;
392
+}
393
+
394
+static void bbram_r8_postw(RegisterInfo *reg, uint64_t val64)
395
+{
396
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
397
+
398
+ if (!bbram_r8_readonly(s)) {
399
+ bbram_bdrv_sync(s, A_BBRAM_8);
400
+ }
401
+}
402
+
403
+static uint64_t bbram_msw_lock_prew(RegisterInfo *reg, uint64_t val64)
404
+{
405
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
406
+
407
+ /* Never lock if bbram8 is wo; and, only POR can clear the lock */
408
+ if (s->bbram8_wo) {
409
+ val64 = 0;
410
+ } else {
411
+ val64 |= s->regs[R_BBRAM_MSW_LOCK];
412
+ }
413
+
414
+ return val64;
415
+}
416
+
417
+static void bbram_isr_postw(RegisterInfo *reg, uint64_t val64)
418
+{
419
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
420
+
421
+ bbram_update_irq(s);
422
+}
423
+
424
+static uint64_t bbram_ier_prew(RegisterInfo *reg, uint64_t val64)
425
+{
426
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
427
+ uint32_t val = val64;
428
+
429
+ s->regs[R_BBRAM_IMR] &= ~val;
430
+ bbram_update_irq(s);
431
+ return 0;
432
+}
433
+
434
+static uint64_t bbram_idr_prew(RegisterInfo *reg, uint64_t val64)
435
+{
436
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
437
+ uint32_t val = val64;
438
+
439
+ s->regs[R_BBRAM_IMR] |= val;
440
+ bbram_update_irq(s);
441
+ return 0;
442
+}
443
+
444
+static RegisterAccessInfo bbram_ctrl_regs_info[] = {
445
+ { .name = "BBRAM_STATUS", .addr = A_BBRAM_STATUS,
446
+ .rsvd = 0xee,
447
+ .ro = 0x3ff,
448
+ },{ .name = "BBRAM_CTRL", .addr = A_BBRAM_CTRL,
449
+ .post_write = bbram_ctrl_postw,
450
+ },{ .name = "PGM_MODE", .addr = A_PGM_MODE,
451
+ .post_write = bbram_pgm_mode_postw,
452
+ },{ .name = "BBRAM_AES_CRC", .addr = A_BBRAM_AES_CRC,
453
+ .post_write = bbram_aes_crc_postw,
454
+ .post_read = bbram_wo_postr,
455
+ },{ .name = "BBRAM_0", .addr = A_BBRAM_0,
456
+ .pre_write = bbram_key_prew,
457
+ .post_write = bbram_key_postw,
458
+ .post_read = bbram_wo_postr,
459
+ },{ .name = "BBRAM_1", .addr = A_BBRAM_1,
460
+ .pre_write = bbram_key_prew,
461
+ .post_write = bbram_key_postw,
462
+ .post_read = bbram_wo_postr,
463
+ },{ .name = "BBRAM_2", .addr = A_BBRAM_2,
464
+ .pre_write = bbram_key_prew,
465
+ .post_write = bbram_key_postw,
466
+ .post_read = bbram_wo_postr,
467
+ },{ .name = "BBRAM_3", .addr = A_BBRAM_3,
468
+ .pre_write = bbram_key_prew,
469
+ .post_write = bbram_key_postw,
470
+ .post_read = bbram_wo_postr,
471
+ },{ .name = "BBRAM_4", .addr = A_BBRAM_4,
472
+ .pre_write = bbram_key_prew,
473
+ .post_write = bbram_key_postw,
474
+ .post_read = bbram_wo_postr,
475
+ },{ .name = "BBRAM_5", .addr = A_BBRAM_5,
476
+ .pre_write = bbram_key_prew,
477
+ .post_write = bbram_key_postw,
478
+ .post_read = bbram_wo_postr,
479
+ },{ .name = "BBRAM_6", .addr = A_BBRAM_6,
480
+ .pre_write = bbram_key_prew,
481
+ .post_write = bbram_key_postw,
482
+ .post_read = bbram_wo_postr,
483
+ },{ .name = "BBRAM_7", .addr = A_BBRAM_7,
484
+ .pre_write = bbram_key_prew,
485
+ .post_write = bbram_key_postw,
486
+ .post_read = bbram_wo_postr,
487
+ },{ .name = "BBRAM_8", .addr = A_BBRAM_8,
488
+ .pre_write = bbram_r8_prew,
489
+ .post_write = bbram_r8_postw,
490
+ .post_read = bbram_r8_postr,
491
+ },{ .name = "BBRAM_SLVERR", .addr = A_BBRAM_SLVERR,
492
+ .rsvd = ~1,
493
+ },{ .name = "BBRAM_ISR", .addr = A_BBRAM_ISR,
494
+ .w1c = 0x1,
495
+ .post_write = bbram_isr_postw,
496
+ },{ .name = "BBRAM_IMR", .addr = A_BBRAM_IMR,
497
+ .ro = 0x1,
498
+ },{ .name = "BBRAM_IER", .addr = A_BBRAM_IER,
499
+ .pre_write = bbram_ier_prew,
500
+ },{ .name = "BBRAM_IDR", .addr = A_BBRAM_IDR,
501
+ .pre_write = bbram_idr_prew,
502
+ },{ .name = "BBRAM_MSW_LOCK", .addr = A_BBRAM_MSW_LOCK,
503
+ .pre_write = bbram_msw_lock_prew,
504
+ .ro = ~R_BBRAM_MSW_LOCK_VAL_MASK,
505
+ }
506
+};
507
+
508
+static void bbram_ctrl_reset(DeviceState *dev)
509
+{
510
+ XlnxBBRam *s = XLNX_BBRAM(dev);
511
+ unsigned int i;
512
+
513
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
514
+ if (i < R_BBRAM_0 || i > R_BBRAM_8) {
515
+ register_reset(&s->regs_info[i]);
516
+ }
517
+ }
518
+
519
+ bbram_update_irq(s);
520
+}
521
+
522
+static const MemoryRegionOps bbram_ctrl_ops = {
523
+ .read = register_read_memory,
524
+ .write = register_write_memory,
525
+ .endianness = DEVICE_LITTLE_ENDIAN,
526
+ .valid = {
527
+ .min_access_size = 4,
528
+ .max_access_size = 4,
529
+ },
463
+ },
530
+};
464
+};
531
+
465
+
532
+static void bbram_ctrl_realize(DeviceState *dev, Error **errp)
466
static const VMStateDescription vmstate_pmsav8 = {
533
+{
467
.name = "cpu/pmsav8",
534
+ XlnxBBRam *s = XLNX_BBRAM(dev);
468
.version_id = 1,
535
+
469
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = {
536
+ if (s->crc_zpads) {
470
VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU),
537
+ s->bbram8_wo = true;
471
VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU),
538
+ }
472
VMSTATE_END_OF_LIST()
539
+
473
+ },
540
+ bbram_bdrv_read(s, errp);
474
+ .subsections = (const VMStateDescription * []) {
541
+}
475
+ &vmstate_pmsav8r,
542
+
476
+ NULL
543
+static void bbram_ctrl_init(Object *obj)
477
}
544
+{
478
};
545
+ XlnxBBRam *s = XLNX_BBRAM(obj);
479
546
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
547
+ RegisterInfoArray *reg_array;
548
+
549
+ reg_array =
550
+ register_init_block32(DEVICE(obj), bbram_ctrl_regs_info,
551
+ ARRAY_SIZE(bbram_ctrl_regs_info),
552
+ s->regs_info, s->regs,
553
+ &bbram_ctrl_ops,
554
+ XLNX_BBRAM_ERR_DEBUG,
555
+ R_MAX * 4);
556
+
557
+ sysbus_init_mmio(sbd, &reg_array->mem);
558
+ sysbus_init_irq(sbd, &s->irq_bbram);
559
+}
560
+
561
+static void bbram_prop_set_drive(Object *obj, Visitor *v, const char *name,
562
+ void *opaque, Error **errp)
563
+{
564
+ DeviceState *dev = DEVICE(obj);
565
+
566
+ qdev_prop_drive.set(obj, v, name, opaque, errp);
567
+
568
+ /* Fill initial data if backend is attached after realized */
569
+ if (dev->realized) {
570
+ bbram_bdrv_read(XLNX_BBRAM(obj), errp);
571
+ }
572
+}
573
+
574
+static void bbram_prop_get_drive(Object *obj, Visitor *v, const char *name,
575
+ void *opaque, Error **errp)
576
+{
577
+ qdev_prop_drive.get(obj, v, name, opaque, errp);
578
+}
579
+
580
+static void bbram_prop_release_drive(Object *obj, const char *name,
581
+ void *opaque)
582
+{
583
+ qdev_prop_drive.release(obj, name, opaque);
584
+}
585
+
586
+static const PropertyInfo bbram_prop_drive = {
587
+ .name = "str",
588
+ .description = "Node name or ID of a block device to use as BBRAM backend",
589
+ .realized_set_allowed = true,
590
+ .get = bbram_prop_get_drive,
591
+ .set = bbram_prop_set_drive,
592
+ .release = bbram_prop_release_drive,
593
+};
594
+
595
+static const VMStateDescription vmstate_bbram_ctrl = {
596
+ .name = TYPE_XLNX_BBRAM,
597
+ .version_id = 1,
598
+ .minimum_version_id = 1,
599
+ .fields = (VMStateField[]) {
600
+ VMSTATE_UINT32_ARRAY(regs, XlnxBBRam, R_MAX),
601
+ VMSTATE_END_OF_LIST(),
602
+ }
603
+};
604
+
605
+static Property bbram_ctrl_props[] = {
606
+ DEFINE_PROP("drive", XlnxBBRam, blk, bbram_prop_drive, BlockBackend *),
607
+ DEFINE_PROP_UINT32("crc-zpads", XlnxBBRam, crc_zpads, 1),
608
+ DEFINE_PROP_END_OF_LIST(),
609
+};
610
+
611
+static void bbram_ctrl_class_init(ObjectClass *klass, void *data)
612
+{
613
+ DeviceClass *dc = DEVICE_CLASS(klass);
614
+
615
+ dc->reset = bbram_ctrl_reset;
616
+ dc->realize = bbram_ctrl_realize;
617
+ dc->vmsd = &vmstate_bbram_ctrl;
618
+ device_class_set_props(dc, bbram_ctrl_props);
619
+}
620
+
621
+static const TypeInfo bbram_ctrl_info = {
622
+ .name = TYPE_XLNX_BBRAM,
623
+ .parent = TYPE_SYS_BUS_DEVICE,
624
+ .instance_size = sizeof(XlnxBBRam),
625
+ .class_init = bbram_ctrl_class_init,
626
+ .instance_init = bbram_ctrl_init,
627
+};
628
+
629
+static void bbram_ctrl_register_types(void)
630
+{
631
+ type_register_static(&bbram_ctrl_info);
632
+}
633
+
634
+type_init(bbram_ctrl_register_types)
635
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
636
index XXXXXXX..XXXXXXX 100644
637
--- a/hw/nvram/Kconfig
638
+++ b/hw/nvram/Kconfig
639
@@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE_VERSAL
640
config XLNX_EFUSE_ZYNQMP
641
bool
642
select XLNX_EFUSE
643
+
644
+config XLNX_BBRAM
645
+ bool
646
+ select XLNX_EFUSE_CRC
647
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
648
index XXXXXXX..XXXXXXX 100644
649
--- a/hw/nvram/meson.build
650
+++ b/hw/nvram/meson.build
651
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
652
'xlnx-versal-efuse-ctrl.c'))
653
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files(
654
'xlnx-zynqmp-efuse.c'))
655
+softmmu_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
656
657
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
658
--
480
--
659
2.20.1
481
2.25.1
660
482
661
483
diff view generated by jsdifflib
[PULL 10/22] hw/arm: xlnx-zcu102: Add Xilinx eFUSE device
[PULL 07/34] target/arm: Add PMSAv8r functionality
1
From: Tong Ho <tong.ho@xilinx.com>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
Connect the support for ZynqMP eFUSE one-time field-programmable
3
Add PMSAv8r translation.
4
bit array.
4
5
5
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
6
The command argument:
7
-drive if=pflash,index=3,...
8
Can be used to optionally connect the bit array to a
9
backend storage, such that field-programmed values
10
in one invocation can be made available to next
11
invocation.
12
13
The backend storage must be a seekable binary file, and
14
its size must be 768 bytes or larger. A file with all
15
binary 0's is a 'blank'.
16
17
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
18
Message-id: 20210917052400.1249094-9-tong.ho@xilinx.com
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20221206102504.165775-7-tobias.roehmel@rwth-aachen.de
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
9
---
22
include/hw/arm/xlnx-zynqmp.h | 3 +++
10
target/arm/ptw.c | 126 ++++++++++++++++++++++++++++++++++++++---------
23
hw/arm/xlnx-zcu102.c | 15 +++++++++++++++
11
1 file changed, 104 insertions(+), 22 deletions(-)
24
hw/arm/xlnx-zynqmp.c | 29 +++++++++++++++++++++++++++++
12
25
hw/Kconfig | 1 +
13
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
26
4 files changed, 48 insertions(+)
27
28
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
29
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/xlnx-zynqmp.h
15
--- a/target/arm/ptw.c
31
+++ b/include/hw/arm/xlnx-zynqmp.h
16
+++ b/target/arm/ptw.c
32
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
33
#include "net/can_emu.h"
18
34
#include "hw/dma/xlnx_csu_dma.h"
19
if (arm_feature(env, ARM_FEATURE_M)) {
35
#include "hw/nvram/xlnx-bbram.h"
20
return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
36
+#include "hw/nvram/xlnx-zynqmp-efuse.h"
21
- } else {
37
22
- return regime_sctlr(env, mmu_idx) & SCTLR_BR;
38
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
23
}
39
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
24
+
40
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
25
+ if (mmu_idx == ARMMMUIdx_Stage2) {
41
MemoryRegion *ddr_ram;
26
+ return false;
42
MemoryRegion ddr_ram_low, ddr_ram_high;
27
+ }
43
XlnxBBRam bbram;
28
+
44
+ XlnxEFuse efuse;
29
+ return regime_sctlr(env, mmu_idx) & SCTLR_BR;
45
+ XlnxZynqMPEFuse efuse_ctrl;
46
47
MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
48
49
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/hw/arm/xlnx-zcu102.c
52
+++ b/hw/arm/xlnx-zcu102.c
53
@@ -XXX,XX +XXX,XX @@ static void bbram_attach_drive(XlnxBBRam *dev)
54
}
55
}
30
}
56
31
57
+static void efuse_attach_drive(XlnxEFuse *dev)
32
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
33
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
34
return !(result->f.prot & (1 << access_type));
35
}
36
37
+static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx,
38
+ uint32_t secure)
58
+{
39
+{
59
+ DriveInfo *dinfo;
40
+ if (regime_el(env, mmu_idx) == 2) {
60
+ BlockBackend *blk;
41
+ return env->pmsav8.hprbar;
61
+
42
+ } else {
62
+ dinfo = drive_get_by_index(IF_PFLASH, 3);
43
+ return env->pmsav8.rbar[secure];
63
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
64
+ if (blk) {
65
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
66
+ }
44
+ }
67
+}
45
+}
68
+
46
+
69
static void xlnx_zcu102_init(MachineState *machine)
47
+static uint32_t *regime_rlar(CPUARMState *env, ARMMMUIdx mmu_idx,
70
{
48
+ uint32_t secure)
71
XlnxZCU102 *s = ZCU102_MACHINE(machine);
49
+{
72
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
50
+ if (regime_el(env, mmu_idx) == 2) {
73
/* Attach bbram backend, if given */
51
+ return env->pmsav8.hprlar;
74
bbram_attach_drive(&s->soc.bbram);
52
+ } else {
75
53
+ return env->pmsav8.rlar[secure];
76
+ /* Attach efuse backend, if given */
54
+ }
77
+ efuse_attach_drive(&s->soc.efuse);
55
+}
78
+
56
+
79
/* Create and plug in the SD cards */
57
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
80
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
58
MMUAccessType access_type, ARMMMUIdx mmu_idx,
81
BusState *bus;
59
bool secure, GetPhysAddrResult *result,
82
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
60
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
83
index XXXXXXX..XXXXXXX 100644
61
bool hit = false;
84
--- a/hw/arm/xlnx-zynqmp.c
62
uint32_t addr_page_base = address & TARGET_PAGE_MASK;
85
+++ b/hw/arm/xlnx-zynqmp.c
63
uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
86
@@ -XXX,XX +XXX,XX @@
64
+ int region_counter;
87
#define BBRAM_ADDR 0xffcd0000
65
+
88
#define BBRAM_IRQ 11
66
+ if (regime_el(env, mmu_idx) == 2) {
89
67
+ region_counter = cpu->pmsav8r_hdregion;
90
+#define EFUSE_ADDR 0xffcc0000
68
+ } else {
91
+#define EFUSE_IRQ 87
69
+ region_counter = cpu->pmsav7_dregion;
92
+
70
+ }
93
#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
71
94
72
result->f.lg_page_size = TARGET_PAGE_BITS;
95
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
73
result->f.phys_addr = address;
96
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
74
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
97
sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
75
*mregion = -1;
76
}
77
78
+ if (mmu_idx == ARMMMUIdx_Stage2) {
79
+ fi->stage2 = true;
80
+ }
81
+
82
/*
83
* Unlike the ARM ARM pseudocode, we don't need to check whether this
84
* was an exception vector read from the vector table (which is always
85
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
86
hit = true;
87
}
88
89
- for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
90
+ uint32_t bitmask;
91
+ if (arm_feature(env, ARM_FEATURE_M)) {
92
+ bitmask = 0x1f;
93
+ } else {
94
+ bitmask = 0x3f;
95
+ fi->level = 0;
96
+ }
97
+
98
+ for (n = region_counter - 1; n >= 0; n--) {
99
/* region search */
100
/*
101
- * Note that the base address is bits [31:5] from the register
102
- * with bits [4:0] all zeroes, but the limit address is bits
103
- * [31:5] from the register with bits [4:0] all ones.
104
+ * Note that the base address is bits [31:x] from the register
105
+ * with bits [x-1:0] all zeroes, but the limit address is bits
106
+ * [31:x] from the register with bits [x:0] all ones. Where x is
107
+ * 5 for Cortex-M and 6 for Cortex-R
108
*/
109
- uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
110
- uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
111
+ uint32_t base = regime_rbar(env, mmu_idx, secure)[n] & ~bitmask;
112
+ uint32_t limit = regime_rlar(env, mmu_idx, secure)[n] | bitmask;
113
114
- if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
115
+ if (!(regime_rlar(env, mmu_idx, secure)[n] & 0x1)) {
116
/* Region disabled */
117
continue;
118
}
119
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
120
* PMSAv7 where highest-numbered-region wins)
121
*/
122
fi->type = ARMFault_Permission;
123
- fi->level = 1;
124
+ if (arm_feature(env, ARM_FEATURE_M)) {
125
+ fi->level = 1;
126
+ }
127
return true;
128
}
129
130
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
131
}
132
133
if (!hit) {
134
- /* background fault */
135
- fi->type = ARMFault_Background;
136
+ if (arm_feature(env, ARM_FEATURE_M)) {
137
+ fi->type = ARMFault_Background;
138
+ } else {
139
+ fi->type = ARMFault_Permission;
140
+ }
141
return true;
142
}
143
144
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
145
/* hit using the background region */
146
get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot);
147
} else {
148
- uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
149
- uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
150
+ uint32_t matched_rbar = regime_rbar(env, mmu_idx, secure)[matchregion];
151
+ uint32_t matched_rlar = regime_rlar(env, mmu_idx, secure)[matchregion];
152
+ uint32_t ap = extract32(matched_rbar, 1, 2);
153
+ uint32_t xn = extract32(matched_rbar, 0, 1);
154
bool pxn = false;
155
156
if (arm_feature(env, ARM_FEATURE_V8_1M)) {
157
- pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
158
+ pxn = extract32(matched_rlar, 4, 1);
159
}
160
161
if (m_is_system_region(env, address)) {
162
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
163
xn = 1;
164
}
165
166
- result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
167
+ if (regime_el(env, mmu_idx) == 2) {
168
+ result->f.prot = simple_ap_to_rw_prot_is_user(ap,
169
+ mmu_idx != ARMMMUIdx_E2);
170
+ } else {
171
+ result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
172
+ }
173
+
174
+ if (!arm_feature(env, ARM_FEATURE_M)) {
175
+ uint8_t attrindx = extract32(matched_rlar, 1, 3);
176
+ uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
177
+ uint8_t sh = extract32(matched_rlar, 3, 2);
178
+
179
+ if (regime_sctlr(env, mmu_idx) & SCTLR_WXN &&
180
+ result->f.prot & PAGE_WRITE && mmu_idx != ARMMMUIdx_Stage2) {
181
+ xn = 0x1;
182
+ }
183
+
184
+ if ((regime_el(env, mmu_idx) == 1) &&
185
+ regime_sctlr(env, mmu_idx) & SCTLR_UWXN && ap == 0x1) {
186
+ pxn = 0x1;
187
+ }
188
+
189
+ result->cacheattrs.is_s2_format = false;
190
+ result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
191
+ result->cacheattrs.shareability = sh;
192
+ }
193
+
194
if (result->f.prot && !xn && !(pxn && !is_user)) {
195
result->f.prot |= PAGE_EXEC;
196
}
197
- /*
198
- * We don't need to look the attribute up in the MAIR0/MAIR1
199
- * registers because that only tells us about cacheability.
200
- */
201
+
202
if (mregion) {
203
*mregion = matchregion;
204
}
205
}
206
207
fi->type = ARMFault_Permission;
208
- fi->level = 1;
209
+ if (arm_feature(env, ARM_FEATURE_M)) {
210
+ fi->level = 1;
211
+ }
212
return !(result->f.prot & (1 << access_type));
98
}
213
}
99
214
100
+static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
215
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
101
+{
216
cacheattrs1 = result->cacheattrs;
102
+ Object *bits = OBJECT(&s->efuse);
217
memset(result, 0, sizeof(*result));
103
+ Object *ctrl = OBJECT(&s->efuse_ctrl);
218
104
+ SysBusDevice *sbd;
219
- ret = get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result, fi);
105
+
220
+ if (arm_feature(env, ARM_FEATURE_PMSA)) {
106
+ object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl,
221
+ ret = get_phys_addr_pmsav8(env, ipa, access_type,
107
+ TYPE_XLNX_ZYNQMP_EFUSE);
222
+ ptw->in_mmu_idx, is_secure, result, fi);
108
+
223
+ } else {
109
+ object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits,
224
+ ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
110
+ sizeof(s->efuse),
225
+ is_el0, result, fi);
111
+ TYPE_XLNX_EFUSE, &error_abort,
226
+ }
112
+ "efuse-nr", "3",
227
fi->s2addr = ipa;
113
+ "efuse-size", "2048",
228
114
+ NULL);
229
/* Combine the S1 and S2 perms. */
115
+
116
+ qdev_realize(DEVICE(bits), NULL, &error_abort);
117
+ object_property_set_link(ctrl, "efuse", bits, &error_abort);
118
+
119
+ sbd = SYS_BUS_DEVICE(ctrl);
120
+ sysbus_realize(sbd, &error_abort);
121
+ sysbus_mmio_map(sbd, 0, EFUSE_ADDR);
122
+ sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
123
+}
124
+
125
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
126
{
127
static const struct UnimpInfo {
128
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
129
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
130
131
xlnx_zynqmp_create_bbram(s, gic_spi);
132
+ xlnx_zynqmp_create_efuse(s, gic_spi);
133
xlnx_zynqmp_create_unimp_mmio(s);
134
135
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
136
diff --git a/hw/Kconfig b/hw/Kconfig
137
index XXXXXXX..XXXXXXX 100644
138
--- a/hw/Kconfig
139
+++ b/hw/Kconfig
140
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP
141
select CAN_BUS
142
select PTIMER
143
select XLNX_BBRAM
144
+ select XLNX_EFUSE_ZYNQMP
145
--
230
--
146
2.20.1
231
2.25.1
147
232
148
233
diff view generated by jsdifflib
[PULL 15/22] target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML
[PULL 08/34] target/arm: Add ARM Cortex-R52 CPU
1
Currently we send VFP XML which includes D0..D15 or D0..D31, plus
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
FPSID, FPSCR and FPEXC. The upstream GDB tolerates this, but its
3
definition of this XML feature does not include FPSID or FPEXC. In
4
particular, for M-profile cores there are no FPSID or FPEXC
5
registers, so advertising those is wrong.
6
2
7
Move FPSID and FPEXC into their own bit of XML which we only send for
3
All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
8
A and R profile cores. This brings our definition of the XML
9
org.gnu.gdb.arm.vfp feature into line with GDB's own (at least for
10
non-Neon cores...) and means we don't claim to have FPSID and FPEXC
11
on M-profile.
12
4
13
(It seems unlikely to me that any gdbstub users really care about
5
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
14
being able to look at FPEXC and FPSID; but we've supplied them to gdb
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
for a decade and it's not hard to keep doing so.)
7
Message-id: 20221206102504.165775-8-tobias.roehmel@rwth-aachen.de
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++
11
1 file changed, 42 insertions(+)
16
12
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20210921162901.17508-5-peter.maydell@linaro.org
20
---
21
configs/targets/aarch64-softmmu.mak | 2 +-
22
configs/targets/arm-linux-user.mak | 2 +-
23
configs/targets/arm-softmmu.mak | 2 +-
24
configs/targets/armeb-linux-user.mak | 2 +-
25
target/arm/gdbstub.c | 56 ++++++++++++++++++++--------
26
gdb-xml/arm-neon.xml | 2 -
27
gdb-xml/arm-vfp-sysregs.xml | 17 +++++++++
28
gdb-xml/arm-vfp.xml | 2 -
29
gdb-xml/arm-vfp3.xml | 2 -
30
9 files changed, 61 insertions(+), 26 deletions(-)
31
create mode 100644 gdb-xml/arm-vfp-sysregs.xml
32
33
diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
34
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
35
--- a/configs/targets/aarch64-softmmu.mak
15
--- a/target/arm/cpu_tcg.c
36
+++ b/configs/targets/aarch64-softmmu.mak
16
+++ b/target/arm/cpu_tcg.c
37
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
38
TARGET_ARCH=aarch64
18
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
39
TARGET_BASE_ARCH=arm
40
TARGET_SUPPORTS_MTTCG=y
41
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
42
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
43
TARGET_NEED_FDT=y
44
diff --git a/configs/targets/arm-linux-user.mak b/configs/targets/arm-linux-user.mak
45
index XXXXXXX..XXXXXXX 100644
46
--- a/configs/targets/arm-linux-user.mak
47
+++ b/configs/targets/arm-linux-user.mak
48
@@ -XXX,XX +XXX,XX @@
49
TARGET_ARCH=arm
50
TARGET_SYSTBL_ABI=common,oabi
51
TARGET_SYSTBL=syscall.tbl
52
-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
53
+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
54
TARGET_HAS_BFLT=y
55
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
56
diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.mak
57
index XXXXXXX..XXXXXXX 100644
58
--- a/configs/targets/arm-softmmu.mak
59
+++ b/configs/targets/arm-softmmu.mak
60
@@ -XXX,XX +XXX,XX @@
61
TARGET_ARCH=arm
62
TARGET_SUPPORTS_MTTCG=y
63
-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
64
+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
65
TARGET_NEED_FDT=y
66
diff --git a/configs/targets/armeb-linux-user.mak b/configs/targets/armeb-linux-user.mak
67
index XXXXXXX..XXXXXXX 100644
68
--- a/configs/targets/armeb-linux-user.mak
69
+++ b/configs/targets/armeb-linux-user.mak
70
@@ -XXX,XX +XXX,XX @@ TARGET_ARCH=arm
71
TARGET_SYSTBL_ABI=common,oabi
72
TARGET_SYSTBL=syscall.tbl
73
TARGET_WORDS_BIGENDIAN=y
74
-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
75
+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
76
TARGET_HAS_BFLT=y
77
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
78
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/target/arm/gdbstub.c
81
+++ b/target/arm/gdbstub.c
82
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
83
}
84
switch (reg - nregs) {
85
case 0:
86
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
87
- case 1:
88
return gdb_get_reg32(buf, vfp_get_fpscr(env));
89
- case 2:
90
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
91
}
92
return 0;
93
}
19
}
94
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
20
95
}
21
+static void cortex_r52_initfn(Object *obj)
96
}
22
+{
97
switch (reg - nregs) {
23
+ ARMCPU *cpu = ARM_CPU(obj);
98
+ case 0:
24
+
99
+ vfp_set_fpscr(env, ldl_p(buf));
25
+ set_feature(&cpu->env, ARM_FEATURE_V8);
100
+ return 4;
26
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
101
+ }
27
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
102
+ return 0;
28
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
29
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
30
+ cpu->midr = 0x411fd133; /* r1p3 */
31
+ cpu->revidr = 0x00000000;
32
+ cpu->reset_fpsid = 0x41034023;
33
+ cpu->isar.mvfr0 = 0x10110222;
34
+ cpu->isar.mvfr1 = 0x12111111;
35
+ cpu->isar.mvfr2 = 0x00000043;
36
+ cpu->ctr = 0x8144c004;
37
+ cpu->reset_sctlr = 0x30c50838;
38
+ cpu->isar.id_pfr0 = 0x00000131;
39
+ cpu->isar.id_pfr1 = 0x10111001;
40
+ cpu->isar.id_dfr0 = 0x03010006;
41
+ cpu->id_afr0 = 0x00000000;
42
+ cpu->isar.id_mmfr0 = 0x00211040;
43
+ cpu->isar.id_mmfr1 = 0x40000000;
44
+ cpu->isar.id_mmfr2 = 0x01200000;
45
+ cpu->isar.id_mmfr3 = 0xf0102211;
46
+ cpu->isar.id_mmfr4 = 0x00000010;
47
+ cpu->isar.id_isar0 = 0x02101110;
48
+ cpu->isar.id_isar1 = 0x13112111;
49
+ cpu->isar.id_isar2 = 0x21232142;
50
+ cpu->isar.id_isar3 = 0x01112131;
51
+ cpu->isar.id_isar4 = 0x00010142;
52
+ cpu->isar.id_isar5 = 0x00010001;
53
+ cpu->isar.dbgdidr = 0x77168000;
54
+ cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
55
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
56
+ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
57
+
58
+ cpu->pmsav7_dregion = 16;
59
+ cpu->pmsav8r_hdregion = 16;
103
+}
60
+}
104
+
61
+
105
+static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
62
static void cortex_r5f_initfn(Object *obj)
106
+{
63
{
107
+ switch (reg) {
64
ARMCPU *cpu = ARM_CPU(obj);
108
+ case 0:
65
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {
109
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
66
.class_init = arm_v7m_class_init },
110
+ case 1:
67
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
111
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
68
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
112
+ }
69
+ { .name = "cortex-r52", .initfn = cortex_r52_initfn },
113
+ return 0;
70
{ .name = "ti925t", .initfn = ti925t_initfn },
114
+}
71
{ .name = "sa1100", .initfn = sa1100_initfn },
115
+
72
{ .name = "sa1110", .initfn = sa1110_initfn },
116
+static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
117
+{
118
+ switch (reg) {
119
case 0:
120
env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
121
return 4;
122
case 1:
123
- vfp_set_fpscr(env, ldl_p(buf));
124
- return 4;
125
- case 2:
126
env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
127
return 4;
128
}
129
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
130
34, "aarch64-fpu.xml", 0);
131
}
132
#endif
133
- } else if (arm_feature(env, ARM_FEATURE_NEON)) {
134
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
135
- 51, "arm-neon.xml", 0);
136
- } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
137
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
138
- 35, "arm-vfp3.xml", 0);
139
- } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
140
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
141
- 19, "arm-vfp.xml", 0);
142
+ } else {
143
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
144
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
145
+ 49, "arm-neon.xml", 0);
146
+ } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
147
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
148
+ 33, "arm-vfp3.xml", 0);
149
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
150
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
151
+ 17, "arm-vfp.xml", 0);
152
+ }
153
+ if (!arm_feature(env, ARM_FEATURE_M)) {
154
+ /*
155
+ * A and R profile have FP sysregs FPEXC and FPSID that we
156
+ * expose to gdb.
157
+ */
158
+ gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_sysreg,
159
+ 2, "arm-vfp-sysregs.xml", 0);
160
+ }
161
}
162
gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
163
arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
164
diff --git a/gdb-xml/arm-neon.xml b/gdb-xml/arm-neon.xml
165
index XXXXXXX..XXXXXXX 100644
166
--- a/gdb-xml/arm-neon.xml
167
+++ b/gdb-xml/arm-neon.xml
168
@@ -XXX,XX +XXX,XX @@
169
<reg name="q14" bitsize="128" type="neon_q"/>
170
<reg name="q15" bitsize="128" type="neon_q"/>
171
172
- <reg name="fpsid" bitsize="32" type="int" group="float"/>
173
<reg name="fpscr" bitsize="32" type="int" group="float"/>
174
- <reg name="fpexc" bitsize="32" type="int" group="float"/>
175
</feature>
176
diff --git a/gdb-xml/arm-vfp-sysregs.xml b/gdb-xml/arm-vfp-sysregs.xml
177
new file mode 100644
178
index XXXXXXX..XXXXXXX
179
--- /dev/null
180
+++ b/gdb-xml/arm-vfp-sysregs.xml
181
@@ -XXX,XX +XXX,XX @@
182
+<?xml version="1.0"?>
183
+<!-- Copyright (C) 2021 Linaro Ltd.
184
+
185
+ Copying and distribution of this file, with or without modification,
186
+ are permitted in any medium without royalty provided the copyright
187
+ notice and this notice are preserved.
188
+
189
+ These are A/R profile VFP system registers. Debugger users probably
190
+ don't really care about these, but because we used to (incorrectly)
191
+ provide them to gdb in the org.gnu.gdb.arm.vfp XML we continue
192
+ to do so via this separate XML.
193
+ -->
194
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
195
+<feature name="org.qemu.gdb.arm.vfp-sysregs">
196
+ <reg name="fpsid" bitsize="32" type="int" group="float"/>
197
+ <reg name="fpexc" bitsize="32" type="int" group="float"/>
198
+</feature>
199
diff --git a/gdb-xml/arm-vfp.xml b/gdb-xml/arm-vfp.xml
200
index XXXXXXX..XXXXXXX 100644
201
--- a/gdb-xml/arm-vfp.xml
202
+++ b/gdb-xml/arm-vfp.xml
203
@@ -XXX,XX +XXX,XX @@
204
<reg name="d14" bitsize="64" type="float"/>
205
<reg name="d15" bitsize="64" type="float"/>
206
207
- <reg name="fpsid" bitsize="32" type="int" group="float"/>
208
<reg name="fpscr" bitsize="32" type="int" group="float"/>
209
- <reg name="fpexc" bitsize="32" type="int" group="float"/>
210
</feature>
211
diff --git a/gdb-xml/arm-vfp3.xml b/gdb-xml/arm-vfp3.xml
212
index XXXXXXX..XXXXXXX 100644
213
--- a/gdb-xml/arm-vfp3.xml
214
+++ b/gdb-xml/arm-vfp3.xml
215
@@ -XXX,XX +XXX,XX @@
216
<reg name="d30" bitsize="64" type="float"/>
217
<reg name="d31" bitsize="64" type="float"/>
218
219
- <reg name="fpsid" bitsize="32" type="int" group="float"/>
220
<reg name="fpscr" bitsize="32" type="int" group="float"/>
221
- <reg name="fpexc" bitsize="32" type="int" group="float"/>
222
</feature>
223
--
73
--
224
2.20.1
74
2.25.1
225
75
226
76
diff view generated by jsdifflib
[PULL 01/22] allwinner-h3: Switch to SMC as PSCI conduit
[PULL 09/34] target/arm: fix handling of HLT semihosting in system mode
1
From: Alexander Graf <agraf@csgraf.de>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
The Allwinner H3 SoC uses Cortex-A7 cores which support virtualization.
3
The check semihosting_enabled() wants to know if the guest is
4
However, today we are configuring QEMU to use HVC as PSCI conduit.
4
currently in user mode. Unlike the other cases the test was inverted
5
causing us to block semihosting calls in non-EL0 modes.
5
6
6
That means HVC calls get trapped into QEMU instead of the guest's own
7
Cc: qemu-stable@nongnu.org
7
emulated CPU and thus break the guest's ability to execute virtualization.
8
Fixes: 19b26317e9 (target/arm: Honour -semihosting-config userspace=on)
8
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Fix this by moving to SMC as conduit, freeing up HYP completely to the VM.
10
11
Signed-off-by: Alexander Graf <agraf@csgraf.de>
12
Message-id: 20210920203931.66527-1-agraf@csgraf.de
13
Fixes: 740dafc0ba0 ("hw/arm: add Allwinner H3 System-on-Chip")
14
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
15
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
12
---
20
hw/arm/allwinner-h3.c | 2 +-
13
target/arm/translate.c | 2 +-
21
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
22
15
23
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
16
diff --git a/target/arm/translate.c b/target/arm/translate.c
24
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/allwinner-h3.c
18
--- a/target/arm/translate.c
26
+++ b/hw/arm/allwinner-h3.c
19
+++ b/target/arm/translate.c
27
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
20
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
28
21
* semihosting, to provide some semblance of security
29
/* Provide Power State Coordination Interface */
22
* (and for consistency with our 32-bit semihosting).
30
qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
23
*/
31
- QEMU_PSCI_CONDUIT_HVC);
24
- if (semihosting_enabled(s->current_el != 0) &&
32
+ QEMU_PSCI_CONDUIT_SMC);
25
+ if (semihosting_enabled(s->current_el == 0) &&
33
26
(imm == (s->thumb ? 0x3c : 0xf000))) {
34
/* Disable secondary CPUs */
27
gen_exception_internal_insn(s, EXCP_SEMIHOST);
35
qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
28
return;
36
--
29
--
37
2.20.1
30
2.25.1
38
31
39
32
diff view generated by jsdifflib
[PULL 09/22] hw/arm: xlnx-zcu102: Add Xilinx BBRAM device
[PULL 10/34] hw/timer/imx_epit: improve comments
1
From: Tong Ho <tong.ho@xilinx.com>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM)
3
Fix typos, add background information
4
4
5
The command argument:
5
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
6
-drive if=pflash,index=2,...
7
Can be used to optionally connect the bbram to a backend
8
storage, such that field-programmed values in one
9
invocation can be made available to next invocation.
10
11
The backend storage must be a seekable binary file, and
12
its size must be 36 bytes or larger. A file with all
13
binary 0's is a 'blank'.
14
15
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
16
Message-id: 20210917052400.1249094-8-tong.ho@xilinx.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
8
---
20
include/hw/arm/xlnx-zynqmp.h | 2 ++
9
hw/timer/imx_epit.c | 20 ++++++++++++++++----
21
hw/arm/xlnx-zcu102.c | 15 +++++++++++++++
10
1 file changed, 16 insertions(+), 4 deletions(-)
22
hw/arm/xlnx-zynqmp.c | 20 ++++++++++++++++++++
23
hw/Kconfig | 1 +
24
4 files changed, 38 insertions(+)
25
11
26
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
12
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
27
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/xlnx-zynqmp.h
14
--- a/hw/timer/imx_epit.c
29
+++ b/include/hw/arm/xlnx-zynqmp.h
15
+++ b/hw/timer/imx_epit.c
30
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
31
#include "qom/object.h"
32
#include "net/can_emu.h"
33
#include "hw/dma/xlnx_csu_dma.h"
34
+#include "hw/nvram/xlnx-bbram.h"
35
36
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
37
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
38
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
39
40
MemoryRegion *ddr_ram;
41
MemoryRegion ddr_ram_low, ddr_ram_high;
42
+ XlnxBBRam bbram;
43
44
MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
45
46
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/xlnx-zcu102.c
49
+++ b/hw/arm/xlnx-zcu102.c
50
@@ -XXX,XX +XXX,XX @@ static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt)
51
}
17
}
52
}
18
}
53
19
54
+static void bbram_attach_drive(XlnxBBRam *dev)
20
+/*
55
+{
21
+ * This is called both on hardware (device) reset and software reset.
56
+ DriveInfo *dinfo;
22
+ */
57
+ BlockBackend *blk;
23
static void imx_epit_reset(DeviceState *dev)
58
+
59
+ dinfo = drive_get_by_index(IF_PFLASH, 2);
60
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
61
+ if (blk) {
62
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
63
+ }
64
+}
65
+
66
static void xlnx_zcu102_init(MachineState *machine)
67
{
24
{
68
XlnxZCU102 *s = ZCU102_MACHINE(machine);
25
IMXEPITState *s = IMX_EPIT(dev);
69
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
26
70
27
- /*
71
qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
28
- * Soft reset doesn't touch some bits; hard reset clears them
72
29
- */
73
+ /* Attach bbram backend, if given */
30
+ /* Soft reset doesn't touch some bits; hard reset clears them */
74
+ bbram_attach_drive(&s->soc.bbram);
31
s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
75
+
32
s->sr = 0;
76
/* Create and plug in the SD cards */
33
s->lr = EPIT_TIMER_MAX;
77
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
34
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
78
BusState *bus;
35
ptimer_transaction_begin(s->timer_cmp);
79
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
36
ptimer_transaction_begin(s->timer_reload);
80
index XXXXXXX..XXXXXXX 100644
37
81
--- a/hw/arm/xlnx-zynqmp.c
38
+ /* Update the frequency. Has been done already in case of a reset. */
82
+++ b/hw/arm/xlnx-zynqmp.c
39
if (!(s->cr & CR_SWR)) {
83
@@ -XXX,XX +XXX,XX @@
40
imx_epit_set_freq(s);
84
#define RTC_ADDR 0xffa60000
41
}
85
#define RTC_IRQ 26
42
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
86
43
break;
87
+#define BBRAM_ADDR 0xffcd0000
44
88
+#define BBRAM_IRQ 11
45
case 1: /* SR - ACK*/
89
+
46
- /* writing 1 to OCIF clear the OCIF bit */
90
#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
47
+ /* writing 1 to OCIF clears the OCIF bit */
91
48
if (value & 0x01) {
92
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
49
s->sr = 0;
93
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
50
imx_epit_update_int(s);
94
qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
51
@@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp)
52
0x00001000);
53
sysbus_init_mmio(sbd, &s->iomem);
54
55
+ /*
56
+ * The reload timer keeps running when the peripheral is enabled. It is a
57
+ * kind of wall clock that does not generate any interrupts. The callback
58
+ * needs to be provided, but it does nothing as the ptimer already supports
59
+ * all necessary reloading functionality.
60
+ */
61
s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY);
62
63
+ /*
64
+ * The compare timer is running only when the peripheral configuration is
65
+ * in a state that will generate compare interrupts.
66
+ */
67
s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
95
}
68
}
96
69
97
+static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
98
+{
99
+ SysBusDevice *sbd;
100
+
101
+ object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram,
102
+ sizeof(s->bbram), TYPE_XLNX_BBRAM,
103
+ &error_fatal,
104
+ "crc-zpads", "1",
105
+ NULL);
106
+ sbd = SYS_BUS_DEVICE(&s->bbram);
107
+
108
+ sysbus_realize(sbd, &error_fatal);
109
+ sysbus_mmio_map(sbd, 0, BBRAM_ADDR);
110
+ sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
111
+}
112
+
113
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
114
{
115
static const struct UnimpInfo {
116
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
117
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
118
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
119
120
+ xlnx_zynqmp_create_bbram(s, gic_spi);
121
xlnx_zynqmp_create_unimp_mmio(s);
122
123
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
124
diff --git a/hw/Kconfig b/hw/Kconfig
125
index XXXXXXX..XXXXXXX 100644
126
--- a/hw/Kconfig
127
+++ b/hw/Kconfig
128
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP
129
select REGISTER
130
select CAN_BUS
131
select PTIMER
132
+ select XLNX_BBRAM
133
--
70
--
134
2.20.1
71
2.25.1
135
136
diff view generated by jsdifflib
New patch
[PULL 11/34] hw/timer/imx_epit: cleanup CR defines
1
From: Axel Heider <axel.heider@hensoldt.net>
1
2
3
remove unused defines, add needed defines
4
5
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
include/hw/timer/imx_epit.h | 4 ++--
10
hw/timer/imx_epit.c | 4 ++--
11
2 files changed, 4 insertions(+), 4 deletions(-)
12
13
diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/timer/imx_epit.h
16
+++ b/include/hw/timer/imx_epit.h
17
@@ -XXX,XX +XXX,XX @@
18
#define CR_OCIEN (1 << 2)
19
#define CR_RLD (1 << 3)
20
#define CR_PRESCALE_SHIFT (4)
21
-#define CR_PRESCALE_MASK (0xfff)
22
+#define CR_PRESCALE_BITS (12)
23
#define CR_SWR (1 << 16)
24
#define CR_IOVW (1 << 17)
25
#define CR_DBGEN (1 << 18)
26
@@ -XXX,XX +XXX,XX @@
27
#define CR_DOZEN (1 << 20)
28
#define CR_STOPEN (1 << 21)
29
#define CR_CLKSRC_SHIFT (24)
30
-#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT)
31
+#define CR_CLKSRC_BITS (2)
32
33
#define EPIT_TIMER_MAX 0XFFFFFFFFUL
34
35
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/timer/imx_epit.c
38
+++ b/hw/timer/imx_epit.c
39
@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
40
uint32_t clksrc;
41
uint32_t prescaler;
42
43
- clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, 2);
44
- prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12);
45
+ clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
46
+ prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
47
48
s->freq = imx_ccm_get_clock_frequency(s->ccm,
49
imx_epit_clocks[clksrc]) / prescaler;
50
--
51
2.25.1
diff view generated by jsdifflib
New patch
[PULL 12/34] hw/timer/imx_epit: define SR_OCIF
1
From: Axel Heider <axel.heider@hensoldt.net>
1
2
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
---
6
include/hw/timer/imx_epit.h | 2 ++
7
hw/timer/imx_epit.c | 12 ++++++------
8
2 files changed, 8 insertions(+), 6 deletions(-)
9
10
diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
11
index XXXXXXX..XXXXXXX 100644
12
--- a/include/hw/timer/imx_epit.h
13
+++ b/include/hw/timer/imx_epit.h
14
@@ -XXX,XX +XXX,XX @@
15
#define CR_CLKSRC_SHIFT (24)
16
#define CR_CLKSRC_BITS (2)
17
18
+#define SR_OCIF (1 << 0)
19
+
20
#define EPIT_TIMER_MAX 0XFFFFFFFFUL
21
22
#define TYPE_IMX_EPIT "imx.epit"
23
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/timer/imx_epit.c
26
+++ b/hw/timer/imx_epit.c
27
@@ -XXX,XX +XXX,XX @@ static const IMXClk imx_epit_clocks[] = {
28
*/
29
static void imx_epit_update_int(IMXEPITState *s)
30
{
31
- if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
32
+ if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
33
qemu_irq_raise(s->irq);
34
} else {
35
qemu_irq_lower(s->irq);
36
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
37
break;
38
39
case 1: /* SR - ACK*/
40
- /* writing 1 to OCIF clears the OCIF bit */
41
- if (value & 0x01) {
42
- s->sr = 0;
43
+ /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
44
+ if (value & SR_OCIF) {
45
+ s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
46
imx_epit_update_int(s);
47
}
48
break;
49
@@ -XXX,XX +XXX,XX @@ static void imx_epit_cmp(void *opaque)
50
IMXEPITState *s = IMX_EPIT(opaque);
51
52
DPRINTF("sr was %d\n", s->sr);
53
-
54
- s->sr = 1;
55
+ /* Set interrupt status bit SR.OCIF and update the interrupt state */
56
+ s->sr |= SR_OCIF;
57
imx_epit_update_int(s);
58
}
59
60
--
61
2.25.1
diff view generated by jsdifflib
New patch
[PULL 13/34] hw/timer/imx_epit: update interrupt state on CR write access
1
From: Axel Heider <axel.heider@hensoldt.net>
1
2
3
The interrupt state can change due to:
4
- reset clears both SR.OCIF and CR.OCIE
5
- write to CR.EN or CR.OCIE
6
7
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/timer/imx_epit.c | 16 ++++++++++++----
12
1 file changed, 12 insertions(+), 4 deletions(-)
13
14
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/timer/imx_epit.c
17
+++ b/hw/timer/imx_epit.c
18
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
19
if (s->cr & CR_SWR) {
20
/* handle the reset */
21
imx_epit_reset(DEVICE(s));
22
- /*
23
- * TODO: could we 'break' here? following operations appear
24
- * to duplicate the work imx_epit_reset() already did.
25
- */
26
}
27
28
+ /*
29
+ * The interrupt state can change due to:
30
+ * - reset clears both SR.OCIF and CR.OCIE
31
+ * - write to CR.EN or CR.OCIE
32
+ */
33
+ imx_epit_update_int(s);
34
+
35
+ /*
36
+ * TODO: could we 'break' here for reset? following operations appear
37
+ * to duplicate the work imx_epit_reset() already did.
38
+ */
39
+
40
ptimer_transaction_begin(s->timer_cmp);
41
ptimer_transaction_begin(s->timer_reload);
42
43
--
44
2.25.1
diff view generated by jsdifflib
New patch
[PULL 14/34] hw/timer/imx_epit: hard reset initializes CR with 0
1
From: Axel Heider <axel.heider@hensoldt.net>
1
2
3
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
---
7
hw/timer/imx_epit.c | 20 ++++++++++++++------
8
1 file changed, 14 insertions(+), 6 deletions(-)
9
10
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/timer/imx_epit.c
13
+++ b/hw/timer/imx_epit.c
14
@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
15
/*
16
* This is called both on hardware (device) reset and software reset.
17
*/
18
-static void imx_epit_reset(DeviceState *dev)
19
+static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset)
20
{
21
- IMXEPITState *s = IMX_EPIT(dev);
22
-
23
/* Soft reset doesn't touch some bits; hard reset clears them */
24
- s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
25
+ if (is_hard_reset) {
26
+ s->cr = 0;
27
+ } else {
28
+ s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
29
+ }
30
s->sr = 0;
31
s->lr = EPIT_TIMER_MAX;
32
s->cmp = 0;
33
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
34
s->cr = value & 0x03ffffff;
35
if (s->cr & CR_SWR) {
36
/* handle the reset */
37
- imx_epit_reset(DEVICE(s));
38
+ imx_epit_reset(s, false);
39
}
40
41
/*
42
@@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp)
43
s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
44
}
45
46
+static void imx_epit_dev_reset(DeviceState *dev)
47
+{
48
+ IMXEPITState *s = IMX_EPIT(dev);
49
+ imx_epit_reset(s, true);
50
+}
51
+
52
static void imx_epit_class_init(ObjectClass *klass, void *data)
53
{
54
DeviceClass *dc = DEVICE_CLASS(klass);
55
56
dc->realize = imx_epit_realize;
57
- dc->reset = imx_epit_reset;
58
+ dc->reset = imx_epit_dev_reset;
59
dc->vmsd = &vmstate_imx_timer_epit;
60
dc->desc = "i.MX periodic timer";
61
}
62
--
63
2.25.1
diff view generated by jsdifflib
[PULL 07/22] hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device
[PULL 15/34] hw/timer/imx_epit: factor out register write handlers
1
From: Tong Ho <tong.ho@xilinx.com>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
Connect the support for Versal Battery-Backed RAM (BBRAM)
3
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
4
5
The command argument:
6
-drive if=pflash,index=0,...
7
Can be used to optionally connect the bbram to a backend
8
storage, such that field-programmed values in one
9
invocation can be made available to next invocation.
10
11
The backend storage must be a seekable binary file, and
12
its size must be 36 bytes or larger. A file with all
13
binary 0's is a 'blank'.
14
15
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
16
Message-id: 20210917052400.1249094-6-tong.ho@xilinx.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
6
---
20
include/hw/arm/xlnx-versal.h | 5 +++++
7
hw/timer/imx_epit.c | 215 ++++++++++++++++++++++++--------------------
21
hw/arm/xlnx-versal-virt.c | 36 ++++++++++++++++++++++++++++++++++++
8
1 file changed, 117 insertions(+), 98 deletions(-)
22
hw/arm/xlnx-versal.c | 18 ++++++++++++++++++
23
hw/arm/Kconfig | 1 +
24
4 files changed, 60 insertions(+)
25
9
26
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
10
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
27
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/xlnx-versal.h
12
--- a/hw/timer/imx_epit.c
29
+++ b/include/hw/arm/xlnx-versal.h
13
+++ b/hw/timer/imx_epit.c
30
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
31
#include "qom/object.h"
32
#include "hw/usb/xlnx-usb-subsystem.h"
33
#include "hw/misc/xlnx-versal-xramc.h"
34
+#include "hw/nvram/xlnx-bbram.h"
35
36
#define TYPE_XLNX_VERSAL "xlnx-versal"
37
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
38
@@ -XXX,XX +XXX,XX @@ struct Versal {
39
} iou;
40
41
XlnxZynqMPRTC rtc;
42
+ XlnxBBRam bbram;
43
} pmc;
44
45
struct {
46
@@ -XXX,XX +XXX,XX @@ struct Versal {
47
#define VERSAL_GEM1_WAKE_IRQ_0 59
48
#define VERSAL_ADMA_IRQ_0 60
49
#define VERSAL_XRAM_IRQ_0 79
50
+#define VERSAL_BBRAM_APB_IRQ_0 121
51
#define VERSAL_RTC_APB_ERR_IRQ 121
52
#define VERSAL_SD0_IRQ_0 126
53
#define VERSAL_RTC_ALARM_IRQ 142
54
@@ -XXX,XX +XXX,XX @@ struct Versal {
55
56
#define MM_PMC_SD0 0xf1040000U
57
#define MM_PMC_SD0_SIZE 0x10000
58
+#define MM_PMC_BBRAM_CTRL 0xf11f0000
59
+#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
60
#define MM_PMC_CRP 0xf1260000U
61
#define MM_PMC_CRP_SIZE 0x10000
62
#define MM_PMC_RTC 0xf12a0000
63
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/arm/xlnx-versal-virt.c
66
+++ b/hw/arm/xlnx-versal-virt.c
67
@@ -XXX,XX +XXX,XX @@ static void fdt_add_rtc_node(VersalVirt *s)
68
g_free(name);
69
}
70
71
+static void fdt_add_bbram_node(VersalVirt *s)
72
+{
73
+ const char compat[] = TYPE_XLNX_BBRAM;
74
+ const char interrupt_names[] = "bbram-error";
75
+ char *name = g_strdup_printf("/bbram@%x", MM_PMC_BBRAM_CTRL);
76
+
77
+ qemu_fdt_add_subnode(s->fdt, name);
78
+
79
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
80
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_BBRAM_APB_IRQ_0,
81
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
82
+ qemu_fdt_setprop(s->fdt, name, "interrupt-names",
83
+ interrupt_names, sizeof(interrupt_names));
84
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
85
+ 2, MM_PMC_BBRAM_CTRL,
86
+ 2, MM_PMC_BBRAM_CTRL_SIZE);
87
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
88
+ g_free(name);
89
+}
90
+
91
static void fdt_nop_memory_nodes(void *fdt, Error **errp)
92
{
93
Error *err = NULL;
94
@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
95
}
15
}
96
}
16
}
97
17
98
+static void bbram_attach_drive(XlnxBBRam *dev)
18
+static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
99
+{
19
+{
100
+ DriveInfo *dinfo;
20
+ uint32_t oldcr = s->cr;
101
+ BlockBackend *blk;
21
+
102
+
22
+ s->cr = value & 0x03ffffff;
103
+ dinfo = drive_get_by_index(IF_PFLASH, 0);
23
+
104
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
24
+ if (s->cr & CR_SWR) {
105
+ if (blk) {
25
+ /* handle the reset */
106
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
26
+ imx_epit_reset(s, false);
107
+ }
27
+ }
108
+}
28
+
109
+
29
+ /*
110
static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
30
+ * The interrupt state can change due to:
31
+ * - reset clears both SR.OCIF and CR.OCIE
32
+ * - write to CR.EN or CR.OCIE
33
+ */
34
+ imx_epit_update_int(s);
35
+
36
+ /*
37
+ * TODO: could we 'break' here for reset? following operations appear
38
+ * to duplicate the work imx_epit_reset() already did.
39
+ */
40
+
41
+ ptimer_transaction_begin(s->timer_cmp);
42
+ ptimer_transaction_begin(s->timer_reload);
43
+
44
+ /* Update the frequency. Has been done already in case of a reset. */
45
+ if (!(s->cr & CR_SWR)) {
46
+ imx_epit_set_freq(s);
47
+ }
48
+
49
+ if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
50
+ if (s->cr & CR_ENMOD) {
51
+ if (s->cr & CR_RLD) {
52
+ ptimer_set_limit(s->timer_reload, s->lr, 1);
53
+ ptimer_set_limit(s->timer_cmp, s->lr, 1);
54
+ } else {
55
+ ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
56
+ ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
57
+ }
58
+ }
59
+
60
+ imx_epit_reload_compare_timer(s);
61
+ ptimer_run(s->timer_reload, 0);
62
+ if (s->cr & CR_OCIEN) {
63
+ ptimer_run(s->timer_cmp, 0);
64
+ } else {
65
+ ptimer_stop(s->timer_cmp);
66
+ }
67
+ } else if (!(s->cr & CR_EN)) {
68
+ /* stop both timers */
69
+ ptimer_stop(s->timer_reload);
70
+ ptimer_stop(s->timer_cmp);
71
+ } else if (s->cr & CR_OCIEN) {
72
+ if (!(oldcr & CR_OCIEN)) {
73
+ imx_epit_reload_compare_timer(s);
74
+ ptimer_run(s->timer_cmp, 0);
75
+ }
76
+ } else {
77
+ ptimer_stop(s->timer_cmp);
78
+ }
79
+
80
+ ptimer_transaction_commit(s->timer_cmp);
81
+ ptimer_transaction_commit(s->timer_reload);
82
+}
83
+
84
+static void imx_epit_write_sr(IMXEPITState *s, uint32_t value)
85
+{
86
+ /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
87
+ if (value & SR_OCIF) {
88
+ s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
89
+ imx_epit_update_int(s);
90
+ }
91
+}
92
+
93
+static void imx_epit_write_lr(IMXEPITState *s, uint32_t value)
94
+{
95
+ s->lr = value;
96
+
97
+ ptimer_transaction_begin(s->timer_cmp);
98
+ ptimer_transaction_begin(s->timer_reload);
99
+ if (s->cr & CR_RLD) {
100
+ /* Also set the limit if the LRD bit is set */
101
+ /* If IOVW bit is set then set the timer value */
102
+ ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
103
+ ptimer_set_limit(s->timer_cmp, s->lr, 0);
104
+ } else if (s->cr & CR_IOVW) {
105
+ /* If IOVW bit is set then set the timer value */
106
+ ptimer_set_count(s->timer_reload, s->lr);
107
+ }
108
+ /*
109
+ * Commit the change to s->timer_reload, so it can propagate. Otherwise
110
+ * the timer interrupt may not fire properly. The commit must happen
111
+ * before calling imx_epit_reload_compare_timer(), which reads
112
+ * s->timer_reload internally again.
113
+ */
114
+ ptimer_transaction_commit(s->timer_reload);
115
+ imx_epit_reload_compare_timer(s);
116
+ ptimer_transaction_commit(s->timer_cmp);
117
+}
118
+
119
+static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value)
120
+{
121
+ s->cmp = value;
122
+
123
+ ptimer_transaction_begin(s->timer_cmp);
124
+ imx_epit_reload_compare_timer(s);
125
+ ptimer_transaction_commit(s->timer_cmp);
126
+}
127
+
128
static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
129
unsigned size)
111
{
130
{
112
BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
131
IMXEPITState *s = IMX_EPIT(opaque);
113
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
132
- uint64_t oldcr;
114
fdt_add_usb_xhci_nodes(s);
133
115
fdt_add_sd_nodes(s);
134
DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2),
116
fdt_add_rtc_node(s);
135
(uint32_t)value);
117
+ fdt_add_bbram_node(s);
136
118
fdt_add_cpu_nodes(s, psci_conduit);
137
switch (offset >> 2) {
119
fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
138
case 0: /* CR */
120
fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
139
-
121
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
140
- oldcr = s->cr;
122
memory_region_add_subregion_overlap(get_system_memory(),
141
- s->cr = value & 0x03ffffff;
123
0, &s->soc.fpd.apu.mr, 0);
142
- if (s->cr & CR_SWR) {
124
143
- /* handle the reset */
125
+ /* Attach bbram backend, if given */
144
- imx_epit_reset(s, false);
126
+ bbram_attach_drive(&s->soc.pmc.bbram);
145
- }
127
+
146
-
128
/* Plugin SD cards. */
147
- /*
129
for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
148
- * The interrupt state can change due to:
130
sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
149
- * - reset clears both SR.OCIF and CR.OCIE
131
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
150
- * - write to CR.EN or CR.OCIE
132
index XXXXXXX..XXXXXXX 100644
151
- */
133
--- a/hw/arm/xlnx-versal.c
152
- imx_epit_update_int(s);
134
+++ b/hw/arm/xlnx-versal.c
153
-
135
@@ -XXX,XX +XXX,XX @@ static void versal_create_xrams(Versal *s, qemu_irq *pic)
154
- /*
155
- * TODO: could we 'break' here for reset? following operations appear
156
- * to duplicate the work imx_epit_reset() already did.
157
- */
158
-
159
- ptimer_transaction_begin(s->timer_cmp);
160
- ptimer_transaction_begin(s->timer_reload);
161
-
162
- /* Update the frequency. Has been done already in case of a reset. */
163
- if (!(s->cr & CR_SWR)) {
164
- imx_epit_set_freq(s);
165
- }
166
-
167
- if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
168
- if (s->cr & CR_ENMOD) {
169
- if (s->cr & CR_RLD) {
170
- ptimer_set_limit(s->timer_reload, s->lr, 1);
171
- ptimer_set_limit(s->timer_cmp, s->lr, 1);
172
- } else {
173
- ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
174
- ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
175
- }
176
- }
177
-
178
- imx_epit_reload_compare_timer(s);
179
- ptimer_run(s->timer_reload, 0);
180
- if (s->cr & CR_OCIEN) {
181
- ptimer_run(s->timer_cmp, 0);
182
- } else {
183
- ptimer_stop(s->timer_cmp);
184
- }
185
- } else if (!(s->cr & CR_EN)) {
186
- /* stop both timers */
187
- ptimer_stop(s->timer_reload);
188
- ptimer_stop(s->timer_cmp);
189
- } else if (s->cr & CR_OCIEN) {
190
- if (!(oldcr & CR_OCIEN)) {
191
- imx_epit_reload_compare_timer(s);
192
- ptimer_run(s->timer_cmp, 0);
193
- }
194
- } else {
195
- ptimer_stop(s->timer_cmp);
196
- }
197
-
198
- ptimer_transaction_commit(s->timer_cmp);
199
- ptimer_transaction_commit(s->timer_reload);
200
+ imx_epit_write_cr(s, (uint32_t)value);
201
break;
202
203
- case 1: /* SR - ACK*/
204
- /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
205
- if (value & SR_OCIF) {
206
- s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
207
- imx_epit_update_int(s);
208
- }
209
+ case 1: /* SR */
210
+ imx_epit_write_sr(s, (uint32_t)value);
211
break;
212
213
- case 2: /* LR - set ticks */
214
- s->lr = value;
215
-
216
- ptimer_transaction_begin(s->timer_cmp);
217
- ptimer_transaction_begin(s->timer_reload);
218
- if (s->cr & CR_RLD) {
219
- /* Also set the limit if the LRD bit is set */
220
- /* If IOVW bit is set then set the timer value */
221
- ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
222
- ptimer_set_limit(s->timer_cmp, s->lr, 0);
223
- } else if (s->cr & CR_IOVW) {
224
- /* If IOVW bit is set then set the timer value */
225
- ptimer_set_count(s->timer_reload, s->lr);
226
- }
227
- /*
228
- * Commit the change to s->timer_reload, so it can propagate. Otherwise
229
- * the timer interrupt may not fire properly. The commit must happen
230
- * before calling imx_epit_reload_compare_timer(), which reads
231
- * s->timer_reload internally again.
232
- */
233
- ptimer_transaction_commit(s->timer_reload);
234
- imx_epit_reload_compare_timer(s);
235
- ptimer_transaction_commit(s->timer_cmp);
236
+ case 2: /* LR */
237
+ imx_epit_write_lr(s, (uint32_t)value);
238
break;
239
240
case 3: /* CMP */
241
- s->cmp = value;
242
-
243
- ptimer_transaction_begin(s->timer_cmp);
244
- imx_epit_reload_compare_timer(s);
245
- ptimer_transaction_commit(s->timer_cmp);
246
-
247
+ imx_epit_write_cmp(s, (uint32_t)value);
248
break;
249
250
default:
251
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
252
HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset);
253
-
254
break;
136
}
255
}
137
}
256
}
138
257
+
139
+static void versal_create_bbram(Versal *s, qemu_irq *pic)
258
static void imx_epit_cmp(void *opaque)
140
+{
259
{
141
+ SysBusDevice *sbd;
260
IMXEPITState *s = IMX_EPIT(opaque);
142
+
143
+ object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram,
144
+ sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM,
145
+ &error_fatal,
146
+ "crc-zpads", "0",
147
+ NULL);
148
+ sbd = SYS_BUS_DEVICE(&s->pmc.bbram);
149
+
150
+ sysbus_realize(sbd, &error_fatal);
151
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL,
152
+ sysbus_mmio_get_region(sbd, 0));
153
+ sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]);
154
+}
155
+
156
/* This takes the board allocated linear DDR memory and creates aliases
157
* for each split DDR range/aperture on the Versal address map.
158
*/
159
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
160
versal_create_sds(s, pic);
161
versal_create_rtc(s, pic);
162
versal_create_xrams(s, pic);
163
+ versal_create_bbram(s, pic);
164
versal_map_ddr(s);
165
versal_unimp(s);
166
167
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
168
index XXXXXXX..XXXXXXX 100644
169
--- a/hw/arm/Kconfig
170
+++ b/hw/arm/Kconfig
171
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
172
select XLNX_ZDMA
173
select XLNX_ZYNQMP
174
select OR_IRQ
175
+ select XLNX_BBRAM
176
177
config NPCM7XX
178
bool
179
--
261
--
180
2.20.1
262
2.25.1
181
182
diff view generated by jsdifflib
[PULL 19/22] qbus: Rename qbus_create_inplace() to qbus_init()
[PULL 16/34] hw/timer/imx_epit: remove explicit fields cnt and freq
1
Rename qbus_create_inplace() to qbus_init(); this is more in line
1
From: Axel Heider <axel.heider@hensoldt.net>
2
with our usual naming convention for functions that in-place
3
initialize objects.
4
2
3
The CNT register is a read-only register. There is no need to
4
store it's value, it can be calculated on demand.
5
The calculated frequency is needed temporarily only.
6
7
Note that this is a migration compatibility break for all boards
8
types that use the EPIT peripheral.
9
10
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
8
Message-id: 20210923121153.23754-5-peter.maydell@linaro.org
9
---
13
---
10
include/hw/qdev-core.h | 4 ++--
14
include/hw/timer/imx_epit.h | 2 -
11
hw/audio/intel-hda.c | 2 +-
15
hw/timer/imx_epit.c | 73 ++++++++++++++-----------------------
12
hw/block/fdc.c | 2 +-
16
2 files changed, 28 insertions(+), 47 deletions(-)
13
hw/block/swim.c | 3 +--
14
hw/char/virtio-serial-bus.c | 4 ++--
15
hw/core/bus.c | 11 ++++++-----
16
hw/core/sysbus.c | 10 ++++++----
17
hw/gpio/bcm2835_gpio.c | 3 +--
18
hw/ide/qdev.c | 2 +-
19
hw/ipack/ipack.c | 2 +-
20
hw/misc/mac_via.c | 4 ++--
21
hw/misc/macio/cuda.c | 4 ++--
22
hw/misc/macio/macio.c | 4 ++--
23
hw/misc/macio/pmu.c | 4 ++--
24
hw/nubus/nubus-bridge.c | 2 +-
25
hw/nvme/ctrl.c | 4 ++--
26
hw/nvme/subsys.c | 3 +--
27
hw/pci/pci.c | 2 +-
28
hw/pci/pci_bridge.c | 4 ++--
29
hw/s390x/event-facility.c | 4 ++--
30
hw/s390x/virtio-ccw.c | 3 +--
31
hw/scsi/scsi-bus.c | 2 +-
32
hw/sd/allwinner-sdhost.c | 4 ++--
33
hw/sd/bcm2835_sdhost.c | 4 ++--
34
hw/sd/pl181.c | 3 +--
35
hw/sd/pxa2xx_mmci.c | 4 ++--
36
hw/sd/sdhci.c | 3 +--
37
hw/sd/ssi-sd.c | 3 +--
38
hw/usb/bus.c | 2 +-
39
hw/usb/dev-smartcard-reader.c | 3 +--
40
hw/virtio/virtio-mmio.c | 3 +--
41
hw/virtio/virtio-pci.c | 3 +--
42
32 files changed, 54 insertions(+), 61 deletions(-)
43
17
44
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
18
diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
45
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/qdev-core.h
20
--- a/include/hw/timer/imx_epit.h
47
+++ b/include/hw/qdev-core.h
21
+++ b/include/hw/timer/imx_epit.h
48
@@ -XXX,XX +XXX,XX @@ DeviceState *qdev_find_recursive(BusState *bus, const char *id);
22
@@ -XXX,XX +XXX,XX @@ struct IMXEPITState {
49
typedef int (qbus_walkerfn)(BusState *bus, void *opaque);
23
uint32_t sr;
50
typedef int (qdev_walkerfn)(DeviceState *dev, void *opaque);
24
uint32_t lr;
51
25
uint32_t cmp;
52
-void qbus_create_inplace(void *bus, size_t size, const char *typename,
26
- uint32_t cnt;
53
- DeviceState *parent, const char *name);
27
54
+void qbus_init(void *bus, size_t size, const char *typename,
28
- uint32_t freq;
55
+ DeviceState *parent, const char *name);
29
qemu_irq irq;
56
BusState *qbus_create(const char *typename, DeviceState *parent, const char *name);
30
};
57
bool qbus_realize(BusState *bus, Error **errp);
31
58
void qbus_unrealize(BusState *bus);
32
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
59
diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
60
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/audio/intel-hda.c
34
--- a/hw/timer/imx_epit.c
62
+++ b/hw/audio/intel-hda.c
35
+++ b/hw/timer/imx_epit.c
63
@@ -XXX,XX +XXX,XX @@ void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
36
@@ -XXX,XX +XXX,XX @@ static void imx_epit_update_int(IMXEPITState *s)
64
hda_codec_response_func response,
65
hda_codec_xfer_func xfer)
66
{
67
- qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
68
+ qbus_init(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
69
bus->response = response;
70
bus->xfer = xfer;
71
}
72
diff --git a/hw/block/fdc.c b/hw/block/fdc.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/block/fdc.c
75
+++ b/hw/block/fdc.c
76
@@ -XXX,XX +XXX,XX @@ static const TypeInfo floppy_bus_info = {
77
78
static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev)
79
{
80
- qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
81
+ qbus_init(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
82
bus->fdc = fdc;
83
}
84
85
diff --git a/hw/block/swim.c b/hw/block/swim.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/hw/block/swim.c
88
+++ b/hw/block/swim.c
89
@@ -XXX,XX +XXX,XX @@ static void sysbus_swim_realize(DeviceState *dev, Error **errp)
90
Swim *sys = SWIM(dev);
91
SWIMCtrl *swimctrl = &sys->ctrl;
92
93
- qbus_create_inplace(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev,
94
- NULL);
95
+ qbus_init(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev, NULL);
96
swimctrl->bus.ctrl = swimctrl;
97
}
98
99
diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/hw/char/virtio-serial-bus.c
102
+++ b/hw/char/virtio-serial-bus.c
103
@@ -XXX,XX +XXX,XX @@ static void virtio_serial_device_realize(DeviceState *dev, Error **errp)
104
config_size);
105
106
/* Spawn a new virtio-serial bus on which the ports will ride as devices */
107
- qbus_create_inplace(&vser->bus, sizeof(vser->bus), TYPE_VIRTIO_SERIAL_BUS,
108
- dev, vdev->bus_name);
109
+ qbus_init(&vser->bus, sizeof(vser->bus), TYPE_VIRTIO_SERIAL_BUS,
110
+ dev, vdev->bus_name);
111
qbus_set_hotplug_handler(BUS(&vser->bus), OBJECT(vser));
112
vser->bus.vser = vser;
113
QTAILQ_INIT(&vser->ports);
114
diff --git a/hw/core/bus.c b/hw/core/bus.c
115
index XXXXXXX..XXXXXXX 100644
116
--- a/hw/core/bus.c
117
+++ b/hw/core/bus.c
118
@@ -XXX,XX +XXX,XX @@ static void bus_reset_child_foreach(Object *obj, ResettableChildCallback cb,
119
}
37
}
120
}
38
}
121
39
122
-static void qbus_init(BusState *bus, DeviceState *parent, const char *name)
40
-/*
123
+static void qbus_init_internal(BusState *bus, DeviceState *parent,
41
- * Must be called from within a ptimer_transaction_begin/commit block
124
+ const char *name)
42
- * for both s->timer_cmp and s->timer_reload.
43
- */
44
-static void imx_epit_set_freq(IMXEPITState *s)
45
+static uint32_t imx_epit_get_freq(IMXEPITState *s)
125
{
46
{
126
const char *typename = object_get_typename(OBJECT(bus));
47
- uint32_t clksrc;
127
BusClass *bc;
48
- uint32_t prescaler;
128
@@ -XXX,XX +XXX,XX @@ static void bus_unparent(Object *obj)
49
-
129
bus->parent = NULL;
50
- clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
51
- prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
52
-
53
- s->freq = imx_ccm_get_clock_frequency(s->ccm,
54
- imx_epit_clocks[clksrc]) / prescaler;
55
-
56
- DPRINTF("Setting ptimer frequency to %u\n", s->freq);
57
-
58
- if (s->freq) {
59
- ptimer_set_freq(s->timer_reload, s->freq);
60
- ptimer_set_freq(s->timer_cmp, s->freq);
61
- }
62
+ uint32_t clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
63
+ uint32_t prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
64
+ uint32_t f_in = imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[clksrc]);
65
+ uint32_t freq = f_in / prescaler;
66
+ DPRINTF("ptimer frequency is %u\n", freq);
67
+ return freq;
130
}
68
}
131
69
132
-void qbus_create_inplace(void *bus, size_t size, const char *typename,
70
/*
133
- DeviceState *parent, const char *name)
71
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset)
134
+void qbus_init(void *bus, size_t size, const char *typename,
72
s->sr = 0;
135
+ DeviceState *parent, const char *name)
73
s->lr = EPIT_TIMER_MAX;
74
s->cmp = 0;
75
- s->cnt = 0;
76
ptimer_transaction_begin(s->timer_cmp);
77
ptimer_transaction_begin(s->timer_reload);
78
- /* stop both timers */
79
+
80
+ /*
81
+ * The reset switches off the input clock, so even if the CR.EN is still
82
+ * set, the timers are no longer running.
83
+ */
84
+ assert(imx_epit_get_freq(s) == 0);
85
ptimer_stop(s->timer_cmp);
86
ptimer_stop(s->timer_reload);
87
- /* compute new frequency */
88
- imx_epit_set_freq(s);
89
/* init both timers to EPIT_TIMER_MAX */
90
ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
91
ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
92
- if (s->freq && (s->cr & CR_EN)) {
93
- /* if the timer is still enabled, restart it */
94
- ptimer_run(s->timer_reload, 0);
95
- }
96
ptimer_transaction_commit(s->timer_cmp);
97
ptimer_transaction_commit(s->timer_reload);
98
}
99
100
-static uint32_t imx_epit_update_count(IMXEPITState *s)
101
-{
102
- s->cnt = ptimer_get_count(s->timer_reload);
103
-
104
- return s->cnt;
105
-}
106
-
107
static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
136
{
108
{
137
object_initialize(bus, size, typename);
109
IMXEPITState *s = IMX_EPIT(opaque);
138
- qbus_init(bus, parent, name);
110
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
139
+ qbus_init_internal(bus, parent, name);
111
break;
140
}
112
141
113
case 4: /* CNT */
142
BusState *qbus_create(const char *typename, DeviceState *parent, const char *name)
114
- imx_epit_update_count(s);
143
@@ -XXX,XX +XXX,XX @@ BusState *qbus_create(const char *typename, DeviceState *parent, const char *nam
115
- reg_value = s->cnt;
144
BusState *bus;
116
+ reg_value = ptimer_get_count(s->timer_reload);
145
117
break;
146
bus = BUS(object_new(typename));
118
147
- qbus_init(bus, parent, name);
119
default:
148
+ qbus_init_internal(bus, parent, name);
120
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
149
150
return bus;
151
}
152
diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c
153
index XXXXXXX..XXXXXXX 100644
154
--- a/hw/core/sysbus.c
155
+++ b/hw/core/sysbus.c
156
@@ -XXX,XX +XXX,XX @@ static BusState *main_system_bus;
157
158
static void main_system_bus_create(void)
159
{
121
{
160
- /* assign main_system_bus before qbus_create_inplace()
122
if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) {
161
- * in order to make "if (bus != sysbus_get_default())" work */
123
/* if the compare feature is on and timers are running */
124
- uint32_t tmp = imx_epit_update_count(s);
125
+ uint32_t tmp = ptimer_get_count(s->timer_reload);
126
uint64_t next;
127
if (tmp > s->cmp) {
128
/* It'll fire in this round of the timer */
129
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
130
131
static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
132
{
133
+ uint32_t freq = 0;
134
uint32_t oldcr = s->cr;
135
136
s->cr = value & 0x03ffffff;
137
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
138
ptimer_transaction_begin(s->timer_cmp);
139
ptimer_transaction_begin(s->timer_reload);
140
141
- /* Update the frequency. Has been done already in case of a reset. */
162
+ /*
142
+ /*
163
+ * assign main_system_bus before qbus_init()
143
+ * Update the frequency. In case of a reset the input clock was
164
+ * in order to make "if (bus != sysbus_get_default())" work
144
+ * switched off, so this can be skipped.
165
+ */
145
+ */
166
main_system_bus = g_malloc0(system_bus_info.instance_size);
146
if (!(s->cr & CR_SWR)) {
167
- qbus_create_inplace(main_system_bus, system_bus_info.instance_size,
147
- imx_epit_set_freq(s);
168
- TYPE_SYSTEM_BUS, NULL, "main-system-bus");
148
+ freq = imx_epit_get_freq(s);
169
+ qbus_init(main_system_bus, system_bus_info.instance_size,
149
+ if (freq) {
170
+ TYPE_SYSTEM_BUS, NULL, "main-system-bus");
150
+ ptimer_set_freq(s->timer_reload, freq);
171
OBJECT(main_system_bus)->free = g_free;
151
+ ptimer_set_freq(s->timer_cmp, freq);
172
}
152
+ }
173
174
diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c
175
index XXXXXXX..XXXXXXX 100644
176
--- a/hw/gpio/bcm2835_gpio.c
177
+++ b/hw/gpio/bcm2835_gpio.c
178
@@ -XXX,XX +XXX,XX @@ static void bcm2835_gpio_init(Object *obj)
179
DeviceState *dev = DEVICE(obj);
180
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
181
182
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
183
- TYPE_SD_BUS, DEVICE(s), "sd-bus");
184
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(s), "sd-bus");
185
186
memory_region_init_io(&s->iomem, obj,
187
&bcm2835_gpio_ops, s, "bcm2835_gpio", 0x1000);
188
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
189
index XXXXXXX..XXXXXXX 100644
190
--- a/hw/ide/qdev.c
191
+++ b/hw/ide/qdev.c
192
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ide_bus_info = {
193
void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
194
int bus_id, int max_units)
195
{
196
- qbus_create_inplace(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL);
197
+ qbus_init(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL);
198
idebus->bus_id = bus_id;
199
idebus->max_units = max_units;
200
}
201
diff --git a/hw/ipack/ipack.c b/hw/ipack/ipack.c
202
index XXXXXXX..XXXXXXX 100644
203
--- a/hw/ipack/ipack.c
204
+++ b/hw/ipack/ipack.c
205
@@ -XXX,XX +XXX,XX @@ void ipack_bus_init(IPackBus *bus, size_t bus_size,
206
uint8_t n_slots,
207
qemu_irq_handler handler)
208
{
209
- qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, NULL);
210
+ qbus_init(bus, bus_size, TYPE_IPACK_BUS, parent, NULL);
211
bus->n_slots = n_slots;
212
bus->set_irq = handler;
213
}
214
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
215
index XXXXXXX..XXXXXXX 100644
216
--- a/hw/misc/mac_via.c
217
+++ b/hw/misc/mac_via.c
218
@@ -XXX,XX +XXX,XX @@ static void mos6522_q800_via1_init(Object *obj)
219
sysbus_init_mmio(sbd, &v1s->via_mem);
220
221
/* ADB */
222
- qbus_create_inplace((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus),
223
- TYPE_ADB_BUS, DEVICE(v1s), "adb.0");
224
+ qbus_init((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus),
225
+ TYPE_ADB_BUS, DEVICE(v1s), "adb.0");
226
227
qdev_init_gpio_in(DEVICE(obj), via1_irq_request, VIA1_IRQ_NB);
228
}
229
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c
230
index XXXXXXX..XXXXXXX 100644
231
--- a/hw/misc/macio/cuda.c
232
+++ b/hw/misc/macio/cuda.c
233
@@ -XXX,XX +XXX,XX @@ static void cuda_init(Object *obj)
234
memory_region_init_io(&s->mem, obj, &mos6522_cuda_ops, s, "cuda", 0x2000);
235
sysbus_init_mmio(sbd, &s->mem);
236
237
- qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
238
- DEVICE(obj), "adb.0");
239
+ qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
240
+ DEVICE(obj), "adb.0");
241
}
242
243
static Property cuda_properties[] = {
244
diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
245
index XXXXXXX..XXXXXXX 100644
246
--- a/hw/misc/macio/macio.c
247
+++ b/hw/misc/macio/macio.c
248
@@ -XXX,XX +XXX,XX @@ static void macio_instance_init(Object *obj)
249
250
memory_region_init(&s->bar, obj, "macio", 0x80000);
251
252
- qbus_create_inplace(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS,
253
- DEVICE(obj), "macio.0");
254
+ qbus_init(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS,
255
+ DEVICE(obj), "macio.0");
256
257
object_initialize_child(OBJECT(s), "dbdma", &s->dbdma, TYPE_MAC_DBDMA);
258
259
diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c
260
index XXXXXXX..XXXXXXX 100644
261
--- a/hw/misc/macio/pmu.c
262
+++ b/hw/misc/macio/pmu.c
263
@@ -XXX,XX +XXX,XX @@ static void pmu_realize(DeviceState *dev, Error **errp)
264
timer_mod(s->one_sec_timer, s->one_sec_target);
265
266
if (s->has_adb) {
267
- qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
268
- dev, "adb.0");
269
+ qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
270
+ dev, "adb.0");
271
adb_register_autopoll_callback(adb_bus, pmu_adb_poll, s);
272
}
153
}
273
}
154
274
diff --git a/hw/nubus/nubus-bridge.c b/hw/nubus/nubus-bridge.c
155
- if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
275
index XXXXXXX..XXXXXXX 100644
156
+ if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
276
--- a/hw/nubus/nubus-bridge.c
157
if (s->cr & CR_ENMOD) {
277
+++ b/hw/nubus/nubus-bridge.c
158
if (s->cr & CR_RLD) {
278
@@ -XXX,XX +XXX,XX @@ static void nubus_bridge_init(Object *obj)
159
ptimer_set_limit(s->timer_reload, s->lr, 1);
279
NubusBridge *s = NUBUS_BRIDGE(obj);
160
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps imx_epit_ops = {
280
NubusBus *bus = &s->bus;
161
281
162
static const VMStateDescription vmstate_imx_timer_epit = {
282
- qbus_create_inplace(bus, sizeof(s->bus), TYPE_NUBUS_BUS, DEVICE(s), NULL);
163
.name = TYPE_IMX_EPIT,
283
+ qbus_init(bus, sizeof(s->bus), TYPE_NUBUS_BUS, DEVICE(s), NULL);
164
- .version_id = 2,
284
165
- .minimum_version_id = 2,
285
qdev_init_gpio_out(DEVICE(s), bus->irqs, NUBUS_IRQS);
166
+ .version_id = 3,
286
}
167
+ .minimum_version_id = 3,
287
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
168
.fields = (VMStateField[]) {
288
index XXXXXXX..XXXXXXX 100644
169
VMSTATE_UINT32(cr, IMXEPITState),
289
--- a/hw/nvme/ctrl.c
170
VMSTATE_UINT32(sr, IMXEPITState),
290
+++ b/hw/nvme/ctrl.c
171
VMSTATE_UINT32(lr, IMXEPITState),
291
@@ -XXX,XX +XXX,XX @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
172
VMSTATE_UINT32(cmp, IMXEPITState),
292
return;
173
- VMSTATE_UINT32(cnt, IMXEPITState),
293
}
174
- VMSTATE_UINT32(freq, IMXEPITState),
294
175
VMSTATE_PTIMER(timer_reload, IMXEPITState),
295
- qbus_create_inplace(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS,
176
VMSTATE_PTIMER(timer_cmp, IMXEPITState),
296
- &pci_dev->qdev, n->parent_obj.qdev.id);
177
VMSTATE_END_OF_LIST()
297
+ qbus_init(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS,
298
+ &pci_dev->qdev, n->parent_obj.qdev.id);
299
300
nvme_init_state(n);
301
if (nvme_init_pci(n, pci_dev, errp)) {
302
diff --git a/hw/nvme/subsys.c b/hw/nvme/subsys.c
303
index XXXXXXX..XXXXXXX 100644
304
--- a/hw/nvme/subsys.c
305
+++ b/hw/nvme/subsys.c
306
@@ -XXX,XX +XXX,XX @@ static void nvme_subsys_realize(DeviceState *dev, Error **errp)
307
{
308
NvmeSubsystem *subsys = NVME_SUBSYS(dev);
309
310
- qbus_create_inplace(&subsys->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev,
311
- dev->id);
312
+ qbus_init(&subsys->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev, dev->id);
313
314
nvme_subsys_setup(subsys);
315
}
316
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
317
index XXXXXXX..XXXXXXX 100644
318
--- a/hw/pci/pci.c
319
+++ b/hw/pci/pci.c
320
@@ -XXX,XX +XXX,XX @@ void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
321
MemoryRegion *address_space_io,
322
uint8_t devfn_min, const char *typename)
323
{
324
- qbus_create_inplace(bus, bus_size, typename, parent, name);
325
+ qbus_init(bus, bus_size, typename, parent, name);
326
pci_root_bus_internal_init(bus, parent, address_space_mem,
327
address_space_io, devfn_min);
328
}
329
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
330
index XXXXXXX..XXXXXXX 100644
331
--- a/hw/pci/pci_bridge.c
332
+++ b/hw/pci/pci_bridge.c
333
@@ -XXX,XX +XXX,XX @@ void pci_bridge_initfn(PCIDevice *dev, const char *typename)
334
br->bus_name = dev->qdev.id;
335
}
336
337
- qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
338
- br->bus_name);
339
+ qbus_init(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
340
+ br->bus_name);
341
sec_bus->parent_dev = dev;
342
sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
343
sec_bus->address_space_mem = &br->address_space_mem;
344
diff --git a/hw/s390x/event-facility.c b/hw/s390x/event-facility.c
345
index XXXXXXX..XXXXXXX 100644
346
--- a/hw/s390x/event-facility.c
347
+++ b/hw/s390x/event-facility.c
348
@@ -XXX,XX +XXX,XX @@ static void init_event_facility(Object *obj)
349
sclp_event_set_allow_all_mask_sizes);
350
351
/* Spawn a new bus for SCLP events */
352
- qbus_create_inplace(&event_facility->sbus, sizeof(event_facility->sbus),
353
- TYPE_SCLP_EVENTS_BUS, sdev, NULL);
354
+ qbus_init(&event_facility->sbus, sizeof(event_facility->sbus),
355
+ TYPE_SCLP_EVENTS_BUS, sdev, NULL);
356
357
object_initialize_child(obj, TYPE_SCLP_QUIESCE,
358
&event_facility->quiesce,
359
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
360
index XXXXXXX..XXXXXXX 100644
361
--- a/hw/s390x/virtio-ccw.c
362
+++ b/hw/s390x/virtio-ccw.c
363
@@ -XXX,XX +XXX,XX @@ static void virtio_ccw_bus_new(VirtioBusState *bus, size_t bus_size,
364
DeviceState *qdev = DEVICE(dev);
365
char virtio_bus_name[] = "virtio-bus";
366
367
- qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_CCW_BUS,
368
- qdev, virtio_bus_name);
369
+ qbus_init(bus, bus_size, TYPE_VIRTIO_CCW_BUS, qdev, virtio_bus_name);
370
}
371
372
static void virtio_ccw_bus_class_init(ObjectClass *klass, void *data)
373
diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c
374
index XXXXXXX..XXXXXXX 100644
375
--- a/hw/scsi/scsi-bus.c
376
+++ b/hw/scsi/scsi-bus.c
377
@@ -XXX,XX +XXX,XX @@ void scsi_device_unit_attention_reported(SCSIDevice *s)
378
void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host,
379
const SCSIBusInfo *info, const char *bus_name)
380
{
381
- qbus_create_inplace(bus, bus_size, TYPE_SCSI_BUS, host, bus_name);
382
+ qbus_init(bus, bus_size, TYPE_SCSI_BUS, host, bus_name);
383
bus->busnr = next_scsi_bus++;
384
bus->info = info;
385
qbus_set_bus_hotplug_handler(BUS(bus));
386
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
387
index XXXXXXX..XXXXXXX 100644
388
--- a/hw/sd/allwinner-sdhost.c
389
+++ b/hw/sd/allwinner-sdhost.c
390
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_init(Object *obj)
391
{
392
AwSdHostState *s = AW_SDHOST(obj);
393
394
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
395
- TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
396
+ qbus_init(&s->sdbus, sizeof(s->sdbus),
397
+ TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
398
399
memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
400
TYPE_AW_SDHOST, 4 * KiB);
401
diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c
402
index XXXXXXX..XXXXXXX 100644
403
--- a/hw/sd/bcm2835_sdhost.c
404
+++ b/hw/sd/bcm2835_sdhost.c
405
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_init(Object *obj)
406
{
407
BCM2835SDHostState *s = BCM2835_SDHOST(obj);
408
409
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
410
- TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus");
411
+ qbus_init(&s->sdbus, sizeof(s->sdbus),
412
+ TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus");
413
414
memory_region_init_io(&s->iomem, obj, &bcm2835_sdhost_ops, s,
415
TYPE_BCM2835_SDHOST, 0x1000);
416
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
417
index XXXXXXX..XXXXXXX 100644
418
--- a/hw/sd/pl181.c
419
+++ b/hw/sd/pl181.c
420
@@ -XXX,XX +XXX,XX @@ static void pl181_init(Object *obj)
421
qdev_init_gpio_out_named(dev, &s->card_readonly, "card-read-only", 1);
422
qdev_init_gpio_out_named(dev, &s->card_inserted, "card-inserted", 1);
423
424
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
425
- TYPE_PL181_BUS, dev, "sd-bus");
426
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_PL181_BUS, dev, "sd-bus");
427
}
428
429
static void pl181_class_init(ObjectClass *klass, void *data)
430
diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c
431
index XXXXXXX..XXXXXXX 100644
432
--- a/hw/sd/pxa2xx_mmci.c
433
+++ b/hw/sd/pxa2xx_mmci.c
434
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_mmci_instance_init(Object *obj)
435
qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
436
qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);
437
438
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
439
- TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
440
+ qbus_init(&s->sdbus, sizeof(s->sdbus),
441
+ TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
442
}
443
444
static void pxa2xx_mmci_class_init(ObjectClass *klass, void *data)
445
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
446
index XXXXXXX..XXXXXXX 100644
447
--- a/hw/sd/sdhci.c
448
+++ b/hw/sd/sdhci.c
449
@@ -XXX,XX +XXX,XX @@ static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
450
451
void sdhci_initfn(SDHCIState *s)
452
{
453
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
454
- TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
455
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
456
457
s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
458
s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
459
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
460
index XXXXXXX..XXXXXXX 100644
461
--- a/hw/sd/ssi-sd.c
462
+++ b/hw/sd/ssi-sd.c
463
@@ -XXX,XX +XXX,XX @@ static void ssi_sd_realize(SSIPeripheral *d, Error **errp)
464
DeviceState *carddev;
465
DriveInfo *dinfo;
466
467
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
468
- DEVICE(d), "sd-bus");
469
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(d), "sd-bus");
470
471
/* Create and plug in the sd card */
472
/* FIXME use a qdev drive property instead of drive_get_next() */
473
diff --git a/hw/usb/bus.c b/hw/usb/bus.c
474
index XXXXXXX..XXXXXXX 100644
475
--- a/hw/usb/bus.c
476
+++ b/hw/usb/bus.c
477
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_usb_device = {
478
void usb_bus_new(USBBus *bus, size_t bus_size,
479
USBBusOps *ops, DeviceState *host)
480
{
481
- qbus_create_inplace(bus, bus_size, TYPE_USB_BUS, host, NULL);
482
+ qbus_init(bus, bus_size, TYPE_USB_BUS, host, NULL);
483
qbus_set_bus_hotplug_handler(BUS(bus));
484
bus->ops = ops;
485
bus->busnr = next_usb_bus++;
486
diff --git a/hw/usb/dev-smartcard-reader.c b/hw/usb/dev-smartcard-reader.c
487
index XXXXXXX..XXXXXXX 100644
488
--- a/hw/usb/dev-smartcard-reader.c
489
+++ b/hw/usb/dev-smartcard-reader.c
490
@@ -XXX,XX +XXX,XX @@ static void ccid_realize(USBDevice *dev, Error **errp)
491
492
usb_desc_create_serial(dev);
493
usb_desc_init(dev);
494
- qbus_create_inplace(&s->bus, sizeof(s->bus), TYPE_CCID_BUS, DEVICE(dev),
495
- NULL);
496
+ qbus_init(&s->bus, sizeof(s->bus), TYPE_CCID_BUS, DEVICE(dev), NULL);
497
qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(dev));
498
s->intr = usb_ep_get(dev, USB_TOKEN_IN, CCID_INT_IN_EP);
499
s->bulk = usb_ep_get(dev, USB_TOKEN_IN, CCID_BULK_IN_EP);
500
diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c
501
index XXXXXXX..XXXXXXX 100644
502
--- a/hw/virtio/virtio-mmio.c
503
+++ b/hw/virtio/virtio-mmio.c
504
@@ -XXX,XX +XXX,XX @@ static void virtio_mmio_realizefn(DeviceState *d, Error **errp)
505
VirtIOMMIOProxy *proxy = VIRTIO_MMIO(d);
506
SysBusDevice *sbd = SYS_BUS_DEVICE(d);
507
508
- qbus_create_inplace(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS,
509
- d, NULL);
510
+ qbus_init(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS, d, NULL);
511
sysbus_init_irq(sbd, &proxy->irq);
512
513
if (!kvm_eventfds_enabled()) {
514
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
515
index XXXXXXX..XXXXXXX 100644
516
--- a/hw/virtio/virtio-pci.c
517
+++ b/hw/virtio/virtio-pci.c
518
@@ -XXX,XX +XXX,XX @@ static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size,
519
DeviceState *qdev = DEVICE(dev);
520
char virtio_bus_name[] = "virtio-bus";
521
522
- qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev,
523
- virtio_bus_name);
524
+ qbus_init(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev, virtio_bus_name);
525
}
526
527
static void virtio_pci_bus_class_init(ObjectClass *klass, void *data)
528
--
178
--
529
2.20.1
179
2.25.1
530
531
diff view generated by jsdifflib
[PULL 04/22] hw/nvram: Introduce Xilinx Versal eFuse device
[PULL 17/34] hw/timer/imx_epit: fix compare timer handling
1
From: Tong Ho <tong.ho@xilinx.com>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
This implements the Xilinx Versal eFuse, an one-time
3
- fix #1263 for CR writes
4
field-programmable non-volatile storage device. There is
4
- rework compare time handling
5
only one such device in the Xilinx Versal product family.
5
- The compare timer has to run even if CR.OCIEN is not set,
6
as SR.OCIF must be updated.
7
- The compare timer fires exactly once when the
8
compare value is less than the current value, but the
9
reload values is less than the compare value.
10
- The compare timer will never fire if the reload value is
11
less than the compare value. Disable it in this case.
6
12
7
This device has two separate mmio interfaces, a controller
13
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
8
and a flatten readback.
14
[PMM: fixed minor style nits]
9
10
The controller provides interfaces for field-programming,
11
configuration, control, and status.
12
13
The flatten readback is a cache to provide a byte-accessible
14
read-only interface to efficiently read efuse array.
15
16
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
17
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
18
19
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
20
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
21
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
22
Message-id: 20210917052400.1249094-3-tong.ho@xilinx.com
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
17
---
26
include/hw/nvram/xlnx-versal-efuse.h | 68 +++
18
hw/timer/imx_epit.c | 192 ++++++++++++++++++++++++++------------------
27
hw/nvram/xlnx-versal-efuse-cache.c | 114 ++++
19
1 file changed, 116 insertions(+), 76 deletions(-)
28
hw/nvram/xlnx-versal-efuse-ctrl.c | 783 +++++++++++++++++++++++++++
29
hw/nvram/Kconfig | 4 +
30
hw/nvram/meson.build | 3 +
31
5 files changed, 972 insertions(+)
32
create mode 100644 include/hw/nvram/xlnx-versal-efuse.h
33
create mode 100644 hw/nvram/xlnx-versal-efuse-cache.c
34
create mode 100644 hw/nvram/xlnx-versal-efuse-ctrl.c
35
20
36
diff --git a/include/hw/nvram/xlnx-versal-efuse.h b/include/hw/nvram/xlnx-versal-efuse.h
21
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
37
new file mode 100644
22
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX
23
--- a/hw/timer/imx_epit.c
39
--- /dev/null
24
+++ b/hw/timer/imx_epit.c
40
+++ b/include/hw/nvram/xlnx-versal-efuse.h
41
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@
26
* Originally written by Hans Jiang
27
* Updated by Peter Chubb
28
* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
29
+ * Updated by Axel Heider
30
*
31
* This code is licensed under GPL version 2 or later. See
32
* the COPYING file in the top-level directory.
33
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
34
return reg_value;
35
}
36
37
-/* Must be called from ptimer_transaction_begin/commit block for s->timer_cmp */
38
-static void imx_epit_reload_compare_timer(IMXEPITState *s)
42
+/*
39
+/*
43
+ * Copyright (c) 2020 Xilinx Inc.
40
+ * Must be called from a ptimer_transaction_begin/commit block for
44
+ *
41
+ * s->timer_cmp, but outside of a transaction block of s->timer_reload,
45
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
42
+ * so the proper counter value is read.
46
+ * of this software and associated documentation files (the "Software"), to deal
47
+ * in the Software without restriction, including without limitation the rights
48
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
49
+ * copies of the Software, and to permit persons to whom the Software is
50
+ * furnished to do so, subject to the following conditions:
51
+ *
52
+ * The above copyright notice and this permission notice shall be included in
53
+ * all copies or substantial portions of the Software.
54
+ *
55
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
56
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
57
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
58
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
59
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
60
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
61
+ * THE SOFTWARE.
62
+ */
43
+ */
63
+#ifndef XLNX_VERSAL_EFUSE_H
44
+static void imx_epit_update_compare_timer(IMXEPITState *s)
64
+#define XLNX_VERSAL_EFUSE_H
45
{
65
+
46
- if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) {
66
+#include "hw/irq.h"
47
- /* if the compare feature is on and timers are running */
67
+#include "hw/sysbus.h"
48
- uint32_t tmp = ptimer_get_count(s->timer_reload);
68
+#include "hw/register.h"
49
- uint64_t next;
69
+#include "hw/nvram/xlnx-efuse.h"
50
- if (tmp > s->cmp) {
70
+
51
- /* It'll fire in this round of the timer */
71
+#define XLNX_VERSAL_EFUSE_CTRL_R_MAX ((0x100 / 4) + 1)
52
- next = tmp - s->cmp;
72
+
53
- } else { /* catch it next time around */
73
+#define TYPE_XLNX_VERSAL_EFUSE_CTRL "xlnx,versal-efuse"
54
- next = tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s->lr);
74
+#define TYPE_XLNX_VERSAL_EFUSE_CACHE "xlnx,pmc-efuse-cache"
55
+ uint64_t counter = 0;
75
+
56
+ bool is_oneshot = false;
76
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCtrl, XLNX_VERSAL_EFUSE_CTRL);
57
+ /*
77
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCache, XLNX_VERSAL_EFUSE_CACHE);
58
+ * The compare timer only has to run if the timer peripheral is active
78
+
59
+ * and there is an input clock, Otherwise it can be switched off.
79
+struct XlnxVersalEFuseCtrl {
60
+ */
80
+ SysBusDevice parent_obj;
61
+ bool is_active = (s->cr & CR_EN) && imx_epit_get_freq(s);
81
+ qemu_irq irq_efuse_imr;
62
+ if (is_active) {
82
+
63
+ /*
83
+ XlnxEFuse *efuse;
64
+ * Calculate next timeout for compare timer. Reading the reload
84
+
65
+ * counter returns proper results only if pending transactions
85
+ void *extra_pg0_lock_spec; /* Opaque property */
66
+ * on it are committed here. Otherwise stale values are be read.
86
+ uint32_t extra_pg0_lock_n16;
67
+ */
87
+
68
+ counter = ptimer_get_count(s->timer_reload);
88
+ uint32_t regs[XLNX_VERSAL_EFUSE_CTRL_R_MAX];
69
+ uint64_t limit = ptimer_get_limit(s->timer_cmp);
89
+ RegisterInfo regs_info[XLNX_VERSAL_EFUSE_CTRL_R_MAX];
70
+ /*
90
+};
71
+ * The compare timer is a periodic timer if the limit is at least
91
+
72
+ * the compare value. Otherwise it may fire at most once in the
92
+struct XlnxVersalEFuseCache {
73
+ * current round.
93
+ SysBusDevice parent_obj;
74
+ */
94
+ MemoryRegion iomem;
75
+ bool is_oneshot = (limit >= s->cmp);
95
+
76
+ if (counter >= s->cmp) {
96
+ XlnxEFuse *efuse;
77
+ /* The compare timer fires in the current round. */
97
+};
78
+ counter -= s->cmp;
98
+
79
+ } else if (!is_oneshot) {
99
+/**
80
+ /*
100
+ * xlnx_versal_efuse_read_row:
81
+ * The compare timer fires after a reload, as it is below the
101
+ * @s: the efuse object
82
+ * compare value already in this round. Note that the counter
102
+ * @bit: the bit-address within the 32-bit row to be read
83
+ * value calculated below can be above the 32-bit limit, which
103
+ * @denied: if non-NULL, to receive true if the row is write-only
84
+ * is legal here because the compare timer is an internal
104
+ *
85
+ * helper ptimer only.
105
+ * Returns: the 32-bit word containing address @bit; 0 if @denies is true
86
+ */
106
+ */
87
+ counter += limit - s->cmp;
107
+uint32_t xlnx_versal_efuse_read_row(XlnxEFuse *s, uint32_t bit, bool *denied);
88
+ } else {
108
+
89
+ /*
109
+#endif
90
+ * The compare timer won't fire in this round, and the limit is
110
diff --git a/hw/nvram/xlnx-versal-efuse-cache.c b/hw/nvram/xlnx-versal-efuse-cache.c
91
+ * set to a value below the compare value. This practically means
111
new file mode 100644
92
+ * it will never fire, so it can be switched off.
112
index XXXXXXX..XXXXXXX
93
+ */
113
--- /dev/null
94
+ is_active = false;
114
+++ b/hw/nvram/xlnx-versal-efuse-cache.c
95
}
115
@@ -XXX,XX +XXX,XX @@
96
- ptimer_set_count(s->timer_cmp, next);
116
+/*
97
}
117
+ * QEMU model of the EFuse_Cache
98
+
118
+ *
99
+ /*
119
+ * Copyright (c) 2017 Xilinx Inc.
100
+ * Set the compare timer and let it run, or stop it. This is agnostic
120
+ *
101
+ * of CR.OCIEN bit, as this bit affects interrupt generation only. The
121
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
102
+ * compare timer needs to run even if no interrupts are to be generated,
122
+ * of this software and associated documentation files (the "Software"), to deal
103
+ * because the SR.OCIF bit must be updated also.
123
+ * in the Software without restriction, including without limitation the rights
104
+ * Note that the timer might already be stopped or be running with
124
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
105
+ * counter values. However, finding out when an update is needed and
125
+ * copies of the Software, and to permit persons to whom the Software is
106
+ * when not is not trivial. It's much easier applying the setting again,
126
+ * furnished to do so, subject to the following conditions:
107
+ * as this does not harm either and the overhead is negligible.
127
+ *
108
+ */
128
+ * The above copyright notice and this permission notice shall be included in
109
+ if (is_active) {
129
+ * all copies or substantial portions of the Software.
110
+ ptimer_set_count(s->timer_cmp, counter);
130
+ *
111
+ ptimer_run(s->timer_cmp, is_oneshot ? 1 : 0);
131
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
112
+ } else {
132
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
113
+ ptimer_stop(s->timer_cmp);
133
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
134
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
135
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
136
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
137
+ * THE SOFTWARE.
138
+ */
139
+
140
+#include "qemu/osdep.h"
141
+#include "hw/nvram/xlnx-versal-efuse.h"
142
+
143
+#include "qemu/log.h"
144
+#include "hw/qdev-properties.h"
145
+
146
+#define MR_SIZE 0xC00
147
+
148
+static uint64_t efuse_cache_read(void *opaque, hwaddr addr, unsigned size)
149
+{
150
+ XlnxVersalEFuseCache *s = XLNX_VERSAL_EFUSE_CACHE(opaque);
151
+ unsigned int w0 = QEMU_ALIGN_DOWN(addr * 8, 32);
152
+ unsigned int w1 = QEMU_ALIGN_DOWN((addr + size - 1) * 8, 32);
153
+
154
+ uint64_t ret;
155
+
156
+ assert(w0 == w1 || (w0 + 32) == w1);
157
+
158
+ ret = xlnx_versal_efuse_read_row(s->efuse, w1, NULL);
159
+ if (w0 < w1) {
160
+ ret <<= 32;
161
+ ret |= xlnx_versal_efuse_read_row(s->efuse, w0, NULL);
162
+ }
114
+ }
163
+
115
+
164
+ /* If 'addr' unaligned, the guest is always assumed to be little-endian. */
116
}
165
+ addr &= 3;
117
166
+ if (addr) {
118
static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
167
+ ret >>= 8 * addr;
119
{
168
+ }
120
- uint32_t freq = 0;
169
+
121
uint32_t oldcr = s->cr;
170
+ return ret;
122
171
+}
123
s->cr = value & 0x03ffffff;
172
+
124
173
+static void efuse_cache_write(void *opaque, hwaddr addr, uint64_t value,
125
if (s->cr & CR_SWR) {
174
+ unsigned size)
126
- /* handle the reset */
175
+{
127
+ /*
176
+ /* No Register Writes allowed */
128
+ * Reset clears CR.SWR again. It does not touch CR.EN, but the timers
177
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: efuse cache registers are read-only",
129
+ * are still stopped because the input clock is disabled.
178
+ __func__);
130
+ */
179
+}
131
imx_epit_reset(s, false);
180
+
132
+ } else {
181
+static const MemoryRegionOps efuse_cache_ops = {
133
+ uint32_t freq;
182
+ .read = efuse_cache_read,
134
+ uint32_t toggled_cr_bits = oldcr ^ s->cr;
183
+ .write = efuse_cache_write,
135
+ /* re-initialize the limits if CR.RLD has changed */
184
+ .endianness = DEVICE_LITTLE_ENDIAN,
136
+ bool set_limit = toggled_cr_bits & CR_RLD;
185
+ .valid = {
137
+ /* set the counter if the timer got just enabled and CR.ENMOD is set */
186
+ .min_access_size = 1,
138
+ bool is_switched_on = (toggled_cr_bits & s->cr) & CR_EN;
187
+ .max_access_size = 4,
139
+ bool set_counter = is_switched_on && (s->cr & CR_ENMOD);
188
+ },
140
+
189
+};
141
+ ptimer_transaction_begin(s->timer_cmp);
190
+
142
+ ptimer_transaction_begin(s->timer_reload);
191
+static void efuse_cache_init(Object *obj)
143
+ freq = imx_epit_get_freq(s);
192
+{
144
+ if (freq) {
193
+ XlnxVersalEFuseCache *s = XLNX_VERSAL_EFUSE_CACHE(obj);
145
+ ptimer_set_freq(s->timer_reload, freq);
194
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
146
+ ptimer_set_freq(s->timer_cmp, freq);
195
+
196
+ memory_region_init_io(&s->iomem, obj, &efuse_cache_ops, s,
197
+ TYPE_XLNX_VERSAL_EFUSE_CACHE, MR_SIZE);
198
+ sysbus_init_mmio(sbd, &s->iomem);
199
+}
200
+
201
+static Property efuse_cache_props[] = {
202
+ DEFINE_PROP_LINK("efuse",
203
+ XlnxVersalEFuseCache, efuse,
204
+ TYPE_XLNX_EFUSE, XlnxEFuse *),
205
+
206
+ DEFINE_PROP_END_OF_LIST(),
207
+};
208
+
209
+static void efuse_cache_class_init(ObjectClass *klass, void *data)
210
+{
211
+ DeviceClass *dc = DEVICE_CLASS(klass);
212
+
213
+ device_class_set_props(dc, efuse_cache_props);
214
+}
215
+
216
+static const TypeInfo efuse_cache_info = {
217
+ .name = TYPE_XLNX_VERSAL_EFUSE_CACHE,
218
+ .parent = TYPE_SYS_BUS_DEVICE,
219
+ .instance_size = sizeof(XlnxVersalEFuseCache),
220
+ .class_init = efuse_cache_class_init,
221
+ .instance_init = efuse_cache_init,
222
+};
223
+
224
+static void efuse_cache_register_types(void)
225
+{
226
+ type_register_static(&efuse_cache_info);
227
+}
228
+
229
+type_init(efuse_cache_register_types)
230
diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c
231
new file mode 100644
232
index XXXXXXX..XXXXXXX
233
--- /dev/null
234
+++ b/hw/nvram/xlnx-versal-efuse-ctrl.c
235
@@ -XXX,XX +XXX,XX @@
236
+/*
237
+ * QEMU model of the Versal eFuse controller
238
+ *
239
+ * Copyright (c) 2020 Xilinx Inc.
240
+ *
241
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
242
+ * of this software and associated documentation files (the "Software"), to deal
243
+ * in the Software without restriction, including without limitation the rights
244
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
245
+ * copies of the Software, and to permit persons to whom the Software is
246
+ * furnished to do so, subject to the following conditions:
247
+ *
248
+ * The above copyright notice and this permission notice shall be included in
249
+ * all copies or substantial portions of the Software.
250
+ *
251
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
252
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
253
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
254
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
255
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
256
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
257
+ * THE SOFTWARE.
258
+ */
259
+
260
+#include "qemu/osdep.h"
261
+#include "hw/nvram/xlnx-versal-efuse.h"
262
+
263
+#include "qemu/log.h"
264
+#include "qapi/error.h"
265
+#include "migration/vmstate.h"
266
+#include "hw/qdev-properties.h"
267
+
268
+#ifndef XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG
269
+#define XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG 0
270
+#endif
271
+
272
+REG32(WR_LOCK, 0x0)
273
+ FIELD(WR_LOCK, LOCK, 0, 16)
274
+REG32(CFG, 0x4)
275
+ FIELD(CFG, SLVERR_ENABLE, 5, 1)
276
+ FIELD(CFG, MARGIN_RD, 2, 1)
277
+ FIELD(CFG, PGM_EN, 1, 1)
278
+REG32(STATUS, 0x8)
279
+ FIELD(STATUS, AES_USER_KEY_1_CRC_PASS, 11, 1)
280
+ FIELD(STATUS, AES_USER_KEY_1_CRC_DONE, 10, 1)
281
+ FIELD(STATUS, AES_USER_KEY_0_CRC_PASS, 9, 1)
282
+ FIELD(STATUS, AES_USER_KEY_0_CRC_DONE, 8, 1)
283
+ FIELD(STATUS, AES_CRC_PASS, 7, 1)
284
+ FIELD(STATUS, AES_CRC_DONE, 6, 1)
285
+ FIELD(STATUS, CACHE_DONE, 5, 1)
286
+ FIELD(STATUS, CACHE_LOAD, 4, 1)
287
+ FIELD(STATUS, EFUSE_2_TBIT, 2, 1)
288
+ FIELD(STATUS, EFUSE_1_TBIT, 1, 1)
289
+ FIELD(STATUS, EFUSE_0_TBIT, 0, 1)
290
+REG32(EFUSE_PGM_ADDR, 0xc)
291
+ FIELD(EFUSE_PGM_ADDR, PAGE, 13, 4)
292
+ FIELD(EFUSE_PGM_ADDR, ROW, 5, 8)
293
+ FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5)
294
+REG32(EFUSE_RD_ADDR, 0x10)
295
+ FIELD(EFUSE_RD_ADDR, PAGE, 13, 4)
296
+ FIELD(EFUSE_RD_ADDR, ROW, 5, 8)
297
+REG32(EFUSE_RD_DATA, 0x14)
298
+REG32(TPGM, 0x18)
299
+ FIELD(TPGM, VALUE, 0, 16)
300
+REG32(TRD, 0x1c)
301
+ FIELD(TRD, VALUE, 0, 8)
302
+REG32(TSU_H_PS, 0x20)
303
+ FIELD(TSU_H_PS, VALUE, 0, 8)
304
+REG32(TSU_H_PS_CS, 0x24)
305
+ FIELD(TSU_H_PS_CS, VALUE, 0, 8)
306
+REG32(TRDM, 0x28)
307
+ FIELD(TRDM, VALUE, 0, 8)
308
+REG32(TSU_H_CS, 0x2c)
309
+ FIELD(TSU_H_CS, VALUE, 0, 8)
310
+REG32(EFUSE_ISR, 0x30)
311
+ FIELD(EFUSE_ISR, APB_SLVERR, 31, 1)
312
+ FIELD(EFUSE_ISR, CACHE_PARITY_E2, 14, 1)
313
+ FIELD(EFUSE_ISR, CACHE_PARITY_E1, 13, 1)
314
+ FIELD(EFUSE_ISR, CACHE_PARITY_E0S, 12, 1)
315
+ FIELD(EFUSE_ISR, CACHE_PARITY_E0R, 11, 1)
316
+ FIELD(EFUSE_ISR, CACHE_APB_SLVERR, 10, 1)
317
+ FIELD(EFUSE_ISR, CACHE_REQ_ERROR, 9, 1)
318
+ FIELD(EFUSE_ISR, MAIN_REQ_ERROR, 8, 1)
319
+ FIELD(EFUSE_ISR, READ_ON_CACHE_LD, 7, 1)
320
+ FIELD(EFUSE_ISR, CACHE_FSM_ERROR, 6, 1)
321
+ FIELD(EFUSE_ISR, MAIN_FSM_ERROR, 5, 1)
322
+ FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1)
323
+ FIELD(EFUSE_ISR, RD_ERROR, 3, 1)
324
+ FIELD(EFUSE_ISR, RD_DONE, 2, 1)
325
+ FIELD(EFUSE_ISR, PGM_ERROR, 1, 1)
326
+ FIELD(EFUSE_ISR, PGM_DONE, 0, 1)
327
+REG32(EFUSE_IMR, 0x34)
328
+ FIELD(EFUSE_IMR, APB_SLVERR, 31, 1)
329
+ FIELD(EFUSE_IMR, CACHE_PARITY_E2, 14, 1)
330
+ FIELD(EFUSE_IMR, CACHE_PARITY_E1, 13, 1)
331
+ FIELD(EFUSE_IMR, CACHE_PARITY_E0S, 12, 1)
332
+ FIELD(EFUSE_IMR, CACHE_PARITY_E0R, 11, 1)
333
+ FIELD(EFUSE_IMR, CACHE_APB_SLVERR, 10, 1)
334
+ FIELD(EFUSE_IMR, CACHE_REQ_ERROR, 9, 1)
335
+ FIELD(EFUSE_IMR, MAIN_REQ_ERROR, 8, 1)
336
+ FIELD(EFUSE_IMR, READ_ON_CACHE_LD, 7, 1)
337
+ FIELD(EFUSE_IMR, CACHE_FSM_ERROR, 6, 1)
338
+ FIELD(EFUSE_IMR, MAIN_FSM_ERROR, 5, 1)
339
+ FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1)
340
+ FIELD(EFUSE_IMR, RD_ERROR, 3, 1)
341
+ FIELD(EFUSE_IMR, RD_DONE, 2, 1)
342
+ FIELD(EFUSE_IMR, PGM_ERROR, 1, 1)
343
+ FIELD(EFUSE_IMR, PGM_DONE, 0, 1)
344
+REG32(EFUSE_IER, 0x38)
345
+ FIELD(EFUSE_IER, APB_SLVERR, 31, 1)
346
+ FIELD(EFUSE_IER, CACHE_PARITY_E2, 14, 1)
347
+ FIELD(EFUSE_IER, CACHE_PARITY_E1, 13, 1)
348
+ FIELD(EFUSE_IER, CACHE_PARITY_E0S, 12, 1)
349
+ FIELD(EFUSE_IER, CACHE_PARITY_E0R, 11, 1)
350
+ FIELD(EFUSE_IER, CACHE_APB_SLVERR, 10, 1)
351
+ FIELD(EFUSE_IER, CACHE_REQ_ERROR, 9, 1)
352
+ FIELD(EFUSE_IER, MAIN_REQ_ERROR, 8, 1)
353
+ FIELD(EFUSE_IER, READ_ON_CACHE_LD, 7, 1)
354
+ FIELD(EFUSE_IER, CACHE_FSM_ERROR, 6, 1)
355
+ FIELD(EFUSE_IER, MAIN_FSM_ERROR, 5, 1)
356
+ FIELD(EFUSE_IER, CACHE_ERROR, 4, 1)
357
+ FIELD(EFUSE_IER, RD_ERROR, 3, 1)
358
+ FIELD(EFUSE_IER, RD_DONE, 2, 1)
359
+ FIELD(EFUSE_IER, PGM_ERROR, 1, 1)
360
+ FIELD(EFUSE_IER, PGM_DONE, 0, 1)
361
+REG32(EFUSE_IDR, 0x3c)
362
+ FIELD(EFUSE_IDR, APB_SLVERR, 31, 1)
363
+ FIELD(EFUSE_IDR, CACHE_PARITY_E2, 14, 1)
364
+ FIELD(EFUSE_IDR, CACHE_PARITY_E1, 13, 1)
365
+ FIELD(EFUSE_IDR, CACHE_PARITY_E0S, 12, 1)
366
+ FIELD(EFUSE_IDR, CACHE_PARITY_E0R, 11, 1)
367
+ FIELD(EFUSE_IDR, CACHE_APB_SLVERR, 10, 1)
368
+ FIELD(EFUSE_IDR, CACHE_REQ_ERROR, 9, 1)
369
+ FIELD(EFUSE_IDR, MAIN_REQ_ERROR, 8, 1)
370
+ FIELD(EFUSE_IDR, READ_ON_CACHE_LD, 7, 1)
371
+ FIELD(EFUSE_IDR, CACHE_FSM_ERROR, 6, 1)
372
+ FIELD(EFUSE_IDR, MAIN_FSM_ERROR, 5, 1)
373
+ FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1)
374
+ FIELD(EFUSE_IDR, RD_ERROR, 3, 1)
375
+ FIELD(EFUSE_IDR, RD_DONE, 2, 1)
376
+ FIELD(EFUSE_IDR, PGM_ERROR, 1, 1)
377
+ FIELD(EFUSE_IDR, PGM_DONE, 0, 1)
378
+REG32(EFUSE_CACHE_LOAD, 0x40)
379
+ FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1)
380
+REG32(EFUSE_PGM_LOCK, 0x44)
381
+ FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1)
382
+REG32(EFUSE_AES_CRC, 0x48)
383
+REG32(EFUSE_AES_USR_KEY0_CRC, 0x4c)
384
+REG32(EFUSE_AES_USR_KEY1_CRC, 0x50)
385
+REG32(EFUSE_PD, 0x54)
386
+REG32(EFUSE_ANLG_OSC_SW_1LP, 0x60)
387
+REG32(EFUSE_TEST_CTRL, 0x100)
388
+
389
+#define R_MAX (R_EFUSE_TEST_CTRL + 1)
390
+
391
+#define R_WR_LOCK_UNLOCK_PASSCODE (0xDF0D)
392
+
393
+/*
394
+ * eFuse layout references:
395
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilnvm/src/xnvm_efuse_hw.h
396
+ */
397
+#define BIT_POS_OF(A_) \
398
+ ((uint32_t)((A_) & (R_EFUSE_PGM_ADDR_ROW_MASK | \
399
+ R_EFUSE_PGM_ADDR_COLUMN_MASK)))
400
+
401
+#define BIT_POS(R_, C_) \
402
+ ((uint32_t)((R_EFUSE_PGM_ADDR_ROW_MASK \
403
+ & ((R_) << R_EFUSE_PGM_ADDR_ROW_SHIFT)) \
404
+ | \
405
+ (R_EFUSE_PGM_ADDR_COLUMN_MASK \
406
+ & ((C_) << R_EFUSE_PGM_ADDR_COLUMN_SHIFT))))
407
+
408
+#define EFUSE_TBIT_POS(A_) (BIT_POS_OF(A_) >= BIT_POS(0, 28))
409
+
410
+#define EFUSE_ANCHOR_ROW (0)
411
+#define EFUSE_ANCHOR_3_COL (27)
412
+#define EFUSE_ANCHOR_1_COL (1)
413
+
414
+#define EFUSE_AES_KEY_START BIT_POS(12, 0)
415
+#define EFUSE_AES_KEY_END BIT_POS(19, 31)
416
+#define EFUSE_USER_KEY_0_START BIT_POS(20, 0)
417
+#define EFUSE_USER_KEY_0_END BIT_POS(27, 31)
418
+#define EFUSE_USER_KEY_1_START BIT_POS(28, 0)
419
+#define EFUSE_USER_KEY_1_END BIT_POS(35, 31)
420
+
421
+#define EFUSE_RD_BLOCKED_START EFUSE_AES_KEY_START
422
+#define EFUSE_RD_BLOCKED_END EFUSE_USER_KEY_1_END
423
+
424
+#define EFUSE_GLITCH_DET_WR_LK BIT_POS(4, 31)
425
+#define EFUSE_PPK0_WR_LK BIT_POS(43, 6)
426
+#define EFUSE_PPK1_WR_LK BIT_POS(43, 7)
427
+#define EFUSE_PPK2_WR_LK BIT_POS(43, 8)
428
+#define EFUSE_AES_WR_LK BIT_POS(43, 11)
429
+#define EFUSE_USER_KEY_0_WR_LK BIT_POS(43, 13)
430
+#define EFUSE_USER_KEY_1_WR_LK BIT_POS(43, 15)
431
+#define EFUSE_PUF_SYN_LK BIT_POS(43, 16)
432
+#define EFUSE_DNA_WR_LK BIT_POS(43, 27)
433
+#define EFUSE_BOOT_ENV_WR_LK BIT_POS(43, 28)
434
+
435
+#define EFUSE_PGM_LOCKED_START BIT_POS(44, 0)
436
+#define EFUSE_PGM_LOCKED_END BIT_POS(51, 31)
437
+
438
+#define EFUSE_PUF_PAGE (2)
439
+#define EFUSE_PUF_SYN_START BIT_POS(129, 0)
440
+#define EFUSE_PUF_SYN_END BIT_POS(255, 27)
441
+
442
+#define EFUSE_KEY_CRC_LK_ROW (43)
443
+#define EFUSE_AES_KEY_CRC_LK_MASK ((1U << 9) | (1U << 10))
444
+#define EFUSE_USER_KEY_0_CRC_LK_MASK (1U << 12)
445
+#define EFUSE_USER_KEY_1_CRC_LK_MASK (1U << 14)
446
+
447
+/*
448
+ * A handy macro to return value of an array element,
449
+ * or a specific default if given index is out of bound.
450
+ */
451
+#define ARRAY_GET(A_, I_, D_) \
452
+ ((unsigned int)(I_) < ARRAY_SIZE(A_) ? (A_)[I_] : (D_))
453
+
454
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxVersalEFuseCtrl *)0)->regs));
455
+
456
+typedef struct XlnxEFuseLkSpec {
457
+ uint16_t row;
458
+ uint16_t lk_bit;
459
+} XlnxEFuseLkSpec;
460
+
461
+static void efuse_imr_update_irq(XlnxVersalEFuseCtrl *s)
462
+{
463
+ bool pending = s->regs[R_EFUSE_ISR] & ~s->regs[R_EFUSE_IMR];
464
+ qemu_set_irq(s->irq_efuse_imr, pending);
465
+}
466
+
467
+static void efuse_isr_postw(RegisterInfo *reg, uint64_t val64)
468
+{
469
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
470
+ efuse_imr_update_irq(s);
471
+}
472
+
473
+static uint64_t efuse_ier_prew(RegisterInfo *reg, uint64_t val64)
474
+{
475
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
476
+ uint32_t val = val64;
477
+
478
+ s->regs[R_EFUSE_IMR] &= ~val;
479
+ efuse_imr_update_irq(s);
480
+ return 0;
481
+}
482
+
483
+static uint64_t efuse_idr_prew(RegisterInfo *reg, uint64_t val64)
484
+{
485
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
486
+ uint32_t val = val64;
487
+
488
+ s->regs[R_EFUSE_IMR] |= val;
489
+ efuse_imr_update_irq(s);
490
+ return 0;
491
+}
492
+
493
+static void efuse_status_tbits_sync(XlnxVersalEFuseCtrl *s)
494
+{
495
+ uint32_t check = xlnx_efuse_tbits_check(s->efuse);
496
+ uint32_t val = s->regs[R_STATUS];
497
+
498
+ val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0)));
499
+ val = FIELD_DP32(val, STATUS, EFUSE_1_TBIT, !!(check & (1 << 1)));
500
+ val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 2)));
501
+
502
+ s->regs[R_STATUS] = val;
503
+}
504
+
505
+static void efuse_anchor_bits_check(XlnxVersalEFuseCtrl *s)
506
+{
507
+ unsigned page;
508
+
509
+ if (!s->efuse || !s->efuse->init_tbits) {
510
+ return;
511
+ }
512
+
513
+ for (page = 0; page < s->efuse->efuse_nr; page++) {
514
+ uint32_t row = 0, bit;
515
+
516
+ row = FIELD_DP32(row, EFUSE_PGM_ADDR, PAGE, page);
517
+ row = FIELD_DP32(row, EFUSE_PGM_ADDR, ROW, EFUSE_ANCHOR_ROW);
518
+
519
+ bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_3_COL);
520
+ if (!xlnx_efuse_get_bit(s->efuse, bit)) {
521
+ xlnx_efuse_set_bit(s->efuse, bit);
522
+ }
147
+ }
523
+
148
+
524
+ bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_1_COL);
149
+ if (set_limit || set_counter) {
525
+ if (!xlnx_efuse_get_bit(s->efuse, bit)) {
150
+ uint64_t limit = (s->cr & CR_RLD) ? s->lr : EPIT_TIMER_MAX;
526
+ xlnx_efuse_set_bit(s->efuse, bit);
151
+ ptimer_set_limit(s->timer_reload, limit, set_counter ? 1 : 0);
152
+ if (set_limit) {
153
+ ptimer_set_limit(s->timer_cmp, limit, 0);
154
+ }
527
+ }
155
+ }
528
+ }
156
+ /*
529
+}
157
+ * If there is an input clock and the peripheral is enabled, then
530
+
158
+ * ensure the wall clock timer is ticking. Otherwise stop the timers.
531
+static void efuse_key_crc_check(RegisterInfo *reg, uint32_t crc,
159
+ * The compare timer will be updated later.
532
+ uint32_t pass_mask, uint32_t done_mask,
160
+ */
533
+ unsigned first, uint32_t lk_mask)
161
+ if (freq && (s->cr & CR_EN)) {
534
+{
162
+ ptimer_run(s->timer_reload, 0);
535
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
163
+ } else {
536
+ uint32_t r, lk_bits;
164
+ ptimer_stop(s->timer_reload);
537
+
538
+ /*
539
+ * To start, assume both DONE and PASS, and clear PASS by xor
540
+ * if CRC-check fails or CRC-check disabled by lock fuse.
541
+ */
542
+ r = s->regs[R_STATUS] | done_mask | pass_mask;
543
+
544
+ lk_bits = xlnx_efuse_get_row(s->efuse, EFUSE_KEY_CRC_LK_ROW) & lk_mask;
545
+ if (lk_bits == 0 && xlnx_efuse_k256_check(s->efuse, crc, first)) {
546
+ pass_mask = 0;
547
+ }
548
+
549
+ s->regs[R_STATUS] = r ^ pass_mask;
550
+}
551
+
552
+static void efuse_data_sync(XlnxVersalEFuseCtrl *s)
553
+{
554
+ efuse_status_tbits_sync(s);
555
+}
556
+
557
+static int efuse_lk_spec_cmp(const void *a, const void *b)
558
+{
559
+ uint16_t r1 = ((const XlnxEFuseLkSpec *)a)->row;
560
+ uint16_t r2 = ((const XlnxEFuseLkSpec *)b)->row;
561
+
562
+ return (r1 > r2) - (r1 < r2);
563
+}
564
+
565
+static void efuse_lk_spec_sort(XlnxVersalEFuseCtrl *s)
566
+{
567
+ XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec;
568
+ const uint32_t n8 = s->extra_pg0_lock_n16 * 2;
569
+ const uint32_t sz = sizeof(ary[0]);
570
+ const uint32_t cnt = n8 / sz;
571
+
572
+ if (ary && cnt) {
573
+ qsort(ary, cnt, sz, efuse_lk_spec_cmp);
574
+ }
575
+}
576
+
577
+static uint32_t efuse_lk_spec_find(XlnxVersalEFuseCtrl *s, uint32_t row)
578
+{
579
+ const XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec;
580
+ const uint32_t n8 = s->extra_pg0_lock_n16 * 2;
581
+ const uint32_t sz = sizeof(ary[0]);
582
+ const uint32_t cnt = n8 / sz;
583
+ const XlnxEFuseLkSpec *item = NULL;
584
+
585
+ if (ary && cnt) {
586
+ XlnxEFuseLkSpec k = { .row = row, };
587
+
588
+ item = bsearch(&k, ary, cnt, sz, efuse_lk_spec_cmp);
589
+ }
590
+
591
+ return item ? item->lk_bit : 0;
592
+}
593
+
594
+static uint32_t efuse_bit_locked(XlnxVersalEFuseCtrl *s, uint32_t bit)
595
+{
596
+ /* Hard-coded locks */
597
+ static const uint16_t pg0_hard_lock[] = {
598
+ [4] = EFUSE_GLITCH_DET_WR_LK,
599
+ [37] = EFUSE_BOOT_ENV_WR_LK,
600
+
601
+ [8 ... 11] = EFUSE_DNA_WR_LK,
602
+ [12 ... 19] = EFUSE_AES_WR_LK,
603
+ [20 ... 27] = EFUSE_USER_KEY_0_WR_LK,
604
+ [28 ... 35] = EFUSE_USER_KEY_1_WR_LK,
605
+ [64 ... 71] = EFUSE_PPK0_WR_LK,
606
+ [72 ... 79] = EFUSE_PPK1_WR_LK,
607
+ [80 ... 87] = EFUSE_PPK2_WR_LK,
608
+ };
609
+
610
+ uint32_t row = FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW);
611
+ uint32_t lk_bit = ARRAY_GET(pg0_hard_lock, row, 0);
612
+
613
+ return lk_bit ? lk_bit : efuse_lk_spec_find(s, row);
614
+}
615
+
616
+static bool efuse_pgm_locked(XlnxVersalEFuseCtrl *s, unsigned int bit)
617
+{
618
+
619
+ unsigned int lock = 1;
620
+
621
+ /* Global lock */
622
+ if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) {
623
+ goto ret_lock;
624
+ }
625
+
626
+ /* Row lock */
627
+ switch (FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE)) {
628
+ case 0:
629
+ if (ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK) &&
630
+ bit >= EFUSE_PGM_LOCKED_START && bit <= EFUSE_PGM_LOCKED_END) {
631
+ goto ret_lock;
632
+ }
165
+ }
633
+
166
+ /* Commit changes to reload timer, so they can propagate. */
634
+ lock = efuse_bit_locked(s, bit);
167
+ ptimer_transaction_commit(s->timer_reload);
635
+ break;
168
+ /* Update compare timer based on the committed reload timer value. */
636
+ case EFUSE_PUF_PAGE:
169
+ imx_epit_update_compare_timer(s);
637
+ if (bit < EFUSE_PUF_SYN_START || bit > EFUSE_PUF_SYN_END) {
170
+ ptimer_transaction_commit(s->timer_cmp);
638
+ lock = 0;
171
}
639
+ goto ret_lock;
172
640
+ }
173
/*
641
+
174
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
642
+ lock = EFUSE_PUF_SYN_LK;
175
* - write to CR.EN or CR.OCIE
643
+ break;
176
*/
644
+ default:
177
imx_epit_update_int(s);
645
+ lock = 0;
178
-
646
+ goto ret_lock;
179
- /*
647
+ }
180
- * TODO: could we 'break' here for reset? following operations appear
648
+
181
- * to duplicate the work imx_epit_reset() already did.
649
+ /* Row lock by an efuse bit */
182
- */
650
+ if (lock) {
183
-
651
+ lock = xlnx_efuse_get_bit(s->efuse, lock);
184
- ptimer_transaction_begin(s->timer_cmp);
652
+ }
185
- ptimer_transaction_begin(s->timer_reload);
653
+
186
-
654
+ ret_lock:
187
- /*
655
+ return lock != 0;
188
- * Update the frequency. In case of a reset the input clock was
656
+}
189
- * switched off, so this can be skipped.
657
+
190
- */
658
+static void efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64)
191
- if (!(s->cr & CR_SWR)) {
659
+{
192
- freq = imx_epit_get_freq(s);
660
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
193
- if (freq) {
661
+ unsigned bit = val64;
194
- ptimer_set_freq(s->timer_reload, freq);
662
+ bool ok = false;
195
- ptimer_set_freq(s->timer_cmp, freq);
663
+
196
- }
664
+ /* Always zero out PGM_ADDR because it is write-only */
197
- }
665
+ s->regs[R_EFUSE_PGM_ADDR] = 0;
198
-
666
+
199
- if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
667
+ /*
200
- if (s->cr & CR_ENMOD) {
668
+ * Indicate error if bit is write-protected (or read-only
201
- if (s->cr & CR_RLD) {
669
+ * as guarded by efuse_set_bit()).
202
- ptimer_set_limit(s->timer_reload, s->lr, 1);
670
+ *
203
- ptimer_set_limit(s->timer_cmp, s->lr, 1);
671
+ * Keep it simple by not modeling program timing.
204
- } else {
672
+ *
205
- ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
673
+ * Note: model must NEVER clear the PGM_ERROR bit; it is
206
- ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
674
+ * up to guest to do so (or by reset).
207
- }
675
+ */
208
- }
676
+ if (efuse_pgm_locked(s, bit)) {
209
-
677
+ qemu_log_mask(LOG_GUEST_ERROR,
210
- imx_epit_reload_compare_timer(s);
678
+ "%s: Denied setting of efuse<%u, %u, %u>\n",
211
- ptimer_run(s->timer_reload, 0);
679
+ object_get_canonical_path(OBJECT(s)),
212
- if (s->cr & CR_OCIEN) {
680
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE),
213
- ptimer_run(s->timer_cmp, 0);
681
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW),
214
- } else {
682
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, COLUMN));
215
- ptimer_stop(s->timer_cmp);
683
+ } else if (xlnx_efuse_set_bit(s->efuse, bit)) {
216
- }
684
+ ok = true;
217
- } else if (!(s->cr & CR_EN)) {
685
+ if (EFUSE_TBIT_POS(bit)) {
218
- /* stop both timers */
686
+ efuse_status_tbits_sync(s);
219
- ptimer_stop(s->timer_reload);
687
+ }
220
- ptimer_stop(s->timer_cmp);
688
+ }
221
- } else if (s->cr & CR_OCIEN) {
689
+
222
- if (!(oldcr & CR_OCIEN)) {
690
+ if (!ok) {
223
- imx_epit_reload_compare_timer(s);
691
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1);
224
- ptimer_run(s->timer_cmp, 0);
692
+ }
225
- }
693
+
226
- } else {
694
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1);
227
- ptimer_stop(s->timer_cmp);
695
+ efuse_imr_update_irq(s);
228
- }
696
+}
229
-
697
+
230
- ptimer_transaction_commit(s->timer_cmp);
698
+static void efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64)
231
- ptimer_transaction_commit(s->timer_reload);
699
+{
232
}
700
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
233
701
+ unsigned bit = val64;
234
static void imx_epit_write_sr(IMXEPITState *s, uint32_t value)
702
+ bool denied;
235
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_lr(IMXEPITState *s, uint32_t value)
703
+
236
/* If IOVW bit is set then set the timer value */
704
+ /* Always zero out RD_ADDR because it is write-only */
237
ptimer_set_count(s->timer_reload, s->lr);
705
+ s->regs[R_EFUSE_RD_ADDR] = 0;
238
}
706
+
239
- /*
707
+ /*
240
- * Commit the change to s->timer_reload, so it can propagate. Otherwise
708
+ * Indicate error if row is read-blocked.
241
- * the timer interrupt may not fire properly. The commit must happen
709
+ *
242
- * before calling imx_epit_reload_compare_timer(), which reads
710
+ * Note: model must NEVER clear the RD_ERROR bit; it is
243
- * s->timer_reload internally again.
711
+ * up to guest to do so (or by reset).
244
- */
712
+ */
245
+ /* Commit the changes to s->timer_reload, so they can propagate. */
713
+ s->regs[R_EFUSE_RD_DATA] = xlnx_versal_efuse_read_row(s->efuse,
246
ptimer_transaction_commit(s->timer_reload);
714
+ bit, &denied);
247
- imx_epit_reload_compare_timer(s);
715
+ if (denied) {
248
+ /* Update the compare timer based on the committed reload timer value. */
716
+ qemu_log_mask(LOG_GUEST_ERROR,
249
+ imx_epit_update_compare_timer(s);
717
+ "%s: Denied reading of efuse<%u, %u>\n",
250
ptimer_transaction_commit(s->timer_cmp);
718
+ object_get_canonical_path(OBJECT(s)),
251
}
719
+ FIELD_EX32(bit, EFUSE_RD_ADDR, PAGE),
252
720
+ FIELD_EX32(bit, EFUSE_RD_ADDR, ROW));
253
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value)
721
+
254
{
722
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1);
255
s->cmp = value;
723
+ }
256
724
+
257
+ /* Update the compare timer based on the committed reload timer value. */
725
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1);
258
ptimer_transaction_begin(s->timer_cmp);
726
+ efuse_imr_update_irq(s);
259
- imx_epit_reload_compare_timer(s);
727
+ return;
260
+ imx_epit_update_compare_timer(s);
728
+}
261
ptimer_transaction_commit(s->timer_cmp);
729
+
262
}
730
+static uint64_t efuse_cache_load_prew(RegisterInfo *reg, uint64_t val64)
263
731
+{
264
@@ -XXX,XX +XXX,XX @@ static void imx_epit_cmp(void *opaque)
732
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
265
{
733
+
266
IMXEPITState *s = IMX_EPIT(opaque);
734
+ if (val64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) {
267
735
+ efuse_data_sync(s);
268
+ /* The cmp ptimer can't be running when the peripheral is disabled */
736
+
269
+ assert(s->cr & CR_EN);
737
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
270
+
738
+ efuse_imr_update_irq(s);
271
DPRINTF("sr was %d\n", s->sr);
739
+ }
272
/* Set interrupt status bit SR.OCIF and update the interrupt state */
740
+
273
s->sr |= SR_OCIF;
741
+ return 0;
742
+}
743
+
744
+static uint64_t efuse_pgm_lock_prew(RegisterInfo *reg, uint64_t val64)
745
+{
746
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
747
+
748
+ /* Ignore all other bits */
749
+ val64 = FIELD_EX32(val64, EFUSE_PGM_LOCK, SPK_ID_LOCK);
750
+
751
+ /* Once the bit is written 1, only reset will clear it to 0 */
752
+ val64 |= ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK);
753
+
754
+ return val64;
755
+}
756
+
757
+static void efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
758
+{
759
+ efuse_key_crc_check(reg, val64,
760
+ R_STATUS_AES_CRC_PASS_MASK,
761
+ R_STATUS_AES_CRC_DONE_MASK,
762
+ EFUSE_AES_KEY_START,
763
+ EFUSE_AES_KEY_CRC_LK_MASK);
764
+}
765
+
766
+static void efuse_aes_u0_crc_postw(RegisterInfo *reg, uint64_t val64)
767
+{
768
+ efuse_key_crc_check(reg, val64,
769
+ R_STATUS_AES_USER_KEY_0_CRC_PASS_MASK,
770
+ R_STATUS_AES_USER_KEY_0_CRC_DONE_MASK,
771
+ EFUSE_USER_KEY_0_START,
772
+ EFUSE_USER_KEY_0_CRC_LK_MASK);
773
+}
774
+
775
+static void efuse_aes_u1_crc_postw(RegisterInfo *reg, uint64_t val64)
776
+{
777
+ efuse_key_crc_check(reg, val64,
778
+ R_STATUS_AES_USER_KEY_1_CRC_PASS_MASK,
779
+ R_STATUS_AES_USER_KEY_1_CRC_DONE_MASK,
780
+ EFUSE_USER_KEY_1_START,
781
+ EFUSE_USER_KEY_1_CRC_LK_MASK);
782
+}
783
+
784
+static uint64_t efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val)
785
+{
786
+ return val != R_WR_LOCK_UNLOCK_PASSCODE;
787
+}
788
+
789
+static const RegisterAccessInfo efuse_ctrl_regs_info[] = {
790
+ { .name = "WR_LOCK", .addr = A_WR_LOCK,
791
+ .reset = 0x1,
792
+ .pre_write = efuse_wr_lock_prew,
793
+ },{ .name = "CFG", .addr = A_CFG,
794
+ .rsvd = 0x9,
795
+ },{ .name = "STATUS", .addr = A_STATUS,
796
+ .rsvd = 0x8,
797
+ .ro = 0xfff,
798
+ },{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR,
799
+ .post_write = efuse_pgm_addr_postw,
800
+ },{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR,
801
+ .rsvd = 0x1f,
802
+ .post_write = efuse_rd_addr_postw,
803
+ },{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA,
804
+ .ro = 0xffffffff,
805
+ },{ .name = "TPGM", .addr = A_TPGM,
806
+ },{ .name = "TRD", .addr = A_TRD,
807
+ .reset = 0x19,
808
+ },{ .name = "TSU_H_PS", .addr = A_TSU_H_PS,
809
+ .reset = 0xff,
810
+ },{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS,
811
+ .reset = 0x11,
812
+ },{ .name = "TRDM", .addr = A_TRDM,
813
+ .reset = 0x3a,
814
+ },{ .name = "TSU_H_CS", .addr = A_TSU_H_CS,
815
+ .reset = 0x16,
816
+ },{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR,
817
+ .rsvd = 0x7fff8000,
818
+ .w1c = 0x80007fff,
819
+ .post_write = efuse_isr_postw,
820
+ },{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR,
821
+ .reset = 0x80007fff,
822
+ .rsvd = 0x7fff8000,
823
+ .ro = 0xffffffff,
824
+ },{ .name = "EFUSE_IER", .addr = A_EFUSE_IER,
825
+ .rsvd = 0x7fff8000,
826
+ .pre_write = efuse_ier_prew,
827
+ },{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR,
828
+ .rsvd = 0x7fff8000,
829
+ .pre_write = efuse_idr_prew,
830
+ },{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD,
831
+ .pre_write = efuse_cache_load_prew,
832
+ },{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK,
833
+ .pre_write = efuse_pgm_lock_prew,
834
+ },{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC,
835
+ .post_write = efuse_aes_crc_postw,
836
+ },{ .name = "EFUSE_AES_USR_KEY0_CRC", .addr = A_EFUSE_AES_USR_KEY0_CRC,
837
+ .post_write = efuse_aes_u0_crc_postw,
838
+ },{ .name = "EFUSE_AES_USR_KEY1_CRC", .addr = A_EFUSE_AES_USR_KEY1_CRC,
839
+ .post_write = efuse_aes_u1_crc_postw,
840
+ },{ .name = "EFUSE_PD", .addr = A_EFUSE_PD,
841
+ .ro = 0xfffffffe,
842
+ },{ .name = "EFUSE_ANLG_OSC_SW_1LP", .addr = A_EFUSE_ANLG_OSC_SW_1LP,
843
+ },{ .name = "EFUSE_TEST_CTRL", .addr = A_EFUSE_TEST_CTRL,
844
+ .reset = 0x8,
845
+ }
846
+};
847
+
848
+static void efuse_ctrl_reg_write(void *opaque, hwaddr addr,
849
+ uint64_t data, unsigned size)
850
+{
851
+ RegisterInfoArray *reg_array = opaque;
852
+ XlnxVersalEFuseCtrl *s;
853
+ Object *dev;
854
+
855
+ assert(reg_array != NULL);
856
+
857
+ dev = reg_array->mem.owner;
858
+ assert(dev);
859
+
860
+ s = XLNX_VERSAL_EFUSE_CTRL(dev);
861
+
862
+ if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {
863
+ qemu_log_mask(LOG_GUEST_ERROR,
864
+ "%s[reg_0x%02lx]: Attempt to write locked register.\n",
865
+ object_get_canonical_path(OBJECT(s)), (long)addr);
866
+ } else {
867
+ register_write_memory(opaque, addr, data, size);
868
+ }
869
+}
870
+
871
+static void efuse_ctrl_register_reset(RegisterInfo *reg)
872
+{
873
+ if (!reg->data || !reg->access) {
874
+ return;
875
+ }
876
+
877
+ /* Reset must not trigger some registers' writers */
878
+ switch (reg->access->addr) {
879
+ case A_EFUSE_AES_CRC:
880
+ case A_EFUSE_AES_USR_KEY0_CRC:
881
+ case A_EFUSE_AES_USR_KEY1_CRC:
882
+ *(uint32_t *)reg->data = reg->access->reset;
883
+ return;
884
+ }
885
+
886
+ register_reset(reg);
887
+}
888
+
889
+static void efuse_ctrl_reset(DeviceState *dev)
890
+{
891
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev);
892
+ unsigned int i;
893
+
894
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
895
+ efuse_ctrl_register_reset(&s->regs_info[i]);
896
+ }
897
+
898
+ efuse_anchor_bits_check(s);
899
+ efuse_data_sync(s);
900
+ efuse_imr_update_irq(s);
901
+}
902
+
903
+static const MemoryRegionOps efuse_ctrl_ops = {
904
+ .read = register_read_memory,
905
+ .write = efuse_ctrl_reg_write,
906
+ .endianness = DEVICE_LITTLE_ENDIAN,
907
+ .valid = {
908
+ .min_access_size = 4,
909
+ .max_access_size = 4,
910
+ },
911
+};
912
+
913
+static void efuse_ctrl_realize(DeviceState *dev, Error **errp)
914
+{
915
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev);
916
+ const uint32_t lks_sz = sizeof(XlnxEFuseLkSpec) / 2;
917
+
918
+ if (!s->efuse) {
919
+ error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE",
920
+ object_get_canonical_path(OBJECT(dev)));
921
+ return;
922
+ }
923
+
924
+ /* Sort property-defined pgm-locks for bsearch lookup */
925
+ if ((s->extra_pg0_lock_n16 % lks_sz) != 0) {
926
+ error_setg(errp,
927
+ "%s.pg0-lock: array property item-count not multiple of %u",
928
+ object_get_canonical_path(OBJECT(dev)), lks_sz);
929
+ return;
930
+ }
931
+
932
+ efuse_lk_spec_sort(s);
933
+}
934
+
935
+static void efuse_ctrl_init(Object *obj)
936
+{
937
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj);
938
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
939
+ RegisterInfoArray *reg_array;
940
+
941
+ reg_array =
942
+ register_init_block32(DEVICE(obj), efuse_ctrl_regs_info,
943
+ ARRAY_SIZE(efuse_ctrl_regs_info),
944
+ s->regs_info, s->regs,
945
+ &efuse_ctrl_ops,
946
+ XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG,
947
+ R_MAX * 4);
948
+
949
+ sysbus_init_mmio(sbd, &reg_array->mem);
950
+ sysbus_init_irq(sbd, &s->irq_efuse_imr);
951
+}
952
+
953
+static const VMStateDescription vmstate_efuse_ctrl = {
954
+ .name = TYPE_XLNX_VERSAL_EFUSE_CTRL,
955
+ .version_id = 1,
956
+ .minimum_version_id = 1,
957
+ .fields = (VMStateField[]) {
958
+ VMSTATE_UINT32_ARRAY(regs, XlnxVersalEFuseCtrl, R_MAX),
959
+ VMSTATE_END_OF_LIST(),
960
+ }
961
+};
962
+
963
+static Property efuse_ctrl_props[] = {
964
+ DEFINE_PROP_LINK("efuse",
965
+ XlnxVersalEFuseCtrl, efuse,
966
+ TYPE_XLNX_EFUSE, XlnxEFuse *),
967
+ DEFINE_PROP_ARRAY("pg0-lock",
968
+ XlnxVersalEFuseCtrl, extra_pg0_lock_n16,
969
+ extra_pg0_lock_spec, qdev_prop_uint16, uint16_t),
970
+
971
+ DEFINE_PROP_END_OF_LIST(),
972
+};
973
+
974
+static void efuse_ctrl_class_init(ObjectClass *klass, void *data)
975
+{
976
+ DeviceClass *dc = DEVICE_CLASS(klass);
977
+
978
+ dc->reset = efuse_ctrl_reset;
979
+ dc->realize = efuse_ctrl_realize;
980
+ dc->vmsd = &vmstate_efuse_ctrl;
981
+ device_class_set_props(dc, efuse_ctrl_props);
982
+}
983
+
984
+static const TypeInfo efuse_ctrl_info = {
985
+ .name = TYPE_XLNX_VERSAL_EFUSE_CTRL,
986
+ .parent = TYPE_SYS_BUS_DEVICE,
987
+ .instance_size = sizeof(XlnxVersalEFuseCtrl),
988
+ .class_init = efuse_ctrl_class_init,
989
+ .instance_init = efuse_ctrl_init,
990
+};
991
+
992
+static void efuse_ctrl_register_types(void)
993
+{
994
+ type_register_static(&efuse_ctrl_info);
995
+}
996
+
997
+type_init(efuse_ctrl_register_types)
998
+
999
+/*
1000
+ * Retrieve a row, with unreadable bits returned as 0.
1001
+ */
1002
+uint32_t xlnx_versal_efuse_read_row(XlnxEFuse *efuse,
1003
+ uint32_t bit, bool *denied)
1004
+{
1005
+ bool dummy;
1006
+
1007
+ if (!denied) {
1008
+ denied = &dummy;
1009
+ }
1010
+
1011
+ if (bit >= EFUSE_RD_BLOCKED_START && bit <= EFUSE_RD_BLOCKED_END) {
1012
+ *denied = true;
1013
+ return 0;
1014
+ }
1015
+
1016
+ *denied = false;
1017
+ return xlnx_efuse_get_row(efuse, bit);
1018
+}
1019
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
1020
index XXXXXXX..XXXXXXX 100644
1021
--- a/hw/nvram/Kconfig
1022
+++ b/hw/nvram/Kconfig
1023
@@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE_CRC
1024
config XLNX_EFUSE
1025
bool
1026
select XLNX_EFUSE_CRC
1027
+
1028
+config XLNX_EFUSE_VERSAL
1029
+ bool
1030
+ select XLNX_EFUSE
1031
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
1032
index XXXXXXX..XXXXXXX 100644
1033
--- a/hw/nvram/meson.build
1034
+++ b/hw/nvram/meson.build
1035
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
1036
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
1037
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c'))
1038
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
1039
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
1040
+ 'xlnx-versal-efuse-cache.c',
1041
+ 'xlnx-versal-efuse-ctrl.c'))
1042
1043
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
1044
--
274
--
1045
2.20.1
275
2.25.1
1046
1047
diff view generated by jsdifflib
New patch
[PULL 18/34] target/arm: Fix checkpatch comment style warnings in helper.c
1
From: Fabiano Rosas <farosas@suse.de>
1
2
3
Fix these:
4
5
WARNING: Block comments use a leading /* on a separate line
6
WARNING: Block comments use * on subsequent lines
7
WARNING: Block comments use a trailing */ on a separate line
8
9
Signed-off-by: Fabiano Rosas <farosas@suse.de>
10
Reviewed-by: Claudio Fontana <cfontana@suse.de>
11
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
12
Message-id: 20221213190537.511-2-farosas@suse.de
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/helper.c | 323 +++++++++++++++++++++++++++++---------------
16
1 file changed, 215 insertions(+), 108 deletions(-)
17
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.c
21
+++ b/target/arm/helper.c
22
@@ -XXX,XX +XXX,XX @@ uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
23
static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
24
uint64_t v)
25
{
26
- /* Raw write of a coprocessor register (as needed for migration, etc).
27
+ /*
28
+ * Raw write of a coprocessor register (as needed for migration, etc).
29
* Note that constant registers are treated as write-ignored; the
30
* caller should check for success by whether a readback gives the
31
* value written.
32
@@ -XXX,XX +XXX,XX @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
33
34
static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
35
{
36
- /* Return true if the regdef would cause an assertion if you called
37
+ /*
38
+ * Return true if the regdef would cause an assertion if you called
39
* read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
40
* program bug for it not to have the NO_RAW flag).
41
* NB that returning false here doesn't necessarily mean that calling
42
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu)
43
if (ri->type & ARM_CP_NO_RAW) {
44
continue;
45
}
46
- /* Write value and confirm it reads back as written
47
+ /*
48
+ * Write value and confirm it reads back as written
49
* (to catch read-only registers and partially read-only
50
* registers where the incoming migration value doesn't match)
51
*/
52
@@ -XXX,XX +XXX,XX @@ static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
53
54
void init_cpreg_list(ARMCPU *cpu)
55
{
56
- /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
57
+ /*
58
+ * Initialise the cpreg_tuples[] array based on the cp_regs hash.
59
* Note that we require cpreg_tuples[] to be sorted by key ID.
60
*/
61
GList *keys;
62
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_el3_aa32ns(CPUARMState *env,
63
return CP_ACCESS_OK;
64
}
65
66
-/* Some secure-only AArch32 registers trap to EL3 if used from
67
+/*
68
+ * Some secure-only AArch32 registers trap to EL3 if used from
69
* Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
70
* Note that an access from Secure EL1 can only happen if EL3 is AArch64.
71
* We assume that the .access field is set to PL1_RW.
72
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
73
return CP_ACCESS_TRAP_UNCATEGORIZED;
74
}
75
76
-/* Check for traps to performance monitor registers, which are controlled
77
+/*
78
+ * Check for traps to performance monitor registers, which are controlled
79
* by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
80
*/
81
static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
82
@@ -XXX,XX +XXX,XX @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
83
ARMCPU *cpu = env_archcpu(env);
84
85
if (raw_read(env, ri) != value) {
86
- /* Unlike real hardware the qemu TLB uses virtual addresses,
87
+ /*
88
+ * Unlike real hardware the qemu TLB uses virtual addresses,
89
* not modified virtual addresses, so this causes a TLB flush.
90
*/
91
tlb_flush(CPU(cpu));
92
@@ -XXX,XX +XXX,XX @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
93
94
if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
95
&& !extended_addresses_enabled(env)) {
96
- /* For VMSA (when not using the LPAE long descriptor page table
97
+ /*
98
+ * For VMSA (when not using the LPAE long descriptor page table
99
* format) this register includes the ASID, so do a TLB flush.
100
* For PMSA it is purely a process ID and no action is needed.
101
*/
102
@@ -XXX,XX +XXX,XX @@ static void tlbiipas2is_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
103
}
104
105
static const ARMCPRegInfo cp_reginfo[] = {
106
- /* Define the secure and non-secure FCSE identifier CP registers
107
+ /*
108
+ * Define the secure and non-secure FCSE identifier CP registers
109
* separately because there is no secure bank in V8 (no _EL3). This allows
110
* the secure register to be properly reset and migrated. There is also no
111
* v8 EL1 version of the register so the non-secure instance stands alone.
112
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
113
.access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
114
.fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
115
.resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
116
- /* Define the secure and non-secure context identifier CP registers
117
+ /*
118
+ * Define the secure and non-secure context identifier CP registers
119
* separately because there is no secure bank in V8 (no _EL3). This allows
120
* the secure register to be properly reset and migrated. In the
121
* non-secure case, the 32-bit register will have reset and migration
122
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
123
};
124
125
static const ARMCPRegInfo not_v8_cp_reginfo[] = {
126
- /* NB: Some of these registers exist in v8 but with more precise
127
+ /*
128
+ * NB: Some of these registers exist in v8 but with more precise
129
* definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
130
*/
131
/* MMU Domain access control / MPU write buffer control */
132
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
133
.writefn = dacr_write, .raw_writefn = raw_write,
134
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
135
offsetoflow32(CPUARMState, cp15.dacr_ns) } },
136
- /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
137
+ /*
138
+ * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
139
* For v6 and v5, these mappings are overly broad.
140
*/
141
{ .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
142
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
143
};
144
145
static const ARMCPRegInfo not_v6_cp_reginfo[] = {
146
- /* Not all pre-v6 cores implemented this WFI, so this is slightly
147
+ /*
148
+ * Not all pre-v6 cores implemented this WFI, so this is slightly
149
* over-broad.
150
*/
151
{ .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
152
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = {
153
};
154
155
static const ARMCPRegInfo not_v7_cp_reginfo[] = {
156
- /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
157
+ /*
158
+ * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
159
* is UNPREDICTABLE; we choose to NOP as most implementations do).
160
*/
161
{ .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
162
.access = PL1_W, .type = ARM_CP_WFI },
163
- /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
164
+ /*
165
+ * L1 cache lockdown. Not architectural in v6 and earlier but in practice
166
* implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
167
* OMAPCP will override this space.
168
*/
169
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
170
{ .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
171
.access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
172
.resetvalue = 0 },
173
- /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
174
+ /*
175
+ * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
176
* implementing it as RAZ means the "debug architecture version" bits
177
* will read as a reserved value, which should cause Linux to not try
178
* to use the debug hardware.
179
*/
180
{ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
181
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
182
- /* MMU TLB control. Note that the wildcarding means we cover not just
183
+ /*
184
+ * MMU TLB control. Note that the wildcarding means we cover not just
185
* the unified TLB ops but also the dside/iside/inner-shareable variants.
186
*/
187
{ .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
188
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
189
190
/* In ARMv8 most bits of CPACR_EL1 are RES0. */
191
if (!arm_feature(env, ARM_FEATURE_V8)) {
192
- /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
193
+ /*
194
+ * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
195
* ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
196
* TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
197
*/
198
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
199
value |= R_CPACR_ASEDIS_MASK;
200
}
201
202
- /* VFPv3 and upwards with NEON implement 32 double precision
203
+ /*
204
+ * VFPv3 and upwards with NEON implement 32 double precision
205
* registers (D0-D31).
206
*/
207
if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) {
208
@@ -XXX,XX +XXX,XX @@ static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri)
209
210
static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
211
{
212
- /* Call cpacr_write() so that we reset with the correct RAO bits set
213
+ /*
214
+ * Call cpacr_write() so that we reset with the correct RAO bits set
215
* for our CPU features.
216
*/
217
cpacr_write(env, ri, 0);
218
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
219
{ .name = "MVA_prefetch",
220
.cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
221
.access = PL1_W, .type = ARM_CP_NOP },
222
- /* We need to break the TB after ISB to execute self-modifying code
223
+ /*
224
+ * We need to break the TB after ISB to execute self-modifying code
225
* correctly and also to take any pending interrupts immediately.
226
* So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
227
*/
228
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
229
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
230
offsetof(CPUARMState, cp15.ifar_ns) },
231
.resetvalue = 0, },
232
- /* Watchpoint Fault Address Register : should actually only be present
233
+ /*
234
+ * Watchpoint Fault Address Register : should actually only be present
235
* for 1136, 1176, 11MPCore.
236
*/
237
{ .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
238
@@ -XXX,XX +XXX,XX @@ static bool event_supported(uint16_t number)
239
static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
240
bool isread)
241
{
242
- /* Performance monitor registers user accessibility is controlled
243
+ /*
244
+ * Performance monitor registers user accessibility is controlled
245
* by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
246
* trapping to EL2 or EL3 for other accesses.
247
*/
248
@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
249
(MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
250
#define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
251
252
-/* Returns true if the counter (pass 31 for PMCCNTR) should count events using
253
+/*
254
+ * Returns true if the counter (pass 31 for PMCCNTR) should count events using
255
* the current EL, security state, and register configuration.
256
*/
257
static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
258
@@ -XXX,XX +XXX,XX @@ static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
259
static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
260
uint64_t value)
261
{
262
- /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
263
+ /*
264
+ * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
265
* PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
266
* meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
267
* accessed.
268
@@ -XXX,XX +XXX,XX @@ static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
269
env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK;
270
pmevcntr_op_finish(env, counter);
271
}
272
- /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
273
+ /*
274
+ * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
275
* PMSELR value is equal to or greater than the number of implemented
276
* counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
277
*/
278
@@ -XXX,XX +XXX,XX @@ static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri,
279
}
280
return ret;
281
} else {
282
- /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
283
- * are CONSTRAINED UNPREDICTABLE. */
284
+ /*
285
+ * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
286
+ * are CONSTRAINED UNPREDICTABLE.
287
+ */
288
return 0;
289
}
290
}
291
@@ -XXX,XX +XXX,XX @@ static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
292
static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
293
uint64_t value)
294
{
295
- /* Note that even though the AArch64 view of this register has bits
296
+ /*
297
+ * Note that even though the AArch64 view of this register has bits
298
* [10:0] all RES0 we can only mask the bottom 5, to comply with the
299
* architectural requirements for bits which are RES0 only in some
300
* contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
301
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
302
if (!arm_feature(env, ARM_FEATURE_EL2)) {
303
valid_mask &= ~SCR_HCE;
304
305
- /* On ARMv7, SMD (or SCD as it is called in v7) is only
306
+ /*
307
+ * On ARMv7, SMD (or SCD as it is called in v7) is only
308
* supported if EL2 exists. The bit is UNK/SBZP when
309
* EL2 is unavailable. In QEMU ARMv7, we force it to always zero
310
* when EL2 is unavailable.
311
@@ -XXX,XX +XXX,XX @@ static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
312
{
313
ARMCPU *cpu = env_archcpu(env);
314
315
- /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
316
+ /*
317
+ * Acquire the CSSELR index from the bank corresponding to the CCSIDR
318
* bank
319
*/
320
uint32_t index = A32_BANKED_REG_GET(env, csselr,
321
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
322
/* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
323
{ .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
324
.access = PL1_W, .type = ARM_CP_NOP },
325
- /* Performance monitors are implementation defined in v7,
326
+ /*
327
+ * Performance monitors are implementation defined in v7,
328
* but with an ARM recommended set of registers, which we
329
* follow.
330
*
331
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
332
.writefn = csselr_write, .resetvalue = 0,
333
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
334
offsetof(CPUARMState, cp15.csselr_ns) } },
335
- /* Auxiliary ID register: this actually has an IMPDEF value but for now
336
+ /*
337
+ * Auxiliary ID register: this actually has an IMPDEF value but for now
338
* just RAZ for all cores:
339
*/
340
{ .name = "AIDR", .state = ARM_CP_STATE_BOTH,
341
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
342
.access = PL1_R, .type = ARM_CP_CONST,
343
.accessfn = access_aa64_tid1,
344
.resetvalue = 0 },
345
- /* Auxiliary fault status registers: these also are IMPDEF, and we
346
+ /*
347
+ * Auxiliary fault status registers: these also are IMPDEF, and we
348
* choose to RAZ/WI for all cores.
349
*/
350
{ .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
351
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
352
.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
353
.access = PL1_RW, .accessfn = access_tvm_trvm,
354
.type = ARM_CP_CONST, .resetvalue = 0 },
355
- /* MAIR can just read-as-written because we don't implement caches
356
+ /*
357
+ * MAIR can just read-as-written because we don't implement caches
358
* and so don't need to care about memory attributes.
359
*/
360
{ .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
361
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
362
.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
363
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
364
.resetvalue = 0 },
365
- /* For non-long-descriptor page tables these are PRRR and NMRR;
366
+ /*
367
+ * For non-long-descriptor page tables these are PRRR and NMRR;
368
* regardless they still act as reads-as-written for QEMU.
369
*/
370
- /* MAIR0/1 are defined separately from their 64-bit counterpart which
371
+ /*
372
+ * MAIR0/1 are defined separately from their 64-bit counterpart which
373
* allows them to assign the correct fieldoffset based on the endianness
374
* handled in the field definitions.
375
*/
376
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
377
static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
378
bool isread)
379
{
380
- /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
381
+ /*
382
+ * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
383
* Writable only at the highest implemented exception level.
384
*/
385
int el = arm_current_el(env);
386
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
387
const ARMCPRegInfo *ri,
388
bool isread)
389
{
390
- /* The AArch64 register view of the secure physical timer is
391
+ /*
392
+ * The AArch64 register view of the secure physical timer is
393
* always accessible from EL3, and configurably accessible from
394
* Secure EL1.
395
*/
396
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
397
ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
398
399
if (gt->ctl & 1) {
400
- /* Timer enabled: calculate and set current ISTATUS, irq, and
401
+ /*
402
+ * Timer enabled: calculate and set current ISTATUS, irq, and
403
* reset timer to when ISTATUS next has to change
404
*/
405
uint64_t offset = timeridx == GTIMER_VIRT ?
406
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
407
/* Next transition is when we hit cval */
408
nexttick = gt->cval + offset;
409
}
410
- /* Note that the desired next expiry time might be beyond the
411
+ /*
412
+ * Note that the desired next expiry time might be beyond the
413
* signed-64-bit range of a QEMUTimer -- in this case we just
414
* set the timer for as far in the future as possible. When the
415
* timer expires we will reset the timer for any remaining period.
416
@@ -XXX,XX +XXX,XX @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
417
/* Enable toggled */
418
gt_recalc_timer(cpu, timeridx);
419
} else if ((oldval ^ value) & 2) {
420
- /* IMASK toggled: don't need to recalculate,
421
+ /*
422
+ * IMASK toggled: don't need to recalculate,
423
* just set the interrupt line based on ISTATUS
424
*/
425
int irqstate = (oldval & 4) && !(value & 2);
426
@@ -XXX,XX +XXX,XX @@ static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
427
}
428
429
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
430
- /* Note that CNTFRQ is purely reads-as-written for the benefit
431
+ /*
432
+ * Note that CNTFRQ is purely reads-as-written for the benefit
433
* of software; writing it doesn't actually change the timer frequency.
434
* Our reset value matches the fixed frequency we implement the timer at.
435
*/
436
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
437
.readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read,
438
.writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write,
439
},
440
- /* Secure timer -- this is actually restricted to only EL3
441
+ /*
442
+ * Secure timer -- this is actually restricted to only EL3
443
* and configurably Secure-EL1 via the accessfn.
444
*/
445
{ .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
446
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
447
448
#else
449
450
-/* In user-mode most of the generic timer registers are inaccessible
451
+/*
452
+ * In user-mode most of the generic timer registers are inaccessible
453
* however modern kernels (4.12+) allow access to cntvct_el0
454
*/
455
456
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
457
{
458
ARMCPU *cpu = env_archcpu(env);
459
460
- /* Currently we have no support for QEMUTimer in linux-user so we
461
+ /*
462
+ * Currently we have no support for QEMUTimer in linux-user so we
463
* can't call gt_get_countervalue(env), instead we directly
464
* call the lower level functions.
465
*/
466
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
467
bool isread)
468
{
469
if (ri->opc2 & 4) {
470
- /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
471
+ /*
472
+ * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
473
* Secure EL1 (which can only happen if EL3 is AArch64).
474
* They are simply UNDEF if executed from NS EL1.
475
* They function normally from EL2 or EL3.
476
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
477
}
478
}
479
} else {
480
- /* fsr is a DFSR/IFSR value for the short descriptor
481
+ /*
482
+ * fsr is a DFSR/IFSR value for the short descriptor
483
* translation table format (with WnR always clear).
484
* Convert it to a 32-bit PAR.
485
*/
486
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav8r_cp_reginfo[] = {
487
};
488
489
static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
490
- /* Reset for all these registers is handled in arm_cpu_reset(),
491
+ /*
492
+ * Reset for all these registers is handled in arm_cpu_reset(),
493
* because the PMSAv7 is also used by M-profile CPUs, which do
494
* not register cpregs but still need the state to be reset.
495
*/
496
@@ -XXX,XX +XXX,XX @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
497
}
498
499
if (arm_feature(env, ARM_FEATURE_LPAE)) {
500
- /* With LPAE the TTBCR could result in a change of ASID
501
+ /*
502
+ * With LPAE the TTBCR could result in a change of ASID
503
* via the TTBCR.A1 bit, so do a TLB flush.
504
*/
505
tlb_flush(CPU(cpu));
506
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
507
offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
508
};
509
510
-/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
511
+/*
512
+ * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
513
* qemu tlbs nor adjusting cached masks.
514
*/
515
static const ARMCPRegInfo ttbcr2_reginfo = {
516
@@ -XXX,XX +XXX,XX @@ static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
517
static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
518
uint64_t value)
519
{
520
- /* On OMAP there are registers indicating the max/min index of dcache lines
521
+ /*
522
+ * On OMAP there are registers indicating the max/min index of dcache lines
523
* containing a dirty line; cache flush operations have to reset these.
524
*/
525
env->cp15.c15_i_max = 0x000;
526
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
527
.crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
528
.type = ARM_CP_NO_RAW,
529
.readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
530
- /* TODO: Peripheral port remap register:
531
+ /*
532
+ * TODO: Peripheral port remap register:
533
* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
534
* base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
535
* when MMU is off.
536
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
537
.cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
538
.fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
539
.resetvalue = 0, },
540
- /* XScale specific cache-lockdown: since we have no cache we NOP these
541
+ /*
542
+ * XScale specific cache-lockdown: since we have no cache we NOP these
543
* and hope the guest does not really rely on cache behaviour.
544
*/
545
{ .name = "XSCALE_LOCK_ICACHE_LINE",
546
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
547
};
548
549
static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
550
- /* RAZ/WI the whole crn=15 space, when we don't have a more specific
551
+ /*
552
+ * RAZ/WI the whole crn=15 space, when we don't have a more specific
553
* implementation of this implementation-defined space.
554
* Ideally this should eventually disappear in favour of actually
555
* implementing the correct behaviour for all cores.
556
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
557
};
558
559
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
560
- /* The cache test-and-clean instructions always return (1 << 30)
561
+ /*
562
+ * The cache test-and-clean instructions always return (1 << 30)
563
* to indicate that there are no dirty cache lines.
564
*/
565
{ .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
566
@@ -XXX,XX +XXX,XX @@ static uint64_t mpidr_read_val(CPUARMState *env)
567
568
if (arm_feature(env, ARM_FEATURE_V7MP)) {
569
mpidr |= (1U << 31);
570
- /* Cores which are uniprocessor (non-coherent)
571
+ /*
572
+ * Cores which are uniprocessor (non-coherent)
573
* but still implement the MP extensions set
574
* bit 30. (For instance, Cortex-R5).
575
*/
576
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri,
577
return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU);
578
}
579
580
-/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
581
+/*
582
+ * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
583
* Page D4-1736 (DDI0487A.b)
584
*/
585
586
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
587
static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
588
uint64_t value)
589
{
590
- /* Invalidate by VA, EL2
591
+ /*
592
+ * Invalidate by VA, EL2
593
* Currently handles both VAE2 and VALE2, since we don't support
594
* flush-last-level-only.
595
*/
596
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
597
static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
598
uint64_t value)
599
{
600
- /* Invalidate by VA, EL3
601
+ /*
602
+ * Invalidate by VA, EL3
603
* Currently handles both VAE3 and VALE3, since we don't support
604
* flush-last-level-only.
605
*/
606
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
607
static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
608
uint64_t value)
609
{
610
- /* Invalidate by VA, EL1&0 (AArch64 version).
611
+ /*
612
+ * Invalidate by VA, EL1&0 (AArch64 version).
613
* Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
614
* since we don't support flush-for-specific-ASID-only or
615
* flush-last-level-only.
616
@@ -XXX,XX +XXX,XX @@ static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
617
bool isread)
618
{
619
if (!(env->pstate & PSTATE_SP)) {
620
- /* Access to SP_EL0 is undefined if it's being used as
621
+ /*
622
+ * Access to SP_EL0 is undefined if it's being used as
623
* the stack pointer.
624
*/
625
return CP_ACCESS_TRAP_UNCATEGORIZED;
626
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
627
}
628
629
if (raw_read(env, ri) == value) {
630
- /* Skip the TLB flush if nothing actually changed; Linux likes
631
+ /*
632
+ * Skip the TLB flush if nothing actually changed; Linux likes
633
* to do a lot of pointless SCTLR writes.
634
*/
635
return;
636
@@ -XXX,XX +XXX,XX @@ static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
637
}
638
639
static const ARMCPRegInfo v8_cp_reginfo[] = {
640
- /* Minimal set of EL0-visible registers. This will need to be expanded
641
+ /*
642
+ * Minimal set of EL0-visible registers. This will need to be expanded
643
* significantly for system emulation of AArch64 CPUs.
644
*/
645
{ .name = "NZCV", .state = ARM_CP_STATE_AA64,
646
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
647
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
648
.access = PL1_RW,
649
.fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
650
- /* We rely on the access checks not allowing the guest to write to the
651
+ /*
652
+ * We rely on the access checks not allowing the guest to write to the
653
* state field when SPSel indicates that it's being used as the stack
654
* pointer.
655
*/
656
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
657
if (arm_feature(env, ARM_FEATURE_EL3)) {
658
valid_mask &= ~HCR_HCD;
659
} else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
660
- /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
661
+ /*
662
+ * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
663
* However, if we're using the SMC PSCI conduit then QEMU is
664
* effectively acting like EL3 firmware and so the guest at
665
* EL2 should retain the ability to prevent EL1 from being
666
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
667
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
668
.writefn = tlbi_aa64_vae2is_write },
669
#ifndef CONFIG_USER_ONLY
670
- /* Unlike the other EL2-related AT operations, these must
671
+ /*
672
+ * Unlike the other EL2-related AT operations, these must
673
* UNDEF from EL3 if EL2 is not implemented, which is why we
674
* define them here rather than with the rest of the AT ops.
675
*/
676
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
677
.access = PL2_W, .accessfn = at_s1e2_access,
678
.type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
679
.writefn = ats_write64 },
680
- /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
681
+ /*
682
+ * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
683
* if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
684
* with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
685
* to behave as if SCR.NS was 1.
686
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
687
.writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
688
{ .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
689
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
690
- /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
691
+ /*
692
+ * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
693
* reset values as IMPDEF. We choose to reset to 3 to comply with
694
* both ARMv7 and ARMv8.
695
*/
696
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
697
static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
698
bool isread)
699
{
700
- /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
701
+ /*
702
+ * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
703
* At Secure EL1 it traps to EL3 or EL2.
704
*/
705
if (arm_current_el(env) == 3) {
706
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
707
}
708
}
709
710
-/* We don't know until after realize whether there's a GICv3
711
+/*
712
+ * We don't know until after realize whether there's a GICv3
713
* attached, and that is what registers the gicv3 sysregs.
714
* So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
715
* at runtime.
716
@@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
717
}
718
#endif
719
720
-/* Shared logic between LORID and the rest of the LOR* registers.
721
+/*
722
+ * Shared logic between LORID and the rest of the LOR* registers.
723
* Secure state exclusion has already been dealt with.
724
*/
725
static CPAccessResult access_lor_ns(CPUARMState *env,
726
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
727
728
define_arm_cp_regs(cpu, cp_reginfo);
729
if (!arm_feature(env, ARM_FEATURE_V8)) {
730
- /* Must go early as it is full of wildcards that may be
731
+ /*
732
+ * Must go early as it is full of wildcards that may be
733
* overridden by later definitions.
734
*/
735
define_arm_cp_regs(cpu, not_v8_cp_reginfo);
736
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
737
.access = PL1_R, .type = ARM_CP_CONST,
738
.accessfn = access_aa32_tid3,
739
.resetvalue = cpu->isar.id_pfr0 },
740
- /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
741
+ /*
742
+ * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
743
* the value of the GIC field until after we define these regs.
744
*/
745
{ .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
746
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
747
748
define_arm_cp_regs(cpu, el3_regs);
749
}
750
- /* The behaviour of NSACR is sufficiently various that we don't
751
+ /*
752
+ * The behaviour of NSACR is sufficiently various that we don't
753
* try to describe it in a single reginfo:
754
* if EL3 is 64 bit, then trap to EL3 from S EL1,
755
* reads as constant 0xc00 from NS EL1 and NS EL2
756
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
757
if (cpu_isar_feature(aa32_jazelle, cpu)) {
758
define_arm_cp_regs(cpu, jazelle_regs);
759
}
760
- /* Slightly awkwardly, the OMAP and StrongARM cores need all of
761
+ /*
762
+ * Slightly awkwardly, the OMAP and StrongARM cores need all of
763
* cp15 crn=0 to be writes-ignored, whereas for other cores they should
764
* be read-only (ie write causes UNDEF exception).
765
*/
766
{
767
ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
768
- /* Pre-v8 MIDR space.
769
+ /*
770
+ * Pre-v8 MIDR space.
771
* Note that the MIDR isn't a simple constant register because
772
* of the TI925 behaviour where writes to another register can
773
* cause the MIDR value to change.
774
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
775
if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
776
arm_feature(env, ARM_FEATURE_STRONGARM)) {
777
size_t i;
778
- /* Register the blanket "writes ignored" value first to cover the
779
+ /*
780
+ * Register the blanket "writes ignored" value first to cover the
781
* whole space. Then update the specific ID registers to allow write
782
* access, so that they ignore writes rather than causing them to
783
* UNDEF.
784
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
785
.raw_writefn = raw_write,
786
};
787
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
788
- /* Normally we would always end the TB on an SCTLR write, but Linux
789
+ /*
790
+ * Normally we would always end the TB on an SCTLR write, but Linux
791
* arch/arm/mach-pxa/sleep.S expects two instructions following
792
* an MMU enable to execute from cache. Imitate this behaviour.
793
*/
794
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
795
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
796
const ARMCPRegInfo *r, void *opaque)
797
{
798
- /* Define implementations of coprocessor registers.
799
+ /*
800
+ * Define implementations of coprocessor registers.
801
* We store these in a hashtable because typically
802
* there are less than 150 registers in a space which
803
* is 16*16*16*8*8 = 262144 in size.
804
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
805
default:
806
g_assert_not_reached();
807
}
808
- /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
809
+ /*
810
+ * The AArch64 pseudocode CheckSystemAccess() specifies that op1
811
* encodes a minimum access level for the register. We roll this
812
* runtime check into our general permission check code, so check
813
* here that the reginfo's specified permissions are strict enough
814
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
815
assert((r->access & ~mask) == 0);
816
}
817
818
- /* Check that the register definition has enough info to handle
819
+ /*
820
+ * Check that the register definition has enough info to handle
821
* reads and writes if they are permitted.
822
*/
823
if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) {
824
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
825
continue;
826
}
827
if (state == ARM_CP_STATE_AA32) {
828
- /* Under AArch32 CP registers can be common
829
+ /*
830
+ * Under AArch32 CP registers can be common
831
* (same for secure and non-secure world) or banked.
832
*/
833
char *name;
834
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
835
g_assert_not_reached();
836
}
837
} else {
838
- /* AArch64 registers get mapped to non-secure instance
839
- * of AArch32 */
840
+ /*
841
+ * AArch64 registers get mapped to non-secure instance
842
+ * of AArch32
843
+ */
844
add_cpreg_to_hashtable(cpu, r, opaque, state,
845
ARM_CP_SECSTATE_NS,
846
crm, opc1, opc2, r->name);
847
@@ -XXX,XX +XXX,XX @@ void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
848
849
static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
850
{
851
- /* Return true if it is not valid for us to switch to
852
+ /*
853
+ * Return true if it is not valid for us to switch to
854
* this CPU mode (ie all the UNPREDICTABLE cases in
855
* the ARM ARM CPSRWriteByInstr pseudocode).
856
*/
857
@@ -XXX,XX +XXX,XX @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
858
case ARM_CPU_MODE_UND:
859
case ARM_CPU_MODE_IRQ:
860
case ARM_CPU_MODE_FIQ:
861
- /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
862
+ /*
863
+ * Note that we don't implement the IMPDEF NSACR.RFR which in v7
864
* allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
865
*/
866
- /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
867
+ /*
868
+ * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
869
* and CPS are treated as illegal mode changes.
870
*/
871
if (write_type == CPSRWriteByInstr &&
872
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
873
env->GE = (val >> 16) & 0xf;
874
}
875
876
- /* In a V7 implementation that includes the security extensions but does
877
+ /*
878
+ * In a V7 implementation that includes the security extensions but does
879
* not include Virtualization Extensions the SCR.FW and SCR.AW bits control
880
* whether non-secure software is allowed to change the CPSR_F and CPSR_A
881
* bits respectively.
882
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
883
changed_daif = (env->daif ^ val) & mask;
884
885
if (changed_daif & CPSR_A) {
886
- /* Check to see if we are allowed to change the masking of async
887
+ /*
888
+ * Check to see if we are allowed to change the masking of async
889
* abort exceptions from a non-secure state.
890
*/
891
if (!(env->cp15.scr_el3 & SCR_AW)) {
892
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
893
}
894
895
if (changed_daif & CPSR_F) {
896
- /* Check to see if we are allowed to change the masking of FIQ
897
+ /*
898
+ * Check to see if we are allowed to change the masking of FIQ
899
* exceptions from a non-secure state.
900
*/
901
if (!(env->cp15.scr_el3 & SCR_FW)) {
902
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
903
mask &= ~CPSR_F;
904
}
905
906
- /* Check whether non-maskable FIQ (NMFI) support is enabled.
907
+ /*
908
+ * Check whether non-maskable FIQ (NMFI) support is enabled.
909
* If this bit is set software is not allowed to mask
910
* FIQs, but is allowed to set CPSR_F to 0.
911
*/
912
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
913
if (write_type != CPSRWriteRaw &&
914
((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
915
if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
916
- /* Note that we can only get here in USR mode if this is a
917
+ /*
918
+ * Note that we can only get here in USR mode if this is a
919
* gdb stub write; for this case we follow the architectural
920
* behaviour for guest writes in USR mode of ignoring an attempt
921
* to switch mode. (Those are caught by translate.c for writes
922
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
923
*/
924
mask &= ~CPSR_M;
925
} else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
926
- /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
927
+ /*
928
+ * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
929
* v7, and has defined behaviour in v8:
930
* + leave CPSR.M untouched
931
* + allow changes to the other CPSR fields
932
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
933
env->regs[14] = env->banked_r14[r14_bank_number(mode)];
934
}
935
936
-/* Physical Interrupt Target EL Lookup Table
937
+/*
938
+ * Physical Interrupt Target EL Lookup Table
939
*
940
* [ From ARM ARM section G1.13.4 (Table G1-15) ]
941
*
942
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
943
if (arm_feature(env, ARM_FEATURE_EL3)) {
944
rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
945
} else {
946
- /* Either EL2 is the highest EL (and so the EL2 register width
947
+ /*
948
+ * Either EL2 is the highest EL (and so the EL2 register width
949
* is given by is64); or there is no EL2 or EL3, in which case
950
* the value of 'rw' does not affect the table lookup anyway.
951
*/
952
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
953
env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
954
}
955
956
- /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
957
+ /*
958
+ * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
959
* mode, then we can copy to r8-r14. Otherwise, we copy to the
960
* FIQ bank for r8-r14.
961
*/
962
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
963
/* High vectors. When enabled, base address cannot be remapped. */
964
addr += 0xffff0000;
965
} else {
966
- /* ARM v7 architectures provide a vector base address register to remap
967
+ /*
968
+ * ARM v7 architectures provide a vector base address register to remap
969
* the interrupt vector table.
970
* This register is only followed in non-monitor mode, and is banked.
971
* Note: only bits 31:5 are valid.
972
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
973
aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
974
975
if (cur_el < new_el) {
976
- /* Entry vector offset depends on whether the implemented EL
977
+ /*
978
+ * Entry vector offset depends on whether the implemented EL
979
* immediately lower than the target level is using AArch32 or AArch64
980
*/
981
bool is_aa64;
982
@@ -XXX,XX +XXX,XX @@ static void handle_semihosting(CPUState *cs)
983
}
984
#endif
985
986
-/* Handle a CPU exception for A and R profile CPUs.
987
+/*
988
+ * Handle a CPU exception for A and R profile CPUs.
989
* Do any appropriate logging, handle PSCI calls, and then hand off
990
* to the AArch64-entry or AArch32-entry function depending on the
991
* target exception level's register width.
992
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
993
}
994
#endif
995
996
- /* Hooks may change global state so BQL should be held, also the
997
+ /*
998
+ * Hooks may change global state so BQL should be held, also the
999
* BQL needs to be held for any modification of
1000
* cs->interrupt_request.
1001
*/
1002
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
1003
};
1004
}
1005
1006
-/* Note that signed overflow is undefined in C. The following routines are
1007
- careful to use unsigned types where modulo arithmetic is required.
1008
- Failure to do so _will_ break on newer gcc. */
1009
+/*
1010
+ * Note that signed overflow is undefined in C. The following routines are
1011
+ * careful to use unsigned types where modulo arithmetic is required.
1012
+ * Failure to do so _will_ break on newer gcc.
1013
+ */
1014
1015
/* Signed saturating arithmetic. */
1016
1017
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
1018
return (a & mask) | (b & ~mask);
1019
}
1020
1021
-/* CRC helpers.
1022
+/*
1023
+ * CRC helpers.
1024
* The upper bytes of val (above the number specified by 'bytes') must have
1025
* been zeroed out by the caller.
1026
*/
1027
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
1028
return crc32c(acc, buf, bytes) ^ 0xffffffff;
1029
}
1030
1031
-/* Return the exception level to which FP-disabled exceptions should
1032
+/*
1033
+ * Return the exception level to which FP-disabled exceptions should
1034
* be taken, or 0 if FP is enabled.
1035
*/
1036
int fp_exception_el(CPUARMState *env, int cur_el)
1037
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
1038
#ifndef CONFIG_USER_ONLY
1039
uint64_t hcr_el2;
1040
1041
- /* CPACR and the CPTR registers don't exist before v6, so FP is
1042
+ /*
1043
+ * CPACR and the CPTR registers don't exist before v6, so FP is
1044
* always accessible
1045
*/
1046
if (!arm_feature(env, ARM_FEATURE_V6)) {
1047
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
1048
1049
hcr_el2 = arm_hcr_el2_eff(env);
1050
1051
- /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
1052
+ /*
1053
+ * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
1054
* 0, 2 : trap EL0 and EL1/PL1 accesses
1055
* 1 : trap only EL0 accesses
1056
* 3 : trap no accesses
1057
--
1058
2.25.1
diff view generated by jsdifflib
New patch
[PULL 19/34] target/arm: Fix checkpatch space errors in helper.c
1
From: Fabiano Rosas <farosas@suse.de>
1
2
3
Fix the following:
4
5
ERROR: spaces required around that '|' (ctx:VxV)
6
ERROR: space required before the open parenthesis '('
7
ERROR: spaces required around that '+' (ctx:VxB)
8
ERROR: space prohibited between function name and open parenthesis '('
9
10
(the last two still have some occurrences in macros which I left
11
behind because it might impact readability)
12
13
Signed-off-by: Fabiano Rosas <farosas@suse.de>
14
Reviewed-by: Claudio Fontana <cfontana@suse.de>
15
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
16
Message-id: 20221213190537.511-3-farosas@suse.de
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
target/arm/helper.c | 42 +++++++++++++++++++++---------------------
20
1 file changed, 21 insertions(+), 21 deletions(-)
21
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.c
25
+++ b/target/arm/helper.c
26
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
27
uint32_t regidx = (uintptr_t)key;
28
const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
29
30
- if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
31
+ if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
32
cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
33
/* The value array need not be initialized at this point */
34
cpu->cpreg_array_len++;
35
@@ -XXX,XX +XXX,XX @@ static void count_cpreg(gpointer key, gpointer opaque)
36
37
ri = g_hash_table_lookup(cpu->cp_regs, key);
38
39
- if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
40
+ if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
41
cpu->cpreg_array_len++;
42
}
43
}
44
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
45
.resetfn = arm_cp_reset_ignore },
46
{ .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
47
.opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
48
- .access = PL0_R|PL1_W,
49
+ .access = PL0_R | PL1_W,
50
.fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
51
.resetvalue = 0},
52
{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
53
- .access = PL0_R|PL1_W,
54
+ .access = PL0_R | PL1_W,
55
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
56
offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
57
.resetfn = arm_cp_reset_ignore },
58
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
59
.resetvalue = 0 },
60
/* The cache ops themselves: these all NOP for QEMU */
61
{ .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
62
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
63
+ .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
64
{ .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
65
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
66
+ .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
67
{ .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
68
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
69
+ .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
70
{ .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
71
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
72
+ .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
73
{ .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
74
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
75
+ .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
76
{ .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
77
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
78
+ .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
79
};
80
81
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
82
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
83
ARMCPRegInfo cbar = {
84
.name = "CBAR",
85
.cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
86
- .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
87
+ .access = PL1_R | PL3_W, .resetvalue = cpu->reset_cbar,
88
.fieldoffset = offsetof(CPUARMState,
89
cp15.c15_config_base_address)
90
};
91
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
92
return;
93
94
if (old_mode == ARM_CPU_MODE_FIQ) {
95
- memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
96
- memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
97
+ memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
98
+ memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
99
} else if (mode == ARM_CPU_MODE_FIQ) {
100
- memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
101
- memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
102
+ memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
103
+ memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
104
}
105
106
i = bank_number(old_mode);
107
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
108
RESULT(sum, n, 16); \
109
if (sum >= 0) \
110
ge |= 3 << (n * 2); \
111
- } while(0)
112
+ } while (0)
113
114
#define SARITH8(a, b, n, op) do { \
115
int32_t sum; \
116
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
117
RESULT(sum, n, 8); \
118
if (sum >= 0) \
119
ge |= 1 << n; \
120
- } while(0)
121
+ } while (0)
122
123
124
#define ADD16(a, b, n) SARITH16(a, b, n, +)
125
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
126
RESULT(sum, n, 16); \
127
if ((sum >> 16) == 1) \
128
ge |= 3 << (n * 2); \
129
- } while(0)
130
+ } while (0)
131
132
#define ADD8(a, b, n) do { \
133
uint32_t sum; \
134
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
135
RESULT(sum, n, 8); \
136
if ((sum >> 8) == 1) \
137
ge |= 1 << n; \
138
- } while(0)
139
+ } while (0)
140
141
#define SUB16(a, b, n) do { \
142
uint32_t sum; \
143
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
144
RESULT(sum, n, 16); \
145
if ((sum >> 16) == 0) \
146
ge |= 3 << (n * 2); \
147
- } while(0)
148
+ } while (0)
149
150
#define SUB8(a, b, n) do { \
151
uint32_t sum; \
152
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
153
RESULT(sum, n, 8); \
154
if ((sum >> 8) == 0) \
155
ge |= 1 << n; \
156
- } while(0)
157
+ } while (0)
158
159
#define PFX u
160
#define ARITH_GE
161
--
162
2.25.1
diff view generated by jsdifflib
[PULL 16/22] scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named()
[PULL 20/34] target/arm: Fix checkpatch brace errors in helper.c
1
The function scsi_bus_new() creates a new SCSI bus; callers can
1
From: Fabiano Rosas <farosas@suse.de>
2
either pass in a name argument to specify the name of the new bus, or
3
they can pass in NULL to allow the bus to be given an automatically
4
generated unique name. Almost all callers want to use the
5
autogenerated name; the only exception is the virtio-scsi device.
6
2
7
Taking a name argument that should almost always be NULL is an
3
Fix this:
8
easy-to-misuse API design -- it encourages callers to think perhaps
4
ERROR: braces {} are necessary for all arms of this statement
9
they should pass in some standard name like "scsi" or "scsi-bus". We
10
don't do this anywhere for SCSI, but we do (incorrectly) do it for
11
other bus types such as i2c.
12
5
13
The function name also implies that it will return a newly allocated
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
14
object, when it in fact does in-place allocation. We more commonly
7
Reviewed-by: Claudio Fontana <cfontana@suse.de>
15
name such functions foo_init(), with foo_new() being the
8
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
16
allocate-and-return variant.
9
Message-id: 20221213190537.511-4-farosas@suse.de
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/helper.c | 67 ++++++++++++++++++++++++++++-----------------
13
1 file changed, 42 insertions(+), 25 deletions(-)
17
14
18
Replace all the scsi_bus_new() callsites with either:
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
* scsi_bus_init() for the usual case where the caller wants
20
an autogenerated bus name
21
* scsi_bus_init_named() for the rare case where the caller
22
needs to specify the bus name
23
24
and document that for the _named() version it's then the caller's
25
responsibility to think about uniqueness of bus names.
26
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
29
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
30
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
31
Message-id: 20210923121153.23754-2-peter.maydell@linaro.org
32
---
33
include/hw/scsi/scsi.h | 30 ++++++++++++++++++++++++++++--
34
hw/scsi/esp-pci.c | 2 +-
35
hw/scsi/esp.c | 2 +-
36
hw/scsi/lsi53c895a.c | 2 +-
37
hw/scsi/megasas.c | 3 +--
38
hw/scsi/mptsas.c | 2 +-
39
hw/scsi/scsi-bus.c | 4 ++--
40
hw/scsi/spapr_vscsi.c | 3 +--
41
hw/scsi/virtio-scsi.c | 4 ++--
42
hw/scsi/vmw_pvscsi.c | 3 +--
43
hw/usb/dev-storage-bot.c | 3 +--
44
hw/usb/dev-storage-classic.c | 4 ++--
45
hw/usb/dev-uas.c | 3 +--
46
13 files changed, 43 insertions(+), 22 deletions(-)
47
48
diff --git a/include/hw/scsi/scsi.h b/include/hw/scsi/scsi.h
49
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/scsi/scsi.h
17
--- a/target/arm/helper.c
51
+++ b/include/hw/scsi/scsi.h
18
+++ b/target/arm/helper.c
52
@@ -XXX,XX +XXX,XX @@ struct SCSIBus {
19
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
53
const SCSIBusInfo *info;
20
env->CF = (val >> 29) & 1;
54
};
21
env->VF = (val << 3) & 0x80000000;
55
22
}
56
-void scsi_bus_new(SCSIBus *bus, size_t bus_size, DeviceState *host,
23
- if (mask & CPSR_Q)
57
- const SCSIBusInfo *info, const char *bus_name);
24
+ if (mask & CPSR_Q) {
58
+/**
25
env->QF = ((val & CPSR_Q) != 0);
59
+ * scsi_bus_init_named: Initialize a SCSI bus with the specified name
26
- if (mask & CPSR_T)
60
+ * @bus: SCSIBus object to initialize
27
+ }
61
+ * @bus_size: size of @bus object
28
+ if (mask & CPSR_T) {
62
+ * @host: Device which owns the bus (generally the SCSI controller)
29
env->thumb = ((val & CPSR_T) != 0);
63
+ * @info: structure defining callbacks etc for the controller
30
+ }
64
+ * @bus_name: Name to use for this bus
31
if (mask & CPSR_IT_0_1) {
65
+ *
32
env->condexec_bits &= ~3;
66
+ * This in-place initializes @bus as a new SCSI bus with a name
33
env->condexec_bits |= (val >> 25) & 3;
67
+ * provided by the caller. It is the caller's responsibility to make
34
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
68
+ * sure that name does not clash with the name of any other bus in the
35
int i;
69
+ * system. Unless you need the new bus to have a specific name, you
36
70
+ * should use scsi_bus_new() instead.
37
old_mode = env->uncached_cpsr & CPSR_M;
71
+ */
38
- if (mode == old_mode)
72
+void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host,
39
+ if (mode == old_mode) {
73
+ const SCSIBusInfo *info, const char *bus_name);
40
return;
74
+
41
+ }
75
+/**
42
76
+ * scsi_bus_init: Initialize a SCSI bus
43
if (old_mode == ARM_CPU_MODE_FIQ) {
77
+ *
44
memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
78
+ * This in-place-initializes @bus as a new SCSI bus and gives it
45
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
79
+ * an automatically generated unique name.
46
new_mode = ARM_CPU_MODE_UND;
80
+ */
47
addr = 0x04;
81
+static inline void scsi_bus_init(SCSIBus *bus, size_t bus_size,
48
mask = CPSR_I;
82
+ DeviceState *host, const SCSIBusInfo *info)
49
- if (env->thumb)
83
+{
50
+ if (env->thumb) {
84
+ scsi_bus_init_named(bus, bus_size, host, info, NULL);
51
offset = 2;
85
+}
52
- else
86
53
+ } else {
87
static inline SCSIBus *scsi_bus_from_device(SCSIDevice *d)
54
offset = 4;
55
+ }
56
break;
57
case EXCP_SWI:
58
new_mode = ARM_CPU_MODE_SVC;
59
@@ -XXX,XX +XXX,XX @@ static inline uint16_t add16_sat(uint16_t a, uint16_t b)
60
61
res = a + b;
62
if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
63
- if (a & 0x8000)
64
+ if (a & 0x8000) {
65
res = 0x8000;
66
- else
67
+ } else {
68
res = 0x7fff;
69
+ }
70
}
71
return res;
72
}
73
@@ -XXX,XX +XXX,XX @@ static inline uint8_t add8_sat(uint8_t a, uint8_t b)
74
75
res = a + b;
76
if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
77
- if (a & 0x80)
78
+ if (a & 0x80) {
79
res = 0x80;
80
- else
81
+ } else {
82
res = 0x7f;
83
+ }
84
}
85
return res;
86
}
87
@@ -XXX,XX +XXX,XX @@ static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
88
89
res = a - b;
90
if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
91
- if (a & 0x8000)
92
+ if (a & 0x8000) {
93
res = 0x8000;
94
- else
95
+ } else {
96
res = 0x7fff;
97
+ }
98
}
99
return res;
100
}
101
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
102
103
res = a - b;
104
if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
105
- if (a & 0x80)
106
+ if (a & 0x80) {
107
res = 0x80;
108
- else
109
+ } else {
110
res = 0x7f;
111
+ }
112
}
113
return res;
114
}
115
@@ -XXX,XX +XXX,XX @@ static inline uint16_t add16_usat(uint16_t a, uint16_t b)
88
{
116
{
89
diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c
117
uint16_t res;
90
index XXXXXXX..XXXXXXX 100644
118
res = a + b;
91
--- a/hw/scsi/esp-pci.c
119
- if (res < a)
92
+++ b/hw/scsi/esp-pci.c
120
+ if (res < a) {
93
@@ -XXX,XX +XXX,XX @@ static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp)
121
res = 0xffff;
94
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
122
+ }
95
s->irq = pci_allocate_irq(dev);
123
return res;
96
97
- scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL);
98
+ scsi_bus_init(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info);
99
}
124
}
100
125
101
static void esp_pci_scsi_exit(PCIDevice *d)
126
static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
102
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
127
{
103
index XXXXXXX..XXXXXXX 100644
128
- if (a > b)
104
--- a/hw/scsi/esp.c
129
+ if (a > b) {
105
+++ b/hw/scsi/esp.c
130
return a - b;
106
@@ -XXX,XX +XXX,XX @@ static void sysbus_esp_realize(DeviceState *dev, Error **errp)
131
- else
107
132
+ } else {
108
qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
133
return 0;
109
134
+ }
110
- scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
111
+ scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info);
112
}
135
}
113
136
114
static void sysbus_esp_hard_reset(DeviceState *dev)
137
static inline uint8_t add8_usat(uint8_t a, uint8_t b)
115
diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
138
{
116
index XXXXXXX..XXXXXXX 100644
139
uint8_t res;
117
--- a/hw/scsi/lsi53c895a.c
140
res = a + b;
118
+++ b/hw/scsi/lsi53c895a.c
141
- if (res < a)
119
@@ -XXX,XX +XXX,XX @@ static void lsi_scsi_realize(PCIDevice *dev, Error **errp)
142
+ if (res < a) {
120
pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_io);
143
res = 0xff;
121
QTAILQ_INIT(&s->queue);
144
+ }
122
145
return res;
123
- scsi_bus_new(&s->bus, sizeof(s->bus), d, &lsi_scsi_info, NULL);
124
+ scsi_bus_init(&s->bus, sizeof(s->bus), d, &lsi_scsi_info);
125
}
146
}
126
147
127
static void lsi_scsi_exit(PCIDevice *dev)
148
static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
128
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
149
{
129
index XXXXXXX..XXXXXXX 100644
150
- if (a > b)
130
--- a/hw/scsi/megasas.c
151
+ if (a > b) {
131
+++ b/hw/scsi/megasas.c
152
return a - b;
132
@@ -XXX,XX +XXX,XX @@ static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
153
- else
133
s->frames[i].state = s;
154
+ } else {
134
}
155
return 0;
135
156
+ }
136
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
137
- &megasas_scsi_info, NULL);
138
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &megasas_scsi_info);
139
}
157
}
140
158
141
static Property megasas_properties_gen1[] = {
159
#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
142
diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c
160
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
143
index XXXXXXX..XXXXXXX 100644
161
144
--- a/hw/scsi/mptsas.c
162
static inline uint8_t do_usad(uint8_t a, uint8_t b)
145
+++ b/hw/scsi/mptsas.c
163
{
146
@@ -XXX,XX +XXX,XX @@ static void mptsas_scsi_realize(PCIDevice *dev, Error **errp)
164
- if (a > b)
147
165
+ if (a > b) {
148
s->request_bh = qemu_bh_new(mptsas_fetch_requests, s);
166
return a - b;
149
167
- else
150
- scsi_bus_new(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info, NULL);
168
+ } else {
151
+ scsi_bus_init(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info);
169
return b - a;
170
+ }
152
}
171
}
153
172
154
static void mptsas_scsi_uninit(PCIDevice *dev)
173
/* Unsigned sum of absolute byte differences. */
155
diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c
174
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
156
index XXXXXXX..XXXXXXX 100644
175
uint32_t mask;
157
--- a/hw/scsi/scsi-bus.c
176
158
+++ b/hw/scsi/scsi-bus.c
177
mask = 0;
159
@@ -XXX,XX +XXX,XX @@ void scsi_device_unit_attention_reported(SCSIDevice *s)
178
- if (flags & 1)
179
+ if (flags & 1) {
180
mask |= 0xff;
181
- if (flags & 2)
182
+ }
183
+ if (flags & 2) {
184
mask |= 0xff00;
185
- if (flags & 4)
186
+ }
187
+ if (flags & 4) {
188
mask |= 0xff0000;
189
- if (flags & 8)
190
+ }
191
+ if (flags & 8) {
192
mask |= 0xff000000;
193
+ }
194
return (a & mask) | (b & ~mask);
160
}
195
}
161
196
162
/* Create a scsi bus, and attach devices to it. */
163
-void scsi_bus_new(SCSIBus *bus, size_t bus_size, DeviceState *host,
164
- const SCSIBusInfo *info, const char *bus_name)
165
+void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host,
166
+ const SCSIBusInfo *info, const char *bus_name)
167
{
168
qbus_create_inplace(bus, bus_size, TYPE_SCSI_BUS, host, bus_name);
169
bus->busnr = next_scsi_bus++;
170
diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c
171
index XXXXXXX..XXXXXXX 100644
172
--- a/hw/scsi/spapr_vscsi.c
173
+++ b/hw/scsi/spapr_vscsi.c
174
@@ -XXX,XX +XXX,XX @@ static void spapr_vscsi_realize(SpaprVioDevice *dev, Error **errp)
175
176
dev->crq.SendFunc = vscsi_do_crq;
177
178
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
179
- &vscsi_scsi_info, NULL);
180
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &vscsi_scsi_info);
181
182
/* ibmvscsi SCSI bus does not allow hotplug. */
183
qbus_set_hotplug_handler(BUS(&s->bus), NULL);
184
diff --git a/hw/scsi/virtio-scsi.c b/hw/scsi/virtio-scsi.c
185
index XXXXXXX..XXXXXXX 100644
186
--- a/hw/scsi/virtio-scsi.c
187
+++ b/hw/scsi/virtio-scsi.c
188
@@ -XXX,XX +XXX,XX @@ static void virtio_scsi_device_realize(DeviceState *dev, Error **errp)
189
return;
190
}
191
192
- scsi_bus_new(&s->bus, sizeof(s->bus), dev,
193
- &virtio_scsi_scsi_info, vdev->bus_name);
194
+ scsi_bus_init_named(&s->bus, sizeof(s->bus), dev,
195
+ &virtio_scsi_scsi_info, vdev->bus_name);
196
/* override default SCSI bus hotplug-handler, with virtio-scsi's one */
197
qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(dev));
198
199
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/hw/scsi/vmw_pvscsi.c
202
+++ b/hw/scsi/vmw_pvscsi.c
203
@@ -XXX,XX +XXX,XX @@ pvscsi_realizefn(PCIDevice *pci_dev, Error **errp)
204
205
s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s);
206
207
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
208
- &pvscsi_scsi_info, NULL);
209
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev), &pvscsi_scsi_info);
210
/* override default SCSI bus hotplug-handler, with pvscsi's one */
211
qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(s));
212
pvscsi_reset_state(s);
213
diff --git a/hw/usb/dev-storage-bot.c b/hw/usb/dev-storage-bot.c
214
index XXXXXXX..XXXXXXX 100644
215
--- a/hw/usb/dev-storage-bot.c
216
+++ b/hw/usb/dev-storage-bot.c
217
@@ -XXX,XX +XXX,XX @@ static void usb_msd_bot_realize(USBDevice *dev, Error **errp)
218
s->dev.auto_attach = 0;
219
}
220
221
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
222
- &usb_msd_scsi_info_bot, NULL);
223
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &usb_msd_scsi_info_bot);
224
usb_msd_handle_reset(dev);
225
}
226
227
diff --git a/hw/usb/dev-storage-classic.c b/hw/usb/dev-storage-classic.c
228
index XXXXXXX..XXXXXXX 100644
229
--- a/hw/usb/dev-storage-classic.c
230
+++ b/hw/usb/dev-storage-classic.c
231
@@ -XXX,XX +XXX,XX @@ static void usb_msd_storage_realize(USBDevice *dev, Error **errp)
232
usb_desc_create_serial(dev);
233
usb_desc_init(dev);
234
dev->flags |= (1 << USB_DEV_FLAG_IS_SCSI_STORAGE);
235
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
236
- &usb_msd_scsi_info_storage, NULL);
237
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev),
238
+ &usb_msd_scsi_info_storage);
239
scsi_dev = scsi_bus_legacy_add_drive(&s->bus, blk, 0, !!s->removable,
240
s->conf.bootindex, s->conf.share_rw,
241
s->conf.rerror, s->conf.werror,
242
diff --git a/hw/usb/dev-uas.c b/hw/usb/dev-uas.c
243
index XXXXXXX..XXXXXXX 100644
244
--- a/hw/usb/dev-uas.c
245
+++ b/hw/usb/dev-uas.c
246
@@ -XXX,XX +XXX,XX @@ static void usb_uas_realize(USBDevice *dev, Error **errp)
247
uas->status_bh = qemu_bh_new(usb_uas_send_status_bh, uas);
248
249
dev->flags |= (1 << USB_DEV_FLAG_IS_SCSI_STORAGE);
250
- scsi_bus_new(&uas->bus, sizeof(uas->bus), DEVICE(dev),
251
- &usb_uas_scsi_info, NULL);
252
+ scsi_bus_init(&uas->bus, sizeof(uas->bus), DEVICE(dev), &usb_uas_scsi_info);
253
}
254
255
static const VMStateDescription vmstate_usb_uas = {
256
--
197
--
257
2.20.1
198
2.25.1
258
259
diff view generated by jsdifflib
New patch
[PULL 21/34] target/arm: Remove unused includes from m_helper.c
1
From: Fabiano Rosas <farosas@suse.de>
1
2
3
Signed-off-by: Fabiano Rosas <farosas@suse.de>
4
Reviewed-by: Claudio Fontana <cfontana@suse.de>
5
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
6
Message-id: 20221213190537.511-5-farosas@suse.de
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/m_helper.c | 16 ----------------
10
1 file changed, 16 deletions(-)
11
12
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/m_helper.c
15
+++ b/target/arm/m_helper.c
16
@@ -XXX,XX +XXX,XX @@
17
*/
18
19
#include "qemu/osdep.h"
20
-#include "qemu/units.h"
21
-#include "target/arm/idau.h"
22
-#include "trace.h"
23
#include "cpu.h"
24
#include "internals.h"
25
-#include "exec/gdbstub.h"
26
#include "exec/helper-proto.h"
27
-#include "qemu/host-utils.h"
28
#include "qemu/main-loop.h"
29
#include "qemu/bitops.h"
30
-#include "qemu/crc32c.h"
31
-#include "qemu/qemu-print.h"
32
#include "qemu/log.h"
33
#include "exec/exec-all.h"
34
-#include <zlib.h> /* For crc32 */
35
-#include "semihosting/semihost.h"
36
-#include "sysemu/cpus.h"
37
-#include "sysemu/kvm.h"
38
-#include "qemu/range.h"
39
-#include "qapi/qapi-commands-machine-target.h"
40
-#include "qapi/error.h"
41
-#include "qemu/guest-random.h"
42
#ifdef CONFIG_TCG
43
-#include "arm_ldst.h"
44
#include "exec/cpu_ldst.h"
45
#include "semihosting/common-semi.h"
46
#endif
47
--
48
2.25.1
diff view generated by jsdifflib
[PULL 14/22] target/arm: Move gdbstub related code out of helper.c
[PULL 22/34] target/arm: Remove unused includes from helper.c
1
Currently helper.c includes some code which is part of the arm
1
From: Fabiano Rosas <farosas@suse.de>
2
target's gdbstub support. This code has a better home: in gdbstub.c
3
and gdbstub64.c. Move it there.
4
2
5
Because aarch64_fpu_gdb_get_reg() and aarch64_fpu_gdb_set_reg() move
3
Signed-off-by: Fabiano Rosas <farosas@suse.de>
6
into gdbstub64.c, this means that they're now compiled only for
4
Reviewed-by: Claudio Fontana <cfontana@suse.de>
7
TARGET_AARCH64 rather than always. That is the only case when they
5
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
8
would ever be used, but it does mean that the ifdef in
6
Message-id: 20221213190537.511-6-farosas@suse.de
9
arm_cpu_register_gdb_regs_for_features() needs to be adjusted to
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
match.
8
---
9
target/arm/helper.c | 7 -------
10
1 file changed, 7 deletions(-)
11
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20210921162901.17508-4-peter.maydell@linaro.org
16
---
17
target/arm/internals.h | 7 ++
18
target/arm/gdbstub.c | 130 ++++++++++++++++++++
19
target/arm/gdbstub64.c | 140 +++++++++++++++++++++
20
target/arm/helper.c | 271 -----------------------------------------
21
4 files changed, 277 insertions(+), 271 deletions(-)
22
23
diff --git a/target/arm/internals.h b/target/arm/internals.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/internals.h
26
+++ b/target/arm/internals.h
27
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
28
return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
29
}
30
31
+#ifdef TARGET_AARCH64
32
+int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);
33
+int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);
34
+int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
35
+int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
36
+#endif
37
+
38
#endif
39
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/gdbstub.c
42
+++ b/target/arm/gdbstub.c
43
@@ -XXX,XX +XXX,XX @@
44
*/
45
#include "qemu/osdep.h"
46
#include "cpu.h"
47
+#include "internals.h"
48
#include "exec/gdbstub.h"
49
50
typedef struct RegisterSysregXmlParam {
51
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
52
return 0;
53
}
54
55
+static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
56
+{
57
+ ARMCPU *cpu = env_archcpu(env);
58
+ int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
59
+
60
+ /* VFP data registers are always little-endian. */
61
+ if (reg < nregs) {
62
+ return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));
63
+ }
64
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
65
+ /* Aliases for Q regs. */
66
+ nregs += 16;
67
+ if (reg < nregs) {
68
+ uint64_t *q = aa32_vfp_qreg(env, reg - 32);
69
+ return gdb_get_reg128(buf, q[0], q[1]);
70
+ }
71
+ }
72
+ switch (reg - nregs) {
73
+ case 0:
74
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
75
+ case 1:
76
+ return gdb_get_reg32(buf, vfp_get_fpscr(env));
77
+ case 2:
78
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
79
+ }
80
+ return 0;
81
+}
82
+
83
+static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
84
+{
85
+ ARMCPU *cpu = env_archcpu(env);
86
+ int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
87
+
88
+ if (reg < nregs) {
89
+ *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
90
+ return 8;
91
+ }
92
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
93
+ nregs += 16;
94
+ if (reg < nregs) {
95
+ uint64_t *q = aa32_vfp_qreg(env, reg - 32);
96
+ q[0] = ldq_le_p(buf);
97
+ q[1] = ldq_le_p(buf + 8);
98
+ return 16;
99
+ }
100
+ }
101
+ switch (reg - nregs) {
102
+ case 0:
103
+ env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
104
+ return 4;
105
+ case 1:
106
+ vfp_set_fpscr(env, ldl_p(buf));
107
+ return 4;
108
+ case 2:
109
+ env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
110
+ return 4;
111
+ }
112
+ return 0;
113
+}
114
+
115
+/**
116
+ * arm_get/set_gdb_*: get/set a gdb register
117
+ * @env: the CPU state
118
+ * @buf: a buffer to copy to/from
119
+ * @reg: register number (offset from start of group)
120
+ *
121
+ * We return the number of bytes copied
122
+ */
123
+
124
+static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
125
+{
126
+ ARMCPU *cpu = env_archcpu(env);
127
+ const ARMCPRegInfo *ri;
128
+ uint32_t key;
129
+
130
+ key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];
131
+ ri = get_arm_cp_reginfo(cpu->cp_regs, key);
132
+ if (ri) {
133
+ if (cpreg_field_is_64bit(ri)) {
134
+ return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
135
+ } else {
136
+ return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
137
+ }
138
+ }
139
+ return 0;
140
+}
141
+
142
+static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
143
+{
144
+ return 0;
145
+}
146
+
147
static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
148
ARMCPRegInfo *ri, uint32_t ri_key,
149
int bitsize, int regnum)
150
@@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
151
}
152
return NULL;
153
}
154
+
155
+void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
156
+{
157
+ CPUState *cs = CPU(cpu);
158
+ CPUARMState *env = &cpu->env;
159
+
160
+ if (arm_feature(env, ARM_FEATURE_AARCH64)) {
161
+ /*
162
+ * The lower part of each SVE register aliases to the FPU
163
+ * registers so we don't need to include both.
164
+ */
165
+#ifdef TARGET_AARCH64
166
+ if (isar_feature_aa64_sve(&cpu->isar)) {
167
+ gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
168
+ arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
169
+ "sve-registers.xml", 0);
170
+ } else {
171
+ gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
172
+ aarch64_fpu_gdb_set_reg,
173
+ 34, "aarch64-fpu.xml", 0);
174
+ }
175
+#endif
176
+ } else if (arm_feature(env, ARM_FEATURE_NEON)) {
177
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
178
+ 51, "arm-neon.xml", 0);
179
+ } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
180
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
181
+ 35, "arm-vfp3.xml", 0);
182
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
183
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
184
+ 19, "arm-vfp.xml", 0);
185
+ }
186
+ gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
187
+ arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
188
+ "system-registers.xml", 0);
189
+
190
+}
191
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
192
index XXXXXXX..XXXXXXX 100644
193
--- a/target/arm/gdbstub64.c
194
+++ b/target/arm/gdbstub64.c
195
@@ -XXX,XX +XXX,XX @@
196
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
197
*/
198
#include "qemu/osdep.h"
199
+#include "qemu/log.h"
200
#include "cpu.h"
201
+#include "internals.h"
202
#include "exec/gdbstub.h"
203
204
int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
205
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
206
/* Unknown register. */
207
return 0;
208
}
209
+
210
+int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
211
+{
212
+ switch (reg) {
213
+ case 0 ... 31:
214
+ {
215
+ /* 128 bit FP register - quads are in LE order */
216
+ uint64_t *q = aa64_vfp_qreg(env, reg);
217
+ return gdb_get_reg128(buf, q[1], q[0]);
218
+ }
219
+ case 32:
220
+ /* FPSR */
221
+ return gdb_get_reg32(buf, vfp_get_fpsr(env));
222
+ case 33:
223
+ /* FPCR */
224
+ return gdb_get_reg32(buf, vfp_get_fpcr(env));
225
+ default:
226
+ return 0;
227
+ }
228
+}
229
+
230
+int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
231
+{
232
+ switch (reg) {
233
+ case 0 ... 31:
234
+ /* 128 bit FP register */
235
+ {
236
+ uint64_t *q = aa64_vfp_qreg(env, reg);
237
+ q[0] = ldq_le_p(buf);
238
+ q[1] = ldq_le_p(buf + 8);
239
+ return 16;
240
+ }
241
+ case 32:
242
+ /* FPSR */
243
+ vfp_set_fpsr(env, ldl_p(buf));
244
+ return 4;
245
+ case 33:
246
+ /* FPCR */
247
+ vfp_set_fpcr(env, ldl_p(buf));
248
+ return 4;
249
+ default:
250
+ return 0;
251
+ }
252
+}
253
+
254
+int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
255
+{
256
+ ARMCPU *cpu = env_archcpu(env);
257
+
258
+ switch (reg) {
259
+ /* The first 32 registers are the zregs */
260
+ case 0 ... 31:
261
+ {
262
+ int vq, len = 0;
263
+ for (vq = 0; vq < cpu->sve_max_vq; vq++) {
264
+ len += gdb_get_reg128(buf,
265
+ env->vfp.zregs[reg].d[vq * 2 + 1],
266
+ env->vfp.zregs[reg].d[vq * 2]);
267
+ }
268
+ return len;
269
+ }
270
+ case 32:
271
+ return gdb_get_reg32(buf, vfp_get_fpsr(env));
272
+ case 33:
273
+ return gdb_get_reg32(buf, vfp_get_fpcr(env));
274
+ /* then 16 predicates and the ffr */
275
+ case 34 ... 50:
276
+ {
277
+ int preg = reg - 34;
278
+ int vq, len = 0;
279
+ for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
280
+ len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
281
+ }
282
+ return len;
283
+ }
284
+ case 51:
285
+ {
286
+ /*
287
+ * We report in Vector Granules (VG) which is 64bit in a Z reg
288
+ * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
289
+ */
290
+ int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
291
+ return gdb_get_reg64(buf, vq * 2);
292
+ }
293
+ default:
294
+ /* gdbstub asked for something out our range */
295
+ qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
296
+ break;
297
+ }
298
+
299
+ return 0;
300
+}
301
+
302
+int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
303
+{
304
+ ARMCPU *cpu = env_archcpu(env);
305
+
306
+ /* The first 32 registers are the zregs */
307
+ switch (reg) {
308
+ /* The first 32 registers are the zregs */
309
+ case 0 ... 31:
310
+ {
311
+ int vq, len = 0;
312
+ uint64_t *p = (uint64_t *) buf;
313
+ for (vq = 0; vq < cpu->sve_max_vq; vq++) {
314
+ env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
315
+ env->vfp.zregs[reg].d[vq * 2] = *p++;
316
+ len += 16;
317
+ }
318
+ return len;
319
+ }
320
+ case 32:
321
+ vfp_set_fpsr(env, *(uint32_t *)buf);
322
+ return 4;
323
+ case 33:
324
+ vfp_set_fpcr(env, *(uint32_t *)buf);
325
+ return 4;
326
+ case 34 ... 50:
327
+ {
328
+ int preg = reg - 34;
329
+ int vq, len = 0;
330
+ uint64_t *p = (uint64_t *) buf;
331
+ for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
332
+ env->vfp.pregs[preg].p[vq / 4] = *p++;
333
+ len += 8;
334
+ }
335
+ return len;
336
+ }
337
+ case 51:
338
+ /* cannot set vg via gdbstub */
339
+ return 0;
340
+ default:
341
+ /* gdbstub asked for something out our range */
342
+ break;
343
+ }
344
+
345
+ return 0;
346
+}
347
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
348
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
349
--- a/target/arm/helper.c
14
--- a/target/arm/helper.c
350
+++ b/target/arm/helper.c
15
+++ b/target/arm/helper.c
351
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@
17
*/
18
19
#include "qemu/osdep.h"
20
-#include "qemu/units.h"
21
#include "qemu/log.h"
352
#include "trace.h"
22
#include "trace.h"
353
#include "cpu.h"
23
#include "cpu.h"
354
#include "internals.h"
24
#include "internals.h"
355
-#include "exec/gdbstub.h"
356
#include "exec/helper-proto.h"
25
#include "exec/helper-proto.h"
357
#include "qemu/host-utils.h"
26
-#include "qemu/host-utils.h"
358
#include "qemu/main-loop.h"
27
#include "qemu/main-loop.h"
359
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
28
#include "qemu/timer.h"
360
static void switch_mode(CPUARMState *env, int mode);
29
#include "qemu/bitops.h"
361
static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
30
@@ -XXX,XX +XXX,XX @@
362
31
#include "exec/exec-all.h"
363
-static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
32
#include <zlib.h> /* For crc32 */
364
-{
33
#include "hw/irq.h"
365
- ARMCPU *cpu = env_archcpu(env);
34
-#include "semihosting/semihost.h"
366
- int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
35
-#include "sysemu/cpus.h"
367
-
36
#include "sysemu/cpu-timers.h"
368
- /* VFP data registers are always little-endian. */
37
#include "sysemu/kvm.h"
369
- if (reg < nregs) {
38
-#include "qemu/range.h"
370
- return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));
39
#include "qapi/qapi-commands-machine-target.h"
371
- }
40
#include "qapi/error.h"
372
- if (arm_feature(env, ARM_FEATURE_NEON)) {
41
#include "qemu/guest-random.h"
373
- /* Aliases for Q regs. */
42
#ifdef CONFIG_TCG
374
- nregs += 16;
43
-#include "arm_ldst.h"
375
- if (reg < nregs) {
44
-#include "exec/cpu_ldst.h"
376
- uint64_t *q = aa32_vfp_qreg(env, reg - 32);
45
#include "semihosting/common-semi.h"
377
- return gdb_get_reg128(buf, q[0], q[1]);
378
- }
379
- }
380
- switch (reg - nregs) {
381
- case 0:
382
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
383
- case 1:
384
- return gdb_get_reg32(buf, vfp_get_fpscr(env));
385
- case 2:
386
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
387
- }
388
- return 0;
389
-}
390
-
391
-static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
392
-{
393
- ARMCPU *cpu = env_archcpu(env);
394
- int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
395
-
396
- if (reg < nregs) {
397
- *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
398
- return 8;
399
- }
400
- if (arm_feature(env, ARM_FEATURE_NEON)) {
401
- nregs += 16;
402
- if (reg < nregs) {
403
- uint64_t *q = aa32_vfp_qreg(env, reg - 32);
404
- q[0] = ldq_le_p(buf);
405
- q[1] = ldq_le_p(buf + 8);
406
- return 16;
407
- }
408
- }
409
- switch (reg - nregs) {
410
- case 0:
411
- env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
412
- return 4;
413
- case 1:
414
- vfp_set_fpscr(env, ldl_p(buf));
415
- return 4;
416
- case 2:
417
- env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
418
- return 4;
419
- }
420
- return 0;
421
-}
422
-
423
-static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
424
-{
425
- switch (reg) {
426
- case 0 ... 31:
427
- {
428
- /* 128 bit FP register - quads are in LE order */
429
- uint64_t *q = aa64_vfp_qreg(env, reg);
430
- return gdb_get_reg128(buf, q[1], q[0]);
431
- }
432
- case 32:
433
- /* FPSR */
434
- return gdb_get_reg32(buf, vfp_get_fpsr(env));
435
- case 33:
436
- /* FPCR */
437
- return gdb_get_reg32(buf, vfp_get_fpcr(env));
438
- default:
439
- return 0;
440
- }
441
-}
442
-
443
-static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
444
-{
445
- switch (reg) {
446
- case 0 ... 31:
447
- /* 128 bit FP register */
448
- {
449
- uint64_t *q = aa64_vfp_qreg(env, reg);
450
- q[0] = ldq_le_p(buf);
451
- q[1] = ldq_le_p(buf + 8);
452
- return 16;
453
- }
454
- case 32:
455
- /* FPSR */
456
- vfp_set_fpsr(env, ldl_p(buf));
457
- return 4;
458
- case 33:
459
- /* FPCR */
460
- vfp_set_fpcr(env, ldl_p(buf));
461
- return 4;
462
- default:
463
- return 0;
464
- }
465
-}
466
-
467
static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
468
{
469
assert(ri->fieldoffset);
470
@@ -XXX,XX +XXX,XX @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
471
}
472
}
473
474
-/**
475
- * arm_get/set_gdb_*: get/set a gdb register
476
- * @env: the CPU state
477
- * @buf: a buffer to copy to/from
478
- * @reg: register number (offset from start of group)
479
- *
480
- * We return the number of bytes copied
481
- */
482
-
483
-static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
484
-{
485
- ARMCPU *cpu = env_archcpu(env);
486
- const ARMCPRegInfo *ri;
487
- uint32_t key;
488
-
489
- key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];
490
- ri = get_arm_cp_reginfo(cpu->cp_regs, key);
491
- if (ri) {
492
- if (cpreg_field_is_64bit(ri)) {
493
- return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
494
- } else {
495
- return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
496
- }
497
- }
498
- return 0;
499
-}
500
-
501
-static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
502
-{
503
- return 0;
504
-}
505
-
506
-#ifdef TARGET_AARCH64
507
-static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
508
-{
509
- ARMCPU *cpu = env_archcpu(env);
510
-
511
- switch (reg) {
512
- /* The first 32 registers are the zregs */
513
- case 0 ... 31:
514
- {
515
- int vq, len = 0;
516
- for (vq = 0; vq < cpu->sve_max_vq; vq++) {
517
- len += gdb_get_reg128(buf,
518
- env->vfp.zregs[reg].d[vq * 2 + 1],
519
- env->vfp.zregs[reg].d[vq * 2]);
520
- }
521
- return len;
522
- }
523
- case 32:
524
- return gdb_get_reg32(buf, vfp_get_fpsr(env));
525
- case 33:
526
- return gdb_get_reg32(buf, vfp_get_fpcr(env));
527
- /* then 16 predicates and the ffr */
528
- case 34 ... 50:
529
- {
530
- int preg = reg - 34;
531
- int vq, len = 0;
532
- for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
533
- len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
534
- }
535
- return len;
536
- }
537
- case 51:
538
- {
539
- /*
540
- * We report in Vector Granules (VG) which is 64bit in a Z reg
541
- * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
542
- */
543
- int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
544
- return gdb_get_reg64(buf, vq * 2);
545
- }
546
- default:
547
- /* gdbstub asked for something out our range */
548
- qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
549
- break;
550
- }
551
-
552
- return 0;
553
-}
554
-
555
-static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
556
-{
557
- ARMCPU *cpu = env_archcpu(env);
558
-
559
- /* The first 32 registers are the zregs */
560
- switch (reg) {
561
- /* The first 32 registers are the zregs */
562
- case 0 ... 31:
563
- {
564
- int vq, len = 0;
565
- uint64_t *p = (uint64_t *) buf;
566
- for (vq = 0; vq < cpu->sve_max_vq; vq++) {
567
- env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
568
- env->vfp.zregs[reg].d[vq * 2] = *p++;
569
- len += 16;
570
- }
571
- return len;
572
- }
573
- case 32:
574
- vfp_set_fpsr(env, *(uint32_t *)buf);
575
- return 4;
576
- case 33:
577
- vfp_set_fpcr(env, *(uint32_t *)buf);
578
- return 4;
579
- case 34 ... 50:
580
- {
581
- int preg = reg - 34;
582
- int vq, len = 0;
583
- uint64_t *p = (uint64_t *) buf;
584
- for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
585
- env->vfp.pregs[preg].p[vq / 4] = *p++;
586
- len += 8;
587
- }
588
- return len;
589
- }
590
- case 51:
591
- /* cannot set vg via gdbstub */
592
- return 0;
593
- default:
594
- /* gdbstub asked for something out our range */
595
- break;
596
- }
597
-
598
- return 0;
599
-}
600
-#endif /* TARGET_AARCH64 */
601
-
602
static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
603
{
604
/* Return true if the regdef would cause an assertion if you called
605
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
606
#endif
46
#endif
607
}
47
#include "cpregs.h"
608
609
-void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
610
-{
611
- CPUState *cs = CPU(cpu);
612
- CPUARMState *env = &cpu->env;
613
-
614
- if (arm_feature(env, ARM_FEATURE_AARCH64)) {
615
- /*
616
- * The lower part of each SVE register aliases to the FPU
617
- * registers so we don't need to include both.
618
- */
619
-#ifdef TARGET_AARCH64
620
- if (isar_feature_aa64_sve(&cpu->isar)) {
621
- gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
622
- arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
623
- "sve-registers.xml", 0);
624
- } else
625
-#endif
626
- {
627
- gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
628
- aarch64_fpu_gdb_set_reg,
629
- 34, "aarch64-fpu.xml", 0);
630
- }
631
- } else if (arm_feature(env, ARM_FEATURE_NEON)) {
632
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
633
- 51, "arm-neon.xml", 0);
634
- } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
635
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
636
- 35, "arm-vfp3.xml", 0);
637
- } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
638
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
639
- 19, "arm-vfp.xml", 0);
640
- }
641
- gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
642
- arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
643
- "system-registers.xml", 0);
644
-
645
-}
646
-
647
/* Sort alphabetically by type name, except for "any". */
648
static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
649
{
650
--
48
--
651
2.20.1
49
2.25.1
652
653
diff view generated by jsdifflib
New patch
[PULL 23/34] target/arm: cleanup cpu includes
1
From: Claudio Fontana <cfontana@suse.de>
1
2
3
Remove some unused headers.
4
5
Signed-off-by: Claudio Fontana <cfontana@suse.de>
6
Acked-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Claudio Fontana <cfontana@suse.de>
8
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
9
Signed-off-by: Fabiano Rosas <farosas@suse.de>
10
Message-id: 20221213190537.511-7-farosas@suse.de
11
[added back some includes that are still needed at this point]
12
Signed-off-by: Fabiano Rosas <farosas@suse.de>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/cpu.c | 1 -
16
target/arm/cpu64.c | 6 ------
17
2 files changed, 7 deletions(-)
18
19
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/cpu.c
22
+++ b/target/arm/cpu.c
23
@@ -XXX,XX +XXX,XX @@
24
#include "target/arm/idau.h"
25
#include "qemu/module.h"
26
#include "qapi/error.h"
27
-#include "qapi/visitor.h"
28
#include "cpu.h"
29
#ifdef CONFIG_TCG
30
#include "hw/core/tcg-cpu-ops.h"
31
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/cpu64.c
34
+++ b/target/arm/cpu64.c
35
@@ -XXX,XX +XXX,XX @@
36
#include "qemu/osdep.h"
37
#include "qapi/error.h"
38
#include "cpu.h"
39
-#ifdef CONFIG_TCG
40
-#include "hw/core/tcg-cpu-ops.h"
41
-#endif /* CONFIG_TCG */
42
#include "qemu/module.h"
43
-#if !defined(CONFIG_USER_ONLY)
44
-#include "hw/loader.h"
45
-#endif
46
#include "sysemu/kvm.h"
47
#include "sysemu/hvf.h"
48
#include "kvm_arm.h"
49
--
50
2.25.1
diff view generated by jsdifflib
[PULL 17/22] ipack: Rename ipack_bus_new_inplace() to ipack_bus_init()
[PULL 24/34] hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg
1
Rename ipack_bus_new_inplace() to ipack_bus_init(), to bring it in to
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
line with a "_init for in-place init, _new for allocate-and-return"
3
convention. Drop the 'name' argument, because the only caller does
4
not pass in a name. If a future caller does need to specify the bus
5
name, we should create an ipack_bus_init_named() function at that
6
point.
7
2
3
The pointed MouseTransformInfo structure is accessed read-only.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20221220142520.24094-2-philmd@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
11
Message-id: 20210923121153.23754-3-peter.maydell@linaro.org
12
---
9
---
13
include/hw/ipack/ipack.h | 8 ++++----
10
include/hw/input/tsc2xxx.h | 4 ++--
14
hw/ipack/ipack.c | 10 +++++-----
11
hw/input/tsc2005.c | 2 +-
15
hw/ipack/tpci200.c | 4 ++--
12
hw/input/tsc210x.c | 3 +--
16
3 files changed, 11 insertions(+), 11 deletions(-)
13
3 files changed, 4 insertions(+), 5 deletions(-)
17
14
18
diff --git a/include/hw/ipack/ipack.h b/include/hw/ipack/ipack.h
15
diff --git a/include/hw/input/tsc2xxx.h b/include/hw/input/tsc2xxx.h
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/ipack/ipack.h
17
--- a/include/hw/input/tsc2xxx.h
21
+++ b/include/hw/ipack/ipack.h
18
+++ b/include/hw/input/tsc2xxx.h
22
@@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ipack_device;
19
@@ -XXX,XX +XXX,XX @@ uWireSlave *tsc2102_init(qemu_irq pint);
23
VMSTATE_STRUCT(_field, _state, 1, vmstate_ipack_device, IPackDevice)
20
uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav);
24
21
I2SCodec *tsc210x_codec(uWireSlave *chip);
25
IPackDevice *ipack_device_find(IPackBus *bus, int32_t slot);
22
uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len);
26
-void ipack_bus_new_inplace(IPackBus *bus, size_t bus_size,
23
-void tsc210x_set_transform(uWireSlave *chip, MouseTransformInfo *info);
27
- DeviceState *parent,
24
+void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *info);
28
- const char *name, uint8_t n_slots,
25
void tsc210x_key_event(uWireSlave *chip, int key, int down);
29
- qemu_irq_handler handler);
26
30
+void ipack_bus_init(IPackBus *bus, size_t bus_size,
27
/* tsc2005.c */
31
+ DeviceState *parent,
28
void *tsc2005_init(qemu_irq pintdav);
32
+ uint8_t n_slots,
29
uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len);
33
+ qemu_irq_handler handler);
30
-void tsc2005_set_transform(void *opaque, MouseTransformInfo *info);
31
+void tsc2005_set_transform(void *opaque, const MouseTransformInfo *info);
34
32
35
#endif
33
#endif
36
diff --git a/hw/ipack/ipack.c b/hw/ipack/ipack.c
34
diff --git a/hw/input/tsc2005.c b/hw/input/tsc2005.c
37
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/ipack/ipack.c
36
--- a/hw/input/tsc2005.c
39
+++ b/hw/ipack/ipack.c
37
+++ b/hw/input/tsc2005.c
40
@@ -XXX,XX +XXX,XX @@ IPackDevice *ipack_device_find(IPackBus *bus, int32_t slot)
38
@@ -XXX,XX +XXX,XX @@ void *tsc2005_init(qemu_irq pintdav)
41
return NULL;
39
* from the touchscreen. Assuming 12-bit precision was used during
42
}
40
* tslib calibration.
43
41
*/
44
-void ipack_bus_new_inplace(IPackBus *bus, size_t bus_size,
42
-void tsc2005_set_transform(void *opaque, MouseTransformInfo *info)
45
- DeviceState *parent,
43
+void tsc2005_set_transform(void *opaque, const MouseTransformInfo *info)
46
- const char *name, uint8_t n_slots,
47
- qemu_irq_handler handler)
48
+void ipack_bus_init(IPackBus *bus, size_t bus_size,
49
+ DeviceState *parent,
50
+ uint8_t n_slots,
51
+ qemu_irq_handler handler)
52
{
44
{
53
- qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, name);
45
TSC2005State *s = (TSC2005State *) opaque;
54
+ qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, NULL);
46
55
bus->n_slots = n_slots;
47
diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c
56
bus->set_irq = handler;
57
}
58
diff --git a/hw/ipack/tpci200.c b/hw/ipack/tpci200.c
59
index XXXXXXX..XXXXXXX 100644
48
index XXXXXXX..XXXXXXX 100644
60
--- a/hw/ipack/tpci200.c
49
--- a/hw/input/tsc210x.c
61
+++ b/hw/ipack/tpci200.c
50
+++ b/hw/input/tsc210x.c
62
@@ -XXX,XX +XXX,XX @@ static void tpci200_realize(PCIDevice *pci_dev, Error **errp)
51
@@ -XXX,XX +XXX,XX @@ I2SCodec *tsc210x_codec(uWireSlave *chip)
63
pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las2);
52
* from the touchscreen. Assuming 12-bit precision was used during
64
pci_register_bar(&s->dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las3);
53
* tslib calibration.
65
54
*/
66
- ipack_bus_new_inplace(&s->bus, sizeof(s->bus), DEVICE(pci_dev), NULL,
55
-void tsc210x_set_transform(uWireSlave *chip,
67
- N_MODULES, tpci200_set_irq);
56
- MouseTransformInfo *info)
68
+ ipack_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
57
+void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *info)
69
+ N_MODULES, tpci200_set_irq);
58
{
70
}
59
TSC210xState *s = (TSC210xState *) chip->opaque;
71
60
#if 0
72
static const VMStateDescription vmstate_tpci200 = {
73
--
61
--
74
2.20.1
62
2.25.1
75
63
76
64
diff view generated by jsdifflib
[PULL 20/22] qbus: Rename qbus_create() to qbus_new()
[PULL 25/34] hw/arm/nseries: Constify various read-only arrays
1
Rename the "allocate and return" qbus creation function to
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
qbus_new(), to bring it into line with our _init vs _new convention.
3
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20221220142520.24094-3-philmd@linaro.org
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
7
Reviewed-by: Corey Minyard <cminyard@mvista.com>
8
Message-id: 20210923121153.23754-6-peter.maydell@linaro.org
9
---
7
---
10
include/hw/qdev-core.h | 2 +-
8
hw/arm/nseries.c | 18 +++++++++---------
11
hw/core/bus.c | 2 +-
9
1 file changed, 9 insertions(+), 9 deletions(-)
12
hw/hyperv/vmbus.c | 2 +-
13
hw/i2c/core.c | 2 +-
14
hw/isa/isa-bus.c | 2 +-
15
hw/misc/auxbus.c | 2 +-
16
hw/pci/pci.c | 2 +-
17
hw/ppc/spapr_vio.c | 2 +-
18
hw/s390x/ap-bridge.c | 2 +-
19
hw/s390x/css-bridge.c | 2 +-
20
hw/s390x/s390-pci-bus.c | 2 +-
21
hw/ssi/ssi.c | 2 +-
22
hw/xen/xen-bus.c | 2 +-
23
hw/xen/xen-legacy-backend.c | 2 +-
24
14 files changed, 14 insertions(+), 14 deletions(-)
25
10
26
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
11
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
27
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/qdev-core.h
13
--- a/hw/arm/nseries.c
29
+++ b/include/hw/qdev-core.h
14
+++ b/hw/arm/nseries.c
30
@@ -XXX,XX +XXX,XX @@ typedef int (qdev_walkerfn)(DeviceState *dev, void *opaque);
15
@@ -XXX,XX +XXX,XX @@ static void n8x0_i2c_setup(struct n800_s *s)
31
32
void qbus_init(void *bus, size_t size, const char *typename,
33
DeviceState *parent, const char *name);
34
-BusState *qbus_create(const char *typename, DeviceState *parent, const char *name);
35
+BusState *qbus_new(const char *typename, DeviceState *parent, const char *name);
36
bool qbus_realize(BusState *bus, Error **errp);
37
void qbus_unrealize(BusState *bus);
38
39
diff --git a/hw/core/bus.c b/hw/core/bus.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/core/bus.c
42
+++ b/hw/core/bus.c
43
@@ -XXX,XX +XXX,XX @@ void qbus_init(void *bus, size_t size, const char *typename,
44
qbus_init_internal(bus, parent, name);
45
}
16
}
46
17
47
-BusState *qbus_create(const char *typename, DeviceState *parent, const char *name)
18
/* Touchscreen and keypad controller */
48
+BusState *qbus_new(const char *typename, DeviceState *parent, const char *name)
19
-static MouseTransformInfo n800_pointercal = {
20
+static const MouseTransformInfo n800_pointercal = {
21
.x = 800,
22
.y = 480,
23
.a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
24
};
25
26
-static MouseTransformInfo n810_pointercal = {
27
+static const MouseTransformInfo n810_pointercal = {
28
.x = 800,
29
.y = 480,
30
.a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
31
@@ -XXX,XX +XXX,XX @@ static void n810_key_event(void *opaque, int keycode)
32
33
#define M    0
34
35
-static int n810_keys[0x80] = {
36
+static const int n810_keys[0x80] = {
37
[0x01] = 16,    /* Q */
38
[0x02] = 37,    /* K */
39
[0x03] = 24,    /* O */
40
@@ -XXX,XX +XXX,XX @@ static void n8x0_usb_setup(struct n800_s *s)
41
/* Setup done before the main bootloader starts by some early setup code
42
* - used when we want to run the main bootloader in emulation. This
43
* isn't documented. */
44
-static uint32_t n800_pinout[104] = {
45
+static const uint32_t n800_pinout[104] = {
46
0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
47
0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
48
0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
49
@@ -XXX,XX +XXX,XX @@ static void n8x0_boot_init(void *opaque)
50
#define OMAP_TAG_CBUS        0x4e03
51
#define OMAP_TAG_EM_ASIC_BB5    0x4e04
52
53
-static struct omap_gpiosw_info_s {
54
+static const struct omap_gpiosw_info_s {
55
const char *name;
56
int line;
57
int type;
58
@@ -XXX,XX +XXX,XX @@ static struct omap_gpiosw_info_s {
59
{ NULL }
60
};
61
62
-static struct omap_partition_info_s {
63
+static const struct omap_partition_info_s {
64
uint32_t offset;
65
uint32_t size;
66
int mask;
67
@@ -XXX,XX +XXX,XX @@ static struct omap_partition_info_s {
68
{ 0, 0, 0, NULL }
69
};
70
71
-static uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
72
+static const uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
73
74
static int n8x0_atag_setup(void *p, int model)
49
{
75
{
50
BusState *bus;
76
uint8_t *b;
51
77
uint16_t *w;
52
diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c
78
uint32_t *l;
53
index XXXXXXX..XXXXXXX 100644
79
- struct omap_gpiosw_info_s *gpiosw;
54
--- a/hw/hyperv/vmbus.c
80
- struct omap_partition_info_s *partition;
55
+++ b/hw/hyperv/vmbus.c
81
+ const struct omap_gpiosw_info_s *gpiosw;
56
@@ -XXX,XX +XXX,XX @@ static void vmbus_bridge_realize(DeviceState *dev, Error **errp)
82
+ const struct omap_partition_info_s *partition;
57
return;
83
const char *tag;
58
}
84
59
85
w = p;
60
- bridge->bus = VMBUS(qbus_create(TYPE_VMBUS, dev, "vmbus"));
61
+ bridge->bus = VMBUS(qbus_new(TYPE_VMBUS, dev, "vmbus"));
62
}
63
64
static char *vmbus_bridge_ofw_unit_address(const SysBusDevice *dev)
65
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/hw/i2c/core.c
68
+++ b/hw/i2c/core.c
69
@@ -XXX,XX +XXX,XX @@ I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
70
{
71
I2CBus *bus;
72
73
- bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name));
74
+ bus = I2C_BUS(qbus_new(TYPE_I2C_BUS, parent, name));
75
QLIST_INIT(&bus->current_devs);
76
vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_i2c_bus, bus);
77
return bus;
78
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/hw/isa/isa-bus.c
81
+++ b/hw/isa/isa-bus.c
82
@@ -XXX,XX +XXX,XX @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion* address_space,
83
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
84
}
85
86
- isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL));
87
+ isabus = ISA_BUS(qbus_new(TYPE_ISA_BUS, dev, NULL));
88
isabus->address_space = address_space;
89
isabus->address_space_io = address_space_io;
90
return isabus;
91
diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/hw/misc/auxbus.c
94
+++ b/hw/misc/auxbus.c
95
@@ -XXX,XX +XXX,XX @@ AUXBus *aux_bus_init(DeviceState *parent, const char *name)
96
AUXBus *bus;
97
Object *auxtoi2c;
98
99
- bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
100
+ bus = AUX_BUS(qbus_new(TYPE_AUX_BUS, parent, name));
101
auxtoi2c = object_new_with_props(TYPE_AUXTOI2C, OBJECT(bus), "i2c",
102
&error_abort, NULL);
103
104
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/hw/pci/pci.c
107
+++ b/hw/pci/pci.c
108
@@ -XXX,XX +XXX,XX @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
109
{
110
PCIBus *bus;
111
112
- bus = PCI_BUS(qbus_create(typename, parent, name));
113
+ bus = PCI_BUS(qbus_new(typename, parent, name));
114
pci_root_bus_internal_init(bus, parent, address_space_mem,
115
address_space_io, devfn_min);
116
return bus;
117
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/hw/ppc/spapr_vio.c
120
+++ b/hw/ppc/spapr_vio.c
121
@@ -XXX,XX +XXX,XX @@ SpaprVioBus *spapr_vio_bus_init(void)
122
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
123
124
/* Create bus on bridge device */
125
- qbus = qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");
126
+ qbus = qbus_new(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");
127
bus = SPAPR_VIO_BUS(qbus);
128
bus->next_reg = SPAPR_VIO_REG_BASE;
129
130
diff --git a/hw/s390x/ap-bridge.c b/hw/s390x/ap-bridge.c
131
index XXXXXXX..XXXXXXX 100644
132
--- a/hw/s390x/ap-bridge.c
133
+++ b/hw/s390x/ap-bridge.c
134
@@ -XXX,XX +XXX,XX @@ void s390_init_ap(void)
135
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
136
137
/* Create bus on bridge device */
138
- bus = qbus_create(TYPE_AP_BUS, dev, TYPE_AP_BUS);
139
+ bus = qbus_new(TYPE_AP_BUS, dev, TYPE_AP_BUS);
140
141
/* Enable hotplugging */
142
qbus_set_hotplug_handler(bus, OBJECT(dev));
143
diff --git a/hw/s390x/css-bridge.c b/hw/s390x/css-bridge.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/hw/s390x/css-bridge.c
146
+++ b/hw/s390x/css-bridge.c
147
@@ -XXX,XX +XXX,XX @@ VirtualCssBus *virtual_css_bus_init(void)
148
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
149
150
/* Create bus on bridge device */
151
- bus = qbus_create(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css");
152
+ bus = qbus_new(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css");
153
cbus = VIRTUAL_CSS_BUS(bus);
154
155
/* Enable hotplugging */
156
diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c
157
index XXXXXXX..XXXXXXX 100644
158
--- a/hw/s390x/s390-pci-bus.c
159
+++ b/hw/s390x/s390-pci-bus.c
160
@@ -XXX,XX +XXX,XX @@ static void s390_pcihost_realize(DeviceState *dev, Error **errp)
161
qbus_set_hotplug_handler(bus, OBJECT(dev));
162
phb->bus = b;
163
164
- s->bus = S390_PCI_BUS(qbus_create(TYPE_S390_PCI_BUS, dev, NULL));
165
+ s->bus = S390_PCI_BUS(qbus_new(TYPE_S390_PCI_BUS, dev, NULL));
166
qbus_set_hotplug_handler(BUS(s->bus), OBJECT(dev));
167
168
s->iommu_table = g_hash_table_new_full(g_int64_hash, g_int64_equal,
169
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
170
index XXXXXXX..XXXXXXX 100644
171
--- a/hw/ssi/ssi.c
172
+++ b/hw/ssi/ssi.c
173
@@ -XXX,XX +XXX,XX @@ DeviceState *ssi_create_peripheral(SSIBus *bus, const char *name)
174
SSIBus *ssi_create_bus(DeviceState *parent, const char *name)
175
{
176
BusState *bus;
177
- bus = qbus_create(TYPE_SSI_BUS, parent, name);
178
+ bus = qbus_new(TYPE_SSI_BUS, parent, name);
179
return SSI_BUS(bus);
180
}
181
182
diff --git a/hw/xen/xen-bus.c b/hw/xen/xen-bus.c
183
index XXXXXXX..XXXXXXX 100644
184
--- a/hw/xen/xen-bus.c
185
+++ b/hw/xen/xen-bus.c
186
@@ -XXX,XX +XXX,XX @@ type_init(xen_register_types)
187
void xen_bus_init(void)
188
{
189
DeviceState *dev = qdev_new(TYPE_XEN_BRIDGE);
190
- BusState *bus = qbus_create(TYPE_XEN_BUS, dev, NULL);
191
+ BusState *bus = qbus_new(TYPE_XEN_BUS, dev, NULL);
192
193
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
194
qbus_set_bus_hotplug_handler(bus);
195
diff --git a/hw/xen/xen-legacy-backend.c b/hw/xen/xen-legacy-backend.c
196
index XXXXXXX..XXXXXXX 100644
197
--- a/hw/xen/xen-legacy-backend.c
198
+++ b/hw/xen/xen-legacy-backend.c
199
@@ -XXX,XX +XXX,XX @@ int xen_be_init(void)
200
201
xen_sysdev = qdev_new(TYPE_XENSYSDEV);
202
sysbus_realize_and_unref(SYS_BUS_DEVICE(xen_sysdev), &error_fatal);
203
- xen_sysbus = qbus_create(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus");
204
+ xen_sysbus = qbus_new(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus");
205
qbus_set_bus_hotplug_handler(xen_sysbus);
206
207
return 0;
208
--
86
--
209
2.20.1
87
2.25.1
210
88
211
89
diff view generated by jsdifflib
[PULL 21/22] ide: Rename ide_bus_new() to ide_bus_init()
[PULL 26/34] hw/arm/nseries: Silent -Wmissing-field-initializers warning
1
The function ide_bus_new() does an in-place initialization. Rename
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
it to ide_bus_init() to follow our _init vs _new convention.
3
2
3
Silent when compiling with -Wextra:
4
5
../hw/arm/nseries.c:1081:12: warning: missing field 'line' initializer [-Wmissing-field-initializers]
6
{ NULL }
7
^
8
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-id: 20221220142520.24094-4-philmd@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
7
Reviewed-by: Corey Minyard <cminyard@mvista.com>
8
Reviewed-by: John Snow <jsnow@redhat.com>
9
Acked-by: John Snow <jsnow@redhat.com> (Feel free to merge.)
10
Message-id: 20210923121153.23754-7-peter.maydell@linaro.org
11
---
13
---
12
include/hw/ide/internal.h | 4 ++--
14
hw/arm/nseries.c | 10 ++++------
13
hw/ide/ahci.c | 2 +-
15
1 file changed, 4 insertions(+), 6 deletions(-)
14
hw/ide/cmd646.c | 2 +-
15
hw/ide/isa.c | 2 +-
16
hw/ide/macio.c | 2 +-
17
hw/ide/microdrive.c | 2 +-
18
hw/ide/mmio.c | 2 +-
19
hw/ide/piix.c | 2 +-
20
hw/ide/qdev.c | 2 +-
21
hw/ide/sii3112.c | 2 +-
22
hw/ide/via.c | 2 +-
23
11 files changed, 12 insertions(+), 12 deletions(-)
24
16
25
diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h
17
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
26
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/ide/internal.h
19
--- a/hw/arm/nseries.c
28
+++ b/include/hw/ide/internal.h
20
+++ b/hw/arm/nseries.c
29
@@ -XXX,XX +XXX,XX @@ void ide_atapi_cmd(IDEState *s);
21
@@ -XXX,XX +XXX,XX @@ static const struct omap_gpiosw_info_s {
30
void ide_atapi_cmd_reply_end(IDEState *s);
22
"headphone", N8X0_HEADPHONE_GPIO,
31
23
OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
32
/* hw/ide/qdev.c */
24
},
33
-void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
25
- { NULL }
34
- int bus_id, int max_units);
26
+ { /* end of list */ }
35
+void ide_bus_init(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
27
}, n810_gpiosw_info[] = {
36
+ int bus_id, int max_units);
28
{
37
IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive);
29
"gps_reset", N810_GPS_RESET_GPIO,
38
30
@@ -XXX,XX +XXX,XX @@ static const struct omap_gpiosw_info_s {
39
int ide_handle_rw_error(IDEState *s, int error, int op);
31
"slide", N810_SLIDE_GPIO,
40
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
32
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
41
index XXXXXXX..XXXXXXX 100644
33
},
42
--- a/hw/ide/ahci.c
34
- { NULL }
43
+++ b/hw/ide/ahci.c
35
+ { /* end of list */ }
44
@@ -XXX,XX +XXX,XX @@ void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
45
for (i = 0; i < s->ports; i++) {
46
AHCIDevice *ad = &s->dev[i];
47
48
- ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1);
49
+ ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1);
50
ide_init2(&ad->port, irqs[i]);
51
52
ad->hba = s;
53
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/ide/cmd646.c
56
+++ b/hw/ide/cmd646.c
57
@@ -XXX,XX +XXX,XX @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
58
59
qdev_init_gpio_in(ds, cmd646_set_irq, 2);
60
for (i = 0; i < 2; i++) {
61
- ide_bus_new(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
62
+ ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
63
ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i));
64
65
bmdma_init(&d->bus[i], &d->bmdma[i], d);
66
diff --git a/hw/ide/isa.c b/hw/ide/isa.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/ide/isa.c
69
+++ b/hw/ide/isa.c
70
@@ -XXX,XX +XXX,XX @@ static void isa_ide_realizefn(DeviceState *dev, Error **errp)
71
ISADevice *isadev = ISA_DEVICE(dev);
72
ISAIDEState *s = ISA_IDE(dev);
73
74
- ide_bus_new(&s->bus, sizeof(s->bus), dev, 0, 2);
75
+ ide_bus_init(&s->bus, sizeof(s->bus), dev, 0, 2);
76
ide_init_ioport(&s->bus, isadev, s->iobase, s->iobase2);
77
isa_init_irq(isadev, &s->irq, s->isairq);
78
ide_init2(&s->bus, s->irq);
79
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/ide/macio.c
82
+++ b/hw/ide/macio.c
83
@@ -XXX,XX +XXX,XX @@ static void macio_ide_initfn(Object *obj)
84
SysBusDevice *d = SYS_BUS_DEVICE(obj);
85
MACIOIDEState *s = MACIO_IDE(obj);
86
87
- ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
88
+ ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
89
memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
90
sysbus_init_mmio(d, &s->mem);
91
sysbus_init_irq(d, &s->real_ide_irq);
92
diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/hw/ide/microdrive.c
95
+++ b/hw/ide/microdrive.c
96
@@ -XXX,XX +XXX,XX @@ static void microdrive_init(Object *obj)
97
{
98
MicroDriveState *md = MICRODRIVE(obj);
99
100
- ide_bus_new(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
101
+ ide_bus_init(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
102
}
103
104
static void microdrive_class_init(ObjectClass *oc, void *data)
105
diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/hw/ide/mmio.c
108
+++ b/hw/ide/mmio.c
109
@@ -XXX,XX +XXX,XX @@ static void mmio_ide_initfn(Object *obj)
110
SysBusDevice *d = SYS_BUS_DEVICE(obj);
111
MMIOState *s = MMIO_IDE(obj);
112
113
- ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
114
+ ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
115
sysbus_init_irq(d, &s->irq);
116
}
117
118
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
119
index XXXXXXX..XXXXXXX 100644
120
--- a/hw/ide/piix.c
121
+++ b/hw/ide/piix.c
122
@@ -XXX,XX +XXX,XX @@ static int pci_piix_init_ports(PCIIDEState *d)
123
int i, ret;
124
125
for (i = 0; i < 2; i++) {
126
- ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
127
+ ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
128
ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
129
port_info[i].iobase2);
130
if (ret) {
131
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/hw/ide/qdev.c
134
+++ b/hw/ide/qdev.c
135
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ide_bus_info = {
136
.class_init = ide_bus_class_init,
137
};
36
};
138
37
139
-void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
38
static const struct omap_partition_info_s {
140
+void ide_bus_init(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
39
@@ -XXX,XX +XXX,XX @@ static const struct omap_partition_info_s {
141
int bus_id, int max_units)
40
{ 0x00080000, 0x00200000, 0x0, "kernel" },
142
{
41
{ 0x00280000, 0x00200000, 0x3, "initfs" },
143
qbus_init(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL);
42
{ 0x00480000, 0x0fb80000, 0x3, "rootfs" },
144
diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c
43
-
145
index XXXXXXX..XXXXXXX 100644
44
- { 0, 0, 0, NULL }
146
--- a/hw/ide/sii3112.c
45
+ { /* end of list */ }
147
+++ b/hw/ide/sii3112.c
46
}, n810_part_info[] = {
148
@@ -XXX,XX +XXX,XX @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp)
47
{ 0x00000000, 0x00020000, 0x3, "bootloader" },
149
48
{ 0x00020000, 0x00060000, 0x0, "config" },
150
qdev_init_gpio_in(ds, sii3112_set_irq, 2);
49
{ 0x00080000, 0x00220000, 0x0, "kernel" },
151
for (i = 0; i < 2; i++) {
50
{ 0x002a0000, 0x00400000, 0x0, "initfs" },
152
- ide_bus_new(&s->bus[i], sizeof(s->bus[i]), ds, i, 1);
51
{ 0x006a0000, 0x0f960000, 0x0, "rootfs" },
153
+ ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1);
52
-
154
ide_init2(&s->bus[i], qdev_get_gpio_in(ds, i));
53
- { 0, 0, 0, NULL }
155
54
+ { /* end of list */ }
156
bmdma_init(&s->bus[i], &s->bmdma[i], s);
55
};
157
diff --git a/hw/ide/via.c b/hw/ide/via.c
56
158
index XXXXXXX..XXXXXXX 100644
57
static const uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
159
--- a/hw/ide/via.c
160
+++ b/hw/ide/via.c
161
@@ -XXX,XX +XXX,XX @@ static void via_ide_realize(PCIDevice *dev, Error **errp)
162
163
qdev_init_gpio_in(ds, via_ide_set_irq, 2);
164
for (i = 0; i < 2; i++) {
165
- ide_bus_new(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
166
+ ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
167
ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i));
168
169
bmdma_init(&d->bus[i], &d->bmdma[i], d);
170
--
58
--
171
2.20.1
59
2.25.1
172
60
173
61
diff view generated by jsdifflib
New patch
[PULL 27/34] target/arm: align exposed ID registers with Linux
1
1
From: Zhuojia Shen <chaosdefinition@hotmail.com>
2
3
In CPUID registers exposed to userspace, some registers were missing
4
and some fields were not exposed. This patch aligns exposed ID
5
registers and their fields with what the upstream kernel currently
6
exposes.
7
8
Specifically, the following new ID registers/fields are exposed to
9
userspace:
10
11
ID_AA64PFR1_EL1.BT: bits 3-0
12
ID_AA64PFR1_EL1.MTE: bits 11-8
13
ID_AA64PFR1_EL1.SME: bits 27-24
14
15
ID_AA64ZFR0_EL1.SVEver: bits 3-0
16
ID_AA64ZFR0_EL1.AES: bits 7-4
17
ID_AA64ZFR0_EL1.BitPerm: bits 19-16
18
ID_AA64ZFR0_EL1.BF16: bits 23-20
19
ID_AA64ZFR0_EL1.SHA3: bits 35-32
20
ID_AA64ZFR0_EL1.SM4: bits 43-40
21
ID_AA64ZFR0_EL1.I8MM: bits 47-44
22
ID_AA64ZFR0_EL1.F32MM: bits 55-52
23
ID_AA64ZFR0_EL1.F64MM: bits 59-56
24
25
ID_AA64SMFR0_EL1.F32F32: bit 32
26
ID_AA64SMFR0_EL1.B16F32: bit 34
27
ID_AA64SMFR0_EL1.F16F32: bit 35
28
ID_AA64SMFR0_EL1.I8I32: bits 39-36
29
ID_AA64SMFR0_EL1.F64F64: bit 48
30
ID_AA64SMFR0_EL1.I16I64: bits 55-52
31
ID_AA64SMFR0_EL1.FA64: bit 63
32
33
ID_AA64MMFR0_EL1.ECV: bits 63-60
34
35
ID_AA64MMFR1_EL1.AFP: bits 47-44
36
37
ID_AA64MMFR2_EL1.AT: bits 35-32
38
39
ID_AA64ISAR0_EL1.RNDR: bits 63-60
40
41
ID_AA64ISAR1_EL1.FRINTTS: bits 35-32
42
ID_AA64ISAR1_EL1.BF16: bits 47-44
43
ID_AA64ISAR1_EL1.DGH: bits 51-48
44
ID_AA64ISAR1_EL1.I8MM: bits 55-52
45
46
ID_AA64ISAR2_EL1.WFxT: bits 3-0
47
ID_AA64ISAR2_EL1.RPRES: bits 7-4
48
ID_AA64ISAR2_EL1.GPA3: bits 11-8
49
ID_AA64ISAR2_EL1.APA3: bits 15-12
50
51
The code is also refactored to use symbolic names for ID register fields
52
for better readability and maintainability.
53
54
The test case in tests/tcg/aarch64/sysregs.c is also updated to match
55
the intended behavior.
56
57
Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
58
Message-id: DS7PR12MB6309FB585E10772928F14271ACE79@DS7PR12MB6309.namprd12.prod.outlook.com
59
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
60
[PMM: use Sn_n_Cn_Cn_n syntax to work with older assemblers
61
that don't recognize id_aa64isar2_el1 and id_aa64mmfr2_el1]
62
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
63
---
64
target/arm/helper.c | 96 +++++++++++++++++++++++++------
65
tests/tcg/aarch64/sysregs.c | 24 ++++++--
66
tests/tcg/aarch64/Makefile.target | 7 ++-
67
3 files changed, 103 insertions(+), 24 deletions(-)
68
69
diff --git a/target/arm/helper.c b/target/arm/helper.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/target/arm/helper.c
72
+++ b/target/arm/helper.c
73
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
74
#ifdef CONFIG_USER_ONLY
75
static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
76
{ .name = "ID_AA64PFR0_EL1",
77
- .exported_bits = 0x000f000f00ff0000,
78
- .fixed_bits = 0x0000000000000011 },
79
+ .exported_bits = R_ID_AA64PFR0_FP_MASK |
80
+ R_ID_AA64PFR0_ADVSIMD_MASK |
81
+ R_ID_AA64PFR0_SVE_MASK |
82
+ R_ID_AA64PFR0_DIT_MASK,
83
+ .fixed_bits = (0x1u << R_ID_AA64PFR0_EL0_SHIFT) |
84
+ (0x1u << R_ID_AA64PFR0_EL1_SHIFT) },
85
{ .name = "ID_AA64PFR1_EL1",
86
- .exported_bits = 0x00000000000000f0 },
87
+ .exported_bits = R_ID_AA64PFR1_BT_MASK |
88
+ R_ID_AA64PFR1_SSBS_MASK |
89
+ R_ID_AA64PFR1_MTE_MASK |
90
+ R_ID_AA64PFR1_SME_MASK },
91
{ .name = "ID_AA64PFR*_EL1_RESERVED",
92
- .is_glob = true },
93
- { .name = "ID_AA64ZFR0_EL1" },
94
+ .is_glob = true },
95
+ { .name = "ID_AA64ZFR0_EL1",
96
+ .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK |
97
+ R_ID_AA64ZFR0_AES_MASK |
98
+ R_ID_AA64ZFR0_BITPERM_MASK |
99
+ R_ID_AA64ZFR0_BFLOAT16_MASK |
100
+ R_ID_AA64ZFR0_SHA3_MASK |
101
+ R_ID_AA64ZFR0_SM4_MASK |
102
+ R_ID_AA64ZFR0_I8MM_MASK |
103
+ R_ID_AA64ZFR0_F32MM_MASK |
104
+ R_ID_AA64ZFR0_F64MM_MASK },
105
+ { .name = "ID_AA64SMFR0_EL1",
106
+ .exported_bits = R_ID_AA64SMFR0_F32F32_MASK |
107
+ R_ID_AA64SMFR0_B16F32_MASK |
108
+ R_ID_AA64SMFR0_F16F32_MASK |
109
+ R_ID_AA64SMFR0_I8I32_MASK |
110
+ R_ID_AA64SMFR0_F64F64_MASK |
111
+ R_ID_AA64SMFR0_I16I64_MASK |
112
+ R_ID_AA64SMFR0_FA64_MASK },
113
{ .name = "ID_AA64MMFR0_EL1",
114
- .fixed_bits = 0x00000000ff000000 },
115
- { .name = "ID_AA64MMFR1_EL1" },
116
+ .exported_bits = R_ID_AA64MMFR0_ECV_MASK,
117
+ .fixed_bits = (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) |
118
+ (0xfu << R_ID_AA64MMFR0_TGRAN4_SHIFT) },
119
+ { .name = "ID_AA64MMFR1_EL1",
120
+ .exported_bits = R_ID_AA64MMFR1_AFP_MASK },
121
+ { .name = "ID_AA64MMFR2_EL1",
122
+ .exported_bits = R_ID_AA64MMFR2_AT_MASK },
123
{ .name = "ID_AA64MMFR*_EL1_RESERVED",
124
- .is_glob = true },
125
+ .is_glob = true },
126
{ .name = "ID_AA64DFR0_EL1",
127
- .fixed_bits = 0x0000000000000006 },
128
- { .name = "ID_AA64DFR1_EL1" },
129
+ .fixed_bits = (0x6u << R_ID_AA64DFR0_DEBUGVER_SHIFT) },
130
+ { .name = "ID_AA64DFR1_EL1" },
131
{ .name = "ID_AA64DFR*_EL1_RESERVED",
132
- .is_glob = true },
133
+ .is_glob = true },
134
{ .name = "ID_AA64AFR*",
135
- .is_glob = true },
136
+ .is_glob = true },
137
{ .name = "ID_AA64ISAR0_EL1",
138
- .exported_bits = 0x00fffffff0fffff0 },
139
+ .exported_bits = R_ID_AA64ISAR0_AES_MASK |
140
+ R_ID_AA64ISAR0_SHA1_MASK |
141
+ R_ID_AA64ISAR0_SHA2_MASK |
142
+ R_ID_AA64ISAR0_CRC32_MASK |
143
+ R_ID_AA64ISAR0_ATOMIC_MASK |
144
+ R_ID_AA64ISAR0_RDM_MASK |
145
+ R_ID_AA64ISAR0_SHA3_MASK |
146
+ R_ID_AA64ISAR0_SM3_MASK |
147
+ R_ID_AA64ISAR0_SM4_MASK |
148
+ R_ID_AA64ISAR0_DP_MASK |
149
+ R_ID_AA64ISAR0_FHM_MASK |
150
+ R_ID_AA64ISAR0_TS_MASK |
151
+ R_ID_AA64ISAR0_RNDR_MASK },
152
{ .name = "ID_AA64ISAR1_EL1",
153
- .exported_bits = 0x000000f0ffffffff },
154
+ .exported_bits = R_ID_AA64ISAR1_DPB_MASK |
155
+ R_ID_AA64ISAR1_APA_MASK |
156
+ R_ID_AA64ISAR1_API_MASK |
157
+ R_ID_AA64ISAR1_JSCVT_MASK |
158
+ R_ID_AA64ISAR1_FCMA_MASK |
159
+ R_ID_AA64ISAR1_LRCPC_MASK |
160
+ R_ID_AA64ISAR1_GPA_MASK |
161
+ R_ID_AA64ISAR1_GPI_MASK |
162
+ R_ID_AA64ISAR1_FRINTTS_MASK |
163
+ R_ID_AA64ISAR1_SB_MASK |
164
+ R_ID_AA64ISAR1_BF16_MASK |
165
+ R_ID_AA64ISAR1_DGH_MASK |
166
+ R_ID_AA64ISAR1_I8MM_MASK },
167
+ { .name = "ID_AA64ISAR2_EL1",
168
+ .exported_bits = R_ID_AA64ISAR2_WFXT_MASK |
169
+ R_ID_AA64ISAR2_RPRES_MASK |
170
+ R_ID_AA64ISAR2_GPA3_MASK |
171
+ R_ID_AA64ISAR2_APA3_MASK },
172
{ .name = "ID_AA64ISAR*_EL1_RESERVED",
173
- .is_glob = true },
174
+ .is_glob = true },
175
};
176
modify_arm_cp_regs(v8_idregs, v8_user_idregs);
177
#endif
178
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
179
#ifdef CONFIG_USER_ONLY
180
static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
181
{ .name = "MIDR_EL1",
182
- .exported_bits = 0x00000000ffffffff },
183
- { .name = "REVIDR_EL1" },
184
+ .exported_bits = R_MIDR_EL1_REVISION_MASK |
185
+ R_MIDR_EL1_PARTNUM_MASK |
186
+ R_MIDR_EL1_ARCHITECTURE_MASK |
187
+ R_MIDR_EL1_VARIANT_MASK |
188
+ R_MIDR_EL1_IMPLEMENTER_MASK },
189
+ { .name = "REVIDR_EL1" },
190
};
191
modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
192
#endif
193
diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c
194
index XXXXXXX..XXXXXXX 100644
195
--- a/tests/tcg/aarch64/sysregs.c
196
+++ b/tests/tcg/aarch64/sysregs.c
197
@@ -XXX,XX +XXX,XX @@
198
#define HWCAP_CPUID (1 << 11)
199
#endif
200
201
+/*
202
+ * Older assemblers don't recognize newer system register names,
203
+ * but we can still access them by the Sn_n_Cn_Cn_n syntax.
204
+ */
205
+#define SYS_ID_AA64ISAR2_EL1 S3_0_C0_C6_2
206
+#define SYS_ID_AA64MMFR2_EL1 S3_0_C0_C7_2
207
+
208
int failed_bit_count;
209
210
/* Read and print system register `id' value */
211
@@ -XXX,XX +XXX,XX @@ int main(void)
212
* minimum valid fields - for the purposes of this check allowed
213
* to have non-zero values.
214
*/
215
- get_cpu_reg_check_mask(id_aa64isar0_el1, _m(00ff,ffff,f0ff,fff0));
216
- get_cpu_reg_check_mask(id_aa64isar1_el1, _m(0000,00f0,ffff,ffff));
217
+ get_cpu_reg_check_mask(id_aa64isar0_el1, _m(f0ff,ffff,f0ff,fff0));
218
+ get_cpu_reg_check_mask(id_aa64isar1_el1, _m(00ff,f0ff,ffff,ffff));
219
+ get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(0000,0000,0000,ffff));
220
/* TGran4 & TGran64 as pegged to -1 */
221
- get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(0000,0000,ff00,0000));
222
- get_cpu_reg_check_zero(id_aa64mmfr1_el1);
223
+ get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(f000,0000,ff00,0000));
224
+ get_cpu_reg_check_mask(id_aa64mmfr1_el1, _m(0000,f000,0000,0000));
225
+ get_cpu_reg_check_mask(SYS_ID_AA64MMFR2_EL1, _m(0000,000f,0000,0000));
226
/* EL1/EL0 reported as AA64 only */
227
get_cpu_reg_check_mask(id_aa64pfr0_el1, _m(000f,000f,00ff,0011));
228
- get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0000,00f0));
229
+ get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0f00,0fff));
230
/* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */
231
get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006));
232
get_cpu_reg_check_zero(id_aa64dfr1_el1);
233
- get_cpu_reg_check_zero(id_aa64zfr0_el1);
234
+ get_cpu_reg_check_mask(id_aa64zfr0_el1, _m(0ff0,ff0f,00ff,00ff));
235
+#ifdef HAS_ARMV9_SME
236
+ get_cpu_reg_check_mask(id_aa64smfr0_el1, _m(80f1,00fd,0000,0000));
237
+#endif
238
239
get_cpu_reg_check_zero(id_aa64afr0_el1);
240
get_cpu_reg_check_zero(id_aa64afr1_el1);
241
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
242
index XXXXXXX..XXXXXXX 100644
243
--- a/tests/tcg/aarch64/Makefile.target
244
+++ b/tests/tcg/aarch64/Makefile.target
245
@@ -XXX,XX +XXX,XX @@ config-cc.mak: Makefile
246
     $(call cc-option,-march=armv8.1-a+sve2, CROSS_CC_HAS_SVE2); \
247
     $(call cc-option,-march=armv8.3-a, CROSS_CC_HAS_ARMV8_3); \
248
     $(call cc-option,-mbranch-protection=standard, CROSS_CC_HAS_ARMV8_BTI); \
249
-     $(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE)) 3> config-cc.mak
250
+     $(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE); \
251
+     $(call cc-option,-march=armv9-a+sme, CROSS_CC_HAS_ARMV9_SME)) 3> config-cc.mak
252
-include config-cc.mak
253
254
# Pauth Tests
255
@@ -XXX,XX +XXX,XX @@ endif
256
ifneq ($(CROSS_CC_HAS_SVE),)
257
# System Registers Tests
258
AARCH64_TESTS += sysregs
259
+ifneq ($(CROSS_CC_HAS_ARMV9_SME),)
260
+sysregs: CFLAGS+=-march=armv9-a+sme -DHAS_ARMV9_SME
261
+else
262
sysregs: CFLAGS+=-march=armv8.1-a+sve
263
+endif
264
265
# SVE ioctl test
266
AARCH64_TESTS += sve-ioctls
267
--
268
2.25.1
diff view generated by jsdifflib
[PULL 18/22] pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init()
[PULL 28/34] hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope
1
Rename the pci_root_bus_new_inplace() function to
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
pci_root_bus_init(); this brings the bus type in to line with a
3
"_init for in-place init, _new for allocate-and-return" convention.
4
To do this we need to rename the implementation-internal function
5
that was using the pci_root_bus_init() name to
6
pci_root_bus_internal_init().
7
2
3
This function is not used anywhere outside this file,
4
so we can make the function "static void".
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Message-id: 20221216214924.4711-2-philmd@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
11
Message-id: 20210923121153.23754-4-peter.maydell@linaro.org
12
---
11
---
13
include/hw/pci/pci.h | 10 +++++-----
12
include/hw/arm/smmu-common.h | 3 ---
14
hw/pci-host/raven.c | 4 ++--
13
hw/arm/smmu-common.c | 2 +-
15
hw/pci-host/versatile.c | 6 +++---
14
2 files changed, 1 insertion(+), 4 deletions(-)
16
hw/pci/pci.c | 26 +++++++++++++-------------
17
4 files changed, 23 insertions(+), 23 deletions(-)
18
15
19
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
16
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
20
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/pci/pci.h
18
--- a/include/hw/arm/smmu-common.h
22
+++ b/include/hw/pci/pci.h
19
+++ b/include/hw/arm/smmu-common.h
23
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
20
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
24
21
/* Unmap the range of all the notifiers registered to any IOMMU mr */
25
bool pci_bus_is_express(PCIBus *bus);
22
void smmu_inv_notifiers_all(SMMUState *s);
26
23
27
-void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
24
-/* Unmap the range of all the notifiers registered to @mr */
28
- const char *name,
25
-void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr);
29
- MemoryRegion *address_space_mem,
26
-
30
- MemoryRegion *address_space_io,
27
#endif /* HW_ARM_SMMU_COMMON_H */
31
- uint8_t devfn_min, const char *typename);
28
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
32
+void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
33
+ const char *name,
34
+ MemoryRegion *address_space_mem,
35
+ MemoryRegion *address_space_io,
36
+ uint8_t devfn_min, const char *typename);
37
PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
38
MemoryRegion *address_space_mem,
39
MemoryRegion *address_space_io,
40
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
41
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/pci-host/raven.c
30
--- a/hw/arm/smmu-common.c
43
+++ b/hw/pci-host/raven.c
31
+++ b/hw/arm/smmu-common.c
44
@@ -XXX,XX +XXX,XX @@ static void raven_pcihost_initfn(Object *obj)
32
@@ -XXX,XX +XXX,XX @@ static void smmu_unmap_notifier_range(IOMMUNotifier *n)
45
memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR,
46
&s->pci_io_non_contiguous, 1);
47
memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
48
- pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
49
- &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
50
+ pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
51
+ &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
52
53
/* Bus master address space */
54
memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB);
55
diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/pci-host/versatile.c
58
+++ b/hw/pci-host/versatile.c
59
@@ -XXX,XX +XXX,XX @@ static void pci_vpb_realize(DeviceState *dev, Error **errp)
60
memory_region_init(&s->pci_io_space, OBJECT(s), "pci_io", 4 * GiB);
61
memory_region_init(&s->pci_mem_space, OBJECT(s), "pci_mem", 4 * GiB);
62
63
- pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), dev, "pci",
64
- &s->pci_mem_space, &s->pci_io_space,
65
- PCI_DEVFN(11, 0), TYPE_PCI_BUS);
66
+ pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), dev, "pci",
67
+ &s->pci_mem_space, &s->pci_io_space,
68
+ PCI_DEVFN(11, 0), TYPE_PCI_BUS);
69
h->bus = &s->pci_bus;
70
71
object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_VERSATILE_PCI_HOST);
72
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/pci/pci.c
75
+++ b/hw/pci/pci.c
76
@@ -XXX,XX +XXX,XX @@ bool pci_bus_bypass_iommu(PCIBus *bus)
77
return host_bridge->bypass_iommu;
78
}
33
}
79
34
80
-static void pci_root_bus_init(PCIBus *bus, DeviceState *parent,
35
/* Unmap all notifiers attached to @mr */
81
- MemoryRegion *address_space_mem,
36
-inline void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
82
- MemoryRegion *address_space_io,
37
+static void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
83
- uint8_t devfn_min)
84
+static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent,
85
+ MemoryRegion *address_space_mem,
86
+ MemoryRegion *address_space_io,
87
+ uint8_t devfn_min)
88
{
38
{
89
assert(PCI_FUNC(devfn_min) == 0);
39
IOMMUNotifier *n;
90
bus->devfn_min = devfn_min;
91
@@ -XXX,XX +XXX,XX @@ bool pci_bus_is_express(PCIBus *bus)
92
return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
93
}
94
95
-void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
96
- const char *name,
97
- MemoryRegion *address_space_mem,
98
- MemoryRegion *address_space_io,
99
- uint8_t devfn_min, const char *typename)
100
+void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
101
+ const char *name,
102
+ MemoryRegion *address_space_mem,
103
+ MemoryRegion *address_space_io,
104
+ uint8_t devfn_min, const char *typename)
105
{
106
qbus_create_inplace(bus, bus_size, typename, parent, name);
107
- pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
108
- devfn_min);
109
+ pci_root_bus_internal_init(bus, parent, address_space_mem,
110
+ address_space_io, devfn_min);
111
}
112
113
PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
114
@@ -XXX,XX +XXX,XX @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
115
PCIBus *bus;
116
117
bus = PCI_BUS(qbus_create(typename, parent, name));
118
- pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
119
- devfn_min);
120
+ pci_root_bus_internal_init(bus, parent, address_space_mem,
121
+ address_space_io, devfn_min);
122
return bus;
123
}
124
40
125
--
41
--
126
2.20.1
42
2.25.1
127
43
128
44
diff view generated by jsdifflib
[PULL 08/22] hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device
[PULL 29/34] hw/arm/smmu-common: Avoid using inlined functions with external linkage
1
From: Tong Ho <tong.ho@xilinx.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Connect the support for Versal eFUSE one-time field-programmable
3
When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)")
4
bit array.
4
and building with -Wall we get:
5
5
6
The command argument:
6
hw/arm/smmu-common.c:173:33: warning: static function 'smmu_hash_remove_by_asid_iova' is used in an inline function with external linkage [-Wstatic-in-inline]
7
-drive if=pflash,index=1,...
7
hw/arm/smmu-common.h:170:1: note: use 'static' to give inline function 'smmu_iotlb_inv_iova' internal linkage
8
Can be used to optionally connect the bit array to a
8
void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
9
backend storage, such that field-programmed values
9
^
10
in one invocation can be made available to next
10
static
11
invocation.
12
11
13
The backend storage must be a seekable binary file, and
12
None of our code base require / use inlined functions with external
14
its size must be 3072 bytes or larger. A file with all
13
linkage. Some places use internal inlining in the hot path. These
15
binary 0's is a 'blank'.
14
two functions are certainly not in any hot path and don't justify
15
any inlining, so these are likely oversights rather than intentional.
16
16
17
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
17
Reported-by: Stefan Weil <sw@weilnetz.de>
18
Message-id: 20210917052400.1249094-7-tong.ho@xilinx.com
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Reviewed-by: Eric Auger <eric.auger@redhat.com>
22
Message-id: 20221216214924.4711-3-philmd@linaro.org
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
24
---
22
include/hw/arm/xlnx-versal.h | 10 +++++++
25
hw/arm/smmu-common.c | 13 ++++++-------
23
hw/arm/xlnx-versal-virt.c | 52 ++++++++++++++++++++++++++++++++++++
26
1 file changed, 6 insertions(+), 7 deletions(-)
24
hw/arm/xlnx-versal.c | 39 +++++++++++++++++++++++++++
25
hw/arm/Kconfig | 1 +
26
4 files changed, 102 insertions(+)
27
27
28
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
28
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
29
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/xlnx-versal.h
30
--- a/hw/arm/smmu-common.c
31
+++ b/include/hw/arm/xlnx-versal.h
31
+++ b/hw/arm/smmu-common.c
32
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new)
33
#include "hw/usb/xlnx-usb-subsystem.h"
33
g_hash_table_insert(bs->iotlb, key, new);
34
#include "hw/misc/xlnx-versal-xramc.h"
35
#include "hw/nvram/xlnx-bbram.h"
36
+#include "hw/nvram/xlnx-versal-efuse.h"
37
38
#define TYPE_XLNX_VERSAL "xlnx-versal"
39
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
40
@@ -XXX,XX +XXX,XX @@ struct Versal {
41
42
XlnxZynqMPRTC rtc;
43
XlnxBBRam bbram;
44
+ XlnxEFuse efuse;
45
+ XlnxVersalEFuseCtrl efuse_ctrl;
46
+ XlnxVersalEFuseCache efuse_cache;
47
} pmc;
48
49
struct {
50
@@ -XXX,XX +XXX,XX @@ struct Versal {
51
#define VERSAL_BBRAM_APB_IRQ_0 121
52
#define VERSAL_RTC_APB_ERR_IRQ 121
53
#define VERSAL_SD0_IRQ_0 126
54
+#define VERSAL_EFUSE_IRQ 139
55
#define VERSAL_RTC_ALARM_IRQ 142
56
#define VERSAL_RTC_SECONDS_IRQ 143
57
58
@@ -XXX,XX +XXX,XX @@ struct Versal {
59
#define MM_PMC_SD0_SIZE 0x10000
60
#define MM_PMC_BBRAM_CTRL 0xf11f0000
61
#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
62
+#define MM_PMC_EFUSE_CTRL 0xf1240000
63
+#define MM_PMC_EFUSE_CTRL_SIZE 0x00104
64
+#define MM_PMC_EFUSE_CACHE 0xf1250000
65
+#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00
66
+
67
#define MM_PMC_CRP 0xf1260000U
68
#define MM_PMC_CRP_SIZE 0x10000
69
#define MM_PMC_RTC 0xf12a0000
70
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/xlnx-versal-virt.c
73
+++ b/hw/arm/xlnx-versal-virt.c
74
@@ -XXX,XX +XXX,XX @@ static void fdt_add_bbram_node(VersalVirt *s)
75
g_free(name);
76
}
34
}
77
35
78
+static void fdt_add_efuse_ctrl_node(VersalVirt *s)
36
-inline void smmu_iotlb_inv_all(SMMUState *s)
79
+{
37
+void smmu_iotlb_inv_all(SMMUState *s)
80
+ const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CTRL;
81
+ const char interrupt_names[] = "pmc_efuse";
82
+ char *name = g_strdup_printf("/pmc_efuse@%x", MM_PMC_EFUSE_CTRL);
83
+
84
+ qemu_fdt_add_subnode(s->fdt, name);
85
+
86
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
87
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_EFUSE_IRQ,
88
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
89
+ qemu_fdt_setprop(s->fdt, name, "interrupt-names",
90
+ interrupt_names, sizeof(interrupt_names));
91
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
92
+ 2, MM_PMC_EFUSE_CTRL,
93
+ 2, MM_PMC_EFUSE_CTRL_SIZE);
94
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
95
+ g_free(name);
96
+}
97
+
98
+static void fdt_add_efuse_cache_node(VersalVirt *s)
99
+{
100
+ const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CACHE;
101
+ char *name = g_strdup_printf("/xlnx_pmc_efuse_cache@%x",
102
+ MM_PMC_EFUSE_CACHE);
103
+
104
+ qemu_fdt_add_subnode(s->fdt, name);
105
+
106
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
107
+ 2, MM_PMC_EFUSE_CACHE,
108
+ 2, MM_PMC_EFUSE_CACHE_SIZE);
109
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
110
+ g_free(name);
111
+}
112
+
113
static void fdt_nop_memory_nodes(void *fdt, Error **errp)
114
{
38
{
115
Error *err = NULL;
39
trace_smmu_iotlb_inv_all();
116
@@ -XXX,XX +XXX,XX @@ static void bbram_attach_drive(XlnxBBRam *dev)
40
g_hash_table_remove_all(s->iotlb);
117
}
41
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,
42
((entry->iova & ~info->mask) == info->iova);
118
}
43
}
119
44
120
+static void efuse_attach_drive(XlnxEFuse *dev)
45
-inline void
121
+{
46
-smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
122
+ DriveInfo *dinfo;
47
- uint8_t tg, uint64_t num_pages, uint8_t ttl)
123
+ BlockBackend *blk;
48
+void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
124
+
49
+ uint8_t tg, uint64_t num_pages, uint8_t ttl)
125
+ dinfo = drive_get_by_index(IF_PFLASH, 1);
126
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
127
+ if (blk) {
128
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
129
+ }
130
+}
131
+
132
static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
133
{
50
{
134
BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
51
/* if tg is not set we use 4KB range invalidation */
135
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
52
uint8_t granule = tg ? tg * 2 + 10 : 12;
136
fdt_add_sd_nodes(s);
53
@@ -XXX,XX +XXX,XX @@ smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
137
fdt_add_rtc_node(s);
54
&info);
138
fdt_add_bbram_node(s);
139
+ fdt_add_efuse_ctrl_node(s);
140
+ fdt_add_efuse_cache_node(s);
141
fdt_add_cpu_nodes(s, psci_conduit);
142
fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
143
fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
144
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
145
/* Attach bbram backend, if given */
146
bbram_attach_drive(&s->soc.pmc.bbram);
147
148
+ /* Attach efuse backend, if given */
149
+ efuse_attach_drive(&s->soc.pmc.efuse);
150
+
151
/* Plugin SD cards. */
152
for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
153
sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
154
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
155
index XXXXXXX..XXXXXXX 100644
156
--- a/hw/arm/xlnx-versal.c
157
+++ b/hw/arm/xlnx-versal.c
158
@@ -XXX,XX +XXX,XX @@ static void versal_create_bbram(Versal *s, qemu_irq *pic)
159
sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]);
160
}
55
}
161
56
162
+static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base)
57
-inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
163
+{
58
+void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
164
+ SysBusDevice *part = SYS_BUS_DEVICE(dev);
59
{
165
+
60
trace_smmu_iotlb_inv_asid(asid);
166
+ object_property_set_link(OBJECT(part), "efuse",
61
g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid);
167
+ OBJECT(&s->pmc.efuse), &error_abort);
62
@@ -XXX,XX +XXX,XX @@ error:
168
+
63
*
169
+ sysbus_realize(part, &error_abort);
64
* return 0 on success
170
+ memory_region_add_subregion(&s->mr_ps, base,
171
+ sysbus_mmio_get_region(part, 0));
172
+}
173
+
174
+static void versal_create_efuse(Versal *s, qemu_irq *pic)
175
+{
176
+ Object *bits = OBJECT(&s->pmc.efuse);
177
+ Object *ctrl = OBJECT(&s->pmc.efuse_ctrl);
178
+ Object *cache = OBJECT(&s->pmc.efuse_cache);
179
+
180
+ object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl,
181
+ TYPE_XLNX_VERSAL_EFUSE_CTRL);
182
+
183
+ object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache,
184
+ TYPE_XLNX_VERSAL_EFUSE_CACHE);
185
+
186
+ object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits,
187
+ sizeof(s->pmc.efuse),
188
+ TYPE_XLNX_EFUSE, &error_abort,
189
+ "efuse-nr", "3",
190
+ "efuse-size", "8192",
191
+ NULL);
192
+
193
+ qdev_realize(DEVICE(bits), NULL, &error_abort);
194
+ versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL);
195
+ versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE);
196
+
197
+ sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]);
198
+}
199
+
200
/* This takes the board allocated linear DDR memory and creates aliases
201
* for each split DDR range/aperture on the Versal address map.
202
*/
65
*/
203
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
66
-inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
204
versal_create_rtc(s, pic);
67
- SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
205
versal_create_xrams(s, pic);
68
+int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
206
versal_create_bbram(s, pic);
69
+ SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
207
+ versal_create_efuse(s, pic);
70
{
208
versal_map_ddr(s);
71
if (!cfg->aa64) {
209
versal_unimp(s);
72
/*
210
211
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
212
index XXXXXXX..XXXXXXX 100644
213
--- a/hw/arm/Kconfig
214
+++ b/hw/arm/Kconfig
215
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
216
select XLNX_ZYNQMP
217
select OR_IRQ
218
select XLNX_BBRAM
219
+ select XLNX_EFUSE_VERSAL
220
221
config NPCM7XX
222
bool
223
--
73
--
224
2.20.1
74
2.25.1
225
75
226
76
diff view generated by jsdifflib
New patch
[PULL 30/34] i.MX7D: Connect GPT timers to IRQ
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
2
3
So far the GPT timers were unable to raise IRQs to the processor.
4
5
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
include/hw/arm/fsl-imx7.h | 5 +++++
10
hw/arm/fsl-imx7.c | 10 ++++++++++
11
2 files changed, 15 insertions(+)
12
13
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/fsl-imx7.h
16
+++ b/include/hw/arm/fsl-imx7.h
17
@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
18
FSL_IMX7_USB2_IRQ = 42,
19
FSL_IMX7_USB3_IRQ = 40,
20
21
+ FSL_IMX7_GPT1_IRQ = 55,
22
+ FSL_IMX7_GPT2_IRQ = 54,
23
+ FSL_IMX7_GPT3_IRQ = 53,
24
+ FSL_IMX7_GPT4_IRQ = 52,
25
+
26
FSL_IMX7_WDOG1_IRQ = 78,
27
FSL_IMX7_WDOG2_IRQ = 79,
28
FSL_IMX7_WDOG3_IRQ = 10,
29
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/fsl-imx7.c
32
+++ b/hw/arm/fsl-imx7.c
33
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
34
FSL_IMX7_GPT4_ADDR,
35
};
36
37
+ static const int FSL_IMX7_GPTn_IRQ[FSL_IMX7_NUM_GPTS] = {
38
+ FSL_IMX7_GPT1_IRQ,
39
+ FSL_IMX7_GPT2_IRQ,
40
+ FSL_IMX7_GPT3_IRQ,
41
+ FSL_IMX7_GPT4_IRQ,
42
+ };
43
+
44
s->gpt[i].ccm = IMX_CCM(&s->ccm);
45
sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
46
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
47
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
48
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
49
+ FSL_IMX7_GPTn_IRQ[i]));
50
}
51
52
for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
53
--
54
2.25.1
diff view generated by jsdifflib
[PULL 05/22] hw/nvram: Introduce Xilinx ZynqMP eFuse device
[PULL 31/34] i.MX7D: Compute clock frequency for the fixed frequency clocks.
1
From: Tong Ho <tong.ho@xilinx.com>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
This implements the Xilinx ZynqMP eFuse, an one-time
3
CCM derived clocks will have to be added later.
4
field-programmable non-volatile storage device. There is
5
only one such device in the Xilinx ZynqMP product family.
6
4
7
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
5
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
8
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
9
10
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
12
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
13
Message-id: 20210917052400.1249094-4-tong.ho@xilinx.com
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
8
---
17
include/hw/nvram/xlnx-zynqmp-efuse.h | 44 ++
9
hw/misc/imx7_ccm.c | 49 +++++++++++++++++++++++++++++++++++++---------
18
hw/nvram/xlnx-zynqmp-efuse.c | 855 +++++++++++++++++++++++++++
10
1 file changed, 40 insertions(+), 9 deletions(-)
19
hw/nvram/Kconfig | 4 +
20
hw/nvram/meson.build | 2 +
21
4 files changed, 905 insertions(+)
22
create mode 100644 include/hw/nvram/xlnx-zynqmp-efuse.h
23
create mode 100644 hw/nvram/xlnx-zynqmp-efuse.c
24
11
25
diff --git a/include/hw/nvram/xlnx-zynqmp-efuse.h b/include/hw/nvram/xlnx-zynqmp-efuse.h
12
diff --git a/hw/misc/imx7_ccm.c b/hw/misc/imx7_ccm.c
26
new file mode 100644
13
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX
14
--- a/hw/misc/imx7_ccm.c
28
--- /dev/null
15
+++ b/hw/misc/imx7_ccm.c
29
+++ b/include/hw/nvram/xlnx-zynqmp-efuse.h
30
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@
31
+/*
17
#include "hw/misc/imx7_ccm.h"
32
+ * Copyright (c) 2021 Xilinx Inc.
18
#include "migration/vmstate.h"
33
+ *
19
34
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
20
+#include "trace.h"
35
+ * of this software and associated documentation files (the "Software"), to deal
36
+ * in the Software without restriction, including without limitation the rights
37
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
38
+ * copies of the Software, and to permit persons to whom the Software is
39
+ * furnished to do so, subject to the following conditions:
40
+ *
41
+ * The above copyright notice and this permission notice shall be included in
42
+ * all copies or substantial portions of the Software.
43
+ *
44
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
45
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
46
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
47
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
48
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
49
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
50
+ * THE SOFTWARE.
51
+ */
52
+#ifndef XLNX_ZYNQMP_EFUSE_H
53
+#define XLNX_ZYNQMP_EFUSE_H
54
+
21
+
55
+#include "hw/irq.h"
22
+#define CKIH_FREQ 24000000 /* 24MHz crystal input */
56
+#include "hw/sysbus.h"
57
+#include "hw/register.h"
58
+#include "hw/nvram/xlnx-efuse.h"
59
+
23
+
60
+#define XLNX_ZYNQMP_EFUSE_R_MAX ((0x10fc / 4) + 1)
24
static void imx7_analog_reset(DeviceState *dev)
25
{
26
IMX7AnalogState *s = IMX7_ANALOG(dev);
27
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx7_ccm = {
28
static uint32_t imx7_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
29
{
30
/*
31
- * This function is "consumed" by GPT emulation code, however on
32
- * i.MX7 each GPT block can have their own clock root. This means
33
- * that this functions needs somehow to know requester's identity
34
- * and the way to pass it: be it via additional IMXClk constants
35
- * or by adding another argument to this method needs to be
36
- * figured out
37
+ * This function is "consumed" by GPT emulation code. Some clocks
38
+ * have fixed frequencies and we can provide requested frequency
39
+ * easily. However for CCM provided clocks (like IPG) each GPT
40
+ * timer can have its own clock root.
41
+ * This means we need additionnal information when calling this
42
+ * function to know the requester's identity.
43
*/
44
- qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Not implemented\n",
45
- TYPE_IMX7_CCM, __func__);
46
- return 0;
47
+ uint32_t freq = 0;
61
+
48
+
62
+#define TYPE_XLNX_ZYNQMP_EFUSE "xlnx,zynqmp-efuse"
49
+ switch (clock) {
63
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPEFuse, XLNX_ZYNQMP_EFUSE);
50
+ case CLK_NONE:
64
+
51
+ break;
65
+struct XlnxZynqMPEFuse {
52
+ case CLK_32k:
66
+ SysBusDevice parent_obj;
53
+ freq = CKIL_FREQ;
67
+ qemu_irq irq;
54
+ break;
68
+
55
+ case CLK_HIGH:
69
+ XlnxEFuse *efuse;
56
+ freq = CKIH_FREQ;
70
+ uint32_t regs[XLNX_ZYNQMP_EFUSE_R_MAX];
57
+ break;
71
+ RegisterInfo regs_info[XLNX_ZYNQMP_EFUSE_R_MAX];
58
+ case CLK_IPG:
72
+};
59
+ case CLK_IPG_HIGH:
73
+
60
+ /*
74
+#endif
61
+ * For now we don't have a way to figure out the device this
75
diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c
62
+ * function is called for. Until then the IPG derived clocks
76
new file mode 100644
63
+ * are left unimplemented.
77
index XXXXXXX..XXXXXXX
64
+ */
78
--- /dev/null
65
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Clock %d Not implemented\n",
79
+++ b/hw/nvram/xlnx-zynqmp-efuse.c
66
+ TYPE_IMX7_CCM, __func__, clock);
80
@@ -XXX,XX +XXX,XX @@
67
+ break;
81
+/*
68
+ default:
82
+ * QEMU model of the ZynqMP eFuse
69
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
83
+ *
70
+ TYPE_IMX7_CCM, __func__, clock);
84
+ * Copyright (c) 2015 Xilinx Inc.
71
+ break;
85
+ *
86
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
87
+ *
88
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
89
+ * of this software and associated documentation files (the "Software"), to deal
90
+ * in the Software without restriction, including without limitation the rights
91
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
92
+ * copies of the Software, and to permit persons to whom the Software is
93
+ * furnished to do so, subject to the following conditions:
94
+ *
95
+ * The above copyright notice and this permission notice shall be included in
96
+ * all copies or substantial portions of the Software.
97
+ *
98
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
99
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
100
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
101
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
102
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
103
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
104
+ * THE SOFTWARE.
105
+ */
106
+
107
+#include "qemu/osdep.h"
108
+#include "hw/nvram/xlnx-zynqmp-efuse.h"
109
+
110
+#include "qemu/log.h"
111
+#include "qapi/error.h"
112
+#include "migration/vmstate.h"
113
+#include "hw/qdev-properties.h"
114
+
115
+#ifndef ZYNQMP_EFUSE_ERR_DEBUG
116
+#define ZYNQMP_EFUSE_ERR_DEBUG 0
117
+#endif
118
+
119
+REG32(WR_LOCK, 0x0)
120
+ FIELD(WR_LOCK, LOCK, 0, 16)
121
+REG32(CFG, 0x4)
122
+ FIELD(CFG, SLVERR_ENABLE, 5, 1)
123
+ FIELD(CFG, MARGIN_RD, 2, 2)
124
+ FIELD(CFG, PGM_EN, 1, 1)
125
+ FIELD(CFG, EFUSE_CLK_SEL, 0, 1)
126
+REG32(STATUS, 0x8)
127
+ FIELD(STATUS, AES_CRC_PASS, 7, 1)
128
+ FIELD(STATUS, AES_CRC_DONE, 6, 1)
129
+ FIELD(STATUS, CACHE_DONE, 5, 1)
130
+ FIELD(STATUS, CACHE_LOAD, 4, 1)
131
+ FIELD(STATUS, EFUSE_3_TBIT, 2, 1)
132
+ FIELD(STATUS, EFUSE_2_TBIT, 1, 1)
133
+ FIELD(STATUS, EFUSE_0_TBIT, 0, 1)
134
+REG32(EFUSE_PGM_ADDR, 0xc)
135
+ FIELD(EFUSE_PGM_ADDR, EFUSE, 11, 2)
136
+ FIELD(EFUSE_PGM_ADDR, ROW, 5, 6)
137
+ FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5)
138
+REG32(EFUSE_RD_ADDR, 0x10)
139
+ FIELD(EFUSE_RD_ADDR, EFUSE, 11, 2)
140
+ FIELD(EFUSE_RD_ADDR, ROW, 5, 6)
141
+REG32(EFUSE_RD_DATA, 0x14)
142
+REG32(TPGM, 0x18)
143
+ FIELD(TPGM, VALUE, 0, 16)
144
+REG32(TRD, 0x1c)
145
+ FIELD(TRD, VALUE, 0, 8)
146
+REG32(TSU_H_PS, 0x20)
147
+ FIELD(TSU_H_PS, VALUE, 0, 8)
148
+REG32(TSU_H_PS_CS, 0x24)
149
+ FIELD(TSU_H_PS_CS, VALUE, 0, 8)
150
+REG32(TSU_H_CS, 0x2c)
151
+ FIELD(TSU_H_CS, VALUE, 0, 4)
152
+REG32(EFUSE_ISR, 0x30)
153
+ FIELD(EFUSE_ISR, APB_SLVERR, 31, 1)
154
+ FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1)
155
+ FIELD(EFUSE_ISR, RD_ERROR, 3, 1)
156
+ FIELD(EFUSE_ISR, RD_DONE, 2, 1)
157
+ FIELD(EFUSE_ISR, PGM_ERROR, 1, 1)
158
+ FIELD(EFUSE_ISR, PGM_DONE, 0, 1)
159
+REG32(EFUSE_IMR, 0x34)
160
+ FIELD(EFUSE_IMR, APB_SLVERR, 31, 1)
161
+ FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1)
162
+ FIELD(EFUSE_IMR, RD_ERROR, 3, 1)
163
+ FIELD(EFUSE_IMR, RD_DONE, 2, 1)
164
+ FIELD(EFUSE_IMR, PGM_ERROR, 1, 1)
165
+ FIELD(EFUSE_IMR, PGM_DONE, 0, 1)
166
+REG32(EFUSE_IER, 0x38)
167
+ FIELD(EFUSE_IER, APB_SLVERR, 31, 1)
168
+ FIELD(EFUSE_IER, CACHE_ERROR, 4, 1)
169
+ FIELD(EFUSE_IER, RD_ERROR, 3, 1)
170
+ FIELD(EFUSE_IER, RD_DONE, 2, 1)
171
+ FIELD(EFUSE_IER, PGM_ERROR, 1, 1)
172
+ FIELD(EFUSE_IER, PGM_DONE, 0, 1)
173
+REG32(EFUSE_IDR, 0x3c)
174
+ FIELD(EFUSE_IDR, APB_SLVERR, 31, 1)
175
+ FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1)
176
+ FIELD(EFUSE_IDR, RD_ERROR, 3, 1)
177
+ FIELD(EFUSE_IDR, RD_DONE, 2, 1)
178
+ FIELD(EFUSE_IDR, PGM_ERROR, 1, 1)
179
+ FIELD(EFUSE_IDR, PGM_DONE, 0, 1)
180
+REG32(EFUSE_CACHE_LOAD, 0x40)
181
+ FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1)
182
+REG32(EFUSE_PGM_LOCK, 0x44)
183
+ FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1)
184
+REG32(EFUSE_AES_CRC, 0x48)
185
+REG32(EFUSE_TBITS_PRGRMG_EN, 0x100)
186
+ FIELD(EFUSE_TBITS_PRGRMG_EN, TBITS_PRGRMG_EN, 3, 1)
187
+REG32(DNA_0, 0x100c)
188
+REG32(DNA_1, 0x1010)
189
+REG32(DNA_2, 0x1014)
190
+REG32(IPDISABLE, 0x1018)
191
+ FIELD(IPDISABLE, VCU_DIS, 8, 1)
192
+ FIELD(IPDISABLE, GPU_DIS, 5, 1)
193
+ FIELD(IPDISABLE, APU3_DIS, 3, 1)
194
+ FIELD(IPDISABLE, APU2_DIS, 2, 1)
195
+ FIELD(IPDISABLE, APU1_DIS, 1, 1)
196
+ FIELD(IPDISABLE, APU0_DIS, 0, 1)
197
+REG32(SYSOSC_CTRL, 0x101c)
198
+ FIELD(SYSOSC_CTRL, SYSOSC_EN, 0, 1)
199
+REG32(USER_0, 0x1020)
200
+REG32(USER_1, 0x1024)
201
+REG32(USER_2, 0x1028)
202
+REG32(USER_3, 0x102c)
203
+REG32(USER_4, 0x1030)
204
+REG32(USER_5, 0x1034)
205
+REG32(USER_6, 0x1038)
206
+REG32(USER_7, 0x103c)
207
+REG32(MISC_USER_CTRL, 0x1040)
208
+ FIELD(MISC_USER_CTRL, FPD_SC_EN_0, 14, 1)
209
+ FIELD(MISC_USER_CTRL, LPD_SC_EN_0, 11, 1)
210
+ FIELD(MISC_USER_CTRL, LBIST_EN, 10, 1)
211
+ FIELD(MISC_USER_CTRL, USR_WRLK_7, 7, 1)
212
+ FIELD(MISC_USER_CTRL, USR_WRLK_6, 6, 1)
213
+ FIELD(MISC_USER_CTRL, USR_WRLK_5, 5, 1)
214
+ FIELD(MISC_USER_CTRL, USR_WRLK_4, 4, 1)
215
+ FIELD(MISC_USER_CTRL, USR_WRLK_3, 3, 1)
216
+ FIELD(MISC_USER_CTRL, USR_WRLK_2, 2, 1)
217
+ FIELD(MISC_USER_CTRL, USR_WRLK_1, 1, 1)
218
+ FIELD(MISC_USER_CTRL, USR_WRLK_0, 0, 1)
219
+REG32(ROM_RSVD, 0x1044)
220
+ FIELD(ROM_RSVD, PBR_BOOT_ERROR, 0, 3)
221
+REG32(PUF_CHASH, 0x1050)
222
+REG32(PUF_MISC, 0x1054)
223
+ FIELD(PUF_MISC, REGISTER_DIS, 31, 1)
224
+ FIELD(PUF_MISC, SYN_WRLK, 30, 1)
225
+ FIELD(PUF_MISC, SYN_INVLD, 29, 1)
226
+ FIELD(PUF_MISC, TEST2_DIS, 28, 1)
227
+ FIELD(PUF_MISC, UNUSED27, 27, 1)
228
+ FIELD(PUF_MISC, UNUSED26, 26, 1)
229
+ FIELD(PUF_MISC, UNUSED25, 25, 1)
230
+ FIELD(PUF_MISC, UNUSED24, 24, 1)
231
+ FIELD(PUF_MISC, AUX, 0, 24)
232
+REG32(SEC_CTRL, 0x1058)
233
+ FIELD(SEC_CTRL, PPK1_INVLD, 30, 2)
234
+ FIELD(SEC_CTRL, PPK1_WRLK, 29, 1)
235
+ FIELD(SEC_CTRL, PPK0_INVLD, 27, 2)
236
+ FIELD(SEC_CTRL, PPK0_WRLK, 26, 1)
237
+ FIELD(SEC_CTRL, RSA_EN, 11, 15)
238
+ FIELD(SEC_CTRL, SEC_LOCK, 10, 1)
239
+ FIELD(SEC_CTRL, PROG_GATE_2, 9, 1)
240
+ FIELD(SEC_CTRL, PROG_GATE_1, 8, 1)
241
+ FIELD(SEC_CTRL, PROG_GATE_0, 7, 1)
242
+ FIELD(SEC_CTRL, DFT_DIS, 6, 1)
243
+ FIELD(SEC_CTRL, JTAG_DIS, 5, 1)
244
+ FIELD(SEC_CTRL, ERROR_DIS, 4, 1)
245
+ FIELD(SEC_CTRL, BBRAM_DIS, 3, 1)
246
+ FIELD(SEC_CTRL, ENC_ONLY, 2, 1)
247
+ FIELD(SEC_CTRL, AES_WRLK, 1, 1)
248
+ FIELD(SEC_CTRL, AES_RDLK, 0, 1)
249
+REG32(SPK_ID, 0x105c)
250
+REG32(PPK0_0, 0x10a0)
251
+REG32(PPK0_1, 0x10a4)
252
+REG32(PPK0_2, 0x10a8)
253
+REG32(PPK0_3, 0x10ac)
254
+REG32(PPK0_4, 0x10b0)
255
+REG32(PPK0_5, 0x10b4)
256
+REG32(PPK0_6, 0x10b8)
257
+REG32(PPK0_7, 0x10bc)
258
+REG32(PPK0_8, 0x10c0)
259
+REG32(PPK0_9, 0x10c4)
260
+REG32(PPK0_10, 0x10c8)
261
+REG32(PPK0_11, 0x10cc)
262
+REG32(PPK1_0, 0x10d0)
263
+REG32(PPK1_1, 0x10d4)
264
+REG32(PPK1_2, 0x10d8)
265
+REG32(PPK1_3, 0x10dc)
266
+REG32(PPK1_4, 0x10e0)
267
+REG32(PPK1_5, 0x10e4)
268
+REG32(PPK1_6, 0x10e8)
269
+REG32(PPK1_7, 0x10ec)
270
+REG32(PPK1_8, 0x10f0)
271
+REG32(PPK1_9, 0x10f4)
272
+REG32(PPK1_10, 0x10f8)
273
+REG32(PPK1_11, 0x10fc)
274
+
275
+#define BIT_POS(ROW, COLUMN) (ROW * 32 + COLUMN)
276
+#define R_MAX (R_PPK1_11 + 1)
277
+
278
+/* #define EFUSE_XOSC 26 */
279
+
280
+/*
281
+ * eFUSE layout references:
282
+ * ZynqMP: UG1085 (v2.1) August 21, 2019, p.277, Table 12-13
283
+ */
284
+#define EFUSE_AES_RDLK BIT_POS(22, 0)
285
+#define EFUSE_AES_WRLK BIT_POS(22, 1)
286
+#define EFUSE_ENC_ONLY BIT_POS(22, 2)
287
+#define EFUSE_BBRAM_DIS BIT_POS(22, 3)
288
+#define EFUSE_ERROR_DIS BIT_POS(22, 4)
289
+#define EFUSE_JTAG_DIS BIT_POS(22, 5)
290
+#define EFUSE_DFT_DIS BIT_POS(22, 6)
291
+#define EFUSE_PROG_GATE_0 BIT_POS(22, 7)
292
+#define EFUSE_PROG_GATE_1 BIT_POS(22, 7)
293
+#define EFUSE_PROG_GATE_2 BIT_POS(22, 9)
294
+#define EFUSE_SEC_LOCK BIT_POS(22, 10)
295
+#define EFUSE_RSA_EN BIT_POS(22, 11)
296
+#define EFUSE_RSA_EN14 BIT_POS(22, 25)
297
+#define EFUSE_PPK0_WRLK BIT_POS(22, 26)
298
+#define EFUSE_PPK0_INVLD BIT_POS(22, 27)
299
+#define EFUSE_PPK0_INVLD_1 BIT_POS(22, 28)
300
+#define EFUSE_PPK1_WRLK BIT_POS(22, 29)
301
+#define EFUSE_PPK1_INVLD BIT_POS(22, 30)
302
+#define EFUSE_PPK1_INVLD_1 BIT_POS(22, 31)
303
+
304
+/* Areas. */
305
+#define EFUSE_TRIM_START BIT_POS(1, 0)
306
+#define EFUSE_TRIM_END BIT_POS(1, 30)
307
+#define EFUSE_DNA_START BIT_POS(3, 0)
308
+#define EFUSE_DNA_END BIT_POS(5, 31)
309
+#define EFUSE_AES_START BIT_POS(24, 0)
310
+#define EFUSE_AES_END BIT_POS(31, 31)
311
+#define EFUSE_ROM_START BIT_POS(17, 0)
312
+#define EFUSE_ROM_END BIT_POS(17, 31)
313
+#define EFUSE_IPDIS_START BIT_POS(6, 0)
314
+#define EFUSE_IPDIS_END BIT_POS(6, 31)
315
+#define EFUSE_USER_START BIT_POS(8, 0)
316
+#define EFUSE_USER_END BIT_POS(15, 31)
317
+#define EFUSE_BISR_START BIT_POS(32, 0)
318
+#define EFUSE_BISR_END BIT_POS(39, 31)
319
+
320
+#define EFUSE_USER_CTRL_START BIT_POS(16, 0)
321
+#define EFUSE_USER_CTRL_END BIT_POS(16, 16)
322
+#define EFUSE_USER_CTRL_MASK ((uint32_t)MAKE_64BIT_MASK(0, 17))
323
+
324
+#define EFUSE_PUF_CHASH_START BIT_POS(20, 0)
325
+#define EFUSE_PUF_CHASH_END BIT_POS(20, 31)
326
+#define EFUSE_PUF_MISC_START BIT_POS(21, 0)
327
+#define EFUSE_PUF_MISC_END BIT_POS(21, 31)
328
+#define EFUSE_PUF_SYN_WRLK BIT_POS(21, 30)
329
+
330
+#define EFUSE_SPK_START BIT_POS(23, 0)
331
+#define EFUSE_SPK_END BIT_POS(23, 31)
332
+
333
+#define EFUSE_PPK0_START BIT_POS(40, 0)
334
+#define EFUSE_PPK0_END BIT_POS(51, 31)
335
+#define EFUSE_PPK1_START BIT_POS(52, 0)
336
+#define EFUSE_PPK1_END BIT_POS(63, 31)
337
+
338
+#define EFUSE_CACHE_FLD(s, reg, field) \
339
+ ARRAY_FIELD_DP32((s)->regs, reg, field, \
340
+ (xlnx_efuse_get_row((s->efuse), EFUSE_ ## field) \
341
+ >> (EFUSE_ ## field % 32)))
342
+
343
+#define EFUSE_CACHE_BIT(s, reg, field) \
344
+ ARRAY_FIELD_DP32((s)->regs, reg, field, xlnx_efuse_get_bit((s->efuse), \
345
+ EFUSE_ ## field))
346
+
347
+#define FBIT_UNKNOWN (~0)
348
+
349
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxZynqMPEFuse *)0)->regs));
350
+
351
+static void update_tbit_status(XlnxZynqMPEFuse *s)
352
+{
353
+ unsigned int check = xlnx_efuse_tbits_check(s->efuse);
354
+ uint32_t val = s->regs[R_STATUS];
355
+
356
+ val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0)));
357
+ val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 1)));
358
+ val = FIELD_DP32(val, STATUS, EFUSE_3_TBIT, !!(check & (1 << 2)));
359
+
360
+ s->regs[R_STATUS] = val;
361
+}
362
+
363
+/* Update the u32 array from efuse bits. Slow but simple approach. */
364
+static void cache_sync_u32(XlnxZynqMPEFuse *s, unsigned int r_start,
365
+ unsigned int f_start, unsigned int f_end,
366
+ unsigned int f_written)
367
+{
368
+ uint32_t *u32 = &s->regs[r_start];
369
+ unsigned int fbit, wbits = 0, u32_off = 0;
370
+
371
+ /* Avoid working on bits that are not relevant. */
372
+ if (f_written != FBIT_UNKNOWN
373
+ && (f_written < f_start || f_written > f_end)) {
374
+ return;
375
+ }
72
+ }
376
+
73
+
377
+ for (fbit = f_start; fbit <= f_end; fbit++, wbits++) {
74
+ trace_ccm_clock_freq(clock, freq);
378
+ if (wbits == 32) {
379
+ /* Update the key offset. */
380
+ u32_off += 1;
381
+ wbits = 0;
382
+ }
383
+ u32[u32_off] |= xlnx_efuse_get_bit(s->efuse, fbit) << wbits;
384
+ }
385
+}
386
+
75
+
387
+/*
76
+ return freq;
388
+ * Keep the syncs in bit order so we can bail out for the
77
}
389
+ * slower ones.
78
390
+ */
79
static void imx7_ccm_class_init(ObjectClass *klass, void *data)
391
+static void zynqmp_efuse_sync_cache(XlnxZynqMPEFuse *s, unsigned int bit)
392
+{
393
+ EFUSE_CACHE_BIT(s, SEC_CTRL, AES_RDLK);
394
+ EFUSE_CACHE_BIT(s, SEC_CTRL, AES_WRLK);
395
+ EFUSE_CACHE_BIT(s, SEC_CTRL, ENC_ONLY);
396
+ EFUSE_CACHE_BIT(s, SEC_CTRL, BBRAM_DIS);
397
+ EFUSE_CACHE_BIT(s, SEC_CTRL, ERROR_DIS);
398
+ EFUSE_CACHE_BIT(s, SEC_CTRL, JTAG_DIS);
399
+ EFUSE_CACHE_BIT(s, SEC_CTRL, DFT_DIS);
400
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_0);
401
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_1);
402
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_2);
403
+ EFUSE_CACHE_BIT(s, SEC_CTRL, SEC_LOCK);
404
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PPK0_WRLK);
405
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PPK1_WRLK);
406
+
407
+ EFUSE_CACHE_FLD(s, SEC_CTRL, RSA_EN);
408
+ EFUSE_CACHE_FLD(s, SEC_CTRL, PPK0_INVLD);
409
+ EFUSE_CACHE_FLD(s, SEC_CTRL, PPK1_INVLD);
410
+
411
+ /* Update the tbits. */
412
+ update_tbit_status(s);
413
+
414
+ /* Sync the various areas. */
415
+ s->regs[R_MISC_USER_CTRL] = xlnx_efuse_get_row(s->efuse,
416
+ EFUSE_USER_CTRL_START)
417
+ & EFUSE_USER_CTRL_MASK;
418
+ s->regs[R_PUF_CHASH] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_CHASH_START);
419
+ s->regs[R_PUF_MISC] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_MISC_START);
420
+
421
+ cache_sync_u32(s, R_DNA_0, EFUSE_DNA_START, EFUSE_DNA_END, bit);
422
+
423
+ if (bit < EFUSE_AES_START) {
424
+ return;
425
+ }
426
+
427
+ cache_sync_u32(s, R_ROM_RSVD, EFUSE_ROM_START, EFUSE_ROM_END, bit);
428
+ cache_sync_u32(s, R_IPDISABLE, EFUSE_IPDIS_START, EFUSE_IPDIS_END, bit);
429
+ cache_sync_u32(s, R_USER_0, EFUSE_USER_START, EFUSE_USER_END, bit);
430
+ cache_sync_u32(s, R_SPK_ID, EFUSE_SPK_START, EFUSE_SPK_END, bit);
431
+ cache_sync_u32(s, R_PPK0_0, EFUSE_PPK0_START, EFUSE_PPK0_END, bit);
432
+ cache_sync_u32(s, R_PPK1_0, EFUSE_PPK1_START, EFUSE_PPK1_END, bit);
433
+}
434
+
435
+static void zynqmp_efuse_update_irq(XlnxZynqMPEFuse *s)
436
+{
437
+ bool pending = s->regs[R_EFUSE_ISR] & s->regs[R_EFUSE_IMR];
438
+ qemu_set_irq(s->irq, pending);
439
+}
440
+
441
+static void zynqmp_efuse_isr_postw(RegisterInfo *reg, uint64_t val64)
442
+{
443
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
444
+ zynqmp_efuse_update_irq(s);
445
+}
446
+
447
+static uint64_t zynqmp_efuse_ier_prew(RegisterInfo *reg, uint64_t val64)
448
+{
449
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
450
+ uint32_t val = val64;
451
+
452
+ s->regs[R_EFUSE_IMR] |= val;
453
+ zynqmp_efuse_update_irq(s);
454
+ return 0;
455
+}
456
+
457
+static uint64_t zynqmp_efuse_idr_prew(RegisterInfo *reg, uint64_t val64)
458
+{
459
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
460
+ uint32_t val = val64;
461
+
462
+ s->regs[R_EFUSE_IMR] &= ~val;
463
+ zynqmp_efuse_update_irq(s);
464
+ return 0;
465
+}
466
+
467
+static void zynqmp_efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64)
468
+{
469
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
470
+ unsigned bit = val64;
471
+ unsigned page = FIELD_EX32(bit, EFUSE_PGM_ADDR, EFUSE);
472
+ bool puf_prot = false;
473
+ const char *errmsg = NULL;
474
+
475
+ /* Allow only valid array, and adjust for skipped array 1 */
476
+ switch (page) {
477
+ case 0:
478
+ break;
479
+ case 2 ... 3:
480
+ bit = FIELD_DP32(bit, EFUSE_PGM_ADDR, EFUSE, page - 1);
481
+ puf_prot = xlnx_efuse_get_bit(s->efuse, EFUSE_PUF_SYN_WRLK);
482
+ break;
483
+ default:
484
+ errmsg = "Invalid address";
485
+ goto pgm_done;
486
+ }
487
+
488
+ if (ARRAY_FIELD_EX32(s->regs, WR_LOCK, LOCK)) {
489
+ errmsg = "Array write-locked";
490
+ goto pgm_done;
491
+ }
492
+
493
+ if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) {
494
+ errmsg = "Array pgm-disabled";
495
+ goto pgm_done;
496
+ }
497
+
498
+ if (puf_prot) {
499
+ errmsg = "PUF_HD-store write-locked";
500
+ goto pgm_done;
501
+ }
502
+
503
+ if (ARRAY_FIELD_EX32(s->regs, SEC_CTRL, AES_WRLK)
504
+ && bit >= EFUSE_AES_START && bit <= EFUSE_AES_END) {
505
+ errmsg = "AES key-store Write-locked";
506
+ goto pgm_done;
507
+ }
508
+
509
+ if (!xlnx_efuse_set_bit(s->efuse, bit)) {
510
+ errmsg = "Write failed";
511
+ }
512
+
513
+ pgm_done:
514
+ if (!errmsg) {
515
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 0);
516
+ } else {
517
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1);
518
+ qemu_log_mask(LOG_GUEST_ERROR,
519
+ "%s - eFuse write error: %s; addr=0x%x\n",
520
+ object_get_canonical_path(OBJECT(s)),
521
+ errmsg, (unsigned)val64);
522
+ }
523
+
524
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1);
525
+ zynqmp_efuse_update_irq(s);
526
+}
527
+
528
+static void zynqmp_efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64)
529
+{
530
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
531
+
532
+ /*
533
+ * Grant reads only to allowed bits; reference sources:
534
+ * 1/ XilSKey - XilSKey_ZynqMp_EfusePs_ReadRow()
535
+ * 2/ UG1085, v2.0, table 12-13
536
+ * (note: enumerates the masks as <first, last> per described in
537
+ * references to avoid mental translation).
538
+ */
539
+#define COL_MASK(L_, H_) \
540
+ ((uint32_t)MAKE_64BIT_MASK((L_), (1 + (H_) - (L_))))
541
+
542
+ static const uint32_t ary0_col_mask[] = {
543
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_TBITS_ROW */
544
+ [0] = COL_MASK(28, 31),
545
+
546
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_USR{0:7}_FUSE_ROW */
547
+ [8] = COL_MASK(0, 31), [9] = COL_MASK(0, 31),
548
+ [10] = COL_MASK(0, 31), [11] = COL_MASK(0, 31),
549
+ [12] = COL_MASK(0, 31), [13] = COL_MASK(0, 31),
550
+ [14] = COL_MASK(0, 31), [15] = COL_MASK(0, 31),
551
+
552
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_MISC_USR_CTRL_ROW */
553
+ [16] = COL_MASK(0, 7) | COL_MASK(10, 16),
554
+
555
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_ROW */
556
+ [17] = COL_MASK(0, 2),
557
+
558
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_CHASH_ROW */
559
+ [20] = COL_MASK(0, 31),
560
+
561
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_AUX_ROW */
562
+ [21] = COL_MASK(0, 23) | COL_MASK(29, 31),
563
+
564
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW */
565
+ [22] = COL_MASK(0, 31),
566
+
567
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW */
568
+ [23] = COL_MASK(0, 31),
569
+
570
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW */
571
+ [40] = COL_MASK(0, 31), [41] = COL_MASK(0, 31),
572
+ [42] = COL_MASK(0, 31), [43] = COL_MASK(0, 31),
573
+ [44] = COL_MASK(0, 31), [45] = COL_MASK(0, 31),
574
+ [46] = COL_MASK(0, 31), [47] = COL_MASK(0, 31),
575
+ [48] = COL_MASK(0, 31), [49] = COL_MASK(0, 31),
576
+ [50] = COL_MASK(0, 31), [51] = COL_MASK(0, 31),
577
+
578
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW */
579
+ [52] = COL_MASK(0, 31), [53] = COL_MASK(0, 31),
580
+ [54] = COL_MASK(0, 31), [55] = COL_MASK(0, 31),
581
+ [56] = COL_MASK(0, 31), [57] = COL_MASK(0, 31),
582
+ [58] = COL_MASK(0, 31), [59] = COL_MASK(0, 31),
583
+ [60] = COL_MASK(0, 31), [61] = COL_MASK(0, 31),
584
+ [62] = COL_MASK(0, 31), [63] = COL_MASK(0, 31),
585
+ };
586
+
587
+ uint32_t col_mask = COL_MASK(0, 31);
588
+#undef COL_MASK
589
+
590
+ uint32_t efuse_idx = s->regs[R_EFUSE_RD_ADDR];
591
+ uint32_t efuse_ary = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, EFUSE);
592
+ uint32_t efuse_row = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, ROW);
593
+
594
+ switch (efuse_ary) {
595
+ case 0: /* Various */
596
+ if (efuse_row >= ARRAY_SIZE(ary0_col_mask)) {
597
+ goto denied;
598
+ }
599
+
600
+ col_mask = ary0_col_mask[efuse_row];
601
+ if (!col_mask) {
602
+ goto denied;
603
+ }
604
+ break;
605
+ case 2: /* PUF helper data, adjust for skipped array 1 */
606
+ case 3:
607
+ val64 = FIELD_DP32(efuse_idx, EFUSE_RD_ADDR, EFUSE, efuse_ary - 1);
608
+ break;
609
+ default:
610
+ goto denied;
611
+ }
612
+
613
+ s->regs[R_EFUSE_RD_DATA] = xlnx_efuse_get_row(s->efuse, val64) & col_mask;
614
+
615
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 0);
616
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1);
617
+ zynqmp_efuse_update_irq(s);
618
+ return;
619
+
620
+ denied:
621
+ qemu_log_mask(LOG_GUEST_ERROR,
622
+ "%s: Denied efuse read from array %u, row %u\n",
623
+ object_get_canonical_path(OBJECT(s)),
624
+ efuse_ary, efuse_row);
625
+
626
+ s->regs[R_EFUSE_RD_DATA] = 0;
627
+
628
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1);
629
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 0);
630
+ zynqmp_efuse_update_irq(s);
631
+}
632
+
633
+static void zynqmp_efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
634
+{
635
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
636
+ bool ok;
637
+
638
+ ok = xlnx_efuse_k256_check(s->efuse, (uint32_t)val64, EFUSE_AES_START);
639
+
640
+ ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_PASS, (ok ? 1 : 0));
641
+ ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_DONE, 1);
642
+
643
+ s->regs[R_EFUSE_AES_CRC] = 0; /* crc value is write-only */
644
+}
645
+
646
+static uint64_t zynqmp_efuse_cache_load_prew(RegisterInfo *reg,
647
+ uint64_t valu64)
648
+{
649
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
650
+
651
+ if (valu64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) {
652
+ zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN);
653
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
654
+ zynqmp_efuse_update_irq(s);
655
+ }
656
+
657
+ return 0;
658
+}
659
+
660
+static uint64_t zynqmp_efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val)
661
+{
662
+ return val == 0xDF0D ? 0 : 1;
663
+}
664
+
665
+static RegisterAccessInfo zynqmp_efuse_regs_info[] = {
666
+ { .name = "WR_LOCK", .addr = A_WR_LOCK,
667
+ .reset = 0x1,
668
+ .pre_write = zynqmp_efuse_wr_lock_prew,
669
+ },{ .name = "CFG", .addr = A_CFG,
670
+ },{ .name = "STATUS", .addr = A_STATUS,
671
+ .rsvd = 0x8,
672
+ .ro = 0xff,
673
+ },{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR,
674
+ .post_write = zynqmp_efuse_pgm_addr_postw
675
+ },{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR,
676
+ .rsvd = 0x1f,
677
+ .post_write = zynqmp_efuse_rd_addr_postw,
678
+ },{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA,
679
+ .ro = 0xffffffff,
680
+ },{ .name = "TPGM", .addr = A_TPGM,
681
+ },{ .name = "TRD", .addr = A_TRD,
682
+ .reset = 0x1b,
683
+ },{ .name = "TSU_H_PS", .addr = A_TSU_H_PS,
684
+ .reset = 0xff,
685
+ },{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS,
686
+ .reset = 0xb,
687
+ },{ .name = "TSU_H_CS", .addr = A_TSU_H_CS,
688
+ .reset = 0x7,
689
+ },{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR,
690
+ .rsvd = 0x7fffffe0,
691
+ .w1c = 0x8000001f,
692
+ .post_write = zynqmp_efuse_isr_postw,
693
+ },{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR,
694
+ .reset = 0x8000001f,
695
+ .rsvd = 0x7fffffe0,
696
+ .ro = 0xffffffff,
697
+ },{ .name = "EFUSE_IER", .addr = A_EFUSE_IER,
698
+ .rsvd = 0x7fffffe0,
699
+ .pre_write = zynqmp_efuse_ier_prew,
700
+ },{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR,
701
+ .rsvd = 0x7fffffe0,
702
+ .pre_write = zynqmp_efuse_idr_prew,
703
+ },{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD,
704
+ .pre_write = zynqmp_efuse_cache_load_prew,
705
+ },{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK,
706
+ },{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC,
707
+ .post_write = zynqmp_efuse_aes_crc_postw,
708
+ },{ .name = "EFUSE_TBITS_PRGRMG_EN", .addr = A_EFUSE_TBITS_PRGRMG_EN,
709
+ .reset = R_EFUSE_TBITS_PRGRMG_EN_TBITS_PRGRMG_EN_MASK,
710
+ },{ .name = "DNA_0", .addr = A_DNA_0,
711
+ .ro = 0xffffffff,
712
+ },{ .name = "DNA_1", .addr = A_DNA_1,
713
+ .ro = 0xffffffff,
714
+ },{ .name = "DNA_2", .addr = A_DNA_2,
715
+ .ro = 0xffffffff,
716
+ },{ .name = "IPDISABLE", .addr = A_IPDISABLE,
717
+ .ro = 0xffffffff,
718
+ },{ .name = "SYSOSC_CTRL", .addr = A_SYSOSC_CTRL,
719
+ .ro = 0xffffffff,
720
+ },{ .name = "USER_0", .addr = A_USER_0,
721
+ .ro = 0xffffffff,
722
+ },{ .name = "USER_1", .addr = A_USER_1,
723
+ .ro = 0xffffffff,
724
+ },{ .name = "USER_2", .addr = A_USER_2,
725
+ .ro = 0xffffffff,
726
+ },{ .name = "USER_3", .addr = A_USER_3,
727
+ .ro = 0xffffffff,
728
+ },{ .name = "USER_4", .addr = A_USER_4,
729
+ .ro = 0xffffffff,
730
+ },{ .name = "USER_5", .addr = A_USER_5,
731
+ .ro = 0xffffffff,
732
+ },{ .name = "USER_6", .addr = A_USER_6,
733
+ .ro = 0xffffffff,
734
+ },{ .name = "USER_7", .addr = A_USER_7,
735
+ .ro = 0xffffffff,
736
+ },{ .name = "MISC_USER_CTRL", .addr = A_MISC_USER_CTRL,
737
+ .ro = 0xffffffff,
738
+ },{ .name = "ROM_RSVD", .addr = A_ROM_RSVD,
739
+ .ro = 0xffffffff,
740
+ },{ .name = "PUF_CHASH", .addr = A_PUF_CHASH,
741
+ .ro = 0xffffffff,
742
+ },{ .name = "PUF_MISC", .addr = A_PUF_MISC,
743
+ .ro = 0xffffffff,
744
+ },{ .name = "SEC_CTRL", .addr = A_SEC_CTRL,
745
+ .ro = 0xffffffff,
746
+ },{ .name = "SPK_ID", .addr = A_SPK_ID,
747
+ .ro = 0xffffffff,
748
+ },{ .name = "PPK0_0", .addr = A_PPK0_0,
749
+ .ro = 0xffffffff,
750
+ },{ .name = "PPK0_1", .addr = A_PPK0_1,
751
+ .ro = 0xffffffff,
752
+ },{ .name = "PPK0_2", .addr = A_PPK0_2,
753
+ .ro = 0xffffffff,
754
+ },{ .name = "PPK0_3", .addr = A_PPK0_3,
755
+ .ro = 0xffffffff,
756
+ },{ .name = "PPK0_4", .addr = A_PPK0_4,
757
+ .ro = 0xffffffff,
758
+ },{ .name = "PPK0_5", .addr = A_PPK0_5,
759
+ .ro = 0xffffffff,
760
+ },{ .name = "PPK0_6", .addr = A_PPK0_6,
761
+ .ro = 0xffffffff,
762
+ },{ .name = "PPK0_7", .addr = A_PPK0_7,
763
+ .ro = 0xffffffff,
764
+ },{ .name = "PPK0_8", .addr = A_PPK0_8,
765
+ .ro = 0xffffffff,
766
+ },{ .name = "PPK0_9", .addr = A_PPK0_9,
767
+ .ro = 0xffffffff,
768
+ },{ .name = "PPK0_10", .addr = A_PPK0_10,
769
+ .ro = 0xffffffff,
770
+ },{ .name = "PPK0_11", .addr = A_PPK0_11,
771
+ .ro = 0xffffffff,
772
+ },{ .name = "PPK1_0", .addr = A_PPK1_0,
773
+ .ro = 0xffffffff,
774
+ },{ .name = "PPK1_1", .addr = A_PPK1_1,
775
+ .ro = 0xffffffff,
776
+ },{ .name = "PPK1_2", .addr = A_PPK1_2,
777
+ .ro = 0xffffffff,
778
+ },{ .name = "PPK1_3", .addr = A_PPK1_3,
779
+ .ro = 0xffffffff,
780
+ },{ .name = "PPK1_4", .addr = A_PPK1_4,
781
+ .ro = 0xffffffff,
782
+ },{ .name = "PPK1_5", .addr = A_PPK1_5,
783
+ .ro = 0xffffffff,
784
+ },{ .name = "PPK1_6", .addr = A_PPK1_6,
785
+ .ro = 0xffffffff,
786
+ },{ .name = "PPK1_7", .addr = A_PPK1_7,
787
+ .ro = 0xffffffff,
788
+ },{ .name = "PPK1_8", .addr = A_PPK1_8,
789
+ .ro = 0xffffffff,
790
+ },{ .name = "PPK1_9", .addr = A_PPK1_9,
791
+ .ro = 0xffffffff,
792
+ },{ .name = "PPK1_10", .addr = A_PPK1_10,
793
+ .ro = 0xffffffff,
794
+ },{ .name = "PPK1_11", .addr = A_PPK1_11,
795
+ .ro = 0xffffffff,
796
+ }
797
+};
798
+
799
+static void zynqmp_efuse_reg_write(void *opaque, hwaddr addr,
800
+ uint64_t data, unsigned size)
801
+{
802
+ RegisterInfoArray *reg_array = opaque;
803
+ XlnxZynqMPEFuse *s;
804
+ Object *dev;
805
+
806
+ assert(reg_array != NULL);
807
+
808
+ dev = reg_array->mem.owner;
809
+ assert(dev);
810
+
811
+ s = XLNX_ZYNQMP_EFUSE(dev);
812
+
813
+ if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {
814
+ qemu_log_mask(LOG_GUEST_ERROR,
815
+ "%s[reg_0x%02lx]: Attempt to write locked register.\n",
816
+ object_get_canonical_path(OBJECT(s)), (long)addr);
817
+ } else {
818
+ register_write_memory(opaque, addr, data, size);
819
+ }
820
+}
821
+
822
+static const MemoryRegionOps zynqmp_efuse_ops = {
823
+ .read = register_read_memory,
824
+ .write = zynqmp_efuse_reg_write,
825
+ .endianness = DEVICE_LITTLE_ENDIAN,
826
+ .valid = {
827
+ .min_access_size = 4,
828
+ .max_access_size = 4,
829
+ },
830
+};
831
+
832
+static void zynqmp_efuse_register_reset(RegisterInfo *reg)
833
+{
834
+ if (!reg->data || !reg->access) {
835
+ return;
836
+ }
837
+
838
+ /* Reset must not trigger some registers' writers */
839
+ switch (reg->access->addr) {
840
+ case A_EFUSE_AES_CRC:
841
+ *(uint32_t *)reg->data = reg->access->reset;
842
+ return;
843
+ }
844
+
845
+ register_reset(reg);
846
+}
847
+
848
+static void zynqmp_efuse_reset(DeviceState *dev)
849
+{
850
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
851
+ unsigned int i;
852
+
853
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
854
+ zynqmp_efuse_register_reset(&s->regs_info[i]);
855
+ }
856
+
857
+ zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN);
858
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
859
+ zynqmp_efuse_update_irq(s);
860
+}
861
+
862
+static void zynqmp_efuse_realize(DeviceState *dev, Error **errp)
863
+{
864
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
865
+
866
+ if (!s->efuse) {
867
+ error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE",
868
+ object_get_canonical_path(OBJECT(dev)));
869
+ return;
870
+ }
871
+
872
+ s->efuse->dev = dev;
873
+}
874
+
875
+static void zynqmp_efuse_init(Object *obj)
876
+{
877
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj);
878
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
879
+ RegisterInfoArray *reg_array;
880
+
881
+ reg_array =
882
+ register_init_block32(DEVICE(obj), zynqmp_efuse_regs_info,
883
+ ARRAY_SIZE(zynqmp_efuse_regs_info),
884
+ s->regs_info, s->regs,
885
+ &zynqmp_efuse_ops,
886
+ ZYNQMP_EFUSE_ERR_DEBUG,
887
+ R_MAX * 4);
888
+
889
+ sysbus_init_mmio(sbd, &reg_array->mem);
890
+ sysbus_init_irq(sbd, &s->irq);
891
+}
892
+
893
+static const VMStateDescription vmstate_efuse = {
894
+ .name = TYPE_XLNX_ZYNQMP_EFUSE,
895
+ .version_id = 1,
896
+ .minimum_version_id = 1,
897
+ .fields = (VMStateField[]) {
898
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPEFuse, R_MAX),
899
+ VMSTATE_END_OF_LIST(),
900
+ }
901
+};
902
+
903
+static Property zynqmp_efuse_props[] = {
904
+ DEFINE_PROP_LINK("efuse",
905
+ XlnxZynqMPEFuse, efuse,
906
+ TYPE_XLNX_EFUSE, XlnxEFuse *),
907
+
908
+ DEFINE_PROP_END_OF_LIST(),
909
+};
910
+
911
+static void zynqmp_efuse_class_init(ObjectClass *klass, void *data)
912
+{
913
+ DeviceClass *dc = DEVICE_CLASS(klass);
914
+
915
+ dc->reset = zynqmp_efuse_reset;
916
+ dc->realize = zynqmp_efuse_realize;
917
+ dc->vmsd = &vmstate_efuse;
918
+ device_class_set_props(dc, zynqmp_efuse_props);
919
+}
920
+
921
+
922
+static const TypeInfo efuse_info = {
923
+ .name = TYPE_XLNX_ZYNQMP_EFUSE,
924
+ .parent = TYPE_SYS_BUS_DEVICE,
925
+ .instance_size = sizeof(XlnxZynqMPEFuse),
926
+ .class_init = zynqmp_efuse_class_init,
927
+ .instance_init = zynqmp_efuse_init,
928
+};
929
+
930
+static void efuse_register_types(void)
931
+{
932
+ type_register_static(&efuse_info);
933
+}
934
+
935
+type_init(efuse_register_types)
936
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
937
index XXXXXXX..XXXXXXX 100644
938
--- a/hw/nvram/Kconfig
939
+++ b/hw/nvram/Kconfig
940
@@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE
941
config XLNX_EFUSE_VERSAL
942
bool
943
select XLNX_EFUSE
944
+
945
+config XLNX_EFUSE_ZYNQMP
946
+ bool
947
+ select XLNX_EFUSE
948
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
949
index XXXXXXX..XXXXXXX 100644
950
--- a/hw/nvram/meson.build
951
+++ b/hw/nvram/meson.build
952
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
953
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
954
'xlnx-versal-efuse-cache.c',
955
'xlnx-versal-efuse-ctrl.c'))
956
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files(
957
+ 'xlnx-zynqmp-efuse.c'))
958
959
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
960
--
80
--
961
2.20.1
81
2.25.1
962
963
diff view generated by jsdifflib
[PULL 03/22] hw/nvram: Introduce Xilinx eFuse QOM
[PULL 32/34] i.MX6UL: Add a specific GPT timer instance for the i.MX6UL
1
From: Tong Ho <tong.ho@xilinx.com>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
This introduces the QOM for Xilinx eFuse, an one-time
3
The i.MX6UL doesn't support CLK_HIGH ou CLK_HIGH_DIV clock source.
4
field-programmable storage bit array.
5
4
6
The actual mmio interface to the array varies by device
5
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
7
families and will be provided in different change-sets.
8
9
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
11
12
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
13
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
14
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
15
Message-id: 20210917052400.1249094-2-tong.ho@xilinx.com
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
8
---
19
include/hw/nvram/xlnx-efuse.h | 132 ++++++++++++++++
9
include/hw/timer/imx_gpt.h | 1 +
20
hw/nvram/xlnx-efuse-crc.c | 119 +++++++++++++++
10
hw/arm/fsl-imx6ul.c | 2 +-
21
hw/nvram/xlnx-efuse.c | 280 ++++++++++++++++++++++++++++++++++
11
hw/misc/imx6ul_ccm.c | 6 ------
22
hw/nvram/Kconfig | 7 +
12
hw/timer/imx_gpt.c | 25 +++++++++++++++++++++++++
23
hw/nvram/meson.build | 2 +
13
4 files changed, 27 insertions(+), 7 deletions(-)
24
5 files changed, 540 insertions(+)
25
create mode 100644 include/hw/nvram/xlnx-efuse.h
26
create mode 100644 hw/nvram/xlnx-efuse-crc.c
27
create mode 100644 hw/nvram/xlnx-efuse.c
28
14
29
diff --git a/include/hw/nvram/xlnx-efuse.h b/include/hw/nvram/xlnx-efuse.h
15
diff --git a/include/hw/timer/imx_gpt.h b/include/hw/timer/imx_gpt.h
30
new file mode 100644
16
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX
17
--- a/include/hw/timer/imx_gpt.h
32
--- /dev/null
18
+++ b/include/hw/timer/imx_gpt.h
33
+++ b/include/hw/nvram/xlnx-efuse.h
34
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@
35
+/*
20
#define TYPE_IMX25_GPT "imx25.gpt"
36
+ * QEMU model of the Xilinx eFuse core
21
#define TYPE_IMX31_GPT "imx31.gpt"
37
+ *
22
#define TYPE_IMX6_GPT "imx6.gpt"
38
+ * Copyright (c) 2015 Xilinx Inc.
23
+#define TYPE_IMX6UL_GPT "imx6ul.gpt"
39
+ *
24
#define TYPE_IMX7_GPT "imx7.gpt"
40
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
25
41
+ *
26
#define TYPE_IMX_GPT TYPE_IMX25_GPT
42
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
27
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
43
+ * of this software and associated documentation files (the "Software"), to deal
28
index XXXXXXX..XXXXXXX 100644
44
+ * in the Software without restriction, including without limitation the rights
29
--- a/hw/arm/fsl-imx6ul.c
45
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
30
+++ b/hw/arm/fsl-imx6ul.c
46
+ * copies of the Software, and to permit persons to whom the Software is
31
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
47
+ * furnished to do so, subject to the following conditions:
32
*/
48
+ *
33
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
49
+ * The above copyright notice and this permission notice shall be included in
34
snprintf(name, NAME_SIZE, "gpt%d", i);
50
+ * all copies or substantial portions of the Software.
35
- object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
51
+ *
36
+ object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT);
52
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
37
}
53
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
38
54
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
39
/*
55
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
40
diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c
56
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41
index XXXXXXX..XXXXXXX 100644
57
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
42
--- a/hw/misc/imx6ul_ccm.c
58
+ * THE SOFTWARE.
43
+++ b/hw/misc/imx6ul_ccm.c
59
+ */
44
@@ -XXX,XX +XXX,XX @@ static uint32_t imx6ul_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
60
+
45
case CLK_32k:
61
+#ifndef XLNX_EFUSE_H
46
freq = CKIL_FREQ;
62
+#define XLNX_EFUSE_H
47
break;
63
+
48
- case CLK_HIGH:
64
+#include "sysemu/block-backend.h"
49
- freq = CKIH_FREQ;
65
+#include "hw/qdev-core.h"
50
- break;
66
+
51
- case CLK_HIGH_DIV:
67
+#define TYPE_XLNX_EFUSE "xlnx,efuse"
52
- freq = CKIH_FREQ / 8;
68
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxEFuse, XLNX_EFUSE);
53
- break;
69
+
54
default:
70
+struct XlnxEFuse {
55
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
71
+ DeviceState parent_obj;
56
TYPE_IMX6UL_CCM, __func__, clock);
72
+ BlockBackend *blk;
57
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
73
+ bool blk_ro;
58
index XXXXXXX..XXXXXXX 100644
74
+ uint32_t *fuse32;
59
--- a/hw/timer/imx_gpt.c
75
+
60
+++ b/hw/timer/imx_gpt.c
76
+ DeviceState *dev;
61
@@ -XXX,XX +XXX,XX @@ static const IMXClk imx6_gpt_clocks[] = {
77
+
62
CLK_HIGH, /* 111 reference clock */
78
+ bool init_tbits;
63
};
79
+
64
80
+ uint8_t efuse_nr;
65
+static const IMXClk imx6ul_gpt_clocks[] = {
81
+ uint32_t efuse_size;
66
+ CLK_NONE, /* 000 No clock source */
82
+
67
+ CLK_IPG, /* 001 ipg_clk, 532MHz*/
83
+ uint32_t *ro_bits;
68
+ CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
84
+ uint32_t ro_bits_cnt;
69
+ CLK_EXT, /* 011 External clock */
70
+ CLK_32k, /* 100 ipg_clk_32k */
71
+ CLK_NONE, /* 101 not defined */
72
+ CLK_NONE, /* 110 not defined */
73
+ CLK_NONE, /* 111 not defined */
85
+};
74
+};
86
+
75
+
87
+/**
76
static const IMXClk imx7_gpt_clocks[] = {
88
+ * xlnx_efuse_calc_crc:
77
CLK_NONE, /* 000 No clock source */
89
+ * @data: an array of 32-bit words for which the CRC should be computed
78
CLK_IPG, /* 001 ipg_clk, 532MHz*/
90
+ * @u32_cnt: the array size in number of 32-bit words
79
@@ -XXX,XX +XXX,XX @@ static void imx6_gpt_init(Object *obj)
91
+ * @zpads: the number of 32-bit zeros prepended to @data before computation
80
s->clocks = imx6_gpt_clocks;
92
+ *
81
}
93
+ * This function is used to compute the CRC for an array of 32-bit words,
82
94
+ * using a Xilinx-specific data padding.
83
+static void imx6ul_gpt_init(Object *obj)
95
+ *
84
+{
96
+ * Returns: the computed 32-bit CRC
85
+ IMXGPTState *s = IMX_GPT(obj);
97
+ */
98
+uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt,
99
+ unsigned zpads);
100
+
86
+
101
+/**
87
+ s->clocks = imx6ul_gpt_clocks;
102
+ * xlnx_efuse_get_bit:
103
+ * @s: the efuse object
104
+ * @bit: the efuse bit-address to read the data
105
+ *
106
+ * Returns: the bit, 0 or 1, at @bit of object @s
107
+ */
108
+bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit);
109
+
110
+/**
111
+ * xlnx_efuse_set_bit:
112
+ * @s: the efuse object
113
+ * @bit: the efuse bit-address to be written a value of 1
114
+ *
115
+ * Returns: true on success, false on failure
116
+ */
117
+bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit);
118
+
119
+/**
120
+ * xlnx_efuse_k256_check:
121
+ * @s: the efuse object
122
+ * @crc: the 32-bit CRC to be compared with
123
+ * @start: the efuse bit-address (which must be multiple of 32) of the
124
+ * start of a 256-bit array
125
+ *
126
+ * This function computes the CRC of a 256-bit array starting at @start
127
+ * then compares to the given @crc
128
+ *
129
+ * Returns: true of @crc == computed, false otherwise
130
+ */
131
+bool xlnx_efuse_k256_check(XlnxEFuse *s, uint32_t crc, unsigned start);
132
+
133
+/**
134
+ * xlnx_efuse_tbits_check:
135
+ * @s: the efuse object
136
+ *
137
+ * This function inspects a number of efuse bits at specific addresses
138
+ * to see if they match a validation pattern. Each pattern is a group
139
+ * of 4 bits, and there are 3 groups.
140
+ *
141
+ * Returns: a 3-bit mask, where a bit of '1' means the corresponding
142
+ * group has a valid pattern.
143
+ */
144
+uint32_t xlnx_efuse_tbits_check(XlnxEFuse *s);
145
+
146
+/**
147
+ * xlnx_efuse_get_row:
148
+ * @s: the efuse object
149
+ * @bit: the efuse bit address for which a 32-bit value is read
150
+ *
151
+ * Returns: the entire 32 bits of the efuse, starting at a bit
152
+ * address that is multiple of 32 and contains the bit at @bit
153
+ */
154
+static inline uint32_t xlnx_efuse_get_row(XlnxEFuse *s, unsigned int bit)
155
+{
156
+ if (!(s->fuse32)) {
157
+ return 0;
158
+ } else {
159
+ unsigned int row_idx = bit / 32;
160
+
161
+ assert(row_idx < (s->efuse_size * s->efuse_nr / 32));
162
+ return s->fuse32[row_idx];
163
+ }
164
+}
88
+}
165
+
89
+
166
+#endif
90
static void imx7_gpt_init(Object *obj)
167
diff --git a/hw/nvram/xlnx-efuse-crc.c b/hw/nvram/xlnx-efuse-crc.c
91
{
168
new file mode 100644
92
IMXGPTState *s = IMX_GPT(obj);
169
index XXXXXXX..XXXXXXX
93
@@ -XXX,XX +XXX,XX @@ static const TypeInfo imx6_gpt_info = {
170
--- /dev/null
94
.instance_init = imx6_gpt_init,
171
+++ b/hw/nvram/xlnx-efuse-crc.c
95
};
172
@@ -XXX,XX +XXX,XX @@
96
173
+/*
97
+static const TypeInfo imx6ul_gpt_info = {
174
+ * Xilinx eFuse/bbram CRC calculator
98
+ .name = TYPE_IMX6UL_GPT,
175
+ *
99
+ .parent = TYPE_IMX25_GPT,
176
+ * Copyright (c) 2021 Xilinx Inc.
100
+ .instance_init = imx6ul_gpt_init,
177
+ *
178
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
179
+ * of this software and associated documentation files (the "Software"), to deal
180
+ * in the Software without restriction, including without limitation the rights
181
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
182
+ * copies of the Software, and to permit persons to whom the Software is
183
+ * furnished to do so, subject to the following conditions:
184
+ *
185
+ * The above copyright notice and this permission notice shall be included in
186
+ * all copies or substantial portions of the Software.
187
+ *
188
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
189
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
190
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
191
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
192
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
193
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
194
+ * THE SOFTWARE.
195
+ */
196
+#include "qemu/osdep.h"
197
+#include "hw/nvram/xlnx-efuse.h"
198
+
199
+static uint32_t xlnx_efuse_u37_crc(uint32_t prev_crc, uint32_t data,
200
+ uint32_t addr)
201
+{
202
+ /* A table for 7-bit slicing */
203
+ static const uint32_t crc_tab[128] = {
204
+ 0x00000000, 0xe13b70f7, 0xc79a971f, 0x26a1e7e8,
205
+ 0x8ad958cf, 0x6be22838, 0x4d43cfd0, 0xac78bf27,
206
+ 0x105ec76f, 0xf165b798, 0xd7c45070, 0x36ff2087,
207
+ 0x9a879fa0, 0x7bbcef57, 0x5d1d08bf, 0xbc267848,
208
+ 0x20bd8ede, 0xc186fe29, 0xe72719c1, 0x061c6936,
209
+ 0xaa64d611, 0x4b5fa6e6, 0x6dfe410e, 0x8cc531f9,
210
+ 0x30e349b1, 0xd1d83946, 0xf779deae, 0x1642ae59,
211
+ 0xba3a117e, 0x5b016189, 0x7da08661, 0x9c9bf696,
212
+ 0x417b1dbc, 0xa0406d4b, 0x86e18aa3, 0x67dafa54,
213
+ 0xcba24573, 0x2a993584, 0x0c38d26c, 0xed03a29b,
214
+ 0x5125dad3, 0xb01eaa24, 0x96bf4dcc, 0x77843d3b,
215
+ 0xdbfc821c, 0x3ac7f2eb, 0x1c661503, 0xfd5d65f4,
216
+ 0x61c69362, 0x80fde395, 0xa65c047d, 0x4767748a,
217
+ 0xeb1fcbad, 0x0a24bb5a, 0x2c855cb2, 0xcdbe2c45,
218
+ 0x7198540d, 0x90a324fa, 0xb602c312, 0x5739b3e5,
219
+ 0xfb410cc2, 0x1a7a7c35, 0x3cdb9bdd, 0xdde0eb2a,
220
+ 0x82f63b78, 0x63cd4b8f, 0x456cac67, 0xa457dc90,
221
+ 0x082f63b7, 0xe9141340, 0xcfb5f4a8, 0x2e8e845f,
222
+ 0x92a8fc17, 0x73938ce0, 0x55326b08, 0xb4091bff,
223
+ 0x1871a4d8, 0xf94ad42f, 0xdfeb33c7, 0x3ed04330,
224
+ 0xa24bb5a6, 0x4370c551, 0x65d122b9, 0x84ea524e,
225
+ 0x2892ed69, 0xc9a99d9e, 0xef087a76, 0x0e330a81,
226
+ 0xb21572c9, 0x532e023e, 0x758fe5d6, 0x94b49521,
227
+ 0x38cc2a06, 0xd9f75af1, 0xff56bd19, 0x1e6dcdee,
228
+ 0xc38d26c4, 0x22b65633, 0x0417b1db, 0xe52cc12c,
229
+ 0x49547e0b, 0xa86f0efc, 0x8ecee914, 0x6ff599e3,
230
+ 0xd3d3e1ab, 0x32e8915c, 0x144976b4, 0xf5720643,
231
+ 0x590ab964, 0xb831c993, 0x9e902e7b, 0x7fab5e8c,
232
+ 0xe330a81a, 0x020bd8ed, 0x24aa3f05, 0xc5914ff2,
233
+ 0x69e9f0d5, 0x88d28022, 0xae7367ca, 0x4f48173d,
234
+ 0xf36e6f75, 0x12551f82, 0x34f4f86a, 0xd5cf889d,
235
+ 0x79b737ba, 0x988c474d, 0xbe2da0a5, 0x5f16d052
236
+ };
237
+
238
+ /*
239
+ * eFuse calculation is shown here:
240
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1496
241
+ *
242
+ * Each u32 word is appended a 5-bit value, for a total of 37 bits; see:
243
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1356
244
+ */
245
+ uint32_t crc = prev_crc;
246
+ const unsigned rshf = 7;
247
+ const uint32_t im = (1 << rshf) - 1;
248
+ const uint32_t rm = (1 << (32 - rshf)) - 1;
249
+ const uint32_t i2 = (1 << 2) - 1;
250
+ const uint32_t r2 = (1 << 30) - 1;
251
+
252
+ unsigned j;
253
+ uint32_t i, r;
254
+ uint64_t w;
255
+
256
+ w = (uint64_t)(addr) << 32;
257
+ w |= data;
258
+
259
+ /* Feed 35 bits, in 5 rounds, each a slice of 7 bits */
260
+ for (j = 0; j < 5; j++) {
261
+ r = rm & (crc >> rshf);
262
+ i = im & (crc ^ w);
263
+ crc = crc_tab[i] ^ r;
264
+
265
+ w >>= rshf;
266
+ }
267
+
268
+ /* Feed the remaining 2 bits */
269
+ r = r2 & (crc >> 2);
270
+ i = i2 & (crc ^ w);
271
+ crc = crc_tab[i << (rshf - 2)] ^ r;
272
+
273
+ return crc;
274
+}
275
+
276
+uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt,
277
+ unsigned zpads)
278
+{
279
+ uint32_t crc = 0;
280
+ unsigned index;
281
+
282
+ for (index = zpads; index; index--) {
283
+ crc = xlnx_efuse_u37_crc(crc, 0, (index + u32_cnt));
284
+ }
285
+
286
+ for (index = u32_cnt; index; index--) {
287
+ crc = xlnx_efuse_u37_crc(crc, data[index - 1], index);
288
+ }
289
+
290
+ return crc;
291
+}
292
diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
293
new file mode 100644
294
index XXXXXXX..XXXXXXX
295
--- /dev/null
296
+++ b/hw/nvram/xlnx-efuse.c
297
@@ -XXX,XX +XXX,XX @@
298
+/*
299
+ * QEMU model of the EFUSE eFuse
300
+ *
301
+ * Copyright (c) 2015 Xilinx Inc.
302
+ *
303
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
304
+ *
305
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
306
+ * of this software and associated documentation files (the "Software"), to deal
307
+ * in the Software without restriction, including without limitation the rights
308
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
309
+ * copies of the Software, and to permit persons to whom the Software is
310
+ * furnished to do so, subject to the following conditions:
311
+ *
312
+ * The above copyright notice and this permission notice shall be included in
313
+ * all copies or substantial portions of the Software.
314
+ *
315
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
316
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
317
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
318
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
319
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
320
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
321
+ * THE SOFTWARE.
322
+ */
323
+
324
+#include "qemu/osdep.h"
325
+#include "hw/nvram/xlnx-efuse.h"
326
+
327
+#include "qemu/error-report.h"
328
+#include "qemu/log.h"
329
+#include "qapi/error.h"
330
+#include "sysemu/blockdev.h"
331
+#include "hw/qdev-properties.h"
332
+#include "hw/qdev-properties-system.h"
333
+
334
+#define TBIT0_OFFSET 28
335
+#define TBIT1_OFFSET 29
336
+#define TBIT2_OFFSET 30
337
+#define TBIT3_OFFSET 31
338
+#define TBITS_PATTERN (0x0AU << TBIT0_OFFSET)
339
+#define TBITS_MASK (0x0FU << TBIT0_OFFSET)
340
+
341
+bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit)
342
+{
343
+ bool b = s->fuse32[bit / 32] & (1 << (bit % 32));
344
+ return b;
345
+}
346
+
347
+static int efuse_bytes(XlnxEFuse *s)
348
+{
349
+ return ROUND_UP((s->efuse_nr * s->efuse_size) / 8, 4);
350
+}
351
+
352
+static int efuse_bdrv_read(XlnxEFuse *s, Error **errp)
353
+{
354
+ uint32_t *ram = s->fuse32;
355
+ int nr = efuse_bytes(s);
356
+
357
+ if (!s->blk) {
358
+ return 0;
359
+ }
360
+
361
+ s->blk_ro = !blk_supports_write_perm(s->blk);
362
+ if (!s->blk_ro) {
363
+ int rc;
364
+
365
+ rc = blk_set_perm(s->blk,
366
+ (BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE),
367
+ BLK_PERM_ALL, NULL);
368
+ if (rc) {
369
+ s->blk_ro = true;
370
+ }
371
+ }
372
+ if (s->blk_ro) {
373
+ warn_report("%s: Skip saving updates to read-only eFUSE backstore.",
374
+ blk_name(s->blk));
375
+ }
376
+
377
+ if (blk_pread(s->blk, 0, ram, nr) < 0) {
378
+ error_setg(errp, "%s: Failed to read %u bytes from eFUSE backstore.",
379
+ blk_name(s->blk), nr);
380
+ return -1;
381
+ }
382
+
383
+ /* Convert from little-endian backstore for each 32-bit row */
384
+ nr /= 4;
385
+ while (nr--) {
386
+ ram[nr] = le32_to_cpu(ram[nr]);
387
+ }
388
+
389
+ return 0;
390
+}
391
+
392
+static void efuse_bdrv_sync(XlnxEFuse *s, unsigned int bit)
393
+{
394
+ unsigned int row_offset;
395
+ uint32_t le32;
396
+
397
+ if (!s->blk || s->blk_ro) {
398
+ return; /* Silent on read-only backend to avoid message flood */
399
+ }
400
+
401
+ /* Backstore is always in little-endian */
402
+ le32 = cpu_to_le32(xlnx_efuse_get_row(s, bit));
403
+
404
+ row_offset = (bit / 32) * 4;
405
+ if (blk_pwrite(s->blk, row_offset, &le32, 4, 0) < 0) {
406
+ error_report("%s: Failed to write offset %u of eFUSE backstore.",
407
+ blk_name(s->blk), row_offset);
408
+ }
409
+}
410
+
411
+static int efuse_ro_bits_cmp(const void *a, const void *b)
412
+{
413
+ uint32_t i = *(const uint32_t *)a;
414
+ uint32_t j = *(const uint32_t *)b;
415
+
416
+ return (i > j) - (i < j);
417
+}
418
+
419
+static void efuse_ro_bits_sort(XlnxEFuse *s)
420
+{
421
+ uint32_t *ary = s->ro_bits;
422
+ const uint32_t cnt = s->ro_bits_cnt;
423
+
424
+ if (ary && cnt > 1) {
425
+ qsort(ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp);
426
+ }
427
+}
428
+
429
+static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k)
430
+{
431
+ const uint32_t *ary = s->ro_bits;
432
+ const uint32_t cnt = s->ro_bits_cnt;
433
+
434
+ if (!ary || !cnt) {
435
+ return false;
436
+ }
437
+
438
+ return bsearch(&k, ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp) != NULL;
439
+}
440
+
441
+bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
442
+{
443
+ if (efuse_ro_bits_find(s, bit)) {
444
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: WARN: "
445
+ "Ignored setting of readonly efuse bit<%u,%u>!\n",
446
+ object_get_canonical_path(OBJECT(s)),
447
+ (bit / 32), (bit % 32));
448
+ return false;
449
+ }
450
+
451
+ s->fuse32[bit / 32] |= 1 << (bit % 32);
452
+ efuse_bdrv_sync(s, bit);
453
+ return true;
454
+}
455
+
456
+bool xlnx_efuse_k256_check(XlnxEFuse *s, uint32_t crc, unsigned start)
457
+{
458
+ uint32_t calc;
459
+
460
+ /* A key always occupies multiple of whole rows */
461
+ assert((start % 32) == 0);
462
+
463
+ calc = xlnx_efuse_calc_crc(&s->fuse32[start / 32], (256 / 32), 0);
464
+ return calc == crc;
465
+}
466
+
467
+uint32_t xlnx_efuse_tbits_check(XlnxEFuse *s)
468
+{
469
+ int nr;
470
+ uint32_t check = 0;
471
+
472
+ for (nr = s->efuse_nr; nr-- > 0; ) {
473
+ int efuse_start_row_num = (s->efuse_size * nr) / 32;
474
+ uint32_t data = s->fuse32[efuse_start_row_num];
475
+
476
+ /*
477
+ * If the option is on, auto-init blank T-bits.
478
+ * (non-blank will still be reported as '0' in the check, e.g.,
479
+ * for error-injection tests)
480
+ */
481
+ if ((data & TBITS_MASK) == 0 && s->init_tbits) {
482
+ data |= TBITS_PATTERN;
483
+
484
+ s->fuse32[efuse_start_row_num] = data;
485
+ efuse_bdrv_sync(s, (efuse_start_row_num * 32 + TBIT0_OFFSET));
486
+ }
487
+
488
+ check = (check << 1) | ((data & TBITS_MASK) == TBITS_PATTERN);
489
+ }
490
+
491
+ return check;
492
+}
493
+
494
+static void efuse_realize(DeviceState *dev, Error **errp)
495
+{
496
+ XlnxEFuse *s = XLNX_EFUSE(dev);
497
+
498
+ /* Sort readonly-list for bsearch lookup */
499
+ efuse_ro_bits_sort(s);
500
+
501
+ if ((s->efuse_size % 32) != 0) {
502
+ error_setg(errp,
503
+ "%s.efuse-size: %u: property value not multiple of 32.",
504
+ object_get_canonical_path(OBJECT(dev)), s->efuse_size);
505
+ return;
506
+ }
507
+
508
+ s->fuse32 = g_malloc0(efuse_bytes(s));
509
+ if (efuse_bdrv_read(s, errp)) {
510
+ g_free(s->fuse32);
511
+ }
512
+}
513
+
514
+static void efuse_prop_set_drive(Object *obj, Visitor *v, const char *name,
515
+ void *opaque, Error **errp)
516
+{
517
+ DeviceState *dev = DEVICE(obj);
518
+
519
+ qdev_prop_drive.set(obj, v, name, opaque, errp);
520
+
521
+ /* Fill initial data if backend is attached after realized */
522
+ if (dev->realized) {
523
+ efuse_bdrv_read(XLNX_EFUSE(obj), errp);
524
+ }
525
+}
526
+
527
+static void efuse_prop_get_drive(Object *obj, Visitor *v, const char *name,
528
+ void *opaque, Error **errp)
529
+{
530
+ qdev_prop_drive.get(obj, v, name, opaque, errp);
531
+}
532
+
533
+static void efuse_prop_release_drive(Object *obj, const char *name,
534
+ void *opaque)
535
+{
536
+ qdev_prop_drive.release(obj, name, opaque);
537
+}
538
+
539
+static const PropertyInfo efuse_prop_drive = {
540
+ .name = "str",
541
+ .description = "Node name or ID of a block device to use as eFUSE backend",
542
+ .realized_set_allowed = true,
543
+ .get = efuse_prop_get_drive,
544
+ .set = efuse_prop_set_drive,
545
+ .release = efuse_prop_release_drive,
546
+};
101
+};
547
+
102
+
548
+static Property efuse_properties[] = {
103
static const TypeInfo imx7_gpt_info = {
549
+ DEFINE_PROP("drive", XlnxEFuse, blk, efuse_prop_drive, BlockBackend *),
104
.name = TYPE_IMX7_GPT,
550
+ DEFINE_PROP_UINT8("efuse-nr", XlnxEFuse, efuse_nr, 3),
105
.parent = TYPE_IMX25_GPT,
551
+ DEFINE_PROP_UINT32("efuse-size", XlnxEFuse, efuse_size, 64 * 32),
106
@@ -XXX,XX +XXX,XX @@ static void imx_gpt_register_types(void)
552
+ DEFINE_PROP_BOOL("init-factory-tbits", XlnxEFuse, init_tbits, true),
107
type_register_static(&imx25_gpt_info);
553
+ DEFINE_PROP_ARRAY("read-only", XlnxEFuse, ro_bits_cnt, ro_bits,
108
type_register_static(&imx31_gpt_info);
554
+ qdev_prop_uint32, uint32_t),
109
type_register_static(&imx6_gpt_info);
555
+ DEFINE_PROP_END_OF_LIST(),
110
+ type_register_static(&imx6ul_gpt_info);
556
+};
111
type_register_static(&imx7_gpt_info);
557
+
112
}
558
+static void efuse_class_init(ObjectClass *klass, void *data)
113
559
+{
560
+ DeviceClass *dc = DEVICE_CLASS(klass);
561
+
562
+ dc->realize = efuse_realize;
563
+ device_class_set_props(dc, efuse_properties);
564
+}
565
+
566
+static const TypeInfo efuse_info = {
567
+ .name = TYPE_XLNX_EFUSE,
568
+ .parent = TYPE_DEVICE,
569
+ .instance_size = sizeof(XlnxEFuse),
570
+ .class_init = efuse_class_init,
571
+};
572
+
573
+static void efuse_register_types(void)
574
+{
575
+ type_register_static(&efuse_info);
576
+}
577
+type_init(efuse_register_types)
578
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
579
index XXXXXXX..XXXXXXX 100644
580
--- a/hw/nvram/Kconfig
581
+++ b/hw/nvram/Kconfig
582
@@ -XXX,XX +XXX,XX @@ config NMC93XX_EEPROM
583
584
config CHRP_NVRAM
585
bool
586
+
587
+config XLNX_EFUSE_CRC
588
+ bool
589
+
590
+config XLNX_EFUSE
591
+ bool
592
+ select XLNX_EFUSE_CRC
593
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
594
index XXXXXXX..XXXXXXX 100644
595
--- a/hw/nvram/meson.build
596
+++ b/hw/nvram/meson.build
597
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_AT24C', if_true: files('eeprom_at24c.c'))
598
softmmu_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c'))
599
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
600
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
601
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c'))
602
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
603
604
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
605
--
114
--
606
2.20.1
115
2.25.1
607
608
diff view generated by jsdifflib
New patch
[PULL 33/34] i.MX7D: Connect IRQs to GPIO devices.
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
2
3
IRQs were not associated to the various GPIO devices inside i.MX7D.
4
This patch brings the i.MX7D on par with i.MX6.
5
6
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
7
Message-id: 20221226101418.415170-1-jcd@tribudubois.net
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/fsl-imx7.h | 15 +++++++++++++++
12
hw/arm/fsl-imx7.c | 31 ++++++++++++++++++++++++++++++-
13
2 files changed, 45 insertions(+), 1 deletion(-)
14
15
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx7.h
18
+++ b/include/hw/arm/fsl-imx7.h
19
@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
20
FSL_IMX7_GPT3_IRQ = 53,
21
FSL_IMX7_GPT4_IRQ = 52,
22
23
+ FSL_IMX7_GPIO1_LOW_IRQ = 64,
24
+ FSL_IMX7_GPIO1_HIGH_IRQ = 65,
25
+ FSL_IMX7_GPIO2_LOW_IRQ = 66,
26
+ FSL_IMX7_GPIO2_HIGH_IRQ = 67,
27
+ FSL_IMX7_GPIO3_LOW_IRQ = 68,
28
+ FSL_IMX7_GPIO3_HIGH_IRQ = 69,
29
+ FSL_IMX7_GPIO4_LOW_IRQ = 70,
30
+ FSL_IMX7_GPIO4_HIGH_IRQ = 71,
31
+ FSL_IMX7_GPIO5_LOW_IRQ = 72,
32
+ FSL_IMX7_GPIO5_HIGH_IRQ = 73,
33
+ FSL_IMX7_GPIO6_LOW_IRQ = 74,
34
+ FSL_IMX7_GPIO6_HIGH_IRQ = 75,
35
+ FSL_IMX7_GPIO7_LOW_IRQ = 76,
36
+ FSL_IMX7_GPIO7_HIGH_IRQ = 77,
37
+
38
FSL_IMX7_WDOG1_IRQ = 78,
39
FSL_IMX7_WDOG2_IRQ = 79,
40
FSL_IMX7_WDOG3_IRQ = 10,
41
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/arm/fsl-imx7.c
44
+++ b/hw/arm/fsl-imx7.c
45
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
46
FSL_IMX7_GPIO7_ADDR,
47
};
48
49
+ static const int FSL_IMX7_GPIOn_LOW_IRQ[FSL_IMX7_NUM_GPIOS] = {
50
+ FSL_IMX7_GPIO1_LOW_IRQ,
51
+ FSL_IMX7_GPIO2_LOW_IRQ,
52
+ FSL_IMX7_GPIO3_LOW_IRQ,
53
+ FSL_IMX7_GPIO4_LOW_IRQ,
54
+ FSL_IMX7_GPIO5_LOW_IRQ,
55
+ FSL_IMX7_GPIO6_LOW_IRQ,
56
+ FSL_IMX7_GPIO7_LOW_IRQ,
57
+ };
58
+
59
+ static const int FSL_IMX7_GPIOn_HIGH_IRQ[FSL_IMX7_NUM_GPIOS] = {
60
+ FSL_IMX7_GPIO1_HIGH_IRQ,
61
+ FSL_IMX7_GPIO2_HIGH_IRQ,
62
+ FSL_IMX7_GPIO3_HIGH_IRQ,
63
+ FSL_IMX7_GPIO4_HIGH_IRQ,
64
+ FSL_IMX7_GPIO5_HIGH_IRQ,
65
+ FSL_IMX7_GPIO6_HIGH_IRQ,
66
+ FSL_IMX7_GPIO7_HIGH_IRQ,
67
+ };
68
+
69
sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
70
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]);
71
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
72
+ FSL_IMX7_GPIOn_ADDR[i]);
73
+
74
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
75
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
76
+ FSL_IMX7_GPIOn_LOW_IRQ[i]));
77
+
78
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
79
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
80
+ FSL_IMX7_GPIOn_HIGH_IRQ[i]));
81
}
82
83
/*
84
--
85
2.25.1
diff view generated by jsdifflib
[PULL 02/22] arm: tcg: Adhere to SMCCC 1.3 section 5.2
[PULL 34/34] hw/net: Fix read of uninitialized memory in imx_fec.
1
From: Alexander Graf <agraf@csgraf.de>
1
From: Stephen Longfield <slongfield@google.com>
2
2
3
The SMCCC 1.3 spec section 5.2 says
3
Size is used at lines 1088/1188 for the loop, which reads the last 4
4
bytes from the crc_ptr so it does need to get increased, however it
5
shouldn't be increased before the buffer is passed to CRC computation,
6
or the crc32 function will access uninitialized memory.
4
7
5
The Unknown SMC Function Identifier is a sign-extended value of (-1)
8
This was pointed out to me by clg@kaod.org during the code review of
6
that is returned in the R0, W0 or X0 registers. An implementation must
9
a similar patch to hw/net/ftgmac100.c
7
return this error code when it receives:
8
10
9
* An SMC or HVC call with an unknown Function Identifier
11
Change-Id: Ib0464303b191af1e28abeb2f5105eb25aadb5e9b
10
* An SMC or HVC call for a removed Function Identifier
12
Signed-off-by: Stephen Longfield <slongfield@google.com>
11
* An SMC64/HVC64 call from AArch32 state
13
Reviewed-by: Patrick Venture <venture@google.com>
12
14
Message-id: 20221221183202.3788132-1-slongfield@google.com
13
To comply with these statements, let's always return -1 when we encounter
14
an unknown HVC or SMC call.
15
16
Signed-off-by: Alexander Graf <agraf@csgraf.de>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
17
---
20
target/arm/psci.c | 35 ++++++-----------------------------
18
hw/net/imx_fec.c | 8 ++++----
21
1 file changed, 6 insertions(+), 29 deletions(-)
19
1 file changed, 4 insertions(+), 4 deletions(-)
22
20
23
diff --git a/target/arm/psci.c b/target/arm/psci.c
21
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
24
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/psci.c
23
--- a/hw/net/imx_fec.c
26
+++ b/target/arm/psci.c
24
+++ b/hw/net/imx_fec.c
27
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
28
26
return 0;
29
bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
30
{
31
- /* Return true if the r0/x0 value indicates a PSCI call and
32
- * the exception type matches the configured PSCI conduit. This is
33
- * called before the SMC/HVC instruction is executed, to decide whether
34
- * we should treat it as a PSCI call or with the architecturally
35
+ /*
36
+ * Return true if the exception type matches the configured PSCI conduit.
37
+ * This is called before the SMC/HVC instruction is executed, to decide
38
+ * whether we should treat it as a PSCI call or with the architecturally
39
* defined behaviour for an SMC or HVC (which might be UNDEF or trap
40
* to EL2 or to EL3).
41
*/
42
- CPUARMState *env = &cpu->env;
43
- uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0];
44
45
switch (excp_type) {
46
case EXCP_HVC:
47
@@ -XXX,XX +XXX,XX @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
48
return false;
49
}
27
}
50
28
51
- switch (param) {
29
- /* 4 bytes for the CRC. */
52
- case QEMU_PSCI_0_2_FN_PSCI_VERSION:
30
- size += 4;
53
- case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
31
crc = cpu_to_be32(crc32(~0, buf, size));
54
- case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
32
+ /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
55
- case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
33
+ size += 4;
56
- case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
34
crc_ptr = (uint8_t *) &crc;
57
- case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
35
58
- case QEMU_PSCI_0_1_FN_CPU_ON:
36
/* Huge frames are truncated. */
59
- case QEMU_PSCI_0_2_FN_CPU_ON:
37
@@ -XXX,XX +XXX,XX @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
60
- case QEMU_PSCI_0_2_FN64_CPU_ON:
38
return 0;
61
- case QEMU_PSCI_0_1_FN_CPU_OFF:
62
- case QEMU_PSCI_0_2_FN_CPU_OFF:
63
- case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
64
- case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
65
- case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
66
- case QEMU_PSCI_0_1_FN_MIGRATE:
67
- case QEMU_PSCI_0_2_FN_MIGRATE:
68
- return true;
69
- default:
70
- return false;
71
- }
72
+ return true;
73
}
74
75
void arm_handle_psci_call(ARMCPU *cpu)
76
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
77
break;
78
case QEMU_PSCI_0_1_FN_MIGRATE:
79
case QEMU_PSCI_0_2_FN_MIGRATE:
80
+ default:
81
ret = QEMU_PSCI_RET_NOT_SUPPORTED;
82
break;
83
- default:
84
- g_assert_not_reached();
85
}
39
}
86
40
87
err:
41
- /* 4 bytes for the CRC. */
42
- size += 4;
43
crc = cpu_to_be32(crc32(~0, buf, size));
44
+ /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
45
+ size += 4;
46
crc_ptr = (uint8_t *) &crc;
47
48
if (shift16) {
88
--
49
--
89
2.20.1
50
2.25.1
90
91
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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