Arm queue; not huge but I figured I might as well send it out since

I've been doing code review today and there's no queue of unprocessed

pullreqs...

thanks

-- PMM

The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112

for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:

ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)

* arm: Support emulation of ARMv8.4-TTST extension

* arm: Update cpu.h ID register field definitions

* arm: Fix breakage of XScale instruction emulation

* hw/net/lan9118: Fix RX Status FIFO PEEK value

* npcm7xx: Add ADC and PWM emulation

* ui/cocoa: Make "open docs" help menu entry work again when binary

is run from the build tree

* ui/cocoa: Fix openFile: deprecation on Big Sur

* docs: Add qemu-storage-daemon(1) manpage to meson.build

* docs: Build and install all the docs in a single manual

Hao Wu (6):

hw/misc: Add clock converter in NPCM7XX CLK module

hw/timer: Refactor NPCM7XX Timer to use CLK clock

hw/adc: Add an ADC module for NPCM7XX

hw/misc: Add a PWM module for NPCM7XX

hw/misc: Add QTest for NPCM7XX PWM Module

hw/*: Use type casting for SysBusDevice in NPCM7XX

Leif Lindholm (6):

target/arm: fix typo in cpu.h ID_AA64PFR1 field name

target/arm: make ARMCPU.clidr 64-bit

target/arm: make ARMCPU.ctr 64-bit

target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

target/arm: add aarch64 ID register fields to cpu.h

target/arm: add aarch32 ID register fields to cpu.h

Peter Maydell (5):

docs: Add qemu-storage-daemon(1) manpage to meson.build

docs: Build and install all the docs in a single manual

target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns

hw/net/lan9118: Fix RX Status FIFO PEEK value

hw/net/lan9118: Add symbolic constants for register offsets

Roman Bolshakov (2):

ui/cocoa: Update path to docs in build tree

ui/cocoa: Fix openFile: deprecation on Big Sur

Rémi Denis-Courmont (2):

target/arm: ARMv8.4-TTST extension

target/arm: enable Small Translation tables in max CPU

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

This adds for the Small Translation tables extension in AArch64 state.

target/arm/cpu.h | 5 +++++

target/arm/helper.c | 15 +++++++++++++--

2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)

return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;

+static inline bool isar_feature_aa64_st(const ARMISARegisters *id)

+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;

static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)

{

return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;

@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,

{

uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;

bool epd, hpd, using16k, using64k;

- int select, tsz, tbi;

+ int select, tsz, tbi, max_tsz;

if (!regime_has_2_ranges(mmu_idx)) {

select = 0;

@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,

hpd = extract64(tcr, 42, 1);

}

}

- tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */

+

+ if (cpu_isar_feature(aa64_st, env_archcpu(env))) {

+ max_tsz = 48 - using64k;

+ } else {

+ max_tsz = 39;

+ }

+

+ tsz = MIN(tsz, max_tsz);

tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */

/* Present TBI as a composite with TBID. */

if (!aarch64 || stride == 9) {

/* AArch32 or 4KB pages */

startlevel = 2 - sl0;

+

+ if (cpu_isar_feature(aa64_st, cpu)) {

+ startlevel &= 3;

+ }

} else {

/* 16KB or 64KB pages */

startlevel = 3 - sl0;

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

target/arm/cpu64.c | 1 +

1 file changed, 1 insertion(+)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

t = cpu->isar.id_aa64mmfr2;

t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);

t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */

+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */

cpu->isar.id_aa64mmfr2 = t;

/* Replicate the same data to the 32-bit id registers. */

From: Leif Lindholm <leif@nuviainc.com>

target/arm/cpu.h | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, RAS, 28, 4)

FIELD(ID_AA64PFR0, SVE, 32, 4)

FIELD(ID_AA64PFR1, BT, 0, 4)

-FIELD(ID_AA64PFR1, SBSS, 4, 4)

+FIELD(ID_AA64PFR1, SSBS, 4, 4)

FIELD(ID_AA64PFR1, MTE, 8, 4)

FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)

From: Leif Lindholm <leif@nuviainc.com>

The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit

32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.

Extend the clidr field to be able to hold this context.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

target/arm/cpu.h | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ struct ARMCPU {

uint32_t id_afr0;

uint64_t id_aa64afr0;

uint64_t id_aa64afr1;

- uint32_t clidr;

+ uint64_t clidr;

uint64_t mp_affinity; /* MP ID without feature bits */

/* The elements of this array are the CCSIDR values for each cache,

* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.