[PATCH 0/1] hw: aspeed_gpio: Fix pin I/O type declarations

pdel@fb.com posted 1 patch 4 years, 4 months ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/20210928032456.3192603-1-pdel@fb.com
Maintainers: Peter Maydell <peter.maydell@linaro.org>, Joel Stanley <joel@jms.id.au>, Andrew Jeffery <andrew@aj.id.au>, "Cédric Le Goater" <clg@kaod.org>
hw/gpio/aspeed_gpio.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
[PATCH 0/1] hw: aspeed_gpio: Fix pin I/O type declarations
Posted by pdel@fb.com 4 years, 4 months ago
From: Peter Delevoryas <pdel@fb.com>

In the Aspeed chips, the GPIO pins are mostly labeled in groups of 8,
but some of the groups only have 4 elements. Also, most pins have input
and output capabilities, but some are strictly input or strictly output
pins. We have some arrays that describe the I/O capabilities of each pin
for each chip.

A few of the declarations for the AST2500 and AST2600 in aspeed_gpio.c
don't seem to match the datasheet, probably because of confusion over
the association between big-endian uint32 literals (right-to-left) and
the array of group labels (left-to-right). I checked the AST2400 too,
but it was correct and didn't need any changes.

We might want to consider replacing the u32's with u8's and putting them
together into a u32 programmatically, or perhaps implicitly performing a
big-endian to little-endian conversion, something to make it easier to
read.

Peter Delevoryas (1):
  hw: aspeed_gpio: Fix pin I/O type declarations

 hw/gpio/aspeed_gpio.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

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