1 | The following changes since commit 57b6f58c1d0df757c9311496c32d502925056894: | 1 | v3: One more try to fix macos issues. |
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2 | 2 | ||
3 | Merge remote-tracking branch 'remotes/hreitz/tags/pull-block-2021-09-15' into staging (2021-09-15 18:55:59 +0100) | 3 | |
4 | r~ | ||
5 | |||
6 | |||
7 | |||
8 | The following changes since commit e0209297cddd5e10a07e15fac5cca7aa1a8e0e59: | ||
9 | |||
10 | Merge tag 'pull-ufs-20250217' of https://gitlab.com/jeuk20.kim/qemu into staging (2025-02-18 10:58:48 +0800) | ||
4 | 11 | ||
5 | are available in the Git repository at: | 12 | are available in the Git repository at: |
6 | 13 | ||
7 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210916 | 14 | https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-3 |
8 | 15 | ||
9 | for you to fetch changes up to 50febfe212f24a9b91b4224d03f653415fddf8e1: | 16 | for you to fetch changes up to e726f65867087d86436de05e9f372a86ec1381a6: |
10 | 17 | ||
11 | tcg/mips: Drop special alignment for code_gen_buffer (2021-09-16 09:37:39 -0400) | 18 | tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-18 08:29:03 -0800) |
12 | 19 | ||
13 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
14 | Restrict cpu_has_work to sysemu, and move to AccelOpsClass. | 21 | tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS |
15 | Move cpu_signal_handler declaration out of target/. | 22 | tcg: Cleanups after disallowing 64-on-32 |
16 | Misc tcg/mips/ cleanups. | 23 | tcg: Introduce constraint for zero register |
24 | tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 | ||
25 | tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2 | ||
26 | linux-user: Move TARGET_SA_RESTORER out of generic/signal.h | ||
27 | linux-user: Fix alignment when unmapping excess reservation | ||
28 | target/sparc: Fix register selection for all F*TOx and FxTO* instructions | ||
29 | target/sparc: Fix gdbstub incorrectly handling registers f32-f62 | ||
30 | target/sparc: fake UltraSPARC T1 PCR and PIC registers | ||
17 | 31 | ||
18 | ---------------------------------------------------------------- | 32 | ---------------------------------------------------------------- |
19 | Philippe Mathieu-Daudé (30): | 33 | Andreas Schwab (1): |
20 | accel/tcg: Restrict cpu_handle_halt() to sysemu | 34 | linux-user: Move TARGET_SA_RESTORER out of generic/signal.h |
21 | hw/core: Restrict cpu_has_work() to sysemu | ||
22 | hw/core: Un-inline cpu_has_work() | ||
23 | sysemu: Introduce AccelOpsClass::has_work() | ||
24 | accel/kvm: Implement AccelOpsClass::has_work() | ||
25 | accel/whpx: Implement AccelOpsClass::has_work() | ||
26 | accel/tcg: Implement AccelOpsClass::has_work() as stub | ||
27 | target/alpha: Restrict has_work() handler to sysemu | ||
28 | target/arm: Restrict has_work() handler to sysemu and TCG | ||
29 | target/avr: Restrict has_work() handler to sysemu | ||
30 | target/cris: Restrict has_work() handler to sysemu | ||
31 | target/hexagon: Remove unused has_work() handler | ||
32 | target/hppa: Restrict has_work() handler to sysemu | ||
33 | target/i386: Restrict has_work() handler to sysemu and TCG | ||
34 | target/m68k: Restrict has_work() handler to sysemu | ||
35 | target/microblaze: Restrict has_work() handler to sysemu | ||
36 | target/mips: Restrict has_work() handler to sysemu and TCG | ||
37 | target/nios2: Restrict has_work() handler to sysemu | ||
38 | target/openrisc: Restrict has_work() handler to sysemu | ||
39 | target/ppc: Introduce PowerPCCPUClass::has_work() | ||
40 | target/ppc: Restrict has_work() handlers to sysemu and TCG | ||
41 | target/riscv: Restrict has_work() handler to sysemu and TCG | ||
42 | target/rx: Restrict has_work() handler to sysemu | ||
43 | target/s390x: Restrict has_work() handler to sysemu and TCG | ||
44 | target/sh4: Restrict has_work() handler to sysemu | ||
45 | target/sparc: Remove pointless use of CONFIG_TCG definition | ||
46 | target/sparc: Restrict has_work() handler to sysemu | ||
47 | target/tricore: Restrict has_work() handler to sysemu | ||
48 | target/xtensa: Restrict has_work() handler to sysemu | ||
49 | accel: Add missing AccelOpsClass::has_work() and drop SysemuCPUOps one | ||
50 | 35 | ||
51 | Richard Henderson (5): | 36 | Artyom Tarasenko (1): |
52 | include/exec: Move cpu_signal_handler declaration | 37 | target/sparc: fake UltraSPARC T1 PCR and PIC registers |
53 | tcg/mips: Drop inline markers | ||
54 | tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr | ||
55 | tcg/mips: Unset TCG_TARGET_HAS_direct_jump | ||
56 | tcg/mips: Drop special alignment for code_gen_buffer | ||
57 | 38 | ||
58 | include/exec/exec-all.h | 13 +++++ | 39 | Fabiano Rosas (1): |
59 | include/hw/core/cpu.h | 28 ++++------ | 40 | elfload: Fix alignment when unmapping excess reservation |
60 | include/hw/core/tcg-cpu-ops.h | 4 ++ | ||
61 | include/sysemu/accel-ops.h | 5 ++ | ||
62 | target/alpha/cpu.h | 6 --- | ||
63 | target/arm/cpu.h | 7 --- | ||
64 | target/avr/cpu.h | 2 - | ||
65 | target/cris/cpu.h | 8 --- | ||
66 | target/hexagon/cpu.h | 3 -- | ||
67 | target/hppa/cpu.h | 3 -- | ||
68 | target/i386/cpu.h | 7 --- | ||
69 | target/m68k/cpu.h | 8 --- | ||
70 | target/microblaze/cpu.h | 7 --- | ||
71 | target/mips/cpu.h | 3 -- | ||
72 | target/mips/internal.h | 2 - | ||
73 | target/nios2/cpu.h | 2 - | ||
74 | target/openrisc/cpu.h | 2 - | ||
75 | target/ppc/cpu-qom.h | 3 ++ | ||
76 | target/ppc/cpu.h | 7 --- | ||
77 | target/riscv/cpu.h | 2 - | ||
78 | target/rx/cpu.h | 4 -- | ||
79 | target/s390x/cpu.h | 7 --- | ||
80 | target/sh4/cpu.h | 3 -- | ||
81 | target/sparc/cpu.h | 2 - | ||
82 | target/tricore/cpu.h | 2 - | ||
83 | target/xtensa/cpu.h | 2 - | ||
84 | tcg/mips/tcg-target.h | 12 ++--- | ||
85 | accel/hvf/hvf-accel-ops.c | 6 +++ | ||
86 | accel/kvm/kvm-accel-ops.c | 6 +++ | ||
87 | accel/qtest/qtest.c | 6 +++ | ||
88 | accel/tcg/cpu-exec.c | 6 ++- | ||
89 | accel/tcg/tcg-accel-ops.c | 12 +++++ | ||
90 | accel/xen/xen-all.c | 6 +++ | ||
91 | hw/core/cpu-common.c | 6 --- | ||
92 | softmmu/cpus.c | 10 ++-- | ||
93 | target/alpha/cpu.c | 4 +- | ||
94 | target/arm/cpu.c | 7 ++- | ||
95 | target/avr/cpu.c | 2 +- | ||
96 | target/cris/cpu.c | 4 +- | ||
97 | target/hexagon/cpu.c | 6 --- | ||
98 | target/hppa/cpu.c | 4 +- | ||
99 | target/i386/cpu.c | 6 --- | ||
100 | target/i386/hax/hax-accel-ops.c | 6 +++ | ||
101 | target/i386/nvmm/nvmm-accel-ops.c | 6 +++ | ||
102 | target/i386/tcg/tcg-cpu.c | 8 ++- | ||
103 | target/i386/whpx/whpx-accel-ops.c | 6 +++ | ||
104 | target/m68k/cpu.c | 4 +- | ||
105 | target/microblaze/cpu.c | 8 +-- | ||
106 | target/mips/cpu.c | 4 +- | ||
107 | target/nios2/cpu.c | 4 +- | ||
108 | target/openrisc/cpu.c | 4 +- | ||
109 | target/ppc/cpu_init.c | 37 ++++++++++---- | ||
110 | target/riscv/cpu.c | 8 ++- | ||
111 | target/rx/cpu.c | 4 +- | ||
112 | target/s390x/cpu.c | 4 +- | ||
113 | target/sh4/cpu.c | 5 +- | ||
114 | target/sparc/cpu.c | 6 +-- | ||
115 | target/tricore/cpu.c | 6 ++- | ||
116 | target/xtensa/cpu.c | 14 ++--- | ||
117 | tcg/region.c | 91 --------------------------------- | ||
118 | tcg/mips/tcg-target.c.inc | 105 +++++++++++++------------------------- | ||
119 | 61 files changed, 233 insertions(+), 342 deletions(-) | ||
120 | 41 | ||
42 | Mikael Szreder (2): | ||
43 | target/sparc: Fix register selection for all F*TOx and FxTO* instructions | ||
44 | target/sparc: Fix gdbstub incorrectly handling registers f32-f62 | ||
45 | |||
46 | Richard Henderson (23): | ||
47 | tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS | ||
48 | tcg: Remove TCG_OVERSIZED_GUEST | ||
49 | tcg: Drop support for two address registers in gen_ldst | ||
50 | tcg: Merge INDEX_op_qemu_*_{a32,a64}_* | ||
51 | tcg/arm: Drop addrhi from prepare_host_addr | ||
52 | tcg/i386: Drop addrhi from prepare_host_addr | ||
53 | tcg/mips: Drop addrhi from prepare_host_addr | ||
54 | tcg/ppc: Drop addrhi from prepare_host_addr | ||
55 | tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst | ||
56 | plugins: Fix qemu_plugin_read_memory_vaddr parameters | ||
57 | accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page | ||
58 | target/loongarch: Use VADDR_PRIx for logging pc_next | ||
59 | target/mips: Use VADDR_PRIx for logging pc_next | ||
60 | include/exec: Change vaddr to uintptr_t | ||
61 | include/exec: Use uintptr_t in CPUTLBEntry | ||
62 | tcg: Introduce the 'z' constraint for a hardware zero register | ||
63 | tcg/aarch64: Use 'z' constraint | ||
64 | tcg/loongarch64: Use 'z' constraint | ||
65 | tcg/mips: Use 'z' constraint | ||
66 | tcg/riscv: Use 'z' constraint | ||
67 | tcg/sparc64: Use 'z' constraint | ||
68 | tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2 | ||
69 | tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 | ||
70 | |||
71 | include/exec/tlb-common.h | 10 +- | ||
72 | include/exec/vaddr.h | 16 +- | ||
73 | include/qemu/atomic.h | 18 +- | ||
74 | include/tcg/oversized-guest.h | 23 --- | ||
75 | include/tcg/tcg-opc.h | 28 +-- | ||
76 | include/tcg/tcg.h | 3 +- | ||
77 | linux-user/aarch64/target_signal.h | 2 + | ||
78 | linux-user/arm/target_signal.h | 2 + | ||
79 | linux-user/generic/signal.h | 1 - | ||
80 | linux-user/i386/target_signal.h | 2 + | ||
81 | linux-user/m68k/target_signal.h | 1 + | ||
82 | linux-user/microblaze/target_signal.h | 2 + | ||
83 | linux-user/ppc/target_signal.h | 2 + | ||
84 | linux-user/s390x/target_signal.h | 2 + | ||
85 | linux-user/sh4/target_signal.h | 2 + | ||
86 | linux-user/x86_64/target_signal.h | 2 + | ||
87 | linux-user/xtensa/target_signal.h | 2 + | ||
88 | tcg/aarch64/tcg-target-con-set.h | 12 +- | ||
89 | tcg/aarch64/tcg-target.h | 2 + | ||
90 | tcg/loongarch64/tcg-target-con-set.h | 15 +- | ||
91 | tcg/loongarch64/tcg-target-con-str.h | 1 - | ||
92 | tcg/loongarch64/tcg-target-has.h | 2 - | ||
93 | tcg/loongarch64/tcg-target.h | 2 + | ||
94 | tcg/mips/tcg-target-con-set.h | 26 +-- | ||
95 | tcg/mips/tcg-target-con-str.h | 1 - | ||
96 | tcg/mips/tcg-target.h | 2 + | ||
97 | tcg/riscv/tcg-target-con-set.h | 10 +- | ||
98 | tcg/riscv/tcg-target-con-str.h | 1 - | ||
99 | tcg/riscv/tcg-target-has.h | 2 - | ||
100 | tcg/riscv/tcg-target.h | 2 + | ||
101 | tcg/sparc64/tcg-target-con-set.h | 12 +- | ||
102 | tcg/sparc64/tcg-target-con-str.h | 1 - | ||
103 | tcg/sparc64/tcg-target.h | 3 +- | ||
104 | tcg/tci/tcg-target.h | 1 - | ||
105 | accel/tcg/cputlb.c | 32 +--- | ||
106 | accel/tcg/tcg-all.c | 9 +- | ||
107 | linux-user/elfload.c | 4 +- | ||
108 | plugins/api.c | 2 +- | ||
109 | target/arm/ptw.c | 34 ---- | ||
110 | target/loongarch/tcg/translate.c | 2 +- | ||
111 | target/mips/tcg/octeon_translate.c | 4 +- | ||
112 | target/riscv/cpu_helper.c | 13 +- | ||
113 | target/sparc/gdbstub.c | 18 +- | ||
114 | target/sparc/translate.c | 19 +++ | ||
115 | tcg/optimize.c | 21 +-- | ||
116 | tcg/tcg-op-ldst.c | 103 +++-------- | ||
117 | tcg/tcg.c | 97 +++++------ | ||
118 | tcg/tci.c | 119 +++---------- | ||
119 | docs/devel/multi-thread-tcg.rst | 1 - | ||
120 | docs/devel/tcg-ops.rst | 4 +- | ||
121 | target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +- | ||
122 | target/sparc/insns.decode | 19 ++- | ||
123 | tcg/aarch64/tcg-target.c.inc | 86 ++++------ | ||
124 | tcg/arm/tcg-target.c.inc | 114 ++++--------- | ||
125 | tcg/i386/tcg-target.c.inc | 190 +++++---------------- | ||
126 | tcg/loongarch64/tcg-target.c.inc | 72 +++----- | ||
127 | tcg/mips/tcg-target.c.inc | 169 ++++++------------ | ||
128 | tcg/ppc/tcg-target.c.inc | 164 +++++------------- | ||
129 | tcg/riscv/tcg-target.c.inc | 56 +++--- | ||
130 | tcg/s390x/tcg-target.c.inc | 40 ++--- | ||
131 | tcg/sparc64/tcg-target.c.inc | 45 ++--- | ||
132 | tcg/tci/tcg-target.c.inc | 60 ++----- | ||
133 | 62 files changed, 550 insertions(+), 1162 deletions(-) | ||
134 | delete mode 100644 include/tcg/oversized-guest.h | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | There is nothing target specific about this. The implementation | ||
2 | is host specific, but the declaration is 100% common. | ||
3 | 1 | ||
4 | Reviewed-By: Warner Losh <imp@bsdimp.com> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | --- | ||
9 | include/exec/exec-all.h | 13 +++++++++++++ | ||
10 | target/alpha/cpu.h | 6 ------ | ||
11 | target/arm/cpu.h | 7 ------- | ||
12 | target/avr/cpu.h | 2 -- | ||
13 | target/cris/cpu.h | 8 -------- | ||
14 | target/hexagon/cpu.h | 3 --- | ||
15 | target/hppa/cpu.h | 3 --- | ||
16 | target/i386/cpu.h | 7 ------- | ||
17 | target/m68k/cpu.h | 8 -------- | ||
18 | target/microblaze/cpu.h | 7 ------- | ||
19 | target/mips/cpu.h | 3 --- | ||
20 | target/mips/internal.h | 2 -- | ||
21 | target/nios2/cpu.h | 2 -- | ||
22 | target/openrisc/cpu.h | 2 -- | ||
23 | target/ppc/cpu.h | 7 ------- | ||
24 | target/riscv/cpu.h | 2 -- | ||
25 | target/rx/cpu.h | 4 ---- | ||
26 | target/s390x/cpu.h | 7 ------- | ||
27 | target/sh4/cpu.h | 3 --- | ||
28 | target/sparc/cpu.h | 2 -- | ||
29 | target/tricore/cpu.h | 2 -- | ||
30 | target/xtensa/cpu.h | 2 -- | ||
31 | 22 files changed, 13 insertions(+), 89 deletions(-) | ||
32 | |||
33 | diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/include/exec/exec-all.h | ||
36 | +++ b/include/exec/exec-all.h | ||
37 | @@ -XXX,XX +XXX,XX @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, | ||
38 | } | ||
39 | return addr; | ||
40 | } | ||
41 | + | ||
42 | +/** | ||
43 | + * cpu_signal_handler | ||
44 | + * @signum: host signal number | ||
45 | + * @pinfo: host siginfo_t | ||
46 | + * @puc: host ucontext_t | ||
47 | + * | ||
48 | + * To be called from the SIGBUS and SIGSEGV signal handler to inform the | ||
49 | + * virtual cpu of exceptions. Returns true if the signal was handled by | ||
50 | + * the virtual CPU. | ||
51 | + */ | ||
52 | +int cpu_signal_handler(int signum, void *pinfo, void *puc); | ||
53 | + | ||
54 | #else | ||
55 | static inline void mmap_lock(void) {} | ||
56 | static inline void mmap_unlock(void) {} | ||
57 | diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/target/alpha/cpu.h | ||
60 | +++ b/target/alpha/cpu.h | ||
61 | @@ -XXX,XX +XXX,XX @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, | ||
62 | int mmu_idx, uintptr_t retaddr); | ||
63 | |||
64 | #define cpu_list alpha_cpu_list | ||
65 | -#define cpu_signal_handler cpu_alpha_signal_handler | ||
66 | |||
67 | typedef CPUAlphaState CPUArchState; | ||
68 | typedef AlphaCPU ArchCPU; | ||
69 | @@ -XXX,XX +XXX,XX @@ void alpha_translate_init(void); | ||
70 | #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU | ||
71 | |||
72 | void alpha_cpu_list(void); | ||
73 | -/* you can call this signal handler from your SIGBUS and SIGSEGV | ||
74 | - signal handlers to inform the virtual CPU of exceptions. non zero | ||
75 | - is returned if the signal was handled by the virtual CPU. */ | ||
76 | -int cpu_alpha_signal_handler(int host_signum, void *pinfo, | ||
77 | - void *puc); | ||
78 | bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
79 | MMUAccessType access_type, int mmu_idx, | ||
80 | bool probe, uintptr_t retaddr); | ||
81 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
82 | index XXXXXXX..XXXXXXX 100644 | ||
83 | --- a/target/arm/cpu.h | ||
84 | +++ b/target/arm/cpu.h | ||
85 | @@ -XXX,XX +XXX,XX @@ static inline bool is_a64(CPUARMState *env) | ||
86 | return env->aarch64; | ||
87 | } | ||
88 | |||
89 | -/* you can call this signal handler from your SIGBUS and SIGSEGV | ||
90 | - signal handlers to inform the virtual CPU of exceptions. non zero | ||
91 | - is returned if the signal was handled by the virtual CPU. */ | ||
92 | -int cpu_arm_signal_handler(int host_signum, void *pinfo, | ||
93 | - void *puc); | ||
94 | - | ||
95 | /** | ||
96 | * pmu_op_start/finish | ||
97 | * @env: CPUARMState | ||
98 | @@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); | ||
99 | #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) | ||
100 | #define CPU_RESOLVING_TYPE TYPE_ARM_CPU | ||
101 | |||
102 | -#define cpu_signal_handler cpu_arm_signal_handler | ||
103 | #define cpu_list arm_cpu_list | ||
104 | |||
105 | /* ARM has the following "translation regimes" (as the ARM ARM calls them): | ||
106 | diff --git a/target/avr/cpu.h b/target/avr/cpu.h | ||
107 | index XXXXXXX..XXXXXXX 100644 | ||
108 | --- a/target/avr/cpu.h | ||
109 | +++ b/target/avr/cpu.h | ||
110 | @@ -XXX,XX +XXX,XX @@ static inline void set_avr_feature(CPUAVRState *env, int feature) | ||
111 | } | ||
112 | |||
113 | #define cpu_list avr_cpu_list | ||
114 | -#define cpu_signal_handler cpu_avr_signal_handler | ||
115 | #define cpu_mmu_index avr_cpu_mmu_index | ||
116 | |||
117 | static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) | ||
118 | @@ -XXX,XX +XXX,XX @@ void avr_cpu_tcg_init(void); | ||
119 | |||
120 | void avr_cpu_list(void); | ||
121 | int cpu_avr_exec(CPUState *cpu); | ||
122 | -int cpu_avr_signal_handler(int host_signum, void *pinfo, void *puc); | ||
123 | int avr_cpu_memory_rw_debug(CPUState *cs, vaddr address, uint8_t *buf, | ||
124 | int len, bool is_write); | ||
125 | |||
126 | diff --git a/target/cris/cpu.h b/target/cris/cpu.h | ||
127 | index XXXXXXX..XXXXXXX 100644 | ||
128 | --- a/target/cris/cpu.h | ||
129 | +++ b/target/cris/cpu.h | ||
130 | @@ -XXX,XX +XXX,XX @@ int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); | ||
131 | int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); | ||
132 | int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | ||
133 | |||
134 | -/* you can call this signal handler from your SIGBUS and SIGSEGV | ||
135 | - signal handlers to inform the virtual CPU of exceptions. non zero | ||
136 | - is returned if the signal was handled by the virtual CPU. */ | ||
137 | -int cpu_cris_signal_handler(int host_signum, void *pinfo, | ||
138 | - void *puc); | ||
139 | - | ||
140 | void cris_initialize_tcg(void); | ||
141 | void cris_initialize_crisv10_tcg(void); | ||
142 | |||
143 | @@ -XXX,XX +XXX,XX @@ enum { | ||
144 | #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) | ||
145 | #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU | ||
146 | |||
147 | -#define cpu_signal_handler cpu_cris_signal_handler | ||
148 | - | ||
149 | /* MMU modes definitions */ | ||
150 | #define MMU_USER_IDX 1 | ||
151 | static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) | ||
152 | diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h | ||
153 | index XXXXXXX..XXXXXXX 100644 | ||
154 | --- a/target/hexagon/cpu.h | ||
155 | +++ b/target/hexagon/cpu.h | ||
156 | @@ -XXX,XX +XXX,XX @@ typedef struct HexagonCPU { | ||
157 | |||
158 | #include "cpu_bits.h" | ||
159 | |||
160 | -#define cpu_signal_handler cpu_hexagon_signal_handler | ||
161 | -int cpu_hexagon_signal_handler(int host_signum, void *pinfo, void *puc); | ||
162 | - | ||
163 | static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc, | ||
164 | target_ulong *cs_base, uint32_t *flags) | ||
165 | { | ||
166 | diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h | ||
167 | index XXXXXXX..XXXXXXX 100644 | ||
168 | --- a/target/hppa/cpu.h | ||
169 | +++ b/target/hppa/cpu.h | ||
170 | @@ -XXX,XX +XXX,XX @@ static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } | ||
171 | void cpu_hppa_change_prot_id(CPUHPPAState *env); | ||
172 | #endif | ||
173 | |||
174 | -#define cpu_signal_handler cpu_hppa_signal_handler | ||
175 | - | ||
176 | -int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); | ||
177 | hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); | ||
178 | int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); | ||
179 | int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | ||
180 | diff --git a/target/i386/cpu.h b/target/i386/cpu.h | ||
181 | index XXXXXXX..XXXXXXX 100644 | ||
182 | --- a/target/i386/cpu.h | ||
183 | +++ b/target/i386/cpu.h | ||
184 | @@ -XXX,XX +XXX,XX @@ void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); | ||
185 | void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); | ||
186 | void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); | ||
187 | |||
188 | -/* you can call this signal handler from your SIGBUS and SIGSEGV | ||
189 | - signal handlers to inform the virtual CPU of exceptions. non zero | ||
190 | - is returned if the signal was handled by the virtual CPU. */ | ||
191 | -int cpu_x86_signal_handler(int host_signum, void *pinfo, | ||
192 | - void *puc); | ||
193 | - | ||
194 | /* cpu.c */ | ||
195 | void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, | ||
196 | uint32_t vendor2, uint32_t vendor3); | ||
197 | @@ -XXX,XX +XXX,XX @@ uint64_t cpu_get_tsc(CPUX86State *env); | ||
198 | #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") | ||
199 | #endif | ||
200 | |||
201 | -#define cpu_signal_handler cpu_x86_signal_handler | ||
202 | #define cpu_list x86_cpu_list | ||
203 | |||
204 | /* MMU modes definitions */ | ||
205 | diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h | ||
206 | index XXXXXXX..XXXXXXX 100644 | ||
207 | --- a/target/m68k/cpu.h | ||
208 | +++ b/target/m68k/cpu.h | ||
209 | @@ -XXX,XX +XXX,XX @@ int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | ||
210 | |||
211 | void m68k_tcg_init(void); | ||
212 | void m68k_cpu_init_gdb(M68kCPU *cpu); | ||
213 | -/* | ||
214 | - * you can call this signal handler from your SIGBUS and SIGSEGV | ||
215 | - * signal handlers to inform the virtual CPU of exceptions. non zero | ||
216 | - * is returned if the signal was handled by the virtual CPU. | ||
217 | - */ | ||
218 | -int cpu_m68k_signal_handler(int host_signum, void *pinfo, | ||
219 | - void *puc); | ||
220 | uint32_t cpu_m68k_get_ccr(CPUM68KState *env); | ||
221 | void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t); | ||
222 | void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); | ||
223 | @@ -XXX,XX +XXX,XX @@ enum { | ||
224 | #define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX | ||
225 | #define CPU_RESOLVING_TYPE TYPE_M68K_CPU | ||
226 | |||
227 | -#define cpu_signal_handler cpu_m68k_signal_handler | ||
228 | #define cpu_list m68k_cpu_list | ||
229 | |||
230 | /* MMU modes definitions */ | ||
231 | diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h | ||
232 | index XXXXXXX..XXXXXXX 100644 | ||
233 | --- a/target/microblaze/cpu.h | ||
234 | +++ b/target/microblaze/cpu.h | ||
235 | @@ -XXX,XX +XXX,XX @@ static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val) | ||
236 | } | ||
237 | |||
238 | void mb_tcg_init(void); | ||
239 | -/* you can call this signal handler from your SIGBUS and SIGSEGV | ||
240 | - signal handlers to inform the virtual CPU of exceptions. non zero | ||
241 | - is returned if the signal was handled by the virtual CPU. */ | ||
242 | -int cpu_mb_signal_handler(int host_signum, void *pinfo, | ||
243 | - void *puc); | ||
244 | |||
245 | #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU | ||
246 | |||
247 | -#define cpu_signal_handler cpu_mb_signal_handler | ||
248 | - | ||
249 | /* MMU modes definitions */ | ||
250 | #define MMU_NOMMU_IDX 0 | ||
251 | #define MMU_KERNEL_IDX 1 | ||
252 | diff --git a/target/mips/cpu.h b/target/mips/cpu.h | ||
253 | index XXXXXXX..XXXXXXX 100644 | ||
254 | --- a/target/mips/cpu.h | ||
255 | +++ b/target/mips/cpu.h | ||
256 | @@ -XXX,XX +XXX,XX @@ struct MIPSCPU { | ||
257 | |||
258 | void mips_cpu_list(void); | ||
259 | |||
260 | -#define cpu_signal_handler cpu_mips_signal_handler | ||
261 | #define cpu_list mips_cpu_list | ||
262 | |||
263 | extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); | ||
264 | @@ -XXX,XX +XXX,XX @@ enum { | ||
265 | */ | ||
266 | #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 | ||
267 | |||
268 | -int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); | ||
269 | - | ||
270 | #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU | ||
271 | #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX | ||
272 | #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU | ||
273 | diff --git a/target/mips/internal.h b/target/mips/internal.h | ||
274 | index XXXXXXX..XXXXXXX 100644 | ||
275 | --- a/target/mips/internal.h | ||
276 | +++ b/target/mips/internal.h | ||
277 | @@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_mips_cpu; | ||
278 | |||
279 | #endif /* !CONFIG_USER_ONLY */ | ||
280 | |||
281 | -#define cpu_signal_handler cpu_mips_signal_handler | ||
282 | - | ||
283 | static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) | ||
284 | { | ||
285 | return (env->CP0_Status & (1 << CP0St_IE)) && | ||
286 | diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h | ||
287 | index XXXXXXX..XXXXXXX 100644 | ||
288 | --- a/target/nios2/cpu.h | ||
289 | +++ b/target/nios2/cpu.h | ||
290 | @@ -XXX,XX +XXX,XX @@ struct Nios2CPU { | ||
291 | |||
292 | void nios2_tcg_init(void); | ||
293 | void nios2_cpu_do_interrupt(CPUState *cs); | ||
294 | -int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc); | ||
295 | void dump_mmu(CPUNios2State *env); | ||
296 | void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); | ||
297 | hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | ||
298 | @@ -XXX,XX +XXX,XX @@ void do_nios2_semihosting(CPUNios2State *env); | ||
299 | #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU | ||
300 | |||
301 | #define cpu_gen_code cpu_nios2_gen_code | ||
302 | -#define cpu_signal_handler cpu_nios2_signal_handler | ||
303 | |||
304 | #define CPU_SAVE_VERSION 1 | ||
305 | |||
306 | diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h | ||
307 | index XXXXXXX..XXXXXXX 100644 | ||
308 | --- a/target/openrisc/cpu.h | ||
309 | +++ b/target/openrisc/cpu.h | ||
310 | @@ -XXX,XX +XXX,XX @@ void openrisc_translate_init(void); | ||
311 | bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
312 | MMUAccessType access_type, int mmu_idx, | ||
313 | bool probe, uintptr_t retaddr); | ||
314 | -int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc); | ||
315 | int print_insn_or1k(bfd_vma addr, disassemble_info *info); | ||
316 | |||
317 | #define cpu_list cpu_openrisc_list | ||
318 | -#define cpu_signal_handler cpu_openrisc_signal_handler | ||
319 | |||
320 | #ifndef CONFIG_USER_ONLY | ||
321 | extern const VMStateDescription vmstate_openrisc_cpu; | ||
322 | diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h | ||
323 | index XXXXXXX..XXXXXXX 100644 | ||
324 | --- a/target/ppc/cpu.h | ||
325 | +++ b/target/ppc/cpu.h | ||
326 | @@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ppc_cpu; | ||
327 | |||
328 | /*****************************************************************************/ | ||
329 | void ppc_translate_init(void); | ||
330 | -/* | ||
331 | - * you can call this signal handler from your SIGBUS and SIGSEGV | ||
332 | - * signal handlers to inform the virtual CPU of exceptions. non zero | ||
333 | - * is returned if the signal was handled by the virtual CPU. | ||
334 | - */ | ||
335 | -int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc); | ||
336 | bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
337 | MMUAccessType access_type, int mmu_idx, | ||
338 | bool probe, uintptr_t retaddr); | ||
339 | @@ -XXX,XX +XXX,XX @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val); | ||
340 | #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX | ||
341 | #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU | ||
342 | |||
343 | -#define cpu_signal_handler cpu_ppc_signal_handler | ||
344 | #define cpu_list ppc_cpu_list | ||
345 | |||
346 | /* MMU modes definitions */ | ||
347 | diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h | ||
348 | index XXXXXXX..XXXXXXX 100644 | ||
349 | --- a/target/riscv/cpu.h | ||
350 | +++ b/target/riscv/cpu.h | ||
351 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, | ||
352 | char *riscv_isa_string(RISCVCPU *cpu); | ||
353 | void riscv_cpu_list(void); | ||
354 | |||
355 | -#define cpu_signal_handler riscv_cpu_signal_handler | ||
356 | #define cpu_list riscv_cpu_list | ||
357 | #define cpu_mmu_index riscv_cpu_mmu_index | ||
358 | |||
359 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), | ||
360 | void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); | ||
361 | |||
362 | void riscv_translate_init(void); | ||
363 | -int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc); | ||
364 | void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, | ||
365 | uint32_t exception, uintptr_t pc); | ||
366 | |||
367 | diff --git a/target/rx/cpu.h b/target/rx/cpu.h | ||
368 | index XXXXXXX..XXXXXXX 100644 | ||
369 | --- a/target/rx/cpu.h | ||
370 | +++ b/target/rx/cpu.h | ||
371 | @@ -XXX,XX +XXX,XX @@ int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | ||
372 | hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); | ||
373 | |||
374 | void rx_translate_init(void); | ||
375 | -int cpu_rx_signal_handler(int host_signum, void *pinfo, | ||
376 | - void *puc); | ||
377 | - | ||
378 | void rx_cpu_list(void); | ||
379 | void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); | ||
380 | |||
381 | -#define cpu_signal_handler cpu_rx_signal_handler | ||
382 | #define cpu_list rx_cpu_list | ||
383 | |||
384 | #include "exec/cpu-all.h" | ||
385 | diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h | ||
386 | index XXXXXXX..XXXXXXX 100644 | ||
387 | --- a/target/s390x/cpu.h | ||
388 | +++ b/target/s390x/cpu.h | ||
389 | @@ -XXX,XX +XXX,XX @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, | ||
390 | #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) | ||
391 | #define CPU_RESOLVING_TYPE TYPE_S390_CPU | ||
392 | |||
393 | -/* you can call this signal handler from your SIGBUS and SIGSEGV | ||
394 | - signal handlers to inform the virtual CPU of exceptions. non zero | ||
395 | - is returned if the signal was handled by the virtual CPU. */ | ||
396 | -int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); | ||
397 | -#define cpu_signal_handler cpu_s390x_signal_handler | ||
398 | - | ||
399 | - | ||
400 | /* interrupt.c */ | ||
401 | #define RA_IGNORED 0 | ||
402 | void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra); | ||
403 | diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h | ||
404 | index XXXXXXX..XXXXXXX 100644 | ||
405 | --- a/target/sh4/cpu.h | ||
406 | +++ b/target/sh4/cpu.h | ||
407 | @@ -XXX,XX +XXX,XX @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, | ||
408 | int mmu_idx, uintptr_t retaddr); | ||
409 | |||
410 | void sh4_translate_init(void); | ||
411 | -int cpu_sh4_signal_handler(int host_signum, void *pinfo, | ||
412 | - void *puc); | ||
413 | bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
414 | MMUAccessType access_type, int mmu_idx, | ||
415 | bool probe, uintptr_t retaddr); | ||
416 | @@ -XXX,XX +XXX,XX @@ void cpu_load_tlb(CPUSH4State * env); | ||
417 | #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX | ||
418 | #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU | ||
419 | |||
420 | -#define cpu_signal_handler cpu_sh4_signal_handler | ||
421 | #define cpu_list sh4_cpu_list | ||
422 | |||
423 | /* MMU modes definitions */ | ||
424 | diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h | ||
425 | index XXXXXXX..XXXXXXX 100644 | ||
426 | --- a/target/sparc/cpu.h | ||
427 | +++ b/target/sparc/cpu.h | ||
428 | @@ -XXX,XX +XXX,XX @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, | ||
429 | int mmu_idx); | ||
430 | #endif | ||
431 | #endif | ||
432 | -int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); | ||
433 | |||
434 | #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU | ||
435 | #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX | ||
436 | #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU | ||
437 | |||
438 | -#define cpu_signal_handler cpu_sparc_signal_handler | ||
439 | #define cpu_list sparc_cpu_list | ||
440 | |||
441 | /* MMU modes definitions */ | ||
442 | diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h | ||
443 | index XXXXXXX..XXXXXXX 100644 | ||
444 | --- a/target/tricore/cpu.h | ||
445 | +++ b/target/tricore/cpu.h | ||
446 | @@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env); | ||
447 | |||
448 | void tricore_cpu_list(void); | ||
449 | |||
450 | -#define cpu_signal_handler cpu_tricore_signal_handler | ||
451 | #define cpu_list tricore_cpu_list | ||
452 | |||
453 | static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) | ||
454 | @@ -XXX,XX +XXX,XX @@ typedef TriCoreCPU ArchCPU; | ||
455 | |||
456 | void cpu_state_reset(CPUTriCoreState *s); | ||
457 | void tricore_tcg_init(void); | ||
458 | -int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc); | ||
459 | |||
460 | static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc, | ||
461 | target_ulong *cs_base, uint32_t *flags) | ||
462 | diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h | ||
463 | index XXXXXXX..XXXXXXX 100644 | ||
464 | --- a/target/xtensa/cpu.h | ||
465 | +++ b/target/xtensa/cpu.h | ||
466 | @@ -XXX,XX +XXX,XX @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, | ||
467 | MMUAccessType access_type, | ||
468 | int mmu_idx, uintptr_t retaddr); | ||
469 | |||
470 | -#define cpu_signal_handler cpu_xtensa_signal_handler | ||
471 | #define cpu_list xtensa_cpu_list | ||
472 | |||
473 | #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU | ||
474 | @@ -XXX,XX +XXX,XX @@ void check_interrupts(CPUXtensaState *s); | ||
475 | void xtensa_irq_init(CPUXtensaState *env); | ||
476 | qemu_irq *xtensa_get_extints(CPUXtensaState *env); | ||
477 | qemu_irq xtensa_get_runstall(CPUXtensaState *env); | ||
478 | -int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); | ||
479 | void xtensa_cpu_list(void); | ||
480 | void xtensa_sync_window_from_phys(CPUXtensaState *env); | ||
481 | void xtensa_sync_phys_from_window(CPUXtensaState *env); | ||
482 | -- | ||
483 | 2.25.1 | ||
484 | |||
485 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Commit 372579427a5 ("tcg: enable thread-per-vCPU") added the following | ||
4 | comment describing EXCP_HALTED in qemu_tcg_cpu_thread_fn(): | ||
5 | |||
6 | case EXCP_HALTED: | ||
7 | /* during start-up the vCPU is reset and the thread is | ||
8 | * kicked several times. If we don't ensure we go back | ||
9 | * to sleep in the halted state we won't cleanly | ||
10 | * start-up when the vCPU is enabled. | ||
11 | * | ||
12 | * cpu->halted should ensure we sleep in wait_io_event | ||
13 | */ | ||
14 | g_assert(cpu->halted); | ||
15 | break; | ||
16 | |||
17 | qemu_wait_io_event() is sysemu-specific, so we can restrict the | ||
18 | cpu_handle_halt() call in cpu_exec() to system emulation. | ||
19 | |||
20 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
21 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
22 | Message-Id: <20210912172731.789788-2-f4bug@amsat.org> | ||
23 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
24 | --- | ||
25 | accel/tcg/cpu-exec.c | 6 ++++-- | ||
26 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
27 | |||
28 | diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/accel/tcg/cpu-exec.c | ||
31 | +++ b/accel/tcg/cpu-exec.c | ||
32 | @@ -XXX,XX +XXX,XX @@ static inline void tb_add_jump(TranslationBlock *tb, int n, | ||
33 | |||
34 | static inline bool cpu_handle_halt(CPUState *cpu) | ||
35 | { | ||
36 | +#ifndef CONFIG_USER_ONLY | ||
37 | if (cpu->halted) { | ||
38 | -#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) | ||
39 | +#if defined(TARGET_I386) | ||
40 | if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { | ||
41 | X86CPU *x86_cpu = X86_CPU(cpu); | ||
42 | qemu_mutex_lock_iothread(); | ||
43 | @@ -XXX,XX +XXX,XX @@ static inline bool cpu_handle_halt(CPUState *cpu) | ||
44 | cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); | ||
45 | qemu_mutex_unlock_iothread(); | ||
46 | } | ||
47 | -#endif | ||
48 | +#endif /* TARGET_I386 */ | ||
49 | if (!cpu_has_work(cpu)) { | ||
50 | return true; | ||
51 | } | ||
52 | |||
53 | cpu->halted = 0; | ||
54 | } | ||
55 | +#endif /* !CONFIG_USER_ONLY */ | ||
56 | |||
57 | return false; | ||
58 | } | ||
59 | -- | ||
60 | 2.25.1 | ||
61 | |||
62 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | cpu_has_work() is only called from system emulation code. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-3-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | include/hw/core/cpu.h | 32 ++++++++++++++++---------------- | ||
11 | 1 file changed, 16 insertions(+), 16 deletions(-) | ||
12 | |||
13 | diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/include/hw/core/cpu.h | ||
16 | +++ b/include/hw/core/cpu.h | ||
17 | @@ -XXX,XX +XXX,XX @@ enum CPUDumpFlags { | ||
18 | void cpu_dump_state(CPUState *cpu, FILE *f, int flags); | ||
19 | |||
20 | #ifndef CONFIG_USER_ONLY | ||
21 | +/** | ||
22 | + * cpu_has_work: | ||
23 | + * @cpu: The vCPU to check. | ||
24 | + * | ||
25 | + * Checks whether the CPU has work to do. | ||
26 | + * | ||
27 | + * Returns: %true if the CPU has work, %false otherwise. | ||
28 | + */ | ||
29 | +static inline bool cpu_has_work(CPUState *cpu) | ||
30 | +{ | ||
31 | + CPUClass *cc = CPU_GET_CLASS(cpu); | ||
32 | + | ||
33 | + g_assert(cc->has_work); | ||
34 | + return cc->has_work(cpu); | ||
35 | +} | ||
36 | + | ||
37 | /** | ||
38 | * cpu_get_phys_page_attrs_debug: | ||
39 | * @cpu: The CPU to obtain the physical page address for. | ||
40 | @@ -XXX,XX +XXX,XX @@ CPUState *cpu_create(const char *typename); | ||
41 | */ | ||
42 | const char *parse_cpu_option(const char *cpu_option); | ||
43 | |||
44 | -/** | ||
45 | - * cpu_has_work: | ||
46 | - * @cpu: The vCPU to check. | ||
47 | - * | ||
48 | - * Checks whether the CPU has work to do. | ||
49 | - * | ||
50 | - * Returns: %true if the CPU has work, %false otherwise. | ||
51 | - */ | ||
52 | -static inline bool cpu_has_work(CPUState *cpu) | ||
53 | -{ | ||
54 | - CPUClass *cc = CPU_GET_CLASS(cpu); | ||
55 | - | ||
56 | - g_assert(cc->has_work); | ||
57 | - return cc->has_work(cpu); | ||
58 | -} | ||
59 | - | ||
60 | /** | ||
61 | * qemu_cpu_is_self: | ||
62 | * @cpu: The vCPU to check against. | ||
63 | -- | ||
64 | 2.25.1 | ||
65 | |||
66 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | We want to make cpu_has_work() per-accelerator. Only declare its | ||
4 | prototype and move its definition to softmmu/cpus.c. | ||
5 | |||
6 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-Id: <20210912172731.789788-4-f4bug@amsat.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | --- | ||
11 | include/hw/core/cpu.h | 8 +------- | ||
12 | softmmu/cpus.c | 8 ++++++++ | ||
13 | 2 files changed, 9 insertions(+), 7 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/core/cpu.h | ||
18 | +++ b/include/hw/core/cpu.h | ||
19 | @@ -XXX,XX +XXX,XX @@ void cpu_dump_state(CPUState *cpu, FILE *f, int flags); | ||
20 | * | ||
21 | * Returns: %true if the CPU has work, %false otherwise. | ||
22 | */ | ||
23 | -static inline bool cpu_has_work(CPUState *cpu) | ||
24 | -{ | ||
25 | - CPUClass *cc = CPU_GET_CLASS(cpu); | ||
26 | - | ||
27 | - g_assert(cc->has_work); | ||
28 | - return cc->has_work(cpu); | ||
29 | -} | ||
30 | +bool cpu_has_work(CPUState *cpu); | ||
31 | |||
32 | /** | ||
33 | * cpu_get_phys_page_attrs_debug: | ||
34 | diff --git a/softmmu/cpus.c b/softmmu/cpus.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/softmmu/cpus.c | ||
37 | +++ b/softmmu/cpus.c | ||
38 | @@ -XXX,XX +XXX,XX @@ void cpu_interrupt(CPUState *cpu, int mask) | ||
39 | } | ||
40 | } | ||
41 | |||
42 | +bool cpu_has_work(CPUState *cpu) | ||
43 | +{ | ||
44 | + CPUClass *cc = CPU_GET_CLASS(cpu); | ||
45 | + | ||
46 | + g_assert(cc->has_work); | ||
47 | + return cc->has_work(cpu); | ||
48 | +} | ||
49 | + | ||
50 | static int do_vm_stop(RunState state, bool send_stop) | ||
51 | { | ||
52 | int ret = 0; | ||
53 | -- | ||
54 | 2.25.1 | ||
55 | |||
56 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Introduce an accelerator-specific has_work() handler. | ||
4 | Eventually call it from cpu_has_work(). | ||
5 | |||
6 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-Id: <20210912172731.789788-5-f4bug@amsat.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | --- | ||
11 | include/sysemu/accel-ops.h | 5 +++++ | ||
12 | softmmu/cpus.c | 3 +++ | ||
13 | 2 files changed, 8 insertions(+) | ||
14 | |||
15 | diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/sysemu/accel-ops.h | ||
18 | +++ b/include/sysemu/accel-ops.h | ||
19 | @@ -XXX,XX +XXX,XX @@ struct AccelOpsClass { | ||
20 | void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */ | ||
21 | void (*kick_vcpu_thread)(CPUState *cpu); | ||
22 | |||
23 | + /** | ||
24 | + * @has_work: Callback for checking if there is work to do. | ||
25 | + */ | ||
26 | + bool (*has_work)(CPUState *cpu); | ||
27 | + | ||
28 | void (*synchronize_post_reset)(CPUState *cpu); | ||
29 | void (*synchronize_post_init)(CPUState *cpu); | ||
30 | void (*synchronize_state)(CPUState *cpu); | ||
31 | diff --git a/softmmu/cpus.c b/softmmu/cpus.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/softmmu/cpus.c | ||
34 | +++ b/softmmu/cpus.c | ||
35 | @@ -XXX,XX +XXX,XX @@ bool cpu_has_work(CPUState *cpu) | ||
36 | { | ||
37 | CPUClass *cc = CPU_GET_CLASS(cpu); | ||
38 | |||
39 | + if (cpus_accel->has_work) { | ||
40 | + return cpus_accel->has_work(cpu); | ||
41 | + } | ||
42 | g_assert(cc->has_work); | ||
43 | return cc->has_work(cpu); | ||
44 | } | ||
45 | -- | ||
46 | 2.25.1 | ||
47 | |||
48 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | DisasContextBase.pc_next has type vaddr; use the correct log format. |
---|---|---|---|
2 | 2 | ||
3 | Implement KVM has_work() handler in AccelOpsClass and | 3 | Fixes: 85c19af63e7 ("include/exec: Use vaddr in DisasContextBase for virtual addresses") |
4 | remove it from cpu_thread_is_idle() since cpu_has_work() | ||
5 | is already called. | ||
6 | |||
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-Id: <20210912172731.789788-6-f4bug@amsat.org> | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
11 | --- | 5 | --- |
12 | accel/kvm/kvm-accel-ops.c | 6 ++++++ | 6 | target/mips/tcg/octeon_translate.c | 4 ++-- |
13 | softmmu/cpus.c | 2 +- | 7 | 1 file changed, 2 insertions(+), 2 deletions(-) |
14 | 2 files changed, 7 insertions(+), 1 deletion(-) | ||
15 | 8 | ||
16 | diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c | 9 | diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c |
17 | index XXXXXXX..XXXXXXX 100644 | 10 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/accel/kvm/kvm-accel-ops.c | 11 | --- a/target/mips/tcg/octeon_translate.c |
19 | +++ b/accel/kvm/kvm-accel-ops.c | 12 | +++ b/target/mips/tcg/octeon_translate.c |
20 | @@ -XXX,XX +XXX,XX @@ static void kvm_start_vcpu_thread(CPUState *cpu) | 13 | @@ -XXX,XX +XXX,XX @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) |
21 | cpu, QEMU_THREAD_JOINABLE); | 14 | TCGv p; |
22 | } | 15 | |
23 | 16 | if (ctx->hflags & MIPS_HFLAG_BMASK) { | |
24 | +static bool kvm_cpu_has_work(CPUState *cpu) | 17 | - LOG_DISAS("Branch in delay / forbidden slot at PC 0x" |
25 | +{ | 18 | - TARGET_FMT_lx "\n", ctx->base.pc_next); |
26 | + return kvm_halt_in_kernel(); | 19 | + LOG_DISAS("Branch in delay / forbidden slot at PC 0x%" VADDR_PRIx "\n", |
27 | +} | 20 | + ctx->base.pc_next); |
28 | + | 21 | generate_exception_end(ctx, EXCP_RI); |
29 | static void kvm_accel_ops_class_init(ObjectClass *oc, void *data) | ||
30 | { | ||
31 | AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); | ||
32 | @@ -XXX,XX +XXX,XX @@ static void kvm_accel_ops_class_init(ObjectClass *oc, void *data) | ||
33 | ops->synchronize_post_init = kvm_cpu_synchronize_post_init; | ||
34 | ops->synchronize_state = kvm_cpu_synchronize_state; | ||
35 | ops->synchronize_pre_loadvm = kvm_cpu_synchronize_pre_loadvm; | ||
36 | + ops->has_work = kvm_cpu_has_work; | ||
37 | } | ||
38 | |||
39 | static const TypeInfo kvm_accel_ops_type = { | ||
40 | diff --git a/softmmu/cpus.c b/softmmu/cpus.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/softmmu/cpus.c | ||
43 | +++ b/softmmu/cpus.c | ||
44 | @@ -XXX,XX +XXX,XX @@ bool cpu_thread_is_idle(CPUState *cpu) | ||
45 | return true; | 22 | return true; |
46 | } | 23 | } |
47 | if (!cpu->halted || cpu_has_work(cpu) || | ||
48 | - kvm_halt_in_kernel() || whpx_apic_in_platform()) { | ||
49 | + whpx_apic_in_platform()) { | ||
50 | return false; | ||
51 | } | ||
52 | return true; | ||
53 | -- | 24 | -- |
54 | 2.25.1 | 25 | 2.43.0 |
55 | |||
56 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Implement WHPX has_work() handler in AccelOpsClass and | ||
4 | remove it from cpu_thread_is_idle() since cpu_has_work() | ||
5 | is already called. | ||
6 | |||
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-Id: <20210912172731.789788-7-f4bug@amsat.org> | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | --- | ||
12 | softmmu/cpus.c | 4 +--- | ||
13 | target/i386/whpx/whpx-accel-ops.c | 6 ++++++ | ||
14 | 2 files changed, 7 insertions(+), 3 deletions(-) | ||
15 | |||
16 | diff --git a/softmmu/cpus.c b/softmmu/cpus.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/softmmu/cpus.c | ||
19 | +++ b/softmmu/cpus.c | ||
20 | @@ -XXX,XX +XXX,XX @@ | ||
21 | #include "sysemu/replay.h" | ||
22 | #include "sysemu/runstate.h" | ||
23 | #include "sysemu/cpu-timers.h" | ||
24 | -#include "sysemu/whpx.h" | ||
25 | #include "hw/boards.h" | ||
26 | #include "hw/hw.h" | ||
27 | #include "trace.h" | ||
28 | @@ -XXX,XX +XXX,XX @@ bool cpu_thread_is_idle(CPUState *cpu) | ||
29 | if (cpu_is_stopped(cpu)) { | ||
30 | return true; | ||
31 | } | ||
32 | - if (!cpu->halted || cpu_has_work(cpu) || | ||
33 | - whpx_apic_in_platform()) { | ||
34 | + if (!cpu->halted || cpu_has_work(cpu)) { | ||
35 | return false; | ||
36 | } | ||
37 | return true; | ||
38 | diff --git a/target/i386/whpx/whpx-accel-ops.c b/target/i386/whpx/whpx-accel-ops.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/i386/whpx/whpx-accel-ops.c | ||
41 | +++ b/target/i386/whpx/whpx-accel-ops.c | ||
42 | @@ -XXX,XX +XXX,XX @@ static void whpx_kick_vcpu_thread(CPUState *cpu) | ||
43 | } | ||
44 | } | ||
45 | |||
46 | +static bool whpx_cpu_has_work(CPUState *cpu) | ||
47 | +{ | ||
48 | + return whpx_apic_in_platform(); | ||
49 | +} | ||
50 | + | ||
51 | static void whpx_accel_ops_class_init(ObjectClass *oc, void *data) | ||
52 | { | ||
53 | AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); | ||
54 | @@ -XXX,XX +XXX,XX @@ static void whpx_accel_ops_class_init(ObjectClass *oc, void *data) | ||
55 | ops->synchronize_post_init = whpx_cpu_synchronize_post_init; | ||
56 | ops->synchronize_state = whpx_cpu_synchronize_state; | ||
57 | ops->synchronize_pre_loadvm = whpx_cpu_synchronize_pre_loadvm; | ||
58 | + ops->has_work = whpx_cpu_has_work; | ||
59 | } | ||
60 | |||
61 | static const TypeInfo whpx_accel_ops_type = { | ||
62 | -- | ||
63 | 2.25.1 | ||
64 | |||
65 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Add TCG target-specific has_work() handler in TCGCPUOps, | ||
4 | and add tcg_cpu_has_work() as AccelOpsClass has_work() | ||
5 | implementation. | ||
6 | |||
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-Id: <20210912172731.789788-8-f4bug@amsat.org> | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | --- | ||
12 | include/hw/core/tcg-cpu-ops.h | 4 ++++ | ||
13 | accel/tcg/tcg-accel-ops.c | 12 ++++++++++++ | ||
14 | 2 files changed, 16 insertions(+) | ||
15 | |||
16 | diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/include/hw/core/tcg-cpu-ops.h | ||
19 | +++ b/include/hw/core/tcg-cpu-ops.h | ||
20 | @@ -XXX,XX +XXX,XX @@ struct TCGCPUOps { | ||
21 | void (*do_interrupt)(CPUState *cpu); | ||
22 | #endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ | ||
23 | #ifdef CONFIG_SOFTMMU | ||
24 | + /** | ||
25 | + * @has_work: Callback for checking if there is work to do. | ||
26 | + */ | ||
27 | + bool (*has_work)(CPUState *cpu); | ||
28 | /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ | ||
29 | bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); | ||
30 | /** | ||
31 | diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/accel/tcg/tcg-accel-ops.c | ||
34 | +++ b/accel/tcg/tcg-accel-ops.c | ||
35 | @@ -XXX,XX +XXX,XX @@ | ||
36 | #include "qemu/main-loop.h" | ||
37 | #include "qemu/guest-random.h" | ||
38 | #include "exec/exec-all.h" | ||
39 | +#include "hw/core/tcg-cpu-ops.h" | ||
40 | |||
41 | #include "tcg-accel-ops.h" | ||
42 | #include "tcg-accel-ops-mttcg.h" | ||
43 | @@ -XXX,XX +XXX,XX @@ int tcg_cpus_exec(CPUState *cpu) | ||
44 | return ret; | ||
45 | } | ||
46 | |||
47 | +static bool tcg_cpu_has_work(CPUState *cpu) | ||
48 | +{ | ||
49 | + CPUClass *cc = CPU_GET_CLASS(cpu); | ||
50 | + | ||
51 | + if (!cc->tcg_ops->has_work) { | ||
52 | + return false; | ||
53 | + } | ||
54 | + return cc->tcg_ops->has_work(cpu); | ||
55 | +} | ||
56 | + | ||
57 | /* mask must never be zero, except for A20 change call */ | ||
58 | void tcg_handle_interrupt(CPUState *cpu, int mask) | ||
59 | { | ||
60 | @@ -XXX,XX +XXX,XX @@ static void tcg_accel_ops_init(AccelOpsClass *ops) | ||
61 | ops->kick_vcpu_thread = rr_kick_vcpu_thread; | ||
62 | ops->handle_interrupt = tcg_handle_interrupt; | ||
63 | } | ||
64 | + ops->has_work = tcg_cpu_has_work; | ||
65 | } | ||
66 | |||
67 | static void tcg_accel_ops_class_init(ObjectClass *oc, void *data) | ||
68 | -- | ||
69 | 2.25.1 | ||
70 | |||
71 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-9-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/alpha/cpu.c | 4 +++- | ||
11 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/alpha/cpu.c | ||
16 | +++ b/target/alpha/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value) | ||
18 | cpu->env.pc = value; | ||
19 | } | ||
20 | |||
21 | +#if !defined(CONFIG_USER_ONLY) | ||
22 | static bool alpha_cpu_has_work(CPUState *cs) | ||
23 | { | ||
24 | /* Here we are checking to see if the CPU should wake up from HALT. | ||
25 | @@ -XXX,XX +XXX,XX @@ static bool alpha_cpu_has_work(CPUState *cs) | ||
26 | | CPU_INTERRUPT_SMP | ||
27 | | CPU_INTERRUPT_MCHK); | ||
28 | } | ||
29 | +#endif /* !CONFIG_USER_ONLY */ | ||
30 | |||
31 | static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) | ||
32 | { | ||
33 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps alpha_tcg_ops = { | ||
34 | .tlb_fill = alpha_cpu_tlb_fill, | ||
35 | |||
36 | #ifndef CONFIG_USER_ONLY | ||
37 | + .has_work = alpha_cpu_has_work, | ||
38 | .cpu_exec_interrupt = alpha_cpu_exec_interrupt, | ||
39 | .do_interrupt = alpha_cpu_do_interrupt, | ||
40 | .do_transaction_failed = alpha_cpu_do_transaction_failed, | ||
41 | @@ -XXX,XX +XXX,XX @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) | ||
42 | &acc->parent_realize); | ||
43 | |||
44 | cc->class_by_name = alpha_cpu_class_by_name; | ||
45 | - cc->has_work = alpha_cpu_has_work; | ||
46 | cc->dump_state = alpha_cpu_dump_state; | ||
47 | cc->set_pc = alpha_cpu_set_pc; | ||
48 | cc->gdb_read_register = alpha_cpu_gdb_read_register; | ||
49 | -- | ||
50 | 2.25.1 | ||
51 | |||
52 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to TCG sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-10-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/arm/cpu.c | 7 +++++-- | ||
11 | 1 file changed, 5 insertions(+), 2 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/cpu.c | ||
16 | +++ b/target/arm/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_synchronize_from_tb(CPUState *cs, | ||
18 | env->regs[15] = tb->pc; | ||
19 | } | ||
20 | } | ||
21 | -#endif /* CONFIG_TCG */ | ||
22 | |||
23 | +#ifndef CONFIG_USER_ONLY | ||
24 | static bool arm_cpu_has_work(CPUState *cs) | ||
25 | { | ||
26 | ARMCPU *cpu = ARM_CPU(cs); | ||
27 | @@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs) | ||
28 | | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | ||
29 | | CPU_INTERRUPT_EXITTB); | ||
30 | } | ||
31 | +#endif /* !CONFIG_USER_ONLY */ | ||
32 | + | ||
33 | +#endif /* CONFIG_TCG */ | ||
34 | |||
35 | void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, | ||
36 | void *opaque) | ||
37 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps arm_tcg_ops = { | ||
38 | .debug_excp_handler = arm_debug_excp_handler, | ||
39 | |||
40 | #if !defined(CONFIG_USER_ONLY) | ||
41 | + .has_work = arm_cpu_has_work, | ||
42 | .cpu_exec_interrupt = arm_cpu_exec_interrupt, | ||
43 | .do_interrupt = arm_cpu_do_interrupt, | ||
44 | .do_transaction_failed = arm_cpu_do_transaction_failed, | ||
45 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) | ||
46 | device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); | ||
47 | |||
48 | cc->class_by_name = arm_cpu_class_by_name; | ||
49 | - cc->has_work = arm_cpu_has_work; | ||
50 | cc->dump_state = arm_cpu_dump_state; | ||
51 | cc->set_pc = arm_cpu_set_pc; | ||
52 | cc->gdb_read_register = arm_cpu_gdb_read_register; | ||
53 | -- | ||
54 | 2.25.1 | ||
55 | |||
56 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-11-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/avr/cpu.c | 2 +- | ||
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/avr/cpu.c b/target/avr/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/avr/cpu.c | ||
16 | +++ b/target/avr/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps avr_sysemu_ops = { | ||
18 | static const struct TCGCPUOps avr_tcg_ops = { | ||
19 | .initialize = avr_cpu_tcg_init, | ||
20 | .synchronize_from_tb = avr_cpu_synchronize_from_tb, | ||
21 | + .has_work = avr_cpu_has_work, | ||
22 | .cpu_exec_interrupt = avr_cpu_exec_interrupt, | ||
23 | .tlb_fill = avr_cpu_tlb_fill, | ||
24 | .do_interrupt = avr_cpu_do_interrupt, | ||
25 | @@ -XXX,XX +XXX,XX @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) | ||
26 | |||
27 | cc->class_by_name = avr_cpu_class_by_name; | ||
28 | |||
29 | - cc->has_work = avr_cpu_has_work; | ||
30 | cc->dump_state = avr_cpu_dump_state; | ||
31 | cc->set_pc = avr_cpu_set_pc; | ||
32 | cc->memory_rw_debug = avr_cpu_memory_rw_debug; | ||
33 | -- | ||
34 | 2.25.1 | ||
35 | |||
36 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-12-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/cris/cpu.c | 4 +++- | ||
11 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/cris/cpu.c b/target/cris/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/cris/cpu.c | ||
16 | +++ b/target/cris/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value) | ||
18 | cpu->env.pc = value; | ||
19 | } | ||
20 | |||
21 | +#if !defined(CONFIG_USER_ONLY) | ||
22 | static bool cris_cpu_has_work(CPUState *cs) | ||
23 | { | ||
24 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); | ||
25 | } | ||
26 | +#endif /* !CONFIG_USER_ONLY */ | ||
27 | |||
28 | static void cris_cpu_reset(DeviceState *dev) | ||
29 | { | ||
30 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps crisv10_tcg_ops = { | ||
31 | .tlb_fill = cris_cpu_tlb_fill, | ||
32 | |||
33 | #ifndef CONFIG_USER_ONLY | ||
34 | + .has_work = cris_cpu_has_work, | ||
35 | .cpu_exec_interrupt = cris_cpu_exec_interrupt, | ||
36 | .do_interrupt = crisv10_cpu_do_interrupt, | ||
37 | #endif /* !CONFIG_USER_ONLY */ | ||
38 | @@ -XXX,XX +XXX,XX @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) | ||
39 | device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); | ||
40 | |||
41 | cc->class_by_name = cris_cpu_class_by_name; | ||
42 | - cc->has_work = cris_cpu_has_work; | ||
43 | cc->dump_state = cris_cpu_dump_state; | ||
44 | cc->set_pc = cris_cpu_set_pc; | ||
45 | cc->gdb_read_register = cris_cpu_gdb_read_register; | ||
46 | -- | ||
47 | 2.25.1 | ||
48 | |||
49 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | has_work() is sysemu specific, and Hexagon target only provides | ||
4 | a linux-user implementation. Remove the unused hexagon_cpu_has_work(). | ||
5 | |||
6 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-Id: <20210912172731.789788-13-f4bug@amsat.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | --- | ||
11 | target/hexagon/cpu.c | 6 ------ | ||
12 | 1 file changed, 6 deletions(-) | ||
13 | |||
14 | diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/hexagon/cpu.c | ||
17 | +++ b/target/hexagon/cpu.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs, | ||
19 | env->gpr[HEX_REG_PC] = tb->pc; | ||
20 | } | ||
21 | |||
22 | -static bool hexagon_cpu_has_work(CPUState *cs) | ||
23 | -{ | ||
24 | - return true; | ||
25 | -} | ||
26 | - | ||
27 | void restore_state_to_opc(CPUHexagonState *env, TranslationBlock *tb, | ||
28 | target_ulong *data) | ||
29 | { | ||
30 | @@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data) | ||
31 | device_class_set_parent_reset(dc, hexagon_cpu_reset, &mcc->parent_reset); | ||
32 | |||
33 | cc->class_by_name = hexagon_cpu_class_by_name; | ||
34 | - cc->has_work = hexagon_cpu_has_work; | ||
35 | cc->dump_state = hexagon_dump_state; | ||
36 | cc->set_pc = hexagon_cpu_set_pc; | ||
37 | cc->gdb_read_register = hexagon_gdb_read_register; | ||
38 | -- | ||
39 | 2.25.1 | ||
40 | |||
41 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-14-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/hppa/cpu.c | 4 +++- | ||
11 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/hppa/cpu.c | ||
16 | +++ b/target/hppa/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, | ||
18 | cpu->env.psw_n = (tb->flags & PSW_N) != 0; | ||
19 | } | ||
20 | |||
21 | +#if !defined(CONFIG_USER_ONLY) | ||
22 | static bool hppa_cpu_has_work(CPUState *cs) | ||
23 | { | ||
24 | return cs->interrupt_request & CPU_INTERRUPT_HARD; | ||
25 | } | ||
26 | +#endif /* !CONFIG_USER_ONLY */ | ||
27 | |||
28 | static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) | ||
29 | { | ||
30 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps hppa_tcg_ops = { | ||
31 | .tlb_fill = hppa_cpu_tlb_fill, | ||
32 | |||
33 | #ifndef CONFIG_USER_ONLY | ||
34 | + .has_work = hppa_cpu_has_work, | ||
35 | .cpu_exec_interrupt = hppa_cpu_exec_interrupt, | ||
36 | .do_interrupt = hppa_cpu_do_interrupt, | ||
37 | .do_unaligned_access = hppa_cpu_do_unaligned_access, | ||
38 | @@ -XXX,XX +XXX,XX @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) | ||
39 | &acc->parent_realize); | ||
40 | |||
41 | cc->class_by_name = hppa_cpu_class_by_name; | ||
42 | - cc->has_work = hppa_cpu_has_work; | ||
43 | cc->dump_state = hppa_cpu_dump_state; | ||
44 | cc->set_pc = hppa_cpu_set_pc; | ||
45 | cc->gdb_read_register = hppa_cpu_gdb_read_register; | ||
46 | -- | ||
47 | 2.25.1 | ||
48 | |||
49 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to TCG sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-15-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/i386/cpu.c | 6 ------ | ||
11 | target/i386/tcg/tcg-cpu.c | 8 +++++++- | ||
12 | 2 files changed, 7 insertions(+), 7 deletions(-) | ||
13 | |||
14 | diff --git a/target/i386/cpu.c b/target/i386/cpu.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/i386/cpu.c | ||
17 | +++ b/target/i386/cpu.c | ||
18 | @@ -XXX,XX +XXX,XX @@ int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) | ||
19 | return 0; | ||
20 | } | ||
21 | |||
22 | -static bool x86_cpu_has_work(CPUState *cs) | ||
23 | -{ | ||
24 | - return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; | ||
25 | -} | ||
26 | - | ||
27 | static void x86_disas_set_info(CPUState *cs, disassemble_info *info) | ||
28 | { | ||
29 | X86CPU *cpu = X86_CPU(cs); | ||
30 | @@ -XXX,XX +XXX,XX @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) | ||
31 | |||
32 | cc->class_by_name = x86_cpu_class_by_name; | ||
33 | cc->parse_features = x86_cpu_parse_featurestr; | ||
34 | - cc->has_work = x86_cpu_has_work; | ||
35 | cc->dump_state = x86_cpu_dump_state; | ||
36 | cc->set_pc = x86_cpu_set_pc; | ||
37 | cc->gdb_read_register = x86_cpu_gdb_read_register; | ||
38 | diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/i386/tcg/tcg-cpu.c | ||
41 | +++ b/target/i386/tcg/tcg-cpu.c | ||
42 | @@ -XXX,XX +XXX,XX @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, | ||
43 | } | ||
44 | |||
45 | #ifndef CONFIG_USER_ONLY | ||
46 | +static bool x86_cpu_has_work(CPUState *cs) | ||
47 | +{ | ||
48 | + return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; | ||
49 | +} | ||
50 | + | ||
51 | static bool x86_debug_check_breakpoint(CPUState *cs) | ||
52 | { | ||
53 | X86CPU *cpu = X86_CPU(cs); | ||
54 | @@ -XXX,XX +XXX,XX @@ static bool x86_debug_check_breakpoint(CPUState *cs) | ||
55 | /* RF disables all architectural breakpoints. */ | ||
56 | return !(env->eflags & RF_MASK); | ||
57 | } | ||
58 | -#endif | ||
59 | +#endif /* CONFIG_USER_ONLY */ | ||
60 | |||
61 | #include "hw/core/tcg-cpu-ops.h" | ||
62 | |||
63 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps x86_tcg_ops = { | ||
64 | #ifdef CONFIG_USER_ONLY | ||
65 | .fake_user_interrupt = x86_cpu_do_interrupt, | ||
66 | #else | ||
67 | + .has_work = x86_cpu_has_work, | ||
68 | .do_interrupt = x86_cpu_do_interrupt, | ||
69 | .cpu_exec_interrupt = x86_cpu_exec_interrupt, | ||
70 | .debug_excp_handler = breakpoint_handler, | ||
71 | -- | ||
72 | 2.25.1 | ||
73 | |||
74 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-16-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/m68k/cpu.c | 4 +++- | ||
11 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/m68k/cpu.c | ||
16 | +++ b/target/m68k/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value) | ||
18 | cpu->env.pc = value; | ||
19 | } | ||
20 | |||
21 | +#if !defined(CONFIG_USER_ONLY) | ||
22 | static bool m68k_cpu_has_work(CPUState *cs) | ||
23 | { | ||
24 | return cs->interrupt_request & CPU_INTERRUPT_HARD; | ||
25 | } | ||
26 | +#endif /* !CONFIG_USER_ONLY */ | ||
27 | |||
28 | static void m68k_set_feature(CPUM68KState *env, int feature) | ||
29 | { | ||
30 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps m68k_tcg_ops = { | ||
31 | .tlb_fill = m68k_cpu_tlb_fill, | ||
32 | |||
33 | #ifndef CONFIG_USER_ONLY | ||
34 | + .has_work = m68k_cpu_has_work, | ||
35 | .cpu_exec_interrupt = m68k_cpu_exec_interrupt, | ||
36 | .do_interrupt = m68k_cpu_do_interrupt, | ||
37 | .do_transaction_failed = m68k_cpu_transaction_failed, | ||
38 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) | ||
39 | device_class_set_parent_reset(dc, m68k_cpu_reset, &mcc->parent_reset); | ||
40 | |||
41 | cc->class_by_name = m68k_cpu_class_by_name; | ||
42 | - cc->has_work = m68k_cpu_has_work; | ||
43 | cc->dump_state = m68k_cpu_dump_state; | ||
44 | cc->set_pc = m68k_cpu_set_pc; | ||
45 | cc->gdb_read_register = m68k_cpu_gdb_read_register; | ||
46 | -- | ||
47 | 2.25.1 | ||
48 | |||
49 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-17-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/microblaze/cpu.c | 8 ++++---- | ||
11 | 1 file changed, 4 insertions(+), 4 deletions(-) | ||
12 | |||
13 | diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/microblaze/cpu.c | ||
16 | +++ b/target/microblaze/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void mb_cpu_synchronize_from_tb(CPUState *cs, | ||
18 | cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; | ||
19 | } | ||
20 | |||
21 | +#ifndef CONFIG_USER_ONLY | ||
22 | + | ||
23 | static bool mb_cpu_has_work(CPUState *cs) | ||
24 | { | ||
25 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); | ||
26 | } | ||
27 | |||
28 | -#ifndef CONFIG_USER_ONLY | ||
29 | static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) | ||
30 | { | ||
31 | MicroBlazeCPU *cpu = opaque; | ||
32 | @@ -XXX,XX +XXX,XX @@ static void microblaze_cpu_set_irq(void *opaque, int irq, int level) | ||
33 | cpu_reset_interrupt(cs, type); | ||
34 | } | ||
35 | } | ||
36 | -#endif | ||
37 | +#endif /* !CONFIG_USER_ONLY */ | ||
38 | |||
39 | static void mb_cpu_reset(DeviceState *dev) | ||
40 | { | ||
41 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps mb_tcg_ops = { | ||
42 | .tlb_fill = mb_cpu_tlb_fill, | ||
43 | |||
44 | #ifndef CONFIG_USER_ONLY | ||
45 | + .has_work = mb_cpu_has_work, | ||
46 | .cpu_exec_interrupt = mb_cpu_exec_interrupt, | ||
47 | .do_interrupt = mb_cpu_do_interrupt, | ||
48 | .do_transaction_failed = mb_cpu_transaction_failed, | ||
49 | @@ -XXX,XX +XXX,XX @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) | ||
50 | device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset); | ||
51 | |||
52 | cc->class_by_name = mb_cpu_class_by_name; | ||
53 | - cc->has_work = mb_cpu_has_work; | ||
54 | - | ||
55 | cc->dump_state = mb_cpu_dump_state; | ||
56 | cc->set_pc = mb_cpu_set_pc; | ||
57 | cc->gdb_read_register = mb_cpu_gdb_read_register; | ||
58 | -- | ||
59 | 2.25.1 | ||
60 | |||
61 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to TCG sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-18-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/mips/cpu.c | 4 +++- | ||
11 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/mips/cpu.c b/target/mips/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/mips/cpu.c | ||
16 | +++ b/target/mips/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) | ||
18 | mips_env_set_pc(&cpu->env, value); | ||
19 | } | ||
20 | |||
21 | +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) | ||
22 | static bool mips_cpu_has_work(CPUState *cs) | ||
23 | { | ||
24 | MIPSCPU *cpu = MIPS_CPU(cs); | ||
25 | @@ -XXX,XX +XXX,XX @@ static bool mips_cpu_has_work(CPUState *cs) | ||
26 | } | ||
27 | return has_work; | ||
28 | } | ||
29 | +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ | ||
30 | |||
31 | #include "cpu-defs.c.inc" | ||
32 | |||
33 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps mips_tcg_ops = { | ||
34 | .tlb_fill = mips_cpu_tlb_fill, | ||
35 | |||
36 | #if !defined(CONFIG_USER_ONLY) | ||
37 | + .has_work = mips_cpu_has_work, | ||
38 | .cpu_exec_interrupt = mips_cpu_exec_interrupt, | ||
39 | .do_interrupt = mips_cpu_do_interrupt, | ||
40 | .do_transaction_failed = mips_cpu_do_transaction_failed, | ||
41 | @@ -XXX,XX +XXX,XX @@ static void mips_cpu_class_init(ObjectClass *c, void *data) | ||
42 | device_class_set_props(dc, mips_cpu_properties); | ||
43 | |||
44 | cc->class_by_name = mips_cpu_class_by_name; | ||
45 | - cc->has_work = mips_cpu_has_work; | ||
46 | cc->dump_state = mips_cpu_dump_state; | ||
47 | cc->set_pc = mips_cpu_set_pc; | ||
48 | cc->gdb_read_register = mips_cpu_gdb_read_register; | ||
49 | -- | ||
50 | 2.25.1 | ||
51 | |||
52 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-19-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/nios2/cpu.c | 4 +++- | ||
11 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/nios2/cpu.c | ||
16 | +++ b/target/nios2/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) | ||
18 | env->regs[R_PC] = value; | ||
19 | } | ||
20 | |||
21 | +#if !defined(CONFIG_USER_ONLY) | ||
22 | static bool nios2_cpu_has_work(CPUState *cs) | ||
23 | { | ||
24 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); | ||
25 | } | ||
26 | +#endif /* !CONFIG_USER_ONLY */ | ||
27 | |||
28 | static void nios2_cpu_reset(DeviceState *dev) | ||
29 | { | ||
30 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps nios2_tcg_ops = { | ||
31 | .tlb_fill = nios2_cpu_tlb_fill, | ||
32 | |||
33 | #ifndef CONFIG_USER_ONLY | ||
34 | + .has_work = nios2_cpu_has_work, | ||
35 | .cpu_exec_interrupt = nios2_cpu_exec_interrupt, | ||
36 | .do_interrupt = nios2_cpu_do_interrupt, | ||
37 | .do_unaligned_access = nios2_cpu_do_unaligned_access, | ||
38 | @@ -XXX,XX +XXX,XX @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) | ||
39 | device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset); | ||
40 | |||
41 | cc->class_by_name = nios2_cpu_class_by_name; | ||
42 | - cc->has_work = nios2_cpu_has_work; | ||
43 | cc->dump_state = nios2_cpu_dump_state; | ||
44 | cc->set_pc = nios2_cpu_set_pc; | ||
45 | cc->disas_set_info = nios2_cpu_disas_set_info; | ||
46 | -- | ||
47 | 2.25.1 | ||
48 | |||
49 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-20-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/openrisc/cpu.c | 4 +++- | ||
11 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/openrisc/cpu.c | ||
16 | +++ b/target/openrisc/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) | ||
18 | cpu->env.dflag = 0; | ||
19 | } | ||
20 | |||
21 | +#if !defined(CONFIG_USER_ONLY) | ||
22 | static bool openrisc_cpu_has_work(CPUState *cs) | ||
23 | { | ||
24 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | | ||
25 | CPU_INTERRUPT_TIMER); | ||
26 | } | ||
27 | +#endif /* !CONFIG_USER_ONLY */ | ||
28 | |||
29 | static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) | ||
30 | { | ||
31 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps openrisc_tcg_ops = { | ||
32 | .tlb_fill = openrisc_cpu_tlb_fill, | ||
33 | |||
34 | #ifndef CONFIG_USER_ONLY | ||
35 | + .has_work = openrisc_cpu_has_work, | ||
36 | .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, | ||
37 | .do_interrupt = openrisc_cpu_do_interrupt, | ||
38 | #endif /* !CONFIG_USER_ONLY */ | ||
39 | @@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) | ||
40 | device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset); | ||
41 | |||
42 | cc->class_by_name = openrisc_cpu_class_by_name; | ||
43 | - cc->has_work = openrisc_cpu_has_work; | ||
44 | cc->dump_state = openrisc_cpu_dump_state; | ||
45 | cc->set_pc = openrisc_cpu_set_pc; | ||
46 | cc->gdb_read_register = openrisc_cpu_gdb_read_register; | ||
47 | -- | ||
48 | 2.25.1 | ||
49 | |||
50 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | We're moving the hook from CPUState to TCGCPUOps. TCGCPUOps is | ||
4 | a const structure, so to avoid creating multiple versions of | ||
5 | the same structure, simply changing the has_work() handler, | ||
6 | introduce yet another indirection with a has_work() handler in | ||
7 | PowerPCCPUClass, and ppc_cpu_has_work() method which dispatch | ||
8 | to it. | ||
9 | |||
10 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-Id: <20210912172731.789788-21-f4bug@amsat.org> | ||
13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | --- | ||
15 | target/ppc/cpu-qom.h | 1 + | ||
16 | target/ppc/cpu_init.c | 23 ++++++++++++++--------- | ||
17 | 2 files changed, 15 insertions(+), 9 deletions(-) | ||
18 | |||
19 | diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/ppc/cpu-qom.h | ||
22 | +++ b/target/ppc/cpu-qom.h | ||
23 | @@ -XXX,XX +XXX,XX @@ struct PowerPCCPUClass { | ||
24 | uint32_t flags; | ||
25 | int bfd_mach; | ||
26 | uint32_t l1_dcache_size, l1_icache_size; | ||
27 | + bool (*has_work)(CPUState *cpu); | ||
28 | #ifndef CONFIG_USER_ONLY | ||
29 | unsigned int gdb_num_sprs; | ||
30 | const char *gdb_spr_xml; | ||
31 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/ppc/cpu_init.c | ||
34 | +++ b/target/ppc/cpu_init.c | ||
35 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) | ||
36 | { | ||
37 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
38 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | ||
39 | - CPUClass *cc = CPU_CLASS(oc); | ||
40 | |||
41 | dc->fw_name = "PowerPC,POWER7"; | ||
42 | dc->desc = "POWER7"; | ||
43 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) | ||
44 | pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; | ||
45 | pcc->init_proc = init_proc_POWER7; | ||
46 | pcc->check_pow = check_pow_nocheck; | ||
47 | - cc->has_work = cpu_has_work_POWER7; | ||
48 | + pcc->has_work = cpu_has_work_POWER7; | ||
49 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | | ||
50 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | ||
51 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | ||
52 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) | ||
53 | { | ||
54 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
55 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | ||
56 | - CPUClass *cc = CPU_CLASS(oc); | ||
57 | |||
58 | dc->fw_name = "PowerPC,POWER8"; | ||
59 | dc->desc = "POWER8"; | ||
60 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) | ||
61 | pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; | ||
62 | pcc->init_proc = init_proc_POWER8; | ||
63 | pcc->check_pow = check_pow_nocheck; | ||
64 | - cc->has_work = cpu_has_work_POWER8; | ||
65 | + pcc->has_work = cpu_has_work_POWER8; | ||
66 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | | ||
67 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | ||
68 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | ||
69 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) | ||
70 | { | ||
71 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
72 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | ||
73 | - CPUClass *cc = CPU_CLASS(oc); | ||
74 | |||
75 | dc->fw_name = "PowerPC,POWER9"; | ||
76 | dc->desc = "POWER9"; | ||
77 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) | ||
78 | PCR_COMPAT_2_05; | ||
79 | pcc->init_proc = init_proc_POWER9; | ||
80 | pcc->check_pow = check_pow_nocheck; | ||
81 | - cc->has_work = cpu_has_work_POWER9; | ||
82 | + pcc->has_work = cpu_has_work_POWER9; | ||
83 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | | ||
84 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | ||
85 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | ||
86 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) | ||
87 | { | ||
88 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
89 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); | ||
90 | - CPUClass *cc = CPU_CLASS(oc); | ||
91 | |||
92 | dc->fw_name = "PowerPC,POWER10"; | ||
93 | dc->desc = "POWER10"; | ||
94 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) | ||
95 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; | ||
96 | pcc->init_proc = init_proc_POWER10; | ||
97 | pcc->check_pow = check_pow_nocheck; | ||
98 | - cc->has_work = cpu_has_work_POWER10; | ||
99 | + pcc->has_work = cpu_has_work_POWER10; | ||
100 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | | ||
101 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | ||
102 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | ||
103 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value) | ||
104 | cpu->env.nip = value; | ||
105 | } | ||
106 | |||
107 | -static bool ppc_cpu_has_work(CPUState *cs) | ||
108 | +static bool cpu_has_work_default(CPUState *cs) | ||
109 | { | ||
110 | PowerPCCPU *cpu = POWERPC_CPU(cs); | ||
111 | CPUPPCState *env = &cpu->env; | ||
112 | @@ -XXX,XX +XXX,XX @@ static bool ppc_cpu_has_work(CPUState *cs) | ||
113 | return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); | ||
114 | } | ||
115 | |||
116 | +static bool ppc_cpu_has_work(CPUState *cs) | ||
117 | +{ | ||
118 | + PowerPCCPU *cpu = POWERPC_CPU(cs); | ||
119 | + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | ||
120 | + | ||
121 | + return pcc->has_work(cs); | ||
122 | +} | ||
123 | + | ||
124 | static void ppc_cpu_reset(DeviceState *dev) | ||
125 | { | ||
126 | CPUState *s = CPU(dev); | ||
127 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) | ||
128 | device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, | ||
129 | &pcc->parent_unrealize); | ||
130 | pcc->pvr_match = ppc_pvr_match_default; | ||
131 | + pcc->has_work = cpu_has_work_default; | ||
132 | device_class_set_props(dc, ppc_cpu_properties); | ||
133 | |||
134 | device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); | ||
135 | -- | ||
136 | 2.25.1 | ||
137 | |||
138 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict PowerPCCPUClass::has_work() and ppc_cpu_has_work() | ||
4 | - SysemuCPUOps::has_work() implementation - to TCG sysemu. | ||
5 | |||
6 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-Id: <20210912172731.789788-22-f4bug@amsat.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | --- | ||
11 | target/ppc/cpu-qom.h | 4 +++- | ||
12 | target/ppc/cpu_init.c | 24 ++++++++++++++++++------ | ||
13 | 2 files changed, 21 insertions(+), 7 deletions(-) | ||
14 | |||
15 | diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/ppc/cpu-qom.h | ||
18 | +++ b/target/ppc/cpu-qom.h | ||
19 | @@ -XXX,XX +XXX,XX @@ struct PowerPCCPUClass { | ||
20 | uint32_t flags; | ||
21 | int bfd_mach; | ||
22 | uint32_t l1_dcache_size, l1_icache_size; | ||
23 | - bool (*has_work)(CPUState *cpu); | ||
24 | #ifndef CONFIG_USER_ONLY | ||
25 | +#ifdef CONFIG_TCG | ||
26 | + bool (*has_work)(CPUState *cpu); | ||
27 | +#endif /* CONFIG_TCG */ | ||
28 | unsigned int gdb_num_sprs; | ||
29 | const char *gdb_spr_xml; | ||
30 | #endif | ||
31 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/ppc/cpu_init.c | ||
34 | +++ b/target/ppc/cpu_init.c | ||
35 | @@ -XXX,XX +XXX,XX @@ static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) | ||
36 | return false; | ||
37 | } | ||
38 | |||
39 | +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) | ||
40 | static bool cpu_has_work_POWER7(CPUState *cs) | ||
41 | { | ||
42 | PowerPCCPU *cpu = POWERPC_CPU(cs); | ||
43 | @@ -XXX,XX +XXX,XX @@ static bool cpu_has_work_POWER7(CPUState *cs) | ||
44 | return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); | ||
45 | } | ||
46 | } | ||
47 | +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ | ||
48 | |||
49 | POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) | ||
50 | { | ||
51 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) | ||
52 | pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; | ||
53 | pcc->init_proc = init_proc_POWER7; | ||
54 | pcc->check_pow = check_pow_nocheck; | ||
55 | - pcc->has_work = cpu_has_work_POWER7; | ||
56 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | | ||
57 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | ||
58 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | ||
59 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) | ||
60 | pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; | ||
61 | pcc->mmu_model = POWERPC_MMU_2_06; | ||
62 | #if defined(CONFIG_SOFTMMU) | ||
63 | + pcc->has_work = cpu_has_work_POWER7; | ||
64 | pcc->hash64_opts = &ppc_hash64_opts_POWER7; | ||
65 | pcc->lrg_decr_bits = 32; | ||
66 | #endif | ||
67 | @@ -XXX,XX +XXX,XX @@ static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) | ||
68 | return false; | ||
69 | } | ||
70 | |||
71 | +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) | ||
72 | static bool cpu_has_work_POWER8(CPUState *cs) | ||
73 | { | ||
74 | PowerPCCPU *cpu = POWERPC_CPU(cs); | ||
75 | @@ -XXX,XX +XXX,XX @@ static bool cpu_has_work_POWER8(CPUState *cs) | ||
76 | return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); | ||
77 | } | ||
78 | } | ||
79 | +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ | ||
80 | |||
81 | POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) | ||
82 | { | ||
83 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) | ||
84 | pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; | ||
85 | pcc->init_proc = init_proc_POWER8; | ||
86 | pcc->check_pow = check_pow_nocheck; | ||
87 | - pcc->has_work = cpu_has_work_POWER8; | ||
88 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | | ||
89 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | ||
90 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | ||
91 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) | ||
92 | LPCR_P8_PECE3 | LPCR_P8_PECE4; | ||
93 | pcc->mmu_model = POWERPC_MMU_2_07; | ||
94 | #if defined(CONFIG_SOFTMMU) | ||
95 | + pcc->has_work = cpu_has_work_POWER8; | ||
96 | pcc->hash64_opts = &ppc_hash64_opts_POWER7; | ||
97 | pcc->lrg_decr_bits = 32; | ||
98 | pcc->n_host_threads = 8; | ||
99 | @@ -XXX,XX +XXX,XX @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) | ||
100 | return false; | ||
101 | } | ||
102 | |||
103 | +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) | ||
104 | static bool cpu_has_work_POWER9(CPUState *cs) | ||
105 | { | ||
106 | PowerPCCPU *cpu = POWERPC_CPU(cs); | ||
107 | @@ -XXX,XX +XXX,XX @@ static bool cpu_has_work_POWER9(CPUState *cs) | ||
108 | return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); | ||
109 | } | ||
110 | } | ||
111 | +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ | ||
112 | |||
113 | POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) | ||
114 | { | ||
115 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) | ||
116 | PCR_COMPAT_2_05; | ||
117 | pcc->init_proc = init_proc_POWER9; | ||
118 | pcc->check_pow = check_pow_nocheck; | ||
119 | - pcc->has_work = cpu_has_work_POWER9; | ||
120 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | | ||
121 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | ||
122 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | ||
123 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) | ||
124 | pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; | ||
125 | pcc->mmu_model = POWERPC_MMU_3_00; | ||
126 | #if defined(CONFIG_SOFTMMU) | ||
127 | + pcc->has_work = cpu_has_work_POWER9; | ||
128 | /* segment page size remain the same */ | ||
129 | pcc->hash64_opts = &ppc_hash64_opts_POWER7; | ||
130 | pcc->radix_page_info = &POWER9_radix_page_info; | ||
131 | @@ -XXX,XX +XXX,XX @@ static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) | ||
132 | return false; | ||
133 | } | ||
134 | |||
135 | +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) | ||
136 | static bool cpu_has_work_POWER10(CPUState *cs) | ||
137 | { | ||
138 | PowerPCCPU *cpu = POWERPC_CPU(cs); | ||
139 | @@ -XXX,XX +XXX,XX @@ static bool cpu_has_work_POWER10(CPUState *cs) | ||
140 | return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); | ||
141 | } | ||
142 | } | ||
143 | +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ | ||
144 | |||
145 | POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) | ||
146 | { | ||
147 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) | ||
148 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; | ||
149 | pcc->init_proc = init_proc_POWER10; | ||
150 | pcc->check_pow = check_pow_nocheck; | ||
151 | - pcc->has_work = cpu_has_work_POWER10; | ||
152 | pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | | ||
153 | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | | ||
154 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | | ||
155 | @@ -XXX,XX +XXX,XX @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) | ||
156 | pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; | ||
157 | pcc->mmu_model = POWERPC_MMU_3_00; | ||
158 | #if defined(CONFIG_SOFTMMU) | ||
159 | + pcc->has_work = cpu_has_work_POWER10; | ||
160 | /* segment page size remain the same */ | ||
161 | pcc->hash64_opts = &ppc_hash64_opts_POWER7; | ||
162 | pcc->radix_page_info = &POWER10_radix_page_info; | ||
163 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value) | ||
164 | cpu->env.nip = value; | ||
165 | } | ||
166 | |||
167 | +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) | ||
168 | static bool cpu_has_work_default(CPUState *cs) | ||
169 | { | ||
170 | PowerPCCPU *cpu = POWERPC_CPU(cs); | ||
171 | @@ -XXX,XX +XXX,XX @@ static bool ppc_cpu_has_work(CPUState *cs) | ||
172 | |||
173 | return pcc->has_work(cs); | ||
174 | } | ||
175 | +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ | ||
176 | |||
177 | static void ppc_cpu_reset(DeviceState *dev) | ||
178 | { | ||
179 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps ppc_tcg_ops = { | ||
180 | .tlb_fill = ppc_cpu_tlb_fill, | ||
181 | |||
182 | #ifndef CONFIG_USER_ONLY | ||
183 | + .has_work = ppc_cpu_has_work, | ||
184 | .cpu_exec_interrupt = ppc_cpu_exec_interrupt, | ||
185 | .do_interrupt = ppc_cpu_do_interrupt, | ||
186 | .cpu_exec_enter = ppc_cpu_exec_enter, | ||
187 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) | ||
188 | device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, | ||
189 | &pcc->parent_unrealize); | ||
190 | pcc->pvr_match = ppc_pvr_match_default; | ||
191 | - pcc->has_work = cpu_has_work_default; | ||
192 | device_class_set_props(dc, ppc_cpu_properties); | ||
193 | |||
194 | device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); | ||
195 | |||
196 | cc->class_by_name = ppc_cpu_class_by_name; | ||
197 | - cc->has_work = ppc_cpu_has_work; | ||
198 | cc->dump_state = ppc_cpu_dump_state; | ||
199 | cc->set_pc = ppc_cpu_set_pc; | ||
200 | cc->gdb_read_register = ppc_cpu_gdb_read_register; | ||
201 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) | ||
202 | |||
203 | #ifdef CONFIG_TCG | ||
204 | cc->tcg_ops = &ppc_tcg_ops; | ||
205 | +#ifndef CONFIG_USER_ONLY | ||
206 | + pcc->has_work = cpu_has_work_default; | ||
207 | +#endif | ||
208 | #endif /* CONFIG_TCG */ | ||
209 | } | ||
210 | |||
211 | -- | ||
212 | 2.25.1 | ||
213 | |||
214 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to TCG sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-23-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/riscv/cpu.c | 8 +++----- | ||
11 | 1 file changed, 3 insertions(+), 5 deletions(-) | ||
12 | |||
13 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/riscv/cpu.c | ||
16 | +++ b/target/riscv/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, | ||
18 | env->pc = tb->pc; | ||
19 | } | ||
20 | |||
21 | +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) | ||
22 | static bool riscv_cpu_has_work(CPUState *cs) | ||
23 | { | ||
24 | -#ifndef CONFIG_USER_ONLY | ||
25 | RISCVCPU *cpu = RISCV_CPU(cs); | ||
26 | CPURISCVState *env = &cpu->env; | ||
27 | /* | ||
28 | @@ -XXX,XX +XXX,XX @@ static bool riscv_cpu_has_work(CPUState *cs) | ||
29 | * mode and delegation registers, but respect individual enables | ||
30 | */ | ||
31 | return (env->mip & env->mie) != 0; | ||
32 | -#else | ||
33 | - return true; | ||
34 | -#endif | ||
35 | } | ||
36 | +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ | ||
37 | |||
38 | void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, | ||
39 | target_ulong *data) | ||
40 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps riscv_tcg_ops = { | ||
41 | .tlb_fill = riscv_cpu_tlb_fill, | ||
42 | |||
43 | #ifndef CONFIG_USER_ONLY | ||
44 | + .has_work = riscv_cpu_has_work, | ||
45 | .cpu_exec_interrupt = riscv_cpu_exec_interrupt, | ||
46 | .do_interrupt = riscv_cpu_do_interrupt, | ||
47 | .do_transaction_failed = riscv_cpu_do_transaction_failed, | ||
48 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) | ||
49 | device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); | ||
50 | |||
51 | cc->class_by_name = riscv_cpu_class_by_name; | ||
52 | - cc->has_work = riscv_cpu_has_work; | ||
53 | cc->dump_state = riscv_cpu_dump_state; | ||
54 | cc->set_pc = riscv_cpu_set_pc; | ||
55 | cc->gdb_read_register = riscv_cpu_gdb_read_register; | ||
56 | -- | ||
57 | 2.25.1 | ||
58 | |||
59 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-24-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/rx/cpu.c | 4 +++- | ||
11 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/rx/cpu.c b/target/rx/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/rx/cpu.c | ||
16 | +++ b/target/rx/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void rx_cpu_synchronize_from_tb(CPUState *cs, | ||
18 | cpu->env.pc = tb->pc; | ||
19 | } | ||
20 | |||
21 | +#if !defined(CONFIG_USER_ONLY) | ||
22 | static bool rx_cpu_has_work(CPUState *cs) | ||
23 | { | ||
24 | return cs->interrupt_request & | ||
25 | (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); | ||
26 | } | ||
27 | +#endif /* !CONFIG_USER_ONLY */ | ||
28 | |||
29 | static void rx_cpu_reset(DeviceState *dev) | ||
30 | { | ||
31 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps rx_tcg_ops = { | ||
32 | .tlb_fill = rx_cpu_tlb_fill, | ||
33 | |||
34 | #ifndef CONFIG_USER_ONLY | ||
35 | + .has_work = rx_cpu_has_work, | ||
36 | .cpu_exec_interrupt = rx_cpu_exec_interrupt, | ||
37 | .do_interrupt = rx_cpu_do_interrupt, | ||
38 | #endif /* !CONFIG_USER_ONLY */ | ||
39 | @@ -XXX,XX +XXX,XX @@ static void rx_cpu_class_init(ObjectClass *klass, void *data) | ||
40 | &rcc->parent_reset); | ||
41 | |||
42 | cc->class_by_name = rx_cpu_class_by_name; | ||
43 | - cc->has_work = rx_cpu_has_work; | ||
44 | cc->dump_state = rx_cpu_dump_state; | ||
45 | cc->set_pc = rx_cpu_set_pc; | ||
46 | |||
47 | -- | ||
48 | 2.25.1 | ||
49 | |||
50 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to TCG sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-25-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/s390x/cpu.c | 4 +++- | ||
11 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/s390x/cpu.c | ||
16 | +++ b/target/s390x/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value) | ||
18 | cpu->env.psw.addr = value; | ||
19 | } | ||
20 | |||
21 | +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) | ||
22 | static bool s390_cpu_has_work(CPUState *cs) | ||
23 | { | ||
24 | S390CPU *cpu = S390_CPU(cs); | ||
25 | @@ -XXX,XX +XXX,XX @@ static bool s390_cpu_has_work(CPUState *cs) | ||
26 | |||
27 | return s390_cpu_has_int(cpu); | ||
28 | } | ||
29 | +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ | ||
30 | |||
31 | /* S390CPUClass::reset() */ | ||
32 | static void s390_cpu_reset(CPUState *s, cpu_reset_type type) | ||
33 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps s390_tcg_ops = { | ||
34 | .tlb_fill = s390_cpu_tlb_fill, | ||
35 | |||
36 | #if !defined(CONFIG_USER_ONLY) | ||
37 | + .has_work = s390_cpu_has_work, | ||
38 | .cpu_exec_interrupt = s390_cpu_exec_interrupt, | ||
39 | .do_interrupt = s390_cpu_do_interrupt, | ||
40 | .debug_excp_handler = s390x_cpu_debug_excp_handler, | ||
41 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) | ||
42 | |||
43 | scc->reset = s390_cpu_reset; | ||
44 | cc->class_by_name = s390_cpu_class_by_name, | ||
45 | - cc->has_work = s390_cpu_has_work; | ||
46 | cc->dump_state = s390_cpu_dump_state; | ||
47 | cc->set_pc = s390_cpu_set_pc; | ||
48 | cc->gdb_read_register = s390_cpu_gdb_read_register; | ||
49 | -- | ||
50 | 2.25.1 | ||
51 | |||
52 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-26-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/sh4/cpu.c | 5 +++-- | ||
11 | 1 file changed, 3 insertions(+), 2 deletions(-) | ||
12 | |||
13 | diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/sh4/cpu.c | ||
16 | +++ b/target/sh4/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static bool superh_io_recompile_replay_branch(CPUState *cs, | ||
18 | } | ||
19 | return false; | ||
20 | } | ||
21 | -#endif | ||
22 | |||
23 | static bool superh_cpu_has_work(CPUState *cs) | ||
24 | { | ||
25 | return cs->interrupt_request & CPU_INTERRUPT_HARD; | ||
26 | } | ||
27 | |||
28 | +#endif /* !CONFIG_USER_ONLY */ | ||
29 | + | ||
30 | static void superh_cpu_reset(DeviceState *dev) | ||
31 | { | ||
32 | CPUState *s = CPU(dev); | ||
33 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps superh_tcg_ops = { | ||
34 | .tlb_fill = superh_cpu_tlb_fill, | ||
35 | |||
36 | #ifndef CONFIG_USER_ONLY | ||
37 | + .has_work = superh_cpu_has_work, | ||
38 | .cpu_exec_interrupt = superh_cpu_exec_interrupt, | ||
39 | .do_interrupt = superh_cpu_do_interrupt, | ||
40 | .do_unaligned_access = superh_cpu_do_unaligned_access, | ||
41 | @@ -XXX,XX +XXX,XX @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) | ||
42 | device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset); | ||
43 | |||
44 | cc->class_by_name = superh_cpu_class_by_name; | ||
45 | - cc->has_work = superh_cpu_has_work; | ||
46 | cc->dump_state = superh_cpu_dump_state; | ||
47 | cc->set_pc = superh_cpu_set_pc; | ||
48 | cc->gdb_read_register = superh_cpu_gdb_read_register; | ||
49 | -- | ||
50 | 2.25.1 | ||
51 | |||
52 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | The SPARC target only support TCG acceleration. Remove the CONFIG_TCG | ||
4 | definition introduced by mistake in commit 78271684719 ("cpu: tcg_ops: | ||
5 | move to tcg-cpu-ops.h, keep a pointer in CPUClass"). | ||
6 | |||
7 | Reported-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-Id: <20210912172731.789788-27-f4bug@amsat.org> | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | --- | ||
13 | target/sparc/cpu.c | 2 -- | ||
14 | 1 file changed, 2 deletions(-) | ||
15 | |||
16 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/sparc/cpu.c | ||
19 | +++ b/target/sparc/cpu.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static const struct SysemuCPUOps sparc_sysemu_ops = { | ||
21 | }; | ||
22 | #endif | ||
23 | |||
24 | -#ifdef CONFIG_TCG | ||
25 | #include "hw/core/tcg-cpu-ops.h" | ||
26 | |||
27 | static const struct TCGCPUOps sparc_tcg_ops = { | ||
28 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps sparc_tcg_ops = { | ||
29 | .do_unaligned_access = sparc_cpu_do_unaligned_access, | ||
30 | #endif /* !CONFIG_USER_ONLY */ | ||
31 | }; | ||
32 | -#endif /* CONFIG_TCG */ | ||
33 | |||
34 | static void sparc_cpu_class_init(ObjectClass *oc, void *data) | ||
35 | { | ||
36 | -- | ||
37 | 2.25.1 | ||
38 | |||
39 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-28-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/sparc/cpu.c | 4 +++- | ||
11 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/sparc/cpu.c | ||
16 | +++ b/target/sparc/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, | ||
18 | cpu->env.npc = tb->cs_base; | ||
19 | } | ||
20 | |||
21 | +#if !defined(CONFIG_USER_ONLY) | ||
22 | static bool sparc_cpu_has_work(CPUState *cs) | ||
23 | { | ||
24 | SPARCCPU *cpu = SPARC_CPU(cs); | ||
25 | @@ -XXX,XX +XXX,XX @@ static bool sparc_cpu_has_work(CPUState *cs) | ||
26 | return (cs->interrupt_request & CPU_INTERRUPT_HARD) && | ||
27 | cpu_interrupts_enabled(env); | ||
28 | } | ||
29 | +#endif /* !CONFIG_USER_ONLY */ | ||
30 | |||
31 | static char *sparc_cpu_type_name(const char *cpu_model) | ||
32 | { | ||
33 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps sparc_tcg_ops = { | ||
34 | .tlb_fill = sparc_cpu_tlb_fill, | ||
35 | |||
36 | #ifndef CONFIG_USER_ONLY | ||
37 | + .has_work = sparc_cpu_has_work, | ||
38 | .cpu_exec_interrupt = sparc_cpu_exec_interrupt, | ||
39 | .do_interrupt = sparc_cpu_do_interrupt, | ||
40 | .do_transaction_failed = sparc_cpu_do_transaction_failed, | ||
41 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) | ||
42 | |||
43 | cc->class_by_name = sparc_cpu_class_by_name; | ||
44 | cc->parse_features = sparc_cpu_parse_features; | ||
45 | - cc->has_work = sparc_cpu_has_work; | ||
46 | cc->dump_state = sparc_cpu_dump_state; | ||
47 | #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) | ||
48 | cc->memory_rw_debug = sparc_cpu_memory_rw_debug; | ||
49 | -- | ||
50 | 2.25.1 | ||
51 | |||
52 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-29-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/tricore/cpu.c | 6 +++++- | ||
11 | 1 file changed, 5 insertions(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/tricore/cpu.c | ||
16 | +++ b/target/tricore/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void tricore_cpu_reset(DeviceState *dev) | ||
18 | cpu_state_reset(env); | ||
19 | } | ||
20 | |||
21 | +#if !defined(CONFIG_USER_ONLY) | ||
22 | static bool tricore_cpu_has_work(CPUState *cs) | ||
23 | { | ||
24 | return true; | ||
25 | } | ||
26 | +#endif /* !CONFIG_USER_ONLY */ | ||
27 | |||
28 | static void tricore_cpu_realizefn(DeviceState *dev, Error **errp) | ||
29 | { | ||
30 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps tricore_tcg_ops = { | ||
31 | .initialize = tricore_tcg_init, | ||
32 | .synchronize_from_tb = tricore_cpu_synchronize_from_tb, | ||
33 | .tlb_fill = tricore_cpu_tlb_fill, | ||
34 | +#if !defined(CONFIG_USER_ONLY) | ||
35 | + .has_work = tricore_cpu_has_work, | ||
36 | +#endif | ||
37 | }; | ||
38 | |||
39 | static void tricore_cpu_class_init(ObjectClass *c, void *data) | ||
40 | @@ -XXX,XX +XXX,XX @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) | ||
41 | |||
42 | device_class_set_parent_reset(dc, tricore_cpu_reset, &mcc->parent_reset); | ||
43 | cc->class_by_name = tricore_cpu_class_by_name; | ||
44 | - cc->has_work = tricore_cpu_has_work; | ||
45 | |||
46 | cc->gdb_read_register = tricore_cpu_gdb_read_register; | ||
47 | cc->gdb_write_register = tricore_cpu_gdb_write_register; | ||
48 | -- | ||
49 | 2.25.1 | ||
50 | |||
51 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Restrict has_work() to sysemu. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-Id: <20210912172731.789788-30-f4bug@amsat.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | --- | ||
10 | target/xtensa/cpu.c | 14 +++++++------- | ||
11 | 1 file changed, 7 insertions(+), 7 deletions(-) | ||
12 | |||
13 | diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/xtensa/cpu.c | ||
16 | +++ b/target/xtensa/cpu.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) | ||
18 | cpu->env.pc = value; | ||
19 | } | ||
20 | |||
21 | +#ifndef CONFIG_USER_ONLY | ||
22 | + | ||
23 | static bool xtensa_cpu_has_work(CPUState *cs) | ||
24 | { | ||
25 | -#ifndef CONFIG_USER_ONLY | ||
26 | XtensaCPU *cpu = XTENSA_CPU(cs); | ||
27 | |||
28 | return !cpu->env.runstall && cpu->env.pending_irq_level; | ||
29 | -#else | ||
30 | - return true; | ||
31 | -#endif | ||
32 | } | ||
33 | |||
34 | -#ifdef CONFIG_USER_ONLY | ||
35 | +#else /* CONFIG_USER_ONLY*/ | ||
36 | + | ||
37 | static bool abi_call0; | ||
38 | |||
39 | void xtensa_set_abi_call0(void) | ||
40 | @@ -XXX,XX +XXX,XX @@ bool xtensa_abi_call0(void) | ||
41 | { | ||
42 | return abi_call0; | ||
43 | } | ||
44 | -#endif | ||
45 | + | ||
46 | +#endif /* CONFIG_USER_ONLY */ | ||
47 | |||
48 | static void xtensa_cpu_reset(DeviceState *dev) | ||
49 | { | ||
50 | @@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps xtensa_tcg_ops = { | ||
51 | .debug_excp_handler = xtensa_breakpoint_handler, | ||
52 | |||
53 | #ifndef CONFIG_USER_ONLY | ||
54 | + .has_work = xtensa_cpu_has_work, | ||
55 | .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, | ||
56 | .do_interrupt = xtensa_cpu_do_interrupt, | ||
57 | .do_transaction_failed = xtensa_cpu_do_transaction_failed, | ||
58 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) | ||
59 | device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset); | ||
60 | |||
61 | cc->class_by_name = xtensa_cpu_class_by_name; | ||
62 | - cc->has_work = xtensa_cpu_has_work; | ||
63 | cc->dump_state = xtensa_cpu_dump_state; | ||
64 | cc->set_pc = xtensa_cpu_set_pc; | ||
65 | cc->gdb_read_register = xtensa_cpu_gdb_read_register; | ||
66 | -- | ||
67 | 2.25.1 | ||
68 | |||
69 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | cpu_common_has_work() is the default has_work() implementation | ||
4 | and returns 'false'. | ||
5 | |||
6 | Explicit it for the QTest / HAX / HVF / NVMM / Xen accelerators | ||
7 | and remove cpu_common_has_work(). | ||
8 | |||
9 | Since there are no more implementations of SysemuCPUOps::has_work, | ||
10 | remove it along with the assertion in cpu_has_work(). | ||
11 | |||
12 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Acked-by: Paul Durrant <paul@xen.org> | ||
15 | Message-Id: <20210912172731.789788-31-f4bug@amsat.org> | ||
16 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | --- | ||
18 | include/hw/core/cpu.h | 2 -- | ||
19 | accel/hvf/hvf-accel-ops.c | 6 ++++++ | ||
20 | accel/qtest/qtest.c | 6 ++++++ | ||
21 | accel/xen/xen-all.c | 6 ++++++ | ||
22 | hw/core/cpu-common.c | 6 ------ | ||
23 | softmmu/cpus.c | 9 ++------- | ||
24 | target/i386/hax/hax-accel-ops.c | 6 ++++++ | ||
25 | target/i386/nvmm/nvmm-accel-ops.c | 6 ++++++ | ||
26 | 8 files changed, 32 insertions(+), 15 deletions(-) | ||
27 | |||
28 | diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/include/hw/core/cpu.h | ||
31 | +++ b/include/hw/core/cpu.h | ||
32 | @@ -XXX,XX +XXX,XX @@ struct SysemuCPUOps; | ||
33 | * instantiatable CPU type. | ||
34 | * @parse_features: Callback to parse command line arguments. | ||
35 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. | ||
36 | - * @has_work: Callback for checking if there is work to do. | ||
37 | * @memory_rw_debug: Callback for GDB memory access. | ||
38 | * @dump_state: Callback for dumping state. | ||
39 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. | ||
40 | @@ -XXX,XX +XXX,XX @@ struct CPUClass { | ||
41 | void (*parse_features)(const char *typename, char *str, Error **errp); | ||
42 | |||
43 | int reset_dump_flags; | ||
44 | - bool (*has_work)(CPUState *cpu); | ||
45 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, | ||
46 | uint8_t *buf, int len, bool is_write); | ||
47 | void (*dump_state)(CPUState *cpu, FILE *, int flags); | ||
48 | diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/accel/hvf/hvf-accel-ops.c | ||
51 | +++ b/accel/hvf/hvf-accel-ops.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static void hvf_start_vcpu_thread(CPUState *cpu) | ||
53 | cpu, QEMU_THREAD_JOINABLE); | ||
54 | } | ||
55 | |||
56 | +static bool hvf_cpu_has_work(CPUState *cpu) | ||
57 | +{ | ||
58 | + return false; | ||
59 | +} | ||
60 | + | ||
61 | static void hvf_accel_ops_class_init(ObjectClass *oc, void *data) | ||
62 | { | ||
63 | AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); | ||
64 | @@ -XXX,XX +XXX,XX @@ static void hvf_accel_ops_class_init(ObjectClass *oc, void *data) | ||
65 | ops->synchronize_post_init = hvf_cpu_synchronize_post_init; | ||
66 | ops->synchronize_state = hvf_cpu_synchronize_state; | ||
67 | ops->synchronize_pre_loadvm = hvf_cpu_synchronize_pre_loadvm; | ||
68 | + ops->has_work = hvf_cpu_has_work; | ||
69 | }; | ||
70 | static const TypeInfo hvf_accel_ops_type = { | ||
71 | .name = ACCEL_OPS_NAME("hvf"), | ||
72 | diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/accel/qtest/qtest.c | ||
75 | +++ b/accel/qtest/qtest.c | ||
76 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo qtest_accel_type = { | ||
77 | }; | ||
78 | module_obj(TYPE_QTEST_ACCEL); | ||
79 | |||
80 | +static bool qtest_cpu_has_work(CPUState *cpu) | ||
81 | +{ | ||
82 | + return false; | ||
83 | +} | ||
84 | + | ||
85 | static void qtest_accel_ops_class_init(ObjectClass *oc, void *data) | ||
86 | { | ||
87 | AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); | ||
88 | |||
89 | ops->create_vcpu_thread = dummy_start_vcpu_thread; | ||
90 | ops->get_virtual_clock = qtest_get_virtual_clock; | ||
91 | + ops->has_work = qtest_cpu_has_work; | ||
92 | }; | ||
93 | |||
94 | static const TypeInfo qtest_accel_ops_type = { | ||
95 | diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c | ||
96 | index XXXXXXX..XXXXXXX 100644 | ||
97 | --- a/accel/xen/xen-all.c | ||
98 | +++ b/accel/xen/xen-all.c | ||
99 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo xen_accel_type = { | ||
100 | .class_init = xen_accel_class_init, | ||
101 | }; | ||
102 | |||
103 | +static bool xen_cpu_has_work(CPUState *cpu) | ||
104 | +{ | ||
105 | + return false; | ||
106 | +} | ||
107 | + | ||
108 | static void xen_accel_ops_class_init(ObjectClass *oc, void *data) | ||
109 | { | ||
110 | AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); | ||
111 | |||
112 | ops->create_vcpu_thread = dummy_start_vcpu_thread; | ||
113 | + ops->has_work = xen_cpu_has_work; | ||
114 | } | ||
115 | |||
116 | static const TypeInfo xen_accel_ops_type = { | ||
117 | diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c | ||
118 | index XXXXXXX..XXXXXXX 100644 | ||
119 | --- a/hw/core/cpu-common.c | ||
120 | +++ b/hw/core/cpu-common.c | ||
121 | @@ -XXX,XX +XXX,XX @@ static void cpu_common_reset(DeviceState *dev) | ||
122 | } | ||
123 | } | ||
124 | |||
125 | -static bool cpu_common_has_work(CPUState *cs) | ||
126 | -{ | ||
127 | - return false; | ||
128 | -} | ||
129 | - | ||
130 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) | ||
131 | { | ||
132 | CPUClass *cc = CPU_CLASS(object_class_by_name(typename)); | ||
133 | @@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data) | ||
134 | |||
135 | k->parse_features = cpu_common_parse_features; | ||
136 | k->get_arch_id = cpu_common_get_arch_id; | ||
137 | - k->has_work = cpu_common_has_work; | ||
138 | k->gdb_read_register = cpu_common_gdb_read_register; | ||
139 | k->gdb_write_register = cpu_common_gdb_write_register; | ||
140 | set_bit(DEVICE_CATEGORY_CPU, dc->categories); | ||
141 | diff --git a/softmmu/cpus.c b/softmmu/cpus.c | ||
142 | index XXXXXXX..XXXXXXX 100644 | ||
143 | --- a/softmmu/cpus.c | ||
144 | +++ b/softmmu/cpus.c | ||
145 | @@ -XXX,XX +XXX,XX @@ void cpu_interrupt(CPUState *cpu, int mask) | ||
146 | |||
147 | bool cpu_has_work(CPUState *cpu) | ||
148 | { | ||
149 | - CPUClass *cc = CPU_GET_CLASS(cpu); | ||
150 | - | ||
151 | - if (cpus_accel->has_work) { | ||
152 | - return cpus_accel->has_work(cpu); | ||
153 | - } | ||
154 | - g_assert(cc->has_work); | ||
155 | - return cc->has_work(cpu); | ||
156 | + g_assert(cpus_accel->has_work); | ||
157 | + return cpus_accel->has_work(cpu); | ||
158 | } | ||
159 | |||
160 | static int do_vm_stop(RunState state, bool send_stop) | ||
161 | diff --git a/target/i386/hax/hax-accel-ops.c b/target/i386/hax/hax-accel-ops.c | ||
162 | index XXXXXXX..XXXXXXX 100644 | ||
163 | --- a/target/i386/hax/hax-accel-ops.c | ||
164 | +++ b/target/i386/hax/hax-accel-ops.c | ||
165 | @@ -XXX,XX +XXX,XX @@ static void hax_start_vcpu_thread(CPUState *cpu) | ||
166 | #endif | ||
167 | } | ||
168 | |||
169 | +static bool hax_cpu_has_work(CPUState *cpu) | ||
170 | +{ | ||
171 | + return false; | ||
172 | +} | ||
173 | + | ||
174 | static void hax_accel_ops_class_init(ObjectClass *oc, void *data) | ||
175 | { | ||
176 | AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); | ||
177 | @@ -XXX,XX +XXX,XX @@ static void hax_accel_ops_class_init(ObjectClass *oc, void *data) | ||
178 | ops->synchronize_post_init = hax_cpu_synchronize_post_init; | ||
179 | ops->synchronize_state = hax_cpu_synchronize_state; | ||
180 | ops->synchronize_pre_loadvm = hax_cpu_synchronize_pre_loadvm; | ||
181 | + ops->has_work = hax_cpu_has_work; | ||
182 | } | ||
183 | |||
184 | static const TypeInfo hax_accel_ops_type = { | ||
185 | diff --git a/target/i386/nvmm/nvmm-accel-ops.c b/target/i386/nvmm/nvmm-accel-ops.c | ||
186 | index XXXXXXX..XXXXXXX 100644 | ||
187 | --- a/target/i386/nvmm/nvmm-accel-ops.c | ||
188 | +++ b/target/i386/nvmm/nvmm-accel-ops.c | ||
189 | @@ -XXX,XX +XXX,XX @@ static void nvmm_kick_vcpu_thread(CPUState *cpu) | ||
190 | cpus_kick_thread(cpu); | ||
191 | } | ||
192 | |||
193 | +static bool nvmm_cpu_has_work(CPUState *cpu) | ||
194 | +{ | ||
195 | + return false; | ||
196 | +} | ||
197 | + | ||
198 | static void nvmm_accel_ops_class_init(ObjectClass *oc, void *data) | ||
199 | { | ||
200 | AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); | ||
201 | @@ -XXX,XX +XXX,XX @@ static void nvmm_accel_ops_class_init(ObjectClass *oc, void *data) | ||
202 | ops->synchronize_post_init = nvmm_cpu_synchronize_post_init; | ||
203 | ops->synchronize_state = nvmm_cpu_synchronize_state; | ||
204 | ops->synchronize_pre_loadvm = nvmm_cpu_synchronize_pre_loadvm; | ||
205 | + ops->has_work = nvmm_cpu_has_work; | ||
206 | } | ||
207 | |||
208 | static const TypeInfo nvmm_accel_ops_type = { | ||
209 | -- | ||
210 | 2.25.1 | ||
211 | |||
212 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Let the compiler decide about inlining. | ||
2 | Remove tcg_out_ext8s and tcg_out_ext16s as unused. | ||
3 | 1 | ||
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | tcg/mips/tcg-target.c.inc | 76 ++++++++++++++------------------------- | ||
8 | 1 file changed, 27 insertions(+), 49 deletions(-) | ||
9 | |||
10 | diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/tcg/mips/tcg-target.c.inc | ||
13 | +++ b/tcg/mips/tcg-target.c.inc | ||
14 | @@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, | ||
15 | #endif | ||
16 | |||
17 | |||
18 | -static inline bool is_p2m1(tcg_target_long val) | ||
19 | +static bool is_p2m1(tcg_target_long val) | ||
20 | { | ||
21 | return val && ((val + 1) & val) == 0; | ||
22 | } | ||
23 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
24 | /* | ||
25 | * Type reg | ||
26 | */ | ||
27 | -static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, | ||
28 | - TCGReg rd, TCGReg rs, TCGReg rt) | ||
29 | +static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, | ||
30 | + TCGReg rd, TCGReg rs, TCGReg rt) | ||
31 | { | ||
32 | int32_t inst; | ||
33 | |||
34 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, | ||
35 | /* | ||
36 | * Type immediate | ||
37 | */ | ||
38 | -static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, | ||
39 | - TCGReg rt, TCGReg rs, TCGArg imm) | ||
40 | +static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, | ||
41 | + TCGReg rt, TCGReg rs, TCGArg imm) | ||
42 | { | ||
43 | int32_t inst; | ||
44 | |||
45 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, | ||
46 | /* | ||
47 | * Type bitfield | ||
48 | */ | ||
49 | -static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, | ||
50 | - TCGReg rs, int msb, int lsb) | ||
51 | +static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, | ||
52 | + TCGReg rs, int msb, int lsb) | ||
53 | { | ||
54 | int32_t inst; | ||
55 | |||
56 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, | ||
57 | tcg_out32(s, inst); | ||
58 | } | ||
59 | |||
60 | -static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, | ||
61 | - MIPSInsn oph, TCGReg rt, TCGReg rs, | ||
62 | +static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, | ||
63 | + MIPSInsn oph, TCGReg rt, TCGReg rs, | ||
64 | int msb, int lsb) | ||
65 | { | ||
66 | if (lsb >= 32) { | ||
67 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, | ||
68 | /* | ||
69 | * Type branch | ||
70 | */ | ||
71 | -static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, | ||
72 | - TCGReg rt, TCGReg rs) | ||
73 | +static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) | ||
74 | { | ||
75 | tcg_out_opc_imm(s, opc, rt, rs, 0); | ||
76 | } | ||
77 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, | ||
78 | /* | ||
79 | * Type sa | ||
80 | */ | ||
81 | -static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, | ||
82 | - TCGReg rd, TCGReg rt, TCGArg sa) | ||
83 | +static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, | ||
84 | + TCGReg rd, TCGReg rt, TCGArg sa) | ||
85 | { | ||
86 | int32_t inst; | ||
87 | |||
88 | @@ -XXX,XX +XXX,XX @@ static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) | ||
89 | return true; | ||
90 | } | ||
91 | |||
92 | -static inline void tcg_out_nop(TCGContext *s) | ||
93 | +static void tcg_out_nop(TCGContext *s) | ||
94 | { | ||
95 | tcg_out32(s, 0); | ||
96 | } | ||
97 | |||
98 | -static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) | ||
99 | +static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) | ||
100 | { | ||
101 | tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); | ||
102 | } | ||
103 | |||
104 | -static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) | ||
105 | +static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) | ||
106 | { | ||
107 | tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); | ||
108 | } | ||
109 | |||
110 | -static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) | ||
111 | +static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) | ||
112 | { | ||
113 | tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); | ||
114 | } | ||
115 | |||
116 | -static inline bool tcg_out_mov(TCGContext *s, TCGType type, | ||
117 | - TCGReg ret, TCGReg arg) | ||
118 | +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) | ||
119 | { | ||
120 | /* Simple reg-reg move, optimising out the 'do nothing' case */ | ||
121 | if (ret != arg) { | ||
122 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) | ||
123 | } | ||
124 | } | ||
125 | |||
126 | -static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) | ||
127 | -{ | ||
128 | - if (use_mips32r2_instructions) { | ||
129 | - tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); | ||
130 | - } else { | ||
131 | - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); | ||
132 | - tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24); | ||
133 | - } | ||
134 | -} | ||
135 | - | ||
136 | -static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) | ||
137 | -{ | ||
138 | - if (use_mips32r2_instructions) { | ||
139 | - tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); | ||
140 | - } else { | ||
141 | - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); | ||
142 | - tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); | ||
143 | - } | ||
144 | -} | ||
145 | - | ||
146 | -static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) | ||
147 | +static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) | ||
148 | { | ||
149 | if (use_mips32r2_instructions) { | ||
150 | tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); | ||
151 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, | ||
152 | tcg_out_opc_imm(s, opc, data, addr, lo); | ||
153 | } | ||
154 | |||
155 | -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, | ||
156 | - TCGReg arg1, intptr_t arg2) | ||
157 | +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, | ||
158 | + TCGReg arg1, intptr_t arg2) | ||
159 | { | ||
160 | MIPSInsn opc = OPC_LD; | ||
161 | if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { | ||
162 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, | ||
163 | tcg_out_ldst(s, opc, arg, arg1, arg2); | ||
164 | } | ||
165 | |||
166 | -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, | ||
167 | - TCGReg arg1, intptr_t arg2) | ||
168 | +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, | ||
169 | + TCGReg arg1, intptr_t arg2) | ||
170 | { | ||
171 | MIPSInsn opc = OPC_SD; | ||
172 | if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { | ||
173 | @@ -XXX,XX +XXX,XX @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, | ||
174 | tcg_out_ldst(s, opc, arg, arg1, arg2); | ||
175 | } | ||
176 | |||
177 | -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, | ||
178 | - TCGReg base, intptr_t ofs) | ||
179 | +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, | ||
180 | + TCGReg base, intptr_t ofs) | ||
181 | { | ||
182 | if (val == 0) { | ||
183 | tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); | ||
184 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, | ||
185 | } | ||
186 | } | ||
187 | |||
188 | -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, | ||
189 | - const TCGArg args[TCG_MAX_OP_ARGS], | ||
190 | - const int const_args[TCG_MAX_OP_ARGS]) | ||
191 | +static void tcg_out_op(TCGContext *s, TCGOpcode opc, | ||
192 | + const TCGArg args[TCG_MAX_OP_ARGS], | ||
193 | + const int const_args[TCG_MAX_OP_ARGS]) | ||
194 | { | ||
195 | MIPSInsn i1, i2; | ||
196 | TCGArg a0, a1, a2; | ||
197 | -- | ||
198 | 2.25.1 | ||
199 | |||
200 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Weaning off of unique alignment requirements, so allow JAL | ||
2 | to not reach the target. TCG_TMP1 is always available for | ||
3 | use as a scratch because it is clobbered by the subroutine | ||
4 | being called. | ||
5 | 1 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | --- | ||
8 | tcg/mips/tcg-target.c.inc | 6 ++++-- | ||
9 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
10 | |||
11 | diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/tcg/mips/tcg-target.c.inc | ||
14 | +++ b/tcg/mips/tcg-target.c.inc | ||
15 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) | ||
16 | |||
17 | static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) | ||
18 | { | ||
19 | - bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); | ||
20 | - tcg_debug_assert(ok); | ||
21 | + if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { | ||
22 | + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); | ||
23 | + tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); | ||
24 | + } | ||
25 | } | ||
26 | |||
27 | static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) | ||
28 | -- | ||
29 | 2.25.1 | ||
30 | |||
31 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Only use indirect jumps. Finish weaning away from the | ||
2 | unique alignment requirements for code_gen_buffer. | ||
3 | 1 | ||
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | tcg/mips/tcg-target.h | 12 +++++------- | ||
8 | tcg/mips/tcg-target.c.inc | 23 +++++------------------ | ||
9 | 2 files changed, 10 insertions(+), 25 deletions(-) | ||
10 | |||
11 | diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/tcg/mips/tcg-target.h | ||
14 | +++ b/tcg/mips/tcg-target.h | ||
15 | @@ -XXX,XX +XXX,XX @@ | ||
16 | #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 | ||
17 | #define TCG_TARGET_NB_REGS 32 | ||
18 | |||
19 | -/* | ||
20 | - * We have a 256MB branch region, but leave room to make sure the | ||
21 | - * main executable is also within that region. | ||
22 | - */ | ||
23 | -#define MAX_CODE_GEN_BUFFER_SIZE (128 * MiB) | ||
24 | +#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) | ||
25 | |||
26 | typedef enum { | ||
27 | TCG_REG_ZERO = 0, | ||
28 | @@ -XXX,XX +XXX,XX @@ extern bool use_mips32r2_instructions; | ||
29 | #define TCG_TARGET_HAS_muluh_i32 1 | ||
30 | #define TCG_TARGET_HAS_mulsh_i32 1 | ||
31 | #define TCG_TARGET_HAS_bswap32_i32 1 | ||
32 | -#define TCG_TARGET_HAS_direct_jump 1 | ||
33 | +#define TCG_TARGET_HAS_direct_jump 0 | ||
34 | |||
35 | #if TCG_TARGET_REG_BITS == 64 | ||
36 | #define TCG_TARGET_HAS_add2_i32 0 | ||
37 | @@ -XXX,XX +XXX,XX @@ extern bool use_mips32r2_instructions; | ||
38 | #define TCG_TARGET_DEFAULT_MO (0) | ||
39 | #define TCG_TARGET_HAS_MEMORY_BSWAP 1 | ||
40 | |||
41 | -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); | ||
42 | +/* not defined -- call should be eliminated at compile time */ | ||
43 | +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t) | ||
44 | + QEMU_ERROR("code path is reachable"); | ||
45 | |||
46 | #ifdef CONFIG_SOFTMMU | ||
47 | #define TCG_TARGET_NEED_LDST_LABELS | ||
48 | diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/tcg/mips/tcg-target.c.inc | ||
51 | +++ b/tcg/mips/tcg-target.c.inc | ||
52 | @@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, | ||
53 | } | ||
54 | break; | ||
55 | case INDEX_op_goto_tb: | ||
56 | - if (s->tb_jmp_insn_offset) { | ||
57 | - /* direct jump method */ | ||
58 | - s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); | ||
59 | - /* Avoid clobbering the address during retranslation. */ | ||
60 | - tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff)); | ||
61 | - } else { | ||
62 | - /* indirect jump method */ | ||
63 | - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, | ||
64 | - (uintptr_t)(s->tb_jmp_target_addr + a0)); | ||
65 | - tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); | ||
66 | - } | ||
67 | + /* indirect jump method */ | ||
68 | + tcg_debug_assert(s->tb_jmp_insn_offset == 0); | ||
69 | + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, | ||
70 | + (uintptr_t)(s->tb_jmp_target_addr + a0)); | ||
71 | + tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); | ||
72 | tcg_out_nop(s); | ||
73 | set_jmp_reset_offset(s, a0); | ||
74 | break; | ||
75 | @@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s) | ||
76 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ | ||
77 | } | ||
78 | |||
79 | -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, | ||
80 | - uintptr_t jmp_rw, uintptr_t addr) | ||
81 | -{ | ||
82 | - qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2)); | ||
83 | - flush_idcache_range(jmp_rx, jmp_rw, 4); | ||
84 | -} | ||
85 | - | ||
86 | typedef struct { | ||
87 | DebugFrameHeader h; | ||
88 | uint8_t fde_def_cfa[4]; | ||
89 | -- | ||
90 | 2.25.1 | ||
91 | |||
92 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | --- | ||
4 | tcg/region.c | 91 ---------------------------------------------------- | ||
5 | 1 file changed, 91 deletions(-) | ||
6 | 1 | ||
7 | diff --git a/tcg/region.c b/tcg/region.c | ||
8 | index XXXXXXX..XXXXXXX 100644 | ||
9 | --- a/tcg/region.c | ||
10 | +++ b/tcg/region.c | ||
11 | @@ -XXX,XX +XXX,XX @@ static size_t tcg_n_regions(size_t tb_size, unsigned max_cpus) | ||
12 | (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \ | ||
13 | ? DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE) | ||
14 | |||
15 | -#ifdef __mips__ | ||
16 | -/* | ||
17 | - * In order to use J and JAL within the code_gen_buffer, we require | ||
18 | - * that the buffer not cross a 256MB boundary. | ||
19 | - */ | ||
20 | -static inline bool cross_256mb(void *addr, size_t size) | ||
21 | -{ | ||
22 | - return ((uintptr_t)addr ^ ((uintptr_t)addr + size)) & ~0x0ffffffful; | ||
23 | -} | ||
24 | - | ||
25 | -/* | ||
26 | - * We weren't able to allocate a buffer without crossing that boundary, | ||
27 | - * so make do with the larger portion of the buffer that doesn't cross. | ||
28 | - * Returns the new base and size of the buffer in *obuf and *osize. | ||
29 | - */ | ||
30 | -static inline void split_cross_256mb(void **obuf, size_t *osize, | ||
31 | - void *buf1, size_t size1) | ||
32 | -{ | ||
33 | - void *buf2 = (void *)(((uintptr_t)buf1 + size1) & ~0x0ffffffful); | ||
34 | - size_t size2 = buf1 + size1 - buf2; | ||
35 | - | ||
36 | - size1 = buf2 - buf1; | ||
37 | - if (size1 < size2) { | ||
38 | - size1 = size2; | ||
39 | - buf1 = buf2; | ||
40 | - } | ||
41 | - | ||
42 | - *obuf = buf1; | ||
43 | - *osize = size1; | ||
44 | -} | ||
45 | -#endif | ||
46 | - | ||
47 | #ifdef USE_STATIC_CODE_GEN_BUFFER | ||
48 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] | ||
49 | __attribute__((aligned(CODE_GEN_ALIGN))); | ||
50 | @@ -XXX,XX +XXX,XX @@ static int alloc_code_gen_buffer(size_t tb_size, int splitwx, Error **errp) | ||
51 | size = QEMU_ALIGN_DOWN(tb_size, qemu_real_host_page_size); | ||
52 | } | ||
53 | |||
54 | -#ifdef __mips__ | ||
55 | - if (cross_256mb(buf, size)) { | ||
56 | - split_cross_256mb(&buf, &size, buf, size); | ||
57 | - } | ||
58 | -#endif | ||
59 | - | ||
60 | region.start_aligned = buf; | ||
61 | region.total_size = size; | ||
62 | |||
63 | @@ -XXX,XX +XXX,XX @@ static int alloc_code_gen_buffer_anon(size_t size, int prot, | ||
64 | return -1; | ||
65 | } | ||
66 | |||
67 | -#ifdef __mips__ | ||
68 | - if (cross_256mb(buf, size)) { | ||
69 | - /* | ||
70 | - * Try again, with the original still mapped, to avoid re-acquiring | ||
71 | - * the same 256mb crossing. | ||
72 | - */ | ||
73 | - size_t size2; | ||
74 | - void *buf2 = mmap(NULL, size, prot, flags, -1, 0); | ||
75 | - switch ((int)(buf2 != MAP_FAILED)) { | ||
76 | - case 1: | ||
77 | - if (!cross_256mb(buf2, size)) { | ||
78 | - /* Success! Use the new buffer. */ | ||
79 | - munmap(buf, size); | ||
80 | - break; | ||
81 | - } | ||
82 | - /* Failure. Work with what we had. */ | ||
83 | - munmap(buf2, size); | ||
84 | - /* fallthru */ | ||
85 | - default: | ||
86 | - /* Split the original buffer. Free the smaller half. */ | ||
87 | - split_cross_256mb(&buf2, &size2, buf, size); | ||
88 | - if (buf == buf2) { | ||
89 | - munmap(buf + size2, size - size2); | ||
90 | - } else { | ||
91 | - munmap(buf, size - size2); | ||
92 | - } | ||
93 | - size = size2; | ||
94 | - break; | ||
95 | - } | ||
96 | - buf = buf2; | ||
97 | - } | ||
98 | -#endif | ||
99 | - | ||
100 | region.start_aligned = buf; | ||
101 | region.total_size = size; | ||
102 | return prot; | ||
103 | @@ -XXX,XX +XXX,XX @@ static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) | ||
104 | void *buf_rw = NULL, *buf_rx = MAP_FAILED; | ||
105 | int fd = -1; | ||
106 | |||
107 | -#ifdef __mips__ | ||
108 | - /* Find space for the RX mapping, vs the 256MiB regions. */ | ||
109 | - if (alloc_code_gen_buffer_anon(size, PROT_NONE, | ||
110 | - MAP_PRIVATE | MAP_ANONYMOUS | | ||
111 | - MAP_NORESERVE, errp) < 0) { | ||
112 | - return false; | ||
113 | - } | ||
114 | - /* The size of the mapping may have been adjusted. */ | ||
115 | - buf_rx = region.start_aligned; | ||
116 | - size = region.total_size; | ||
117 | -#endif | ||
118 | - | ||
119 | buf_rw = qemu_memfd_alloc("tcg-jit", size, 0, &fd, errp); | ||
120 | if (buf_rw == NULL) { | ||
121 | goto fail; | ||
122 | } | ||
123 | |||
124 | -#ifdef __mips__ | ||
125 | - void *tmp = mmap(buf_rx, size, PROT_READ | PROT_EXEC, | ||
126 | - MAP_SHARED | MAP_FIXED, fd, 0); | ||
127 | - if (tmp != buf_rx) { | ||
128 | - goto fail_rx; | ||
129 | - } | ||
130 | -#else | ||
131 | buf_rx = mmap(NULL, size, PROT_READ | PROT_EXEC, MAP_SHARED, fd, 0); | ||
132 | if (buf_rx == MAP_FAILED) { | ||
133 | goto fail_rx; | ||
134 | } | ||
135 | -#endif | ||
136 | |||
137 | close(fd); | ||
138 | region.start_aligned = buf_rw; | ||
139 | -- | ||
140 | 2.25.1 | ||
141 | |||
142 | diff view generated by jsdifflib |