target/riscv/cpu_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
From: Frank Chang <frank.chang@sifive.com>
When virtual registers are swapped, mstatus.SD bit should also be
backed up/restored. Otherwise, mstatus.SD bit will be incorrectly kept
across the world switches.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Vincent Chen <vincent.chen@sifive.com>
---
target/riscv/cpu_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 968cb8046f4..488867b59eb 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -111,9 +111,10 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
{
+ target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
- MSTATUS64_UXL;
+ MSTATUS64_UXL | sd;
bool current_virt = riscv_cpu_virt_enabled(env);
g_assert(riscv_has_ext(env, RVH));
--
2.25.1
On Tue, Sep 14, 2021 at 11:37 AM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > When virtual registers are swapped, mstatus.SD bit should also be > backed up/restored. Otherwise, mstatus.SD bit will be incorrectly kept > across the world switches. > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_helper.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 968cb8046f4..488867b59eb 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -111,9 +111,10 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) > > void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) > { > + target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD; > uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | > MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | > - MSTATUS64_UXL; > + MSTATUS64_UXL | sd; > bool current_virt = riscv_cpu_virt_enabled(env); > > g_assert(riscv_has_ext(env, RVH)); > -- > 2.25.1 > >
On Tue, Sep 14, 2021 at 11:37 AM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > When virtual registers are swapped, mstatus.SD bit should also be > backed up/restored. Otherwise, mstatus.SD bit will be incorrectly kept > across the world switches. > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Vincent Chen <vincent.chen@sifive.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu_helper.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 968cb8046f4..488867b59eb 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -111,9 +111,10 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) > > void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) > { > + target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD; > uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | > MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | > - MSTATUS64_UXL; > + MSTATUS64_UXL | sd; > bool current_virt = riscv_cpu_virt_enabled(env); > > g_assert(riscv_has_ext(env, RVH)); > -- > 2.25.1 > >
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