[PULL 0/9] tcg patch queue
[PULL 00/24] tcg patch queue
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Note that I've extended the expiration date of my gpg key
1
The following changes since commit 6587b0c1331d427b0939c37e763842550ed581db:
2
and have uploaded it to keyserver.ubuntu.com.
3
2
4
3
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-10-15' into staging (2021-10-15 14:16:28 -0700)
5
r~
6
7
8
The following changes since commit 99c44988d5ba1866a411450c877ed818b1b70081:
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10
Merge remote-tracking branch 'remotes/bsdimp/tags/pull-bsd-user-20210910' into staging (2021-09-11 14:00:39 +0100)
11
4
12
are available in the Git repository at:
5
are available in the Git repository at:
13
6
14
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210912
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211016
15
8
16
for you to fetch changes up to 267a3ec3e2a8fb3e06a9d46d09fcfc57dfefd118:
9
for you to fetch changes up to 995b87dedc78b0467f5f18bbc3546072ba97516a:
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10
18
tcg/arm: Fix tcg_out_vec_op function signature (2021-09-12 05:07:36 -0700)
11
Revert "cpu: Move cpu_common_props to hw/core/cpu.c" (2021-10-15 16:39:15 -0700)
19
12
20
----------------------------------------------------------------
13
----------------------------------------------------------------
21
Fix translation race condition for user-only.
14
Move gdb singlestep to generic code
22
Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ.
15
Fix cpu_common_props
23
Fix tcg/arm tcg_out_vec_op signature.
24
Fix tcg/ppc (32bit) build with clang.
25
Remove dupluate TCG_KICK_PERIOD definition.
26
Remove unused tcg_global_reg_new.
27
Use __builtin_bswap*.
28
16
29
----------------------------------------------------------------
17
----------------------------------------------------------------
30
Bin Meng (1):
18
Richard Henderson (24):
31
tcg: Remove tcg_global_reg_new defines
19
accel/tcg: Handle gdb singlestep in cpu_tb_exec
20
target/alpha: Drop checks for singlestep_enabled
21
target/avr: Drop checks for singlestep_enabled
22
target/cris: Drop checks for singlestep_enabled
23
target/hexagon: Drop checks for singlestep_enabled
24
target/arm: Drop checks for singlestep_enabled
25
target/hppa: Drop checks for singlestep_enabled
26
target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt
27
target/i386: Drop check for singlestep_enabled
28
target/m68k: Drop checks for singlestep_enabled
29
target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP
30
target/microblaze: Drop checks for singlestep_enabled
31
target/mips: Fix single stepping
32
target/mips: Drop exit checks for singlestep_enabled
33
target/openrisc: Drop checks for singlestep_enabled
34
target/ppc: Drop exit checks for singlestep_enabled
35
target/riscv: Remove dead code after exception
36
target/riscv: Remove exit_tb and lookup_and_goto_ptr
37
target/rx: Drop checks for singlestep_enabled
38
target/s390x: Drop check for singlestep_enabled
39
target/sh4: Drop check for singlestep_enabled
40
target/tricore: Drop check for singlestep_enabled
41
target/xtensa: Drop check for singlestep_enabled
42
Revert "cpu: Move cpu_common_props to hw/core/cpu.c"
32
43
33
Ilya Leoshkevich (2):
44
include/hw/core/cpu.h | 1 +
34
accel/tcg: Add DisasContextBase argument to translator_ld*
45
target/i386/helper.h | 1 -
35
accel/tcg: Clear PAGE_WRITE before translation
46
target/rx/helper.h | 1 -
47
target/sh4/helper.h | 1 -
48
target/tricore/helper.h | 1 -
49
accel/tcg/cpu-exec.c | 11 ++++
50
cpu.c | 21 ++++++++
51
hw/core/cpu-common.c | 17 +-----
52
target/alpha/translate.c | 13 ++---
53
target/arm/translate-a64.c | 10 +---
54
target/arm/translate.c | 36 +++----------
55
target/avr/translate.c | 19 ++-----
56
target/cris/translate.c | 16 ------
57
target/hexagon/translate.c | 12 +----
58
target/hppa/translate.c | 17 ++----
59
target/i386/tcg/misc_helper.c | 8 ---
60
target/i386/tcg/translate.c | 9 ++--
61
target/m68k/translate.c | 44 ++++-----------
62
target/microblaze/translate.c | 18 ++-----
63
target/mips/tcg/translate.c | 75 ++++++++++++--------------
64
target/openrisc/translate.c | 18 ++-----
65
target/ppc/translate.c | 38 +++----------
66
target/riscv/translate.c | 27 +---------
67
target/rx/op_helper.c | 8 ---
68
target/rx/translate.c | 12 +----
69
target/s390x/tcg/translate.c | 8 +--
70
target/sh4/op_helper.c | 5 --
71
target/sh4/translate.c | 14 ++---
72
target/tricore/op_helper.c | 7 ---
73
target/tricore/translate.c | 14 +----
74
target/xtensa/translate.c | 25 +++------
75
target/riscv/insn_trans/trans_privileged.c.inc | 10 ++--
76
target/riscv/insn_trans/trans_rvi.c.inc | 8 ++-
77
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
78
34 files changed, 141 insertions(+), 386 deletions(-)
36
79
37
Jose R. Ziviani (1):
38
tcg/arm: Fix tcg_out_vec_op function signature
39
40
Luc Michel (1):
41
accel/tcg: remove redundant TCG_KICK_PERIOD define
42
43
Richard Henderson (4):
44
tcg/i386: Split P_VEXW from P_REXW
45
include/qemu: Use builtins for bswap
46
tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN
47
tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF
48
49
meson.build | 6 ----
50
include/exec/translate-all.h | 1 +
51
include/exec/translator.h | 44 +++++++++++++----------
52
include/qemu/bswap.h | 53 ++-------------------------
53
include/tcg/tcg-op.h | 2 --
54
target/arm/arm_ldst.h | 12 +++----
55
accel/tcg/tcg-accel-ops-rr.c | 2 --
56
accel/tcg/translate-all.c | 59 ++++++++++++++++++-------------
57
accel/tcg/translator.c | 39 ++++++++++++++++++++
58
target/alpha/translate.c | 2 +-
59
target/arm/translate-a64.c | 2 +-
60
target/arm/translate.c | 9 ++---
61
target/hexagon/translate.c | 3 +-
62
target/hppa/translate.c | 5 +--
63
target/i386/tcg/translate.c | 10 +++---
64
target/m68k/translate.c | 2 +-
65
target/mips/tcg/translate.c | 8 ++---
66
target/openrisc/translate.c | 2 +-
67
target/ppc/translate.c | 5 +--
68
target/riscv/translate.c | 5 +--
69
target/s390x/tcg/translate.c | 16 +++++----
70
target/sh4/translate.c | 4 +--
71
target/sparc/translate.c | 2 +-
72
target/xtensa/translate.c | 5 +--
73
target/mips/tcg/micromips_translate.c.inc | 2 +-
74
target/mips/tcg/mips16e_translate.c.inc | 4 +--
75
target/mips/tcg/nanomips_translate.c.inc | 4 +--
76
tcg/arm/tcg-target.c.inc | 3 +-
77
tcg/i386/tcg-target.c.inc | 13 +++----
78
tcg/ppc/tcg-target.c.inc | 25 ++++++++++---
79
30 files changed, 185 insertions(+), 164 deletions(-)
80
diff view generated by jsdifflib
New patch
[PULL 01/24] accel/tcg: Handle gdb singlestep in cpu_tb_exec
1
Currently the change in cpu_tb_exec is masked by the debug exception
2
being raised by the translators. But this allows us to remove that code.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
accel/tcg/cpu-exec.c | 11 +++++++++++
7
1 file changed, 11 insertions(+)
8
9
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/accel/tcg/cpu-exec.c
12
+++ b/accel/tcg/cpu-exec.c
13
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
14
cc->set_pc(cpu, last_tb->pc);
15
}
16
}
17
+
18
+ /*
19
+ * If gdb single-step, and we haven't raised another exception,
20
+ * raise a debug exception. Single-step with another exception
21
+ * is handled in cpu_handle_exception.
22
+ */
23
+ if (unlikely(cpu->singlestep_enabled) && cpu->exception_index == -1) {
24
+ cpu->exception_index = EXCP_DEBUG;
25
+ cpu_loop_exit(cpu);
26
+ }
27
+
28
return last_tb;
29
}
30
31
--
32
2.25.1
33
34
diff view generated by jsdifflib
New patch
[PULL 02/24] target/alpha: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/alpha/translate.c | 13 +++----------
7
1 file changed, 3 insertions(+), 10 deletions(-)
8
9
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/alpha/translate.c
12
+++ b/target/alpha/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
14
tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);
15
/* FALLTHRU */
16
case DISAS_PC_UPDATED:
17
- if (!ctx->base.singlestep_enabled) {
18
- tcg_gen_lookup_and_goto_ptr();
19
- break;
20
- }
21
- /* FALLTHRU */
22
+ tcg_gen_lookup_and_goto_ptr();
23
+ break;
24
case DISAS_PC_UPDATED_NOCHAIN:
25
- if (ctx->base.singlestep_enabled) {
26
- gen_excp_1(EXCP_DEBUG, 0);
27
- } else {
28
- tcg_gen_exit_tb(NULL, 0);
29
- }
30
+ tcg_gen_exit_tb(NULL, 0);
31
break;
32
default:
33
g_assert_not_reached();
34
--
35
2.25.1
36
37
diff view generated by jsdifflib
New patch
[PULL 03/24] target/avr: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Tested-by: Michael Rolnik <mrolnik@gmail.com>
4
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
target/avr/translate.c | 19 ++++---------------
9
1 file changed, 4 insertions(+), 15 deletions(-)
10
11
diff --git a/target/avr/translate.c b/target/avr/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/avr/translate.c
14
+++ b/target/avr/translate.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
16
tcg_gen_exit_tb(tb, n);
17
} else {
18
tcg_gen_movi_i32(cpu_pc, dest);
19
- if (ctx->base.singlestep_enabled) {
20
- gen_helper_debug(cpu_env);
21
- } else {
22
- tcg_gen_lookup_and_goto_ptr();
23
- }
24
+ tcg_gen_lookup_and_goto_ptr();
25
}
26
ctx->base.is_jmp = DISAS_NORETURN;
27
}
28
@@ -XXX,XX +XXX,XX @@ static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
29
tcg_gen_movi_tl(cpu_pc, ctx->npc);
30
/* fall through */
31
case DISAS_LOOKUP:
32
- if (!ctx->base.singlestep_enabled) {
33
- tcg_gen_lookup_and_goto_ptr();
34
- break;
35
- }
36
- /* fall through */
37
+ tcg_gen_lookup_and_goto_ptr();
38
+ break;
39
case DISAS_EXIT:
40
- if (ctx->base.singlestep_enabled) {
41
- gen_helper_debug(cpu_env);
42
- } else {
43
- tcg_gen_exit_tb(NULL, 0);
44
- }
45
+ tcg_gen_exit_tb(NULL, 0);
46
break;
47
default:
48
g_assert_not_reached();
49
--
50
2.25.1
51
52
diff view generated by jsdifflib
New patch
[PULL 04/24] target/cris: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/cris/translate.c | 16 ----------------
6
1 file changed, 16 deletions(-)
7
8
diff --git a/target/cris/translate.c b/target/cris/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/target/cris/translate.c
11
+++ b/target/cris/translate.c
12
@@ -XXX,XX +XXX,XX @@ static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
13
}
14
}
15
16
- if (unlikely(dc->base.singlestep_enabled)) {
17
- switch (is_jmp) {
18
- case DISAS_TOO_MANY:
19
- case DISAS_UPDATE_NEXT:
20
- tcg_gen_movi_tl(env_pc, npc);
21
- /* fall through */
22
- case DISAS_JUMP:
23
- case DISAS_UPDATE:
24
- t_gen_raise_exception(EXCP_DEBUG);
25
- return;
26
- default:
27
- break;
28
- }
29
- g_assert_not_reached();
30
- }
31
-
32
switch (is_jmp) {
33
case DISAS_TOO_MANY:
34
gen_goto_tb(dc, 0, npc);
35
--
36
2.25.1
37
38
diff view generated by jsdifflib
New patch
[PULL 05/24] target/hexagon: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/hexagon/translate.c | 12 ++----------
7
1 file changed, 2 insertions(+), 10 deletions(-)
8
9
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/hexagon/translate.c
12
+++ b/target/hexagon/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void gen_end_tb(DisasContext *ctx)
14
{
15
gen_exec_counters(ctx);
16
tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
17
- if (ctx->base.singlestep_enabled) {
18
- gen_exception_raw(EXCP_DEBUG);
19
- } else {
20
- tcg_gen_exit_tb(NULL, 0);
21
- }
22
+ tcg_gen_exit_tb(NULL, 0);
23
ctx->base.is_jmp = DISAS_NORETURN;
24
}
25
26
@@ -XXX,XX +XXX,XX @@ static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
27
case DISAS_TOO_MANY:
28
gen_exec_counters(ctx);
29
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
30
- if (ctx->base.singlestep_enabled) {
31
- gen_exception_raw(EXCP_DEBUG);
32
- } else {
33
- tcg_gen_exit_tb(NULL, 0);
34
- }
35
+ tcg_gen_exit_tb(NULL, 0);
36
break;
37
case DISAS_NORETURN:
38
break;
39
--
40
2.25.1
41
42
diff view generated by jsdifflib
[PULL 1/9] accel/tcg: Add DisasContextBase argument to translator_ld*
[PULL 06/24] target/arm: Drop checks for singlestep_enabled
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
1
GDB single-stepping is now handled generically.
2
2
3
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
4
[rth: Split out of a larger patch.]
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
4
---
7
include/exec/translator.h | 9 +++++----
5
target/arm/translate-a64.c | 10 ++--------
8
target/arm/arm_ldst.h | 12 ++++++------
6
target/arm/translate.c | 36 ++++++------------------------------
9
target/alpha/translate.c | 2 +-
7
2 files changed, 8 insertions(+), 38 deletions(-)
10
target/arm/translate-a64.c | 2 +-
11
target/arm/translate.c | 9 +++++----
12
target/hexagon/translate.c | 3 ++-
13
target/hppa/translate.c | 2 +-
14
target/i386/tcg/translate.c | 10 +++++-----
15
target/m68k/translate.c | 2 +-
16
target/mips/tcg/translate.c | 8 ++++----
17
target/openrisc/translate.c | 2 +-
18
target/ppc/translate.c | 5 +++--
19
target/riscv/translate.c | 5 +++--
20
target/s390x/tcg/translate.c | 16 +++++++++-------
21
target/sh4/translate.c | 4 ++--
22
target/sparc/translate.c | 2 +-
23
target/xtensa/translate.c | 5 +++--
24
target/mips/tcg/micromips_translate.c.inc | 2 +-
25
target/mips/tcg/mips16e_translate.c.inc | 4 ++--
26
target/mips/tcg/nanomips_translate.c.inc | 4 ++--
27
20 files changed, 58 insertions(+), 50 deletions(-)
28
8
29
diff --git a/include/exec/translator.h b/include/exec/translator.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/include/exec/translator.h
32
+++ b/include/exec/translator.h
33
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
34
35
#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
36
static inline type \
37
- fullname ## _swap(CPUArchState *env, abi_ptr pc, bool do_swap) \
38
+ fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
39
+ abi_ptr pc, bool do_swap) \
40
{ \
41
type ret = load_fn(env, pc); \
42
if (do_swap) { \
43
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
44
plugin_insn_append(&ret, sizeof(ret)); \
45
return ret; \
46
} \
47
- \
48
- static inline type fullname(CPUArchState *env, abi_ptr pc) \
49
+ static inline type fullname(CPUArchState *env, \
50
+ DisasContextBase *dcbase, abi_ptr pc) \
51
{ \
52
- return fullname ## _swap(env, pc, false); \
53
+ return fullname ## _swap(env, dcbase, pc, false); \
54
}
55
56
GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */)
57
diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/arm_ldst.h
60
+++ b/target/arm/arm_ldst.h
61
@@ -XXX,XX +XXX,XX @@
62
#include "qemu/bswap.h"
63
64
/* Load an instruction and return it in the standard little-endian order */
65
-static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
66
- bool sctlr_b)
67
+static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s,
68
+ target_ulong addr, bool sctlr_b)
69
{
70
- return translator_ldl_swap(env, addr, bswap_code(sctlr_b));
71
+ return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b));
72
}
73
74
/* Ditto, for a halfword (Thumb) instruction */
75
-static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
76
- bool sctlr_b)
77
+static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s,
78
+ target_ulong addr, bool sctlr_b)
79
{
80
#ifndef CONFIG_USER_ONLY
81
/* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped
82
@@ -XXX,XX +XXX,XX @@ static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
83
addr ^= 2;
84
}
85
#endif
86
- return translator_lduw_swap(env, addr, bswap_code(sctlr_b));
87
+ return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b));
88
}
89
90
#endif
91
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/target/alpha/translate.c
94
+++ b/target/alpha/translate.c
95
@@ -XXX,XX +XXX,XX @@ static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
96
{
97
DisasContext *ctx = container_of(dcbase, DisasContext, base);
98
CPUAlphaState *env = cpu->env_ptr;
99
- uint32_t insn = translator_ldl(env, ctx->base.pc_next);
100
+ uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
101
102
ctx->base.pc_next += 4;
103
ctx->base.is_jmp = translate_one(ctx, insn);
104
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
9
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
105
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
106
--- a/target/arm/translate-a64.c
11
--- a/target/arm/translate-a64.c
107
+++ b/target/arm/translate-a64.c
12
+++ b/target/arm/translate-a64.c
108
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
13
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
109
uint32_t insn;
14
gen_a64_set_pc_im(dest);
110
15
if (s->ss_active) {
111
s->pc_curr = s->base.pc_next;
16
gen_step_complete_exception(s);
112
- insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b);
17
- } else if (s->base.singlestep_enabled) {
113
+ insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b);
18
- gen_exception_internal(EXCP_DEBUG);
114
s->insn = insn;
19
} else {
115
s->base.pc_next += 4;
20
tcg_gen_lookup_and_goto_ptr();
116
21
s->base.is_jmp = DISAS_NORETURN;
22
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
23
{
24
DisasContext *dc = container_of(dcbase, DisasContext, base);
25
26
- if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) {
27
+ if (unlikely(dc->ss_active)) {
28
/* Note that this means single stepping WFI doesn't halt the CPU.
29
* For conditional branch insns this is harmless unreachable code as
30
* gen_goto_tb() has already handled emitting the debug exception
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
32
/* fall through */
33
case DISAS_EXIT:
34
case DISAS_JUMP:
35
- if (dc->base.singlestep_enabled) {
36
- gen_exception_internal(EXCP_DEBUG);
37
- } else {
38
- gen_step_complete_exception(dc);
39
- }
40
+ gen_step_complete_exception(dc);
41
break;
42
case DISAS_NORETURN:
43
break;
117
diff --git a/target/arm/translate.c b/target/arm/translate.c
44
diff --git a/target/arm/translate.c b/target/arm/translate.c
118
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
119
--- a/target/arm/translate.c
46
--- a/target/arm/translate.c
120
+++ b/target/arm/translate.c
47
+++ b/target/arm/translate.c
121
@@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
48
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
122
* boundary, so we cross the page if the first 16 bits indicate
49
tcg_temp_free_i32(tcg_excp);
123
* that this is a 32 bit insn.
124
*/
125
- uint16_t insn = arm_lduw_code(env, s->base.pc_next, s->sctlr_b);
126
+ uint16_t insn = arm_lduw_code(env, &s->base, s->base.pc_next, s->sctlr_b);
127
128
return !thumb_insn_is_16bit(s, s->base.pc_next, insn);
129
}
50
}
130
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
51
52
-static void gen_step_complete_exception(DisasContext *s)
53
+static void gen_singlestep_exception(DisasContext *s)
54
{
55
/* We just completed step of an insn. Move from Active-not-pending
56
* to Active-pending, and then also take the swstep exception.
57
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
58
s->base.is_jmp = DISAS_NORETURN;
59
}
60
61
-static void gen_singlestep_exception(DisasContext *s)
62
-{
63
- /* Generate the right kind of exception for singlestep, which is
64
- * either the architectural singlestep or EXCP_DEBUG for QEMU's
65
- * gdb singlestepping.
66
- */
67
- if (s->ss_active) {
68
- gen_step_complete_exception(s);
69
- } else {
70
- gen_exception_internal(EXCP_DEBUG);
71
- }
72
-}
73
-
74
-static inline bool is_singlestepping(DisasContext *s)
75
-{
76
- /* Return true if we are singlestepping either because of
77
- * architectural singlestep or QEMU gdbstub singlestep. This does
78
- * not include the command line '-singlestep' mode which is rather
79
- * misnamed as it only means "one instruction per TB" and doesn't
80
- * affect the code we generate.
81
- */
82
- return s->base.singlestep_enabled || s->ss_active;
83
-}
84
-
85
void clear_eci_state(DisasContext *s)
86
{
87
/*
88
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)
89
/* Is the new PC value in the magic range indicating exception return? */
90
tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);
91
/* No: end the TB as we would for a DISAS_JMP */
92
- if (is_singlestepping(s)) {
93
+ if (s->ss_active) {
94
gen_singlestep_exception(s);
95
} else {
96
tcg_gen_exit_tb(NULL, 0);
97
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
98
/* Jump, specifying which TB number to use if we gen_goto_tb() */
99
static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
100
{
101
- if (unlikely(is_singlestepping(s))) {
102
+ if (unlikely(s->ss_active)) {
103
/* An indirect jump so that we still trigger the debug exception. */
104
gen_set_pc_im(s, dest);
105
s->base.is_jmp = DISAS_JUMP;
106
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
107
dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK;
108
109
/* If architectural single step active, limit to 1. */
110
- if (is_singlestepping(dc)) {
111
+ if (dc->ss_active) {
112
dc->base.max_insns = 1;
131
}
113
}
132
114
133
dc->pc_curr = dc->base.pc_next;
115
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
134
- insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b);
116
* insn codepath itself.
135
+ insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
117
*/
136
dc->insn = insn;
118
gen_bx_excret_final_code(dc);
137
dc->base.pc_next += 4;
119
- } else if (unlikely(is_singlestepping(dc))) {
138
disas_arm_insn(dc, insn);
120
+ } else if (unlikely(dc->ss_active)) {
139
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
121
/* Unconditional and "condition passed" instruction codepath. */
140
}
122
switch (dc->base.is_jmp) {
141
123
case DISAS_SWI:
142
dc->pc_curr = dc->base.pc_next;
124
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
143
- insn = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
125
/* "Condition failed" instruction codepath for the branch/trap insn */
144
+ insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
126
gen_set_label(dc->condlabel);
145
is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
127
gen_set_condexec(dc);
146
dc->base.pc_next += 2;
128
- if (unlikely(is_singlestepping(dc))) {
147
if (!is_16bit) {
129
+ if (unlikely(dc->ss_active)) {
148
- uint32_t insn2 = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
130
gen_set_pc_im(dc, dc->base.pc_next);
149
+ uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next,
131
gen_singlestep_exception(dc);
150
+ dc->sctlr_b);
132
} else {
151
152
insn = insn << 16 | insn2;
153
dc->base.pc_next += 2;
154
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
155
index XXXXXXX..XXXXXXX 100644
156
--- a/target/hexagon/translate.c
157
+++ b/target/hexagon/translate.c
158
@@ -XXX,XX +XXX,XX @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
159
memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t));
160
for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) {
161
words[nwords] =
162
- translator_ldl(env, ctx->base.pc_next + nwords * sizeof(uint32_t));
163
+ translator_ldl(env, &ctx->base,
164
+ ctx->base.pc_next + nwords * sizeof(uint32_t));
165
found_end = is_packet_end(words[nwords]);
166
}
167
if (!found_end) {
168
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
169
index XXXXXXX..XXXXXXX 100644
170
--- a/target/hppa/translate.c
171
+++ b/target/hppa/translate.c
172
@@ -XXX,XX +XXX,XX @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
173
{
174
/* Always fetch the insn, even if nullified, so that we check
175
the page permissions for execute. */
176
- uint32_t insn = translator_ldl(env, ctx->base.pc_next);
177
+ uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
178
179
/* Set up the IA queue for the next insn.
180
This will be overwritten by a branch. */
181
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
182
index XXXXXXX..XXXXXXX 100644
183
--- a/target/i386/tcg/translate.c
184
+++ b/target/i386/tcg/translate.c
185
@@ -XXX,XX +XXX,XX @@ static uint64_t advance_pc(CPUX86State *env, DisasContext *s, int num_bytes)
186
187
static inline uint8_t x86_ldub_code(CPUX86State *env, DisasContext *s)
188
{
189
- return translator_ldub(env, advance_pc(env, s, 1));
190
+ return translator_ldub(env, &s->base, advance_pc(env, s, 1));
191
}
192
193
static inline int16_t x86_ldsw_code(CPUX86State *env, DisasContext *s)
194
{
195
- return translator_ldsw(env, advance_pc(env, s, 2));
196
+ return translator_ldsw(env, &s->base, advance_pc(env, s, 2));
197
}
198
199
static inline uint16_t x86_lduw_code(CPUX86State *env, DisasContext *s)
200
{
201
- return translator_lduw(env, advance_pc(env, s, 2));
202
+ return translator_lduw(env, &s->base, advance_pc(env, s, 2));
203
}
204
205
static inline uint32_t x86_ldl_code(CPUX86State *env, DisasContext *s)
206
{
207
- return translator_ldl(env, advance_pc(env, s, 4));
208
+ return translator_ldl(env, &s->base, advance_pc(env, s, 4));
209
}
210
211
#ifdef TARGET_X86_64
212
static inline uint64_t x86_ldq_code(CPUX86State *env, DisasContext *s)
213
{
214
- return translator_ldq(env, advance_pc(env, s, 8));
215
+ return translator_ldq(env, &s->base, advance_pc(env, s, 8));
216
}
217
#endif
218
219
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
220
index XXXXXXX..XXXXXXX 100644
221
--- a/target/m68k/translate.c
222
+++ b/target/m68k/translate.c
223
@@ -XXX,XX +XXX,XX @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
224
static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
225
{
226
uint16_t im;
227
- im = translator_lduw(env, s->pc);
228
+ im = translator_lduw(env, &s->base, s->pc);
229
s->pc += 2;
230
return im;
231
}
232
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
233
index XXXXXXX..XXXXXXX 100644
234
--- a/target/mips/tcg/translate.c
235
+++ b/target/mips/tcg/translate.c
236
@@ -XXX,XX +XXX,XX @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
237
238
is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
239
if (ctx->insn_flags & ISA_NANOMIPS32) {
240
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
241
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
242
insn_bytes = decode_isa_nanomips(env, ctx);
243
} else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
244
- ctx->opcode = translator_ldl(env, ctx->base.pc_next);
245
+ ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
246
insn_bytes = 4;
247
decode_opc(env, ctx);
248
} else if (ctx->insn_flags & ASE_MICROMIPS) {
249
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
250
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
251
insn_bytes = decode_isa_micromips(env, ctx);
252
} else if (ctx->insn_flags & ASE_MIPS16) {
253
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
254
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
255
insn_bytes = decode_ase_mips16e(env, ctx);
256
} else {
257
gen_reserved_instruction(ctx);
258
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
259
index XXXXXXX..XXXXXXX 100644
260
--- a/target/openrisc/translate.c
261
+++ b/target/openrisc/translate.c
262
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
263
{
264
DisasContext *dc = container_of(dcbase, DisasContext, base);
265
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
266
- uint32_t insn = translator_ldl(&cpu->env, dc->base.pc_next);
267
+ uint32_t insn = translator_ldl(&cpu->env, &dc->base, dc->base.pc_next);
268
269
if (!decode(dc, insn)) {
270
gen_illegal_exception(dc);
271
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
272
index XXXXXXX..XXXXXXX 100644
273
--- a/target/ppc/translate.c
274
+++ b/target/ppc/translate.c
275
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
276
ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
277
278
ctx->cia = pc = ctx->base.pc_next;
279
- insn = translator_ldl_swap(env, pc, need_byteswap(ctx));
280
+ insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
281
ctx->base.pc_next = pc += 4;
282
283
if (!is_prefix_insn(ctx, insn)) {
284
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
285
gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
286
ok = true;
287
} else {
288
- uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx));
289
+ uint32_t insn2 = translator_ldl_swap(env, dcbase, pc,
290
+ need_byteswap(ctx));
291
ctx->base.pc_next = pc += 4;
292
ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
293
}
294
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
295
index XXXXXXX..XXXXXXX 100644
296
--- a/target/riscv/translate.c
297
+++ b/target/riscv/translate.c
298
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
299
} else {
300
uint32_t opcode32 = opcode;
301
opcode32 = deposit32(opcode32, 16, 16,
302
- translator_lduw(env, ctx->base.pc_next + 2));
303
+ translator_lduw(env, &ctx->base,
304
+ ctx->base.pc_next + 2));
305
ctx->pc_succ_insn = ctx->base.pc_next + 4;
306
if (!decode_insn32(ctx, opcode32)) {
307
gen_exception_illegal(ctx);
308
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
309
{
310
DisasContext *ctx = container_of(dcbase, DisasContext, base);
311
CPURISCVState *env = cpu->env_ptr;
312
- uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next);
313
+ uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
314
315
decode_opc(env, ctx, opcode16);
316
ctx->base.pc_next = ctx->pc_succ_insn;
317
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
318
index XXXXXXX..XXXXXXX 100644
319
--- a/target/s390x/tcg/translate.c
320
+++ b/target/s390x/tcg/translate.c
321
@@ -XXX,XX +XXX,XX @@ static void update_cc_op(DisasContext *s)
322
}
323
}
324
325
-static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
326
+static inline uint64_t ld_code2(CPUS390XState *env, DisasContext *s,
327
+ uint64_t pc)
328
{
329
- return (uint64_t)cpu_lduw_code(env, pc);
330
+ return (uint64_t)translator_lduw(env, &s->base, pc);
331
}
332
333
-static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
334
+static inline uint64_t ld_code4(CPUS390XState *env, DisasContext *s,
335
+ uint64_t pc)
336
{
337
- return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
338
+ return (uint64_t)(uint32_t)translator_ldl(env, &s->base, pc);
339
}
340
341
static int get_mem_index(DisasContext *s)
342
@@ -XXX,XX +XXX,XX @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
343
ilen = s->ex_value & 0xf;
344
op = insn >> 56;
345
} else {
346
- insn = ld_code2(env, pc);
347
+ insn = ld_code2(env, s, pc);
348
op = (insn >> 8) & 0xff;
349
ilen = get_ilen(op);
350
switch (ilen) {
351
@@ -XXX,XX +XXX,XX @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
352
insn = insn << 48;
353
break;
354
case 4:
355
- insn = ld_code4(env, pc) << 32;
356
+ insn = ld_code4(env, s, pc) << 32;
357
break;
358
case 6:
359
- insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
360
+ insn = (insn << 48) | (ld_code4(env, s, pc + 2) << 16);
361
break;
362
default:
363
g_assert_not_reached();
364
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
365
index XXXXXXX..XXXXXXX 100644
366
--- a/target/sh4/translate.c
367
+++ b/target/sh4/translate.c
368
@@ -XXX,XX +XXX,XX @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
369
370
/* Read all of the insns for the region. */
371
for (i = 0; i < max_insns; ++i) {
372
- insns[i] = translator_lduw(env, pc + i * 2);
373
+ insns[i] = translator_lduw(env, &ctx->base, pc + i * 2);
374
}
375
376
ld_adr = ld_dst = ld_mop = -1;
377
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
378
}
379
#endif
380
381
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
382
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
383
decode_opc(ctx);
384
ctx->base.pc_next += 2;
385
}
386
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
387
index XXXXXXX..XXXXXXX 100644
388
--- a/target/sparc/translate.c
389
+++ b/target/sparc/translate.c
390
@@ -XXX,XX +XXX,XX @@ static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
391
CPUSPARCState *env = cs->env_ptr;
392
unsigned int insn;
393
394
- insn = translator_ldl(env, dc->pc);
395
+ insn = translator_ldl(env, &dc->base, dc->pc);
396
dc->base.pc_next += 4;
397
disas_sparc_insn(dc, insn);
398
399
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
400
index XXXXXXX..XXXXXXX 100644
401
--- a/target/xtensa/translate.c
402
+++ b/target/xtensa/translate.c
403
@@ -XXX,XX +XXX,XX @@ static int arg_copy_compare(const void *a, const void *b)
404
static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
405
{
406
xtensa_isa isa = dc->config->isa;
407
- unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, dc->pc)};
408
+ unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, &dc->base,
409
+ dc->pc)};
410
unsigned len = xtensa_op0_insn_len(dc, b[0]);
411
xtensa_format fmt;
412
int slot, slots;
413
@@ -XXX,XX +XXX,XX @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
414
415
dc->base.pc_next = dc->pc + len;
416
for (i = 1; i < len; ++i) {
417
- b[i] = translator_ldub(env, dc->pc + i);
418
+ b[i] = translator_ldub(env, &dc->base, dc->pc + i);
419
}
420
xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len);
421
fmt = xtensa_format_decode(isa, dc->insnbuf);
422
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
423
index XXXXXXX..XXXXXXX 100644
424
--- a/target/mips/tcg/micromips_translate.c.inc
425
+++ b/target/mips/tcg/micromips_translate.c.inc
426
@@ -XXX,XX +XXX,XX @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
427
uint32_t op, minor, minor2, mips32_op;
428
uint32_t cond, fmt, cc;
429
430
- insn = translator_lduw(env, ctx->base.pc_next + 2);
431
+ insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
432
ctx->opcode = (ctx->opcode << 16) | insn;
433
434
rt = (ctx->opcode >> 21) & 0x1f;
435
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
436
index XXXXXXX..XXXXXXX 100644
437
--- a/target/mips/tcg/mips16e_translate.c.inc
438
+++ b/target/mips/tcg/mips16e_translate.c.inc
439
@@ -XXX,XX +XXX,XX @@ static void decode_i64_mips16(DisasContext *ctx,
440
441
static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
442
{
443
- int extend = translator_lduw(env, ctx->base.pc_next + 2);
444
+ int extend = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
445
int op, rx, ry, funct, sa;
446
int16_t imm, offset;
447
448
@@ -XXX,XX +XXX,XX @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
449
/* No delay slot, so just process as a normal instruction */
450
break;
451
case M16_OPC_JAL:
452
- offset = translator_lduw(env, ctx->base.pc_next + 2);
453
+ offset = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
454
offset = (((ctx->opcode & 0x1f) << 21)
455
| ((ctx->opcode >> 5) & 0x1f) << 16
456
| offset) << 2;
457
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
458
index XXXXXXX..XXXXXXX 100644
459
--- a/target/mips/tcg/nanomips_translate.c.inc
460
+++ b/target/mips/tcg/nanomips_translate.c.inc
461
@@ -XXX,XX +XXX,XX @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
462
int offset;
463
int imm;
464
465
- insn = translator_lduw(env, ctx->base.pc_next + 2);
466
+ insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
467
ctx->opcode = (ctx->opcode << 16) | insn;
468
469
rt = extract32(ctx->opcode, 21, 5);
470
@@ -XXX,XX +XXX,XX @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
471
break;
472
case NM_P48I:
473
{
474
- insn = translator_lduw(env, ctx->base.pc_next + 4);
475
+ insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4);
476
target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;
477
switch (extract32(ctx->opcode, 16, 5)) {
478
case NM_LI48:
479
--
133
--
480
2.25.1
134
2.25.1
481
135
482
136
diff view generated by jsdifflib
[PULL 5/9] tcg: Remove tcg_global_reg_new defines
[PULL 07/24] target/hppa: Drop checks for singlestep_enabled
1
From: Bin Meng <bmeng.cn@gmail.com>
1
GDB single-stepping is now handled generically.
2
2
3
Since commit 1c2adb958fc0 ("tcg: Initialize cpu_env generically"),
4
these tcg_global_reg_new_ macros are not used anywhere.
5
6
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-Id: <20210816143507.11200-1-bmeng.cn@gmail.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
5
---
11
include/tcg/tcg-op.h | 2 --
6
target/hppa/translate.c | 17 ++++-------------
12
target/hppa/translate.c | 3 ---
7
1 file changed, 4 insertions(+), 13 deletions(-)
13
2 files changed, 5 deletions(-)
14
8
15
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/tcg/tcg-op.h
18
+++ b/include/tcg/tcg-op.h
19
@@ -XXX,XX +XXX,XX @@ static inline void tcg_gen_plugin_cb_end(void)
20
21
#if TARGET_LONG_BITS == 32
22
#define tcg_temp_new() tcg_temp_new_i32()
23
-#define tcg_global_reg_new tcg_global_reg_new_i32
24
#define tcg_global_mem_new tcg_global_mem_new_i32
25
#define tcg_temp_local_new() tcg_temp_local_new_i32()
26
#define tcg_temp_free tcg_temp_free_i32
27
@@ -XXX,XX +XXX,XX @@ static inline void tcg_gen_plugin_cb_end(void)
28
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
29
#else
30
#define tcg_temp_new() tcg_temp_new_i64()
31
-#define tcg_global_reg_new tcg_global_reg_new_i64
32
#define tcg_global_mem_new tcg_global_mem_new_i64
33
#define tcg_temp_local_new() tcg_temp_local_new_i64()
34
#define tcg_temp_free tcg_temp_free_i64
35
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
9
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
36
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
37
--- a/target/hppa/translate.c
11
--- a/target/hppa/translate.c
38
+++ b/target/hppa/translate.c
12
+++ b/target/hppa/translate.c
39
@@ -XXX,XX +XXX,XX @@
13
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int which,
40
14
} else {
41
#undef TCGv
15
copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b);
42
#undef tcg_temp_new
16
copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var);
43
-#undef tcg_global_reg_new
17
- if (ctx->base.singlestep_enabled) {
44
#undef tcg_global_mem_new
18
- gen_excp_1(EXCP_DEBUG);
45
#undef tcg_temp_local_new
19
- } else {
46
#undef tcg_temp_free
20
- tcg_gen_lookup_and_goto_ptr();
47
@@ -XXX,XX +XXX,XX @@
21
- }
48
#define TCGv_reg TCGv_i64
22
+ tcg_gen_lookup_and_goto_ptr();
49
23
}
50
#define tcg_temp_new tcg_temp_new_i64
24
}
51
-#define tcg_global_reg_new tcg_global_reg_new_i64
25
52
#define tcg_global_mem_new tcg_global_mem_new_i64
26
@@ -XXX,XX +XXX,XX @@ static bool do_rfi(DisasContext *ctx, bool rfi_r)
53
#define tcg_temp_local_new tcg_temp_local_new_i64
27
gen_helper_rfi(cpu_env);
54
#define tcg_temp_free tcg_temp_free_i64
28
}
55
@@ -XXX,XX +XXX,XX @@
29
/* Exit the TB to recognize new interrupts. */
56
#else
30
- if (ctx->base.singlestep_enabled) {
57
#define TCGv_reg TCGv_i32
31
- gen_excp_1(EXCP_DEBUG);
58
#define tcg_temp_new tcg_temp_new_i32
32
- } else {
59
-#define tcg_global_reg_new tcg_global_reg_new_i32
33
- tcg_gen_exit_tb(NULL, 0);
60
#define tcg_global_mem_new tcg_global_mem_new_i32
34
- }
61
#define tcg_temp_local_new tcg_temp_local_new_i32
35
+ tcg_gen_exit_tb(NULL, 0);
62
#define tcg_temp_free tcg_temp_free_i32
36
ctx->base.is_jmp = DISAS_NORETURN;
37
38
return nullify_end(ctx);
39
@@ -XXX,XX +XXX,XX @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
40
nullify_save(ctx);
41
/* FALLTHRU */
42
case DISAS_IAQ_N_UPDATED:
43
- if (ctx->base.singlestep_enabled) {
44
- gen_excp_1(EXCP_DEBUG);
45
- } else if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
46
+ if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
47
tcg_gen_lookup_and_goto_ptr();
48
+ break;
49
}
50
/* FALLTHRU */
51
case DISAS_EXIT:
63
--
52
--
64
2.25.1
53
2.25.1
65
54
66
55
diff view generated by jsdifflib
New patch
[PULL 08/24] target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt
1
We were using singlestep_enabled as a proxy for whether
2
translator_use_goto_tb would always return false.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/i386/tcg/translate.c | 5 +++--
7
1 file changed, 3 insertions(+), 2 deletions(-)
8
9
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/i386/tcg/translate.c
12
+++ b/target/i386/tcg/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
14
DisasContext *dc = container_of(dcbase, DisasContext, base);
15
CPUX86State *env = cpu->env_ptr;
16
uint32_t flags = dc->base.tb->flags;
17
+ uint32_t cflags = tb_cflags(dc->base.tb);
18
int cpl = (flags >> HF_CPL_SHIFT) & 3;
19
int iopl = (flags >> IOPL_SHIFT) & 3;
20
21
@@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
22
dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
23
dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
24
dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
25
- dc->jmp_opt = !(dc->base.singlestep_enabled ||
26
+ dc->jmp_opt = !((cflags & CF_NO_GOTO_TB) ||
27
(flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)));
28
/*
29
* If jmp_opt, we want to handle each string instruction individually.
30
* For icount also disable repz optimization so that each iteration
31
* is accounted separately.
32
*/
33
- dc->repz_opt = !dc->jmp_opt && !(tb_cflags(dc->base.tb) & CF_USE_ICOUNT);
34
+ dc->repz_opt = !dc->jmp_opt && !(cflags & CF_USE_ICOUNT);
35
36
dc->T0 = tcg_temp_new();
37
dc->T1 = tcg_temp_new();
38
--
39
2.25.1
40
41
diff view generated by jsdifflib
New patch
[PULL 09/24] target/i386: Drop check for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/i386/helper.h | 1 -
6
target/i386/tcg/misc_helper.c | 8 --------
7
target/i386/tcg/translate.c | 4 +---
8
3 files changed, 1 insertion(+), 12 deletions(-)
9
10
diff --git a/target/i386/helper.h b/target/i386/helper.h
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/i386/helper.h
13
+++ b/target/i386/helper.h
14
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(syscall, void, env, int)
15
DEF_HELPER_2(sysret, void, env, int)
16
#endif
17
DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int)
18
-DEF_HELPER_FLAGS_1(debug, TCG_CALL_NO_WG, noreturn, env)
19
DEF_HELPER_1(reset_rf, void, env)
20
DEF_HELPER_FLAGS_3(raise_interrupt, TCG_CALL_NO_WG, noreturn, env, int, int)
21
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, int)
22
diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/i386/tcg/misc_helper.c
25
+++ b/target/i386/tcg/misc_helper.c
26
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend)
27
do_pause(env);
28
}
29
30
-void QEMU_NORETURN helper_debug(CPUX86State *env)
31
-{
32
- CPUState *cs = env_cpu(env);
33
-
34
- cs->exception_index = EXCP_DEBUG;
35
- cpu_loop_exit(cs);
36
-}
37
-
38
uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx)
39
{
40
if ((env->cr[4] & CR4_PKE_MASK) == 0) {
41
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/i386/tcg/translate.c
44
+++ b/target/i386/tcg/translate.c
45
@@ -XXX,XX +XXX,XX @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr)
46
if (s->base.tb->flags & HF_RF_MASK) {
47
gen_helper_reset_rf(cpu_env);
48
}
49
- if (s->base.singlestep_enabled) {
50
- gen_helper_debug(cpu_env);
51
- } else if (recheck_tf) {
52
+ if (recheck_tf) {
53
gen_helper_rechecking_single_step(cpu_env);
54
tcg_gen_exit_tb(NULL, 0);
55
} else if (s->flags & HF_TF_MASK) {
56
--
57
2.25.1
58
59
diff view generated by jsdifflib
New patch
[PULL 10/24] target/m68k: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Acked-by: Laurent Vivier <laurent@vivier.eu>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/m68k/translate.c | 44 +++++++++--------------------------------
7
1 file changed, 9 insertions(+), 35 deletions(-)
8
9
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/m68k/translate.c
12
+++ b/target/m68k/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void do_writebacks(DisasContext *s)
14
}
15
}
16
17
-static bool is_singlestepping(DisasContext *s)
18
-{
19
- /*
20
- * Return true if we are singlestepping either because of
21
- * architectural singlestep or QEMU gdbstub singlestep. This does
22
- * not include the command line '-singlestep' mode which is rather
23
- * misnamed as it only means "one instruction per TB" and doesn't
24
- * affect the code we generate.
25
- */
26
- return s->base.singlestep_enabled || s->ss_active;
27
-}
28
-
29
/* is_jmp field values */
30
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
31
#define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
32
@@ -XXX,XX +XXX,XX @@ static void gen_exception(DisasContext *s, uint32_t dest, int nr)
33
s->base.is_jmp = DISAS_NORETURN;
34
}
35
36
-static void gen_singlestep_exception(DisasContext *s)
37
-{
38
- /*
39
- * Generate the right kind of exception for singlestep, which is
40
- * either the architectural singlestep or EXCP_DEBUG for QEMU's
41
- * gdb singlestepping.
42
- */
43
- if (s->ss_active) {
44
- gen_raise_exception(EXCP_TRACE);
45
- } else {
46
- gen_raise_exception(EXCP_DEBUG);
47
- }
48
-}
49
-
50
static inline void gen_addr_fault(DisasContext *s)
51
{
52
gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
53
@@ -XXX,XX +XXX,XX @@ static void gen_exit_tb(DisasContext *s)
54
/* Generate a jump to an immediate address. */
55
static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
56
{
57
- if (unlikely(is_singlestepping(s))) {
58
+ if (unlikely(s->ss_active)) {
59
update_cc_op(s);
60
tcg_gen_movi_i32(QREG_PC, dest);
61
- gen_singlestep_exception(s);
62
+ gen_raise_exception(EXCP_TRACE);
63
} else if (translator_use_goto_tb(&s->base, dest)) {
64
tcg_gen_goto_tb(n);
65
tcg_gen_movi_i32(QREG_PC, dest);
66
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
67
68
dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS);
69
/* If architectural single step active, limit to 1 */
70
- if (is_singlestepping(dc)) {
71
+ if (dc->ss_active) {
72
dc->base.max_insns = 1;
73
}
74
}
75
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
76
break;
77
case DISAS_TOO_MANY:
78
update_cc_op(dc);
79
- if (is_singlestepping(dc)) {
80
+ if (dc->ss_active) {
81
tcg_gen_movi_i32(QREG_PC, dc->pc);
82
- gen_singlestep_exception(dc);
83
+ gen_raise_exception(EXCP_TRACE);
84
} else {
85
gen_jmp_tb(dc, 0, dc->pc);
86
}
87
break;
88
case DISAS_JUMP:
89
/* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
90
- if (is_singlestepping(dc)) {
91
- gen_singlestep_exception(dc);
92
+ if (dc->ss_active) {
93
+ gen_raise_exception(EXCP_TRACE);
94
} else {
95
tcg_gen_lookup_and_goto_ptr();
96
}
97
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
98
* We updated CC_OP and PC in gen_exit_tb, but also modified
99
* other state that may require returning to the main loop.
100
*/
101
- if (is_singlestepping(dc)) {
102
- gen_singlestep_exception(dc);
103
+ if (dc->ss_active) {
104
+ gen_raise_exception(EXCP_TRACE);
105
} else {
106
tcg_gen_exit_tb(NULL, 0);
107
}
108
--
109
2.25.1
110
111
diff view generated by jsdifflib
New patch
[PULL 11/24] target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP
1
We were using singlestep_enabled as a proxy for whether
2
translator_use_goto_tb would always return false.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/microblaze/translate.c | 4 ++--
7
1 file changed, 2 insertions(+), 2 deletions(-)
8
9
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/microblaze/translate.c
12
+++ b/target/microblaze/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
14
break;
15
16
case DISAS_JUMP:
17
- if (dc->jmp_dest != -1 && !cs->singlestep_enabled) {
18
+ if (dc->jmp_dest != -1 && !(tb_cflags(dc->base.tb) & CF_NO_GOTO_TB)) {
19
/* Direct jump. */
20
tcg_gen_discard_i32(cpu_btarget);
21
22
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
23
return;
24
}
25
26
- /* Indirect jump (or direct jump w/ singlestep) */
27
+ /* Indirect jump (or direct jump w/ goto_tb disabled) */
28
tcg_gen_mov_i32(cpu_pc, cpu_btarget);
29
tcg_gen_discard_i32(cpu_btarget);
30
31
--
32
2.25.1
33
34
diff view generated by jsdifflib
New patch
[PULL 12/24] target/microblaze: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/microblaze/translate.c | 14 ++------------
6
1 file changed, 2 insertions(+), 12 deletions(-)
7
8
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/target/microblaze/translate.c
11
+++ b/target/microblaze/translate.c
12
@@ -XXX,XX +XXX,XX @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
13
14
static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
15
{
16
- if (dc->base.singlestep_enabled) {
17
- TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
18
- tcg_gen_movi_i32(cpu_pc, dest);
19
- gen_helper_raise_exception(cpu_env, tmp);
20
- tcg_temp_free_i32(tmp);
21
- } else if (translator_use_goto_tb(&dc->base, dest)) {
22
+ if (translator_use_goto_tb(&dc->base, dest)) {
23
tcg_gen_goto_tb(n);
24
tcg_gen_movi_i32(cpu_pc, dest);
25
tcg_gen_exit_tb(dc->base.tb, n);
26
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
27
/* Indirect jump (or direct jump w/ goto_tb disabled) */
28
tcg_gen_mov_i32(cpu_pc, cpu_btarget);
29
tcg_gen_discard_i32(cpu_btarget);
30
-
31
- if (unlikely(cs->singlestep_enabled)) {
32
- gen_raise_exception(dc, EXCP_DEBUG);
33
- } else {
34
- tcg_gen_lookup_and_goto_ptr();
35
- }
36
+ tcg_gen_lookup_and_goto_ptr();
37
return;
38
39
default:
40
--
41
2.25.1
42
43
diff view generated by jsdifflib
New patch
[PULL 13/24] target/mips: Fix single stepping
1
As per an ancient comment in mips_tr_translate_insn about the
2
expectations of gdb, when restarting the insn in a delay slot
3
we also re-execute the branch. Which means that we are
4
expected to execute two insns in this case.
1
5
6
This has been broken since 8b86d6d2580, where we forced max_insns
7
to 1 while single-stepping. This resulted in an exit from the
8
translator loop after the branch but before the delay slot is
9
translated.
10
11
Increase the max_insns to 2 for this case. In addition, bypass
12
the end-of-page check, for when the branch itself ends the page.
13
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
---
17
target/mips/tcg/translate.c | 25 ++++++++++++++++---------
18
1 file changed, 16 insertions(+), 9 deletions(-)
19
20
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/mips/tcg/translate.c
23
+++ b/target/mips/tcg/translate.c
24
@@ -XXX,XX +XXX,XX @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
25
ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
26
INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
27
28
+ /*
29
+ * Execute a branch and its delay slot as a single instruction.
30
+ * This is what GDB expects and is consistent with what the
31
+ * hardware does (e.g. if a delay slot instruction faults, the
32
+ * reported PC is the PC of the branch).
33
+ */
34
+ if (ctx->base.singlestep_enabled && (ctx->hflags & MIPS_HFLAG_BMASK)) {
35
+ ctx->base.max_insns = 2;
36
+ }
37
+
38
LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
39
ctx->hflags);
40
}
41
@@ -XXX,XX +XXX,XX @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
42
if (ctx->base.is_jmp != DISAS_NEXT) {
43
return;
44
}
45
+
46
/*
47
- * Execute a branch and its delay slot as a single instruction.
48
- * This is what GDB expects and is consistent with what the
49
- * hardware does (e.g. if a delay slot instruction faults, the
50
- * reported PC is the PC of the branch).
51
+ * End the TB on (most) page crossings.
52
+ * See mips_tr_init_disas_context about single-stepping a branch
53
+ * together with its delay slot.
54
*/
55
- if (ctx->base.singlestep_enabled &&
56
- (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
57
- ctx->base.is_jmp = DISAS_TOO_MANY;
58
- }
59
- if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE) {
60
+ if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE
61
+ && !ctx->base.singlestep_enabled) {
62
ctx->base.is_jmp = DISAS_TOO_MANY;
63
}
64
}
65
--
66
2.25.1
67
68
diff view generated by jsdifflib
New patch
[PULL 14/24] target/mips: Drop exit checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/mips/tcg/translate.c | 50 +++++++++++++------------------------
7
1 file changed, 18 insertions(+), 32 deletions(-)
8
9
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/mips/tcg/translate.c
12
+++ b/target/mips/tcg/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
14
tcg_gen_exit_tb(ctx->base.tb, n);
15
} else {
16
gen_save_pc(dest);
17
- if (ctx->base.singlestep_enabled) {
18
- save_cpu_state(ctx, 0);
19
- gen_helper_raise_exception_debug(cpu_env);
20
- } else {
21
- tcg_gen_lookup_and_goto_ptr();
22
- }
23
+ tcg_gen_lookup_and_goto_ptr();
24
}
25
}
26
27
@@ -XXX,XX +XXX,XX @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
28
} else {
29
tcg_gen_mov_tl(cpu_PC, btarget);
30
}
31
- if (ctx->base.singlestep_enabled) {
32
- save_cpu_state(ctx, 0);
33
- gen_helper_raise_exception_debug(cpu_env);
34
- }
35
tcg_gen_lookup_and_goto_ptr();
36
break;
37
default:
38
@@ -XXX,XX +XXX,XX @@ static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
39
{
40
DisasContext *ctx = container_of(dcbase, DisasContext, base);
41
42
- if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) {
43
- save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXIT);
44
- gen_helper_raise_exception_debug(cpu_env);
45
- } else {
46
- switch (ctx->base.is_jmp) {
47
- case DISAS_STOP:
48
- gen_save_pc(ctx->base.pc_next);
49
- tcg_gen_lookup_and_goto_ptr();
50
- break;
51
- case DISAS_NEXT:
52
- case DISAS_TOO_MANY:
53
- save_cpu_state(ctx, 0);
54
- gen_goto_tb(ctx, 0, ctx->base.pc_next);
55
- break;
56
- case DISAS_EXIT:
57
- tcg_gen_exit_tb(NULL, 0);
58
- break;
59
- case DISAS_NORETURN:
60
- break;
61
- default:
62
- g_assert_not_reached();
63
- }
64
+ switch (ctx->base.is_jmp) {
65
+ case DISAS_STOP:
66
+ gen_save_pc(ctx->base.pc_next);
67
+ tcg_gen_lookup_and_goto_ptr();
68
+ break;
69
+ case DISAS_NEXT:
70
+ case DISAS_TOO_MANY:
71
+ save_cpu_state(ctx, 0);
72
+ gen_goto_tb(ctx, 0, ctx->base.pc_next);
73
+ break;
74
+ case DISAS_EXIT:
75
+ tcg_gen_exit_tb(NULL, 0);
76
+ break;
77
+ case DISAS_NORETURN:
78
+ break;
79
+ default:
80
+ g_assert_not_reached();
81
}
82
}
83
84
--
85
2.25.1
86
87
diff view generated by jsdifflib
New patch
[PULL 15/24] target/openrisc: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/openrisc/translate.c | 18 +++---------------
7
1 file changed, 3 insertions(+), 15 deletions(-)
8
9
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/openrisc/translate.c
12
+++ b/target/openrisc/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
14
/* The jump destination is indirect/computed; use jmp_pc. */
15
tcg_gen_mov_tl(cpu_pc, jmp_pc);
16
tcg_gen_discard_tl(jmp_pc);
17
- if (unlikely(dc->base.singlestep_enabled)) {
18
- gen_exception(dc, EXCP_DEBUG);
19
- } else {
20
- tcg_gen_lookup_and_goto_ptr();
21
- }
22
+ tcg_gen_lookup_and_goto_ptr();
23
break;
24
}
25
/* The jump destination is direct; use jmp_pc_imm.
26
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
27
break;
28
}
29
tcg_gen_movi_tl(cpu_pc, jmp_dest);
30
- if (unlikely(dc->base.singlestep_enabled)) {
31
- gen_exception(dc, EXCP_DEBUG);
32
- } else {
33
- tcg_gen_lookup_and_goto_ptr();
34
- }
35
+ tcg_gen_lookup_and_goto_ptr();
36
break;
37
38
case DISAS_EXIT:
39
- if (unlikely(dc->base.singlestep_enabled)) {
40
- gen_exception(dc, EXCP_DEBUG);
41
- } else {
42
- tcg_gen_exit_tb(NULL, 0);
43
- }
44
+ tcg_gen_exit_tb(NULL, 0);
45
break;
46
default:
47
g_assert_not_reached();
48
--
49
2.25.1
50
51
diff view generated by jsdifflib
New patch
[PULL 16/24] target/ppc: Drop exit checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
2
Reuse gen_debug_exception to handle architectural debug exceptions.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/ppc/translate.c | 38 ++++++++------------------------------
7
1 file changed, 8 insertions(+), 30 deletions(-)
8
9
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/ppc/translate.c
12
+++ b/target/ppc/translate.c
13
@@ -XXX,XX +XXX,XX @@
14
15
#define CPU_SINGLE_STEP 0x1
16
#define CPU_BRANCH_STEP 0x2
17
-#define GDBSTUB_SINGLE_STEP 0x4
18
19
/* Include definitions for instructions classes and implementations flags */
20
/* #define PPC_DEBUG_DISAS */
21
@@ -XXX,XX +XXX,XX @@ static uint32_t gen_prep_dbgex(DisasContext *ctx)
22
23
static void gen_debug_exception(DisasContext *ctx)
24
{
25
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
26
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
27
ctx->base.is_jmp = DISAS_NORETURN;
28
}
29
30
@@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
31
32
static void gen_lookup_and_goto_ptr(DisasContext *ctx)
33
{
34
- int sse = ctx->singlestep_enabled;
35
- if (unlikely(sse)) {
36
- if (sse & GDBSTUB_SINGLE_STEP) {
37
- gen_debug_exception(ctx);
38
- } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
39
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
40
- } else {
41
- tcg_gen_exit_tb(NULL, 0);
42
- }
43
+ if (unlikely(ctx->singlestep_enabled)) {
44
+ gen_debug_exception(ctx);
45
} else {
46
tcg_gen_lookup_and_goto_ptr();
47
}
48
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
49
ctx->singlestep_enabled = 0;
50
if ((hflags >> HFLAGS_SE) & 1) {
51
ctx->singlestep_enabled |= CPU_SINGLE_STEP;
52
+ ctx->base.max_insns = 1;
53
}
54
if ((hflags >> HFLAGS_BE) & 1) {
55
ctx->singlestep_enabled |= CPU_BRANCH_STEP;
56
}
57
- if (unlikely(ctx->base.singlestep_enabled)) {
58
- ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
59
- }
60
-
61
- if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) {
62
- ctx->base.max_insns = 1;
63
- }
64
}
65
66
static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
67
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
68
DisasContext *ctx = container_of(dcbase, DisasContext, base);
69
DisasJumpType is_jmp = ctx->base.is_jmp;
70
target_ulong nip = ctx->base.pc_next;
71
- int sse;
72
73
if (is_jmp == DISAS_NORETURN) {
74
/* We have already exited the TB. */
75
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
76
}
77
78
/* Honor single stepping. */
79
- sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP);
80
- if (unlikely(sse)) {
81
+ if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)
82
+ && (nip <= 0x100 || nip > 0xf00)) {
83
switch (is_jmp) {
84
case DISAS_TOO_MANY:
85
case DISAS_EXIT_UPDATE:
86
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
87
g_assert_not_reached();
88
}
89
90
- if (sse & GDBSTUB_SINGLE_STEP) {
91
- gen_debug_exception(ctx);
92
- return;
93
- }
94
- /* else CPU_SINGLE_STEP... */
95
- if (nip <= 0x100 || nip > 0xf00) {
96
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
97
- return;
98
- }
99
+ gen_debug_exception(ctx);
100
+ return;
101
}
102
103
switch (is_jmp) {
104
--
105
2.25.1
106
107
diff view generated by jsdifflib
[PULL 3/9] tcg/i386: Split P_VEXW from P_REXW
[PULL 17/24] target/riscv: Remove dead code after exception
1
We need to be able to represent VEX.W on a 32-bit host, where REX.W
1
We have already set DISAS_NORETURN in generate_exception,
2
will always be zero. Fixes the encoding for VPSLLVQ and VPSRLVQ.
2
which makes the exit_tb unreachable.
3
3
4
Fixes: a2ce146a068 ("tcg/i386: Support vector variable shift opcodes")
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/385
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
6
---
8
tcg/i386/tcg-target.c.inc | 13 +++++++------
7
target/riscv/insn_trans/trans_privileged.c.inc | 6 +-----
9
1 file changed, 7 insertions(+), 6 deletions(-)
8
1 file changed, 1 insertion(+), 5 deletions(-)
10
9
11
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
10
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/i386/tcg-target.c.inc
12
--- a/target/riscv/insn_trans/trans_privileged.c.inc
14
+++ b/tcg/i386/tcg-target.c.inc
13
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
15
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
14
@@ -XXX,XX +XXX,XX @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
16
#define P_EXT        0x100        /* 0x0f opcode prefix */
15
{
17
#define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */
16
/* always generates U-level ECALL, fixed in do_interrupt handler */
18
#define P_DATA16 0x400 /* 0x66 opcode prefix */
17
generate_exception(ctx, RISCV_EXCP_U_ECALL);
19
+#define P_VEXW 0x1000 /* Set VEX.W = 1 */
18
- exit_tb(ctx); /* no chaining */
20
#if TCG_TARGET_REG_BITS == 64
19
- ctx->base.is_jmp = DISAS_NORETURN;
21
-# define P_REXW 0x1000 /* Set REX.W = 1 */
20
return true;
22
+# define P_REXW P_VEXW /* Set REX.W = 1; match VEXW */
21
}
23
# define P_REXB_R 0x2000 /* REG field as byte register */
22
24
# define P_REXB_RM 0x4000 /* R/M field as byte register */
23
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
25
# define P_GS 0x8000 /* gs segment override */
24
post = opcode_at(&ctx->base, post_addr);
26
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
27
#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16)
28
#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16)
29
#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
30
-#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW)
31
+#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW)
32
#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
33
#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16)
34
-#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_REXW)
35
+#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW)
36
#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16)
37
#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16)
38
-#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_REXW)
39
+#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW)
40
#define OPC_VZEROUPPER (0x77 | P_EXT)
41
#define OPC_XCHG_ax_r32    (0x90)
42
43
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v,
44
45
/* Use the two byte form if possible, which cannot encode
46
VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */
47
- if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_REXW)) == P_EXT
48
+ if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_VEXW)) == P_EXT
49
&& ((rm | index) & 8) == 0) {
50
/* Two byte VEX prefix. */
51
tcg_out8(s, 0xc5);
52
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v,
53
tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */
54
tcg_out8(s, tmp);
55
56
- tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */
57
+ tmp = (opc & P_VEXW ? 0x80 : 0); /* VEX.W */
58
}
25
}
59
26
60
tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */
27
- if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
28
+ if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
29
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
30
} else {
31
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
32
}
33
- exit_tb(ctx); /* no chaining */
34
- ctx->base.is_jmp = DISAS_NORETURN;
35
return true;
36
}
37
61
--
38
--
62
2.25.1
39
2.25.1
63
40
64
41
diff view generated by jsdifflib
New patch
[PULL 18/24] target/riscv: Remove exit_tb and lookup_and_goto_ptr
1
GDB single-stepping is now handled generically, which means
2
we don't need to do anything in the wrappers.
1
3
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
target/riscv/translate.c | 27 +------------------
8
.../riscv/insn_trans/trans_privileged.c.inc | 4 +--
9
target/riscv/insn_trans/trans_rvi.c.inc | 8 +++---
10
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
11
4 files changed, 7 insertions(+), 34 deletions(-)
12
13
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/translate.c
16
+++ b/target/riscv/translate.c
17
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
18
ctx->base.is_jmp = DISAS_NORETURN;
19
}
20
21
-static void gen_exception_debug(void)
22
-{
23
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
24
-}
25
-
26
-/* Wrapper around tcg_gen_exit_tb that handles single stepping */
27
-static void exit_tb(DisasContext *ctx)
28
-{
29
- if (ctx->base.singlestep_enabled) {
30
- gen_exception_debug();
31
- } else {
32
- tcg_gen_exit_tb(NULL, 0);
33
- }
34
-}
35
-
36
-/* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
37
-static void lookup_and_goto_ptr(DisasContext *ctx)
38
-{
39
- if (ctx->base.singlestep_enabled) {
40
- gen_exception_debug();
41
- } else {
42
- tcg_gen_lookup_and_goto_ptr();
43
- }
44
-}
45
-
46
static void gen_exception_illegal(DisasContext *ctx)
47
{
48
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
49
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
50
tcg_gen_exit_tb(ctx->base.tb, n);
51
} else {
52
tcg_gen_movi_tl(cpu_pc, dest);
53
- lookup_and_goto_ptr(ctx);
54
+ tcg_gen_lookup_and_goto_ptr();
55
}
56
}
57
58
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/riscv/insn_trans/trans_privileged.c.inc
61
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
62
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
63
64
if (has_ext(ctx, RVS)) {
65
gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
66
- exit_tb(ctx); /* no chaining */
67
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
68
ctx->base.is_jmp = DISAS_NORETURN;
69
} else {
70
return false;
71
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
72
#ifndef CONFIG_USER_ONLY
73
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
74
gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
75
- exit_tb(ctx); /* no chaining */
76
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
77
ctx->base.is_jmp = DISAS_NORETURN;
78
return true;
79
#else
80
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/riscv/insn_trans/trans_rvi.c.inc
83
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
84
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
85
if (a->rd != 0) {
86
tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
87
}
88
-
89
- /* No chaining with JALR. */
90
- lookup_and_goto_ptr(ctx);
91
+ tcg_gen_lookup_and_goto_ptr();
92
93
if (misaligned) {
94
gen_set_label(misaligned);
95
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
96
* however we need to end the translation block
97
*/
98
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
99
- exit_tb(ctx);
100
+ tcg_gen_exit_tb(NULL, 0);
101
ctx->base.is_jmp = DISAS_NORETURN;
102
return true;
103
}
104
@@ -XXX,XX +XXX,XX @@ static bool do_csr_post(DisasContext *ctx)
105
{
106
/* We may have changed important cpu state -- exit to main loop. */
107
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
108
- exit_tb(ctx);
109
+ tcg_gen_exit_tb(NULL, 0);
110
ctx->base.is_jmp = DISAS_NORETURN;
111
return true;
112
}
113
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
114
index XXXXXXX..XXXXXXX 100644
115
--- a/target/riscv/insn_trans/trans_rvv.c.inc
116
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
117
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
118
gen_set_gpr(ctx, a->rd, dst);
119
120
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
121
- lookup_and_goto_ptr(ctx);
122
+ tcg_gen_lookup_and_goto_ptr();
123
ctx->base.is_jmp = DISAS_NORETURN;
124
return true;
125
}
126
--
127
2.25.1
128
129
diff view generated by jsdifflib
[PULL 9/9] tcg/arm: Fix tcg_out_vec_op function signature
[PULL 19/24] target/rx: Drop checks for singlestep_enabled
1
From: "Jose R. Ziviani" <jziviani@suse.de>
1
GDB single-stepping is now handled generically.
2
2
3
Commit 5e8892db93 fixed several function signatures but tcg_out_vec_op
4
for arm is missing. It causes a build error on armv6 and armv7:
5
6
tcg-target.c.inc:2718:42: error: argument 5 of type 'const TCGArg *'
7
{aka 'const unsigned int *'} declared as a pointer [-Werror=array-parameter=]
8
const TCGArg *args, const int *const_args)
9
~~~~~~~~~~~~~~^~~~
10
../tcg/tcg.c:120:41: note: previously declared as an array 'const TCGArg[16]'
11
{aka 'const unsigned int[16]'}
12
const TCGArg args[TCG_MAX_OP_ARGS],
13
~~~~~~~~~~~~~~^~~~
14
15
Signed-off-by: Jose R. Ziviani <jziviani@suse.de>
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-Id: <20210908185338.7927-1-jziviani@suse.de>
18
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
19
---
5
---
20
tcg/arm/tcg-target.c.inc | 3 ++-
6
target/rx/helper.h | 1 -
21
1 file changed, 2 insertions(+), 1 deletion(-)
7
target/rx/op_helper.c | 8 --------
8
target/rx/translate.c | 12 ++----------
9
3 files changed, 2 insertions(+), 19 deletions(-)
22
10
23
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
11
diff --git a/target/rx/helper.h b/target/rx/helper.h
24
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
25
--- a/tcg/arm/tcg-target.c.inc
13
--- a/target/rx/helper.h
26
+++ b/tcg/arm/tcg-target.c.inc
14
+++ b/target/rx/helper.h
27
@@ -XXX,XX +XXX,XX @@ static const ARMInsn vec_cmp0_insn[16] = {
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
28
16
DEF_HELPER_1(raise_access_fault, noreturn, env)
29
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
17
DEF_HELPER_1(raise_privilege_violation, noreturn, env)
30
unsigned vecl, unsigned vece,
18
DEF_HELPER_1(wait, noreturn, env)
31
- const TCGArg *args, const int *const_args)
19
-DEF_HELPER_1(debug, noreturn, env)
32
+ const TCGArg args[TCG_MAX_OP_ARGS],
20
DEF_HELPER_2(rxint, noreturn, env, i32)
33
+ const int const_args[TCG_MAX_OP_ARGS])
21
DEF_HELPER_1(rxbrk, noreturn, env)
22
DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32)
23
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/rx/op_helper.c
26
+++ b/target/rx/op_helper.c
27
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_wait(CPURXState *env)
28
raise_exception(env, EXCP_HLT, 0);
29
}
30
31
-void QEMU_NORETURN helper_debug(CPURXState *env)
32
-{
33
- CPUState *cs = env_cpu(env);
34
-
35
- cs->exception_index = EXCP_DEBUG;
36
- cpu_loop_exit(cs);
37
-}
38
-
39
void QEMU_NORETURN helper_rxint(CPURXState *env, uint32_t vec)
34
{
40
{
35
TCGType type = vecl + TCG_TYPE_V64;
41
raise_exception(env, 0x100 + vec, 0);
36
unsigned q = vecl;
42
diff --git a/target/rx/translate.c b/target/rx/translate.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/rx/translate.c
45
+++ b/target/rx/translate.c
46
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
47
tcg_gen_exit_tb(dc->base.tb, n);
48
} else {
49
tcg_gen_movi_i32(cpu_pc, dest);
50
- if (dc->base.singlestep_enabled) {
51
- gen_helper_debug(cpu_env);
52
- } else {
53
- tcg_gen_lookup_and_goto_ptr();
54
- }
55
+ tcg_gen_lookup_and_goto_ptr();
56
}
57
dc->base.is_jmp = DISAS_NORETURN;
58
}
59
@@ -XXX,XX +XXX,XX @@ static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
60
gen_goto_tb(ctx, 0, dcbase->pc_next);
61
break;
62
case DISAS_JUMP:
63
- if (ctx->base.singlestep_enabled) {
64
- gen_helper_debug(cpu_env);
65
- } else {
66
- tcg_gen_lookup_and_goto_ptr();
67
- }
68
+ tcg_gen_lookup_and_goto_ptr();
69
break;
70
case DISAS_UPDATE:
71
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
37
--
72
--
38
2.25.1
73
2.25.1
39
74
40
75
diff view generated by jsdifflib
[PULL 7/9] tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN
[PULL 20/24] target/s390x: Drop check for singlestep_enabled
1
If __APPLE__, ensure that _CALL_DARWIN is set, then remove
1
GDB single-stepping is now handled generically.
2
our local TCG_TARGET_CALL_DARWIN.
3
2
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
4
---
6
tcg/ppc/tcg-target.c.inc | 8 ++++----
5
target/s390x/tcg/translate.c | 8 ++------
7
1 file changed, 4 insertions(+), 4 deletions(-)
6
1 file changed, 2 insertions(+), 6 deletions(-)
8
7
9
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
8
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
10
index XXXXXXX..XXXXXXX 100644
9
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/ppc/tcg-target.c.inc
10
--- a/target/s390x/tcg/translate.c
12
+++ b/tcg/ppc/tcg-target.c.inc
11
+++ b/target/s390x/tcg/translate.c
13
@@ -XXX,XX +XXX,XX @@
12
@@ -XXX,XX +XXX,XX @@ struct DisasContext {
14
#include "elf.h"
13
uint64_t pc_tmp;
15
#include "../tcg-pool.c.inc"
14
uint32_t ilen;
16
15
enum cc_op cc_op;
17
-#if defined _CALL_DARWIN || defined __APPLE__
16
- bool do_debug;
18
-#define TCG_TARGET_CALL_DARWIN
19
+#if !defined _CALL_DARWIN && defined __APPLE__
20
+#define _CALL_DARWIN 1
21
#endif
22
#ifdef _CALL_SYSV
23
# define TCG_TARGET_CALL_ALIGN_ARGS 1
24
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[] = {
25
};
17
};
26
18
27
static const int tcg_target_callee_save_regs[] = {
19
/* Information carried about a condition to be evaluated. */
28
-#ifdef TCG_TARGET_CALL_DARWIN
20
@@ -XXX,XX +XXX,XX @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
29
+#ifdef _CALL_DARWIN
21
30
TCG_REG_R11,
22
dc->cc_op = CC_OP_DYNAMIC;
31
#endif
23
dc->ex_value = dc->base.tb->cs_base;
32
TCG_REG_R14,
24
- dc->do_debug = dc->base.singlestep_enabled;
33
@@ -XXX,XX +XXX,XX @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
25
}
34
# define LINK_AREA_SIZE (6 * SZR)
26
35
# define LR_OFFSET (1 * SZR)
27
static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs)
36
# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
28
@@ -XXX,XX +XXX,XX @@ static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
37
-#elif defined(TCG_TARGET_CALL_DARWIN)
29
/* FALLTHRU */
38
+#elif defined(_CALL_DARWIN)
30
case DISAS_PC_CC_UPDATED:
39
# define LINK_AREA_SIZE (6 * SZR)
31
/* Exit the TB, either by raising a debug exception or by return. */
40
# define LR_OFFSET (2 * SZR)
32
- if (dc->do_debug) {
41
#elif TCG_TARGET_REG_BITS == 64
33
- gen_exception(EXCP_DEBUG);
34
- } else if ((dc->base.tb->flags & FLAG_MASK_PER) ||
35
- dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
36
+ if ((dc->base.tb->flags & FLAG_MASK_PER) ||
37
+ dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
38
tcg_gen_exit_tb(NULL, 0);
39
} else {
40
tcg_gen_lookup_and_goto_ptr();
42
--
41
--
43
2.25.1
42
2.25.1
44
43
45
44
diff view generated by jsdifflib
[PULL 8/9] tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF
[PULL 21/24] target/sh4: Drop check for singlestep_enabled
1
Clang only sets _CALL_ELF for ppc64, and nothing at all to specify
1
GDB single-stepping is now handled generically.
2
the ABI for ppc32. Make a good guess based on other symbols.
3
2
4
Reported-by: Brad Smith <brad@comstyle.com>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
5
---
7
tcg/ppc/tcg-target.c.inc | 21 ++++++++++++++++++---
6
target/sh4/helper.h | 1 -
8
1 file changed, 18 insertions(+), 3 deletions(-)
7
target/sh4/op_helper.c | 5 -----
8
target/sh4/translate.c | 14 +++-----------
9
3 files changed, 3 insertions(+), 17 deletions(-)
9
10
10
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
11
diff --git a/target/sh4/helper.h b/target/sh4/helper.h
11
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/ppc/tcg-target.c.inc
13
--- a/target/sh4/helper.h
13
+++ b/tcg/ppc/tcg-target.c.inc
14
+++ b/target/sh4/helper.h
14
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
15
#include "elf.h"
16
DEF_HELPER_1(raise_slot_illegal_instruction, noreturn, env)
16
#include "../tcg-pool.c.inc"
17
DEF_HELPER_1(raise_fpu_disable, noreturn, env)
17
18
DEF_HELPER_1(raise_slot_fpu_disable, noreturn, env)
18
-#if !defined _CALL_DARWIN && defined __APPLE__
19
-DEF_HELPER_1(debug, noreturn, env)
19
-#define _CALL_DARWIN 1
20
DEF_HELPER_1(sleep, noreturn, env)
20
-#endif
21
DEF_HELPER_2(trapa, noreturn, env, i32)
21
+/*
22
DEF_HELPER_1(exclusive, noreturn, env)
22
+ * Standardize on the _CALL_FOO symbols used by GCC:
23
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
23
+ * Apple XCode does not define _CALL_DARWIN.
24
index XXXXXXX..XXXXXXX 100644
24
+ * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV (32-bit).
25
--- a/target/sh4/op_helper.c
25
+ */
26
+++ b/target/sh4/op_helper.c
26
+#if !defined(_CALL_SYSV) && \
27
@@ -XXX,XX +XXX,XX @@ void helper_raise_slot_fpu_disable(CPUSH4State *env)
27
+ !defined(_CALL_DARWIN) && \
28
raise_exception(env, 0x820, 0);
28
+ !defined(_CALL_AIX) && \
29
}
29
+ !defined(_CALL_ELF)
30
30
+# if defined(__APPLE__)
31
-void helper_debug(CPUSH4State *env)
31
+# define _CALL_DARWIN
32
-{
32
+# elif defined(__ELF__) && TCG_TARGET_REG_BITS == 32
33
- raise_exception(env, EXCP_DEBUG, 0);
33
+# define _CALL_SYSV
34
-}
34
+# else
35
-
35
+# error "Unknown ABI"
36
void helper_sleep(CPUSH4State *env)
36
+# endif
37
{
37
+#endif
38
CPUState *cs = env_cpu(env);
38
+
39
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
39
#ifdef _CALL_SYSV
40
index XXXXXXX..XXXXXXX 100644
40
# define TCG_TARGET_CALL_ALIGN_ARGS 1
41
--- a/target/sh4/translate.c
41
#endif
42
+++ b/target/sh4/translate.c
43
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
44
tcg_gen_exit_tb(ctx->base.tb, n);
45
} else {
46
tcg_gen_movi_i32(cpu_pc, dest);
47
- if (ctx->base.singlestep_enabled) {
48
- gen_helper_debug(cpu_env);
49
- } else if (use_exit_tb(ctx)) {
50
+ if (use_exit_tb(ctx)) {
51
tcg_gen_exit_tb(NULL, 0);
52
} else {
53
tcg_gen_lookup_and_goto_ptr();
54
@@ -XXX,XX +XXX,XX @@ static void gen_jump(DisasContext * ctx)
55
     delayed jump as immediate jump are conditinal jumps */
56
    tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
57
tcg_gen_discard_i32(cpu_delayed_pc);
58
- if (ctx->base.singlestep_enabled) {
59
- gen_helper_debug(cpu_env);
60
- } else if (use_exit_tb(ctx)) {
61
+ if (use_exit_tb(ctx)) {
62
tcg_gen_exit_tb(NULL, 0);
63
} else {
64
tcg_gen_lookup_and_goto_ptr();
65
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
66
switch (ctx->base.is_jmp) {
67
case DISAS_STOP:
68
gen_save_cpu_state(ctx, true);
69
- if (ctx->base.singlestep_enabled) {
70
- gen_helper_debug(cpu_env);
71
- } else {
72
- tcg_gen_exit_tb(NULL, 0);
73
- }
74
+ tcg_gen_exit_tb(NULL, 0);
75
break;
76
case DISAS_NEXT:
77
case DISAS_TOO_MANY:
42
--
78
--
43
2.25.1
79
2.25.1
44
80
45
81
diff view generated by jsdifflib
[PULL 6/9] include/qemu: Use builtins for bswap
[PULL 22/24] target/tricore: Drop check for singlestep_enabled
1
All supported compilers have builtins for this.
1
GDB single-stepping is now handled generically.
2
Drop all of the complicated system detection stuff.
3
2
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-Id: <20210708181743.750220-1-richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
5
---
8
meson.build | 6 -----
6
target/tricore/helper.h | 1 -
9
include/qemu/bswap.h | 53 +++-----------------------------------------
7
target/tricore/op_helper.c | 7 -------
10
2 files changed, 3 insertions(+), 56 deletions(-)
8
target/tricore/translate.c | 14 +-------------
9
3 files changed, 1 insertion(+), 21 deletions(-)
11
10
12
diff --git a/meson.build b/meson.build
11
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
13
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
14
--- a/meson.build
13
--- a/target/tricore/helper.h
15
+++ b/meson.build
14
+++ b/target/tricore/helper.h
16
@@ -XXX,XX +XXX,XX @@ config_host_data.set('HAVE_STRCHRNUL', cc.has_function('strchrnul'))
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(psw_write, void, env, i32)
17
config_host_data.set('HAVE_SYSTEM_FUNCTION', cc.has_function('system', prefix: '#include <stdlib.h>'))
16
DEF_HELPER_1(psw_read, i32, env)
18
17
/* Exceptions */
19
# has_header_symbol
18
DEF_HELPER_3(raise_exception_sync, noreturn, env, i32, i32)
20
-config_host_data.set('CONFIG_BYTESWAP_H',
19
-DEF_HELPER_2(qemu_excp, noreturn, env, i32)
21
- cc.has_header_symbol('byteswap.h', 'bswap_32'))
20
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
22
config_host_data.set('CONFIG_EPOLL_CREATE1',
23
cc.has_header_symbol('sys/epoll.h', 'epoll_create1'))
24
config_host_data.set('CONFIG_HAS_ENVIRON',
25
@@ -XXX,XX +XXX,XX @@ config_host_data.set('CONFIG_INOTIFY',
26
cc.has_header_symbol('sys/inotify.h', 'inotify_init'))
27
config_host_data.set('CONFIG_INOTIFY1',
28
cc.has_header_symbol('sys/inotify.h', 'inotify_init1'))
29
-config_host_data.set('CONFIG_MACHINE_BSWAP_H',
30
- cc.has_header_symbol('machine/bswap.h', 'bswap32',
31
- prefix: '''#include <sys/endian.h>
32
- #include <sys/types.h>'''))
33
config_host_data.set('CONFIG_PRCTL_PR_SET_TIMERSLACK',
34
cc.has_header_symbol('sys/prctl.h', 'PR_SET_TIMERSLACK'))
35
config_host_data.set('CONFIG_RTNETLINK',
36
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
37
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
38
--- a/include/qemu/bswap.h
22
--- a/target/tricore/op_helper.c
39
+++ b/include/qemu/bswap.h
23
+++ b/target/tricore/op_helper.c
40
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ static void raise_exception_sync_helper(CPUTriCoreState *env, uint32_t class,
41
#ifndef BSWAP_H
25
raise_exception_sync_internal(env, class, tin, pc, 0);
42
#define BSWAP_H
43
44
-#ifdef CONFIG_MACHINE_BSWAP_H
45
-# include <sys/endian.h>
46
-# include <machine/bswap.h>
47
-#elif defined(__FreeBSD__)
48
-# include <sys/endian.h>
49
-#elif defined(__HAIKU__)
50
-# include <endian.h>
51
-#elif defined(CONFIG_BYTESWAP_H)
52
-# include <byteswap.h>
53
-#define BSWAP_FROM_BYTESWAP
54
-# else
55
-#define BSWAP_FROM_FALLBACKS
56
-#endif /* ! CONFIG_MACHINE_BSWAP_H */
57
-
58
#ifdef __cplusplus
59
extern "C" {
60
#endif
61
62
#include "fpu/softfloat-types.h"
63
64
-#ifdef BSWAP_FROM_BYTESWAP
65
static inline uint16_t bswap16(uint16_t x)
66
{
67
- return bswap_16(x);
68
+ return __builtin_bswap16(x);
69
}
26
}
70
27
71
static inline uint32_t bswap32(uint32_t x)
28
-void helper_qemu_excp(CPUTriCoreState *env, uint32_t excp)
72
{
73
- return bswap_32(x);
74
+ return __builtin_bswap32(x);
75
}
76
77
static inline uint64_t bswap64(uint64_t x)
78
{
79
- return bswap_64(x);
80
+ return __builtin_bswap64(x);
81
}
82
-#endif
83
-
84
-#ifdef BSWAP_FROM_FALLBACKS
85
-static inline uint16_t bswap16(uint16_t x)
86
-{
29
-{
87
- return (((x & 0x00ff) << 8) |
30
- CPUState *cs = env_cpu(env);
88
- ((x & 0xff00) >> 8));
31
- cs->exception_index = excp;
32
- cpu_loop_exit(cs);
89
-}
33
-}
90
-
34
-
91
-static inline uint32_t bswap32(uint32_t x)
35
/* Addressing mode helper */
36
37
static uint16_t reverse16(uint16_t val)
38
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/tricore/translate.c
41
+++ b/target/tricore/translate.c
42
@@ -XXX,XX +XXX,XX @@ static inline void gen_save_pc(target_ulong pc)
43
tcg_gen_movi_tl(cpu_PC, pc);
44
}
45
46
-static void generate_qemu_excp(DisasContext *ctx, int excp)
92
-{
47
-{
93
- return (((x & 0x000000ffU) << 24) |
48
- TCGv_i32 tmp = tcg_const_i32(excp);
94
- ((x & 0x0000ff00U) << 8) |
49
- gen_helper_qemu_excp(cpu_env, tmp);
95
- ((x & 0x00ff0000U) >> 8) |
50
- ctx->base.is_jmp = DISAS_NORETURN;
96
- ((x & 0xff000000U) >> 24));
51
- tcg_temp_free(tmp);
97
-}
52
-}
98
-
53
-
99
-static inline uint64_t bswap64(uint64_t x)
54
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
100
-{
101
- return (((x & 0x00000000000000ffULL) << 56) |
102
- ((x & 0x000000000000ff00ULL) << 40) |
103
- ((x & 0x0000000000ff0000ULL) << 24) |
104
- ((x & 0x00000000ff000000ULL) << 8) |
105
- ((x & 0x000000ff00000000ULL) >> 8) |
106
- ((x & 0x0000ff0000000000ULL) >> 24) |
107
- ((x & 0x00ff000000000000ULL) >> 40) |
108
- ((x & 0xff00000000000000ULL) >> 56));
109
-}
110
-#endif
111
-
112
-#undef BSWAP_FROM_BYTESWAP
113
-#undef BSWAP_FROM_FALLBACKS
114
115
static inline void bswap16s(uint16_t *s)
116
{
55
{
56
if (translator_use_goto_tb(&ctx->base, dest)) {
57
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
58
tcg_gen_exit_tb(ctx->base.tb, n);
59
} else {
60
gen_save_pc(dest);
61
- if (ctx->base.singlestep_enabled) {
62
- generate_qemu_excp(ctx, EXCP_DEBUG);
63
- } else {
64
- tcg_gen_lookup_and_goto_ptr();
65
- }
66
+ tcg_gen_lookup_and_goto_ptr();
67
}
68
}
69
117
--
70
--
118
2.25.1
71
2.25.1
119
72
120
73
diff view generated by jsdifflib
[PULL 4/9] accel/tcg: remove redundant TCG_KICK_PERIOD define
[PULL 23/24] target/xtensa: Drop check for singlestep_enabled
1
From: Luc Michel <lmichel@kalray.eu>
1
GDB single-stepping is now handled generically.
2
2
3
The TCG_KICK_PERIOD macro is already defined in tcg-accel-ops-rr.h.
4
Remove it from tcg-accel-ops-rr.c.
5
6
Signed-off-by: Luc Michel <lmichel@kalray.eu>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-Id: <20210811141229.12470-1-lmichel@kalray.eu>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
4
---
12
accel/tcg/tcg-accel-ops-rr.c | 2 --
5
target/xtensa/translate.c | 25 ++++++++-----------------
13
1 file changed, 2 deletions(-)
6
1 file changed, 8 insertions(+), 17 deletions(-)
14
7
15
diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c
8
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
16
index XXXXXXX..XXXXXXX 100644
9
index XXXXXXX..XXXXXXX 100644
17
--- a/accel/tcg/tcg-accel-ops-rr.c
10
--- a/target/xtensa/translate.c
18
+++ b/accel/tcg/tcg-accel-ops-rr.c
11
+++ b/target/xtensa/translate.c
19
@@ -XXX,XX +XXX,XX @@ void rr_kick_vcpu_thread(CPUState *unused)
12
@@ -XXX,XX +XXX,XX @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
20
static QEMUTimer *rr_kick_vcpu_timer;
13
if (dc->icount) {
21
static CPUState *rr_current_cpu;
14
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
22
15
}
23
-#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
16
- if (dc->base.singlestep_enabled) {
24
-
17
- gen_exception(dc, EXCP_DEBUG);
25
static inline int64_t rr_next_kick_time(void)
18
+ if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
26
{
19
+ slot = gen_postprocess(dc, slot);
27
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD;
20
+ }
21
+ if (slot >= 0) {
22
+ tcg_gen_goto_tb(slot);
23
+ tcg_gen_exit_tb(dc->base.tb, slot);
24
} else {
25
- if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
26
- slot = gen_postprocess(dc, slot);
27
- }
28
- if (slot >= 0) {
29
- tcg_gen_goto_tb(slot);
30
- tcg_gen_exit_tb(dc->base.tb, slot);
31
- } else {
32
- tcg_gen_exit_tb(NULL, 0);
33
- }
34
+ tcg_gen_exit_tb(NULL, 0);
35
}
36
dc->base.is_jmp = DISAS_NORETURN;
37
}
38
@@ -XXX,XX +XXX,XX @@ static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
39
case DISAS_NORETURN:
40
break;
41
case DISAS_TOO_MANY:
42
- if (dc->base.singlestep_enabled) {
43
- tcg_gen_movi_i32(cpu_pc, dc->pc);
44
- gen_exception(dc, EXCP_DEBUG);
45
- } else {
46
- gen_jumpi(dc, dc->pc, 0);
47
- }
48
+ gen_jumpi(dc, dc->pc, 0);
49
break;
50
default:
51
g_assert_not_reached();
28
--
52
--
29
2.25.1
53
2.25.1
30
54
31
55
diff view generated by jsdifflib
[PULL 2/9] accel/tcg: Clear PAGE_WRITE before translation
[PULL 24/24] Revert "cpu: Move cpu_common_props to hw/core/cpu.c"
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
1
This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f.
2
2
3
translate_insn() implementations fetch instruction bytes piecemeal,
3
Despite a comment saying why cpu_common_props cannot be placed in
4
which can cause qemu-user to generate inconsistent translations if
4
a file that is compiled once, it was moved anyway. Revert that.
5
another thread modifies them concurrently [1].
6
5
7
Fix by making pages containing translated instruction non-writable
6
Since then, Property is not defined in hw/core/cpu.h, so it is now
8
right before loading instruction bytes from them.
7
easier to declare a function to install the properties rather than
8
the Property array itself.
9
9
10
[1] https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00644.html
10
Cc: Eduardo Habkost <ehabkost@redhat.com>
11
11
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
13
Message-Id: <20210805204835.158918-1-iii@linux.ibm.com>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
---
13
---
16
include/exec/translate-all.h | 1 +
14
include/hw/core/cpu.h | 1 +
17
include/exec/translator.h | 39 ++++++++++++++----------
15
cpu.c | 21 +++++++++++++++++++++
18
accel/tcg/translate-all.c | 59 +++++++++++++++++++++---------------
16
hw/core/cpu-common.c | 17 +----------------
19
accel/tcg/translator.c | 39 ++++++++++++++++++++++++
17
3 files changed, 23 insertions(+), 16 deletions(-)
20
4 files changed, 97 insertions(+), 41 deletions(-)
21
18
22
diff --git a/include/exec/translate-all.h b/include/exec/translate-all.h
19
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
23
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
24
--- a/include/exec/translate-all.h
21
--- a/include/hw/core/cpu.h
25
+++ b/include/exec/translate-all.h
22
+++ b/include/hw/core/cpu.h
26
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end);
23
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
27
void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr);
24
GCC_FMT_ATTR(2, 3);
28
25
29
#ifdef CONFIG_USER_ONLY
26
/* $(top_srcdir)/cpu.c */
30
+void page_protect(tb_page_addr_t page_addr);
27
+void cpu_class_init_props(DeviceClass *dc);
31
int page_unprotect(target_ulong address, uintptr_t pc);
28
void cpu_exec_initfn(CPUState *cpu);
32
#endif
29
void cpu_exec_realizefn(CPUState *cpu, Error **errp);
33
30
void cpu_exec_unrealizefn(CPUState *cpu);
34
diff --git a/include/exec/translator.h b/include/exec/translator.h
31
diff --git a/cpu.c b/cpu.c
35
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
36
--- a/include/exec/translator.h
33
--- a/cpu.c
37
+++ b/include/exec/translator.h
34
+++ b/cpu.c
38
@@ -XXX,XX +XXX,XX @@
35
@@ -XXX,XX +XXX,XX @@ void cpu_exec_unrealizefn(CPUState *cpu)
39
#include "exec/exec-all.h"
36
cpu_list_remove(cpu);
40
#include "exec/cpu_ldst.h"
37
}
41
#include "exec/plugin-gen.h"
38
42
+#include "exec/translate-all.h"
39
+static Property cpu_common_props[] = {
43
#include "tcg/tcg.h"
40
+#ifndef CONFIG_USER_ONLY
44
45
46
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContextBase {
47
int num_insns;
48
int max_insns;
49
bool singlestep_enabled;
50
+#ifdef CONFIG_USER_ONLY
51
+ /*
41
+ /*
52
+ * Guest address of the last byte of the last protected page.
42
+ * Create a memory property for softmmu CPU object,
53
+ *
43
+ * so users can wire up its memory. (This can't go in hw/core/cpu.c
54
+ * Pages containing the translated instructions are made non-writable in
44
+ * because that file is compiled only once for both user-mode
55
+ * order to achieve consistency in case another thread is modifying the
45
+ * and system builds.) The default if no link is set up is to use
56
+ * code while translate_insn() fetches the instruction bytes piecemeal.
46
+ * the system address space.
57
+ * Such writer threads are blocked on mmap_lock() in page_unprotect().
58
+ */
47
+ */
59
+ target_ulong page_protect_end;
48
+ DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
49
+ MemoryRegion *),
60
+#endif
50
+#endif
61
} DisasContextBase;
51
+ DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
62
52
+ DEFINE_PROP_END_OF_LIST(),
63
/**
53
+};
64
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
65
*/
66
67
#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
68
- static inline type \
69
- fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
70
- abi_ptr pc, bool do_swap) \
71
- { \
72
- type ret = load_fn(env, pc); \
73
- if (do_swap) { \
74
- ret = swap_fn(ret); \
75
- } \
76
- plugin_insn_append(&ret, sizeof(ret)); \
77
- return ret; \
78
- } \
79
+ type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
80
+ abi_ptr pc, bool do_swap); \
81
static inline type fullname(CPUArchState *env, \
82
DisasContextBase *dcbase, abi_ptr pc) \
83
{ \
84
return fullname ## _swap(env, dcbase, pc, false); \
85
}
86
87
-GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */)
88
-GEN_TRANSLATOR_LD(translator_ldsw, int16_t, cpu_ldsw_code, bswap16)
89
-GEN_TRANSLATOR_LD(translator_lduw, uint16_t, cpu_lduw_code, bswap16)
90
-GEN_TRANSLATOR_LD(translator_ldl, uint32_t, cpu_ldl_code, bswap32)
91
-GEN_TRANSLATOR_LD(translator_ldq, uint64_t, cpu_ldq_code, bswap64)
92
+#define FOR_EACH_TRANSLATOR_LD(F) \
93
+ F(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) \
94
+ F(translator_ldsw, int16_t, cpu_ldsw_code, bswap16) \
95
+ F(translator_lduw, uint16_t, cpu_lduw_code, bswap16) \
96
+ F(translator_ldl, uint32_t, cpu_ldl_code, bswap32) \
97
+ F(translator_ldq, uint64_t, cpu_ldq_code, bswap64)
98
+
54
+
99
+FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
55
+void cpu_class_init_props(DeviceClass *dc)
100
+
101
#undef GEN_TRANSLATOR_LD
102
103
#endif /* EXEC__TRANSLATOR_H */
104
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/accel/tcg/translate-all.c
107
+++ b/accel/tcg/translate-all.c
108
@@ -XXX,XX +XXX,XX @@ static inline void tb_page_add(PageDesc *p, TranslationBlock *tb,
109
invalidate_page_bitmap(p);
110
111
#if defined(CONFIG_USER_ONLY)
112
- if (p->flags & PAGE_WRITE) {
113
- target_ulong addr;
114
- PageDesc *p2;
115
- int prot;
116
-
117
- /* force the host page as non writable (writes will have a
118
- page fault + mprotect overhead) */
119
- page_addr &= qemu_host_page_mask;
120
- prot = 0;
121
- for (addr = page_addr; addr < page_addr + qemu_host_page_size;
122
- addr += TARGET_PAGE_SIZE) {
123
-
124
- p2 = page_find(addr >> TARGET_PAGE_BITS);
125
- if (!p2) {
126
- continue;
127
- }
128
- prot |= p2->flags;
129
- p2->flags &= ~PAGE_WRITE;
130
- }
131
- mprotect(g2h_untagged(page_addr), qemu_host_page_size,
132
- (prot & PAGE_BITS) & ~PAGE_WRITE);
133
- if (DEBUG_TB_INVALIDATE_GATE) {
134
- printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr);
135
- }
136
- }
137
+ /* translator_loop() must have made all TB pages non-writable */
138
+ assert(!(p->flags & PAGE_WRITE));
139
#else
140
/* if some code is already present, then the pages are already
141
protected. So we handle the case where only the first TB is
142
@@ -XXX,XX +XXX,XX @@ int page_check_range(target_ulong start, target_ulong len, int flags)
143
return 0;
144
}
145
146
+void page_protect(tb_page_addr_t page_addr)
147
+{
56
+{
148
+ target_ulong addr;
57
+ device_class_set_props(dc, cpu_common_props);
149
+ PageDesc *p;
150
+ int prot;
151
+
152
+ p = page_find(page_addr >> TARGET_PAGE_BITS);
153
+ if (p && (p->flags & PAGE_WRITE)) {
154
+ /*
155
+ * Force the host page as non writable (writes will have a page fault +
156
+ * mprotect overhead).
157
+ */
158
+ page_addr &= qemu_host_page_mask;
159
+ prot = 0;
160
+ for (addr = page_addr; addr < page_addr + qemu_host_page_size;
161
+ addr += TARGET_PAGE_SIZE) {
162
+
163
+ p = page_find(addr >> TARGET_PAGE_BITS);
164
+ if (!p) {
165
+ continue;
166
+ }
167
+ prot |= p->flags;
168
+ p->flags &= ~PAGE_WRITE;
169
+ }
170
+ mprotect(g2h_untagged(page_addr), qemu_host_page_size,
171
+ (prot & PAGE_BITS) & ~PAGE_WRITE);
172
+ if (DEBUG_TB_INVALIDATE_GATE) {
173
+ printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr);
174
+ }
175
+ }
176
+}
58
+}
177
+
59
+
178
/* called from signal handler: invalidate the code and unprotect the
60
void cpu_exec_initfn(CPUState *cpu)
179
* page. Return 0 if the fault was not handled, 1 if it was handled,
61
{
180
* and 2 if it was handled but the caller must cause the TB to be
62
cpu->as = NULL;
181
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
63
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
182
index XXXXXXX..XXXXXXX 100644
64
index XXXXXXX..XXXXXXX 100644
183
--- a/accel/tcg/translator.c
65
--- a/hw/core/cpu-common.c
184
+++ b/accel/tcg/translator.c
66
+++ b/hw/core/cpu-common.c
185
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest)
67
@@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
186
return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) == 0;
68
return cpu->cpu_index;
187
}
69
}
188
70
189
+static inline void translator_page_protect(DisasContextBase *dcbase,
71
-static Property cpu_common_props[] = {
190
+ target_ulong pc)
72
-#ifndef CONFIG_USER_ONLY
191
+{
73
- /* Create a memory property for softmmu CPU object,
192
+#ifdef CONFIG_USER_ONLY
74
- * so users can wire up its memory. (This can't go in hw/core/cpu.c
193
+ dcbase->page_protect_end = pc | ~TARGET_PAGE_MASK;
75
- * because that file is compiled only once for both user-mode
194
+ page_protect(pc);
76
- * and system builds.) The default if no link is set up is to use
195
+#endif
77
- * the system address space.
196
+}
78
- */
197
+
79
- DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
198
void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
80
- MemoryRegion *),
199
CPUState *cpu, TranslationBlock *tb, int max_insns)
81
-#endif
82
- DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
83
- DEFINE_PROP_END_OF_LIST(),
84
-};
85
-
86
static void cpu_class_init(ObjectClass *klass, void *data)
200
{
87
{
201
@@ -XXX,XX +XXX,XX @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
88
DeviceClass *dc = DEVICE_CLASS(klass);
202
db->num_insns = 0;
89
@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
203
db->max_insns = max_insns;
90
dc->realize = cpu_common_realizefn;
204
db->singlestep_enabled = cflags & CF_SINGLE_STEP;
91
dc->unrealize = cpu_common_unrealizefn;
205
+ translator_page_protect(db, db->pc_next);
92
dc->reset = cpu_common_reset;
206
93
- device_class_set_props(dc, cpu_common_props);
207
ops->init_disas_context(db, cpu);
94
+ cpu_class_init_props(dc);
208
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
95
/*
209
@@ -XXX,XX +XXX,XX @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
96
* Reason: CPUs still need special care by board code: wiring up
210
}
97
* IRQs, adding reset handlers, halting non-first CPUs, ...
211
#endif
212
}
213
+
214
+static inline void translator_maybe_page_protect(DisasContextBase *dcbase,
215
+ target_ulong pc, size_t len)
216
+{
217
+#ifdef CONFIG_USER_ONLY
218
+ target_ulong end = pc + len - 1;
219
+
220
+ if (end > dcbase->page_protect_end) {
221
+ translator_page_protect(dcbase, end);
222
+ }
223
+#endif
224
+}
225
+
226
+#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
227
+ type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
228
+ abi_ptr pc, bool do_swap) \
229
+ { \
230
+ translator_maybe_page_protect(dcbase, pc, sizeof(type)); \
231
+ type ret = load_fn(env, pc); \
232
+ if (do_swap) { \
233
+ ret = swap_fn(ret); \
234
+ } \
235
+ plugin_insn_append(&ret, sizeof(ret)); \
236
+ return ret; \
237
+ }
238
+
239
+FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
240
+
241
+#undef GEN_TRANSLATOR_LD
242
--
98
--
243
2.25.1
99
2.25.1
244
100
245
101
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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