Hi,

This series adds the minimum set of models (XIVE2, PHB5) to boot a
baremetal POWER10 machine using the OpenPOWER firmware images.

The major change is the support for the interrupt controller of the
POWER10 processor. XIVE2 is very much like XIVE but the register
interface, the different MMIO regions, the XIVE internal descriptors
have gone through a major cleanup. It was easier to duplicate the
models then to try to adapt the current models. XIVE2 adds some new
set of features. Not all are modeled here but we add the
"Address-based trigger" mode which is activated by default on the
PHB5. When using ABT, the PHB5 offloads all interrupt management on
the IC, this to improve latency.

Thanks,

C.

Changes in v2:

  - Most comments on v1 have been addressed independently and merged
    in ppc-for-6.2.

Cédric Le Goater (20):
  docs/system: ppc: Update the URL for OpenPOWER firmware images
  ppc/pnv: Add an assert when calculating the RAM distribution on chips
  ppc/xive2: Introduce a XIVE2 core framework
  ppc/xive2: Introduce a presenter matching routine
  ppc/pnv: Add a XIVE2 controller to the POWER10 chip
  ppc/pnv: Add a OCC model for POWER10
  ppc/pnv: Add POWER10 quads
  ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge
  ppc/pnv: Add a HOMER model to POWER10
  ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10)
  ppc/xive2: Add support for notification injection on ESB pages
  ppc/xive: Add support for PQ state bits offload
  ppc/pnv: Add support for PQ offload on PHB5
  ppc/pnv: Add support for PHB5 "Address-based trigger" mode
  pnv/xive2: Introduce new capability bits
  ppc/pnv: add XIVE Gen2 TIMA support
  pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1)
  xive2: Add a get_config() handler for the router configuration
  pnv/xive2: Add support for automatic save&restore
  pnv/xive2: Add support for 8bits thread id

 docs/system/ppc/powernv.rst         |    3 +-
 hw/intc/pnv_xive2_regs.h            |  442 ++++++
 include/hw/pci-host/pnv_phb4.h      |   11 +
 include/hw/pci-host/pnv_phb4_regs.h |    3 +
 include/hw/ppc/pnv.h                |   39 +
 include/hw/ppc/pnv_homer.h          |    3 +
 include/hw/ppc/pnv_occ.h            |    2 +
 include/hw/ppc/pnv_xive.h           |   71 +
 include/hw/ppc/pnv_xscom.h          |   15 +
 include/hw/ppc/xive.h               |   10 +-
 include/hw/ppc/xive2.h              |  109 ++
 include/hw/ppc/xive2_regs.h         |  210 +++
 hw/intc/pnv_xive.c                  |   37 +-
 hw/intc/pnv_xive2.c                 | 2127 +++++++++++++++++++++++++++
 hw/intc/spapr_xive.c                |   25 +
 hw/intc/xive.c                      |   77 +-
 hw/intc/xive2.c                     | 1017 +++++++++++++
 hw/pci-host/pnv_phb4.c              |   87 +-
 hw/pci-host/pnv_phb4_pec.c          |   44 +
 hw/ppc/pnv.c                        |  267 +++-
 hw/ppc/pnv_homer.c                  |   64 +
 hw/ppc/pnv_occ.c                    |   16 +
 hw/ppc/pnv_psi.c                    |   38 +-
 hw/intc/meson.build                 |    4 +-
 hw/pci-host/trace-events            |    2 +
 25 files changed, 4680 insertions(+), 43 deletions(-)
 create mode 100644 hw/intc/pnv_xive2_regs.h
 create mode 100644 include/hw/ppc/xive2.h
 create mode 100644 include/hw/ppc/xive2_regs.h
 create mode 100644 hw/intc/pnv_xive2.c
 create mode 100644 hw/intc/xive2.c

-- 
2.31.1