Series comparison

-[PULL 00/33] riscv-to-apply queue
+[PULL 00/28] riscv-to-apply queue
-From: Alistair Francis <alistair.francis@wdc.com>
+The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
-The following changes since commit d52dff5d8048d4982437db9606c27bb4127cf9d0:
+  Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
   Merge remote-tracking branch 'remotes/marcandre/tags/clip-pull-request' into staging (2021-08-31 14:38:15 +0100)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210901-2
+  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
-for you to fetch changes up to 8e034ae44dba6291beb07f7f2a932c1e5ab83e98:
+for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
-  target/riscv: Use {get,dest}_gpr for RVV (2021-09-01 11:59:12 +1000)
+  target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
 ----------------------------------------------------------------
-First RISC-V PR for QEMU 6.2
+RISC-V PR for 9.1
- - Add a config for Shakti UART
+* APLICs add child earlier than realize
- - Fixup virt flash node
+* Fix exposure of Zkr
- - Don't override users supplied ISA version
+* Raise exceptions on wrs.nto
- - Fixup some CSR accesses
+* Implement SBI debug console (DBCN) calls for KVM
- - Use g_strjoinv() for virt machine PLIC string config
+* Support 64-bit addresses for initrd
- - Fix an overflow in the SiFive CLINT
+* Change RISCV_EXCP_SEMIHOST exception number to 63
- - Add 64-bit register access helpers
+* Tolerate KVM disable ext errors
- - Replace tcg_const_* with direct constant usage
+* Set tval in breakpoints
 * Add support for Zve32x extension
 * Add support for Zve64x extension
 * Relax vector register check in RISCV gdbstub
 * Fix the element agnostic Vector function problem
 * Fix Zvkb extension config
 * Implement dynamic establishment of custom decoder
 * Add th.sxstatus CSR emulation
 * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
 * Check single width operator for vector fp widen instructions
 * Check single width operator for vfncvt.rod.f.f.w
 * Remove redudant SEW checking for vector fp narrow/widen instructions
 * Prioritize pmp errors in raise_mmu_exception()
 * Do not set mtval2 for non guest-page faults
 * Remove experimental prefix from "B" extension
 * Fixup CBO extension register calculation
 * Fix the hart bit setting of AIA
 * Fix reg_width in ricsv_gen_dynamic_vector_feature()
 * Decode all of the pmpcfg and pmpaddr CSRs
 * Raise an exception when CSRRS/CSRRC writes a read-only CSR
 ----------------------------------------------------------------
-Bin Meng (2):
+Alexei Filippov (1):
-      hw/riscv: virt: Move flash node to root
+      target/riscv: do not set mtval2 for non guest-page faults
       target/riscv: Correct a comment in riscv_csrrw()
-David Hoppenbrouwers (1):
+Alistair Francis (2):
-      hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp()
+      target/riscv: rvzicbo: Fixup CBO extension register calculation
       disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
-Joe Komlodi (2):
+Andrew Jones (2):
-      hw/core/register: Add more 64-bit utilities
+      target/riscv/kvm: Fix exposure of Zkr
-      hw/registerfields: Use 64-bit bitfield for FIELD_DP64
+      target/riscv: Raise exceptions on wrs.nto
-LIU Zhiwei (2):
+Cheng Yang (1):
-      target/riscv: Don't wrongly override isa version
+      hw/riscv/boot.c: Support 64-bit address for initrd
       target/riscv: Add User CSRs read-only check
-Peter Maydell (1):
+Christoph Müllner (1):
-      hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()
+      riscv: thead: Add th.sxstatus CSR emulation
-Richard Henderson (24):
+Clément Léger (1):
-      target/riscv: Use tcg_constant_*
+      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
       tests/tcg/riscv64: Add test for division
       target/riscv: Clean up division helpers
       target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
       target/riscv: Introduce DisasExtend and new helpers
       target/riscv: Add DisasExtend to gen_arith*
       target/riscv: Remove gen_arith_div*
       target/riscv: Use gen_arith for mulh and mulhu
       target/riscv: Move gen_* helpers for RVM
       target/riscv: Move gen_* helpers for RVB
       target/riscv: Add DisasExtend to gen_unary
       target/riscv: Use DisasExtend in shift operations
       target/riscv: Use extracts for sraiw and srliw
       target/riscv: Use get_gpr in branches
       target/riscv: Use {get, dest}_gpr for integer load/store
       target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation
       target/riscv: Fix hgeie, hgeip
       target/riscv: Reorg csr instructions
       target/riscv: Use {get,dest}_gpr for RVA
       target/riscv: Use gen_shift_imm_fn for slli_uw
       target/riscv: Use {get,dest}_gpr for RVF
       target/riscv: Use {get,dest}_gpr for RVD
       target/riscv: Tidy trans_rvh.c.inc
       target/riscv: Use {get,dest}_gpr for RVV
-Vijai Kumar K (1):
+Daniel Henrique Barboza (6):
-      hw/char: Add config for shakti uart
+      target/riscv/kvm: implement SBI debug console (DBCN) calls
       target/riscv/kvm: tolerate KVM disable ext errors
       target/riscv/debug: set tval=pc in breakpoint exceptions
       trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
       target/riscv: prioritize pmp errors in raise_mmu_exception()
       riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
- include/hw/register.h                   |   8 +
+Huang Tao (2):
- include/hw/registerfields.h             |  10 +-
+      target/riscv: Fix the element agnostic function problem
- target/riscv/helper.h                   |   6 +-
+      target/riscv: Implement dynamic establishment of custom decoder
  target/riscv/insn32.decode              |   1 +
  hw/core/register.c                      |  12 +
  hw/intc/sifive_clint.c                  |  25 +-
  hw/riscv/virt.c                         |  35 +-
  target/riscv/cpu.c                      |  14 +-
  target/riscv/csr.c                      |  59 ++-
  target/riscv/op_helper.c                |  18 +-
  target/riscv/translate.c                | 689 +++++++-------------------------
  tests/tcg/riscv64/test-div.c            |  58 +++
  target/riscv/insn_trans/trans_rva.c.inc |  49 +--
  target/riscv/insn_trans/trans_rvb.c.inc | 366 +++++++++++++----
  target/riscv/insn_trans/trans_rvd.c.inc | 127 +++---
  target/riscv/insn_trans/trans_rvf.c.inc | 149 ++++---
  target/riscv/insn_trans/trans_rvh.c.inc | 266 +++---------
  target/riscv/insn_trans/trans_rvi.c.inc | 372 +++++++++--------
  target/riscv/insn_trans/trans_rvm.c.inc | 193 +++++++--
  target/riscv/insn_trans/trans_rvv.c.inc | 149 +++----
  hw/char/Kconfig                         |   3 +
  hw/char/meson.build                     |   2 +-
  hw/riscv/Kconfig                        |   5 +-
  tests/tcg/riscv64/Makefile.target       |   5 +
 files changed, 1240 insertions(+), 1381 deletions(-)
  create mode 100644 tests/tcg/riscv64/test-div.c
  create mode 100644 tests/tcg/riscv64/Makefile.target
+Jason Chien (3):
+      target/riscv: Add support for Zve32x extension
+      target/riscv: Add support for Zve64x extension
+      target/riscv: Relax vector register check in RISCV gdbstub
+Max Chou (4):
+      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
+      target/riscv: rvv: Check single width operator for vector fp widen instructions
+      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
+      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
+Rob Bradford (1):
+      target/riscv: Remove experimental prefix from "B" extension
+Yangyu Chen (1):
+      target/riscv/cpu.c: fix Zvkb extension config
+Yong-Xuan Wang (1):
+      target/riscv/kvm.c: Fix the hart bit setting of AIA
+Yu-Ming Chang (1):
+      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
+yang.zhang (1):
+      hw/intc/riscv_aplic: APLICs should add child earlier than realize
+ MAINTAINERS                                    |   1 +
+ target/riscv/cpu.h                             |  11 ++
+ target/riscv/cpu_bits.h                        |   2 +-
+ target/riscv/cpu_cfg.h                         |   2 +
+ target/riscv/helper.h                          |   1 +
+ target/riscv/sbi_ecall_interface.h             |  17 +++
+ target/riscv/tcg/tcg-cpu.h                     |  15 +++
+ disas/riscv.c                                  |  65 +++++++++-
+ hw/intc/riscv_aplic.c                          |   8 +-
+ hw/riscv/boot.c                                |   4 +-
+ target/riscv/cpu.c                             |  10 +-
+ target/riscv/cpu_helper.c                      |  37 +++---
+ target/riscv/csr.c                             |  71 +++++++++--
+ target/riscv/debug.c                           |   3 +
+ target/riscv/gdbstub.c                         |   8 +-
+ target/riscv/kvm/kvm-cpu.c                     | 157 ++++++++++++++++++++++++-
+ target/riscv/op_helper.c                       |  17 ++-
+ target/riscv/tcg/tcg-cpu.c                     |  50 +++++---
+ target/riscv/th_csr.c                          |  79 +++++++++++++
+ target/riscv/translate.c                       |  31 +++--
+ target/riscv/vector_internals.c                |  22 ++++
+ target/riscv/insn_trans/trans_privileged.c.inc |   2 +
+ target/riscv/insn_trans/trans_rvv.c.inc        |  46 +++++---
+ target/riscv/insn_trans/trans_rvzawrs.c.inc    |  29 +++--
+ target/riscv/insn_trans/trans_rvzicbo.c.inc    |  16 ++-
+ target/riscv/meson.build                       |   1 +
+files changed, 596 insertions(+), 109 deletions(-)
+ create mode 100644 target/riscv/th_csr.c

-[PULL 01/33] hw/char: Add config for shakti uart
+Deleted patch
-From: Vijai Kumar K <vijai@behindbytes.com>
-Use a dedicated UART config(CONFIG_SHAKTI_UART) to select
-shakti uart.
-Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210731190229.137483-1-vijai@behindbytes.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/char/Kconfig     | 3 +++
- hw/char/meson.build | 2 +-
- hw/riscv/Kconfig    | 5 +----
-files changed, 5 insertions(+), 5 deletions(-)
-diff --git a/hw/char/Kconfig b/hw/char/Kconfig
-index XXXXXXX..XXXXXXX 100644
---- a/hw/char/Kconfig
-+++ b/hw/char/Kconfig
-@@ -XXX,XX +XXX,XX @@ config SIFIVE_UART
- config GOLDFISH_TTY
-     bool
-+
-+config SHAKTI_UART
-+    bool
-diff --git a/hw/char/meson.build b/hw/char/meson.build
-index XXXXXXX..XXXXXXX 100644
---- a/hw/char/meson.build
-+++ b/hw/char/meson.build
-@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('serial.c'))
- softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c'))
- softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c'))
- softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci-multi.c'))
--softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c'))
-+softmmu_ss.add(when: 'CONFIG_SHAKTI_UART', if_true: files('shakti_uart.c'))
- softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-console.c'))
- softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c'))
- softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c'))
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/Kconfig
-+++ b/hw/riscv/Kconfig
-@@ -XXX,XX +XXX,XX @@ config OPENTITAN
-     select IBEX
-     select UNIMP
--config SHAKTI
--    bool
--
- config SHAKTI_C
-     bool
-     select UNIMP
--    select SHAKTI
-+    select SHAKTI_UART
-     select SIFIVE_CLINT
-     select SIFIVE_PLIC
---
-.31.1

-[PULL 02/33] hw/riscv: virt: Move flash node to root
+Deleted patch
-From: Bin Meng <bmeng.cn@gmail.com>
-The flash is not inside the SoC, so it's inappropriate to put it
-under the /soc node. Move it to root instead.
-Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210807035641.22449-1-bmeng.cn@gmail.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/virt.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
-     qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ);
-     g_free(name);
--    name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase);
-+    name = g_strdup_printf("/flash@%" PRIx64, flashbase);
-     qemu_fdt_add_subnode(mc->fdt, name);
-     qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
-     qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
---
-.31.1

-[PULL 31/33] target/riscv: Use {get,dest}_gpr for RVD
+[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
-From: Richard Henderson <richard.henderson@linaro.org>
+From: "yang.zhang" <yang.zhang@hexintek.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Since only root APLICs can have hw IRQ lines, aplic->parent should
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+be initialized first.
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210823195529.560295-23-richard.henderson@linaro.org
+Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvd.c.inc | 125 ++++++++++++------------
+ hw/intc/riscv_aplic.c | 8 ++++----
-file changed, 60 insertions(+), 65 deletions(-)
+file changed, 4 insertions(+), 4 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
+diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvd.c.inc
+--- a/hw/intc/riscv_aplic.c
-+++ b/target/riscv/insn_trans/trans_rvd.c.inc
++++ b/hw/intc/riscv_aplic.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
+     qdev_prop_set_bit(dev, "msimode", msimode);
- static bool trans_fld(DisasContext *ctx, arg_fld *a)
+     qdev_prop_set_bit(dev, "mmode", mmode);
- {
-+    TCGv addr;
++    if (parent) {
-+
++        riscv_aplic_add_child(parent, dev);
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    TCGv t0 = tcg_temp_new();
 -    gen_get_gpr(ctx, t0, a->rs1);
 -    tcg_gen_addi_tl(t0, t0, a->imm);
 -    tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
 +    addr = get_gpr(ctx, a->rs1, EXT_NONE);
 +    if (a->imm) {
 +        TCGv temp = temp_new(ctx);
 +        tcg_gen_addi_tl(temp, addr, a->imm);
 +        addr = temp;
 +    }
 +
-+    tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ);
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-     mark_fs_dirty(ctx);
+     if (!is_kvm_aia(msimode)) {
--    tcg_temp_free(t0);
+         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
-     return true;
+     }
- }
+-    if (parent) {
- static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
+-        riscv_aplic_add_child(parent, dev);
- {
+-    }
 +    TCGv addr;
 +
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    TCGv t0 = tcg_temp_new();
 -    gen_get_gpr(ctx, t0, a->rs1);
 -    tcg_gen_addi_tl(t0, t0, a->imm);
 -    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
 +    addr = get_gpr(ctx, a->rs1, EXT_NONE);
 +    if (a->imm) {
 +        TCGv temp = temp_new(ctx);
 +        tcg_gen_addi_tl(temp, addr, a->imm);
 +        addr = temp;
 +    }
 +
 +    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ);
 -    tcg_temp_free(t0);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    TCGv t0 = tcg_temp_new();
 -    gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +    gen_helper_feq_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    TCGv t0 = tcg_temp_new();
 -    gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +    gen_helper_flt_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    TCGv t0 = tcg_temp_new();
 -    gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +    gen_helper_fle_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    TCGv t0 = tcg_temp_new();
 -    gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +
 +    gen_helper_fclass_d(dest, cpu_fpr[a->rs1]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    TCGv t0 = tcg_temp_new();
 -    gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +    gen_set_rm(ctx, a->rm);
 +    gen_helper_fcvt_w_d(dest, cpu_env, cpu_fpr[a->rs1]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    TCGv t0 = tcg_temp_new();
 -    gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +    gen_set_rm(ctx, a->rm);
 +    gen_helper_fcvt_wu_d(dest, cpu_env, cpu_fpr[a->rs1]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    TCGv t0 = tcg_temp_new();
 -    gen_get_gpr(ctx, t0, a->rs1);
 +    TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
      gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
 -    tcg_temp_free(t0);
 +    gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, src);
      mark_fs_dirty(ctx);
      return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    TCGv t0 = tcg_temp_new();
 -    gen_get_gpr(ctx, t0, a->rs1);
 +    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
      gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
 -    tcg_temp_free(t0);
 +    gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, src);
      mark_fs_dirty(ctx);
      return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    TCGv t0 = tcg_temp_new();
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +
      gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +    gen_helper_fcvt_l_d(dest, cpu_env, cpu_fpr[a->rs1]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    TCGv t0 = tcg_temp_new();
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +
      gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +    gen_helper_fcvt_lu_d(dest, cpu_env, cpu_fpr[a->rs1]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    TCGv t0 = tcg_temp_new();
 -    gen_get_gpr(ctx, t0, a->rs1);
 +    TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
      gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
 -    tcg_temp_free(t0);
 +    gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, src);
 +
      mark_fs_dirty(ctx);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVD);
 -    TCGv t0 = tcg_temp_new();
 -    gen_get_gpr(ctx, t0, a->rs1);
 +    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
      gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
 -    tcg_temp_free(t0);
 +    gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, src);
 +
      mark_fs_dirty(ctx);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
      REQUIRE_EXT(ctx, RVD);
  #ifdef TARGET_RISCV64
 -    TCGv t0 = tcg_temp_new();
 -    gen_get_gpr(ctx, t0, a->rs1);
 -
--    tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
+     if (!msimode) {
--    tcg_temp_free(t0);
+         for (i = 0; i < num_harts; i++) {
-+    tcg_gen_mov_tl(cpu_fpr[a->rd], get_gpr(ctx, a->rs1, EXT_NONE));
+             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
      mark_fs_dirty(ctx);
      return true;
  #else
 --
-.31.1
+.45.1

-[PULL 25/33] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation
+[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Andrew Jones <ajones@ventanamicro.com>
-We distinguish write-only by passing ret_value as NULL.
+The Zkr extension may only be exposed to KVM guests if the VMM
 implements the SEED CSR. Use the same implementation as TCG.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Without this patch, running with a KVM which does not forward the
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+SEED CSR access to QEMU will result in an ILL exception being
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+injected into the guest (this results in Linux guests crashing on
-Message-id: 20210823195529.560295-17-richard.henderson@linaro.org
+boot). And, when running with a KVM which does forward the access,
 QEMU will crash, since QEMU doesn't know what to do with the exit.
 Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
 Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 23 +++++++++++++++--------
+ target/riscv/cpu.h         |  3 +++
-file changed, 15 insertions(+), 8 deletions(-)
+ target/riscv/csr.c         | 18 ++++++++++++++----
  target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 files changed, 42 insertions(+), 4 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
+ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
++target_ulong riscv_new_csr_seed(target_ulong new_value,
++                                target_ulong write_mask);
++
+ uint8_t satp_mode_max_from_map(uint32_t map);
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
-     /* Shift the S bits to their VS bit location in mip */
+ #endif
-     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
-                       (write_mask << 1) & vsip_writable_mask & env->hideleg);
+ /* Crypto Extension */
--    *ret_value &= VS_MODE_INTERRUPTS;
+-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
--    /* Shift the VS bits to their S bit location in vsip */
+-                               target_ulong *ret_value,
--    *ret_value >>= 1;
+-                               target_ulong new_value,
 -                               target_ulong write_mask)
 +target_ulong riscv_new_csr_seed(target_ulong new_value,
 +                                target_ulong write_mask)
  {
      uint16_t random_v;
      Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
          rval = random_v | SEED_OPST_ES16;
      }
 +    return rval;
 +}
 +
-+    if (ret_value) {
++static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-+        *ret_value &= VS_MODE_INTERRUPTS;
++                               target_ulong *ret_value,
-+        /* Shift the VS bits to their S bit location in vsip */
++                               target_ulong new_value,
-+        *ret_value >>= 1;
++                               target_ulong write_mask)
-+    }
++{
 +    target_ulong rval;
 +
 +    rval = riscv_new_csr_seed(new_value, write_mask);
 +
      if (ret_value) {
          *ret_value = rval;
      }
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
      return ret;
  }
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
++static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
-                       write_mask & env->mideleg & sip_writable_mask);
++{
-     }
++    target_ulong csr_num = run->riscv_csr.csr_num;
++    target_ulong new_value = run->riscv_csr.new_value;
--    *ret_value &= env->mideleg;
++    target_ulong write_mask = run->riscv_csr.write_mask;
-+    if (ret_value) {
++    int ret = 0;
-+        *ret_value &= env->mideleg;
++
 +    switch (csr_num) {
 +    case CSR_SEED:
 +        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "%s: un-handled CSR EXIT for CSR %lx\n",
 +                      __func__, csr_num);
 +        ret = -1;
 +        break;
 +    }
-     return ret;
++
- }
++    return ret;
++}
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
++
-     int ret = rmw_mip(env, 0, ret_value, new_value,
+ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
-                       write_mask & hvip_writable_mask);
+ {
+     int ret = 0;
--    *ret_value &= hvip_writable_mask;
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
--
+     case KVM_EXIT_RISCV_SBI:
-+    if (ret_value) {
+         ret = kvm_riscv_handle_sbi(cs, run);
-+        *ret_value &= hvip_writable_mask;
+         break;
-+    }
++    case KVM_EXIT_RISCV_CSR:
-     return ret;
++        ret = kvm_riscv_handle_csr(cs, run);
- }
++        break;
+     default:
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
+         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
-     int ret = rmw_mip(env, 0, ret_value, new_value,
+                       __func__, run->exit_reason);
                        write_mask & hip_writable_mask);
 -    *ret_value &= hip_writable_mask;
 -
 +    if (ret_value) {
 +        *ret_value &= hip_writable_mask;
 +    }
      return ret;
  }
 --
-.31.1
+.45.1

-[PULL 27/33] target/riscv: Reorg csr instructions
+[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Andrew Jones <ajones@ventanamicro.com>
-Introduce csrr and csrw helpers, for read-only and write-only insns.
+Implementing wrs.nto to always just return is consistent with the
 specification, as the instruction is permitted to terminate the
 stall for any reason, but it's not useful for virtualization, where
 we'd like the guest to trap to the hypervisor in order to allow
 scheduling of the lock holding VCPU. Change to always immediately
 raise exceptions when the appropriate conditions are present,
 otherwise continue to just return. Note, immediately raising
 exceptions is also consistent with the specification since the
 time limit that should expire prior to the exception is
 implementation-specific.
-Note that we do not properly implement this in riscv_csrrw, in that
+Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
-we cannot distinguish true read-only (rs1 == 0) from any other zero
+Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
-write_mask another source register -- this should still raise an
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 exception for read-only registers.
 Only issue gen_io_start for CF_USE_ICOUNT.
 Use ctx->zero for csrrc.
 Use get_gpr and dest_gpr.
 Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210823195529.560295-19-richard.henderson@linaro.org
+Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/helper.h                   |   6 +-
+ target/riscv/helper.h                       |  1 +
- target/riscv/op_helper.c                |  18 +--
+ target/riscv/op_helper.c                    | 11 ++++++++
- target/riscv/insn_trans/trans_rvi.c.inc | 174 +++++++++++++++++-------
+ target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
-files changed, 132 insertions(+), 66 deletions(-)
+files changed, 32 insertions(+), 9 deletions(-)
 diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/helper.h
 +++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
- DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+ DEF_HELPER_1(sret, tl, env)
+ DEF_HELPER_1(mret, tl, env)
- /* Special functions */
+ DEF_HELPER_1(wfi, void, env)
--DEF_HELPER_3(csrrw, tl, env, tl, tl)
++DEF_HELPER_1(wrs_nto, void, env)
--DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
+ DEF_HELPER_1(tlb_flush, void, env)
--DEF_HELPER_4(csrrc, tl, env, tl, tl, tl)
+ DEF_HELPER_1(tlb_flush_all, void, env)
-+DEF_HELPER_2(csrr, tl, env, int)
+ /* Native Debug */
 +DEF_HELPER_3(csrw, void, env, int, tl)
 +DEF_HELPER_4(csrrw, tl, env, int, tl, tl)
  #ifndef CONFIG_USER_ONLY
  DEF_HELPER_2(sret, tl, env, tl)
  DEF_HELPER_2(mret, tl, env, tl)
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
-@@ -XXX,XX +XXX,XX @@ void helper_raise_exception(CPURISCVState *env, uint32_t exception)
+@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
-     riscv_raise_exception(env, exception, 0);
+     }
  }
--target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
++void helper_wrs_nto(CPURISCVState *env)
--        target_ulong csr)
++{
-+target_ulong helper_csrr(CPURISCVState *env, int csr)
++    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
 +        get_field(env->hstatus, HSTATUS_VTW) &&
 +        !get_field(env->mstatus, MSTATUS_TW)) {
 +        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
 +    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
 +        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    }
 +}
 +
  void helper_tlb_flush(CPURISCVState *env)
  {
-     target_ulong val = 0;
+     CPUState *cs = env_cpu(env);
--    RISCVException ret = riscv_csrrw(env, csr, &val, src, -1);
+diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
-+    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
-     if (ret != RISCV_EXCP_NONE) {
++++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
-         riscv_raise_exception(env, ret, GETPC());
+@@ -XXX,XX +XXX,XX @@
-@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
+  * this program.  If not, see <http://www.gnu.org/licenses/>.
-     return val;
+  */
- }
+-static bool trans_wrs(DisasContext *ctx)
--target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
++static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
 -        target_ulong csr, target_ulong rs1_pass)
 +void helper_csrw(CPURISCVState *env, int csr, target_ulong src)
  {
--    target_ulong val = 0;
+     if (!ctx->cfg_ptr->ext_zawrs) {
--    RISCVException ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
+         return false;
-+    RISCVException ret = riscv_csrrw(env, csr, NULL, src, -1);
+@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
      if (ret != RISCV_EXCP_NONE) {
          riscv_raise_exception(env, ret, GETPC());
      }
 -    return val;
  }
 -target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
 -        target_ulong csr, target_ulong rs1_pass)
 +target_ulong helper_csrrw(CPURISCVState *env, int csr,
 +                          target_ulong src, target_ulong write_mask)
  {
      target_ulong val = 0;
 -    RISCVException ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
 +    RISCVException ret = riscv_csrrw(env, csr, &val, src, write_mask);
      if (ret != RISCV_EXCP_NONE) {
          riscv_raise_exception(env, ret, GETPC());
 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvi.c.inc
 +++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
      return true;
  }
--#define RISCV_OP_CSR_PRE do {\
+-#define GEN_TRANS_WRS(insn)                                     \
--    source1 = tcg_temp_new(); \
+-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
--    csr_store = tcg_temp_new(); \
+-{                                                               \
--    dest = tcg_temp_new(); \
+-    (void)a;                                                    \
--    rs1_pass = tcg_temp_new(); \
+-    return trans_wrs(ctx);                                      \
--    gen_get_gpr(ctx, source1, a->rs1); \
+-}
--    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
++static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
 -    tcg_gen_movi_tl(rs1_pass, a->rs1); \
 -    tcg_gen_movi_tl(csr_store, a->csr); \
 -    gen_io_start();\
 -} while (0)
 -
 -#define RISCV_OP_CSR_POST do {\
 -    gen_set_gpr(ctx, a->rd, dest); \
 -    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
 -    exit_tb(ctx); \
 -    ctx->base.is_jmp = DISAS_NORETURN; \
 -    tcg_temp_free(source1); \
 -    tcg_temp_free(csr_store); \
 -    tcg_temp_free(dest); \
 -    tcg_temp_free(rs1_pass); \
 -} while (0)
 +static bool do_csr_post(DisasContext *ctx)
 +{
-+    /* We may have changed important cpu state -- exit to main loop. */
++    if (!ctx->cfg_ptr->ext_zawrs) {
-+    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
++        return false;
-+    exit_tb(ctx);
++    }
-+    ctx->base.is_jmp = DISAS_NORETURN;
-+    return true;
+-GEN_TRANS_WRS(wrs_nto)
 -GEN_TRANS_WRS(wrs_sto)
 +    /*
 +     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
 +     * should raise an exception when the implementation-specific bounded time
 +     * limit has expired. Our time limit is zero, so we either return
 +     * immediately, as does our implementation of wrs.sto, or raise an
 +     * exception, as handled by the wrs.nto helper.
 +     */
 +#ifndef CONFIG_USER_ONLY
 +    gen_helper_wrs_nto(tcg_env);
 +#endif
 +
 +    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
 +    return trans_wrs_sto(ctx, NULL);
 +}
-+
-+static bool do_csrr(DisasContext *ctx, int rd, int rc)
-+{
-+    TCGv dest = dest_gpr(ctx, rd);
-+    TCGv_i32 csr = tcg_constant_i32(rc);
-+
-+    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
-+        gen_io_start();
-+    }
-+    gen_helper_csrr(dest, cpu_env, csr);
-+    gen_set_gpr(ctx, rd, dest);
-+    return do_csr_post(ctx);
-+}
-+
-+static bool do_csrw(DisasContext *ctx, int rc, TCGv src)
-+{
-+    TCGv_i32 csr = tcg_constant_i32(rc);
-+    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
-+        gen_io_start();
-+    }
-+    gen_helper_csrw(cpu_env, csr, src);
-+    return do_csr_post(ctx);
-+}
-+
-+static bool do_csrrw(DisasContext *ctx, int rd, int rc, TCGv src, TCGv mask)
-+{
-+    TCGv dest = dest_gpr(ctx, rd);
-+    TCGv_i32 csr = tcg_constant_i32(rc);
-+
-+    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
-+        gen_io_start();
-+    }
-+    gen_helper_csrrw(dest, cpu_env, csr, src, mask);
-+    gen_set_gpr(ctx, rd, dest);
-+    return do_csr_post(ctx);
-+}
- static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
- {
--    TCGv source1, csr_store, dest, rs1_pass;
--    RISCV_OP_CSR_PRE;
--    gen_helper_csrrw(dest, cpu_env, source1, csr_store);
--    RISCV_OP_CSR_POST;
--    return true;
-+    TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
-+
-+    /*
-+     * If rd == 0, the insn shall not read the csr, nor cause any of the
-+     * side effects that might occur on a csr read.
-+     */
-+    if (a->rd == 0) {
-+        return do_csrw(ctx, a->csr, src);
-+    }
-+
-+    TCGv mask = tcg_constant_tl(-1);
-+    return do_csrrw(ctx, a->rd, a->csr, src, mask);
- }
- static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
- {
--    TCGv source1, csr_store, dest, rs1_pass;
--    RISCV_OP_CSR_PRE;
--    gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
--    RISCV_OP_CSR_POST;
--    return true;
-+    /*
-+     * If rs1 == 0, the insn shall not write to the csr at all, nor
-+     * cause any of the side effects that might occur on a csr write.
-+     * Note that if rs1 specifies a register other than x0, holding
-+     * a zero value, the instruction will still attempt to write the
-+     * unmodified value back to the csr and will cause side effects.
-+     */
-+    if (a->rs1 == 0) {
-+        return do_csrr(ctx, a->rd, a->csr);
-+    }
-+
-+    TCGv ones = tcg_constant_tl(-1);
-+    TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
-+    return do_csrrw(ctx, a->rd, a->csr, ones, mask);
- }
- static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
- {
--    TCGv source1, csr_store, dest, rs1_pass;
--    RISCV_OP_CSR_PRE;
--    gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
--    RISCV_OP_CSR_POST;
--    return true;
-+    /*
-+     * If rs1 == 0, the insn shall not write to the csr at all, nor
-+     * cause any of the side effects that might occur on a csr write.
-+     * Note that if rs1 specifies a register other than x0, holding
-+     * a zero value, the instruction will still attempt to write the
-+     * unmodified value back to the csr and will cause side effects.
-+     */
-+    if (a->rs1 == 0) {
-+        return do_csrr(ctx, a->rd, a->csr);
-+    }
-+
-+    TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
-+    return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
- }
- static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
- {
--    TCGv source1, csr_store, dest, rs1_pass;
--    RISCV_OP_CSR_PRE;
--    gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
--    RISCV_OP_CSR_POST;
--    return true;
-+    TCGv src = tcg_constant_tl(a->rs1);
-+
-+    /*
-+     * If rd == 0, the insn shall not read the csr, nor cause any of the
-+     * side effects that might occur on a csr read.
-+     */
-+    if (a->rd == 0) {
-+        return do_csrw(ctx, a->csr, src);
-+    }
-+
-+    TCGv mask = tcg_constant_tl(-1);
-+    return do_csrrw(ctx, a->rd, a->csr, src, mask);
- }
- static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
- {
--    TCGv source1, csr_store, dest, rs1_pass;
--    RISCV_OP_CSR_PRE;
--    gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
--    RISCV_OP_CSR_POST;
--    return true;
-+    /*
-+     * If rs1 == 0, the insn shall not write to the csr at all, nor
-+     * cause any of the side effects that might occur on a csr write.
-+     * Note that if rs1 specifies a register other than x0, holding
-+     * a zero value, the instruction will still attempt to write the
-+     * unmodified value back to the csr and will cause side effects.
-+     */
-+    if (a->rs1 == 0) {
-+        return do_csrr(ctx, a->rd, a->csr);
-+    }
-+
-+    TCGv ones = tcg_constant_tl(-1);
-+    TCGv mask = tcg_constant_tl(a->rs1);
-+    return do_csrrw(ctx, a->rd, a->csr, ones, mask);
- }
- static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
- {
--    TCGv source1, csr_store, dest, rs1_pass;
--    RISCV_OP_CSR_PRE;
--    gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
--    RISCV_OP_CSR_POST;
--    return true;
-+    /*
-+     * If rs1 == 0, the insn shall not write to the csr at all, nor
-+     * cause any of the side effects that might occur on a csr write.
-+     * Note that if rs1 specifies a register other than x0, holding
-+     * a zero value, the instruction will still attempt to write the
-+     * unmodified value back to the csr and will cause side effects.
-+     */
-+    if (a->rs1 == 0) {
-+        return do_csrr(ctx, a->rd, a->csr);
-+    }
-+
-+    TCGv mask = tcg_constant_tl(a->rs1);
-+    return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
- }
 --
-.31.1
+.45.1

-[PULL 21/33] target/riscv: Use DisasExtend in shift operations
+[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-These operations are greatly simplified by ctx->w, which allows
+SBI defines a Debug Console extension "DBCN" that will, in time, replace
-us to fold gen_shiftw into gen_shift.  Split gen_shifti into
+the legacy console putchar and getchar SBI extensions.
-gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}.
+The appeal of the DBCN extension is that it allows multiple bytes to be
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+read/written in the SBI console in a single SBI call.
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
-Message-id: 20210823195529.560295-13-richard.henderson@linaro.org
+module to userspace. But this will only happens if the KVM module
 actually supports this SBI extension and we activate it.
 We'll check for DBCN support during init time, checking if get-reg-list
 is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
 kvm_set_one_reg() during kvm_arch_init_vcpu().
 Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
 SBI_EXT_DBCN, reading and writing as required.
 A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
 host, takes around 20 seconds to boot without using DBCN. With this
 patch we're taking around 14 seconds to boot due to the speed-up in the
 terminal output.  There's no change in boot time if the guest isn't
 using earlycon.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                | 110 +++++++++-----------
+ target/riscv/sbi_ecall_interface.h |  17 +++++
- target/riscv/insn_trans/trans_rvb.c.inc | 129 +++++++++++-------------
+ target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
- target/riscv/insn_trans/trans_rvi.c.inc |  88 ++++------------
+files changed, 128 insertions(+)
-files changed, 125 insertions(+), 202 deletions(-)
+diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/sbi_ecall_interface.h
-+++ b/target/riscv/translate.c
++++ b/target/riscv/sbi_ecall_interface.h
-@@ -XXX,XX +XXX,XX @@ static inline bool is_32bit(DisasContext *ctx)
+@@ -XXX,XX +XXX,XX @@
- }
- #endif
+ /* clang-format off */
-+/* The word size for this operation. */
++#define SBI_SUCCESS                      0
-+static inline int oper_len(DisasContext *ctx)
++#define SBI_ERR_FAILED                  -1
 +#define SBI_ERR_NOT_SUPPORTED           -2
 +#define SBI_ERR_INVALID_PARAM           -3
 +#define SBI_ERR_DENIED                  -4
 +#define SBI_ERR_INVALID_ADDRESS         -5
 +#define SBI_ERR_ALREADY_AVAILABLE       -6
 +#define SBI_ERR_ALREADY_STARTED         -7
 +#define SBI_ERR_ALREADY_STOPPED         -8
 +#define SBI_ERR_NO_SHMEM                -9
 +
  /* SBI Extension IDs */
  #define SBI_EXT_0_1_SET_TIMER           0x0
  #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
  #define SBI_EXT_IPI                     0x735049
  #define SBI_EXT_RFENCE                  0x52464E43
  #define SBI_EXT_HSM                     0x48534D
 +#define SBI_EXT_DBCN                    0x4442434E
  /* SBI function IDs for BASE extension */
  #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
  #define SBI_EXT_HSM_HART_STOP           0x1
  #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 +/* SBI function IDs for DBCN extension */
 +#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
 +#define SBI_EXT_DBCN_CONSOLE_READ       0x1
 +#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
 +
  #define SBI_HSM_HART_STATUS_STARTED     0x0
  #define SBI_HSM_HART_STATUS_STOPPED     0x1
  #define SBI_HSM_HART_STATUS_START_PENDING   0x2
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                     KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
  };
 +static KVMCPUConfig kvm_sbi_dbcn = {
 +    .name = "sbi_dbcn",
 +    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
 +                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
 +};
 +
  static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
  {
      CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
      return 0;
  }
 +static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
 +                                             KVMScratchCPU *kvmcpu,
 +                                             struct kvm_reg_list *reglist)
 +{
-+    return ctx->w ? 32 : TARGET_LONG_BITS;
++    struct kvm_reg_list *reg_search;
 +
 +    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
 +                         sizeof(uint64_t), uint64_cmp);
 +
 +    if (reg_search) {
 +        kvm_sbi_dbcn.supported = true;
 +    }
 +}
 +
-+
+ static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
- /*
+                                  struct kvm_reg_list *reglist)
-  * RISC-V requires NaN-boxing of narrower width floating point values.
+ {
-  * This applies when a 32-bit value is assigned to a 64-bit FP register.
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
-@@ -XXX,XX +XXX,XX @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
+     if (riscv_has_ext(&cpu->env, RVV)) {
          kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
      }
 +
 +    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
  }
  static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
      return ret;
  }
 +static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
 +{
 +    target_ulong reg = 1;
 +
 +    if (!kvm_sbi_dbcn.supported) {
 +        return 0;
 +    }
 +
 +    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
 +}
 +
  int kvm_arch_init_vcpu(CPUState *cs)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
      kvm_riscv_update_cpu_misa_ext(cpu, cs);
      kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 +    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
 +
      return ret;
  }
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
      return true;
  }
--static bool gen_shift(DisasContext *ctx, arg_r *a,
++static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
--                        void(*func)(TCGv, TCGv, TCGv))
++{
--{
++    g_autofree uint8_t *buf = NULL;
--    TCGv source1 = tcg_temp_new();
++    RISCVCPU *cpu = RISCV_CPU(cs);
--    TCGv source2 = tcg_temp_new();
++    target_ulong num_bytes;
--
++    uint64_t addr;
--    gen_get_gpr(ctx, source1, a->rs1);
++    unsigned char ch;
--    gen_get_gpr(ctx, source2, a->rs2);
++    int ret;
--
++
--    tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
++    switch (run->riscv_sbi.function_id) {
--    (*func)(source1, source1, source2);
++    case SBI_EXT_DBCN_CONSOLE_READ:
--
++    case SBI_EXT_DBCN_CONSOLE_WRITE:
--    gen_set_gpr(ctx, a->rd, source1);
++        num_bytes = run->riscv_sbi.args[0];
--    tcg_temp_free(source1);
++
--    tcg_temp_free(source2);
++        if (num_bytes == 0) {
--    return true;
++            run->riscv_sbi.ret[0] = SBI_SUCCESS;
--}
++            run->riscv_sbi.ret[1] = 0;
--
++            break;
--static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
++        }
-+static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
++
-+                             void (*func)(TCGv, TCGv, target_long))
++        addr = run->riscv_sbi.args[1];
- {
++
--    DisasContext *ctx = container_of(dcbase, DisasContext, base);
++        /*
--    CPUState *cpu = ctx->cs;
++         * Handle the case where a 32 bit CPU is running in a
--    CPURISCVState *env = cpu->env_ptr;
++         * 64 bit addressing env.
-+    TCGv dest, src1;
++         */
-+    int max_len = oper_len(ctx);
++        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
++            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
--    return cpu_ldl_code(env, pc);
++        }
--}
++
--
++        buf = g_malloc0(num_bytes);
--static bool gen_shifti(DisasContext *ctx, arg_shift *a,
++
--                       void(*func)(TCGv, TCGv, TCGv))
++        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
--{
++            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
--    if (a->shamt >= TARGET_LONG_BITS) {
++            if (ret < 0) {
-+    if (a->shamt >= max_len) {
++                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
-         return false;
++                             "reading chardev");
-     }
++                exit(1);
++            }
--    TCGv source1 = tcg_temp_new();
++
--    TCGv source2 = tcg_temp_new();
++            cpu_physical_memory_write(addr, buf, ret);
--
++        } else {
--    gen_get_gpr(ctx, source1, a->rs1);
++            cpu_physical_memory_read(addr, buf, num_bytes);
-+    dest = dest_gpr(ctx, a->rd);
++
-+    src1 = get_gpr(ctx, a->rs1, ext);
++            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
++            if (ret < 0) {
--    tcg_gen_movi_tl(source2, a->shamt);
++                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
--    (*func)(source1, source1, source2);
++                             "writing chardev");
-+    func(dest, src1, a->shamt);
++                exit(1);
++            }
--    gen_set_gpr(ctx, a->rd, source1);
++        }
--    tcg_temp_free(source1);
++
--    tcg_temp_free(source2);
++        run->riscv_sbi.ret[0] = SBI_SUCCESS;
-+    gen_set_gpr(ctx, a->rd, dest);
++        run->riscv_sbi.ret[1] = ret;
-     return true;
++        break;
- }
++    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
++        ch = run->riscv_sbi.args[0];
--static bool gen_shiftw(DisasContext *ctx, arg_r *a,
++        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
--                       void(*func)(TCGv, TCGv, TCGv))
++
-+static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
++        if (ret < 0) {
-+                             void (*func)(TCGv, TCGv, TCGv))
++            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
- {
++                         "writing chardev");
--    TCGv source1 = tcg_temp_new();
++            exit(1);
--    TCGv source2 = tcg_temp_new();
++        }
-+    TCGv dest, src1, src2;
++
-+    int max_len = oper_len(ctx);
++        run->riscv_sbi.ret[0] = SBI_SUCCESS;
-+
++        run->riscv_sbi.ret[1] = 0;
-+    if (a->shamt >= max_len) {
++        break;
-+        return false;
++    default:
 +        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
 +    }
--    gen_get_gpr(ctx, source1, a->rs1);
--    gen_get_gpr(ctx, source2, a->rs2);
-+    dest = dest_gpr(ctx, a->rd);
-+    src1 = get_gpr(ctx, a->rs1, ext);
-+    src2 = tcg_constant_tl(a->shamt);
--    tcg_gen_andi_tl(source2, source2, 31);
--    (*func)(source1, source1, source2);
--    tcg_gen_ext32s_tl(source1, source1);
-+    func(dest, src1, src2);
--    gen_set_gpr(ctx, a->rd, source1);
--    tcg_temp_free(source1);
--    tcg_temp_free(source2);
-+    gen_set_gpr(ctx, a->rd, dest);
-     return true;
- }
--static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
--                        void(*func)(TCGv, TCGv, TCGv))
-+static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
-+                      void (*func)(TCGv, TCGv, TCGv))
- {
--    TCGv source1 = tcg_temp_new();
--    TCGv source2 = tcg_temp_new();
--
--    gen_get_gpr(ctx, source1, a->rs1);
--    tcg_gen_movi_tl(source2, a->shamt);
-+    TCGv dest = dest_gpr(ctx, a->rd);
-+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
-+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
-+    TCGv ext2 = tcg_temp_new();
--    (*func)(source1, source1, source2);
--    tcg_gen_ext32s_tl(source1, source1);
-+    tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
-+    func(dest, src1, ext2);
--    gen_set_gpr(ctx, a->rd, source1);
--    tcg_temp_free(source1);
--    tcg_temp_free(source2);
-+    gen_set_gpr(ctx, a->rd, dest);
-+    tcg_temp_free(ext2);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
-     return true;
- }
-+static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
-+{
-+    DisasContext *ctx = container_of(dcbase, DisasContext, base);
-+    CPUState *cpu = ctx->cs;
-+    CPURISCVState *env = cpu->env_ptr;
-+
-+    return cpu_ldl_code(env, pc);
 +}
 +
- /* Include insn module translation function */
+ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
- #include "insn_trans/trans_rvi.c.inc"
+ {
- #include "insn_trans/trans_rvm.c.inc"
+     int ret = 0;
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
-index XXXXXXX..XXXXXXX 100644
+         }
---- a/target/riscv/insn_trans/trans_rvb.c.inc
+         ret = 0;
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
+         break;
-@@ -XXX,XX +XXX,XX @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
++    case SBI_EXT_DBCN:
- static bool trans_bset(DisasContext *ctx, arg_bset *a)
++        kvm_riscv_handle_sbi_dbcn(cs, run);
- {
++        break;
-     REQUIRE_EXT(ctx, RVB);
+     default:
--    return gen_shift(ctx, a, gen_bset);
+         qemu_log_mask(LOG_UNIMP,
-+    return gen_shift(ctx, a, EXT_NONE, gen_bset);
+                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
  }
  static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shifti(ctx, a, gen_bset);
 +    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
  }
  static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
@@ -XXX,XX +XXX,XX @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
  static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shift(ctx, a, gen_bclr);
 +    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
  }
  static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shifti(ctx, a, gen_bclr);
 +    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
  }
  static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
@@ -XXX,XX +XXX,XX @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
  static bool trans_binv(DisasContext *ctx, arg_binv *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shift(ctx, a, gen_binv);
 +    return gen_shift(ctx, a, EXT_NONE, gen_binv);
  }
  static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shifti(ctx, a, gen_binv);
 +    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
  }
  static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
@@ -XXX,XX +XXX,XX @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
  static bool trans_bext(DisasContext *ctx, arg_bext *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shift(ctx, a, gen_bext);
 +    return gen_shift(ctx, a, EXT_NONE, gen_bext);
  }
  static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shifti(ctx, a, gen_bext);
 +    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
  }
  static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
@@ -XXX,XX +XXX,XX @@ static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
  static bool trans_slo(DisasContext *ctx, arg_slo *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shift(ctx, a, gen_slo);
 +    return gen_shift(ctx, a, EXT_NONE, gen_slo);
  }
  static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shifti(ctx, a, gen_slo);
 +    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
  }
  static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
@@ -XXX,XX +XXX,XX @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
  static bool trans_sro(DisasContext *ctx, arg_sro *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shift(ctx, a, gen_sro);
 +    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
  }
  static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shifti(ctx, a, gen_sro);
 +    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
  }
  static bool trans_ror(DisasContext *ctx, arg_ror *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shift(ctx, a, tcg_gen_rotr_tl);
 +    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
  }
  static bool trans_rori(DisasContext *ctx, arg_rori *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shifti(ctx, a, tcg_gen_rotr_tl);
 +    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
  }
  static bool trans_rol(DisasContext *ctx, arg_rol *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shift(ctx, a, tcg_gen_rotl_tl);
 +    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
  }
  static bool trans_grev(DisasContext *ctx, arg_grev *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shift(ctx, a, gen_helper_grev);
 +    return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
  }
 -static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
 +static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
  {
 -    TCGv source1 = tcg_temp_new();
 -    TCGv source2;
 -
 -    gen_get_gpr(ctx, source1, a->rs1);
 -
 -    if (a->shamt == (TARGET_LONG_BITS - 8)) {
 +    if (shamt == TARGET_LONG_BITS - 8) {
          /* rev8, byte swaps */
 -        tcg_gen_bswap_tl(source1, source1);
 +        tcg_gen_bswap_tl(dest, src);
      } else {
 -        source2 = tcg_temp_new();
 -        tcg_gen_movi_tl(source2, a->shamt);
 -        gen_helper_grev(source1, source1, source2);
 -        tcg_temp_free(source2);
 +        gen_helper_grev(dest, src, tcg_constant_tl(shamt));
      }
 -
 -    gen_set_gpr(ctx, a->rd, source1);
 -    tcg_temp_free(source1);
 -    return true;
  }
  static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -
 -    if (a->shamt >= TARGET_LONG_BITS) {
 -        return false;
 -    }
 -
 -    return gen_grevi(ctx, a);
 +    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
  }
  static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shift(ctx, a, gen_helper_gorc);
 +    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
  }
  static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shifti(ctx, a, gen_helper_gorc);
 +    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
  }
  #define GEN_SHADD(SHAMT)                                       \
@@ -XXX,XX +XXX,XX @@ static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftw(ctx, a, gen_bset);
 +    ctx->w = true;
 +    return gen_shift(ctx, a, EXT_NONE, gen_bset);
  }
  static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftiw(ctx, a, gen_bset);
 +    ctx->w = true;
 +    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
  }
  static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftw(ctx, a, gen_bclr);
 +    ctx->w = true;
 +    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
  }
  static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftiw(ctx, a, gen_bclr);
 +    ctx->w = true;
 +    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
  }
  static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftw(ctx, a, gen_binv);
 +    ctx->w = true;
 +    return gen_shift(ctx, a, EXT_NONE, gen_binv);
  }
  static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftiw(ctx, a, gen_binv);
 +    ctx->w = true;
 +    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
  }
  static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftw(ctx, a, gen_bext);
 +    ctx->w = true;
 +    return gen_shift(ctx, a, EXT_NONE, gen_bext);
  }
  static bool trans_slow(DisasContext *ctx, arg_slow *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftw(ctx, a, gen_slo);
 +    ctx->w = true;
 +    return gen_shift(ctx, a, EXT_NONE, gen_slo);
  }
  static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftiw(ctx, a, gen_slo);
 +    ctx->w = true;
 +    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
  }
  static bool trans_srow(DisasContext *ctx, arg_srow *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftw(ctx, a, gen_sro);
 +    ctx->w = true;
 +    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
  }
  static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftiw(ctx, a, gen_sro);
 +    ctx->w = true;
 +    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
  }
  static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
@@ -XXX,XX +XXX,XX @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftw(ctx, a, gen_rorw);
 +    ctx->w = true;
 +    return gen_shift(ctx, a, EXT_NONE, gen_rorw);
  }
  static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftiw(ctx, a, gen_rorw);
 +    ctx->w = true;
 +    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
  }
  static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftw(ctx, a, gen_rolw);
 -}
 -
 -static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    tcg_gen_ext32u_tl(arg1, arg1);
 -    gen_helper_grev(ret, arg1, arg2);
 +    ctx->w = true;
 +    return gen_shift(ctx, a, EXT_NONE, gen_rolw);
  }
  static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftw(ctx, a, gen_grevw);
 +    ctx->w = true;
 +    return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
  }
  static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftiw(ctx, a, gen_grevw);
 -}
 -
 -static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    tcg_gen_ext32u_tl(arg1, arg1);
 -    gen_helper_gorcw(ret, arg1, arg2);
 +    ctx->w = true;
 +    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
  }
  static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftw(ctx, a, gen_gorcw);
 +    ctx->w = true;
 +    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
  }
  static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_shiftiw(ctx, a, gen_gorcw);
 +    ctx->w = true;
 +    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
  }
  #define GEN_SHADD_UW(SHAMT)                                       \
 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvi.c.inc
 +++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
  static bool trans_slli(DisasContext *ctx, arg_slli *a)
  {
 -    return gen_shifti(ctx, a, tcg_gen_shl_tl);
 +    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
  }
  static bool trans_srli(DisasContext *ctx, arg_srli *a)
  {
 -    return gen_shifti(ctx, a, tcg_gen_shr_tl);
 +    return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
  }
  static bool trans_srai(DisasContext *ctx, arg_srai *a)
  {
 -    return gen_shifti(ctx, a, tcg_gen_sar_tl);
 +    return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
  }
  static bool trans_add(DisasContext *ctx, arg_add *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_sub(DisasContext *ctx, arg_sub *a)
  static bool trans_sll(DisasContext *ctx, arg_sll *a)
  {
 -    return gen_shift(ctx, a, &tcg_gen_shl_tl);
 +    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
  }
  static bool trans_slt(DisasContext *ctx, arg_slt *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_xor(DisasContext *ctx, arg_xor *a)
  static bool trans_srl(DisasContext *ctx, arg_srl *a)
  {
 -    return gen_shift(ctx, a, &tcg_gen_shr_tl);
 +    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
  }
  static bool trans_sra(DisasContext *ctx, arg_sra *a)
  {
 -    return gen_shift(ctx, a, &tcg_gen_sar_tl);
 +    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
  }
  static bool trans_or(DisasContext *ctx, arg_or *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
  static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
  {
      REQUIRE_64BIT(ctx);
 -    return gen_shiftiw(ctx, a, tcg_gen_shl_tl);
 +    ctx->w = true;
 +    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
  }
  static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
  {
      REQUIRE_64BIT(ctx);
 -    TCGv t = tcg_temp_new();
 -    gen_get_gpr(ctx, t, a->rs1);
 -    tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
 -    /* sign-extend for W instructions */
 -    tcg_gen_ext32s_tl(t, t);
 -    gen_set_gpr(ctx, a->rd, t);
 -    tcg_temp_free(t);
 -    return true;
 +    ctx->w = true;
 +    return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
  }
  static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
  {
      REQUIRE_64BIT(ctx);
 -    TCGv t = tcg_temp_new();
 -    gen_get_gpr(ctx, t, a->rs1);
 -    tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
 -    gen_set_gpr(ctx, a->rd, t);
 -    tcg_temp_free(t);
 -    return true;
 +    ctx->w = true;
 +    return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
  }
  static bool trans_addw(DisasContext *ctx, arg_addw *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_subw(DisasContext *ctx, arg_subw *a)
  static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
  {
      REQUIRE_64BIT(ctx);
 -    TCGv source1 = tcg_temp_new();
 -    TCGv source2 = tcg_temp_new();
 -
 -    gen_get_gpr(ctx, source1, a->rs1);
 -    gen_get_gpr(ctx, source2, a->rs2);
 -
 -    tcg_gen_andi_tl(source2, source2, 0x1F);
 -    tcg_gen_shl_tl(source1, source1, source2);
 -
 -    tcg_gen_ext32s_tl(source1, source1);
 -    gen_set_gpr(ctx, a->rd, source1);
 -    tcg_temp_free(source1);
 -    tcg_temp_free(source2);
 -    return true;
 +    ctx->w = true;
 +    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
  }
  static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
  {
      REQUIRE_64BIT(ctx);
 -    TCGv source1 = tcg_temp_new();
 -    TCGv source2 = tcg_temp_new();
 -
 -    gen_get_gpr(ctx, source1, a->rs1);
 -    gen_get_gpr(ctx, source2, a->rs2);
 -
 -    /* clear upper 32 */
 -    tcg_gen_ext32u_tl(source1, source1);
 -    tcg_gen_andi_tl(source2, source2, 0x1F);
 -    tcg_gen_shr_tl(source1, source1, source2);
 -
 -    tcg_gen_ext32s_tl(source1, source1);
 -    gen_set_gpr(ctx, a->rd, source1);
 -    tcg_temp_free(source1);
 -    tcg_temp_free(source2);
 -    return true;
 +    ctx->w = true;
 +    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
  }
  static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
  {
      REQUIRE_64BIT(ctx);
 -    TCGv source1 = tcg_temp_new();
 -    TCGv source2 = tcg_temp_new();
 -
 -    gen_get_gpr(ctx, source1, a->rs1);
 -    gen_get_gpr(ctx, source2, a->rs2);
 -
 -    /*
 -     * first, trick to get it to act like working on 32 bits (get rid of
 -     * upper 32, sign extend to fill space)
 -     */
 -    tcg_gen_ext32s_tl(source1, source1);
 -    tcg_gen_andi_tl(source2, source2, 0x1F);
 -    tcg_gen_sar_tl(source1, source1, source2);
 -
 -    gen_set_gpr(ctx, a->rd, source1);
 -    tcg_temp_free(source1);
 -    tcg_temp_free(source2);
 -
 -    return true;
 +    ctx->w = true;
 +    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
  }
  static bool trans_fence(DisasContext *ctx, arg_fence *a)
 --
-.31.1
+.45.1

-[PULL 07/33] hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp()
+[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
-From: David Hoppenbrouwers <david@salt-inc.org>
+From: Cheng Yang <yangcheng.work@foxmail.com>
-`muldiv64` would overflow in cases where the final 96-bit value does not
+Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
-fit in a `uint64_t`. This would result in small values that cause an
+to set the address of initrd in FDT to support 64-bit address.
 interrupt to be triggered much sooner than intended.
-The overflow can be detected in most cases by checking if the new value is
+Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
 smaller than the previous value. If the final result is larger than
 `diff` it is either correct or it doesn't matter as it is effectively
 infinite anyways.
 `next` is an `uint64_t` value, but `timer_mod` takes an `int64_t`. This
 resulted in high values such as `UINT64_MAX` being converted to `-1`,
 which caused an immediate timer interrupt.
 By limiting `next` to `INT64_MAX` no overflow will happen while the
 timer will still be effectively set to "infinitely" far in the future.
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/493
 Signed-off-by: David Hoppenbrouwers <david@salt-inc.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210827152324.5201-1-david@salt-inc.org
+Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/intc/sifive_clint.c | 25 +++++++++++++++++++++++--
+ hw/riscv/boot.c | 4 ++--
-file changed, 23 insertions(+), 2 deletions(-)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/intc/sifive_clint.c b/hw/intc/sifive_clint.c
+diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/sifive_clint.c
+--- a/hw/riscv/boot.c
-+++ b/hw/intc/sifive_clint.c
++++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value,
+@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
-     riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
+     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
-     diff = cpu->env.timecmp - rtc_r;
+     if (fdt) {
-     /* back to ns (note args switched in muldiv64) */
+         end = start + size;
--    next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
--        muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
-+    uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
-+
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
-+    /*
+     }
 +     * check if ns_diff overflowed and check if the addition would potentially
 +     * overflow
 +     */
 +    if ((NANOSECONDS_PER_SECOND > timebase_freq && ns_diff < diff) ||
 +        ns_diff > INT64_MAX) {
 +        next = INT64_MAX;
 +    } else {
 +        /*
 +         * as it is very unlikely qemu_clock_get_ns will return a value
 +         * greater than INT64_MAX, no additional check is needed for an
 +         * unsigned integer overflow.
 +         */
 +        next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns_diff;
 +        /*
 +         * if ns_diff is INT64_MAX next may still be outside the range
 +         * of a signed integer.
 +         */
 +        next = MIN(next, INT64_MAX);
 +    }
 +
      timer_mod(cpu->env.timer, next);
  }
 --
-.31.1
+.45.1

-[PULL 20/33] target/riscv: Add DisasExtend to gen_unary
+[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Clément Léger <cleger@rivosinc.com>
-Use ctx->w for ctpopw, which is the only one that can
+The current semihost exception number (16) is a reserved number (range
-re-use the generic algorithm for the narrow operation.
+[16-17]). The upcoming double trap specification uses that number for
 the double trap exception. Since the privileged spec (Table 22) defines
 ranges for custom uses change the semihosting exception number to 63
 which belongs to the range [48-63] in order to avoid any future
 collisions with reserved exception.
 Signed-off-by: Clément Léger <cleger@rivosinc.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
 Message-id: 20210823195529.560295-12-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                | 14 ++++++--------
+ target/riscv/cpu_bits.h | 2 +-
- target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++---------------
+file changed, 1 insertion(+), 1 deletion(-)
 files changed, 15 insertions(+), 23 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/cpu_bits.h
-+++ b/target/riscv/translate.c
++++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@ static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
+@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
-     return true;
+     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
- }
+     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
+     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
--static bool gen_unary(DisasContext *ctx, arg_r2 *a,
+-    RISCV_EXCP_SEMIHOST = 0x10,
--                      void(*func)(TCGv, TCGv))
+     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
-+static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
+     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
-+                      void (*func)(TCGv, TCGv))
+     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
- {
+     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
--    TCGv source = tcg_temp_new();
++    RISCV_EXCP_SEMIHOST = 0x3f,
--
+ } RISCVException;
--    gen_get_gpr(ctx, source, a->rs1);
-+    TCGv dest = dest_gpr(ctx, a->rd);
+ #define RISCV_EXCP_INT_FLAG                0x80000000
 +    TCGv src1 = get_gpr(ctx, a->rs1, ext);
 -    (*func)(source, source);
 +    func(dest, src1);
 -    gen_set_gpr(ctx, a->rd, source);
 -    tcg_temp_free(source);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static void gen_clz(TCGv ret, TCGv arg1)
  static bool trans_clz(DisasContext *ctx, arg_clz *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_unary(ctx, a, gen_clz);
 +    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
  }
  static void gen_ctz(TCGv ret, TCGv arg1)
@@ -XXX,XX +XXX,XX @@ static void gen_ctz(TCGv ret, TCGv arg1)
  static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_unary(ctx, a, gen_ctz);
 +    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
  }
  static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_unary(ctx, a, tcg_gen_ctpop_tl);
 +    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
  }
  static bool trans_andn(DisasContext *ctx, arg_andn *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
  static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_unary(ctx, a, tcg_gen_ext8s_tl);
 +    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
  }
  static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
  {
      REQUIRE_EXT(ctx, RVB);
 -    return gen_unary(ctx, a, tcg_gen_ext16s_tl);
 +    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
  }
  static void gen_sbop_mask(TCGv ret, TCGv shamt)
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(3)
  static void gen_clzw(TCGv ret, TCGv arg1)
  {
 -    tcg_gen_ext32u_tl(ret, arg1);
      tcg_gen_clzi_tl(ret, ret, 64);
      tcg_gen_subi_tl(ret, ret, 32);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_unary(ctx, a, gen_clzw);
 +    return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
  }
  static void gen_ctzw(TCGv ret, TCGv arg1)
@@ -XXX,XX +XXX,XX @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_unary(ctx, a, gen_ctzw);
 -}
 -
 -static void gen_cpopw(TCGv ret, TCGv arg1)
 -{
 -    tcg_gen_ext32u_tl(arg1, arg1);
 -    tcg_gen_ctpop_tl(ret, arg1);
 +    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
  }
  static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVB);
 -    return gen_unary(ctx, a, gen_cpopw);
 +    ctx->w = true;
 +    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
  }
  static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
 --
-.31.1
+.45.1

-[PULL 29/33] target/riscv: Use gen_shift_imm_fn for slli_uw
+[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Always use tcg_gen_deposit_z_tl; the special case for
+Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
-shamt >= 32 is handled there.
+enabled, will fail with a kernel oops SIGILL right at the start. The
 reason is that we can't expose zkr without implementing the SEED CSR.
 Disabling zkr in the guest would be a workaround, but if the KVM doesn't
 allow it we'll error out and never boot.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+In hindsight this is too strict. If we keep proceeding, despite not
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+disabling the extension in the KVM vcpu, we'll not add the extension in
-Message-id: 20210823195529.560295-21-richard.henderson@linaro.org
+the riscv,isa. The guest kernel will be unaware of the extension, i.e.
 it doesn't matter if the KVM vcpu has it enabled underneath or not. So
 it's ok to keep booting in this case.
 Change our current logic to not error out if we fail to disable an
 extension in kvm_set_one_reg(), but show a warning and keep booting. It
 is important to throw a warning because we must make the user aware that
 the extension is still available in the vcpu, meaning that an
 ill-behaved guest can ignore the riscv,isa settings and  use the
 extension.
 The case we're handling happens with an EINVAL error code. If we fail to
 disable the extension in KVM for any other reason, error out.
 We'll also keep erroring out when we fail to enable an extension in KVM,
 since adding the extension in riscv,isa at this point will cause a guest
 malfunction because the extension isn't enabled in the vcpu.
 Suggested-by: Andrew Jones <ajones@ventanamicro.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvb.c.inc | 19 ++++++-------------
+ target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
-file changed, 6 insertions(+), 13 deletions(-)
+file changed, 8 insertions(+), 4 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
-     return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
+         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
- }
+         ret = kvm_set_one_reg(cs, id, &reg);
+         if (ret != 0) {
-+static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
+-            error_report("Unable to %s extension %s in KVM, error %d",
-+{
+-                         reg ? "enable" : "disable",
-+    tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
+-                         multi_ext_cfg->name, ret);
-+}
+-            exit(EXIT_FAILURE);
-+
++            if (!reg && ret == -EINVAL) {
- static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
++                warn_report("KVM cannot disable extension %s",
- {
++                            multi_ext_cfg->name);
-     REQUIRE_64BIT(ctx);
++            } else {
-     REQUIRE_EXT(ctx, RVB);
++                error_report("Unable to enable extension %s in KVM, error %d",
--
++                             multi_ext_cfg->name, ret);
--    TCGv source1 = tcg_temp_new();
++                exit(EXIT_FAILURE);
--    gen_get_gpr(ctx, source1, a->rs1);
++            }
--
+         }
--    if (a->shamt < 32) {
+     }
 -        tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
 -    } else {
 -        tcg_gen_shli_tl(source1, source1, a->shamt);
 -    }
 -
 -    gen_set_gpr(ctx, a->rd, source1);
 -    tcg_temp_free(source1);
 -    return true;
 +    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
  }
 --
-.31.1
+.45.1

-[PULL 32/33] target/riscv: Tidy trans_rvh.c.inc
+[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Exit early if check_access fails.
+We're not setting (s/m)tval when triggering breakpoints of type 2
-Split out do_hlv, do_hsv, do_hlvx subroutines.
+(mcontrol) and 6 (mcontrol6). According to the debug spec section
-Use dest_gpr, get_gpr in the new subroutines.
+.7.12, "Match Control Type 6":
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+"The Privileged Spec says that breakpoint exceptions that occur on
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+instruction fetches, loads, or stores update the tval CSR with either
 zero or the faulting virtual address. The faulting virtual address for
 an mcontrol6 trigger with action = 0 is the address being accessed and
 which caused that trigger to fire."
 A similar text is also found in the Debug spec section 5.7.11 w.r.t.
 mcontrol.
 Note that what we're doing ATM is not violating the spec, but it's
 simple enough to set mtval/stval and it makes life easier for any
 software that relies on this info.
 Given that we always use action = 0, save the faulting address for the
 mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
 used as as scratch area for traps with address information. 'tval' is
 then set during riscv_cpu_do_interrupt().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210823195529.560295-24-richard.henderson@linaro.org
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn32.decode              |   1 +
+ target/riscv/cpu_helper.c | 1 +
- target/riscv/insn_trans/trans_rvh.c.inc | 266 +++++-------------------
+ target/riscv/debug.c      | 3 +++
-files changed, 57 insertions(+), 210 deletions(-)
+files changed, 4 insertions(+)
-diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn32.decode
+--- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/insn32.decode
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
- &j    imm rd
+             tval = env->bins;
- &r    rd rs1 rs2
+             break;
- &r2   rd rs1
+         case RISCV_EXCP_BREAKPOINT:
-+&r2_s rs1 rs2
++            tval = env->badaddr;
- &s    imm rs1 rs2
+             if (cs->watchpoint_hit) {
- &u    imm rd
+                 tval = cs->watchpoint_hit->hitaddr;
- &shift     shamt rs1 rd
+                 cs->watchpoint_hit = NULL;
-diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
+diff --git a/target/riscv/debug.c b/target/riscv/debug.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvh.c.inc
+--- a/target/riscv/debug.c
-+++ b/target/riscv/insn_trans/trans_rvh.c.inc
++++ b/target/riscv/debug.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
-  */
+                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
+                     /* check U/S/M bit against current privilege level */
- #ifndef CONFIG_USER_ONLY
+                     if ((ctrl >> 3) & BIT(env->priv)) {
--static void check_access(DisasContext *ctx) {
++                        env->badaddr = pc;
-+static bool check_access(DisasContext *ctx)
+                         return true;
-+{
+                     }
-     if (!ctx->hlsx) {
+                 }
-         if (ctx->virt_enabled) {
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
-             generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
+                     if (env->virt_enabled) {
-         } else {
+                         /* check VU/VS bit against current privilege level */
-             generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
+                         if ((ctrl >> 23) & BIT(env->priv)) {
-         }
++                            env->badaddr = pc;
-+        return false;
+                             return true;
-     }
+                         }
-+    return true;
+                     } else {
- }
+                         /* check U/S/M bit against current privilege level */
- #endif
+                         if ((ctrl >> 3) & BIT(env->priv)) {
++                            env->badaddr = pc;
--static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
+                             return true;
-+static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop)
+                         }
- {
+                     }
 -    REQUIRE_EXT(ctx, RVH);
 -#ifndef CONFIG_USER_ONLY
 -    TCGv t0 = tcg_temp_new();
 -    TCGv t1 = tcg_temp_new();
 -
 -    check_access(ctx);
 -
 -    gen_get_gpr(ctx, t0, a->rs1);
 -
 -    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_SB);
 -    gen_set_gpr(ctx, a->rd, t1);
 -
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -    return true;
 -#else
 +#ifdef CONFIG_USER_ONLY
      return false;
 +#else
 +    if (check_access(ctx)) {
 +        TCGv dest = dest_gpr(ctx, a->rd);
 +        TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
 +        int mem_idx = ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
 +        tcg_gen_qemu_ld_tl(dest, addr, mem_idx, mop);
 +        gen_set_gpr(ctx, a->rd, dest);
 +    }
 +    return true;
  #endif
  }
 -static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
 +static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
  {
      REQUIRE_EXT(ctx, RVH);
 -#ifndef CONFIG_USER_ONLY
 -    TCGv t0 = tcg_temp_new();
 -    TCGv t1 = tcg_temp_new();
 -
 -    check_access(ctx);
 -
 -    gen_get_gpr(ctx, t0, a->rs1);
 -
 -    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESW);
 -    gen_set_gpr(ctx, a->rd, t1);
 +    return do_hlv(ctx, a, MO_SB);
 +}
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -    return true;
 -#else
 -    return false;
 -#endif
 +static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
 +{
 +    REQUIRE_EXT(ctx, RVH);
 +    return do_hlv(ctx, a, MO_TESW);
  }
  static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a)
  {
      REQUIRE_EXT(ctx, RVH);
 -#ifndef CONFIG_USER_ONLY
 -    TCGv t0 = tcg_temp_new();
 -    TCGv t1 = tcg_temp_new();
 -
 -    check_access(ctx);
 -
 -    gen_get_gpr(ctx, t0, a->rs1);
 -
 -    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESL);
 -    gen_set_gpr(ctx, a->rd, t1);
 -
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -    return true;
 -#else
 -    return false;
 -#endif
 +    return do_hlv(ctx, a, MO_TESL);
  }
  static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a)
  {
      REQUIRE_EXT(ctx, RVH);
 -#ifndef CONFIG_USER_ONLY
 -    TCGv t0 = tcg_temp_new();
 -    TCGv t1 = tcg_temp_new();
 -
 -    check_access(ctx);
 -
 -    gen_get_gpr(ctx, t0, a->rs1);
 -
 -    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_UB);
 -    gen_set_gpr(ctx, a->rd, t1);
 -
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -    return true;
 -#else
 -    return false;
 -#endif
 +    return do_hlv(ctx, a, MO_UB);
  }
  static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a)
  {
      REQUIRE_EXT(ctx, RVH);
 -#ifndef CONFIG_USER_ONLY
 -    TCGv t0 = tcg_temp_new();
 -    TCGv t1 = tcg_temp_new();
 -
 -    check_access(ctx);
 -
 -    gen_get_gpr(ctx, t0, a->rs1);
 -    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEUW);
 -    gen_set_gpr(ctx, a->rd, t1);
 +    return do_hlv(ctx, a, MO_TEUW);
 +}
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -    return true;
 -#else
 +static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop)
 +{
 +#ifdef CONFIG_USER_ONLY
      return false;
 +#else
 +    if (check_access(ctx)) {
 +        TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
 +        TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
 +        int mem_idx = ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
 +        tcg_gen_qemu_st_tl(data, addr, mem_idx, mop);
 +    }
 +    return true;
  #endif
  }
  static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a)
  {
      REQUIRE_EXT(ctx, RVH);
 -#ifndef CONFIG_USER_ONLY
 -    TCGv t0 = tcg_temp_new();
 -    TCGv dat = tcg_temp_new();
 -
 -    check_access(ctx);
 -
 -    gen_get_gpr(ctx, t0, a->rs1);
 -    gen_get_gpr(ctx, dat, a->rs2);
 -
 -    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_SB);
 -
 -    tcg_temp_free(t0);
 -    tcg_temp_free(dat);
 -    return true;
 -#else
 -    return false;
 -#endif
 +    return do_hsv(ctx, a, MO_SB);
  }
  static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a)
  {
      REQUIRE_EXT(ctx, RVH);
 -#ifndef CONFIG_USER_ONLY
 -    TCGv t0 = tcg_temp_new();
 -    TCGv dat = tcg_temp_new();
 -
 -    check_access(ctx);
 -
 -    gen_get_gpr(ctx, t0, a->rs1);
 -    gen_get_gpr(ctx, dat, a->rs2);
 -
 -    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESW);
 -
 -    tcg_temp_free(t0);
 -    tcg_temp_free(dat);
 -    return true;
 -#else
 -    return false;
 -#endif
 +    return do_hsv(ctx, a, MO_TESW);
  }
  static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
  {
      REQUIRE_EXT(ctx, RVH);
 -#ifndef CONFIG_USER_ONLY
 -    TCGv t0 = tcg_temp_new();
 -    TCGv dat = tcg_temp_new();
 -
 -    check_access(ctx);
 -
 -    gen_get_gpr(ctx, t0, a->rs1);
 -    gen_get_gpr(ctx, dat, a->rs2);
 -
 -    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESL);
 -
 -    tcg_temp_free(t0);
 -    tcg_temp_free(dat);
 -    return true;
 -#else
 -    return false;
 -#endif
 +    return do_hsv(ctx, a, MO_TESL);
  }
  static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVH);
 -
 -#ifndef CONFIG_USER_ONLY
 -    TCGv t0 = tcg_temp_new();
 -    TCGv t1 = tcg_temp_new();
 -
 -    check_access(ctx);
 -
 -    gen_get_gpr(ctx, t0, a->rs1);
 -
 -    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEUL);
 -    gen_set_gpr(ctx, a->rd, t1);
 -
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -    return true;
 -#else
 -    return false;
 -#endif
 +    return do_hlv(ctx, a, MO_TEUL);
  }
  static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVH);
 -
 -#ifndef CONFIG_USER_ONLY
 -    TCGv t0 = tcg_temp_new();
 -    TCGv t1 = tcg_temp_new();
 -
 -    check_access(ctx);
 -
 -    gen_get_gpr(ctx, t0, a->rs1);
 -
 -    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEQ);
 -    gen_set_gpr(ctx, a->rd, t1);
 -
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -    return true;
 -#else
 -    return false;
 -#endif
 +    return do_hlv(ctx, a, MO_TEQ);
  }
  static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVH);
 +    return do_hsv(ctx, a, MO_TEQ);
 +}
  #ifndef CONFIG_USER_ONLY
 -    TCGv t0 = tcg_temp_new();
 -    TCGv dat = tcg_temp_new();
 -
 -    check_access(ctx);
 -
 -    gen_get_gpr(ctx, t0, a->rs1);
 -    gen_get_gpr(ctx, dat, a->rs2);
 -
 -    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEQ);
 -
 -    tcg_temp_free(t0);
 -    tcg_temp_free(dat);
 +static bool do_hlvx(DisasContext *ctx, arg_r2 *a,
 +                    void (*func)(TCGv, TCGv_env, TCGv))
 +{
 +    if (check_access(ctx)) {
 +        TCGv dest = dest_gpr(ctx, a->rd);
 +        TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
 +        func(dest, cpu_env, addr);
 +        gen_set_gpr(ctx, a->rd, dest);
 +    }
      return true;
 -#else
 -    return false;
 -#endif
  }
 +#endif
  static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
  {
      REQUIRE_EXT(ctx, RVH);
  #ifndef CONFIG_USER_ONLY
 -    TCGv t0 = tcg_temp_new();
 -    TCGv t1 = tcg_temp_new();
 -
 -    check_access(ctx);
 -
 -    gen_get_gpr(ctx, t0, a->rs1);
 -
 -    gen_helper_hyp_hlvx_hu(t1, cpu_env, t0);
 -    gen_set_gpr(ctx, a->rd, t1);
 -
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -    return true;
 +    return do_hlvx(ctx, a, gen_helper_hyp_hlvx_hu);
  #else
      return false;
  #endif
@@ -XXX,XX +XXX,XX @@ static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a)
  {
      REQUIRE_EXT(ctx, RVH);
  #ifndef CONFIG_USER_ONLY
 -    TCGv t0 = tcg_temp_new();
 -    TCGv t1 = tcg_temp_new();
 -
 -    check_access(ctx);
 -
 -    gen_get_gpr(ctx, t0, a->rs1);
 -
 -    gen_helper_hyp_hlvx_wu(t1, cpu_env, t0);
 -    gen_set_gpr(ctx, a->rd, t1);
 -
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 -    return true;
 +    return do_hlvx(ctx, a, gen_helper_hyp_hlvx_wu);
  #else
      return false;
  #endif
 --
-.31.1
+.45.1

-[PULL 24/33] target/riscv: Use {get, dest}_gpr for integer load/store
+[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Privileged spec section 4.1.9 mentions:
 "When a trap is taken into S-mode, stval is written with
 exception-specific information to assist software in handling the trap.
 (...)
 If stval is written with a nonzero value when a breakpoint,
 address-misaligned, access-fault, or page-fault exception occurs on an
 instruction fetch, load, or store, then stval will contain the faulting
 virtual address."
 A similar text is found for mtval in section 3.1.16.
 Setting mtval/stval in this scenario is optional, but some softwares read
 these regs when handling ebreaks.
 Write 'badaddr' in all ebreak breakpoints to write the appropriate
 'tval' during riscv_do_cpu_interrrupt().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-Message-id: 20210823195529.560295-16-richard.henderson@linaro.org
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvi.c.inc | 38 +++++++++++++------------
+ target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
-file changed, 20 insertions(+), 18 deletions(-)
+file changed, 2 insertions(+)
-diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
+diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvi.c.inc
+--- a/target/riscv/insn_trans/trans_privileged.c.inc
-+++ b/target/riscv/insn_trans/trans_rvi.c.inc
++++ b/target/riscv/insn_trans/trans_privileged.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
+@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
+     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
- static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
+         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
- {
+     } else {
--    TCGv t0 = tcg_temp_new();
++        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
--    TCGv t1 = tcg_temp_new();
++                      offsetof(CPURISCVState, badaddr));
--    gen_get_gpr(ctx, t0, a->rs1);
+         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
--    tcg_gen_addi_tl(t0, t0, a->imm);
+     }
 -
 -    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
 -    gen_set_gpr(ctx, a->rd, t1);
 -    tcg_temp_free(t0);
 -    tcg_temp_free(t1);
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
 +
 +    if (a->imm) {
 +        TCGv temp = temp_new(ctx);
 +        tcg_gen_addi_tl(temp, addr, a->imm);
 +        addr = temp;
 +    }
 +
 +    tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
- static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
- {
--    TCGv t0 = tcg_temp_new();
--    TCGv dat = tcg_temp_new();
--    gen_get_gpr(ctx, t0, a->rs1);
--    tcg_gen_addi_tl(t0, t0, a->imm);
--    gen_get_gpr(ctx, dat, a->rs2);
-+    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
-+    TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
--    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
--    tcg_temp_free(t0);
--    tcg_temp_free(dat);
-+    if (a->imm) {
-+        TCGv temp = temp_new(ctx);
-+        tcg_gen_addi_tl(temp, addr, a->imm);
-+        addr = temp;
-+    }
-+
-+    tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
-     return true;
- }
--
- static bool trans_sb(DisasContext *ctx, arg_sb *a)
- {
-     return gen_store(ctx, a, MO_SB);
 --
-.31.1
+.45.1

-[PULL 10/33] target/riscv: Use tcg_constant_*
+[PULL 10/28] target/riscv: Add support for Zve32x extension
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jason Chien <jason.chien@sifive.com>
-Replace uses of tcg_const_* with the allocate and free close together.
+Add support for Zve32x extension and replace some checks for Zve32f with
 Zve32x, since Zve32f depends on Zve32x.
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-id: 20210823195529.560295-2-richard.henderson@linaro.org
+Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                | 36 ++++----------
+ target/riscv/cpu_cfg.h                  |  1 +
- target/riscv/insn_trans/trans_rvf.c.inc |  3 +-
+ target/riscv/cpu.c                      |  2 ++
- target/riscv/insn_trans/trans_rvv.c.inc | 65 +++++++++----------------
+ target/riscv/cpu_helper.c               |  2 +-
-files changed, 34 insertions(+), 70 deletions(-)
+ target/riscv/csr.c                      |  2 +-
  target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
  target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 files changed, 15 insertions(+), 12 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/translate.c
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-  */
+     bool ext_zhinx;
- static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
+     bool ext_zhinxmin;
      bool ext_zve32f;
 +    bool ext_zve32x;
      bool ext_zve64f;
      bool ext_zve64d;
      bool ext_zvbb;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
      ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
      ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
 +    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
      ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
      ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
      ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
      MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
      MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
 +    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
      MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
      MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
      MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
      *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
      *cs_base = 0;
 -    if (cpu->cfg.ext_zve32f) {
 +    if (cpu->cfg.ext_zve32x) {
          /*
           * If env->vl equals to VLMAX, we can use generic vector operation
           * expanders (GVEC) to accerlate the vector operations.
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
  static RISCVException vs(CPURISCVState *env, int csrno)
  {
--    TCGv_i64 t_max = tcg_const_i64(0xffffffff00000000ull);
+-    if (riscv_cpu_cfg(env)->ext_zve32f) {
--    TCGv_i64 t_nan = tcg_const_i64(0xffffffff7fc00000ull);
++    if (riscv_cpu_cfg(env)->ext_zve32x) {
-+    TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull);
+ #if !defined(CONFIG_USER_ONLY)
-+    TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull);
+         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+             return RISCV_EXCP_ILLEGAL_INST;
-     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
--    tcg_temp_free_i64(t_max);
+index XXXXXXX..XXXXXXX 100644
--    tcg_temp_free_i64(t_nan);
+--- a/target/riscv/tcg/tcg-cpu.c
- }
++++ b/target/riscv/tcg/tcg-cpu.c
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
  static void generate_exception(DisasContext *ctx, int excp)
  {
      tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
 -    TCGv_i32 helper_tmp = tcg_const_i32(excp);
 -    gen_helper_raise_exception(cpu_env, helper_tmp);
 -    tcg_temp_free_i32(helper_tmp);
 +    gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
      ctx->base.is_jmp = DISAS_NORETURN;
  }
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
  {
      tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
      tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
 -    TCGv_i32 helper_tmp = tcg_const_i32(excp);
 -    gen_helper_raise_exception(cpu_env, helper_tmp);
 -    tcg_temp_free_i32(helper_tmp);
 +    gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
      ctx->base.is_jmp = DISAS_NORETURN;
  }
  static void gen_exception_debug(void)
  {
 -    TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG);
 -    gen_helper_raise_exception(cpu_env, helper_tmp);
 -    tcg_temp_free_i32(helper_tmp);
 +    gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
  }
  /* Wrapper around tcg_gen_exit_tb that handles single stepping */
@@ -XXX,XX +XXX,XX @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2)
       */
      cond1 = tcg_temp_new();
      cond2 = tcg_temp_new();
 -    zeroreg = tcg_const_tl(0);
 +    zeroreg = tcg_constant_tl(0);
      resultopt1 = tcg_temp_new();
      tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
@@ -XXX,XX +XXX,XX @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2)
      tcg_temp_free(cond1);
      tcg_temp_free(cond2);
 -    tcg_temp_free(zeroreg);
      tcg_temp_free(resultopt1);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
      TCGv cond1, zeroreg, resultopt1;
      cond1 = tcg_temp_new();
 -    zeroreg = tcg_const_tl(0);
 +    zeroreg = tcg_constant_tl(0);
      resultopt1 = tcg_temp_new();
      tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
@@ -XXX,XX +XXX,XX @@ static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
      tcg_gen_divu_tl(ret, source1, source2);
      tcg_temp_free(cond1);
 -    tcg_temp_free(zeroreg);
      tcg_temp_free(resultopt1);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
      cond1 = tcg_temp_new();
      cond2 = tcg_temp_new();
 -    zeroreg = tcg_const_tl(0);
 +    zeroreg = tcg_constant_tl(0);
      resultopt1 = tcg_temp_new();
      tcg_gen_movi_tl(resultopt1, 1L);
@@ -XXX,XX +XXX,XX @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
      tcg_temp_free(cond1);
      tcg_temp_free(cond2);
 -    tcg_temp_free(zeroreg);
      tcg_temp_free(resultopt1);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
  {
      TCGv cond1, zeroreg, resultopt1;
      cond1 = tcg_temp_new();
 -    zeroreg = tcg_const_tl(0);
 +    zeroreg = tcg_constant_tl(0);
      resultopt1 = tcg_temp_new();
      tcg_gen_movi_tl(resultopt1, (target_ulong)1);
@@ -XXX,XX +XXX,XX @@ static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
              source1);
      tcg_temp_free(cond1);
 -    tcg_temp_free(zeroreg);
      tcg_temp_free(resultopt1);
  }
@@ -XXX,XX +XXX,XX @@ static inline void mark_fs_dirty(DisasContext *ctx) { }
  static void gen_set_rm(DisasContext *ctx, int rm)
  {
 -    TCGv_i32 t0;
 -
      if (ctx->frm == rm) {
          return;
      }
-     ctx->frm = rm;
--    t0 = tcg_const_i32(rm);
+-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
--    gen_helper_set_rounding_mode(cpu_env, t0);
+-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
--    tcg_temp_free_i32(t0);
+-        return;
-+    gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
++    /* The Zve32f extension depends on the Zve32x extension */
- }
++    if (cpu->cfg.ext_zve32f) {
++        if (!riscv_has_ext(env, RVF)) {
- static int ex_plus_1(DisasContext *ctx, int nf)
++            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
++            return;
-index XXXXXXX..XXXXXXX 100644
++        }
---- a/target/riscv/insn_trans/trans_rvf.c.inc
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
 +++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
           * Replace bit 31 in rs1 with inverse in rs2.
           * This formulation retains the nanboxing of rs1.
           */
 -        mask = tcg_const_i64(~MAKE_64BIT_MASK(31, 1));
 +        mask = tcg_constant_i64(~MAKE_64BIT_MASK(31, 1));
          tcg_gen_nor_i64(rs2, rs2, mask);
          tcg_gen_and_i64(rs1, mask, rs1);
          tcg_gen_or_i64(cpu_fpr[a->rd], rs1, rs2);
 -        tcg_temp_free_i64(mask);
          tcg_temp_free_i64(rs2);
      }
-     tcg_temp_free_i64(rs1);
      if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
      }
 -    /*
 -     * In principle Zve*x would also suffice here, were they supported
 -     * in qemu
 -     */
      if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
           cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
 -         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
 +         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
          error_setg(errp,
                     "Vector crypto extensions require V or Zve* extensions");
          return;
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
+@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
-     /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
+ {
-     if (a->rs1 == 0) {
+     TCGv s1, dst;
-         /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
--        s1 = tcg_const_tl(RV_VLEN_MAX);
+-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
-+        s1 = tcg_constant_tl(RV_VLEN_MAX);
++    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
      } else {
          s1 = tcg_temp_new();
          gen_get_gpr(s1, a->rs1);
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
          return false;
      }
--    s2 = tcg_const_tl(a->zimm);
+@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
-+    s2 = tcg_constant_tl(a->zimm);
+ {
-     dst = tcg_temp_new();
+     TCGv dst;
-     /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
+-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
-     if (a->rs1 == 0) {
++    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
-         /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
+         return false;
 -        s1 = tcg_const_tl(RV_VLEN_MAX);
 +        s1 = tcg_constant_tl(RV_VLEN_MAX);
      } else {
          s1 = tcg_temp_new();
          gen_get_gpr(s1, a->rs1);
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
      ctx->base.is_jmp = DISAS_NORETURN;
      tcg_temp_free(s1);
 -    tcg_temp_free(s2);
      tcg_temp_free(dst);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
       * The first part is vlen in bytes, encoded in maxsz of simd_desc.
       * The second part is lmul, encoded in data of simd_desc.
       */
 -    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 +    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
      gen_get_gpr(base, rs1);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      tcg_temp_free_ptr(dest);
      tcg_temp_free_ptr(mask);
      tcg_temp_free(base);
 -    tcg_temp_free_i32(desc);
      gen_set_label(over);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
      mask = tcg_temp_new_ptr();
      base = tcg_temp_new();
      stride = tcg_temp_new();
 -    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 +    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
      gen_get_gpr(base, rs1);
      gen_get_gpr(stride, rs2);
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
      tcg_temp_free_ptr(mask);
      tcg_temp_free(base);
      tcg_temp_free(stride);
 -    tcg_temp_free_i32(desc);
      gen_set_label(over);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
      mask = tcg_temp_new_ptr();
      index = tcg_temp_new_ptr();
      base = tcg_temp_new();
 -    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 +    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
      gen_get_gpr(base, rs1);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
      tcg_temp_free_ptr(mask);
      tcg_temp_free_ptr(index);
      tcg_temp_free(base);
 -    tcg_temp_free_i32(desc);
      gen_set_label(over);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
      base = tcg_temp_new();
 -    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 +    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
      gen_get_gpr(base, rs1);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      tcg_temp_free_ptr(dest);
      tcg_temp_free_ptr(mask);
      tcg_temp_free(base);
 -    tcg_temp_free_i32(desc);
      gen_set_label(over);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
      mask = tcg_temp_new_ptr();
      index = tcg_temp_new_ptr();
      base = tcg_temp_new();
 -    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 +    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
      gen_get_gpr(base, rs1);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -XXX,XX +XXX,XX @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
      tcg_temp_free_ptr(mask);
      tcg_temp_free_ptr(index);
      tcg_temp_free(base);
 -    tcg_temp_free_i32(desc);
      gen_set_label(over);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
      data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
      data = FIELD_DP32(data, VDATA, VM, vm);
      data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
 -    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 +    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
      tcg_temp_free_ptr(mask);
      tcg_temp_free_ptr(src2);
      tcg_temp_free(src1);
 -    tcg_temp_free_i32(desc);
      gen_set_label(over);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
      mask = tcg_temp_new_ptr();
      src2 = tcg_temp_new_ptr();
      if (zx) {
 -        src1 = tcg_const_tl(imm);
 +        src1 = tcg_constant_tl(imm);
      } else {
 -        src1 = tcg_const_tl(sextract64(imm, 0, 5));
 +        src1 = tcg_constant_tl(sextract64(imm, 0, 5));
      }
-     data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
-     data = FIELD_DP32(data, VDATA, VM, vm);
-     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
--    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-+    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
-     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
-@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
-     tcg_temp_free_ptr(dest);
-     tcg_temp_free_ptr(mask);
-     tcg_temp_free_ptr(src2);
--    tcg_temp_free(src1);
--    tcg_temp_free_i32(desc);
-     gen_set_label(over);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ GEN_OPIVI_GVEC_TRANS(vadd_vi, 0, vadd_vx, addi)
- static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs,
-                                int64_t c, uint32_t oprsz, uint32_t maxsz)
- {
--    TCGv_i64 tmp = tcg_const_i64(c);
-+    TCGv_i64 tmp = tcg_constant_i64(c);
-     tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz);
--    tcg_temp_free_i64(tmp);
- }
- GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi)
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
-             tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
-                                 MAXSZ(s), MAXSZ(s), s1);
-         } else {
--            TCGv_i32 desc ;
-+            TCGv_i32 desc;
-             TCGv_i64 s1_i64 = tcg_temp_new_i64();
-             TCGv_ptr dest = tcg_temp_new_ptr();
-             uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
-             };
-             tcg_gen_ext_tl_i64(s1_i64, s1);
--            desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-+            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
-             fns[s->sew](dest, s1_i64, cpu_env, desc);
-             tcg_temp_free_ptr(dest);
--            tcg_temp_free_i32(desc);
-             tcg_temp_free_i64(s1_i64);
-         }
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
-             TCGLabel *over = gen_new_label();
-             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
--            s1 = tcg_const_i64(simm);
-+            s1 = tcg_constant_i64(simm);
-             dest = tcg_temp_new_ptr();
--            desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-+            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
-             fns[s->sew](dest, s1, cpu_env, desc);
-             tcg_temp_free_ptr(dest);
--            tcg_temp_free_i32(desc);
--            tcg_temp_free_i64(s1);
-             gen_set_label(over);
-         }
-         return true;
-@@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
-     dest = tcg_temp_new_ptr();
-     mask = tcg_temp_new_ptr();
-     src2 = tcg_temp_new_ptr();
--    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-+    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
-     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
-@@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
-     tcg_temp_free_ptr(dest);
-     tcg_temp_free_ptr(mask);
-     tcg_temp_free_ptr(src2);
--    tcg_temp_free_i32(desc);
-     gen_set_label(over);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
-             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-             dest = tcg_temp_new_ptr();
--            desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-+            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
-             fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
-             tcg_temp_free_ptr(dest);
--            tcg_temp_free_i32(desc);
-             gen_set_label(over);
-         }
-         return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
-         mask = tcg_temp_new_ptr();
-         src2 = tcg_temp_new_ptr();
-         dst = tcg_temp_new();
--        desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-+        desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-         tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
-         tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
-         tcg_temp_free_ptr(mask);
-         tcg_temp_free_ptr(src2);
-         tcg_temp_free(dst);
--        tcg_temp_free_i32(desc);
-         return true;
-     }
-     return false;
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
-         mask = tcg_temp_new_ptr();
-         src2 = tcg_temp_new_ptr();
-         dst = tcg_temp_new();
--        desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-+        desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-         tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
-         tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
-@@ -XXX,XX +XXX,XX @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
-         tcg_temp_free_ptr(mask);
-         tcg_temp_free_ptr(src2);
-         tcg_temp_free(dst);
--        tcg_temp_free_i32(desc);
-         return true;
-     }
-     return false;
-@@ -XXX,XX +XXX,XX @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
-     tcg_temp_free_i32(ofs);
-     /* Flush out-of-range indexing to zero.  */
--    t_vlmax = tcg_const_i64(vlmax);
--    t_zero = tcg_const_i64(0);
-+    t_vlmax = tcg_constant_i64(vlmax);
-+    t_zero = tcg_constant_i64(0);
-     tcg_gen_extu_tl_i64(t_idx, idx);
-     tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx,
-                         t_vlmax, dest, t_zero);
--    tcg_temp_free_i64(t_vlmax);
--    tcg_temp_free_i64(t_zero);
-     tcg_temp_free_i64(t_idx);
- }
 --
-.31.1
+.45.1

-[PULL 23/33] target/riscv: Use get_gpr in branches
+[PULL 11/28] target/riscv: Add support for Zve64x extension
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jason Chien <jason.chien@sifive.com>
-Narrow the scope of t0 in trans_jalr.
+Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
 enabling Zve64x enables Zve32x according to their dependency.
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Message-id: 20210823195529.560295-15-richard.henderson@linaro.org
+Reviewed-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvi.c.inc | 25 ++++++++++---------------
+ target/riscv/cpu_cfg.h     |  1 +
-file changed, 10 insertions(+), 15 deletions(-)
+ target/riscv/cpu.c         |  2 ++
  target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 files changed, 14 insertions(+), 6 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvi.c.inc
+--- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/insn_trans/trans_rvi.c.inc
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+     bool ext_zve32x;
- static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
+     bool ext_zve64f;
- {
+     bool ext_zve64d;
--    /* no chaining with JALR */
++    bool ext_zve64x;
-     TCGLabel *misaligned = NULL;
+     bool ext_zvbb;
--    TCGv t0 = tcg_temp_new();
+     bool ext_zvbc;
--
+     bool ext_zvkb;
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
--    gen_get_gpr(ctx, cpu_pc, a->rs1);
+index XXXXXXX..XXXXXXX 100644
--    tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+--- a/target/riscv/cpu.c
-+    tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
++++ b/target/riscv/cpu.c
-     tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
+     ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
-     if (!has_ext(ctx, RVC)) {
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
-+        TCGv t0 = tcg_temp_new();
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
-+
++    ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
-         misaligned = gen_new_label();
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
-         tcg_gen_andi_tl(t0, cpu_pc, 0x2);
+     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
-         tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
-+        tcg_temp_free(t0);
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
      MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
      MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
 +    MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
      MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
      MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
      MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
      /* The Zve64d extension depends on the Zve64f extension */
      if (cpu->cfg.ext_zve64d) {
 +        if (!riscv_has_ext(env, RVD)) {
 +            error_setg(errp, "Zve64d/V extensions require D extension");
 +            return;
 +        }
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
      }
-     if (a->rd != 0) {
+-    /* The Zve64f extension depends on the Zve32f extension */
-         tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
++    /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
      if (cpu->cfg.ext_zve64f) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
      }
-+
-+    /* No chaining with JALR. */
+-    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
-     lookup_and_goto_ptr(ctx);
+-        error_setg(errp, "Zve64d/V extensions require D extension");
+-        return;
-     if (misaligned) {
++    /* The Zve64x extension depends on the Zve32x extension */
-@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
++    if (cpu->cfg.ext_zve64x) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
      }
-     ctx->base.is_jmp = DISAS_NORETURN;
+     /* The Zve32f extension depends on the Zve32x extension */
--    tcg_temp_free(t0);
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-     return true;
+         return;
  }
  static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
  {
      TCGLabel *l = gen_new_label();
 -    TCGv source1, source2;
 -    source1 = tcg_temp_new();
 -    source2 = tcg_temp_new();
 -    gen_get_gpr(ctx, source1, a->rs1);
 -    gen_get_gpr(ctx, source2, a->rs2);
 +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
 +    TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
 -    tcg_gen_brcond_tl(cond, source1, source2, l);
 +    tcg_gen_brcond_tl(cond, src1, src2, l);
      gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
 +
      gen_set_label(l); /* branch taken */
      if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
@@ -XXX,XX +XXX,XX @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
      }
-     ctx->base.is_jmp = DISAS_NORETURN;
+-    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
--    tcg_temp_free(source1);
++    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
--    tcg_temp_free(source2);
+         error_setg(
--
+             errp,
-     return true;
+-            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
- }
++            "Zvbc and Zvknhb extensions require V or Zve64x extensions");
          return;
      }
 --
-.31.1
+.45.1

-[PULL 09/33] hw/registerfields: Use 64-bit bitfield for FIELD_DP64
+[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
-From: Joe Komlodi <joe.komlodi@xilinx.com>
+From: Jason Chien <jason.chien@sifive.com>
-If we have a field that's wider than 32-bits, we need a data type wide enough to
+In current implementation, the gdbstub allows reading vector registers
-be able to create the bitfield used to deposit the value.
+only if V extension is supported. However, all vector extensions and
 vector crypto extensions have the vector registers and they all depend
 on Zve32x. The gdbstub should check for Zve32x instead.
-Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
-Message-id: 1626805903-162860-3-git-send-email-joe.komlodi@xilinx.com
+Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/registerfields.h | 2 +-
+ target/riscv/gdbstub.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/registerfields.h
+--- a/target/riscv/gdbstub.c
-+++ b/include/hw/registerfields.h
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
-     _d; })
+                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
- #define FIELD_DP64(storage, reg, field, val) ({                           \
+);
-     struct {                                                              \
+     }
--        unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
+-    if (env->misa_ext & RVV) {
-+        uint64_t v:R_ ## reg ## _ ## field ## _LENGTH;                \
++    if (cpu->cfg.ext_zve32x) {
-     } _v = { .v = val };                                                  \
+         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
-     uint64_t _d;                                                          \
+                                  riscv_gdb_set_vector,
-     _d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT,          \
+                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
 --
-.31.1
+.45.1

-[PULL 28/33] target/riscv: Use {get,dest}_gpr for RVA
+[PULL 13/28] target/riscv: Fix the element agnostic function problem
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+In RVV and vcrypto instructions, the masked and tail elements are set to 1s
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+using vext_set_elems_1s function if the vma/vta bit is set. It is the element
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+agnostic policy.
-Message-id: 20210823195529.560295-20-richard.henderson@linaro.org
 However, this function can't deal the big endian situation. This patch fixes
 the problem by adding handling of such case.
 Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
 Suggested-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rva.c.inc | 47 ++++++++++---------------
+ target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
-file changed, 19 insertions(+), 28 deletions(-)
+file changed, 22 insertions(+)
-diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
+diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rva.c.inc
+--- a/target/riscv/vector_internals.c
-+++ b/target/riscv/insn_trans/trans_rva.c.inc
++++ b/target/riscv/vector_internals.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
-  * this program.  If not, see <http://www.gnu.org/licenses/>.
+     if (tot - cnt == 0) {
-  */
+         return ;
 -static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
 +static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
  {
 -    TCGv src1 = tcg_temp_new();
 -    /* Put addr in load_res, data in load_val.  */
 -    gen_get_gpr(ctx, src1, a->rs1);
 +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
 +
      if (a->rl) {
          tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
      }
@@ -XXX,XX +XXX,XX @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
      if (a->aq) {
          tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
      }
 +
-+    /* Put addr in load_res, data in load_val.  */
++    if (HOST_BIG_ENDIAN) {
-     tcg_gen_mov_tl(load_res, src1);
++        /*
-     gen_set_gpr(ctx, a->rd, load_val);
++         * Deal the situation when the elements are insdie
++         * only one uint64 block including setting the
--    tcg_temp_free(src1);
++         * masked-off element.
-     return true;
++         */
 +        if (((tot - 1) ^ cnt) < 8) {
 +            memset(base + H1(tot - 1), -1, tot - cnt);
 +            return;
 +        }
 +        /*
 +         * Otherwise, at least cross two uint64_t blocks.
 +         * Set first unaligned block.
 +         */
 +        if (cnt % 8 != 0) {
 +            uint32_t j = ROUND_UP(cnt, 8);
 +            memset(base + H1(j - 1), -1, j - cnt);
 +            cnt = j;
 +        }
 +        /* Set other 64bit aligend blocks */
 +    }
      memset(base + cnt, -1, tot - cnt);
  }
--static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
-+static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
- {
--    TCGv src1 = tcg_temp_new();
--    TCGv src2 = tcg_temp_new();
--    TCGv dat = tcg_temp_new();
-+    TCGv dest, src1, src2;
-     TCGLabel *l1 = gen_new_label();
-     TCGLabel *l2 = gen_new_label();
--    gen_get_gpr(ctx, src1, a->rs1);
-+    src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
-     tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
--    gen_get_gpr(ctx, src2, a->rs2);
-     /*
-      * Note that the TCG atomic primitives are SC,
-      * so we can ignore AQ/RL along this path.
-      */
--    tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
-+    dest = dest_gpr(ctx, a->rd);
-+    src2 = get_gpr(ctx, a->rs2, EXT_NONE);
-+    tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2,
-                               ctx->mem_idx, mop);
--    tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
--    gen_set_gpr(ctx, a->rd, dat);
-+    tcg_gen_setcond_tl(TCG_COND_NE, dest, dest, load_val);
-+    gen_set_gpr(ctx, a->rd, dest);
-     tcg_gen_br(l2);
-     gen_set_label(l1);
-@@ -XXX,XX +XXX,XX @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
-      * provide the memory barrier implied by AQ/RL.
-      */
-     tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
--    tcg_gen_movi_tl(dat, 1);
--    gen_set_gpr(ctx, a->rd, dat);
-+    gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
-     gen_set_label(l2);
-     /*
-@@ -XXX,XX +XXX,XX @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
-      */
-     tcg_gen_movi_tl(load_res, -1);
--    tcg_temp_free(dat);
--    tcg_temp_free(src1);
--    tcg_temp_free(src2);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
-                     void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
-                     MemOp mop)
- {
--    TCGv src1 = tcg_temp_new();
--    TCGv src2 = tcg_temp_new();
--
--    gen_get_gpr(ctx, src1, a->rs1);
--    gen_get_gpr(ctx, src2, a->rs2);
-+    TCGv dest = dest_gpr(ctx, a->rd);
-+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
-+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
--    (*func)(src2, src1, src2, ctx->mem_idx, mop);
-+    func(dest, src1, src2, ctx->mem_idx, mop);
--    gen_set_gpr(ctx, a->rd, src2);
--    tcg_temp_free(src1);
--    tcg_temp_free(src2);
-+    gen_set_gpr(ctx, a->rd, dest);
-     return true;
- }
 --
-.31.1
+.45.1

-[PULL 03/33] target/riscv: Correct a comment in riscv_csrrw()
+[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
-From: Bin Meng <bmeng.cn@gmail.com>
+From: Yangyu Chen <cyy@cyyself.name>
-When privilege check fails, RISCV_EXCP_ILLEGAL_INST is returned,
+This code has a typo that writes zvkb to zvkg, causing users can't
-not -1 (RISCV_EXCP_NONE).
+enable zvkb through the config. This patch gets this fixed.
-Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
+Signed-off-by: Yangyu Chen <cyy@cyyself.name>
 Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210807141025.31808-1-bmeng.cn@gmail.com
+Reviewed-by: Max Chou <max.chou@sifive.com>
 Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
 Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 2 +-
+ target/riscv/cpu.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/csr.c
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-     target_ulong old_value;
+     /* Vector cryptography extensions */
-     RISCVCPU *cpu = env_archcpu(env);
+     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
+     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
--    /* check privileges and return -1 if check fails */
+-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
-+    /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
++    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
- #if !defined(CONFIG_USER_ONLY)
+     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
-     int effective_priv = env->priv;
+     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
-     int read_only = get_field(csrno, 0xC00) == 3;
+     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
 --
-.31.1
+.45.1

-[PULL 14/33] target/riscv: Introduce DisasExtend and new helpers
+[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-Introduce get_gpr, dest_gpr, temp_new -- new helpers that do not force
+In this patch, we modify the decoder to be a freely composable data
-tcg globals into temps, returning a constant 0 for $zero as source and
+structure instead of a hardcoded one. It can be dynamically builded up
-a new temp for $zero as destination.
+according to the extensions.
 This approach has several benefits:
 . Provides support for heterogeneous cpu architectures. As we add decoder in
    RISCVCPU, each cpu can have their own decoder, and the decoders can be
    different due to cpu's features.
 . Improve the decoding efficiency. We run the guard_func to see if the decoder
    can be added to the dynamic_decoder when building up the decoder. Therefore,
    there is no need to run the guard_func when decoding each instruction. It can
    improve the decoding efficiency
 . For vendor or dynamic cpus, it allows them to customize their own decoder
    functions to improve decoding efficiency, especially when vendor-defined
    instruction sets increase. Because of dynamic building up, it can skip the other
    decoder guard functions when decoding.
 . Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
    overhead for users that don't need this particular vendor decoder.
-Introduce ctx->w for simplifying word operations, such as addw.
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
+Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
 Message-id: 20210823195529.560295-6-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c | 97 +++++++++++++++++++++++++++++++++-------
+ target/riscv/cpu.h         |  1 +
-file changed, 81 insertions(+), 16 deletions(-)
+ target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
  target/riscv/cpu.c         |  1 +
  target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
  target/riscv/translate.c   | 31 +++++++++++++++----------------
 files changed, 47 insertions(+), 16 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
+     uint32_t pmu_avail_ctrs;
+     /* Mapping of events to counters */
+     GHashTable *pmu_event_ctr_map;
++    const GPtrArray *decoders;
+ };
+ /**
+diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/tcg/tcg-cpu.h
++++ b/target/riscv/tcg/tcg-cpu.h
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
+ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
+ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
++struct DisasContext;
++struct RISCVCPUConfig;
++typedef struct RISCVDecoder {
++    bool (*guard_func)(const struct RISCVCPUConfig *);
++    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
++} RISCVDecoder;
++
++typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
++
++extern const size_t decoder_table_size;
++
++extern const RISCVDecoder decoder_table[];
++
++void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
++
+ #endif
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
+             error_propagate(errp, local_err);
+             return;
+         }
++        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
+     } else if (kvm_enabled()) {
+         riscv_kvm_cpu_finalize_features(cpu, &local_err);
+         if (local_err != NULL) {
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/tcg/tcg-cpu.c
++++ b/target/riscv/tcg/tcg-cpu.c
+@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
+     }
+ }
++void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
++{
++    GPtrArray *dynamic_decoders;
++    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
++    for (size_t i = 0; i < decoder_table_size; ++i) {
++        if (decoder_table[i].guard_func &&
++            decoder_table[i].guard_func(&cpu->cfg)) {
++            g_ptr_array_add(dynamic_decoders,
++                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
++        }
++    }
++
++    cpu->decoders = dynamic_decoders;
++}
++
+ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
+ {
+     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static TCGv load_val;
+@@ -XXX,XX +XXX,XX @@
+ #include "exec/helper-info.c.inc"
- #include "exec/gen-icount.h"
+ #undef  HELPER_H
-+/*
++#include "tcg/tcg-cpu.h"
 + * If an operation is being performed on less than TARGET_LONG_BITS,
 + * it may require the inputs to be sign- or zero-extended; which will
 + * depend on the exact operation being performed.
 + */
 +typedef enum {
 +    EXT_NONE,
 +    EXT_SIGN,
 +    EXT_ZERO,
 +} DisasExtend;
 +
- typedef struct DisasContext {
+ /* global register indices */
-     DisasContextBase base;
+ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
-     /* pc_succ_insn points to the instruction following base.pc_next */
+ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
      target_ulong pc_succ_insn;
      target_ulong priv_ver;
 -    bool virt_enabled;
 +    target_ulong misa;
      uint32_t opcode;
      uint32_t mstatus_fs;
 -    target_ulong misa;
      uint32_t mem_idx;
      /* Remember the rounding mode encoded in the previous fp instruction,
         which we have already installed into env->fp_status.  Or -1 for
 @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-        to any system register, which includes CSR_FRM, so we do not have
+     /* FRM is known to contain a valid value. */
-        to reset this known value.  */
+     bool frm_valid;
-     int frm;
+     bool insn_start_updated;
-+    bool w;
++    const GPtrArray *decoders;
 +    bool virt_enabled;
      bool ext_ifencei;
      bool hlsx;
      /* vector extension */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      uint16_t vlen;
      uint16_t mlen;
      bool vl_eq_vlmax;
 +    uint8_t ntemp;
      CPUState *cs;
 +    TCGv zero;
 +    /* Space for 3 operands plus 1 extra for address computation. */
 +    TCGv temp[4];
  } DisasContext;
  static inline bool has_ext(DisasContext *ctx, uint32_t ext)
-@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
-     }
+     return (first_word & 3) == 3 ? 4 : 2;
  }
--/* Wrapper for getting reg values - need to check of reg is zero since
++const RISCVDecoder decoder_table[] = {
-- * cpu_gpr[0] is not actually allocated
++    { always_true_p, decode_insn32 },
-+/*
++    { has_xthead_p, decode_xthead},
-+ * Wrappers for getting reg values.
++    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
-+ *
++};
 + * The $zero register does not have cpu_gpr[0] allocated -- we supply the
 + * constant zero as a source, and an uninitialized sink as destination.
 + *
 + * Further, we may provide an extension for word operations.
   */
 -static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num)
 +static TCGv temp_new(DisasContext *ctx)
 +{
 +    assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
 +    return ctx->temp[ctx->ntemp++] = tcg_temp_new();
 +}
 +
-+static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
++const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
 +
  static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
  {
-+    TCGv t;
+-    /*
-+
+-     * A table with predicate (i.e., guard) functions and decoder functions
-     if (reg_num == 0) {
+-     * that are tested in-order until a decoder matches onto the opcode.
--        tcg_gen_movi_tl(t, 0);
+-     */
--    } else {
+-    static const struct {
--        tcg_gen_mov_tl(t, cpu_gpr[reg_num]);
+-        bool (*guard_func)(const RISCVCPUConfig *);
-+        return ctx->zero;
+-        bool (*decode_func)(DisasContext *, uint32_t);
-     }
+-    } decoders[] = {
-+
+-        { always_true_p,  decode_insn32 },
-+    switch (ctx->w ? ext : EXT_NONE) {
+-        { has_xthead_p, decode_xthead },
-+    case EXT_NONE:
+-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
-+        return cpu_gpr[reg_num];
+-    };
-+    case EXT_SIGN:
+-
-+        t = temp_new(ctx);
+     ctx->virt_inst_excp = false;
-+        tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
+     ctx->cur_insn_len = insn_len(opcode);
-+        return t;
+     /* Check for compressed insn */
-+    case EXT_ZERO:
+@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
-+        t = temp_new(ctx);
+                                              ctx->base.pc_next + 2));
-+        tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
+         ctx->opcode = opcode32;
-+        return t;
-+    }
+-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
-+    g_assert_not_reached();
+-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
 -                decoders[i].decode_func(ctx, opcode32)) {
 +        for (guint i = 0; i < ctx->decoders->len; ++i) {
 +            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
 +            if (func(ctx, opcode32)) {
                  return;
              }
          }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
      ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
      ctx->zero = tcg_constant_tl(0);
      ctx->virt_inst_excp = false;
 +    ctx->decoders = cpu->decoders;
  }
--/* Wrapper for setting reg values - need to check of reg is zero since
-- * cpu_gpr[0] is not actually allocated. this is more for safety purposes,
-- * since we usually avoid calling the OP_TYPE_gen function if we see a write to
-- * $zero
-- */
--static void gen_set_gpr(DisasContext *ctx, int reg_num_dst, TCGv t)
-+static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num)
-+{
-+    tcg_gen_mov_tl(t, get_gpr(ctx, reg_num, EXT_NONE));
-+}
-+
-+static TCGv __attribute__((unused)) dest_gpr(DisasContext *ctx, int reg_num)
-+{
-+    if (reg_num == 0 || ctx->w) {
-+        return temp_new(ctx);
-+    }
-+    return cpu_gpr[reg_num];
-+}
-+
-+static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
- {
--    if (reg_num_dst != 0) {
--        tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t);
-+    if (reg_num != 0) {
-+        if (ctx->w) {
-+            tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
-+        } else {
-+            tcg_gen_mov_tl(cpu_gpr[reg_num], t);
-+        }
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-     ctx->mlen = 1 << (ctx->sew  + 3 - ctx->lmul);
-     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
-     ctx->cs = cs;
-+    ctx->w = false;
-+    ctx->ntemp = 0;
-+    memset(ctx->temp, 0, sizeof(ctx->temp));
-+
-+    ctx->zero = tcg_constant_tl(0);
- }
  static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
-     decode_opc(env, ctx, opcode16);
-     ctx->base.pc_next = ctx->pc_succ_insn;
-+    ctx->w = false;
-+
-+    for (int i = ctx->ntemp - 1; i >= 0; --i) {
-+        tcg_temp_free(ctx->temp[i]);
-+        ctx->temp[i] = NULL;
-+    }
-+    ctx->ntemp = 0;
-     if (ctx->base.is_jmp == DISAS_NEXT) {
-         target_ulong page_start;
 --
-.31.1
+.45.1

-[PULL 11/33] tests/tcg/riscv64: Add test for division
+[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Christoph Müllner <christoph.muellner@vrull.eu>
-Tested-by: Bin Meng <bmeng.cn@gmail.com>
+The th.sxstatus CSR can be used to identify available custom extension
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+on T-Head CPUs. The CSR is documented here:
   https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
 An important property of this patch is, that the th.sxstatus MAEE field
 is not set (indicating that XTheadMae is not available).
 XTheadMae is a memory attribute extension (similar to Svpbmt) which is
 implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
 in PTEs that are marked as reserved. QEMU maintainers prefer to not
 implement XTheadMae, so we need give kernels a mechanism to identify
 if XTheadMae is available in a system or not. And this patch introduces
 this mechanism in QEMU in a way that's compatible with real HW
 (i.e., probing the th.sxstatus.MAEE bit).
 Further context can be found on the list:
 https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
 Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
-Message-id: 20210823195529.560295-3-richard.henderson@linaro.org
+Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- tests/tcg/riscv64/test-div.c      | 58 +++++++++++++++++++++++++++++++
+ MAINTAINERS              |  1 +
- tests/tcg/riscv64/Makefile.target |  5 +++
+ target/riscv/cpu.h       |  3 ++
-files changed, 63 insertions(+)
+ target/riscv/cpu.c       |  1 +
- create mode 100644 tests/tcg/riscv64/test-div.c
+ target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
- create mode 100644 tests/tcg/riscv64/Makefile.target
+ target/riscv/meson.build |  1 +
 files changed, 85 insertions(+)
  create mode 100644 target/riscv/th_csr.c
-diff --git a/tests/tcg/riscv64/test-div.c b/tests/tcg/riscv64/test-div.c
+diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
  S: Supported
  F: target/riscv/insn_trans/trans_xthead.c.inc
  F: target/riscv/xthead*.decode
 +F: target/riscv/th_*
  F: disas/riscv-xthead*
  RISC-V XVentanaCondOps extension
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
  uint8_t satp_mode_max_from_map(uint32_t map);
  const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 +/* Implemented in th_csr.c */
 +void th_register_custom_csrs(RISCVCPU *cpu);
 +
  #endif /* RISCV_CPU_H */
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
      cpu->cfg.mvendorid = THEAD_VENDOR_ID;
  #ifndef CONFIG_USER_ONLY
      set_satp_mode_max_supported(cpu, VM_1_10_SV39);
 +    th_register_custom_csrs(cpu);
  #endif
      /* inherited from parent obj via riscv_cpu_init() */
 diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/tests/tcg/riscv64/test-div.c
++++ b/target/riscv/th_csr.c
 @@ -XXX,XX +XXX,XX @@
-+#include <assert.h>
++/*
-+#include <limits.h>
++ * T-Head-specific CSRs.
 + *
 + * Copyright (c) 2024 VRULL GmbH
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
-+struct TestS {
++#include "qemu/osdep.h"
-+    long x, y, q, r;
++#include "cpu.h"
-+};
++#include "cpu_vendorid.h"
 +
-+static struct TestS test_s[] = {
++#define CSR_TH_SXSTATUS 0x5c0
 +    { 4, 2, 2, 0 },                 /* normal cases */
 +    { 9, 7, 1, 2 },
 +    { 0, 0, -1, 0 },                /* div by zero cases */
 +    { 9, 0, -1, 9 },
 +    { LONG_MIN, -1, LONG_MIN, 0 },  /* overflow case */
 +};
 +
-+struct TestU {
++/* TH_SXSTATUS bits */
-+    unsigned long x, y, q, r;
++#define TH_SXSTATUS_UCME        BIT(16)
-+};
++#define TH_SXSTATUS_MAEE        BIT(21)
 +#define TH_SXSTATUS_THEADISAEE  BIT(22)
 +
-+static struct TestU test_u[] = {
++typedef struct {
-+    { 4, 2, 2, 0 },                 /* normal cases */
++    int csrno;
-+    { 9, 7, 1, 2 },
++    int (*insertion_test)(RISCVCPU *cpu);
-+    { 0, 0, ULONG_MAX, 0 },         /* div by zero cases */
++    riscv_csr_operations csr_ops;
-+    { 9, 0, ULONG_MAX, 9 },
++} riscv_csr;
 +};
 +
-+#define ARRAY_SIZE(X)  (sizeof(X) / sizeof(*(X)))
++static RISCVException smode(CPURISCVState *env, int csrno)
 +
 +int main (void)
 +{
-+    int i;
++    if (riscv_has_ext(env, RVS)) {
-+
++        return RISCV_EXCP_NONE;
 +    for (i = 0; i < ARRAY_SIZE(test_s); i++) {
 +        long q, r;
 +
 +        asm("div %0, %2, %3\n\t"
 +            "rem %1, %2, %3"
 +            : "=&r" (q), "=r" (r)
 +            : "r" (test_s[i].x), "r" (test_s[i].y));
 +
 +        assert(q == test_s[i].q);
 +        assert(r == test_s[i].r);
 +    }
 +
-+    for (i = 0; i < ARRAY_SIZE(test_u); i++) {
++    return RISCV_EXCP_ILLEGAL_INST;
-+        unsigned long q, r;
++}
 +
-+        asm("divu %0, %2, %3\n\t"
++static int test_thead_mvendorid(RISCVCPU *cpu)
-+            "remu %1, %2, %3"
++{
-+            : "=&r" (q), "=r" (r)
++    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
-+            : "r" (test_u[i].x), "r" (test_u[i].y));
++        return -1;
 +
 +        assert(q == test_u[i].q);
 +        assert(r == test_u[i].r);
 +    }
 +
 +    return 0;
 +}
-diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tests/tcg/riscv64/Makefile.target
-@@ -XXX,XX +XXX,XX @@
-+# -*- Mode: makefile -*-
-+# RISC-V specific tweaks
 +
-+VPATH += $(SRC_PATH)/tests/tcg/riscv64
++static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
-+TESTS += test-div
++                                       target_ulong *val)
 +{
 +    /* We don't set MAEE here, because QEMU does not implement MAEE. */
 +    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static riscv_csr th_csr_list[] = {
 +    {
 +        .csrno = CSR_TH_SXSTATUS,
 +        .insertion_test = test_thead_mvendorid,
 +        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
 +    }
 +};
 +
 +void th_register_custom_csrs(RISCVCPU *cpu)
 +{
 +    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
 +        int csrno = th_csr_list[i].csrno;
 +        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
 +        if (!th_csr_list[i].insertion_test(cpu)) {
 +            riscv_set_csr_ops(csrno, csr_ops);
 +        }
 +    }
 +}
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/meson.build
 +++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
    'monitor.c',
    'machine.c',
    'pmu.c',
 +  'th_csr.c',
    'time_helper.c',
    'riscv-qmp-cmds.c',
  ))
 --
-.31.1
+.45.1

-[PULL 18/33] target/riscv: Move gen_* helpers for RVM
+[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Max Chou <max.chou@sifive.com>
-Move these helpers near their use by the trans_*
+According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
-functions within insn_trans/trans_rvm.c.inc.
+instructions will be affected by Zvfhmin extension.
 And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
 conversions of
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+* From 1*SEW(16/32) to 2*SEW(32/64)
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+* From 2*SEW(32/64) to 1*SEW(16/32)
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Message-id: 20210823195529.560295-10-richard.henderson@linaro.org
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                | 127 ------------------------
+ target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
- target/riscv/insn_trans/trans_rvm.c.inc | 127 ++++++++++++++++++++++++
+file changed, 18 insertions(+), 2 deletions(-)
 files changed, 127 insertions(+), 127 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/translate.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
+@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
      }
  }
--static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
++static bool require_rvfmin(DisasContext *s)
 -{
 -    TCGv rl = tcg_temp_new();
 -    TCGv rh = tcg_temp_new();
 -
 -    tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
 -    /* fix up for one negative */
 -    tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
 -    tcg_gen_and_tl(rl, rl, arg2);
 -    tcg_gen_sub_tl(ret, rh, rl);
 -
 -    tcg_temp_free(rl);
 -    tcg_temp_free(rh);
 -}
 -
 -static void gen_div(TCGv ret, TCGv source1, TCGv source2)
 -{
 -    TCGv temp1, temp2, zero, one, mone, min;
 -
 -    temp1 = tcg_temp_new();
 -    temp2 = tcg_temp_new();
 -    zero = tcg_constant_tl(0);
 -    one = tcg_constant_tl(1);
 -    mone = tcg_constant_tl(-1);
 -    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
 -
 -    /*
 -     * If overflow, set temp2 to 1, else source2.
 -     * This produces the required result of min.
 -     */
 -    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
 -    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
 -    tcg_gen_and_tl(temp1, temp1, temp2);
 -    tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2);
 -
 -    /*
 -     * If div by zero, set temp1 to -1 and temp2 to 1 to
 -     * produce the required result of -1.
 -     */
 -    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
 -    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2);
 -
 -    tcg_gen_div_tl(ret, temp1, temp2);
 -
 -    tcg_temp_free(temp1);
 -    tcg_temp_free(temp2);
 -}
 -
 -static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
 -{
 -    TCGv temp1, temp2, zero, one, max;
 -
 -    temp1 = tcg_temp_new();
 -    temp2 = tcg_temp_new();
 -    zero = tcg_constant_tl(0);
 -    one = tcg_constant_tl(1);
 -    max = tcg_constant_tl(~0);
 -
 -    /*
 -     * If div by zero, set temp1 to max and temp2 to 1 to
 -     * produce the required result of max.
 -     */
 -    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
 -    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
 -    tcg_gen_divu_tl(ret, temp1, temp2);
 -
 -    tcg_temp_free(temp1);
 -    tcg_temp_free(temp2);
 -}
 -
 -static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
 -{
 -    TCGv temp1, temp2, zero, one, mone, min;
 -
 -    temp1 = tcg_temp_new();
 -    temp2 = tcg_temp_new();
 -    zero = tcg_constant_tl(0);
 -    one = tcg_constant_tl(1);
 -    mone = tcg_constant_tl(-1);
 -    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
 -
 -    /*
 -     * If overflow, set temp1 to 0, else source1.
 -     * This avoids a possible host trap, and produces the required result of 0.
 -     */
 -    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
 -    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
 -    tcg_gen_and_tl(temp1, temp1, temp2);
 -    tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1);
 -
 -    /*
 -     * If div by zero, set temp2 to 1, else source2.
 -     * This avoids a possible host trap, but produces an incorrect result.
 -     */
 -    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
 -
 -    tcg_gen_rem_tl(temp1, temp1, temp2);
 -
 -    /* If div by zero, the required result is the original dividend. */
 -    tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1);
 -
 -    tcg_temp_free(temp1);
 -    tcg_temp_free(temp2);
 -}
 -
 -static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
 -{
 -    TCGv temp, zero, one;
 -
 -    temp = tcg_temp_new();
 -    zero = tcg_constant_tl(0);
 -    one = tcg_constant_tl(1);
 -
 -    /*
 -     * If div by zero, set temp to 1, else source2.
 -     * This avoids a possible host trap, but produces an incorrect result.
 -     */
 -    tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2);
 -
 -    tcg_gen_remu_tl(temp, source1, temp);
 -
 -    /* If div by zero, the required result is the original dividend. */
 -    tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp);
 -
 -    tcg_temp_free(temp);
 -}
 -
  static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
  {
      target_ulong next_pc;
 diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvm.c.inc
 +++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
      return gen_arith(ctx, a, EXT_NONE, gen_mulh);
  }
 +static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
 +{
-+    TCGv rl = tcg_temp_new();
++    if (s->mstatus_fs == EXT_STATUS_DISABLED) {
-+    TCGv rh = tcg_temp_new();
++        return false;
 +    }
 +
-+    tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
++    switch (s->sew) {
-+    /* fix up for one negative */
++    case MO_16:
-+    tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
++        return s->cfg_ptr->ext_zvfhmin;
-+    tcg_gen_and_tl(rl, rl, arg2);
++    case MO_32:
-+    tcg_gen_sub_tl(ret, rh, rl);
++        return s->cfg_ptr->ext_zve32f;
-+
++    default:
-+    tcg_temp_free(rl);
++        return false;
-+    tcg_temp_free(rh);
++    }
 +}
 +
- static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
+ static bool require_scale_rvf(DisasContext *s)
  {
-     REQUIRE_EXT(ctx, RVM);
+     if (s->mstatus_fs == EXT_STATUS_DISABLED) {
-@@ -XXX,XX +XXX,XX @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
+@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
-     return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
+     }
      switch (s->sew) {
 -    case MO_8:
 -        return s->cfg_ptr->ext_zvfhmin;
      case MO_16:
          return s->cfg_ptr->ext_zve32f;
      case MO_32:
@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
  static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  {
      return opfv_widen_check(s, a) &&
 +           require_rvfmin(s) &&
             require_scale_rvfmin(s) &&
             (s->sew != MO_8);
  }
+@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
-+static void gen_div(TCGv ret, TCGv source1, TCGv source2)
+ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 +{
 +    TCGv temp1, temp2, zero, one, mone, min;
 +
 +    temp1 = tcg_temp_new();
 +    temp2 = tcg_temp_new();
 +    zero = tcg_constant_tl(0);
 +    one = tcg_constant_tl(1);
 +    mone = tcg_constant_tl(-1);
 +    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
 +
 +    /*
 +     * If overflow, set temp2 to 1, else source2.
 +     * This produces the required result of min.
 +     */
 +    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
 +    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
 +    tcg_gen_and_tl(temp1, temp1, temp2);
 +    tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2);
 +
 +    /*
 +     * If div by zero, set temp1 to -1 and temp2 to 1 to
 +     * produce the required result of -1.
 +     */
 +    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
 +    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2);
 +
 +    tcg_gen_div_tl(ret, temp1, temp2);
 +
 +    tcg_temp_free(temp1);
 +    tcg_temp_free(temp2);
 +}
 +
  static bool trans_div(DisasContext *ctx, arg_div *a)
  {
-     REQUIRE_EXT(ctx, RVM);
+     return opfv_narrow_check(s, a) &&
-     return gen_arith(ctx, a, EXT_SIGN, gen_div);
++           require_rvfmin(s) &&
             require_scale_rvfmin(s) &&
             (s->sew != MO_8);
  }
-+static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
-+{
-+    TCGv temp1, temp2, zero, one, max;
-+
-+    temp1 = tcg_temp_new();
-+    temp2 = tcg_temp_new();
-+    zero = tcg_constant_tl(0);
-+    one = tcg_constant_tl(1);
-+    max = tcg_constant_tl(~0);
-+
-+    /*
-+     * If div by zero, set temp1 to max and temp2 to 1 to
-+     * produce the required result of max.
-+     */
-+    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
-+    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
-+    tcg_gen_divu_tl(ret, temp1, temp2);
-+
-+    tcg_temp_free(temp1);
-+    tcg_temp_free(temp2);
-+}
-+
- static bool trans_divu(DisasContext *ctx, arg_divu *a)
- {
-     REQUIRE_EXT(ctx, RVM);
-     return gen_arith(ctx, a, EXT_ZERO, gen_divu);
- }
-+static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
-+{
-+    TCGv temp1, temp2, zero, one, mone, min;
-+
-+    temp1 = tcg_temp_new();
-+    temp2 = tcg_temp_new();
-+    zero = tcg_constant_tl(0);
-+    one = tcg_constant_tl(1);
-+    mone = tcg_constant_tl(-1);
-+    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
-+
-+    /*
-+     * If overflow, set temp1 to 0, else source1.
-+     * This avoids a possible host trap, and produces the required result of 0.
-+     */
-+    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
-+    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
-+    tcg_gen_and_tl(temp1, temp1, temp2);
-+    tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1);
-+
-+    /*
-+     * If div by zero, set temp2 to 1, else source2.
-+     * This avoids a possible host trap, but produces an incorrect result.
-+     */
-+    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
-+
-+    tcg_gen_rem_tl(temp1, temp1, temp2);
-+
-+    /* If div by zero, the required result is the original dividend. */
-+    tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1);
-+
-+    tcg_temp_free(temp1);
-+    tcg_temp_free(temp2);
-+}
-+
- static bool trans_rem(DisasContext *ctx, arg_rem *a)
- {
-     REQUIRE_EXT(ctx, RVM);
-     return gen_arith(ctx, a, EXT_SIGN, gen_rem);
- }
-+static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
-+{
-+    TCGv temp, zero, one;
-+
-+    temp = tcg_temp_new();
-+    zero = tcg_constant_tl(0);
-+    one = tcg_constant_tl(1);
-+
-+    /*
-+     * If div by zero, set temp to 1, else source2.
-+     * This avoids a possible host trap, but produces an incorrect result.
-+     */
-+    tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2);
-+
-+    tcg_gen_remu_tl(temp, source1, temp);
-+
-+    /* If div by zero, the required result is the original dividend. */
-+    tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp);
-+
-+    tcg_temp_free(temp);
-+}
-+
- static bool trans_remu(DisasContext *ctx, arg_remu *a)
- {
-     REQUIRE_EXT(ctx, RVM);
 --
-.31.1
+.45.1

-[PULL 33/33] target/riscv: Use {get,dest}_gpr for RVV
+[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Max Chou <max.chou@sifive.com>
-Remove gen_get_gpr, as the function becomes unused.
+The require_scale_rvf function only checks the double width operator for
 the vector floating point widen instructions, so most of the widen
 checking functions need to add require_rvf for single width operator.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+integer to double width float, so the opfxv_widen_check function doesn’t
-Message-id: 20210823195529.560295-25-richard.henderson@linaro.org
+need require_rvf for the single width operator(integer).
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                | 13 ++---
+ target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
- target/riscv/insn_trans/trans_rvv.c.inc | 74 +++++++------------------
+file changed, 5 insertions(+)
 files changed, 26 insertions(+), 61 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
-     g_assert_not_reached();
- }
--static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num)
--{
--    tcg_gen_mov_tl(t, get_gpr(ctx, reg_num, EXT_NONE));
--}
--
- static TCGv dest_gpr(DisasContext *ctx, int reg_num)
- {
-     if (reg_num == 0 || ctx->w) {
-@@ -XXX,XX +XXX,XX @@ void riscv_translate_init(void)
- {
-     int i;
--    /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */
--    /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
--    /* registers, unless you specifically block reads/writes to reg 0 */
-+    /*
-+     * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
-+     * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
-+     * unless you specifically block reads/writes to reg 0.
-+     */
-     cpu_gpr[0] = NULL;
-     for (i = 1; i < 32; i++) {
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf,  opfvf_check)
-         return false;
+ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
      }
 -    s2 = tcg_temp_new();
 -    dst = tcg_temp_new();
 +    s2 = get_gpr(ctx, a->rs2, EXT_ZERO);
 +    dst = dest_gpr(ctx, a->rd);
      /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
      if (a->rs1 == 0) {
          /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
          s1 = tcg_constant_tl(RV_VLEN_MAX);
      } else {
 -        s1 = tcg_temp_new();
 -        gen_get_gpr(ctx, s1, a->rs1);
 +        s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
      }
 -    gen_get_gpr(ctx, s2, a->rs2);
      gen_helper_vsetvl(dst, cpu_env, s1, s2);
      gen_set_gpr(ctx, a->rd, dst);
 +
      tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
      lookup_and_goto_ptr(ctx);
      ctx->base.is_jmp = DISAS_NORETURN;
 -
 -    tcg_temp_free(s1);
 -    tcg_temp_free(s2);
 -    tcg_temp_free(dst);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
      }
      s2 = tcg_constant_tl(a->zimm);
 -    dst = tcg_temp_new();
 +    dst = dest_gpr(ctx, a->rd);
      /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
      if (a->rs1 == 0) {
          /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
          s1 = tcg_constant_tl(RV_VLEN_MAX);
      } else {
 -        s1 = tcg_temp_new();
 -        gen_get_gpr(ctx, s1, a->rs1);
 +        s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
      }
      gen_helper_vsetvl(dst, cpu_env, s1, s2);
      gen_set_gpr(ctx, a->rd, dst);
 +
      gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
      ctx->base.is_jmp = DISAS_NORETURN;
 -
 -    tcg_temp_free(s1);
 -    tcg_temp_free(dst);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
 -    base = tcg_temp_new();
 +    base = get_gpr(s, rs1, EXT_NONE);
      /*
       * As simd_desc supports at most 256 bytes, and in this implementation,
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
       */
      desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 -    gen_get_gpr(s, base, rs1);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      tcg_temp_free_ptr(dest);
      tcg_temp_free_ptr(mask);
 -    tcg_temp_free(base);
      gen_set_label(over);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
 -    base = tcg_temp_new();
 -    stride = tcg_temp_new();
 +    base = get_gpr(s, rs1, EXT_NONE);
 +    stride = get_gpr(s, rs2, EXT_NONE);
      desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 -    gen_get_gpr(s, base, rs1);
 -    gen_get_gpr(s, stride, rs2);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
      tcg_temp_free_ptr(dest);
      tcg_temp_free_ptr(mask);
 -    tcg_temp_free(base);
 -    tcg_temp_free(stride);
      gen_set_label(over);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
      index = tcg_temp_new_ptr();
 -    base = tcg_temp_new();
 +    base = get_gpr(s, rs1, EXT_NONE);
      desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 -    gen_get_gpr(s, base, rs1);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
      tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
      tcg_temp_free_ptr(dest);
      tcg_temp_free_ptr(mask);
      tcg_temp_free_ptr(index);
 -    tcg_temp_free(base);
      gen_set_label(over);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
 -    base = tcg_temp_new();
 +    base = get_gpr(s, rs1, EXT_NONE);
      desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 -    gen_get_gpr(s, base, rs1);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      tcg_temp_free_ptr(dest);
      tcg_temp_free_ptr(mask);
 -    tcg_temp_free(base);
      gen_set_label(over);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
      index = tcg_temp_new_ptr();
 -    base = tcg_temp_new();
 +    base = get_gpr(s, rs1, EXT_NONE);
      desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 -    gen_get_gpr(s, base, rs1);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
      tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
      tcg_temp_free_ptr(dest);
      tcg_temp_free_ptr(mask);
      tcg_temp_free_ptr(index);
 -    tcg_temp_free(base);
      gen_set_label(over);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
      dest = tcg_temp_new_ptr();
      mask = tcg_temp_new_ptr();
      src2 = tcg_temp_new_ptr();
 -    src1 = tcg_temp_new();
 -    gen_get_gpr(s, src1, rs1);
 +    src1 = get_gpr(s, rs1, EXT_NONE);
      data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
      data = FIELD_DP32(data, VDATA, VM, vm);
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
      tcg_temp_free_ptr(dest);
      tcg_temp_free_ptr(mask);
      tcg_temp_free_ptr(src2);
 -    tcg_temp_free(src1);
      gen_set_label(over);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
      if (a->vm && s->vl_eq_vlmax) {
          TCGv_i64 src1 = tcg_temp_new_i64();
 -        TCGv tmp = tcg_temp_new();
 -        gen_get_gpr(s, tmp, a->rs1);
 -        tcg_gen_ext_tl_i64(src1, tmp);
 +        tcg_gen_ext_tl_i64(src1, get_gpr(s, a->rs1, EXT_SIGN));
          gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
                  src1, MAXSZ(s), MAXSZ(s));
          tcg_temp_free_i64(src1);
 -        tcg_temp_free(tmp);
          return true;
      }
      return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
@@ -XXX,XX +XXX,XX @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
      if (a->vm && s->vl_eq_vlmax) {
          TCGv_i32 src1 = tcg_temp_new_i32();
 -        TCGv tmp = tcg_temp_new();
 -        gen_get_gpr(s, tmp, a->rs1);
 -        tcg_gen_trunc_tl_i32(src1, tmp);
 +        tcg_gen_trunc_tl_i32(src1, get_gpr(s, a->rs1, EXT_NONE));
          tcg_gen_extract_i32(src1, src1, 0, s->sew + 3);
          gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
                  src1, MAXSZ(s), MAXSZ(s));
          tcg_temp_free_i32(src1);
 -        tcg_temp_free(tmp);
          return true;
      }
      return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
          TCGLabel *over = gen_new_label();
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 -        s1 = tcg_temp_new();
 -        gen_get_gpr(s, s1, a->rs1);
 +        s1 = get_gpr(s, a->rs1, EXT_SIGN);
          if (s->vl_eq_vlmax) {
              tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
              tcg_temp_free_i64(s1_i64);
          }
 -        tcg_temp_free(s1);
          gen_set_label(over);
          return true;
      }
@@ -XXX,XX +XXX,XX @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
          mask = tcg_temp_new_ptr();
          src2 = tcg_temp_new_ptr();
 -        dst = tcg_temp_new();
 +        dst = dest_gpr(s, a->rd);
          desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
          tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
@@ -XXX,XX +XXX,XX @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
          tcg_temp_free_ptr(mask);
          tcg_temp_free_ptr(src2);
 -        tcg_temp_free(dst);
          return true;
      }
      return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
          mask = tcg_temp_new_ptr();
          src2 = tcg_temp_new_ptr();
 -        dst = tcg_temp_new();
 +        dst = dest_gpr(s, a->rd);
          desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
          tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
@@ -XXX,XX +XXX,XX @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
          tcg_temp_free_ptr(mask);
          tcg_temp_free_ptr(src2);
 -        tcg_temp_free(dst);
          return true;
      }
      return false;
@@ -XXX,XX +XXX,XX @@ static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
  static bool trans_vext_x_v(DisasContext *s, arg_r *a)
  {
-     TCGv_i64 tmp = tcg_temp_new_i64();
+     return require_rvv(s) &&
--    TCGv dest = tcg_temp_new();
++           require_rvf(s) &&
-+    TCGv dest = dest_gpr(s, a->rd);
+            require_scale_rvf(s) &&
+            (s->sew != MO_8) &&
-     if (a->rs1 == 0) {
+            vext_check_isa_ill(s) &&
-         /* Special case vmv.x.s rd, vs2. */
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
-@@ -XXX,XX +XXX,XX @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a)
+ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
-         int vlmax = s->vlen >> (3 + s->sew);
+ {
-         vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
+     return require_rvv(s) &&
-     }
++           require_rvf(s) &&
-+
+            require_scale_rvf(s) &&
-     tcg_gen_trunc_i64_tl(dest, tmp);
+            (s->sew != MO_8) &&
-     gen_set_gpr(s, a->rd, dest);
+            vext_check_isa_ill(s) &&
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
--    tcg_temp_free(dest);
+ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
-     tcg_temp_free_i64(tmp);
+ {
-     return true;
+     return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
  static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
  static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return reduction_widen_check(s, a) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8);
  }
 --
-.31.1
+.45.1

-[PULL 13/33] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
+[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Max Chou <max.chou@sifive.com>
-We will require the context to handle RV64 word operations.
+The opfv_narrow_check needs to check the single width float operator by
 require_rvf.
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
 Message-id: 20210823195529.560295-5-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                | 58 ++++++++++++-------------
+ target/riscv/insn_trans/trans_rvv.c.inc | 1 +
- target/riscv/insn_trans/trans_rva.c.inc | 18 ++++----
+file changed, 1 insertion(+)
  target/riscv/insn_trans/trans_rvb.c.inc |  4 +-
  target/riscv/insn_trans/trans_rvd.c.inc | 32 +++++++-------
  target/riscv/insn_trans/trans_rvf.c.inc | 32 +++++++-------
  target/riscv/insn_trans/trans_rvh.c.inc | 52 +++++++++++-----------
  target/riscv/insn_trans/trans_rvi.c.inc | 44 +++++++++----------
  target/riscv/insn_trans/trans_rvm.c.inc | 12 ++---
  target/riscv/insn_trans/trans_rvv.c.inc | 36 +++++++--------
 files changed, 144 insertions(+), 144 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
- /* Wrapper for getting reg values - need to check of reg is zero since
-  * cpu_gpr[0] is not actually allocated
-  */
--static inline void gen_get_gpr(TCGv t, int reg_num)
-+static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num)
- {
-     if (reg_num == 0) {
-         tcg_gen_movi_tl(t, 0);
-@@ -XXX,XX +XXX,XX @@ static inline void gen_get_gpr(TCGv t, int reg_num)
-  * since we usually avoid calling the OP_TYPE_gen function if we see a write to
-  * $zero
-  */
--static inline void gen_set_gpr(int reg_num_dst, TCGv t)
-+static void gen_set_gpr(DisasContext *ctx, int reg_num_dst, TCGv t)
- {
-     if (reg_num_dst != 0) {
-         tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t);
-@@ -XXX,XX +XXX,XX @@ static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
-     TCGv source1;
-     source1 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
-+    gen_get_gpr(ctx, source1, a->rs1);
-     (*func)(source1, source1, a->imm);
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
-     source1 = tcg_temp_new();
-     source2 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
-+    gen_get_gpr(ctx, source1, a->rs1);
-     tcg_gen_movi_tl(source2, a->imm);
-     (*func)(source1, source1, source2);
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     tcg_temp_free(source2);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
-     source1 = tcg_temp_new();
-     source2 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
--    gen_get_gpr(source2, a->rs2);
-+    gen_get_gpr(ctx, source1, a->rs1);
-+    gen_get_gpr(ctx, source2, a->rs2);
-     tcg_gen_ext32s_tl(source1, source1);
-     tcg_gen_ext32s_tl(source2, source2);
-     (*func)(source1, source1, source2);
-     tcg_gen_ext32s_tl(source1, source1);
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     tcg_temp_free(source2);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
-     source1 = tcg_temp_new();
-     source2 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
--    gen_get_gpr(source2, a->rs2);
-+    gen_get_gpr(ctx, source1, a->rs1);
-+    gen_get_gpr(ctx, source2, a->rs2);
-     tcg_gen_ext32u_tl(source1, source1);
-     tcg_gen_ext32u_tl(source2, source2);
-     (*func)(source1, source1, source2);
-     tcg_gen_ext32s_tl(source1, source1);
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     tcg_temp_free(source2);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
-     TCGv source1 = tcg_temp_new();
-     TCGv source2;
--    gen_get_gpr(source1, a->rs1);
-+    gen_get_gpr(ctx, source1, a->rs1);
-     if (a->shamt == (TARGET_LONG_BITS - 8)) {
-         /* rev8, byte swaps */
-@@ -XXX,XX +XXX,XX @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
-         tcg_temp_free(source2);
-     }
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool gen_arith(DisasContext *ctx, arg_r *a,
-     source1 = tcg_temp_new();
-     source2 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
--    gen_get_gpr(source2, a->rs2);
-+    gen_get_gpr(ctx, source1, a->rs1);
-+    gen_get_gpr(ctx, source2, a->rs2);
-     (*func)(source1, source1, source2);
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     tcg_temp_free(source2);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
-     TCGv source1 = tcg_temp_new();
-     TCGv source2 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
--    gen_get_gpr(source2, a->rs2);
-+    gen_get_gpr(ctx, source1, a->rs1);
-+    gen_get_gpr(ctx, source2, a->rs2);
-     tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
-     (*func)(source1, source1, source2);
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     tcg_temp_free(source2);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool gen_shifti(DisasContext *ctx, arg_shift *a,
-     TCGv source1 = tcg_temp_new();
-     TCGv source2 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
-+    gen_get_gpr(ctx, source1, a->rs1);
-     tcg_gen_movi_tl(source2, a->shamt);
-     (*func)(source1, source1, source2);
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     tcg_temp_free(source2);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool gen_shiftw(DisasContext *ctx, arg_r *a,
-     TCGv source1 = tcg_temp_new();
-     TCGv source2 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
--    gen_get_gpr(source2, a->rs2);
-+    gen_get_gpr(ctx, source1, a->rs1);
-+    gen_get_gpr(ctx, source2, a->rs2);
-     tcg_gen_andi_tl(source2, source2, 31);
-     (*func)(source1, source1, source2);
-     tcg_gen_ext32s_tl(source1, source1);
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     tcg_temp_free(source2);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
-     TCGv source1 = tcg_temp_new();
-     TCGv source2 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
-+    gen_get_gpr(ctx, source1, a->rs1);
-     tcg_gen_movi_tl(source2, a->shamt);
-     (*func)(source1, source1, source2);
-     tcg_gen_ext32s_tl(source1, source1);
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     tcg_temp_free(source2);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a,
- {
-     TCGv source = tcg_temp_new();
--    gen_get_gpr(source, a->rs1);
-+    gen_get_gpr(ctx, source, a->rs1);
-     (*func)(source, source);
--    gen_set_gpr(a->rd, source);
-+    gen_set_gpr(ctx, a->rd, source);
-     tcg_temp_free(source);
-     return true;
- }
-diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rva.c.inc
-+++ b/target/riscv/insn_trans/trans_rva.c.inc
-@@ -XXX,XX +XXX,XX @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
- {
-     TCGv src1 = tcg_temp_new();
-     /* Put addr in load_res, data in load_val.  */
--    gen_get_gpr(src1, a->rs1);
-+    gen_get_gpr(ctx, src1, a->rs1);
-     if (a->rl) {
-         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
-     }
-@@ -XXX,XX +XXX,XX @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
-         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
-     }
-     tcg_gen_mov_tl(load_res, src1);
--    gen_set_gpr(a->rd, load_val);
-+    gen_set_gpr(ctx, a->rd, load_val);
-     tcg_temp_free(src1);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
-     TCGLabel *l1 = gen_new_label();
-     TCGLabel *l2 = gen_new_label();
--    gen_get_gpr(src1, a->rs1);
-+    gen_get_gpr(ctx, src1, a->rs1);
-     tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
--    gen_get_gpr(src2, a->rs2);
-+    gen_get_gpr(ctx, src2, a->rs2);
-     /*
-      * Note that the TCG atomic primitives are SC,
-      * so we can ignore AQ/RL along this path.
-@@ -XXX,XX +XXX,XX @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
-     tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
-                               ctx->mem_idx, mop);
-     tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
--    gen_set_gpr(a->rd, dat);
-+    gen_set_gpr(ctx, a->rd, dat);
-     tcg_gen_br(l2);
-     gen_set_label(l1);
-@@ -XXX,XX +XXX,XX @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
-      */
-     tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
-     tcg_gen_movi_tl(dat, 1);
--    gen_set_gpr(a->rd, dat);
-+    gen_set_gpr(ctx, a->rd, dat);
-     gen_set_label(l2);
-     /*
-@@ -XXX,XX +XXX,XX @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
-     TCGv src1 = tcg_temp_new();
-     TCGv src2 = tcg_temp_new();
--    gen_get_gpr(src1, a->rs1);
--    gen_get_gpr(src2, a->rs2);
-+    gen_get_gpr(ctx, src1, a->rs1);
-+    gen_get_gpr(ctx, src2, a->rs2);
-     (*func)(src2, src1, src2, ctx->mem_idx, mop);
--    gen_set_gpr(a->rd, src2);
-+    gen_set_gpr(ctx, a->rd, src2);
-     tcg_temp_free(src1);
-     tcg_temp_free(src2);
-     return true;
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
-     REQUIRE_EXT(ctx, RVB);
-     TCGv source1 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
-+    gen_get_gpr(ctx, source1, a->rs1);
-     if (a->shamt < 32) {
-         tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
-@@ -XXX,XX +XXX,XX @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
-         tcg_gen_shli_tl(source1, source1, a->shamt);
-     }
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     return true;
- }
-diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvd.c.inc
-+++ b/target/riscv/insn_trans/trans_rvd.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
-     REQUIRE_FPU;
-     REQUIRE_EXT(ctx, RVD);
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_addi_tl(t0, t0, a->imm);
-     tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
-     REQUIRE_FPU;
-     REQUIRE_EXT(ctx, RVD);
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_addi_tl(t0, t0, a->imm);
-     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
-@@ -XXX,XX +XXX,XX @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
-     TCGv t0 = tcg_temp_new();
-     gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
-     TCGv t0 = tcg_temp_new();
-     gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
-     TCGv t0 = tcg_temp_new();
-     gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
-     TCGv t0 = tcg_temp_new();
-     gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
-     TCGv t0 = tcg_temp_new();
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
-     TCGv t0 = tcg_temp_new();
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
-     REQUIRE_EXT(ctx, RVD);
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
-     REQUIRE_EXT(ctx, RVD);
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
-     TCGv t0 = tcg_temp_new();
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
-     TCGv t0 = tcg_temp_new();
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
-     REQUIRE_EXT(ctx, RVD);
- #ifdef TARGET_RISCV64
--    gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
-+    gen_set_gpr(ctx, a->rd, cpu_fpr[a->rs1]);
-     return true;
- #else
-     qemu_build_not_reached();
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
-     REQUIRE_EXT(ctx, RVD);
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
-     REQUIRE_EXT(ctx, RVD);
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
- #ifdef TARGET_RISCV64
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
-     tcg_temp_free(t0);
-diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvf.c.inc
-+++ b/target/riscv/insn_trans/trans_rvf.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
-     REQUIRE_FPU;
-     REQUIRE_EXT(ctx, RVF);
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_addi_tl(t0, t0, a->imm);
-     tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
-     REQUIRE_FPU;
-     REQUIRE_EXT(ctx, RVF);
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_addi_tl(t0, t0, a->imm);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
-     TCGv t0 = tcg_temp_new();
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
-     TCGv t0 = tcg_temp_new();
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
-     tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
- #endif
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
-     REQUIRE_EXT(ctx, RVF);
-     TCGv t0 = tcg_temp_new();
-     gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
-     REQUIRE_EXT(ctx, RVF);
-     TCGv t0 = tcg_temp_new();
-     gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
-     REQUIRE_EXT(ctx, RVF);
-     TCGv t0 = tcg_temp_new();
-     gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
-     gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
-     REQUIRE_EXT(ctx, RVF);
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
-     REQUIRE_EXT(ctx, RVF);
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
-     REQUIRE_EXT(ctx, RVF);
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
-     gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
-     TCGv t0 = tcg_temp_new();
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
-     TCGv t0 = tcg_temp_new();
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
--    gen_set_gpr(a->rd, t0);
-+    gen_set_gpr(ctx, a->rd, t0);
-     tcg_temp_free(t0);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
-     REQUIRE_EXT(ctx, RVF);
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
-     REQUIRE_EXT(ctx, RVF);
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     gen_set_rm(ctx, a->rm);
-     gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
-diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvh.c.inc
-+++ b/target/riscv/insn_trans/trans_rvh.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
-     check_access(ctx);
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_SB);
--    gen_set_gpr(a->rd, t1);
-+    gen_set_gpr(ctx, a->rd, t1);
-     tcg_temp_free(t0);
-     tcg_temp_free(t1);
-@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
-     check_access(ctx);
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESW);
--    gen_set_gpr(a->rd, t1);
-+    gen_set_gpr(ctx, a->rd, t1);
-     tcg_temp_free(t0);
-     tcg_temp_free(t1);
-@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a)
-     check_access(ctx);
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESL);
--    gen_set_gpr(a->rd, t1);
-+    gen_set_gpr(ctx, a->rd, t1);
-     tcg_temp_free(t0);
-     tcg_temp_free(t1);
-@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a)
-     check_access(ctx);
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_UB);
--    gen_set_gpr(a->rd, t1);
-+    gen_set_gpr(ctx, a->rd, t1);
-     tcg_temp_free(t0);
-     tcg_temp_free(t1);
-@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a)
-     check_access(ctx);
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEUW);
--    gen_set_gpr(a->rd, t1);
-+    gen_set_gpr(ctx, a->rd, t1);
-     tcg_temp_free(t0);
-     tcg_temp_free(t1);
-@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a)
-     check_access(ctx);
--    gen_get_gpr(t0, a->rs1);
--    gen_get_gpr(dat, a->rs2);
-+    gen_get_gpr(ctx, t0, a->rs1);
-+    gen_get_gpr(ctx, dat, a->rs2);
-     tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_SB);
-@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a)
-     check_access(ctx);
--    gen_get_gpr(t0, a->rs1);
--    gen_get_gpr(dat, a->rs2);
-+    gen_get_gpr(ctx, t0, a->rs1);
-+    gen_get_gpr(ctx, dat, a->rs2);
-     tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESW);
-@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
-     check_access(ctx);
--    gen_get_gpr(t0, a->rs1);
--    gen_get_gpr(dat, a->rs2);
-+    gen_get_gpr(ctx, t0, a->rs1);
-+    gen_get_gpr(ctx, dat, a->rs2);
-     tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESL);
-@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
-     check_access(ctx);
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEUL);
--    gen_set_gpr(a->rd, t1);
-+    gen_set_gpr(ctx, a->rd, t1);
-     tcg_temp_free(t0);
-     tcg_temp_free(t1);
-@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
-     check_access(ctx);
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEQ);
--    gen_set_gpr(a->rd, t1);
-+    gen_set_gpr(ctx, a->rd, t1);
-     tcg_temp_free(t0);
-     tcg_temp_free(t1);
-@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
-     check_access(ctx);
--    gen_get_gpr(t0, a->rs1);
--    gen_get_gpr(dat, a->rs2);
-+    gen_get_gpr(ctx, t0, a->rs1);
-+    gen_get_gpr(ctx, dat, a->rs2);
-     tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEQ);
-@@ -XXX,XX +XXX,XX @@ static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
-     check_access(ctx);
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     gen_helper_hyp_hlvx_hu(t1, cpu_env, t0);
--    gen_set_gpr(a->rd, t1);
-+    gen_set_gpr(ctx, a->rd, t1);
-     tcg_temp_free(t0);
-     tcg_temp_free(t1);
-@@ -XXX,XX +XXX,XX @@ static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a)
-     check_access(ctx);
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     gen_helper_hyp_hlvx_wu(t1, cpu_env, t0);
--    gen_set_gpr(a->rd, t1);
-+    gen_set_gpr(ctx, a->rd, t1);
-     tcg_temp_free(t0);
-     tcg_temp_free(t1);
-diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvi.c.inc
-+++ b/target/riscv/insn_trans/trans_rvi.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
-     TCGv t0 = tcg_temp_new();
--    gen_get_gpr(cpu_pc, a->rs1);
-+    gen_get_gpr(ctx, cpu_pc, a->rs1);
-     tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
-     tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
-@@ -XXX,XX +XXX,XX @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
-     TCGv source1, source2;
-     source1 = tcg_temp_new();
-     source2 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
--    gen_get_gpr(source2, a->rs2);
-+    gen_get_gpr(ctx, source1, a->rs1);
-+    gen_get_gpr(ctx, source2, a->rs2);
-     tcg_gen_brcond_tl(cond, source1, source2, l);
-     gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
-@@ -XXX,XX +XXX,XX @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
- {
-     TCGv t0 = tcg_temp_new();
-     TCGv t1 = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_addi_tl(t0, t0, a->imm);
-     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
--    gen_set_gpr(a->rd, t1);
-+    gen_set_gpr(ctx, a->rd, t1);
-     tcg_temp_free(t0);
-     tcg_temp_free(t1);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
- {
-     TCGv t0 = tcg_temp_new();
-     TCGv dat = tcg_temp_new();
--    gen_get_gpr(t0, a->rs1);
-+    gen_get_gpr(ctx, t0, a->rs1);
-     tcg_gen_addi_tl(t0, t0, a->imm);
--    gen_get_gpr(dat, a->rs2);
-+    gen_get_gpr(ctx, dat, a->rs2);
-     tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
-     tcg_temp_free(t0);
-@@ -XXX,XX +XXX,XX @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
- {
-     REQUIRE_64BIT(ctx);
-     TCGv t = tcg_temp_new();
--    gen_get_gpr(t, a->rs1);
-+    gen_get_gpr(ctx, t, a->rs1);
-     tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
-     /* sign-extend for W instructions */
-     tcg_gen_ext32s_tl(t, t);
--    gen_set_gpr(a->rd, t);
-+    gen_set_gpr(ctx, a->rd, t);
-     tcg_temp_free(t);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
- {
-     REQUIRE_64BIT(ctx);
-     TCGv t = tcg_temp_new();
--    gen_get_gpr(t, a->rs1);
-+    gen_get_gpr(ctx, t, a->rs1);
-     tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
--    gen_set_gpr(a->rd, t);
-+    gen_set_gpr(ctx, a->rd, t);
-     tcg_temp_free(t);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
-     TCGv source1 = tcg_temp_new();
-     TCGv source2 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
--    gen_get_gpr(source2, a->rs2);
-+    gen_get_gpr(ctx, source1, a->rs1);
-+    gen_get_gpr(ctx, source2, a->rs2);
-     tcg_gen_andi_tl(source2, source2, 0x1F);
-     tcg_gen_shl_tl(source1, source1, source2);
-     tcg_gen_ext32s_tl(source1, source1);
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     tcg_temp_free(source2);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
-     TCGv source1 = tcg_temp_new();
-     TCGv source2 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
--    gen_get_gpr(source2, a->rs2);
-+    gen_get_gpr(ctx, source1, a->rs1);
-+    gen_get_gpr(ctx, source2, a->rs2);
-     /* clear upper 32 */
-     tcg_gen_ext32u_tl(source1, source1);
-@@ -XXX,XX +XXX,XX @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
-     tcg_gen_shr_tl(source1, source1, source2);
-     tcg_gen_ext32s_tl(source1, source1);
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     tcg_temp_free(source2);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
-     TCGv source1 = tcg_temp_new();
-     TCGv source2 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
--    gen_get_gpr(source2, a->rs2);
-+    gen_get_gpr(ctx, source1, a->rs1);
-+    gen_get_gpr(ctx, source2, a->rs2);
-     /*
-      * first, trick to get it to act like working on 32 bits (get rid of
-@@ -XXX,XX +XXX,XX @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
-     tcg_gen_andi_tl(source2, source2, 0x1F);
-     tcg_gen_sar_tl(source1, source1, source2);
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     tcg_temp_free(source2);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
-     csr_store = tcg_temp_new(); \
-     dest = tcg_temp_new(); \
-     rs1_pass = tcg_temp_new(); \
--    gen_get_gpr(source1, a->rs1); \
-+    gen_get_gpr(ctx, source1, a->rs1); \
-     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
-     tcg_gen_movi_tl(rs1_pass, a->rs1); \
-     tcg_gen_movi_tl(csr_store, a->csr); \
-@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
- } while (0)
- #define RISCV_OP_CSR_POST do {\
--    gen_set_gpr(a->rd, dest); \
-+    gen_set_gpr(ctx, a->rd, dest); \
-     tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
-     exit_tb(ctx); \
-     ctx->base.is_jmp = DISAS_NORETURN; \
-diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvm.c.inc
-+++ b/target/riscv/insn_trans/trans_rvm.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
-     REQUIRE_EXT(ctx, RVM);
-     TCGv source1 = tcg_temp_new();
-     TCGv source2 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
--    gen_get_gpr(source2, a->rs2);
-+    gen_get_gpr(ctx, source1, a->rs1);
-+    gen_get_gpr(ctx, source2, a->rs2);
-     tcg_gen_muls2_tl(source2, source1, source1, source2);
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     tcg_temp_free(source2);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
-     REQUIRE_EXT(ctx, RVM);
-     TCGv source1 = tcg_temp_new();
-     TCGv source2 = tcg_temp_new();
--    gen_get_gpr(source1, a->rs1);
--    gen_get_gpr(source2, a->rs2);
-+    gen_get_gpr(ctx, source1, a->rs1);
-+    gen_get_gpr(ctx, source2, a->rs2);
-     tcg_gen_mulu2_tl(source2, source1, source1, source2);
--    gen_set_gpr(a->rd, source1);
-+    gen_set_gpr(ctx, a->rd, source1);
-     tcg_temp_free(source1);
-     tcg_temp_free(source2);
-     return true;
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
-         s1 = tcg_constant_tl(RV_VLEN_MAX);
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
-     } else {
+ {
-         s1 = tcg_temp_new();
+     return opfv_narrow_check(s, a) &&
--        gen_get_gpr(s1, a->rs1);
++           require_rvf(s) &&
-+        gen_get_gpr(ctx, s1, a->rs1);
+            require_scale_rvf(s) &&
-     }
+            (s->sew != MO_8);
--    gen_get_gpr(s2, a->rs2);
+ }
 +    gen_get_gpr(ctx, s2, a->rs2);
      gen_helper_vsetvl(dst, cpu_env, s1, s2);
 -    gen_set_gpr(a->rd, dst);
 +    gen_set_gpr(ctx, a->rd, dst);
      tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
      lookup_and_goto_ptr(ctx);
      ctx->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
          s1 = tcg_constant_tl(RV_VLEN_MAX);
      } else {
          s1 = tcg_temp_new();
 -        gen_get_gpr(s1, a->rs1);
 +        gen_get_gpr(ctx, s1, a->rs1);
      }
      gen_helper_vsetvl(dst, cpu_env, s1, s2);
 -    gen_set_gpr(a->rd, dst);
 +    gen_set_gpr(ctx, a->rd, dst);
      gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
      ctx->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
       */
      desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 -    gen_get_gpr(base, rs1);
 +    gen_get_gpr(s, base, rs1);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
      stride = tcg_temp_new();
      desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 -    gen_get_gpr(base, rs1);
 -    gen_get_gpr(stride, rs2);
 +    gen_get_gpr(s, base, rs1);
 +    gen_get_gpr(s, stride, rs2);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
      base = tcg_temp_new();
      desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 -    gen_get_gpr(base, rs1);
 +    gen_get_gpr(s, base, rs1);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
      tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      base = tcg_temp_new();
      desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 -    gen_get_gpr(base, rs1);
 +    gen_get_gpr(s, base, rs1);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
      base = tcg_temp_new();
      desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 -    gen_get_gpr(base, rs1);
 +    gen_get_gpr(s, base, rs1);
      tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
      tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
      tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
      mask = tcg_temp_new_ptr();
      src2 = tcg_temp_new_ptr();
      src1 = tcg_temp_new();
 -    gen_get_gpr(src1, rs1);
 +    gen_get_gpr(s, src1, rs1);
      data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
      data = FIELD_DP32(data, VDATA, VM, vm);
@@ -XXX,XX +XXX,XX @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
          TCGv_i64 src1 = tcg_temp_new_i64();
          TCGv tmp = tcg_temp_new();
 -        gen_get_gpr(tmp, a->rs1);
 +        gen_get_gpr(s, tmp, a->rs1);
          tcg_gen_ext_tl_i64(src1, tmp);
          gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
                  src1, MAXSZ(s), MAXSZ(s));
@@ -XXX,XX +XXX,XX @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
          TCGv_i32 src1 = tcg_temp_new_i32();
          TCGv tmp = tcg_temp_new();
 -        gen_get_gpr(tmp, a->rs1);
 +        gen_get_gpr(s, tmp, a->rs1);
          tcg_gen_trunc_tl_i32(src1, tmp);
          tcg_gen_extract_i32(src1, src1, 0, s->sew + 3);
          gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
          s1 = tcg_temp_new();
 -        gen_get_gpr(s1, a->rs1);
 +        gen_get_gpr(s, s1, a->rs1);
          if (s->vl_eq_vlmax) {
              tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
@@ -XXX,XX +XXX,XX @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
          tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
          gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc);
 -        gen_set_gpr(a->rd, dst);
 +        gen_set_gpr(s, a->rd, dst);
          tcg_temp_free_ptr(mask);
          tcg_temp_free_ptr(src2);
@@ -XXX,XX +XXX,XX @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
          tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
          gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
 -        gen_set_gpr(a->rd, dst);
 +        gen_set_gpr(s, a->rd, dst);
          tcg_temp_free_ptr(mask);
          tcg_temp_free_ptr(src2);
@@ -XXX,XX +XXX,XX @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a)
          vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
      }
      tcg_gen_trunc_i64_tl(dest, tmp);
 -    gen_set_gpr(a->rd, dest);
 +    gen_set_gpr(s, a->rd, dest);
      tcg_temp_free(dest);
      tcg_temp_free_i64(tmp);
 --
-.31.1
+.45.1

-[PULL 12/33] target/riscv: Clean up division helpers
+[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Max Chou <max.chou@sifive.com>
-Utilize the condition in the movcond more; this allows some of
+If the checking functions check both the single and double width
-the setcond that were feeding into movcond to be removed.
+operators at the same time, then the single width operator checking
-Do not write into source1 and source2.  Re-name "condN" to "tempN"
+functions (require_rvf[min]) will check whether the SEW is 8.
 and use the temporaries for more than holding conditions.
-Tested-by: Bin Meng <bmeng.cn@gmail.com>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
 Message-id: 20210823195529.560295-4-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c | 174 ++++++++++++++++++++-------------------
+ target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
-file changed, 91 insertions(+), 83 deletions(-)
+file changed, 4 insertions(+), 12 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/translate.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
+     return require_rvv(s) &&
- static void gen_div(TCGv ret, TCGv source1, TCGv source2)
+            require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_ds(s, a->rd, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dd(s, a->rd, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  {
--    TCGv cond1, cond2, zeroreg, resultopt1;
+     return opfv_widen_check(s, a) &&
-+    TCGv temp1, temp2, zero, one, mone, min;
+            require_rvfmin(s) &&
-+
+-           require_scale_rvfmin(s) &&
-+    temp1 = tcg_temp_new();
+-           (s->sew != MO_8);
-+    temp2 = tcg_temp_new();
++           require_scale_rvfmin(s);
 +    zero = tcg_constant_tl(0);
 +    one = tcg_constant_tl(1);
 +    mone = tcg_constant_tl(-1);
 +    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
 +
      /*
 -     * Handle by altering args to tcg_gen_div to produce req'd results:
 -     * For overflow: want source1 in source1 and 1 in source2
 -     * For div by zero: want -1 in source1 and 1 in source2 -> -1 result
 +     * If overflow, set temp2 to 1, else source2.
 +     * This produces the required result of min.
       */
 -    cond1 = tcg_temp_new();
 -    cond2 = tcg_temp_new();
 -    zeroreg = tcg_constant_tl(0);
 -    resultopt1 = tcg_temp_new();
 -
 -    tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
 -    tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
 -    tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
 -                        ((target_ulong)1) << (TARGET_LONG_BITS - 1));
 -    tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
 -    tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
 -    /* if div by zero, set source1 to -1, otherwise don't change */
 -    tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
 -            resultopt1);
 -    /* if overflow or div by zero, set source2 to 1, else don't change */
 -    tcg_gen_or_tl(cond1, cond1, cond2);
 -    tcg_gen_movi_tl(resultopt1, (target_ulong)1);
 -    tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
 -            resultopt1);
 -    tcg_gen_div_tl(ret, source1, source2);
 -
 -    tcg_temp_free(cond1);
 -    tcg_temp_free(cond2);
 -    tcg_temp_free(resultopt1);
 +    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
 +    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
 +    tcg_gen_and_tl(temp1, temp1, temp2);
 +    tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2);
 +
 +    /*
 +     * If div by zero, set temp1 to -1 and temp2 to 1 to
 +     * produce the required result of -1.
 +     */
 +    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
 +    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2);
 +
 +    tcg_gen_div_tl(ret, temp1, temp2);
 +
 +    tcg_temp_free(temp1);
 +    tcg_temp_free(temp2);
  }
- static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
+ #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
  {
--    TCGv cond1, zeroreg, resultopt1;
+     return opfv_narrow_check(s, a) &&
--    cond1 = tcg_temp_new();
+            require_rvfmin(s) &&
-+    TCGv temp1, temp2, zero, one, max;
+-           require_scale_rvfmin(s) &&
+-           (s->sew != MO_8);
--    zeroreg = tcg_constant_tl(0);
++           require_scale_rvfmin(s);
 -    resultopt1 = tcg_temp_new();
 +    temp1 = tcg_temp_new();
 +    temp2 = tcg_temp_new();
 +    zero = tcg_constant_tl(0);
 +    one = tcg_constant_tl(1);
 +    max = tcg_constant_tl(~0);
 -    tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
 -    tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
 -    tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
 -            resultopt1);
 -    tcg_gen_movi_tl(resultopt1, (target_ulong)1);
 -    tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
 -            resultopt1);
 -    tcg_gen_divu_tl(ret, source1, source2);
 +    /*
 +     * If div by zero, set temp1 to max and temp2 to 1 to
 +     * produce the required result of max.
 +     */
 +    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
 +    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
 +    tcg_gen_divu_tl(ret, temp1, temp2);
 -    tcg_temp_free(cond1);
 -    tcg_temp_free(resultopt1);
 +    tcg_temp_free(temp1);
 +    tcg_temp_free(temp2);
  }
- static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
  {
--    TCGv cond1, cond2, zeroreg, resultopt1;
+     return opfv_narrow_check(s, a) &&
--
+            require_rvf(s) &&
--    cond1 = tcg_temp_new();
+-           require_scale_rvf(s) &&
--    cond2 = tcg_temp_new();
+-           (s->sew != MO_8);
--    zeroreg = tcg_constant_tl(0);
++           require_scale_rvf(s);
 -    resultopt1 = tcg_temp_new();
 -
 -    tcg_gen_movi_tl(resultopt1, 1L);
 -    tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
 -    tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
 -                        (target_ulong)1 << (TARGET_LONG_BITS - 1));
 -    tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
 -    tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
 -    /* if overflow or div by zero, set source2 to 1, else don't change */
 -    tcg_gen_or_tl(cond2, cond1, cond2);
 -    tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
 -            resultopt1);
 -    tcg_gen_rem_tl(resultopt1, source1, source2);
 -    /* if div by zero, just return the original dividend */
 -    tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
 -            source1);
 -
 -    tcg_temp_free(cond1);
 -    tcg_temp_free(cond2);
 -    tcg_temp_free(resultopt1);
 +    TCGv temp1, temp2, zero, one, mone, min;
 +
 +    temp1 = tcg_temp_new();
 +    temp2 = tcg_temp_new();
 +    zero = tcg_constant_tl(0);
 +    one = tcg_constant_tl(1);
 +    mone = tcg_constant_tl(-1);
 +    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
 +
 +    /*
 +     * If overflow, set temp1 to 0, else source1.
 +     * This avoids a possible host trap, and produces the required result of 0.
 +     */
 +    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
 +    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
 +    tcg_gen_and_tl(temp1, temp1, temp2);
 +    tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1);
 +
 +    /*
 +     * If div by zero, set temp2 to 1, else source2.
 +     * This avoids a possible host trap, but produces an incorrect result.
 +     */
 +    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
 +
 +    tcg_gen_rem_tl(temp1, temp1, temp2);
 +
 +    /* If div by zero, the required result is the original dividend. */
 +    tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1);
 +
 +    tcg_temp_free(temp1);
 +    tcg_temp_free(temp2);
  }
- static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
+ #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
  {
--    TCGv cond1, zeroreg, resultopt1;
+     return reduction_widen_check(s, a) &&
--    cond1 = tcg_temp_new();
+            require_rvf(s) &&
--    zeroreg = tcg_constant_tl(0);
+-           require_scale_rvf(s) &&
--    resultopt1 = tcg_temp_new();
+-           (s->sew != MO_8);
--
++           require_scale_rvf(s);
 -    tcg_gen_movi_tl(resultopt1, (target_ulong)1);
 -    tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
 -    tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
 -            resultopt1);
 -    tcg_gen_remu_tl(resultopt1, source1, source2);
 -    /* if div by zero, just return the original dividend */
 -    tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
 -            source1);
 -
 -    tcg_temp_free(cond1);
 -    tcg_temp_free(resultopt1);
 +    TCGv temp, zero, one;
 +
 +    temp = tcg_temp_new();
 +    zero = tcg_constant_tl(0);
 +    one = tcg_constant_tl(1);
 +
 +    /*
 +     * If div by zero, set temp to 1, else source2.
 +     * This avoids a possible host trap, but produces an incorrect result.
 +     */
 +    tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2);
 +
 +    tcg_gen_remu_tl(temp, source1, temp);
 +
 +    /* If div by zero, the required result is the original dividend. */
 +    tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp);
 +
 +    tcg_temp_free(temp);
  }
- static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
+ GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
 --
-.31.1
+.45.1

-[PULL 22/33] target/riscv: Use extracts for sraiw and srliw
+[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-These operations can be done in one instruction on some hosts.
+raise_mmu_exception(), as is today, is prioritizing guest page faults by
 checking first if virt_enabled && !first_stage, and then considering the
 regular inst/load/store faults.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+There's no mention in the spec about guest page fault being a higher
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+priority that PMP faults. In fact, privileged spec section 3.7.1 says:
 "Attempting to fetch an instruction from a PMP region that does not have
 execute permissions raises an instruction access-fault exception.
 Attempting to execute a load or load-reserved instruction which accesses
 a physical address within a PMP region without read permissions raises a
 load access-fault exception. Attempting to execute a store,
 store-conditional, or AMO instruction which accesses a physical address
 within a PMP region without write permissions raises a store
 access-fault exception."
 So, in fact, we're doing it wrong - PMP faults should always be thrown,
 regardless of also being a first or second stage fault.
 The way riscv_cpu_tlb_fill() and get_physical_address() work is
 adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
 reflected in the 'pmp_violation' flag. What we need is to change
 raise_mmu_exception() to prioritize it.
 Reported-by: Joseph Chan <jchan@ventanamicro.com>
 Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210823195529.560295-14-richard.henderson@linaro.org
+Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvi.c.inc | 14 ++++++++++++--
+ target/riscv/cpu_helper.c | 22 ++++++++++++----------
-file changed, 12 insertions(+), 2 deletions(-)
+file changed, 12 insertions(+), 10 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvi.c.inc
+--- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/insn_trans/trans_rvi.c.inc
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
+@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
-     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
- }
+     switch (access_type) {
+     case MMU_INST_FETCH:
-+static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
+-        if (env->virt_enabled && !first_stage) {
-+{
++        if (pmp_violation) {
-+    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
++            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
-+}
++        } else if (env->virt_enabled && !first_stage) {
-+
+             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
- static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
+         } else {
- {
+-            cs->exception_index = pmp_violation ?
-     REQUIRE_64BIT(ctx);
+-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
-     ctx->w = true;
++            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
--    return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
+         }
-+    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
+         break;
-+}
+     case MMU_DATA_LOAD:
-+
+-        if (two_stage && !first_stage) {
-+static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
++        if (pmp_violation) {
-+{
++            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
-+    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
++        } else if (two_stage && !first_stage) {
- }
+             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
+         } else {
- static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
+-            cs->exception_index = pmp_violation ?
- {
+-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
-     REQUIRE_64BIT(ctx);
++            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
-     ctx->w = true;
+         }
--    return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
+         break;
-+    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
+     case MMU_DATA_STORE:
- }
+-        if (two_stage && !first_stage) {
++        if (pmp_violation) {
- static bool trans_addw(DisasContext *ctx, arg_addw *a)
++            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
 +        } else if (two_stage && !first_stage) {
              cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
          } else {
 -            cs->exception_index = pmp_violation ?
 -                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
 -                RISCV_EXCP_STORE_PAGE_FAULT;
 +            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
          }
          break;
      default:
 --
-.31.1
+.45.1

-[PULL 16/33] target/riscv: Remove gen_arith_div*
+[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Alexei Filippov <alexei.filippov@syntacore.com>
-Use ctx->w and the enhanced gen_arith function.
+Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
 setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
 translation part, mtval2 will be set in case of successes 2 stage translation but
 failed pmp check.
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
 riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
 should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
 page-fault is taken into M-mode, mtval2 is written with either zero or guest
 physical address that faulted, shifted by 2 bits. *For other traps, mtval2
 is set to zero...*
 Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
-Message-id: 20210823195529.560295-8-richard.henderson@linaro.org
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                | 42 -------------------------
+ target/riscv/cpu_helper.c | 12 ++++++------
- target/riscv/insn_trans/trans_rvm.c.inc | 16 +++++-----
+file changed, 6 insertions(+), 6 deletions(-)
 files changed, 8 insertions(+), 50 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/cpu_helper.c
-+++ b/target/riscv/translate.c
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-     return true;
+                               __func__, pa, ret, prot_pmp, tlb_size);
- }
+                 prot &= prot_pmp;
--static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
+-            }
 -                            void(*func)(TCGv, TCGv, TCGv))
 -{
 -    TCGv source1, source2;
 -    source1 = tcg_temp_new();
 -    source2 = tcg_temp_new();
 -
--    gen_get_gpr(ctx, source1, a->rs1);
+-            if (ret != TRANSLATE_SUCCESS) {
--    gen_get_gpr(ctx, source2, a->rs2);
++            } else {
--    tcg_gen_ext32s_tl(source1, source1);
+                 /*
--    tcg_gen_ext32s_tl(source2, source2);
+                  * Guest physical address translation failed, this is a HS
--
+                  * level exception
--    (*func)(source1, source1, source2);
+                  */
--
+                 first_stage_error = false;
--    tcg_gen_ext32s_tl(source1, source1);
+-                env->guest_phys_fault_addr = (im_address |
--    gen_set_gpr(ctx, a->rd, source1);
+-                                              (address &
--    tcg_temp_free(source1);
+-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
--    tcg_temp_free(source2);
++                if (ret != TRANSLATE_PMP_FAIL) {
--    return true;
++                    env->guest_phys_fault_addr = (im_address |
--}
++                                                  (address &
--
++                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
--static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
++                }
--                            void(*func)(TCGv, TCGv, TCGv))
+             }
--{
+         }
--    TCGv source1, source2;
+     } else {
 -    source1 = tcg_temp_new();
 -    source2 = tcg_temp_new();
 -
 -    gen_get_gpr(ctx, source1, a->rs1);
 -    gen_get_gpr(ctx, source2, a->rs2);
 -    tcg_gen_ext32u_tl(source1, source1);
 -    tcg_gen_ext32u_tl(source2, source2);
 -
 -    (*func)(source1, source1, source2);
 -
 -    tcg_gen_ext32s_tl(source1, source1);
 -    gen_set_gpr(ctx, a->rd, source1);
 -    tcg_temp_free(source1);
 -    tcg_temp_free(source2);
 -    return true;
 -}
 -
  static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
  {
      tcg_gen_deposit_tl(ret, arg1, arg2,
 diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvm.c.inc
 +++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVM);
 -
 -    return gen_arith_div_w(ctx, a, &gen_div);
 +    ctx->w = true;
 +    return gen_arith(ctx, a, EXT_SIGN, gen_div);
  }
  static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVM);
 -
 -    return gen_arith_div_uw(ctx, a, &gen_divu);
 +    ctx->w = true;
 +    return gen_arith(ctx, a, EXT_ZERO, gen_divu);
  }
  static bool trans_remw(DisasContext *ctx, arg_remw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVM);
 -
 -    return gen_arith_div_w(ctx, a, &gen_rem);
 +    ctx->w = true;
 +    return gen_arith(ctx, a, EXT_SIGN, gen_rem);
  }
  static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVM);
 -
 -    return gen_arith_div_uw(ctx, a, &gen_remu);
 +    ctx->w = true;
 +    return gen_arith(ctx, a, EXT_ZERO, gen_remu);
  }
 --
-.31.1
+.45.1

-[PULL 04/33] target/riscv: Don't wrongly override isa version
+[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Rob Bradford <rbradford@rivosinc.com>
-For some cpu, the isa version has already been set in cpu init function.
+This extension has now been ratified:
-Thus only override the isa version when isa version is not set, or
+https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
-users set different isa version explicitly by cpu parameters.
+removed.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Since this is now a ratified extension add it to the list of extensions
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+included in the "max" CPU variant.
-Message-id: 20210811144612.68674-1-zhiwei_liu@c-sky.com
 Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 14 ++++++++------
+ target/riscv/cpu.c         | 2 +-
-file changed, 8 insertions(+), 6 deletions(-)
+ target/riscv/tcg/tcg-cpu.c | 2 +-
 files changed, 2 insertions(+), 2 deletions(-)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
-     RISCVCPU *cpu = RISCV_CPU(dev);
+     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
-     CPURISCVState *env = &cpu->env;
+     MISA_EXT_INFO(RVV, "v", "Vector operations"),
-     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
+     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
--    int priv_version = PRIV_VERSION_1_11_0;
+-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
--    int bext_version = BEXT_VERSION_0_93_0;
++    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
--    int vext_version = VEXT_VERSION_0_07_1;
+ };
-+    int priv_version = 0;
-     target_ulong target_misa = env->misa;
+ static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
-     Error *local_err = NULL;
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+--- a/target/riscv/tcg/tcg-cpu.c
-         }
++++ b/target/riscv/tcg/tcg-cpu.c
-     }
+@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
+     const RISCVCPUMultiExtConfig *prop;
--    set_priv_version(env, priv_version);
--    set_bext_version(env, bext_version);
+     /* Enable RVG, RVJ and RVV that are disabled by default */
--    set_vext_version(env, vext_version);
+-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
-+    if (priv_version) {
++    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
-+        set_priv_version(env, priv_version);
-+    } else if (!env->priv_ver) {
+     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
-+        set_priv_version(env, PRIV_VERSION_1_11_0);
+         isa_ext_update_enabled(cpu, prop->offset, true);
 +    }
      if (cpu->cfg.mmu) {
          set_feature(env, RISCV_FEATURE_MMU);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
              target_misa |= RVH;
          }
          if (cpu->cfg.ext_b) {
 +            int bext_version = BEXT_VERSION_0_93_0;
              target_misa |= RVB;
              if (cpu->cfg.bext_spec) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
              set_bext_version(env, bext_version);
          }
          if (cpu->cfg.ext_v) {
 +            int vext_version = VEXT_VERSION_0_07_1;
              target_misa |= RVV;
              if (!is_power_of_2(cpu->cfg.vlen)) {
                  error_setg(errp,
 --
-.31.1
+.45.1

-[PULL 30/33] target/riscv: Use {get,dest}_gpr for RVF
+[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Alistair Francis <alistair23@gmail.com>
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+When running the instruction
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+```
-Message-id: 20210823195529.560295-22-richard.henderson@linaro.org
+    cbo.flush 0(x0)
 ```
 QEMU would segfault.
 The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
 allocated.
 In order to fix this let's use the existing get_address()
 helper. This also has the benefit of performing pointer mask
 calculations on the address specified in rs1.
 The pointer masking specificiation specifically states:
 """
 Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
 """
 So this is the correct behaviour and we previously have been incorrectly
 not masking the address.
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
 Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvf.c.inc | 146 ++++++++++++------------
+ target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
-file changed, 70 insertions(+), 76 deletions(-)
+file changed, 12 insertions(+), 4 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
+diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvf.c.inc
+--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
-+++ b/target/riscv/insn_trans/trans_rvf.c.inc
++++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
 @@ -XXX,XX +XXX,XX @@
+ static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
  static bool trans_flw(DisasContext *ctx, arg_flw *a)
  {
-+    TCGv_i64 dest;
+     REQUIRE_ZICBOM(ctx);
-+    TCGv addr;
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
 +    TCGv src = get_address(ctx, a->rs1, 0);
 +
-     REQUIRE_FPU;
++    gen_helper_cbo_clean_flush(tcg_env, src);
      REQUIRE_EXT(ctx, RVF);
 -    TCGv t0 = tcg_temp_new();
 -    gen_get_gpr(ctx, t0, a->rs1);
 -    tcg_gen_addi_tl(t0, t0, a->imm);
 -    tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
 -    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
 +    addr = get_gpr(ctx, a->rs1, EXT_NONE);
 +    if (a->imm) {
 +        TCGv temp = temp_new(ctx);
 +        tcg_gen_addi_tl(temp, addr, a->imm);
 +        addr = temp;
 +    }
 +
 +    dest = cpu_fpr[a->rd];
 +    tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
 +    gen_nanbox_s(dest, dest);
 -    tcg_temp_free(t0);
      mark_fs_dirty(ctx);
      return true;
  }
- static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
+ static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
  {
-+    TCGv addr;
+     REQUIRE_ZICBOM(ctx);
 -    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
 +    TCGv src = get_address(ctx, a->rs1, 0);
 +
-     REQUIRE_FPU;
++    gen_helper_cbo_clean_flush(tcg_env, src);
      REQUIRE_EXT(ctx, RVF);
 -    TCGv t0 = tcg_temp_new();
 -    gen_get_gpr(ctx, t0, a->rs1);
 -    tcg_gen_addi_tl(t0, t0, a->imm);
 +    addr = get_gpr(ctx, a->rs1, EXT_NONE);
 +    if (a->imm) {
 +        TCGv temp = tcg_temp_new();
 +        tcg_gen_addi_tl(temp, addr, a->imm);
 +        addr = temp;
 +    }
 -    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
 +    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
 -    tcg_temp_free(t0);
      return true;
  }
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
+ static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
-     REQUIRE_FPU;
+ {
-     REQUIRE_EXT(ctx, RVF);
+     REQUIRE_ZICBOM(ctx);
+-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
--    TCGv t0 = tcg_temp_new();
++    TCGv src = get_address(ctx, a->rs1, 0);
--    gen_set_rm(ctx, a->rm);
++
--    gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
++    gen_helper_cbo_inval(tcg_env, src);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +    gen_set_rm(ctx, a->rm);
 +    gen_helper_fcvt_w_s(dest, cpu_env, cpu_fpr[a->rs1]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
-@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
+ static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    TCGv t0 = tcg_temp_new();
 -    gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +    gen_set_rm(ctx, a->rm);
 +    gen_helper_fcvt_wu_s(dest, cpu_env, cpu_fpr[a->rs1]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    TCGv t0 = tcg_temp_new();
 +    TCGv dest = dest_gpr(ctx, a->rd);
  #if defined(TARGET_RISCV64)
 -    tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
 +    tcg_gen_ext32s_tl(dest, cpu_fpr[a->rs1]);
  #else
 -    tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
 +    tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]);
  #endif
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 -
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
  {
-     REQUIRE_FPU;
+     REQUIRE_ZICBOZ(ctx);
-     REQUIRE_EXT(ctx, RVF);
+-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
--    TCGv t0 = tcg_temp_new();
++    TCGv src = get_address(ctx, a->rs1, 0);
 -    gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +
-+    TCGv dest = dest_gpr(ctx, a->rd);
++    gen_helper_cbo_zero(tcg_env, src);
 +
 +    gen_helper_feq_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
  {
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    TCGv t0 = tcg_temp_new();
 -    gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +
 +    gen_helper_flt_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
  {
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    TCGv t0 = tcg_temp_new();
 -    gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +
 +    gen_helper_fle_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    TCGv t0 = tcg_temp_new();
 -
 -    gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
 -
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +    gen_helper_fclass_s(dest, cpu_fpr[a->rs1]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    TCGv t0 = tcg_temp_new();
 -    gen_get_gpr(ctx, t0, a->rs1);
 +    TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
      gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
 +    gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, src);
      mark_fs_dirty(ctx);
 -    tcg_temp_free(t0);
 -
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    TCGv t0 = tcg_temp_new();
 -    gen_get_gpr(ctx, t0, a->rs1);
 +    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
      gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
 +    gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, src);
      mark_fs_dirty(ctx);
 -    tcg_temp_free(t0);
 -
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    TCGv t0 = tcg_temp_new();
 -    gen_get_gpr(ctx, t0, a->rs1);
 +    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
 -    tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
 +    tcg_gen_extu_tl_i64(cpu_fpr[a->rd], src);
      gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
      mark_fs_dirty(ctx);
 -    tcg_temp_free(t0);
 -
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    TCGv t0 = tcg_temp_new();
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +
      gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +    gen_helper_fcvt_l_s(dest, cpu_env, cpu_fpr[a->rs1]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    TCGv t0 = tcg_temp_new();
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +
      gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
 -    gen_set_gpr(ctx, a->rd, t0);
 -    tcg_temp_free(t0);
 +    gen_helper_fcvt_lu_s(dest, cpu_env, cpu_fpr[a->rs1]);
 +    gen_set_gpr(ctx, a->rd, dest);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    TCGv t0 = tcg_temp_new();
 -    gen_get_gpr(ctx, t0, a->rs1);
 +    TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
      gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
 +    gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, src);
      mark_fs_dirty(ctx);
 -    tcg_temp_free(t0);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
      REQUIRE_FPU;
      REQUIRE_EXT(ctx, RVF);
 -    TCGv t0 = tcg_temp_new();
 -    gen_get_gpr(ctx, t0, a->rs1);
 +    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
      gen_set_rm(ctx, a->rm);
 -    gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
 +    gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, src);
      mark_fs_dirty(ctx);
 -    tcg_temp_free(t0);
      return true;
  }
 --
-.31.1
+.45.1

-[PULL 19/33] target/riscv: Move gen_* helpers for RVB
+[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-Move these helpers near their use by the trans_*
+In AIA spec, each hart (or each hart within a group) has a unique hart
-functions within insn_trans/trans_rvb.c.inc.
+number to locate the memory pages of interrupt files in the address
 space. The number of bits required to represent any hart number is equal
 to ceil(log2(hmax + 1)), where hmax is the largest hart number among
 groups.
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+However, if the largest hart number among groups is a power of 2, QEMU
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+will pass an inaccurate hart-index-bit setting to Linux. For example, when
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+to represent 4 harts, but we passes 3 to Linux. The code needs to be
-Message-id: 20210823195529.560295-11-richard.henderson@linaro.org
+updated to ensure accurate hart-index-bit settings.
 Additionally, a Linux patch[1] is necessary to correctly recover the hart
 index when the guest OS has only 1 hart, where the hart-index-bit is 0.
 [1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
 Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c                | 233 -----------------------
+ target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
- target/riscv/insn_trans/trans_rvb.c.inc | 234 ++++++++++++++++++++++++
+file changed, 8 insertions(+), 1 deletion(-)
 files changed, 234 insertions(+), 233 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/target/riscv/translate.c
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
-     return true;
+         }
- }
+     }
--static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
+-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
 -{
 -    tcg_gen_deposit_tl(ret, arg1, arg2,
 -                       TARGET_LONG_BITS / 2,
 -                       TARGET_LONG_BITS / 2);
 -}
 -
 -static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    TCGv t = tcg_temp_new();
 -    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
 -    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
 -    tcg_temp_free(t);
 -}
 -
 -static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    TCGv t = tcg_temp_new();
 -    tcg_gen_ext8u_tl(t, arg2);
 -    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
 -    tcg_temp_free(t);
 -}
 -
 -static void gen_sbop_mask(TCGv ret, TCGv shamt)
 -{
 -    tcg_gen_movi_tl(ret, 1);
 -    tcg_gen_shl_tl(ret, ret, shamt);
 -}
 -
 -static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
 -{
 -    TCGv t = tcg_temp_new();
 -
 -    gen_sbop_mask(t, shamt);
 -    tcg_gen_or_tl(ret, arg1, t);
 -
 -    tcg_temp_free(t);
 -}
 -
 -static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
 -{
 -    TCGv t = tcg_temp_new();
 -
 -    gen_sbop_mask(t, shamt);
 -    tcg_gen_andc_tl(ret, arg1, t);
 -
 -    tcg_temp_free(t);
 -}
 -
 -static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
 -{
 -    TCGv t = tcg_temp_new();
 -
 -    gen_sbop_mask(t, shamt);
 -    tcg_gen_xor_tl(ret, arg1, t);
 -
 -    tcg_temp_free(t);
 -}
 -
 -static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
 -{
 -    tcg_gen_shr_tl(ret, arg1, shamt);
 -    tcg_gen_andi_tl(ret, ret, 1);
 -}
 -
 -static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    tcg_gen_not_tl(ret, arg1);
 -    tcg_gen_shl_tl(ret, ret, arg2);
 -    tcg_gen_not_tl(ret, ret);
 -}
 -
 -static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    tcg_gen_not_tl(ret, arg1);
 -    tcg_gen_shr_tl(ret, ret, arg2);
 -    tcg_gen_not_tl(ret, ret);
 -}
 -
 -static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
 -{
 -    TCGv source1 = tcg_temp_new();
 -    TCGv source2;
 -
 -    gen_get_gpr(ctx, source1, a->rs1);
 -
 -    if (a->shamt == (TARGET_LONG_BITS - 8)) {
 -        /* rev8, byte swaps */
 -        tcg_gen_bswap_tl(source1, source1);
 -    } else {
 -        source2 = tcg_temp_new();
 -        tcg_gen_movi_tl(source2, a->shamt);
 -        gen_helper_grev(source1, source1, source2);
 -        tcg_temp_free(source2);
 -    }
 -
 -    gen_set_gpr(ctx, a->rd, source1);
 -    tcg_temp_free(source1);
 -    return true;
 -}
 -
 -#define GEN_SHADD(SHAMT)                                       \
 -static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
 -{                                                              \
 -    TCGv t = tcg_temp_new();                                   \
 -                                                               \
 -    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
 -    tcg_gen_add_tl(ret, t, arg2);                              \
 -                                                               \
 -    tcg_temp_free(t);                                          \
 -}
 -
 -GEN_SHADD(1)
 -GEN_SHADD(2)
 -GEN_SHADD(3)
 -
 -static void gen_ctzw(TCGv ret, TCGv arg1)
 -{
 -    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
 -    tcg_gen_ctzi_tl(ret, ret, 64);
 -}
 -
 -static void gen_clzw(TCGv ret, TCGv arg1)
 -{
 -    tcg_gen_ext32u_tl(ret, arg1);
 -    tcg_gen_clzi_tl(ret, ret, 64);
 -    tcg_gen_subi_tl(ret, ret, 32);
 -}
 -
 -static void gen_cpopw(TCGv ret, TCGv arg1)
 -{
 -    tcg_gen_ext32u_tl(arg1, arg1);
 -    tcg_gen_ctpop_tl(ret, arg1);
 -}
 -
 -static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    TCGv t = tcg_temp_new();
 -    tcg_gen_ext16s_tl(t, arg2);
 -    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
 -    tcg_temp_free(t);
 -}
 -
 -static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    TCGv t = tcg_temp_new();
 -    tcg_gen_shri_tl(t, arg1, 16);
 -    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
 -    tcg_gen_ext32s_tl(ret, ret);
 -    tcg_temp_free(t);
 -}
 -
 -static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    TCGv_i32 t1 = tcg_temp_new_i32();
 -    TCGv_i32 t2 = tcg_temp_new_i32();
 -
 -    /* truncate to 32-bits */
 -    tcg_gen_trunc_tl_i32(t1, arg1);
 -    tcg_gen_trunc_tl_i32(t2, arg2);
 -
 -    tcg_gen_rotr_i32(t1, t1, t2);
 -
 -    /* sign-extend 64-bits */
 -    tcg_gen_ext_i32_tl(ret, t1);
 -
 -    tcg_temp_free_i32(t1);
 -    tcg_temp_free_i32(t2);
 -}
 -
 -static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    TCGv_i32 t1 = tcg_temp_new_i32();
 -    TCGv_i32 t2 = tcg_temp_new_i32();
 -
 -    /* truncate to 32-bits */
 -    tcg_gen_trunc_tl_i32(t1, arg1);
 -    tcg_gen_trunc_tl_i32(t2, arg2);
 -
 -    tcg_gen_rotl_i32(t1, t1, t2);
 -
 -    /* sign-extend 64-bits */
 -    tcg_gen_ext_i32_tl(ret, t1);
 -
 -    tcg_temp_free_i32(t1);
 -    tcg_temp_free_i32(t2);
 -}
 -
 -static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    tcg_gen_ext32u_tl(arg1, arg1);
 -    gen_helper_grev(ret, arg1, arg2);
 -}
 -
 -static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    tcg_gen_ext32u_tl(arg1, arg1);
 -    gen_helper_gorcw(ret, arg1, arg2);
 -}
 -
 -#define GEN_SHADD_UW(SHAMT)                                       \
 -static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
 -{                                                                 \
 -    TCGv t = tcg_temp_new();                                      \
 -                                                                  \
 -    tcg_gen_ext32u_tl(t, arg1);                                   \
 -                                                                  \
 -    tcg_gen_shli_tl(t, t, SHAMT);                                 \
 -    tcg_gen_add_tl(ret, t, arg2);                                 \
 -                                                                  \
 -    tcg_temp_free(t);                                             \
 -}
 -
 -GEN_SHADD_UW(1)
 -GEN_SHADD_UW(2)
 -GEN_SHADD_UW(3)
 -
 -static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    tcg_gen_ext32u_tl(arg1, arg1);
 -    tcg_gen_add_tl(ret, arg1, arg2);
 -}
 -
  static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
                        void (*func)(TCGv, TCGv, TCGv))
  {
@@ -XXX,XX +XXX,XX @@ static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
      return true;
  }
 -static void gen_ctz(TCGv ret, TCGv arg1)
 -{
 -    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
 -}
 -
 -static void gen_clz(TCGv ret, TCGv arg1)
 -{
 -    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
 -}
 -
  static bool gen_unary(DisasContext *ctx, arg_r2 *a,
                        void(*func)(TCGv, TCGv))
  {
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
   * this program.  If not, see <http://www.gnu.org/licenses/>.
   */
 +
-+static void gen_clz(TCGv ret, TCGv arg1)
++    if (max_hart_per_socket > 1) {
-+{
++        max_hart_per_socket--;
-+    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
++        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
 +}
 +
  static bool trans_clz(DisasContext *ctx, arg_clz *a)
  {
      REQUIRE_EXT(ctx, RVB);
      return gen_unary(ctx, a, gen_clz);
  }
 +static void gen_ctz(TCGv ret, TCGv arg1)
 +{
 +    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
 +}
 +
  static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
  {
      REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
      return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
  }
 +static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
 +{
 +    tcg_gen_deposit_tl(ret, arg1, arg2,
 +                       TARGET_LONG_BITS / 2,
 +                       TARGET_LONG_BITS / 2);
 +}
 +
  static bool trans_pack(DisasContext *ctx, arg_pack *a)
  {
      REQUIRE_EXT(ctx, RVB);
      return gen_arith(ctx, a, EXT_NONE, gen_pack);
  }
 +static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
 +{
 +    TCGv t = tcg_temp_new();
 +    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
 +    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
 +    tcg_temp_free(t);
 +}
 +
  static bool trans_packu(DisasContext *ctx, arg_packu *a)
  {
      REQUIRE_EXT(ctx, RVB);
      return gen_arith(ctx, a, EXT_NONE, gen_packu);
  }
 +static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
 +{
 +    TCGv t = tcg_temp_new();
 +    tcg_gen_ext8u_tl(t, arg2);
 +    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
 +    tcg_temp_free(t);
 +}
 +
  static bool trans_packh(DisasContext *ctx, arg_packh *a)
  {
      REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
      return gen_unary(ctx, a, tcg_gen_ext16s_tl);
  }
 +static void gen_sbop_mask(TCGv ret, TCGv shamt)
 +{
 +    tcg_gen_movi_tl(ret, 1);
 +    tcg_gen_shl_tl(ret, ret, shamt);
 +}
 +
 +static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
 +{
 +    TCGv t = tcg_temp_new();
 +
 +    gen_sbop_mask(t, shamt);
 +    tcg_gen_or_tl(ret, arg1, t);
 +
 +    tcg_temp_free(t);
 +}
 +
  static bool trans_bset(DisasContext *ctx, arg_bset *a)
  {
      REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
      return gen_shifti(ctx, a, gen_bset);
  }
 +static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
 +{
 +    TCGv t = tcg_temp_new();
 +
 +    gen_sbop_mask(t, shamt);
 +    tcg_gen_andc_tl(ret, arg1, t);
 +
 +    tcg_temp_free(t);
 +}
 +
  static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
  {
      REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
      return gen_shifti(ctx, a, gen_bclr);
  }
 +static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
 +{
 +    TCGv t = tcg_temp_new();
 +
 +    gen_sbop_mask(t, shamt);
 +    tcg_gen_xor_tl(ret, arg1, t);
 +
 +    tcg_temp_free(t);
 +}
 +
  static bool trans_binv(DisasContext *ctx, arg_binv *a)
  {
      REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
      return gen_shifti(ctx, a, gen_binv);
  }
 +static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
 +{
 +    tcg_gen_shr_tl(ret, arg1, shamt);
 +    tcg_gen_andi_tl(ret, ret, 1);
 +}
 +
  static bool trans_bext(DisasContext *ctx, arg_bext *a)
  {
      REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
      return gen_shifti(ctx, a, gen_bext);
  }
 +static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
 +{
 +    tcg_gen_not_tl(ret, arg1);
 +    tcg_gen_shl_tl(ret, ret, arg2);
 +    tcg_gen_not_tl(ret, ret);
 +}
 +
  static bool trans_slo(DisasContext *ctx, arg_slo *a)
  {
      REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
      return gen_shifti(ctx, a, gen_slo);
  }
 +static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
 +{
 +    tcg_gen_not_tl(ret, arg1);
 +    tcg_gen_shr_tl(ret, ret, arg2);
 +    tcg_gen_not_tl(ret, ret);
 +}
 +
  static bool trans_sro(DisasContext *ctx, arg_sro *a)
  {
      REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_grev(DisasContext *ctx, arg_grev *a)
      return gen_shift(ctx, a, gen_helper_grev);
  }
 +static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
 +{
 +    TCGv source1 = tcg_temp_new();
 +    TCGv source2;
 +
 +    gen_get_gpr(ctx, source1, a->rs1);
 +
 +    if (a->shamt == (TARGET_LONG_BITS - 8)) {
 +        /* rev8, byte swaps */
 +        tcg_gen_bswap_tl(source1, source1);
 +    } else {
-+        source2 = tcg_temp_new();
++        hart_bits = 0;
 +        tcg_gen_movi_tl(source2, a->shamt);
 +        gen_helper_grev(source1, source1, source2);
 +        tcg_temp_free(source2);
 +    }
 +
-+    gen_set_gpr(ctx, a->rd, source1);
+     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
-+    tcg_temp_free(source1);
+                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
-+    return true;
+                             &hart_bits, true, NULL);
 +}
 +
  static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
  {
      REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
      return gen_shifti(ctx, a, gen_helper_gorc);
  }
 +#define GEN_SHADD(SHAMT)                                       \
 +static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
 +{                                                              \
 +    TCGv t = tcg_temp_new();                                   \
 +                                                               \
 +    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
 +    tcg_gen_add_tl(ret, t, arg2);                              \
 +                                                               \
 +    tcg_temp_free(t);                                          \
 +}
 +
 +GEN_SHADD(1)
 +GEN_SHADD(2)
 +GEN_SHADD(3)
 +
  #define GEN_TRANS_SHADD(SHAMT)                                             \
  static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
  {                                                                          \
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(1)
  GEN_TRANS_SHADD(2)
  GEN_TRANS_SHADD(3)
 +static void gen_clzw(TCGv ret, TCGv arg1)
 +{
 +    tcg_gen_ext32u_tl(ret, arg1);
 +    tcg_gen_clzi_tl(ret, ret, 64);
 +    tcg_gen_subi_tl(ret, ret, 32);
 +}
 +
  static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
  {
      REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
      return gen_unary(ctx, a, gen_clzw);
  }
 +static void gen_ctzw(TCGv ret, TCGv arg1)
 +{
 +    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
 +    tcg_gen_ctzi_tl(ret, ret, 64);
 +}
 +
  static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
  {
      REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
      return gen_unary(ctx, a, gen_ctzw);
  }
 +static void gen_cpopw(TCGv ret, TCGv arg1)
 +{
 +    tcg_gen_ext32u_tl(arg1, arg1);
 +    tcg_gen_ctpop_tl(ret, arg1);
 +}
 +
  static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
  {
      REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
      return gen_unary(ctx, a, gen_cpopw);
  }
 +static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
 +{
 +    TCGv t = tcg_temp_new();
 +    tcg_gen_ext16s_tl(t, arg2);
 +    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
 +    tcg_temp_free(t);
 +}
 +
  static bool trans_packw(DisasContext *ctx, arg_packw *a)
  {
      REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_packw(DisasContext *ctx, arg_packw *a)
      return gen_arith(ctx, a, EXT_NONE, gen_packw);
  }
 +static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
 +{
 +    TCGv t = tcg_temp_new();
 +    tcg_gen_shri_tl(t, arg1, 16);
 +    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
 +    tcg_gen_ext32s_tl(ret, ret);
 +    tcg_temp_free(t);
 +}
 +
  static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
  {
      REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
      return gen_shiftiw(ctx, a, gen_sro);
  }
 +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
 +{
 +    TCGv_i32 t1 = tcg_temp_new_i32();
 +    TCGv_i32 t2 = tcg_temp_new_i32();
 +
 +    /* truncate to 32-bits */
 +    tcg_gen_trunc_tl_i32(t1, arg1);
 +    tcg_gen_trunc_tl_i32(t2, arg2);
 +
 +    tcg_gen_rotr_i32(t1, t1, t2);
 +
 +    /* sign-extend 64-bits */
 +    tcg_gen_ext_i32_tl(ret, t1);
 +
 +    tcg_temp_free_i32(t1);
 +    tcg_temp_free_i32(t2);
 +}
 +
  static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
  {
      REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
      return gen_shiftiw(ctx, a, gen_rorw);
  }
 +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
 +{
 +    TCGv_i32 t1 = tcg_temp_new_i32();
 +    TCGv_i32 t2 = tcg_temp_new_i32();
 +
 +    /* truncate to 32-bits */
 +    tcg_gen_trunc_tl_i32(t1, arg1);
 +    tcg_gen_trunc_tl_i32(t2, arg2);
 +
 +    tcg_gen_rotl_i32(t1, t1, t2);
 +
 +    /* sign-extend 64-bits */
 +    tcg_gen_ext_i32_tl(ret, t1);
 +
 +    tcg_temp_free_i32(t1);
 +    tcg_temp_free_i32(t2);
 +}
 +
  static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
  {
      REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
      return gen_shiftw(ctx, a, gen_rolw);
  }
 +static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
 +{
 +    tcg_gen_ext32u_tl(arg1, arg1);
 +    gen_helper_grev(ret, arg1, arg2);
 +}
 +
  static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
  {
      REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
      return gen_shiftiw(ctx, a, gen_grevw);
  }
 +static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
 +{
 +    tcg_gen_ext32u_tl(arg1, arg1);
 +    gen_helper_gorcw(ret, arg1, arg2);
 +}
 +
  static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
  {
      REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
      return gen_shiftiw(ctx, a, gen_gorcw);
  }
 +#define GEN_SHADD_UW(SHAMT)                                       \
 +static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
 +{                                                                 \
 +    TCGv t = tcg_temp_new();                                      \
 +                                                                  \
 +    tcg_gen_ext32u_tl(t, arg1);                                   \
 +                                                                  \
 +    tcg_gen_shli_tl(t, t, SHAMT);                                 \
 +    tcg_gen_add_tl(ret, t, arg2);                                 \
 +                                                                  \
 +    tcg_temp_free(t);                                             \
 +}
 +
 +GEN_SHADD_UW(1)
 +GEN_SHADD_UW(2)
 +GEN_SHADD_UW(3)
 +
  #define GEN_TRANS_SHADD_UW(SHAMT)                             \
  static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
                                      arg_sh##SHAMT##add_uw *a) \
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD_UW(1)
  GEN_TRANS_SHADD_UW(2)
  GEN_TRANS_SHADD_UW(3)
 +static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
 +{
 +    tcg_gen_ext32u_tl(arg1, arg1);
 +    tcg_gen_add_tl(ret, arg1, arg2);
 +}
 +
  static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
  {
      REQUIRE_64BIT(ctx);
 --
-.31.1
+.45.1

-[PULL 05/33] target/riscv: Add User CSRs read-only check
+[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
-From: LIU Zhiwei <zhiwei_liu@c-sky.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-For U-mode CSRs, read-only check is also needed.
+Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
 in bytes, when in this context we want 'reg_width' as the length in
 bits.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Fix 'reg_width' back to the value in bits like 7cb59921c05a
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
-Message-id: 20210810014552.4884-1-zhiwei_liu@c-sky.com
+beforehand.
 While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
 clarity about what the variable represents. 'bitsize' is also used in
 riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
 gdb_feature_builder_append_reg().
 Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
 Cc: Alex Bennée <alex.bennee@linaro.org>
 Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
 Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Acked-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 8 +++++---
+ target/riscv/gdbstub.c | 6 +++---
-file changed, 5 insertions(+), 3 deletions(-)
+file changed, 3 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/gdbstub.c
-+++ b/target/riscv/csr.c
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
-     RISCVException ret;
+ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-     target_ulong old_value;
+ {
-     RISCVCPU *cpu = env_archcpu(env);
+     RISCVCPU *cpu = RISCV_CPU(cs);
-+    int read_only = get_field(csrno, 0xC00) == 3;
+-    int reg_width = cpu->cfg.vlenb;
++    int bitsize = cpu->cfg.vlenb << 3;
-     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
+     GDBFeatureBuilder builder;
- #if !defined(CONFIG_USER_ONLY)
+     int i;
-     int effective_priv = env->priv;
--    int read_only = get_field(csrno, 0xC00) == 3;
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-     if (riscv_has_ext(env, RVH) &&
+     /* First define types and totals in a whole VL */
-         env->priv == PRV_S &&
+     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-@@ -XXX,XX +XXX,XX @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
+-        int count = reg_width / vec_lanes[i].size;
-         effective_priv++;
++        int count = bitsize / vec_lanes[i].size;
          gdb_feature_builder_append_tag(
              &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
              vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
      /* Define vector registers */
      for (i = 0; i < 32; i++) {
          gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
 -                                       reg_width, i, "riscv_vector", "vector");
 +                                       bitsize, i, "riscv_vector", "vector");
      }
--    if ((write_mask && read_only) ||
+     gdb_feature_builder_end(&builder);
 -        (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
 +    if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
          return RISCV_EXCP_ILLEGAL_INST;
      }
  #endif
 +    if (write_mask && read_only) {
 +        return RISCV_EXCP_ILLEGAL_INST;
 +    }
      /* ensure the CSR extension is enabled. */
      if (!cpu->cfg.ext_icsr) {
 --
-.31.1
+.45.1

-[PULL 06/33] hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()
+Deleted patch
-From: Peter Maydell <peter.maydell@linaro.org>
-In the riscv virt machine init function, We assemble a string
-plic_hart_config which is a comma-separated list of N copies of the
-VIRT_PLIC_HART_CONFIG string.  The code that does this has a
-misunderstanding of the strncat() length argument.  If the source
-string is too large strncat() will write a maximum of length+1 bytes
-(length bytes from the source string plus a trailing NUL), but the
-code here assumes that it will write only length bytes at most.
-This isn't an actual bug because the code has correctly precalculated
-the amount of memory it needs to allocate so that it will never be
-too small (i.e.  we could have used plain old strcat()), but it does
-mean that the code looks like it has a guard against accidental
-overrun when it doesn't.
-Rewrite the string handling here to use the glib g_strjoinv()
-function, which means we don't need to do careful accountancy of
-string lengths, and makes it clearer that what we're doing is
-"create a comma-separated string".
-Fixes: Coverity 1460752
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210812144647.10516-1-peter.maydell@linaro.org
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/virt.c | 33 ++++++++++++++++++++-------------
-file changed, 20 insertions(+), 13 deletions(-)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static FWCfgState *create_fw_cfg(const MachineState *mc)
-     return fw_cfg;
- }
-+/*
-+ * Return the per-socket PLIC hart topology configuration string
-+ * (caller must free with g_free())
-+ */
-+static char *plic_hart_config_string(int hart_count)
-+{
-+    g_autofree const char **vals = g_new(const char *, hart_count + 1);
-+    int i;
-+
-+    for (i = 0; i < hart_count; i++) {
-+        vals[i] = VIRT_PLIC_HART_CONFIG;
-+    }
-+    vals[i] = NULL;
-+
-+    /* g_strjoinv() obliges us to cast away const here */
-+    return g_strjoinv(",", (char **)vals);
-+}
-+
- static void virt_machine_init(MachineState *machine)
- {
-     const MemMapEntry *memmap = virt_memmap;
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
-     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
-     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
-     char *plic_hart_config, *soc_name;
--    size_t plic_hart_config_len;
-     target_ulong start_addr = memmap[VIRT_DRAM].base;
-     target_ulong firmware_end_addr, kernel_start_addr;
-     uint32_t fdt_load_addr;
-     uint64_t kernel_entry;
-     DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
--    int i, j, base_hartid, hart_count;
-+    int i, base_hartid, hart_count;
-     /* Check socket count limit */
-     if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
-             SIFIVE_CLINT_TIMEBASE_FREQ, true);
-         /* Per-socket PLIC hart topology configuration string */
--        plic_hart_config_len =
--            (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count;
--        plic_hart_config = g_malloc0(plic_hart_config_len);
--        for (j = 0; j < hart_count; j++) {
--            if (j != 0) {
--                strncat(plic_hart_config, ",", plic_hart_config_len);
--            }
--            strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG,
--                plic_hart_config_len);
--            plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
--        }
-+        plic_hart_config = plic_hart_config_string(hart_count);
-         /* Per-socket PLIC */
-         s->plic[i] = sifive_plic_create(
---
-.31.1

-[PULL 08/33] hw/core/register: Add more 64-bit utilities
+Deleted patch
-From: Joe Komlodi <joe.komlodi@xilinx.com>
-We already have some utilities to handle 64-bit wide registers, so this just
-adds some more for:
-- Initializing 64-bit registers
-- Extracting and depositing to an array of 64-bit registers
-Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 1626805903-162860-2-git-send-email-joe.komlodi@xilinx.com
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/register.h       |  8 ++++++++
- include/hw/registerfields.h |  8 ++++++++
- hw/core/register.c          | 12 ++++++++++++
-files changed, 28 insertions(+)
-diff --git a/include/hw/register.h b/include/hw/register.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/register.h
-+++ b/include/hw/register.h
-@@ -XXX,XX +XXX,XX @@ RegisterInfoArray *register_init_block32(DeviceState *owner,
-                                          bool debug_enabled,
-                                          uint64_t memory_size);
-+RegisterInfoArray *register_init_block64(DeviceState *owner,
-+                                         const RegisterAccessInfo *rae,
-+                                         int num, RegisterInfo *ri,
-+                                         uint64_t *data,
-+                                         const MemoryRegionOps *ops,
-+                                         bool debug_enabled,
-+                                         uint64_t memory_size);
-+
- /**
-  * This function should be called to cleanup the registers that were initialized
-  * when calling register_init_block32(). This function should only be called
-diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/registerfields.h
-+++ b/include/hw/registerfields.h
-@@ -XXX,XX +XXX,XX @@
-     enum { A_ ## reg = (addr) };                                          \
-     enum { R_ ## reg = (addr) / 2 };
-+#define REG64(reg, addr)                                                  \
-+    enum { A_ ## reg = (addr) };                                          \
-+    enum { R_ ## reg = (addr) / 8 };
-+
- /* Define SHIFT, LENGTH and MASK constants for a field within a register */
- /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
-@@ -XXX,XX +XXX,XX @@
- /* Extract a field from an array of registers */
- #define ARRAY_FIELD_EX32(regs, reg, field)                                \
-     FIELD_EX32((regs)[R_ ## reg], reg, field)
-+#define ARRAY_FIELD_EX64(regs, reg, field)                                \
-+    FIELD_EX64((regs)[R_ ## reg], reg, field)
- /* Deposit a register field.
-  * Assigning values larger then the target field will result in
-@@ -XXX,XX +XXX,XX @@
- /* Deposit a field to array of registers.  */
- #define ARRAY_FIELD_DP32(regs, reg, field, val)                           \
-     (regs)[R_ ## reg] = FIELD_DP32((regs)[R_ ## reg], reg, field, val);
-+#define ARRAY_FIELD_DP64(regs, reg, field, val)                           \
-+    (regs)[R_ ## reg] = FIELD_DP64((regs)[R_ ## reg], reg, field, val);
- #endif
-diff --git a/hw/core/register.c b/hw/core/register.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/core/register.c
-+++ b/hw/core/register.c
-@@ -XXX,XX +XXX,XX @@ RegisterInfoArray *register_init_block32(DeviceState *owner,
-                                data, ops, debug_enabled, memory_size, 32);
- }
-+RegisterInfoArray *register_init_block64(DeviceState *owner,
-+                                         const RegisterAccessInfo *rae,
-+                                         int num, RegisterInfo *ri,
-+                                         uint64_t *data,
-+                                         const MemoryRegionOps *ops,
-+                                         bool debug_enabled,
-+                                         uint64_t memory_size)
-+{
-+    return register_init_block(owner, rae, num, ri, (void *)
-+                               data, ops, debug_enabled, memory_size, 64);
-+}
-+
- void register_finalize_block(RegisterInfoArray *r_array)
- {
-     object_unparent(OBJECT(&r_array->mem));
---
-.31.1

-[PULL 15/33] target/riscv: Add DisasExtend to gen_arith*
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Most arithmetic does not require extending the inputs.
-Exceptions include division, comparison and minmax.
-Begin using ctx->w, which allows elimination of gen_addw,
-gen_subw, gen_mulw.
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210823195529.560295-7-richard.henderson@linaro.org
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/translate.c                | 69 +++++++------------------
- target/riscv/insn_trans/trans_rvb.c.inc | 30 +++++------
- target/riscv/insn_trans/trans_rvi.c.inc | 39 ++++++++------
- target/riscv/insn_trans/trans_rvm.c.inc | 16 +++---
-files changed, 64 insertions(+), 90 deletions(-)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num)
-     tcg_gen_mov_tl(t, get_gpr(ctx, reg_num, EXT_NONE));
- }
--static TCGv __attribute__((unused)) dest_gpr(DisasContext *ctx, int reg_num)
-+static TCGv dest_gpr(DisasContext *ctx, int reg_num)
- {
-     if (reg_num == 0 || ctx->w) {
-         return temp_new(ctx);
-@@ -XXX,XX +XXX,XX @@ static int ex_rvc_shifti(DisasContext *ctx, int imm)
- /* Include the auto-generated decoder for 32 bit insn */
- #include "decode-insn32.c.inc"
--static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
-+static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
-                              void (*func)(TCGv, TCGv, target_long))
- {
--    TCGv source1;
--    source1 = tcg_temp_new();
--
--    gen_get_gpr(ctx, source1, a->rs1);
-+    TCGv dest = dest_gpr(ctx, a->rd);
-+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
--    (*func)(source1, source1, a->imm);
-+    func(dest, src1, a->imm);
--    gen_set_gpr(ctx, a->rd, source1);
--    tcg_temp_free(source1);
-+    gen_set_gpr(ctx, a->rd, dest);
-     return true;
- }
--static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
-+static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
-                              void (*func)(TCGv, TCGv, TCGv))
- {
--    TCGv source1, source2;
--    source1 = tcg_temp_new();
--    source2 = tcg_temp_new();
-+    TCGv dest = dest_gpr(ctx, a->rd);
-+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
-+    TCGv src2 = tcg_constant_tl(a->imm);
--    gen_get_gpr(ctx, source1, a->rs1);
--    tcg_gen_movi_tl(source2, a->imm);
-+    func(dest, src1, src2);
--    (*func)(source1, source1, source2);
--
--    gen_set_gpr(ctx, a->rd, source1);
--    tcg_temp_free(source1);
--    tcg_temp_free(source2);
-+    gen_set_gpr(ctx, a->rd, dest);
-     return true;
- }
--static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
--{
--    tcg_gen_add_tl(ret, arg1, arg2);
--    tcg_gen_ext32s_tl(ret, ret);
--}
--
--static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
--{
--    tcg_gen_sub_tl(ret, arg1, arg2);
--    tcg_gen_ext32s_tl(ret, ret);
--}
--
--static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2)
--{
--    tcg_gen_mul_tl(ret, arg1, arg2);
--    tcg_gen_ext32s_tl(ret, ret);
--}
--
- static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
-                             void(*func)(TCGv, TCGv, TCGv))
- {
-@@ -XXX,XX +XXX,XX @@ static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
-     tcg_gen_add_tl(ret, arg1, arg2);
- }
--static bool gen_arith(DisasContext *ctx, arg_r *a,
--                      void(*func)(TCGv, TCGv, TCGv))
-+static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
-+                      void (*func)(TCGv, TCGv, TCGv))
- {
--    TCGv source1, source2;
--    source1 = tcg_temp_new();
--    source2 = tcg_temp_new();
-+    TCGv dest = dest_gpr(ctx, a->rd);
-+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
-+    TCGv src2 = get_gpr(ctx, a->rs2, ext);
--    gen_get_gpr(ctx, source1, a->rs1);
--    gen_get_gpr(ctx, source2, a->rs2);
-+    func(dest, src1, src2);
--    (*func)(source1, source1, source2);
--
--    gen_set_gpr(ctx, a->rd, source1);
--    tcg_temp_free(source1);
--    tcg_temp_free(source2);
-+    gen_set_gpr(ctx, a->rd, dest);
-     return true;
- }
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
- static bool trans_andn(DisasContext *ctx, arg_andn *a)
- {
-     REQUIRE_EXT(ctx, RVB);
--    return gen_arith(ctx, a, tcg_gen_andc_tl);
-+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
- }
- static bool trans_orn(DisasContext *ctx, arg_orn *a)
- {
-     REQUIRE_EXT(ctx, RVB);
--    return gen_arith(ctx, a, tcg_gen_orc_tl);
-+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
- }
- static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
- {
-     REQUIRE_EXT(ctx, RVB);
--    return gen_arith(ctx, a, tcg_gen_eqv_tl);
-+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
- }
- static bool trans_pack(DisasContext *ctx, arg_pack *a)
- {
-     REQUIRE_EXT(ctx, RVB);
--    return gen_arith(ctx, a, gen_pack);
-+    return gen_arith(ctx, a, EXT_NONE, gen_pack);
- }
- static bool trans_packu(DisasContext *ctx, arg_packu *a)
- {
-     REQUIRE_EXT(ctx, RVB);
--    return gen_arith(ctx, a, gen_packu);
-+    return gen_arith(ctx, a, EXT_NONE, gen_packu);
- }
- static bool trans_packh(DisasContext *ctx, arg_packh *a)
- {
-     REQUIRE_EXT(ctx, RVB);
--    return gen_arith(ctx, a, gen_packh);
-+    return gen_arith(ctx, a, EXT_NONE, gen_packh);
- }
- static bool trans_min(DisasContext *ctx, arg_min *a)
- {
-     REQUIRE_EXT(ctx, RVB);
--    return gen_arith(ctx, a, tcg_gen_smin_tl);
-+    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
- }
- static bool trans_max(DisasContext *ctx, arg_max *a)
- {
-     REQUIRE_EXT(ctx, RVB);
--    return gen_arith(ctx, a, tcg_gen_smax_tl);
-+    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
- }
- static bool trans_minu(DisasContext *ctx, arg_minu *a)
- {
-     REQUIRE_EXT(ctx, RVB);
--    return gen_arith(ctx, a, tcg_gen_umin_tl);
-+    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
- }
- static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
- {
-     REQUIRE_EXT(ctx, RVB);
--    return gen_arith(ctx, a, tcg_gen_umax_tl);
-+    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
- }
- static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
-@@ -XXX,XX +XXX,XX @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
- static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
- {                                                                          \
-     REQUIRE_EXT(ctx, RVB);                                                 \
--    return gen_arith(ctx, a, gen_sh##SHAMT##add);                          \
-+    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
- }
- GEN_TRANS_SHADD(1)
-@@ -XXX,XX +XXX,XX @@ static bool trans_packw(DisasContext *ctx, arg_packw *a)
- {
-     REQUIRE_64BIT(ctx);
-     REQUIRE_EXT(ctx, RVB);
--    return gen_arith(ctx, a, gen_packw);
-+    return gen_arith(ctx, a, EXT_NONE, gen_packw);
- }
- static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
- {
-     REQUIRE_64BIT(ctx);
-     REQUIRE_EXT(ctx, RVB);
--    return gen_arith(ctx, a, gen_packuw);
-+    return gen_arith(ctx, a, EXT_NONE, gen_packuw);
- }
- static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
-@@ -XXX,XX +XXX,XX @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
- {                                                             \
-     REQUIRE_64BIT(ctx);                                       \
-     REQUIRE_EXT(ctx, RVB);                                    \
--    return gen_arith(ctx, a, gen_sh##SHAMT##add_uw);          \
-+    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
- }
- GEN_TRANS_SHADD_UW(1)
-@@ -XXX,XX +XXX,XX @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
- {
-     REQUIRE_64BIT(ctx);
-     REQUIRE_EXT(ctx, RVB);
--    return gen_arith(ctx, a, gen_add_uw);
-+    return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
- }
- static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
-diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvi.c.inc
-+++ b/target/riscv/insn_trans/trans_rvi.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
- static bool trans_addi(DisasContext *ctx, arg_addi *a)
- {
--    return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
-+    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
- }
- static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
-@@ -XXX,XX +XXX,XX @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
-     tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
- }
--
- static bool trans_slti(DisasContext *ctx, arg_slti *a)
- {
--    return gen_arith_imm_tl(ctx, a, &gen_slt);
-+    return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt);
- }
- static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
- {
--    return gen_arith_imm_tl(ctx, a, &gen_sltu);
-+    return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu);
- }
- static bool trans_xori(DisasContext *ctx, arg_xori *a)
- {
--    return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
-+    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl);
- }
-+
- static bool trans_ori(DisasContext *ctx, arg_ori *a)
- {
--    return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
-+    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl);
- }
-+
- static bool trans_andi(DisasContext *ctx, arg_andi *a)
- {
--    return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
-+    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
- }
-+
- static bool trans_slli(DisasContext *ctx, arg_slli *a)
- {
-     return gen_shifti(ctx, a, tcg_gen_shl_tl);
-@@ -XXX,XX +XXX,XX @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
- static bool trans_add(DisasContext *ctx, arg_add *a)
- {
--    return gen_arith(ctx, a, &tcg_gen_add_tl);
-+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
- }
- static bool trans_sub(DisasContext *ctx, arg_sub *a)
- {
--    return gen_arith(ctx, a, &tcg_gen_sub_tl);
-+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
- }
- static bool trans_sll(DisasContext *ctx, arg_sll *a)
-@@ -XXX,XX +XXX,XX @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
- static bool trans_slt(DisasContext *ctx, arg_slt *a)
- {
--    return gen_arith(ctx, a, &gen_slt);
-+    return gen_arith(ctx, a, EXT_SIGN, gen_slt);
- }
- static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
- {
--    return gen_arith(ctx, a, &gen_sltu);
-+    return gen_arith(ctx, a, EXT_SIGN, gen_sltu);
- }
- static bool trans_xor(DisasContext *ctx, arg_xor *a)
- {
--    return gen_arith(ctx, a, &tcg_gen_xor_tl);
-+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_xor_tl);
- }
- static bool trans_srl(DisasContext *ctx, arg_srl *a)
-@@ -XXX,XX +XXX,XX @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
- static bool trans_or(DisasContext *ctx, arg_or *a)
- {
--    return gen_arith(ctx, a, &tcg_gen_or_tl);
-+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_or_tl);
- }
- static bool trans_and(DisasContext *ctx, arg_and *a)
- {
--    return gen_arith(ctx, a, &tcg_gen_and_tl);
-+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_and_tl);
- }
- static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
- {
-     REQUIRE_64BIT(ctx);
--    return gen_arith_imm_tl(ctx, a, &gen_addw);
-+    ctx->w = true;
-+    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
- }
- static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
-@@ -XXX,XX +XXX,XX @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
- static bool trans_addw(DisasContext *ctx, arg_addw *a)
- {
-     REQUIRE_64BIT(ctx);
--    return gen_arith(ctx, a, &gen_addw);
-+    ctx->w = true;
-+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
- }
- static bool trans_subw(DisasContext *ctx, arg_subw *a)
- {
-     REQUIRE_64BIT(ctx);
--    return gen_arith(ctx, a, &gen_subw);
-+    ctx->w = true;
-+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
- }
- static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
-diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvm.c.inc
-+++ b/target/riscv/insn_trans/trans_rvm.c.inc
-@@ -XXX,XX +XXX,XX @@
- static bool trans_mul(DisasContext *ctx, arg_mul *a)
- {
-     REQUIRE_EXT(ctx, RVM);
--    return gen_arith(ctx, a, &tcg_gen_mul_tl);
-+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
- }
- static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
-@@ -XXX,XX +XXX,XX @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
- static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
- {
-     REQUIRE_EXT(ctx, RVM);
--    return gen_arith(ctx, a, &gen_mulhsu);
-+    return gen_arith(ctx, a, EXT_NONE, gen_mulhsu);
- }
- static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
-@@ -XXX,XX +XXX,XX @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
- static bool trans_div(DisasContext *ctx, arg_div *a)
- {
-     REQUIRE_EXT(ctx, RVM);
--    return gen_arith(ctx, a, &gen_div);
-+    return gen_arith(ctx, a, EXT_SIGN, gen_div);
- }
- static bool trans_divu(DisasContext *ctx, arg_divu *a)
- {
-     REQUIRE_EXT(ctx, RVM);
--    return gen_arith(ctx, a, &gen_divu);
-+    return gen_arith(ctx, a, EXT_ZERO, gen_divu);
- }
- static bool trans_rem(DisasContext *ctx, arg_rem *a)
- {
-     REQUIRE_EXT(ctx, RVM);
--    return gen_arith(ctx, a, &gen_rem);
-+    return gen_arith(ctx, a, EXT_SIGN, gen_rem);
- }
- static bool trans_remu(DisasContext *ctx, arg_remu *a)
- {
-     REQUIRE_EXT(ctx, RVM);
--    return gen_arith(ctx, a, &gen_remu);
-+    return gen_arith(ctx, a, EXT_ZERO, gen_remu);
- }
- static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
- {
-     REQUIRE_64BIT(ctx);
-     REQUIRE_EXT(ctx, RVM);
--
--    return gen_arith(ctx, a, &gen_mulw);
-+    ctx->w = true;
-+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
- }
- static bool trans_divw(DisasContext *ctx, arg_divw *a)
---
-.31.1

-[PULL 17/33] target/riscv: Use gen_arith for mulh and mulhu
+[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Alistair Francis <alistair23@gmail.com>
-Split out gen_mulh and gen_mulhu and use the common helper.
+Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
 CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
 CSRs are part of the disassembly.
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Fixes: ea10325917 ("RISC-V Disassembler")
-Message-id: 20210823195529.560295-9-richard.henderson@linaro.org
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvm.c.inc | 40 +++++++++++--------------
+ disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
-file changed, 18 insertions(+), 22 deletions(-)
+file changed, 64 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
+diff --git a/disas/riscv.c b/disas/riscv.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvm.c.inc
+--- a/disas/riscv.c
-+++ b/target/riscv/insn_trans/trans_rvm.c.inc
++++ b/disas/riscv.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_mul(DisasContext *ctx, arg_mul *a)
+@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
-     return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
+     case 0x0383: return "mibound";
- }
+     case 0x0384: return "mdbase";
+     case 0x0385: return "mdbound";
--static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
+-    case 0x03a0: return "pmpcfg3";
-+static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
++    case 0x03a0: return "pmpcfg0";
- {
++    case 0x03a1: return "pmpcfg1";
--    REQUIRE_EXT(ctx, RVM);
++    case 0x03a2: return "pmpcfg2";
--    TCGv source1 = tcg_temp_new();
++    case 0x03a3: return "pmpcfg3";
--    TCGv source2 = tcg_temp_new();
++    case 0x03a4: return "pmpcfg4";
--    gen_get_gpr(ctx, source1, a->rs1);
++    case 0x03a5: return "pmpcfg5";
--    gen_get_gpr(ctx, source2, a->rs2);
++    case 0x03a6: return "pmpcfg6";
-+    TCGv discard = tcg_temp_new();
++    case 0x03a7: return "pmpcfg7";
++    case 0x03a8: return "pmpcfg8";
--    tcg_gen_muls2_tl(source2, source1, source1, source2);
++    case 0x03a9: return "pmpcfg9";
-+    tcg_gen_muls2_tl(discard, ret, s1, s2);
++    case 0x03aa: return "pmpcfg10";
-+    tcg_temp_free(discard);
++    case 0x03ab: return "pmpcfg11";
-+}
++    case 0x03ac: return "pmpcfg12";
++    case 0x03ad: return "pmpcfg13";
--    gen_set_gpr(ctx, a->rd, source1);
++    case 0x03ae: return "pmpcfg14";
--    tcg_temp_free(source1);
++    case 0x03af: return "pmpcfg15";
--    tcg_temp_free(source2);
+     case 0x03b0: return "pmpaddr0";
--    return true;
+     case 0x03b1: return "pmpaddr1";
-+static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
+     case 0x03b2: return "pmpaddr2";
-+{
+@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
-+    REQUIRE_EXT(ctx, RVM);
+     case 0x03bd: return "pmpaddr13";
-+    return gen_arith(ctx, a, EXT_NONE, gen_mulh);
+     case 0x03be: return "pmpaddr14";
- }
+     case 0x03bf: return "pmpaddr15";
++    case 0x03c0: return "pmpaddr16";
- static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
++    case 0x03c1: return "pmpaddr17";
-@@ -XXX,XX +XXX,XX @@ static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
++    case 0x03c2: return "pmpaddr18";
-     return gen_arith(ctx, a, EXT_NONE, gen_mulhsu);
++    case 0x03c3: return "pmpaddr19";
- }
++    case 0x03c4: return "pmpaddr20";
++    case 0x03c5: return "pmpaddr21";
--static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
++    case 0x03c6: return "pmpaddr22";
-+static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
++    case 0x03c7: return "pmpaddr23";
- {
++    case 0x03c8: return "pmpaddr24";
--    REQUIRE_EXT(ctx, RVM);
++    case 0x03c9: return "pmpaddr25";
--    TCGv source1 = tcg_temp_new();
++    case 0x03ca: return "pmpaddr26";
--    TCGv source2 = tcg_temp_new();
++    case 0x03cb: return "pmpaddr27";
--    gen_get_gpr(ctx, source1, a->rs1);
++    case 0x03cc: return "pmpaddr28";
--    gen_get_gpr(ctx, source2, a->rs2);
++    case 0x03cd: return "pmpaddr29";
-+    TCGv discard = tcg_temp_new();
++    case 0x03ce: return "pmpaddr30";
++    case 0x03cf: return "pmpaddr31";
--    tcg_gen_mulu2_tl(source2, source1, source1, source2);
++    case 0x03d0: return "pmpaddr32";
-+    tcg_gen_mulu2_tl(discard, ret, s1, s2);
++    case 0x03d1: return "pmpaddr33";
-+    tcg_temp_free(discard);
++    case 0x03d2: return "pmpaddr34";
-+}
++    case 0x03d3: return "pmpaddr35";
++    case 0x03d4: return "pmpaddr36";
--    gen_set_gpr(ctx, a->rd, source1);
++    case 0x03d5: return "pmpaddr37";
--    tcg_temp_free(source1);
++    case 0x03d6: return "pmpaddr38";
--    tcg_temp_free(source2);
++    case 0x03d7: return "pmpaddr39";
--    return true;
++    case 0x03d8: return "pmpaddr40";
-+static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
++    case 0x03d9: return "pmpaddr41";
-+{
++    case 0x03da: return "pmpaddr42";
-+    REQUIRE_EXT(ctx, RVM);
++    case 0x03db: return "pmpaddr43";
-+    return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
++    case 0x03dc: return "pmpaddr44";
- }
++    case 0x03dd: return "pmpaddr45";
++    case 0x03de: return "pmpaddr46";
- static bool trans_div(DisasContext *ctx, arg_div *a)
++    case 0x03df: return "pmpaddr47";
 +    case 0x03e0: return "pmpaddr48";
 +    case 0x03e1: return "pmpaddr49";
 +    case 0x03e2: return "pmpaddr50";
 +    case 0x03e3: return "pmpaddr51";
 +    case 0x03e4: return "pmpaddr52";
 +    case 0x03e5: return "pmpaddr53";
 +    case 0x03e6: return "pmpaddr54";
 +    case 0x03e7: return "pmpaddr55";
 +    case 0x03e8: return "pmpaddr56";
 +    case 0x03e9: return "pmpaddr57";
 +    case 0x03ea: return "pmpaddr58";
 +    case 0x03eb: return "pmpaddr59";
 +    case 0x03ec: return "pmpaddr60";
 +    case 0x03ed: return "pmpaddr61";
 +    case 0x03ee: return "pmpaddr62";
 +    case 0x03ef: return "pmpaddr63";
      case 0x0780: return "mtohost";
      case 0x0781: return "mfromhost";
      case 0x0782: return "mreset";
 --
-.31.1
+.45.1

-[PULL 26/33] target/riscv: Fix hgeie, hgeip
+[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Yu-Ming Chang <yumin686@andestech.com>
-We failed to write into *val for these read functions;
+Both CSRRS and CSRRC always read the addressed CSR and cause any read side
-replace them with read_zero.  Only warn about unsupported
+effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
-non-zero value when writing a non-zero value.
+holding a zero value other than x0, the instruction will still attempt to write
 the unmodified value back to the CSR and will cause any attendant side effects.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
-Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+a register holding a zero value, an illegal instruction exception should be
 raised.
 Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 20210823195529.560295-18-richard.henderson@linaro.org
+Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 26 ++++++++------------------
+ target/riscv/cpu.h       |  4 ++++
-file changed, 8 insertions(+), 18 deletions(-)
+ target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
  target/riscv/op_helper.c |  6 ++---
 files changed, 53 insertions(+), 8 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
+ void riscv_cpu_update_mask(CPURISCVState *env);
+ bool riscv_cpu_is_32bit(RISCVCPU *cpu);
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
++                          target_ulong *ret_value);
+ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
+                            target_ulong *ret_value,
+                            target_ulong new_value, target_ulong write_mask);
+@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
+                                           target_ulong new_value,
+                                           target_ulong write_mask);
++RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
++                               Int128 *ret_value);
+ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
+                                 Int128 *ret_value,
+                                 Int128 new_value, Int128 write_mask);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
  static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                 int csrno,
 -                                               bool write_mask)
 +                                               bool write)
  {
      /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
      bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
      }
      /* read / write check */
 -    if (write_mask && read_only) {
 +    if (write && read_only) {
          return RISCV_EXCP_ILLEGAL_INST;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
--static RISCVException read_hgeie(CPURISCVState *env, int csrno,
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
--                                 target_ulong *val)
++                           target_ulong *ret_value)
--{
++{
--    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
++    RISCVException ret = riscv_csrrw_check(env, csrno, false);
--    return RISCV_EXCP_NONE;
++    if (ret != RISCV_EXCP_NONE) {
--}
++        return ret;
--
++    }
- static RISCVException write_hgeie(CPURISCVState *env, int csrno,
++
-                                   target_ulong val)
++    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
 +}
 +
  RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                             target_ulong *ret_value,
                             target_ulong new_value, target_ulong write_mask)
  {
--    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+-    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
-+    if (val) {
++    RISCVException ret = riscv_csrrw_check(env, csrno, true);
-+        qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+     if (ret != RISCV_EXCP_NONE) {
-+    }
+         return ret;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_htinst(CPURISCVState *env, int csrno,
++RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
-     return RISCV_EXCP_NONE;
++                               Int128 *ret_value)
- }
++{
++    RISCVException ret;
--static RISCVException read_hgeip(CPURISCVState *env, int csrno,
++
--                                 target_ulong *val)
++    ret = riscv_csrrw_check(env, csrno, false);
--{
++    if (ret != RISCV_EXCP_NONE) {
--    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
++        return ret;
--    return RISCV_EXCP_NONE;
++    }
--}
++
--
++    if (csr_ops[csrno].read128) {
- static RISCVException write_hgeip(CPURISCVState *env, int csrno,
++        return riscv_csrrw_do128(env, csrno, ret_value,
-                                   target_ulong val)
++                                 int128_zero(), int128_zero());
 +    }
 +
 +    /*
 +     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
 +     * at all defined.
 +     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
 +     * significant), for those, this fallback is correctly handling the
 +     * accesses
 +     */
 +    target_ulong old_value;
 +    ret = riscv_csrrw_do64(env, csrno, &old_value,
 +                           (target_ulong)0,
 +                           (target_ulong)0);
 +    if (ret == RISCV_EXCP_NONE && ret_value) {
 +        *ret_value = int128_make64(old_value);
 +    }
 +    return ret;
 +}
 +
  RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                  Int128 *ret_value,
                                  Int128 new_value, Int128 write_mask)
  {
--    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+     RISCVException ret;
-+    if (val) {
-+        qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
-+    }
++    ret = riscv_csrrw_check(env, csrno, true);
-     return RISCV_EXCP_NONE;
+     if (ret != RISCV_EXCP_NONE) {
- }
+         return ret;
+     }
-@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
+diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
-     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
+index XXXXXXX..XXXXXXX 100644
-     [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
+--- a/target/riscv/op_helper.c
-     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
++++ b/target/riscv/op_helper.c
--    [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,       write_hgeie       },
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
-+    [CSR_HGEIE]       = { "hgeie",       hmode,   read_zero,        write_hgeie       },
+     }
-     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
-     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
+     target_ulong val = 0;
--    [CSR_HGEIP]       = { "hgeip",       hmode,   read_hgeip,       write_hgeip       },
+-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
-+    [CSR_HGEIP]       = { "hgeip",       hmode,   read_zero,        write_hgeip       },
++    RISCVException ret = riscv_csrr(env, csr, &val);
-     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
-     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
+     if (ret != RISCV_EXCP_NONE) {
-     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
+         riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
  target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
  {
      Int128 rv = int128_zero();
 -    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
 -                                          int128_zero(),
 -                                          int128_zero());
 +    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
      if (ret != RISCV_EXCP_NONE) {
          riscv_raise_exception(env, ret, GETPC());
 --
-.31.1
+.45.1

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit d52dff5d8048d4982437db9606c27bb4127cf9d0:

Merge remote-tracking branch 'remotes/marcandre/tags/clip-pull-request' into staging (2021-08-31 14:38:15 +0100)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210901-2

for you to fetch changes up to 8e034ae44dba6291beb07f7f2a932c1e5ab83e98:

target/riscv: Use {get,dest}_gpr for RVV (2021-09-01 11:59:12 +1000)

----------------------------------------------------------------
First RISC-V PR for QEMU 6.2

- Add a config for Shakti UART
 - Fixup virt flash node
 - Don't override users supplied ISA version
 - Fixup some CSR accesses
 - Use g_strjoinv() for virt machine PLIC string config
 - Fix an overflow in the SiFive CLINT
 - Add 64-bit register access helpers
 - Replace tcg_const_* with direct constant usage

----------------------------------------------------------------
Bin Meng (2):
      hw/riscv: virt: Move flash node to root
      target/riscv: Correct a comment in riscv_csrrw()

David Hoppenbrouwers (1):
      hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp()

Joe Komlodi (2):
      hw/core/register: Add more 64-bit utilities
      hw/registerfields: Use 64-bit bitfield for FIELD_DP64

LIU Zhiwei (2):
      target/riscv: Don't wrongly override isa version
      target/riscv: Add User CSRs read-only check

Peter Maydell (1):
      hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()

Richard Henderson (24):
      target/riscv: Use tcg_constant_*
      tests/tcg/riscv64: Add test for division
      target/riscv: Clean up division helpers
      target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
      target/riscv: Introduce DisasExtend and new helpers
      target/riscv: Add DisasExtend to gen_arith*
      target/riscv: Remove gen_arith_div*
      target/riscv: Use gen_arith for mulh and mulhu
      target/riscv: Move gen_* helpers for RVM
      target/riscv: Move gen_* helpers for RVB
      target/riscv: Add DisasExtend to gen_unary
      target/riscv: Use DisasExtend in shift operations
      target/riscv: Use extracts for sraiw and srliw
      target/riscv: Use get_gpr in branches
      target/riscv: Use {get, dest}_gpr for integer load/store
      target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation
      target/riscv: Fix hgeie, hgeip
      target/riscv: Reorg csr instructions
      target/riscv: Use {get,dest}_gpr for RVA
      target/riscv: Use gen_shift_imm_fn for slli_uw
      target/riscv: Use {get,dest}_gpr for RVF
      target/riscv: Use {get,dest}_gpr for RVD
      target/riscv: Tidy trans_rvh.c.inc
      target/riscv: Use {get,dest}_gpr for RVV

Vijai Kumar K (1):
      hw/char: Add config for shakti uart

include/hw/register.h                   |   8 +
 include/hw/registerfields.h             |  10 +-
 target/riscv/helper.h                   |   6 +-
 target/riscv/insn32.decode              |   1 +
 hw/core/register.c                      |  12 +
 hw/intc/sifive_clint.c                  |  25 +-
 hw/riscv/virt.c                         |  35 +-
 target/riscv/cpu.c                      |  14 +-
 target/riscv/csr.c                      |  59 ++-
 target/riscv/op_helper.c                |  18 +-
 target/riscv/translate.c                | 689 +++++++-------------------------
 tests/tcg/riscv64/test-div.c            |  58 +++
 target/riscv/insn_trans/trans_rva.c.inc |  49 +--
 target/riscv/insn_trans/trans_rvb.c.inc | 366 +++++++++++++----
 target/riscv/insn_trans/trans_rvd.c.inc | 127 +++---
 target/riscv/insn_trans/trans_rvf.c.inc | 149 ++++---
 target/riscv/insn_trans/trans_rvh.c.inc | 266 +++---------
 target/riscv/insn_trans/trans_rvi.c.inc | 372 +++++++++--------
 target/riscv/insn_trans/trans_rvm.c.inc | 193 +++++++--
 target/riscv/insn_trans/trans_rvv.c.inc | 149 +++----
 hw/char/Kconfig                         |   3 +
 hw/char/meson.build                     |   2 +-
 hw/riscv/Kconfig                        |   5 +-
 tests/tcg/riscv64/Makefile.target       |   5 +
 24 files changed, 1240 insertions(+), 1381 deletions(-)
 create mode 100644 tests/tcg/riscv64/test-div.c
 create mode 100644 tests/tcg/riscv64/Makefile.target

From: Vijai Kumar K <vijai@behindbytes.com>

Use a dedicated UART config(CONFIG_SHAKTI_UART) to select
shakti uart.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210731190229.137483-1-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/char/Kconfig     | 3 +++
 hw/char/meson.build | 2 +-
 hw/riscv/Kconfig    | 5 +----
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_UART
 
 config GOLDFISH_TTY
     bool
+
+config SHAKTI_UART
+    bool
diff --git a/hw/char/meson.build b/hw/char/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('serial.c'))
 softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c'))
 softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c'))
 softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci-multi.c'))
-softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c'))
+softmmu_ss.add(when: 'CONFIG_SHAKTI_UART', if_true: files('shakti_uart.c'))
 softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-console.c'))
 softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c'))
 softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config OPENTITAN
     select IBEX
     select UNIMP
 
-config SHAKTI
-    bool
-
 config SHAKTI_C
     bool
     select UNIMP
-    select SHAKTI
+    select SHAKTI_UART
     select SIFIVE_CLINT
     select SIFIVE_PLIC
 
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

The flash is not inside the SoC, so it's inappropriate to put it
under the /soc node. Move it to root instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210807035641.22449-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
     qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ);
     g_free(name);
 
-    name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase);
+    name = g_strdup_printf("/flash@%" PRIx64, flashbase);
     qemu_fdt_add_subnode(mc->fdt, name);
     qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
     qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

For some cpu, the isa version has already been set in cpu init function.
Thus only override the isa version when isa version is not set, or
users set different isa version explicitly by cpu parameters.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210811144612.68674-1-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     RISCVCPU *cpu = RISCV_CPU(dev);
     CPURISCVState *env = &cpu->env;
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
-    int priv_version = PRIV_VERSION_1_11_0;
-    int bext_version = BEXT_VERSION_0_93_0;
-    int vext_version = VEXT_VERSION_0_07_1;
+    int priv_version = 0;
     target_ulong target_misa = env->misa;
     Error *local_err = NULL;
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         }
     }
 
-    set_priv_version(env, priv_version);
-    set_bext_version(env, bext_version);
-    set_vext_version(env, vext_version);
+    if (priv_version) {
+        set_priv_version(env, priv_version);
+    } else if (!env->priv_ver) {
+        set_priv_version(env, PRIV_VERSION_1_11_0);
+    }
 
     if (cpu->cfg.mmu) {
         set_feature(env, RISCV_FEATURE_MMU);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             target_misa |= RVH;
         }
         if (cpu->cfg.ext_b) {
+            int bext_version = BEXT_VERSION_0_93_0;
             target_misa |= RVB;
 
             if (cpu->cfg.bext_spec) {
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             set_bext_version(env, bext_version);
         }
         if (cpu->cfg.ext_v) {
+            int vext_version = VEXT_VERSION_0_07_1;
             target_misa |= RVV;
             if (!is_power_of_2(cpu->cfg.vlen)) {
                 error_setg(errp,
-- 
2.31.1

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

For U-mode CSRs, read-only check is also needed.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210810014552.4884-1-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
     RISCVException ret;
     target_ulong old_value;
     RISCVCPU *cpu = env_archcpu(env);
+    int read_only = get_field(csrno, 0xC00) == 3;
 
     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
 #if !defined(CONFIG_USER_ONLY)
     int effective_priv = env->priv;
-    int read_only = get_field(csrno, 0xC00) == 3;
 
     if (riscv_has_ext(env, RVH) &&
         env->priv == PRV_S &&
@@ -XXX,XX +XXX,XX @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
         effective_priv++;
     }
 
-    if ((write_mask && read_only) ||
-        (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
+    if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
+    if (write_mask && read_only) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
 
     /* ensure the CSR extension is enabled. */
     if (!cpu->cfg.ext_icsr) {
-- 
2.31.1

From: Peter Maydell <peter.maydell@linaro.org>

In the riscv virt machine init function, We assemble a string
plic_hart_config which is a comma-separated list of N copies of the
VIRT_PLIC_HART_CONFIG string.  The code that does this has a
misunderstanding of the strncat() length argument.  If the source
string is too large strncat() will write a maximum of length+1 bytes
(length bytes from the source string plus a trailing NUL), but the
code here assumes that it will write only length bytes at most.

This isn't an actual bug because the code has correctly precalculated
the amount of memory it needs to allocate so that it will never be
too small (i.e.  we could have used plain old strcat()), but it does
mean that the code looks like it has a guard against accidental
overrun when it doesn't.

Rewrite the string handling here to use the glib g_strjoinv()
function, which means we don't need to do careful accountancy of
string lengths, and makes it clearer that what we're doing is
"create a comma-separated string".

Fixes: Coverity 1460752
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210812144647.10516-1-peter.maydell@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 33 ++++++++++++++++++++-------------
 1 file changed, 20 insertions(+), 13 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static FWCfgState *create_fw_cfg(const MachineState *mc)
     return fw_cfg;
 }
 
+/*
+ * Return the per-socket PLIC hart topology configuration string
+ * (caller must free with g_free())
+ */
+static char *plic_hart_config_string(int hart_count)
+{
+    g_autofree const char **vals = g_new(const char *, hart_count + 1);
+    int i;
+
+    for (i = 0; i < hart_count; i++) {
+        vals[i] = VIRT_PLIC_HART_CONFIG;
+    }
+    vals[i] = NULL;
+
+    /* g_strjoinv() obliges us to cast away const here */
+    return g_strjoinv(",", (char **)vals);
+}
+
 static void virt_machine_init(MachineState *machine)
 {
     const MemMapEntry *memmap = virt_memmap;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
     char *plic_hart_config, *soc_name;
-    size_t plic_hart_config_len;
     target_ulong start_addr = memmap[VIRT_DRAM].base;
     target_ulong firmware_end_addr, kernel_start_addr;
     uint32_t fdt_load_addr;
     uint64_t kernel_entry;
     DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
-    int i, j, base_hartid, hart_count;
+    int i, base_hartid, hart_count;
 
     /* Check socket count limit */
     if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
             SIFIVE_CLINT_TIMEBASE_FREQ, true);
 
         /* Per-socket PLIC hart topology configuration string */
-        plic_hart_config_len =
-            (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count;
-        plic_hart_config = g_malloc0(plic_hart_config_len);
-        for (j = 0; j < hart_count; j++) {
-            if (j != 0) {
-                strncat(plic_hart_config, ",", plic_hart_config_len);
-            }
-            strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG,
-                plic_hart_config_len);
-            plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
-        }
+        plic_hart_config = plic_hart_config_string(hart_count);
 
         /* Per-socket PLIC */
         s->plic[i] = sifive_plic_create(
-- 
2.31.1

From: David Hoppenbrouwers <david@salt-inc.org>

`muldiv64` would overflow in cases where the final 96-bit value does not
fit in a `uint64_t`. This would result in small values that cause an
interrupt to be triggered much sooner than intended.

The overflow can be detected in most cases by checking if the new value is
smaller than the previous value. If the final result is larger than
`diff` it is either correct or it doesn't matter as it is effectively
infinite anyways.

`next` is an `uint64_t` value, but `timer_mod` takes an `int64_t`. This
resulted in high values such as `UINT64_MAX` being converted to `-1`,
which caused an immediate timer interrupt.

By limiting `next` to `INT64_MAX` no overflow will happen while the
timer will still be effectively set to "infinitely" far in the future.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/493
Signed-off-by: David Hoppenbrouwers <david@salt-inc.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210827152324.5201-1-david@salt-inc.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/sifive_clint.c | 25 +++++++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/hw/intc/sifive_clint.c b/hw/intc/sifive_clint.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_clint.c
+++ b/hw/intc/sifive_clint.c
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value,
     riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
     diff = cpu->env.timecmp - rtc_r;
     /* back to ns (note args switched in muldiv64) */
-    next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
-        muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
+    uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
+
+    /*
+     * check if ns_diff overflowed and check if the addition would potentially
+     * overflow
+     */
+    if ((NANOSECONDS_PER_SECOND > timebase_freq && ns_diff < diff) ||
+        ns_diff > INT64_MAX) {
+        next = INT64_MAX;
+    } else {
+        /*
+         * as it is very unlikely qemu_clock_get_ns will return a value
+         * greater than INT64_MAX, no additional check is needed for an
+         * unsigned integer overflow.
+         */
+        next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns_diff;
+        /*
+         * if ns_diff is INT64_MAX next may still be outside the range
+         * of a signed integer.
+         */
+        next = MIN(next, INT64_MAX);
+    }
+
     timer_mod(cpu->env.timer, next);
 }
 
-- 
2.31.1

From: Joe Komlodi <joe.komlodi@xilinx.com>

We already have some utilities to handle 64-bit wide registers, so this just
adds some more for:
- Initializing 64-bit registers
- Extracting and depositing to an array of 64-bit registers

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1626805903-162860-2-git-send-email-joe.komlodi@xilinx.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/register.h       |  8 ++++++++
 include/hw/registerfields.h |  8 ++++++++
 hw/core/register.c          | 12 ++++++++++++
 3 files changed, 28 insertions(+)

diff --git a/include/hw/register.h b/include/hw/register.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/register.h
+++ b/include/hw/register.h
@@ -XXX,XX +XXX,XX @@ RegisterInfoArray *register_init_block32(DeviceState *owner,
                                          bool debug_enabled,
                                          uint64_t memory_size);
 
+RegisterInfoArray *register_init_block64(DeviceState *owner,
+                                         const RegisterAccessInfo *rae,
+                                         int num, RegisterInfo *ri,
+                                         uint64_t *data,
+                                         const MemoryRegionOps *ops,
+                                         bool debug_enabled,
+                                         uint64_t memory_size);
+
 /**
  * This function should be called to cleanup the registers that were initialized
  * when calling register_init_block32(). This function should only be called
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -XXX,XX +XXX,XX @@
     enum { A_ ## reg = (addr) };                                          \
     enum { R_ ## reg = (addr) / 2 };
 
+#define REG64(reg, addr)                                                  \
+    enum { A_ ## reg = (addr) };                                          \
+    enum { R_ ## reg = (addr) / 8 };
+
 /* Define SHIFT, LENGTH and MASK constants for a field within a register */
 
 /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
@@ -XXX,XX +XXX,XX @@
 /* Extract a field from an array of registers */
 #define ARRAY_FIELD_EX32(regs, reg, field)                                \
     FIELD_EX32((regs)[R_ ## reg], reg, field)
+#define ARRAY_FIELD_EX64(regs, reg, field)                                \
+    FIELD_EX64((regs)[R_ ## reg], reg, field)
 
 /* Deposit a register field.
  * Assigning values larger then the target field will result in
@@ -XXX,XX +XXX,XX @@
 /* Deposit a field to array of registers.  */
 #define ARRAY_FIELD_DP32(regs, reg, field, val)                           \
     (regs)[R_ ## reg] = FIELD_DP32((regs)[R_ ## reg], reg, field, val);
+#define ARRAY_FIELD_DP64(regs, reg, field, val)                           \
+    (regs)[R_ ## reg] = FIELD_DP64((regs)[R_ ## reg], reg, field, val);
 
 #endif
diff --git a/hw/core/register.c b/hw/core/register.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/register.c
+++ b/hw/core/register.c
@@ -XXX,XX +XXX,XX @@ RegisterInfoArray *register_init_block32(DeviceState *owner,
                                data, ops, debug_enabled, memory_size, 32);
 }
 
+RegisterInfoArray *register_init_block64(DeviceState *owner,
+                                         const RegisterAccessInfo *rae,
+                                         int num, RegisterInfo *ri,
+                                         uint64_t *data,
+                                         const MemoryRegionOps *ops,
+                                         bool debug_enabled,
+                                         uint64_t memory_size)
+{
+    return register_init_block(owner, rae, num, ri, (void *)
+                               data, ops, debug_enabled, memory_size, 64);
+}
+
 void register_finalize_block(RegisterInfoArray *r_array)
 {
     object_unparent(OBJECT(&r_array->mem));
-- 
2.31.1

From: Joe Komlodi <joe.komlodi@xilinx.com>

If we have a field that's wider than 32-bits, we need a data type wide enough to
be able to create the bitfield used to deposit the value.

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1626805903-162860-3-git-send-email-joe.komlodi@xilinx.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/registerfields.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -XXX,XX +XXX,XX @@
     _d; })
 #define FIELD_DP64(storage, reg, field, val) ({                           \
     struct {                                                              \
-        unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
+        uint64_t v:R_ ## reg ## _ ## field ## _LENGTH;                \
     } _v = { .v = val };                                                  \
     uint64_t _d;                                                          \
     _d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT,          \
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Replace uses of tcg_const_* with the allocate and free close together.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-2-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 36 ++++----------
 target/riscv/insn_trans/trans_rvf.c.inc |  3 +-
 target/riscv/insn_trans/trans_rvv.c.inc | 65 +++++++++----------------
 3 files changed, 34 insertions(+), 70 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
  */
 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
 {
-    TCGv_i64 t_max = tcg_const_i64(0xffffffff00000000ull);
-    TCGv_i64 t_nan = tcg_const_i64(0xffffffff7fc00000ull);
+    TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull);
+    TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull);
 
     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
-    tcg_temp_free_i64(t_max);
-    tcg_temp_free_i64(t_nan);
 }
 
 static void generate_exception(DisasContext *ctx, int excp)
 {
     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-    TCGv_i32 helper_tmp = tcg_const_i32(excp);
-    gen_helper_raise_exception(cpu_env, helper_tmp);
-    tcg_temp_free_i32(helper_tmp);
+    gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
 {
     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
-    TCGv_i32 helper_tmp = tcg_const_i32(excp);
-    gen_helper_raise_exception(cpu_env, helper_tmp);
-    tcg_temp_free_i32(helper_tmp);
+    gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
 static void gen_exception_debug(void)
 {
-    TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG);
-    gen_helper_raise_exception(cpu_env, helper_tmp);
-    tcg_temp_free_i32(helper_tmp);
+    gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
 }
 
 /* Wrapper around tcg_gen_exit_tb that handles single stepping */
@@ -XXX,XX +XXX,XX @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2)
      */
     cond1 = tcg_temp_new();
     cond2 = tcg_temp_new();
-    zeroreg = tcg_const_tl(0);
+    zeroreg = tcg_constant_tl(0);
     resultopt1 = tcg_temp_new();
 
     tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
@@ -XXX,XX +XXX,XX @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2)
 
     tcg_temp_free(cond1);
     tcg_temp_free(cond2);
-    tcg_temp_free(zeroreg);
     tcg_temp_free(resultopt1);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
     TCGv cond1, zeroreg, resultopt1;
     cond1 = tcg_temp_new();
 
-    zeroreg = tcg_const_tl(0);
+    zeroreg = tcg_constant_tl(0);
     resultopt1 = tcg_temp_new();
 
     tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
@@ -XXX,XX +XXX,XX @@ static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
     tcg_gen_divu_tl(ret, source1, source2);
 
     tcg_temp_free(cond1);
-    tcg_temp_free(zeroreg);
     tcg_temp_free(resultopt1);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
 
     cond1 = tcg_temp_new();
     cond2 = tcg_temp_new();
-    zeroreg = tcg_const_tl(0);
+    zeroreg = tcg_constant_tl(0);
     resultopt1 = tcg_temp_new();
 
     tcg_gen_movi_tl(resultopt1, 1L);
@@ -XXX,XX +XXX,XX @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
 
     tcg_temp_free(cond1);
     tcg_temp_free(cond2);
-    tcg_temp_free(zeroreg);
     tcg_temp_free(resultopt1);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
 {
     TCGv cond1, zeroreg, resultopt1;
     cond1 = tcg_temp_new();
-    zeroreg = tcg_const_tl(0);
+    zeroreg = tcg_constant_tl(0);
     resultopt1 = tcg_temp_new();
 
     tcg_gen_movi_tl(resultopt1, (target_ulong)1);
@@ -XXX,XX +XXX,XX @@ static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
             source1);
 
     tcg_temp_free(cond1);
-    tcg_temp_free(zeroreg);
     tcg_temp_free(resultopt1);
 }
 
@@ -XXX,XX +XXX,XX @@ static inline void mark_fs_dirty(DisasContext *ctx) { }
 
 static void gen_set_rm(DisasContext *ctx, int rm)
 {
-    TCGv_i32 t0;
-
     if (ctx->frm == rm) {
         return;
     }
     ctx->frm = rm;
-    t0 = tcg_const_i32(rm);
-    gen_helper_set_rounding_mode(cpu_env, t0);
-    tcg_temp_free_i32(t0);
+    gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
 }
 
 static int ex_plus_1(DisasContext *ctx, int nf)
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
          * Replace bit 31 in rs1 with inverse in rs2.
          * This formulation retains the nanboxing of rs1.
          */
-        mask = tcg_const_i64(~MAKE_64BIT_MASK(31, 1));
+        mask = tcg_constant_i64(~MAKE_64BIT_MASK(31, 1));
         tcg_gen_nor_i64(rs2, rs2, mask);
         tcg_gen_and_i64(rs1, mask, rs1);
         tcg_gen_or_i64(cpu_fpr[a->rd], rs1, rs2);
 
-        tcg_temp_free_i64(mask);
         tcg_temp_free_i64(rs2);
     }
     tcg_temp_free_i64(rs1);
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
     /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
     if (a->rs1 == 0) {
         /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
-        s1 = tcg_const_tl(RV_VLEN_MAX);
+        s1 = tcg_constant_tl(RV_VLEN_MAX);
     } else {
         s1 = tcg_temp_new();
         gen_get_gpr(s1, a->rs1);
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
         return false;
     }
 
-    s2 = tcg_const_tl(a->zimm);
+    s2 = tcg_constant_tl(a->zimm);
     dst = tcg_temp_new();
 
     /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
     if (a->rs1 == 0) {
         /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
-        s1 = tcg_const_tl(RV_VLEN_MAX);
+        s1 = tcg_constant_tl(RV_VLEN_MAX);
     } else {
         s1 = tcg_temp_new();
         gen_get_gpr(s1, a->rs1);
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
     ctx->base.is_jmp = DISAS_NORETURN;
 
     tcg_temp_free(s1);
-    tcg_temp_free(s2);
     tcg_temp_free(dst);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      * The first part is vlen in bytes, encoded in maxsz of simd_desc.
      * The second part is lmul, encoded in data of simd_desc.
      */
-    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     gen_get_gpr(base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
     tcg_temp_free_ptr(dest);
     tcg_temp_free_ptr(mask);
     tcg_temp_free(base);
-    tcg_temp_free_i32(desc);
     gen_set_label(over);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
     mask = tcg_temp_new_ptr();
     base = tcg_temp_new();
     stride = tcg_temp_new();
-    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     gen_get_gpr(base, rs1);
     gen_get_gpr(stride, rs2);
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
     tcg_temp_free_ptr(mask);
     tcg_temp_free(base);
     tcg_temp_free(stride);
-    tcg_temp_free_i32(desc);
     gen_set_label(over);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     mask = tcg_temp_new_ptr();
     index = tcg_temp_new_ptr();
     base = tcg_temp_new();
-    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     gen_get_gpr(base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     tcg_temp_free_ptr(mask);
     tcg_temp_free_ptr(index);
     tcg_temp_free(base);
-    tcg_temp_free_i32(desc);
     gen_set_label(over);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
     base = tcg_temp_new();
-    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     gen_get_gpr(base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
     tcg_temp_free_ptr(dest);
     tcg_temp_free_ptr(mask);
     tcg_temp_free(base);
-    tcg_temp_free_i32(desc);
     gen_set_label(over);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     mask = tcg_temp_new_ptr();
     index = tcg_temp_new_ptr();
     base = tcg_temp_new();
-    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     gen_get_gpr(base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@@ -XXX,XX +XXX,XX @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     tcg_temp_free_ptr(mask);
     tcg_temp_free_ptr(index);
     tcg_temp_free(base);
-    tcg_temp_free_i32(desc);
     gen_set_label(over);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
     data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
     data = FIELD_DP32(data, VDATA, VM, vm);
     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
     tcg_temp_free_ptr(mask);
     tcg_temp_free_ptr(src2);
     tcg_temp_free(src1);
-    tcg_temp_free_i32(desc);
     gen_set_label(over);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
     mask = tcg_temp_new_ptr();
     src2 = tcg_temp_new_ptr();
     if (zx) {
-        src1 = tcg_const_tl(imm);
+        src1 = tcg_constant_tl(imm);
     } else {
-        src1 = tcg_const_tl(sextract64(imm, 0, 5));
+        src1 = tcg_constant_tl(sextract64(imm, 0, 5));
     }
     data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
     data = FIELD_DP32(data, VDATA, VM, vm);
     data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
     tcg_temp_free_ptr(dest);
     tcg_temp_free_ptr(mask);
     tcg_temp_free_ptr(src2);
-    tcg_temp_free(src1);
-    tcg_temp_free_i32(desc);
     gen_set_label(over);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ GEN_OPIVI_GVEC_TRANS(vadd_vi, 0, vadd_vx, addi)
 static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs,
                                int64_t c, uint32_t oprsz, uint32_t maxsz)
 {
-    TCGv_i64 tmp = tcg_const_i64(c);
+    TCGv_i64 tmp = tcg_constant_i64(c);
     tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz);
-    tcg_temp_free_i64(tmp);
 }
 
 GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi)
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
             tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
                                 MAXSZ(s), MAXSZ(s), s1);
         } else {
-            TCGv_i32 desc ;
+            TCGv_i32 desc;
             TCGv_i64 s1_i64 = tcg_temp_new_i64();
             TCGv_ptr dest = tcg_temp_new_ptr();
             uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
             };
 
             tcg_gen_ext_tl_i64(s1_i64, s1);
-            desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
             fns[s->sew](dest, s1_i64, cpu_env, desc);
 
             tcg_temp_free_ptr(dest);
-            tcg_temp_free_i32(desc);
             tcg_temp_free_i64(s1_i64);
         }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
             TCGLabel *over = gen_new_label();
             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 
-            s1 = tcg_const_i64(simm);
+            s1 = tcg_constant_i64(simm);
             dest = tcg_temp_new_ptr();
-            desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
             fns[s->sew](dest, s1, cpu_env, desc);
 
             tcg_temp_free_ptr(dest);
-            tcg_temp_free_i32(desc);
-            tcg_temp_free_i64(s1);
             gen_set_label(over);
         }
         return true;
@@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
     src2 = tcg_temp_new_ptr();
-    desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+    desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     tcg_temp_free_ptr(dest);
     tcg_temp_free_ptr(mask);
     tcg_temp_free_ptr(src2);
-    tcg_temp_free_i32(desc);
     gen_set_label(over);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 
             dest = tcg_temp_new_ptr();
-            desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+            desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
             tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
             fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
 
             tcg_temp_free_ptr(dest);
-            tcg_temp_free_i32(desc);
             gen_set_label(over);
         }
         return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
         mask = tcg_temp_new_ptr();
         src2 = tcg_temp_new_ptr();
         dst = tcg_temp_new();
-        desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+        desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
         tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
         tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
         tcg_temp_free_ptr(mask);
         tcg_temp_free_ptr(src2);
         tcg_temp_free(dst);
-        tcg_temp_free_i32(desc);
         return true;
     }
     return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
         mask = tcg_temp_new_ptr();
         src2 = tcg_temp_new_ptr();
         dst = tcg_temp_new();
-        desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
+        desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
         tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
         tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
         tcg_temp_free_ptr(mask);
         tcg_temp_free_ptr(src2);
         tcg_temp_free(dst);
-        tcg_temp_free_i32(desc);
         return true;
     }
     return false;
@@ -XXX,XX +XXX,XX @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
     tcg_temp_free_i32(ofs);
 
     /* Flush out-of-range indexing to zero.  */
-    t_vlmax = tcg_const_i64(vlmax);
-    t_zero = tcg_const_i64(0);
+    t_vlmax = tcg_constant_i64(vlmax);
+    t_zero = tcg_constant_i64(0);
     tcg_gen_extu_tl_i64(t_idx, idx);
 
     tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx,
                         t_vlmax, dest, t_zero);
 
-    tcg_temp_free_i64(t_vlmax);
-    tcg_temp_free_i64(t_zero);
     tcg_temp_free_i64(t_idx);
 }
 
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-3-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 tests/tcg/riscv64/test-div.c      | 58 +++++++++++++++++++++++++++++++
 tests/tcg/riscv64/Makefile.target |  5 +++
 2 files changed, 63 insertions(+)
 create mode 100644 tests/tcg/riscv64/test-div.c
 create mode 100644 tests/tcg/riscv64/Makefile.target

diff --git a/tests/tcg/riscv64/test-div.c b/tests/tcg/riscv64/test-div.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/tcg/riscv64/test-div.c
@@ -XXX,XX +XXX,XX @@
+#include <assert.h>
+#include <limits.h>
+
+struct TestS {
+    long x, y, q, r;
+};
+
+static struct TestS test_s[] = {
+    { 4, 2, 2, 0 },                 /* normal cases */
+    { 9, 7, 1, 2 },
+    { 0, 0, -1, 0 },                /* div by zero cases */
+    { 9, 0, -1, 9 },
+    { LONG_MIN, -1, LONG_MIN, 0 },  /* overflow case */
+};
+
+struct TestU {
+    unsigned long x, y, q, r;
+};
+
+static struct TestU test_u[] = {
+    { 4, 2, 2, 0 },                 /* normal cases */
+    { 9, 7, 1, 2 },
+    { 0, 0, ULONG_MAX, 0 },         /* div by zero cases */
+    { 9, 0, ULONG_MAX, 9 },
+};
+
+#define ARRAY_SIZE(X)  (sizeof(X) / sizeof(*(X)))
+
+int main (void)
+{
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(test_s); i++) {
+        long q, r;
+
+        asm("div %0, %2, %3\n\t"
+            "rem %1, %2, %3"
+            : "=&r" (q), "=r" (r)
+            : "r" (test_s[i].x), "r" (test_s[i].y));
+
+        assert(q == test_s[i].q);
+        assert(r == test_s[i].r);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(test_u); i++) {
+        unsigned long q, r;
+
+        asm("divu %0, %2, %3\n\t"
+            "remu %1, %2, %3"
+            : "=&r" (q), "=r" (r)
+            : "r" (test_u[i].x), "r" (test_u[i].y));
+
+        assert(q == test_u[i].q);
+        assert(r == test_u[i].r);
+    }
+
+    return 0;
+}
diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/tcg/riscv64/Makefile.target
@@ -XXX,XX +XXX,XX @@
+# -*- Mode: makefile -*-
+# RISC-V specific tweaks
+
+VPATH += $(SRC_PATH)/tests/tcg/riscv64
+TESTS += test-div
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Utilize the condition in the movcond more; this allows some of
the setcond that were feeding into movcond to be removed.
Do not write into source1 and source2.  Re-name "condN" to "tempN"
and use the temporaries for more than holding conditions.

Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-4-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 174 ++++++++++++++++++++-------------------
 1 file changed, 91 insertions(+), 83 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
 
 static void gen_div(TCGv ret, TCGv source1, TCGv source2)
 {
-    TCGv cond1, cond2, zeroreg, resultopt1;
+    TCGv temp1, temp2, zero, one, mone, min;
+
+    temp1 = tcg_temp_new();
+    temp2 = tcg_temp_new();
+    zero = tcg_constant_tl(0);
+    one = tcg_constant_tl(1);
+    mone = tcg_constant_tl(-1);
+    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
+
     /*
-     * Handle by altering args to tcg_gen_div to produce req'd results:
-     * For overflow: want source1 in source1 and 1 in source2
-     * For div by zero: want -1 in source1 and 1 in source2 -> -1 result
+     * If overflow, set temp2 to 1, else source2.
+     * This produces the required result of min.
      */
-    cond1 = tcg_temp_new();
-    cond2 = tcg_temp_new();
-    zeroreg = tcg_constant_tl(0);
-    resultopt1 = tcg_temp_new();
-
-    tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
-    tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
-    tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
-                        ((target_ulong)1) << (TARGET_LONG_BITS - 1));
-    tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
-    tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
-    /* if div by zero, set source1 to -1, otherwise don't change */
-    tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
-            resultopt1);
-    /* if overflow or div by zero, set source2 to 1, else don't change */
-    tcg_gen_or_tl(cond1, cond1, cond2);
-    tcg_gen_movi_tl(resultopt1, (target_ulong)1);
-    tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
-            resultopt1);
-    tcg_gen_div_tl(ret, source1, source2);
-
-    tcg_temp_free(cond1);
-    tcg_temp_free(cond2);
-    tcg_temp_free(resultopt1);
+    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
+    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
+    tcg_gen_and_tl(temp1, temp1, temp2);
+    tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2);
+
+    /*
+     * If div by zero, set temp1 to -1 and temp2 to 1 to
+     * produce the required result of -1.
+     */
+    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
+    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2);
+
+    tcg_gen_div_tl(ret, temp1, temp2);
+
+    tcg_temp_free(temp1);
+    tcg_temp_free(temp2);
 }
 
 static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
 {
-    TCGv cond1, zeroreg, resultopt1;
-    cond1 = tcg_temp_new();
+    TCGv temp1, temp2, zero, one, max;
 
-    zeroreg = tcg_constant_tl(0);
-    resultopt1 = tcg_temp_new();
+    temp1 = tcg_temp_new();
+    temp2 = tcg_temp_new();
+    zero = tcg_constant_tl(0);
+    one = tcg_constant_tl(1);
+    max = tcg_constant_tl(~0);
 
-    tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
-    tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
-    tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
-            resultopt1);
-    tcg_gen_movi_tl(resultopt1, (target_ulong)1);
-    tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
-            resultopt1);
-    tcg_gen_divu_tl(ret, source1, source2);
+    /*
+     * If div by zero, set temp1 to max and temp2 to 1 to
+     * produce the required result of max.
+     */
+    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
+    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
+    tcg_gen_divu_tl(ret, temp1, temp2);
 
-    tcg_temp_free(cond1);
-    tcg_temp_free(resultopt1);
+    tcg_temp_free(temp1);
+    tcg_temp_free(temp2);
 }
 
 static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
 {
-    TCGv cond1, cond2, zeroreg, resultopt1;
-
-    cond1 = tcg_temp_new();
-    cond2 = tcg_temp_new();
-    zeroreg = tcg_constant_tl(0);
-    resultopt1 = tcg_temp_new();
-
-    tcg_gen_movi_tl(resultopt1, 1L);
-    tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
-    tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
-                        (target_ulong)1 << (TARGET_LONG_BITS - 1));
-    tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
-    tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
-    /* if overflow or div by zero, set source2 to 1, else don't change */
-    tcg_gen_or_tl(cond2, cond1, cond2);
-    tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
-            resultopt1);
-    tcg_gen_rem_tl(resultopt1, source1, source2);
-    /* if div by zero, just return the original dividend */
-    tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
-            source1);
-
-    tcg_temp_free(cond1);
-    tcg_temp_free(cond2);
-    tcg_temp_free(resultopt1);
+    TCGv temp1, temp2, zero, one, mone, min;
+
+    temp1 = tcg_temp_new();
+    temp2 = tcg_temp_new();
+    zero = tcg_constant_tl(0);
+    one = tcg_constant_tl(1);
+    mone = tcg_constant_tl(-1);
+    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
+
+    /*
+     * If overflow, set temp1 to 0, else source1.
+     * This avoids a possible host trap, and produces the required result of 0.
+     */
+    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
+    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
+    tcg_gen_and_tl(temp1, temp1, temp2);
+    tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1);
+
+    /*
+     * If div by zero, set temp2 to 1, else source2.
+     * This avoids a possible host trap, but produces an incorrect result.
+     */
+    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
+
+    tcg_gen_rem_tl(temp1, temp1, temp2);
+
+    /* If div by zero, the required result is the original dividend. */
+    tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1);
+
+    tcg_temp_free(temp1);
+    tcg_temp_free(temp2);
 }
 
 static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
 {
-    TCGv cond1, zeroreg, resultopt1;
-    cond1 = tcg_temp_new();
-    zeroreg = tcg_constant_tl(0);
-    resultopt1 = tcg_temp_new();
-
-    tcg_gen_movi_tl(resultopt1, (target_ulong)1);
-    tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
-    tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
-            resultopt1);
-    tcg_gen_remu_tl(resultopt1, source1, source2);
-    /* if div by zero, just return the original dividend */
-    tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
-            source1);
-
-    tcg_temp_free(cond1);
-    tcg_temp_free(resultopt1);
+    TCGv temp, zero, one;
+
+    temp = tcg_temp_new();
+    zero = tcg_constant_tl(0);
+    one = tcg_constant_tl(1);
+
+    /*
+     * If div by zero, set temp to 1, else source2.
+     * This avoids a possible host trap, but produces an incorrect result.
+     */
+    tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2);
+
+    tcg_gen_remu_tl(temp, source1, temp);
+
+    /* If div by zero, the required result is the original dividend. */
+    tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp);
+
+    tcg_temp_free(temp);
 }
 
 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

We will require the context to handle RV64 word operations.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-5-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 58 ++++++++++++-------------
 target/riscv/insn_trans/trans_rva.c.inc | 18 ++++----
 target/riscv/insn_trans/trans_rvb.c.inc |  4 +-
 target/riscv/insn_trans/trans_rvd.c.inc | 32 +++++++-------
 target/riscv/insn_trans/trans_rvf.c.inc | 32 +++++++-------
 target/riscv/insn_trans/trans_rvh.c.inc | 52 +++++++++++-----------
 target/riscv/insn_trans/trans_rvi.c.inc | 44 +++++++++----------
 target/riscv/insn_trans/trans_rvm.c.inc | 12 ++---
 target/riscv/insn_trans/trans_rvv.c.inc | 36 +++++++--------
 9 files changed, 144 insertions(+), 144 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 /* Wrapper for getting reg values - need to check of reg is zero since
  * cpu_gpr[0] is not actually allocated
  */
-static inline void gen_get_gpr(TCGv t, int reg_num)
+static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num)
 {
     if (reg_num == 0) {
         tcg_gen_movi_tl(t, 0);
@@ -XXX,XX +XXX,XX @@ static inline void gen_get_gpr(TCGv t, int reg_num)
  * since we usually avoid calling the OP_TYPE_gen function if we see a write to
  * $zero
  */
-static inline void gen_set_gpr(int reg_num_dst, TCGv t)
+static void gen_set_gpr(DisasContext *ctx, int reg_num_dst, TCGv t)
 {
     if (reg_num_dst != 0) {
         tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t);
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
     TCGv source1;
     source1 = tcg_temp_new();
 
-    gen_get_gpr(source1, a->rs1);
+    gen_get_gpr(ctx, source1, a->rs1);
 
     (*func)(source1, source1, a->imm);
 
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
     source1 = tcg_temp_new();
     source2 = tcg_temp_new();
 
-    gen_get_gpr(source1, a->rs1);
+    gen_get_gpr(ctx, source1, a->rs1);
     tcg_gen_movi_tl(source2, a->imm);
 
     (*func)(source1, source1, source2);
 
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     tcg_temp_free(source2);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
     source1 = tcg_temp_new();
     source2 = tcg_temp_new();
 
-    gen_get_gpr(source1, a->rs1);
-    gen_get_gpr(source2, a->rs2);
+    gen_get_gpr(ctx, source1, a->rs1);
+    gen_get_gpr(ctx, source2, a->rs2);
     tcg_gen_ext32s_tl(source1, source1);
     tcg_gen_ext32s_tl(source2, source2);
 
     (*func)(source1, source1, source2);
 
     tcg_gen_ext32s_tl(source1, source1);
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     tcg_temp_free(source2);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
     source1 = tcg_temp_new();
     source2 = tcg_temp_new();
 
-    gen_get_gpr(source1, a->rs1);
-    gen_get_gpr(source2, a->rs2);
+    gen_get_gpr(ctx, source1, a->rs1);
+    gen_get_gpr(ctx, source2, a->rs2);
     tcg_gen_ext32u_tl(source1, source1);
     tcg_gen_ext32u_tl(source2, source2);
 
     (*func)(source1, source1, source2);
 
     tcg_gen_ext32s_tl(source1, source1);
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     tcg_temp_free(source2);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
     TCGv source1 = tcg_temp_new();
     TCGv source2;
 
-    gen_get_gpr(source1, a->rs1);
+    gen_get_gpr(ctx, source1, a->rs1);
 
     if (a->shamt == (TARGET_LONG_BITS - 8)) {
         /* rev8, byte swaps */
@@ -XXX,XX +XXX,XX @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
         tcg_temp_free(source2);
     }
 
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool gen_arith(DisasContext *ctx, arg_r *a,
     source1 = tcg_temp_new();
     source2 = tcg_temp_new();
 
-    gen_get_gpr(source1, a->rs1);
-    gen_get_gpr(source2, a->rs2);
+    gen_get_gpr(ctx, source1, a->rs1);
+    gen_get_gpr(ctx, source2, a->rs2);
 
     (*func)(source1, source1, source2);
 
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     tcg_temp_free(source2);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
 
-    gen_get_gpr(source1, a->rs1);
-    gen_get_gpr(source2, a->rs2);
+    gen_get_gpr(ctx, source1, a->rs1);
+    gen_get_gpr(ctx, source2, a->rs2);
 
     tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
     (*func)(source1, source1, source2);
 
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     tcg_temp_free(source2);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool gen_shifti(DisasContext *ctx, arg_shift *a,
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
 
-    gen_get_gpr(source1, a->rs1);
+    gen_get_gpr(ctx, source1, a->rs1);
 
     tcg_gen_movi_tl(source2, a->shamt);
     (*func)(source1, source1, source2);
 
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     tcg_temp_free(source2);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool gen_shiftw(DisasContext *ctx, arg_r *a,
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
 
-    gen_get_gpr(source1, a->rs1);
-    gen_get_gpr(source2, a->rs2);
+    gen_get_gpr(ctx, source1, a->rs1);
+    gen_get_gpr(ctx, source2, a->rs2);
 
     tcg_gen_andi_tl(source2, source2, 31);
     (*func)(source1, source1, source2);
     tcg_gen_ext32s_tl(source1, source1);
 
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     tcg_temp_free(source2);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
 
-    gen_get_gpr(source1, a->rs1);
+    gen_get_gpr(ctx, source1, a->rs1);
     tcg_gen_movi_tl(source2, a->shamt);
 
     (*func)(source1, source1, source2);
     tcg_gen_ext32s_tl(source1, source1);
 
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     tcg_temp_free(source2);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a,
 {
     TCGv source = tcg_temp_new();
 
-    gen_get_gpr(source, a->rs1);
+    gen_get_gpr(ctx, source, a->rs1);
 
     (*func)(source, source);
 
-    gen_set_gpr(a->rd, source);
+    gen_set_gpr(ctx, a->rd, source);
     tcg_temp_free(source);
     return true;
 }
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -XXX,XX +XXX,XX @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
 {
     TCGv src1 = tcg_temp_new();
     /* Put addr in load_res, data in load_val.  */
-    gen_get_gpr(src1, a->rs1);
+    gen_get_gpr(ctx, src1, a->rs1);
     if (a->rl) {
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
     }
@@ -XXX,XX +XXX,XX @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
     }
     tcg_gen_mov_tl(load_res, src1);
-    gen_set_gpr(a->rd, load_val);
+    gen_set_gpr(ctx, a->rd, load_val);
 
     tcg_temp_free(src1);
     return true;
@@ -XXX,XX +XXX,XX @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
     TCGLabel *l1 = gen_new_label();
     TCGLabel *l2 = gen_new_label();
 
-    gen_get_gpr(src1, a->rs1);
+    gen_get_gpr(ctx, src1, a->rs1);
     tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
 
-    gen_get_gpr(src2, a->rs2);
+    gen_get_gpr(ctx, src2, a->rs2);
     /*
      * Note that the TCG atomic primitives are SC,
      * so we can ignore AQ/RL along this path.
@@ -XXX,XX +XXX,XX @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
     tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
                               ctx->mem_idx, mop);
     tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
-    gen_set_gpr(a->rd, dat);
+    gen_set_gpr(ctx, a->rd, dat);
     tcg_gen_br(l2);
 
     gen_set_label(l1);
@@ -XXX,XX +XXX,XX @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
      */
     tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
     tcg_gen_movi_tl(dat, 1);
-    gen_set_gpr(a->rd, dat);
+    gen_set_gpr(ctx, a->rd, dat);
 
     gen_set_label(l2);
     /*
@@ -XXX,XX +XXX,XX @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
     TCGv src1 = tcg_temp_new();
     TCGv src2 = tcg_temp_new();
 
-    gen_get_gpr(src1, a->rs1);
-    gen_get_gpr(src2, a->rs2);
+    gen_get_gpr(ctx, src1, a->rs1);
+    gen_get_gpr(ctx, src2, a->rs2);
 
     (*func)(src2, src1, src2, ctx->mem_idx, mop);
 
-    gen_set_gpr(a->rd, src2);
+    gen_set_gpr(ctx, a->rd, src2);
     tcg_temp_free(src1);
     tcg_temp_free(src2);
     return true;
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
     REQUIRE_EXT(ctx, RVB);
 
     TCGv source1 = tcg_temp_new();
-    gen_get_gpr(source1, a->rs1);
+    gen_get_gpr(ctx, source1, a->rs1);
 
     if (a->shamt < 32) {
         tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
@@ -XXX,XX +XXX,XX @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
         tcg_gen_shli_tl(source1, source1, a->shamt);
     }
 
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     return true;
 }
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
     TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
     tcg_gen_addi_tl(t0, t0, a->imm);
 
     tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
@@ -XXX,XX +XXX,XX @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
     TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
     tcg_gen_addi_tl(t0, t0, a->imm);
 
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
@@ -XXX,XX +XXX,XX @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
 
     TCGv t0 = tcg_temp_new();
     gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
 
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
 
     TCGv t0 = tcg_temp_new();
     gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
 
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
 
     TCGv t0 = tcg_temp_new();
     gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
 
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
 
     TCGv t0 = tcg_temp_new();
     gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
     TCGv t0 = tcg_temp_new();
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
 
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
     TCGv t0 = tcg_temp_new();
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
 
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
     REQUIRE_EXT(ctx, RVD);
 
     TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
     REQUIRE_EXT(ctx, RVD);
 
     TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
     TCGv t0 = tcg_temp_new();
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
     TCGv t0 = tcg_temp_new();
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
     REQUIRE_EXT(ctx, RVD);
 
 #ifdef TARGET_RISCV64
-    gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
+    gen_set_gpr(ctx, a->rd, cpu_fpr[a->rs1]);
     return true;
 #else
     qemu_build_not_reached();
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
     REQUIRE_EXT(ctx, RVD);
 
     TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
     REQUIRE_EXT(ctx, RVD);
 
     TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
 
 #ifdef TARGET_RISCV64
     TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
     tcg_temp_free(t0);
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
     TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
     tcg_gen_addi_tl(t0, t0, a->imm);
 
     tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
@@ -XXX,XX +XXX,XX @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
     TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     tcg_gen_addi_tl(t0, t0, a->imm);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
     TCGv t0 = tcg_temp_new();
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
 
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
     TCGv t0 = tcg_temp_new();
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
 
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
     tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
 #endif
 
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
 
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
     REQUIRE_EXT(ctx, RVF);
     TCGv t0 = tcg_temp_new();
     gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
     REQUIRE_EXT(ctx, RVF);
     TCGv t0 = tcg_temp_new();
     gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
     REQUIRE_EXT(ctx, RVF);
     TCGv t0 = tcg_temp_new();
     gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
 
     gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
 
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
 
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
     REQUIRE_EXT(ctx, RVF);
 
     TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
     REQUIRE_EXT(ctx, RVF);
 
     TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
     REQUIRE_EXT(ctx, RVF);
 
     TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
     gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
     TCGv t0 = tcg_temp_new();
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
     TCGv t0 = tcg_temp_new();
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(a->rd, t0);
+    gen_set_gpr(ctx, a->rd, t0);
     tcg_temp_free(t0);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
     REQUIRE_EXT(ctx, RVF);
 
     TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
     REQUIRE_EXT(ctx, RVF);
 
     TCGv t0 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     gen_set_rm(ctx, a->rm);
     gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
 
     check_access(ctx);
 
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_SB);
-    gen_set_gpr(a->rd, t1);
+    gen_set_gpr(ctx, a->rd, t1);
 
     tcg_temp_free(t0);
     tcg_temp_free(t1);
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
 
     check_access(ctx);
 
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESW);
-    gen_set_gpr(a->rd, t1);
+    gen_set_gpr(ctx, a->rd, t1);
 
     tcg_temp_free(t0);
     tcg_temp_free(t1);
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a)
 
     check_access(ctx);
 
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESL);
-    gen_set_gpr(a->rd, t1);
+    gen_set_gpr(ctx, a->rd, t1);
 
     tcg_temp_free(t0);
     tcg_temp_free(t1);
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a)
 
     check_access(ctx);
 
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_UB);
-    gen_set_gpr(a->rd, t1);
+    gen_set_gpr(ctx, a->rd, t1);
 
     tcg_temp_free(t0);
     tcg_temp_free(t1);
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a)
 
     check_access(ctx);
 
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEUW);
-    gen_set_gpr(a->rd, t1);
+    gen_set_gpr(ctx, a->rd, t1);
 
     tcg_temp_free(t0);
     tcg_temp_free(t1);
@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a)
 
     check_access(ctx);
 
-    gen_get_gpr(t0, a->rs1);
-    gen_get_gpr(dat, a->rs2);
+    gen_get_gpr(ctx, t0, a->rs1);
+    gen_get_gpr(ctx, dat, a->rs2);
 
     tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_SB);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a)
 
     check_access(ctx);
 
-    gen_get_gpr(t0, a->rs1);
-    gen_get_gpr(dat, a->rs2);
+    gen_get_gpr(ctx, t0, a->rs1);
+    gen_get_gpr(ctx, dat, a->rs2);
 
     tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESW);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
 
     check_access(ctx);
 
-    gen_get_gpr(t0, a->rs1);
-    gen_get_gpr(dat, a->rs2);
+    gen_get_gpr(ctx, t0, a->rs1);
+    gen_get_gpr(ctx, dat, a->rs2);
 
     tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESL);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
 
     check_access(ctx);
 
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEUL);
-    gen_set_gpr(a->rd, t1);
+    gen_set_gpr(ctx, a->rd, t1);
 
     tcg_temp_free(t0);
     tcg_temp_free(t1);
@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
 
     check_access(ctx);
 
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEQ);
-    gen_set_gpr(a->rd, t1);
+    gen_set_gpr(ctx, a->rd, t1);
 
     tcg_temp_free(t0);
     tcg_temp_free(t1);
@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
 
     check_access(ctx);
 
-    gen_get_gpr(t0, a->rs1);
-    gen_get_gpr(dat, a->rs2);
+    gen_get_gpr(ctx, t0, a->rs1);
+    gen_get_gpr(ctx, dat, a->rs2);
 
     tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEQ);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
 
     check_access(ctx);
 
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     gen_helper_hyp_hlvx_hu(t1, cpu_env, t0);
-    gen_set_gpr(a->rd, t1);
+    gen_set_gpr(ctx, a->rd, t1);
 
     tcg_temp_free(t0);
     tcg_temp_free(t1);
@@ -XXX,XX +XXX,XX @@ static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a)
 
     check_access(ctx);
 
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
 
     gen_helper_hyp_hlvx_wu(t1, cpu_env, t0);
-    gen_set_gpr(a->rd, t1);
+    gen_set_gpr(ctx, a->rd, t1);
 
     tcg_temp_free(t0);
     tcg_temp_free(t1);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
     TCGv t0 = tcg_temp_new();
 
 
-    gen_get_gpr(cpu_pc, a->rs1);
+    gen_get_gpr(ctx, cpu_pc, a->rs1);
     tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
     tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
 
@@ -XXX,XX +XXX,XX @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
     TCGv source1, source2;
     source1 = tcg_temp_new();
     source2 = tcg_temp_new();
-    gen_get_gpr(source1, a->rs1);
-    gen_get_gpr(source2, a->rs2);
+    gen_get_gpr(ctx, source1, a->rs1);
+    gen_get_gpr(ctx, source2, a->rs2);
 
     tcg_gen_brcond_tl(cond, source1, source2, l);
     gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
@@ -XXX,XX +XXX,XX @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
 {
     TCGv t0 = tcg_temp_new();
     TCGv t1 = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
     tcg_gen_addi_tl(t0, t0, a->imm);
 
     tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
-    gen_set_gpr(a->rd, t1);
+    gen_set_gpr(ctx, a->rd, t1);
     tcg_temp_free(t0);
     tcg_temp_free(t1);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
 {
     TCGv t0 = tcg_temp_new();
     TCGv dat = tcg_temp_new();
-    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(ctx, t0, a->rs1);
     tcg_gen_addi_tl(t0, t0, a->imm);
-    gen_get_gpr(dat, a->rs2);
+    gen_get_gpr(ctx, dat, a->rs2);
 
     tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
     tcg_temp_free(t0);
@@ -XXX,XX +XXX,XX @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
 {
     REQUIRE_64BIT(ctx);
     TCGv t = tcg_temp_new();
-    gen_get_gpr(t, a->rs1);
+    gen_get_gpr(ctx, t, a->rs1);
     tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
     /* sign-extend for W instructions */
     tcg_gen_ext32s_tl(t, t);
-    gen_set_gpr(a->rd, t);
+    gen_set_gpr(ctx, a->rd, t);
     tcg_temp_free(t);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 {
     REQUIRE_64BIT(ctx);
     TCGv t = tcg_temp_new();
-    gen_get_gpr(t, a->rs1);
+    gen_get_gpr(ctx, t, a->rs1);
     tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
-    gen_set_gpr(a->rd, t);
+    gen_set_gpr(ctx, a->rd, t);
     tcg_temp_free(t);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
 
-    gen_get_gpr(source1, a->rs1);
-    gen_get_gpr(source2, a->rs2);
+    gen_get_gpr(ctx, source1, a->rs1);
+    gen_get_gpr(ctx, source2, a->rs2);
 
     tcg_gen_andi_tl(source2, source2, 0x1F);
     tcg_gen_shl_tl(source1, source1, source2);
 
     tcg_gen_ext32s_tl(source1, source1);
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     tcg_temp_free(source2);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
 
-    gen_get_gpr(source1, a->rs1);
-    gen_get_gpr(source2, a->rs2);
+    gen_get_gpr(ctx, source1, a->rs1);
+    gen_get_gpr(ctx, source2, a->rs2);
 
     /* clear upper 32 */
     tcg_gen_ext32u_tl(source1, source1);
@@ -XXX,XX +XXX,XX @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
     tcg_gen_shr_tl(source1, source1, source2);
 
     tcg_gen_ext32s_tl(source1, source1);
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     tcg_temp_free(source2);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
 
-    gen_get_gpr(source1, a->rs1);
-    gen_get_gpr(source2, a->rs2);
+    gen_get_gpr(ctx, source1, a->rs1);
+    gen_get_gpr(ctx, source2, a->rs2);
 
     /*
      * first, trick to get it to act like working on 32 bits (get rid of
@@ -XXX,XX +XXX,XX @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
     tcg_gen_andi_tl(source2, source2, 0x1F);
     tcg_gen_sar_tl(source1, source1, source2);
 
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     tcg_temp_free(source2);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
     csr_store = tcg_temp_new(); \
     dest = tcg_temp_new(); \
     rs1_pass = tcg_temp_new(); \
-    gen_get_gpr(source1, a->rs1); \
+    gen_get_gpr(ctx, source1, a->rs1); \
     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
     tcg_gen_movi_tl(rs1_pass, a->rs1); \
     tcg_gen_movi_tl(csr_store, a->csr); \
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
 } while (0)
 
 #define RISCV_OP_CSR_POST do {\
-    gen_set_gpr(a->rd, dest); \
+    gen_set_gpr(ctx, a->rd, dest); \
     tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
     exit_tb(ctx); \
     ctx->base.is_jmp = DISAS_NORETURN; \
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
     REQUIRE_EXT(ctx, RVM);
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
-    gen_get_gpr(source1, a->rs1);
-    gen_get_gpr(source2, a->rs2);
+    gen_get_gpr(ctx, source1, a->rs1);
+    gen_get_gpr(ctx, source2, a->rs2);
 
     tcg_gen_muls2_tl(source2, source1, source1, source2);
 
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     tcg_temp_free(source2);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
     REQUIRE_EXT(ctx, RVM);
     TCGv source1 = tcg_temp_new();
     TCGv source2 = tcg_temp_new();
-    gen_get_gpr(source1, a->rs1);
-    gen_get_gpr(source2, a->rs2);
+    gen_get_gpr(ctx, source1, a->rs1);
+    gen_get_gpr(ctx, source2, a->rs2);
 
     tcg_gen_mulu2_tl(source2, source1, source1, source2);
 
-    gen_set_gpr(a->rd, source1);
+    gen_set_gpr(ctx, a->rd, source1);
     tcg_temp_free(source1);
     tcg_temp_free(source2);
     return true;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
         s1 = tcg_constant_tl(RV_VLEN_MAX);
     } else {
         s1 = tcg_temp_new();
-        gen_get_gpr(s1, a->rs1);
+        gen_get_gpr(ctx, s1, a->rs1);
     }
-    gen_get_gpr(s2, a->rs2);
+    gen_get_gpr(ctx, s2, a->rs2);
     gen_helper_vsetvl(dst, cpu_env, s1, s2);
-    gen_set_gpr(a->rd, dst);
+    gen_set_gpr(ctx, a->rd, dst);
     tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
     lookup_and_goto_ptr(ctx);
     ctx->base.is_jmp = DISAS_NORETURN;
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
         s1 = tcg_constant_tl(RV_VLEN_MAX);
     } else {
         s1 = tcg_temp_new();
-        gen_get_gpr(s1, a->rs1);
+        gen_get_gpr(ctx, s1, a->rs1);
     }
     gen_helper_vsetvl(dst, cpu_env, s1, s2);
-    gen_set_gpr(a->rd, dst);
+    gen_set_gpr(ctx, a->rd, dst);
     gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
     ctx->base.is_jmp = DISAS_NORETURN;
 
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      */
     desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
-    gen_get_gpr(base, rs1);
+    gen_get_gpr(s, base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
 
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
     stride = tcg_temp_new();
     desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
-    gen_get_gpr(base, rs1);
-    gen_get_gpr(stride, rs2);
+    gen_get_gpr(s, base, rs1);
+    gen_get_gpr(s, stride, rs2);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
 
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     base = tcg_temp_new();
     desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
-    gen_get_gpr(base, rs1);
+    gen_get_gpr(s, base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
     tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
     base = tcg_temp_new();
     desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
-    gen_get_gpr(base, rs1);
+    gen_get_gpr(s, base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
 
@@ -XXX,XX +XXX,XX @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     base = tcg_temp_new();
     desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
-    gen_get_gpr(base, rs1);
+    gen_get_gpr(s, base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
     tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
     mask = tcg_temp_new_ptr();
     src2 = tcg_temp_new_ptr();
     src1 = tcg_temp_new();
-    gen_get_gpr(src1, rs1);
+    gen_get_gpr(s, src1, rs1);
 
     data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
     data = FIELD_DP32(data, VDATA, VM, vm);
@@ -XXX,XX +XXX,XX @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
         TCGv_i64 src1 = tcg_temp_new_i64();
         TCGv tmp = tcg_temp_new();
 
-        gen_get_gpr(tmp, a->rs1);
+        gen_get_gpr(s, tmp, a->rs1);
         tcg_gen_ext_tl_i64(src1, tmp);
         gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
                 src1, MAXSZ(s), MAXSZ(s));
@@ -XXX,XX +XXX,XX @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
         TCGv_i32 src1 = tcg_temp_new_i32();
         TCGv tmp = tcg_temp_new();
 
-        gen_get_gpr(tmp, a->rs1);
+        gen_get_gpr(s, tmp, a->rs1);
         tcg_gen_trunc_tl_i32(src1, tmp);
         tcg_gen_extract_i32(src1, src1, 0, s->sew + 3);
         gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 
         s1 = tcg_temp_new();
-        gen_get_gpr(s1, a->rs1);
+        gen_get_gpr(s, s1, a->rs1);
 
         if (s->vl_eq_vlmax) {
             tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
@@ -XXX,XX +XXX,XX @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
         tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
 
         gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc);
-        gen_set_gpr(a->rd, dst);
+        gen_set_gpr(s, a->rd, dst);
 
         tcg_temp_free_ptr(mask);
         tcg_temp_free_ptr(src2);
@@ -XXX,XX +XXX,XX @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
         tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
 
         gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
-        gen_set_gpr(a->rd, dst);
+        gen_set_gpr(s, a->rd, dst);
 
         tcg_temp_free_ptr(mask);
         tcg_temp_free_ptr(src2);
@@ -XXX,XX +XXX,XX @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a)
         vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
     }
     tcg_gen_trunc_i64_tl(dest, tmp);
-    gen_set_gpr(a->rd, dest);
+    gen_set_gpr(s, a->rd, dest);
 
     tcg_temp_free(dest);
     tcg_temp_free_i64(tmp);
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Introduce get_gpr, dest_gpr, temp_new -- new helpers that do not force
tcg globals into temps, returning a constant 0 for $zero as source and
a new temp for $zero as destination.

Introduce ctx->w for simplifying word operations, such as addw.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-6-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 97 +++++++++++++++++++++++++++++++++-------
 1 file changed, 81 insertions(+), 16 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static TCGv load_val;
 
 #include "exec/gen-icount.h"
 
+/*
+ * If an operation is being performed on less than TARGET_LONG_BITS,
+ * it may require the inputs to be sign- or zero-extended; which will
+ * depend on the exact operation being performed.
+ */
+typedef enum {
+    EXT_NONE,
+    EXT_SIGN,
+    EXT_ZERO,
+} DisasExtend;
+
 typedef struct DisasContext {
     DisasContextBase base;
     /* pc_succ_insn points to the instruction following base.pc_next */
     target_ulong pc_succ_insn;
     target_ulong priv_ver;
-    bool virt_enabled;
+    target_ulong misa;
     uint32_t opcode;
     uint32_t mstatus_fs;
-    target_ulong misa;
     uint32_t mem_idx;
     /* Remember the rounding mode encoded in the previous fp instruction,
        which we have already installed into env->fp_status.  Or -1 for
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
        to any system register, which includes CSR_FRM, so we do not have
        to reset this known value.  */
     int frm;
+    bool w;
+    bool virt_enabled;
     bool ext_ifencei;
     bool hlsx;
     /* vector extension */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     uint16_t vlen;
     uint16_t mlen;
     bool vl_eq_vlmax;
+    uint8_t ntemp;
     CPUState *cs;
+    TCGv zero;
+    /* Space for 3 operands plus 1 extra for address computation. */
+    TCGv temp[4];
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
     }
 }
 
-/* Wrapper for getting reg values - need to check of reg is zero since
- * cpu_gpr[0] is not actually allocated
+/*
+ * Wrappers for getting reg values.
+ *
+ * The $zero register does not have cpu_gpr[0] allocated -- we supply the
+ * constant zero as a source, and an uninitialized sink as destination.
+ *
+ * Further, we may provide an extension for word operations.
  */
-static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num)
+static TCGv temp_new(DisasContext *ctx)
+{
+    assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
+    return ctx->temp[ctx->ntemp++] = tcg_temp_new();
+}
+
+static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
 {
+    TCGv t;
+
     if (reg_num == 0) {
-        tcg_gen_movi_tl(t, 0);
-    } else {
-        tcg_gen_mov_tl(t, cpu_gpr[reg_num]);
+        return ctx->zero;
     }
+
+    switch (ctx->w ? ext : EXT_NONE) {
+    case EXT_NONE:
+        return cpu_gpr[reg_num];
+    case EXT_SIGN:
+        t = temp_new(ctx);
+        tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
+        return t;
+    case EXT_ZERO:
+        t = temp_new(ctx);
+        tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
+        return t;
+    }
+    g_assert_not_reached();
 }
 
-/* Wrapper for setting reg values - need to check of reg is zero since
- * cpu_gpr[0] is not actually allocated. this is more for safety purposes,
- * since we usually avoid calling the OP_TYPE_gen function if we see a write to
- * $zero
- */
-static void gen_set_gpr(DisasContext *ctx, int reg_num_dst, TCGv t)
+static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num)
+{
+    tcg_gen_mov_tl(t, get_gpr(ctx, reg_num, EXT_NONE));
+}
+
+static TCGv __attribute__((unused)) dest_gpr(DisasContext *ctx, int reg_num)
+{
+    if (reg_num == 0 || ctx->w) {
+        return temp_new(ctx);
+    }
+    return cpu_gpr[reg_num];
+}
+
+static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
 {
-    if (reg_num_dst != 0) {
-        tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t);
+    if (reg_num != 0) {
+        if (ctx->w) {
+            tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
+        } else {
+            tcg_gen_mov_tl(cpu_gpr[reg_num], t);
+        }
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->mlen = 1 << (ctx->sew  + 3 - ctx->lmul);
     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
     ctx->cs = cs;
+    ctx->w = false;
+    ctx->ntemp = 0;
+    memset(ctx->temp, 0, sizeof(ctx->temp));
+
+    ctx->zero = tcg_constant_tl(0);
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 
     decode_opc(env, ctx, opcode16);
     ctx->base.pc_next = ctx->pc_succ_insn;
+    ctx->w = false;
+
+    for (int i = ctx->ntemp - 1; i >= 0; --i) {
+        tcg_temp_free(ctx->temp[i]);
+        ctx->temp[i] = NULL;
+    }
+    ctx->ntemp = 0;
 
     if (ctx->base.is_jmp == DISAS_NEXT) {
         target_ulong page_start;
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Most arithmetic does not require extending the inputs.
Exceptions include division, comparison and minmax.

Begin using ctx->w, which allows elimination of gen_addw,
gen_subw, gen_mulw.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-7-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 69 +++++++------------------
 target/riscv/insn_trans/trans_rvb.c.inc | 30 +++++------
 target/riscv/insn_trans/trans_rvi.c.inc | 39 ++++++++------
 target/riscv/insn_trans/trans_rvm.c.inc | 16 +++---
 4 files changed, 64 insertions(+), 90 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num)
     tcg_gen_mov_tl(t, get_gpr(ctx, reg_num, EXT_NONE));
 }
 
-static TCGv __attribute__((unused)) dest_gpr(DisasContext *ctx, int reg_num)
+static TCGv dest_gpr(DisasContext *ctx, int reg_num)
 {
     if (reg_num == 0 || ctx->w) {
         return temp_new(ctx);
@@ -XXX,XX +XXX,XX @@ static int ex_rvc_shifti(DisasContext *ctx, int imm)
 /* Include the auto-generated decoder for 32 bit insn */
 #include "decode-insn32.c.inc"
 
-static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
+static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
                              void (*func)(TCGv, TCGv, target_long))
 {
-    TCGv source1;
-    source1 = tcg_temp_new();
-
-    gen_get_gpr(ctx, source1, a->rs1);
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
 
-    (*func)(source1, source1, a->imm);
+    func(dest, src1, a->imm);
 
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
-static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
+static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
                              void (*func)(TCGv, TCGv, TCGv))
 {
-    TCGv source1, source2;
-    source1 = tcg_temp_new();
-    source2 = tcg_temp_new();
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
+    TCGv src2 = tcg_constant_tl(a->imm);
 
-    gen_get_gpr(ctx, source1, a->rs1);
-    tcg_gen_movi_tl(source2, a->imm);
+    func(dest, src1, src2);
 
-    (*func)(source1, source1, source2);
-
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
-static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    tcg_gen_add_tl(ret, arg1, arg2);
-    tcg_gen_ext32s_tl(ret, ret);
-}
-
-static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    tcg_gen_sub_tl(ret, arg1, arg2);
-    tcg_gen_ext32s_tl(ret, ret);
-}
-
-static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    tcg_gen_mul_tl(ret, arg1, arg2);
-    tcg_gen_ext32s_tl(ret, ret);
-}
-
 static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
                             void(*func)(TCGv, TCGv, TCGv))
 {
@@ -XXX,XX +XXX,XX @@ static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_gen_add_tl(ret, arg1, arg2);
 }
 
-static bool gen_arith(DisasContext *ctx, arg_r *a,
-                      void(*func)(TCGv, TCGv, TCGv))
+static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
+                      void (*func)(TCGv, TCGv, TCGv))
 {
-    TCGv source1, source2;
-    source1 = tcg_temp_new();
-    source2 = tcg_temp_new();
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
+    TCGv src2 = get_gpr(ctx, a->rs2, ext);
 
-    gen_get_gpr(ctx, source1, a->rs1);
-    gen_get_gpr(ctx, source2, a->rs2);
+    func(dest, src1, src2);
 
-    (*func)(source1, source1, source2);
-
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
 static bool trans_andn(DisasContext *ctx, arg_andn *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_arith(ctx, a, tcg_gen_andc_tl);
+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
 }
 
 static bool trans_orn(DisasContext *ctx, arg_orn *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_arith(ctx, a, tcg_gen_orc_tl);
+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
 }
 
 static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_arith(ctx, a, tcg_gen_eqv_tl);
+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
 }
 
 static bool trans_pack(DisasContext *ctx, arg_pack *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_arith(ctx, a, gen_pack);
+    return gen_arith(ctx, a, EXT_NONE, gen_pack);
 }
 
 static bool trans_packu(DisasContext *ctx, arg_packu *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_arith(ctx, a, gen_packu);
+    return gen_arith(ctx, a, EXT_NONE, gen_packu);
 }
 
 static bool trans_packh(DisasContext *ctx, arg_packh *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_arith(ctx, a, gen_packh);
+    return gen_arith(ctx, a, EXT_NONE, gen_packh);
 }
 
 static bool trans_min(DisasContext *ctx, arg_min *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_arith(ctx, a, tcg_gen_smin_tl);
+    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
 }
 
 static bool trans_max(DisasContext *ctx, arg_max *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_arith(ctx, a, tcg_gen_smax_tl);
+    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
 }
 
 static bool trans_minu(DisasContext *ctx, arg_minu *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_arith(ctx, a, tcg_gen_umin_tl);
+    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
 }
 
 static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_arith(ctx, a, tcg_gen_umax_tl);
+    return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
 }
 
 static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
 static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
 {                                                                          \
     REQUIRE_EXT(ctx, RVB);                                                 \
-    return gen_arith(ctx, a, gen_sh##SHAMT##add);                          \
+    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add);                \
 }
 
 GEN_TRANS_SHADD(1)
@@ -XXX,XX +XXX,XX @@ static bool trans_packw(DisasContext *ctx, arg_packw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_arith(ctx, a, gen_packw);
+    return gen_arith(ctx, a, EXT_NONE, gen_packw);
 }
 
 static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_arith(ctx, a, gen_packuw);
+    return gen_arith(ctx, a, EXT_NONE, gen_packuw);
 }
 
 static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
 {                                                             \
     REQUIRE_64BIT(ctx);                                       \
     REQUIRE_EXT(ctx, RVB);                                    \
-    return gen_arith(ctx, a, gen_sh##SHAMT##add_uw);          \
+    return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw);  \
 }
 
 GEN_TRANS_SHADD_UW(1)
@@ -XXX,XX +XXX,XX @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_arith(ctx, a, gen_add_uw);
+    return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
 }
 
 static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
 
 static bool trans_addi(DisasContext *ctx, arg_addi *a)
 {
-    return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
+    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
 }
 
 static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
@@ -XXX,XX +XXX,XX @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
     tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
 }
 
-
 static bool trans_slti(DisasContext *ctx, arg_slti *a)
 {
-    return gen_arith_imm_tl(ctx, a, &gen_slt);
+    return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt);
 }
 
 static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
 {
-    return gen_arith_imm_tl(ctx, a, &gen_sltu);
+    return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu);
 }
 
 static bool trans_xori(DisasContext *ctx, arg_xori *a)
 {
-    return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
+    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl);
 }
+
 static bool trans_ori(DisasContext *ctx, arg_ori *a)
 {
-    return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
+    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl);
 }
+
 static bool trans_andi(DisasContext *ctx, arg_andi *a)
 {
-    return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
+    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
 }
+
 static bool trans_slli(DisasContext *ctx, arg_slli *a)
 {
     return gen_shifti(ctx, a, tcg_gen_shl_tl);
@@ -XXX,XX +XXX,XX @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
 
 static bool trans_add(DisasContext *ctx, arg_add *a)
 {
-    return gen_arith(ctx, a, &tcg_gen_add_tl);
+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
 }
 
 static bool trans_sub(DisasContext *ctx, arg_sub *a)
 {
-    return gen_arith(ctx, a, &tcg_gen_sub_tl);
+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
 }
 
 static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
 
 static bool trans_slt(DisasContext *ctx, arg_slt *a)
 {
-    return gen_arith(ctx, a, &gen_slt);
+    return gen_arith(ctx, a, EXT_SIGN, gen_slt);
 }
 
 static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
 {
-    return gen_arith(ctx, a, &gen_sltu);
+    return gen_arith(ctx, a, EXT_SIGN, gen_sltu);
 }
 
 static bool trans_xor(DisasContext *ctx, arg_xor *a)
 {
-    return gen_arith(ctx, a, &tcg_gen_xor_tl);
+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_xor_tl);
 }
 
 static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
 
 static bool trans_or(DisasContext *ctx, arg_or *a)
 {
-    return gen_arith(ctx, a, &tcg_gen_or_tl);
+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_or_tl);
 }
 
 static bool trans_and(DisasContext *ctx, arg_and *a)
 {
-    return gen_arith(ctx, a, &tcg_gen_and_tl);
+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_and_tl);
 }
 
 static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
 {
     REQUIRE_64BIT(ctx);
-    return gen_arith_imm_tl(ctx, a, &gen_addw);
+    ctx->w = true;
+    return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
 }
 
 static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 static bool trans_addw(DisasContext *ctx, arg_addw *a)
 {
     REQUIRE_64BIT(ctx);
-    return gen_arith(ctx, a, &gen_addw);
+    ctx->w = true;
+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
 }
 
 static bool trans_subw(DisasContext *ctx, arg_subw *a)
 {
     REQUIRE_64BIT(ctx);
-    return gen_arith(ctx, a, &gen_subw);
+    ctx->w = true;
+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
 }
 
 static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@
 static bool trans_mul(DisasContext *ctx, arg_mul *a)
 {
     REQUIRE_EXT(ctx, RVM);
-    return gen_arith(ctx, a, &tcg_gen_mul_tl);
+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
 }
 
 static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
 static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
 {
     REQUIRE_EXT(ctx, RVM);
-    return gen_arith(ctx, a, &gen_mulhsu);
+    return gen_arith(ctx, a, EXT_NONE, gen_mulhsu);
 }
 
 static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
 static bool trans_div(DisasContext *ctx, arg_div *a)
 {
     REQUIRE_EXT(ctx, RVM);
-    return gen_arith(ctx, a, &gen_div);
+    return gen_arith(ctx, a, EXT_SIGN, gen_div);
 }
 
 static bool trans_divu(DisasContext *ctx, arg_divu *a)
 {
     REQUIRE_EXT(ctx, RVM);
-    return gen_arith(ctx, a, &gen_divu);
+    return gen_arith(ctx, a, EXT_ZERO, gen_divu);
 }
 
 static bool trans_rem(DisasContext *ctx, arg_rem *a)
 {
     REQUIRE_EXT(ctx, RVM);
-    return gen_arith(ctx, a, &gen_rem);
+    return gen_arith(ctx, a, EXT_SIGN, gen_rem);
 }
 
 static bool trans_remu(DisasContext *ctx, arg_remu *a)
 {
     REQUIRE_EXT(ctx, RVM);
-    return gen_arith(ctx, a, &gen_remu);
+    return gen_arith(ctx, a, EXT_ZERO, gen_remu);
 }
 
 static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-
-    return gen_arith(ctx, a, &gen_mulw);
+    ctx->w = true;
+    return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
 }
 
 static bool trans_divw(DisasContext *ctx, arg_divw *a)
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Use ctx->w and the enhanced gen_arith function.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-8-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 42 -------------------------
 target/riscv/insn_trans/trans_rvm.c.inc | 16 +++++-----
 2 files changed, 8 insertions(+), 50 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
     return true;
 }
 
-static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
-                            void(*func)(TCGv, TCGv, TCGv))
-{
-    TCGv source1, source2;
-    source1 = tcg_temp_new();
-    source2 = tcg_temp_new();
-
-    gen_get_gpr(ctx, source1, a->rs1);
-    gen_get_gpr(ctx, source2, a->rs2);
-    tcg_gen_ext32s_tl(source1, source1);
-    tcg_gen_ext32s_tl(source2, source2);
-
-    (*func)(source1, source1, source2);
-
-    tcg_gen_ext32s_tl(source1, source1);
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
-    return true;
-}
-
-static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
-                            void(*func)(TCGv, TCGv, TCGv))
-{
-    TCGv source1, source2;
-    source1 = tcg_temp_new();
-    source2 = tcg_temp_new();
-
-    gen_get_gpr(ctx, source1, a->rs1);
-    gen_get_gpr(ctx, source2, a->rs2);
-    tcg_gen_ext32u_tl(source1, source1);
-    tcg_gen_ext32u_tl(source2, source2);
-
-    (*func)(source1, source1, source2);
-
-    tcg_gen_ext32s_tl(source1, source1);
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
-    return true;
-}
-
 static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
 {
     tcg_gen_deposit_tl(ret, arg1, arg2,
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-
-    return gen_arith_div_w(ctx, a, &gen_div);
+    ctx->w = true;
+    return gen_arith(ctx, a, EXT_SIGN, gen_div);
 }
 
 static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-
-    return gen_arith_div_uw(ctx, a, &gen_divu);
+    ctx->w = true;
+    return gen_arith(ctx, a, EXT_ZERO, gen_divu);
 }
 
 static bool trans_remw(DisasContext *ctx, arg_remw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-
-    return gen_arith_div_w(ctx, a, &gen_rem);
+    ctx->w = true;
+    return gen_arith(ctx, a, EXT_SIGN, gen_rem);
 }
 
 static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-
-    return gen_arith_div_uw(ctx, a, &gen_remu);
+    ctx->w = true;
+    return gen_arith(ctx, a, EXT_ZERO, gen_remu);
 }
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Split out gen_mulh and gen_mulhu and use the common helper.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-9-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvm.c.inc | 40 +++++++++++--------------
 1 file changed, 18 insertions(+), 22 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_mul(DisasContext *ctx, arg_mul *a)
     return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
 }
 
-static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
+static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
 {
-    REQUIRE_EXT(ctx, RVM);
-    TCGv source1 = tcg_temp_new();
-    TCGv source2 = tcg_temp_new();
-    gen_get_gpr(ctx, source1, a->rs1);
-    gen_get_gpr(ctx, source2, a->rs2);
+    TCGv discard = tcg_temp_new();
 
-    tcg_gen_muls2_tl(source2, source1, source1, source2);
+    tcg_gen_muls2_tl(discard, ret, s1, s2);
+    tcg_temp_free(discard);
+}
 
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
-    return true;
+static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
+{
+    REQUIRE_EXT(ctx, RVM);
+    return gen_arith(ctx, a, EXT_NONE, gen_mulh);
 }
 
 static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
     return gen_arith(ctx, a, EXT_NONE, gen_mulhsu);
 }
 
-static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
+static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
 {
-    REQUIRE_EXT(ctx, RVM);
-    TCGv source1 = tcg_temp_new();
-    TCGv source2 = tcg_temp_new();
-    gen_get_gpr(ctx, source1, a->rs1);
-    gen_get_gpr(ctx, source2, a->rs2);
+    TCGv discard = tcg_temp_new();
 
-    tcg_gen_mulu2_tl(source2, source1, source1, source2);
+    tcg_gen_mulu2_tl(discard, ret, s1, s2);
+    tcg_temp_free(discard);
+}
 
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
-    return true;
+static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
+{
+    REQUIRE_EXT(ctx, RVM);
+    return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
 }
 
 static bool trans_div(DisasContext *ctx, arg_div *a)
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Move these helpers near their use by the trans_*
functions within insn_trans/trans_rvm.c.inc.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-10-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 127 ------------------------
 target/riscv/insn_trans/trans_rvm.c.inc | 127 ++++++++++++++++++++++++
 2 files changed, 127 insertions(+), 127 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
     }
 }
 
-static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    TCGv rl = tcg_temp_new();
-    TCGv rh = tcg_temp_new();
-
-    tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
-    /* fix up for one negative */
-    tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
-    tcg_gen_and_tl(rl, rl, arg2);
-    tcg_gen_sub_tl(ret, rh, rl);
-
-    tcg_temp_free(rl);
-    tcg_temp_free(rh);
-}
-
-static void gen_div(TCGv ret, TCGv source1, TCGv source2)
-{
-    TCGv temp1, temp2, zero, one, mone, min;
-
-    temp1 = tcg_temp_new();
-    temp2 = tcg_temp_new();
-    zero = tcg_constant_tl(0);
-    one = tcg_constant_tl(1);
-    mone = tcg_constant_tl(-1);
-    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
-
-    /*
-     * If overflow, set temp2 to 1, else source2.
-     * This produces the required result of min.
-     */
-    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
-    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
-    tcg_gen_and_tl(temp1, temp1, temp2);
-    tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2);
-
-    /*
-     * If div by zero, set temp1 to -1 and temp2 to 1 to
-     * produce the required result of -1.
-     */
-    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
-    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2);
-
-    tcg_gen_div_tl(ret, temp1, temp2);
-
-    tcg_temp_free(temp1);
-    tcg_temp_free(temp2);
-}
-
-static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
-{
-    TCGv temp1, temp2, zero, one, max;
-
-    temp1 = tcg_temp_new();
-    temp2 = tcg_temp_new();
-    zero = tcg_constant_tl(0);
-    one = tcg_constant_tl(1);
-    max = tcg_constant_tl(~0);
-
-    /*
-     * If div by zero, set temp1 to max and temp2 to 1 to
-     * produce the required result of max.
-     */
-    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
-    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
-    tcg_gen_divu_tl(ret, temp1, temp2);
-
-    tcg_temp_free(temp1);
-    tcg_temp_free(temp2);
-}
-
-static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
-{
-    TCGv temp1, temp2, zero, one, mone, min;
-
-    temp1 = tcg_temp_new();
-    temp2 = tcg_temp_new();
-    zero = tcg_constant_tl(0);
-    one = tcg_constant_tl(1);
-    mone = tcg_constant_tl(-1);
-    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
-
-    /*
-     * If overflow, set temp1 to 0, else source1.
-     * This avoids a possible host trap, and produces the required result of 0.
-     */
-    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
-    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
-    tcg_gen_and_tl(temp1, temp1, temp2);
-    tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1);
-
-    /*
-     * If div by zero, set temp2 to 1, else source2.
-     * This avoids a possible host trap, but produces an incorrect result.
-     */
-    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
-
-    tcg_gen_rem_tl(temp1, temp1, temp2);
-
-    /* If div by zero, the required result is the original dividend. */
-    tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1);
-
-    tcg_temp_free(temp1);
-    tcg_temp_free(temp2);
-}
-
-static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
-{
-    TCGv temp, zero, one;
-
-    temp = tcg_temp_new();
-    zero = tcg_constant_tl(0);
-    one = tcg_constant_tl(1);
-
-    /*
-     * If div by zero, set temp to 1, else source2.
-     * This avoids a possible host trap, but produces an incorrect result.
-     */
-    tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2);
-
-    tcg_gen_remu_tl(temp, source1, temp);
-
-    /* If div by zero, the required result is the original dividend. */
-    tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp);
-
-    tcg_temp_free(temp);
-}
-
 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 {
     target_ulong next_pc;
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
     return gen_arith(ctx, a, EXT_NONE, gen_mulh);
 }
 
+static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv rl = tcg_temp_new();
+    TCGv rh = tcg_temp_new();
+
+    tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
+    /* fix up for one negative */
+    tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
+    tcg_gen_and_tl(rl, rl, arg2);
+    tcg_gen_sub_tl(ret, rh, rl);
+
+    tcg_temp_free(rl);
+    tcg_temp_free(rh);
+}
+
 static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
 {
     REQUIRE_EXT(ctx, RVM);
@@ -XXX,XX +XXX,XX @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
     return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
 }
 
+static void gen_div(TCGv ret, TCGv source1, TCGv source2)
+{
+    TCGv temp1, temp2, zero, one, mone, min;
+
+    temp1 = tcg_temp_new();
+    temp2 = tcg_temp_new();
+    zero = tcg_constant_tl(0);
+    one = tcg_constant_tl(1);
+    mone = tcg_constant_tl(-1);
+    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
+
+    /*
+     * If overflow, set temp2 to 1, else source2.
+     * This produces the required result of min.
+     */
+    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
+    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
+    tcg_gen_and_tl(temp1, temp1, temp2);
+    tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2);
+
+    /*
+     * If div by zero, set temp1 to -1 and temp2 to 1 to
+     * produce the required result of -1.
+     */
+    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
+    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2);
+
+    tcg_gen_div_tl(ret, temp1, temp2);
+
+    tcg_temp_free(temp1);
+    tcg_temp_free(temp2);
+}
+
 static bool trans_div(DisasContext *ctx, arg_div *a)
 {
     REQUIRE_EXT(ctx, RVM);
     return gen_arith(ctx, a, EXT_SIGN, gen_div);
 }
 
+static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
+{
+    TCGv temp1, temp2, zero, one, max;
+
+    temp1 = tcg_temp_new();
+    temp2 = tcg_temp_new();
+    zero = tcg_constant_tl(0);
+    one = tcg_constant_tl(1);
+    max = tcg_constant_tl(~0);
+
+    /*
+     * If div by zero, set temp1 to max and temp2 to 1 to
+     * produce the required result of max.
+     */
+    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
+    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
+    tcg_gen_divu_tl(ret, temp1, temp2);
+
+    tcg_temp_free(temp1);
+    tcg_temp_free(temp2);
+}
+
 static bool trans_divu(DisasContext *ctx, arg_divu *a)
 {
     REQUIRE_EXT(ctx, RVM);
     return gen_arith(ctx, a, EXT_ZERO, gen_divu);
 }
 
+static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
+{
+    TCGv temp1, temp2, zero, one, mone, min;
+
+    temp1 = tcg_temp_new();
+    temp2 = tcg_temp_new();
+    zero = tcg_constant_tl(0);
+    one = tcg_constant_tl(1);
+    mone = tcg_constant_tl(-1);
+    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
+
+    /*
+     * If overflow, set temp1 to 0, else source1.
+     * This avoids a possible host trap, and produces the required result of 0.
+     */
+    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
+    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
+    tcg_gen_and_tl(temp1, temp1, temp2);
+    tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1);
+
+    /*
+     * If div by zero, set temp2 to 1, else source2.
+     * This avoids a possible host trap, but produces an incorrect result.
+     */
+    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
+
+    tcg_gen_rem_tl(temp1, temp1, temp2);
+
+    /* If div by zero, the required result is the original dividend. */
+    tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1);
+
+    tcg_temp_free(temp1);
+    tcg_temp_free(temp2);
+}
+
 static bool trans_rem(DisasContext *ctx, arg_rem *a)
 {
     REQUIRE_EXT(ctx, RVM);
     return gen_arith(ctx, a, EXT_SIGN, gen_rem);
 }
 
+static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
+{
+    TCGv temp, zero, one;
+
+    temp = tcg_temp_new();
+    zero = tcg_constant_tl(0);
+    one = tcg_constant_tl(1);
+
+    /*
+     * If div by zero, set temp to 1, else source2.
+     * This avoids a possible host trap, but produces an incorrect result.
+     */
+    tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2);
+
+    tcg_gen_remu_tl(temp, source1, temp);
+
+    /* If div by zero, the required result is the original dividend. */
+    tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp);
+
+    tcg_temp_free(temp);
+}
+
 static bool trans_remu(DisasContext *ctx, arg_remu *a)
 {
     REQUIRE_EXT(ctx, RVM);
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Move these helpers near their use by the trans_*
functions within insn_trans/trans_rvb.c.inc.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-11-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 233 -----------------------
 target/riscv/insn_trans/trans_rvb.c.inc | 234 ++++++++++++++++++++++++
 2 files changed, 234 insertions(+), 233 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
     return true;
 }
 
-static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    tcg_gen_deposit_tl(ret, arg1, arg2,
-                       TARGET_LONG_BITS / 2,
-                       TARGET_LONG_BITS / 2);
-}
-
-static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    TCGv t = tcg_temp_new();
-    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
-    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
-    tcg_temp_free(t);
-}
-
-static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    TCGv t = tcg_temp_new();
-    tcg_gen_ext8u_tl(t, arg2);
-    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
-    tcg_temp_free(t);
-}
-
-static void gen_sbop_mask(TCGv ret, TCGv shamt)
-{
-    tcg_gen_movi_tl(ret, 1);
-    tcg_gen_shl_tl(ret, ret, shamt);
-}
-
-static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
-{
-    TCGv t = tcg_temp_new();
-
-    gen_sbop_mask(t, shamt);
-    tcg_gen_or_tl(ret, arg1, t);
-
-    tcg_temp_free(t);
-}
-
-static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
-{
-    TCGv t = tcg_temp_new();
-
-    gen_sbop_mask(t, shamt);
-    tcg_gen_andc_tl(ret, arg1, t);
-
-    tcg_temp_free(t);
-}
-
-static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
-{
-    TCGv t = tcg_temp_new();
-
-    gen_sbop_mask(t, shamt);
-    tcg_gen_xor_tl(ret, arg1, t);
-
-    tcg_temp_free(t);
-}
-
-static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
-{
-    tcg_gen_shr_tl(ret, arg1, shamt);
-    tcg_gen_andi_tl(ret, ret, 1);
-}
-
-static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    tcg_gen_not_tl(ret, arg1);
-    tcg_gen_shl_tl(ret, ret, arg2);
-    tcg_gen_not_tl(ret, ret);
-}
-
-static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    tcg_gen_not_tl(ret, arg1);
-    tcg_gen_shr_tl(ret, ret, arg2);
-    tcg_gen_not_tl(ret, ret);
-}
-
-static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
-{
-    TCGv source1 = tcg_temp_new();
-    TCGv source2;
-
-    gen_get_gpr(ctx, source1, a->rs1);
-
-    if (a->shamt == (TARGET_LONG_BITS - 8)) {
-        /* rev8, byte swaps */
-        tcg_gen_bswap_tl(source1, source1);
-    } else {
-        source2 = tcg_temp_new();
-        tcg_gen_movi_tl(source2, a->shamt);
-        gen_helper_grev(source1, source1, source2);
-        tcg_temp_free(source2);
-    }
-
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    return true;
-}
-
-#define GEN_SHADD(SHAMT)                                       \
-static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
-{                                                              \
-    TCGv t = tcg_temp_new();                                   \
-                                                               \
-    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
-    tcg_gen_add_tl(ret, t, arg2);                              \
-                                                               \
-    tcg_temp_free(t);                                          \
-}
-
-GEN_SHADD(1)
-GEN_SHADD(2)
-GEN_SHADD(3)
-
-static void gen_ctzw(TCGv ret, TCGv arg1)
-{
-    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
-    tcg_gen_ctzi_tl(ret, ret, 64);
-}
-
-static void gen_clzw(TCGv ret, TCGv arg1)
-{
-    tcg_gen_ext32u_tl(ret, arg1);
-    tcg_gen_clzi_tl(ret, ret, 64);
-    tcg_gen_subi_tl(ret, ret, 32);
-}
-
-static void gen_cpopw(TCGv ret, TCGv arg1)
-{
-    tcg_gen_ext32u_tl(arg1, arg1);
-    tcg_gen_ctpop_tl(ret, arg1);
-}
-
-static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    TCGv t = tcg_temp_new();
-    tcg_gen_ext16s_tl(t, arg2);
-    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
-    tcg_temp_free(t);
-}
-
-static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    TCGv t = tcg_temp_new();
-    tcg_gen_shri_tl(t, arg1, 16);
-    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
-    tcg_gen_ext32s_tl(ret, ret);
-    tcg_temp_free(t);
-}
-
-static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    TCGv_i32 t1 = tcg_temp_new_i32();
-    TCGv_i32 t2 = tcg_temp_new_i32();
-
-    /* truncate to 32-bits */
-    tcg_gen_trunc_tl_i32(t1, arg1);
-    tcg_gen_trunc_tl_i32(t2, arg2);
-
-    tcg_gen_rotr_i32(t1, t1, t2);
-
-    /* sign-extend 64-bits */
-    tcg_gen_ext_i32_tl(ret, t1);
-
-    tcg_temp_free_i32(t1);
-    tcg_temp_free_i32(t2);
-}
-
-static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    TCGv_i32 t1 = tcg_temp_new_i32();
-    TCGv_i32 t2 = tcg_temp_new_i32();
-
-    /* truncate to 32-bits */
-    tcg_gen_trunc_tl_i32(t1, arg1);
-    tcg_gen_trunc_tl_i32(t2, arg2);
-
-    tcg_gen_rotl_i32(t1, t1, t2);
-
-    /* sign-extend 64-bits */
-    tcg_gen_ext_i32_tl(ret, t1);
-
-    tcg_temp_free_i32(t1);
-    tcg_temp_free_i32(t2);
-}
-
-static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    tcg_gen_ext32u_tl(arg1, arg1);
-    gen_helper_grev(ret, arg1, arg2);
-}
-
-static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    tcg_gen_ext32u_tl(arg1, arg1);
-    gen_helper_gorcw(ret, arg1, arg2);
-}
-
-#define GEN_SHADD_UW(SHAMT)                                       \
-static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
-{                                                                 \
-    TCGv t = tcg_temp_new();                                      \
-                                                                  \
-    tcg_gen_ext32u_tl(t, arg1);                                   \
-                                                                  \
-    tcg_gen_shli_tl(t, t, SHAMT);                                 \
-    tcg_gen_add_tl(ret, t, arg2);                                 \
-                                                                  \
-    tcg_temp_free(t);                                             \
-}
-
-GEN_SHADD_UW(1)
-GEN_SHADD_UW(2)
-GEN_SHADD_UW(3)
-
-static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    tcg_gen_ext32u_tl(arg1, arg1);
-    tcg_gen_add_tl(ret, arg1, arg2);
-}
-
 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
                       void (*func)(TCGv, TCGv, TCGv))
 {
@@ -XXX,XX +XXX,XX @@ static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
     return true;
 }
 
-static void gen_ctz(TCGv ret, TCGv arg1)
-{
-    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
-}
-
-static void gen_clz(TCGv ret, TCGv arg1)
-{
-    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
-}
-
 static bool gen_unary(DisasContext *ctx, arg_r2 *a,
                       void(*func)(TCGv, TCGv))
 {
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+
+static void gen_clz(TCGv ret, TCGv arg1)
+{
+    tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
+}
+
 static bool trans_clz(DisasContext *ctx, arg_clz *a)
 {
     REQUIRE_EXT(ctx, RVB);
     return gen_unary(ctx, a, gen_clz);
 }
 
+static void gen_ctz(TCGv ret, TCGv arg1)
+{
+    tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
+}
+
 static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
 {
     REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
     return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
 }
 
+static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_deposit_tl(ret, arg1, arg2,
+                       TARGET_LONG_BITS / 2,
+                       TARGET_LONG_BITS / 2);
+}
+
 static bool trans_pack(DisasContext *ctx, arg_pack *a)
 {
     REQUIRE_EXT(ctx, RVB);
     return gen_arith(ctx, a, EXT_NONE, gen_pack);
 }
 
+static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv t = tcg_temp_new();
+    tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
+    tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
+    tcg_temp_free(t);
+}
+
 static bool trans_packu(DisasContext *ctx, arg_packu *a)
 {
     REQUIRE_EXT(ctx, RVB);
     return gen_arith(ctx, a, EXT_NONE, gen_packu);
 }
 
+static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv t = tcg_temp_new();
+    tcg_gen_ext8u_tl(t, arg2);
+    tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
+    tcg_temp_free(t);
+}
+
 static bool trans_packh(DisasContext *ctx, arg_packh *a)
 {
     REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
     return gen_unary(ctx, a, tcg_gen_ext16s_tl);
 }
 
+static void gen_sbop_mask(TCGv ret, TCGv shamt)
+{
+    tcg_gen_movi_tl(ret, 1);
+    tcg_gen_shl_tl(ret, ret, shamt);
+}
+
+static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
+{
+    TCGv t = tcg_temp_new();
+
+    gen_sbop_mask(t, shamt);
+    tcg_gen_or_tl(ret, arg1, t);
+
+    tcg_temp_free(t);
+}
+
 static bool trans_bset(DisasContext *ctx, arg_bset *a)
 {
     REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
     return gen_shifti(ctx, a, gen_bset);
 }
 
+static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
+{
+    TCGv t = tcg_temp_new();
+
+    gen_sbop_mask(t, shamt);
+    tcg_gen_andc_tl(ret, arg1, t);
+
+    tcg_temp_free(t);
+}
+
 static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
 {
     REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
     return gen_shifti(ctx, a, gen_bclr);
 }
 
+static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
+{
+    TCGv t = tcg_temp_new();
+
+    gen_sbop_mask(t, shamt);
+    tcg_gen_xor_tl(ret, arg1, t);
+
+    tcg_temp_free(t);
+}
+
 static bool trans_binv(DisasContext *ctx, arg_binv *a)
 {
     REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
     return gen_shifti(ctx, a, gen_binv);
 }
 
+static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
+{
+    tcg_gen_shr_tl(ret, arg1, shamt);
+    tcg_gen_andi_tl(ret, ret, 1);
+}
+
 static bool trans_bext(DisasContext *ctx, arg_bext *a)
 {
     REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
     return gen_shifti(ctx, a, gen_bext);
 }
 
+static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_not_tl(ret, arg1);
+    tcg_gen_shl_tl(ret, ret, arg2);
+    tcg_gen_not_tl(ret, ret);
+}
+
 static bool trans_slo(DisasContext *ctx, arg_slo *a)
 {
     REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
     return gen_shifti(ctx, a, gen_slo);
 }
 
+static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_not_tl(ret, arg1);
+    tcg_gen_shr_tl(ret, ret, arg2);
+    tcg_gen_not_tl(ret, ret);
+}
+
 static bool trans_sro(DisasContext *ctx, arg_sro *a)
 {
     REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_grev(DisasContext *ctx, arg_grev *a)
     return gen_shift(ctx, a, gen_helper_grev);
 }
 
+static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
+{
+    TCGv source1 = tcg_temp_new();
+    TCGv source2;
+
+    gen_get_gpr(ctx, source1, a->rs1);
+
+    if (a->shamt == (TARGET_LONG_BITS - 8)) {
+        /* rev8, byte swaps */
+        tcg_gen_bswap_tl(source1, source1);
+    } else {
+        source2 = tcg_temp_new();
+        tcg_gen_movi_tl(source2, a->shamt);
+        gen_helper_grev(source1, source1, source2);
+        tcg_temp_free(source2);
+    }
+
+    gen_set_gpr(ctx, a->rd, source1);
+    tcg_temp_free(source1);
+    return true;
+}
+
 static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
 {
     REQUIRE_EXT(ctx, RVB);
@@ -XXX,XX +XXX,XX @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
     return gen_shifti(ctx, a, gen_helper_gorc);
 }
 
+#define GEN_SHADD(SHAMT)                                       \
+static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
+{                                                              \
+    TCGv t = tcg_temp_new();                                   \
+                                                               \
+    tcg_gen_shli_tl(t, arg1, SHAMT);                           \
+    tcg_gen_add_tl(ret, t, arg2);                              \
+                                                               \
+    tcg_temp_free(t);                                          \
+}
+
+GEN_SHADD(1)
+GEN_SHADD(2)
+GEN_SHADD(3)
+
 #define GEN_TRANS_SHADD(SHAMT)                                             \
 static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
 {                                                                          \
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(1)
 GEN_TRANS_SHADD(2)
 GEN_TRANS_SHADD(3)
 
+static void gen_clzw(TCGv ret, TCGv arg1)
+{
+    tcg_gen_ext32u_tl(ret, arg1);
+    tcg_gen_clzi_tl(ret, ret, 64);
+    tcg_gen_subi_tl(ret, ret, 32);
+}
+
 static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
     return gen_unary(ctx, a, gen_clzw);
 }
 
+static void gen_ctzw(TCGv ret, TCGv arg1)
+{
+    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
+    tcg_gen_ctzi_tl(ret, ret, 64);
+}
+
 static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
     return gen_unary(ctx, a, gen_ctzw);
 }
 
+static void gen_cpopw(TCGv ret, TCGv arg1)
+{
+    tcg_gen_ext32u_tl(arg1, arg1);
+    tcg_gen_ctpop_tl(ret, arg1);
+}
+
 static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
     return gen_unary(ctx, a, gen_cpopw);
 }
 
+static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv t = tcg_temp_new();
+    tcg_gen_ext16s_tl(t, arg2);
+    tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
+    tcg_temp_free(t);
+}
+
 static bool trans_packw(DisasContext *ctx, arg_packw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_packw(DisasContext *ctx, arg_packw *a)
     return gen_arith(ctx, a, EXT_NONE, gen_packw);
 }
 
+static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv t = tcg_temp_new();
+    tcg_gen_shri_tl(t, arg1, 16);
+    tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
+    tcg_gen_ext32s_tl(ret, ret);
+    tcg_temp_free(t);
+}
+
 static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
     return gen_shiftiw(ctx, a, gen_sro);
 }
 
+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv_i32 t1 = tcg_temp_new_i32();
+    TCGv_i32 t2 = tcg_temp_new_i32();
+
+    /* truncate to 32-bits */
+    tcg_gen_trunc_tl_i32(t1, arg1);
+    tcg_gen_trunc_tl_i32(t2, arg2);
+
+    tcg_gen_rotr_i32(t1, t1, t2);
+
+    /* sign-extend 64-bits */
+    tcg_gen_ext_i32_tl(ret, t1);
+
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t2);
+}
+
 static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
     return gen_shiftiw(ctx, a, gen_rorw);
 }
 
+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv_i32 t1 = tcg_temp_new_i32();
+    TCGv_i32 t2 = tcg_temp_new_i32();
+
+    /* truncate to 32-bits */
+    tcg_gen_trunc_tl_i32(t1, arg1);
+    tcg_gen_trunc_tl_i32(t2, arg2);
+
+    tcg_gen_rotl_i32(t1, t1, t2);
+
+    /* sign-extend 64-bits */
+    tcg_gen_ext_i32_tl(ret, t1);
+
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t2);
+}
+
 static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
     return gen_shiftw(ctx, a, gen_rolw);
 }
 
+static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_ext32u_tl(arg1, arg1);
+    gen_helper_grev(ret, arg1, arg2);
+}
+
 static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
     return gen_shiftiw(ctx, a, gen_grevw);
 }
 
+static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_ext32u_tl(arg1, arg1);
+    gen_helper_gorcw(ret, arg1, arg2);
+}
+
 static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
     return gen_shiftiw(ctx, a, gen_gorcw);
 }
 
+#define GEN_SHADD_UW(SHAMT)                                       \
+static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
+{                                                                 \
+    TCGv t = tcg_temp_new();                                      \
+                                                                  \
+    tcg_gen_ext32u_tl(t, arg1);                                   \
+                                                                  \
+    tcg_gen_shli_tl(t, t, SHAMT);                                 \
+    tcg_gen_add_tl(ret, t, arg2);                                 \
+                                                                  \
+    tcg_temp_free(t);                                             \
+}
+
+GEN_SHADD_UW(1)
+GEN_SHADD_UW(2)
+GEN_SHADD_UW(3)
+
 #define GEN_TRANS_SHADD_UW(SHAMT)                             \
 static bool trans_sh##SHAMT##add_uw(DisasContext *ctx,        \
                                     arg_sh##SHAMT##add_uw *a) \
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD_UW(1)
 GEN_TRANS_SHADD_UW(2)
 GEN_TRANS_SHADD_UW(3)
 
+static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    tcg_gen_ext32u_tl(arg1, arg1);
+    tcg_gen_add_tl(ret, arg1, arg2);
+}
+
 static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
 {
     REQUIRE_64BIT(ctx);
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Use ctx->w for ctpopw, which is the only one that can
re-use the generic algorithm for the narrow operation.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-12-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 14 ++++++--------
 target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++---------------
 2 files changed, 15 insertions(+), 23 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
     return true;
 }
 
-static bool gen_unary(DisasContext *ctx, arg_r2 *a,
-                      void(*func)(TCGv, TCGv))
+static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
+                      void (*func)(TCGv, TCGv))
 {
-    TCGv source = tcg_temp_new();
-
-    gen_get_gpr(ctx, source, a->rs1);
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
 
-    (*func)(source, source);
+    func(dest, src1);
 
-    gen_set_gpr(ctx, a->rd, source);
-    tcg_temp_free(source);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static void gen_clz(TCGv ret, TCGv arg1)
 static bool trans_clz(DisasContext *ctx, arg_clz *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_unary(ctx, a, gen_clz);
+    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
 }
 
 static void gen_ctz(TCGv ret, TCGv arg1)
@@ -XXX,XX +XXX,XX @@ static void gen_ctz(TCGv ret, TCGv arg1)
 static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_unary(ctx, a, gen_ctz);
+    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
 }
 
 static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_unary(ctx, a, tcg_gen_ctpop_tl);
+    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
 }
 
 static bool trans_andn(DisasContext *ctx, arg_andn *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
 static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_unary(ctx, a, tcg_gen_ext8s_tl);
+    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
 }
 
 static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_unary(ctx, a, tcg_gen_ext16s_tl);
+    return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
 }
 
 static void gen_sbop_mask(TCGv ret, TCGv shamt)
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_SHADD(3)
 
 static void gen_clzw(TCGv ret, TCGv arg1)
 {
-    tcg_gen_ext32u_tl(ret, arg1);
     tcg_gen_clzi_tl(ret, ret, 64);
     tcg_gen_subi_tl(ret, ret, 32);
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_unary(ctx, a, gen_clzw);
+    return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
 }
 
 static void gen_ctzw(TCGv ret, TCGv arg1)
@@ -XXX,XX +XXX,XX @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_unary(ctx, a, gen_ctzw);
-}
-
-static void gen_cpopw(TCGv ret, TCGv arg1)
-{
-    tcg_gen_ext32u_tl(arg1, arg1);
-    tcg_gen_ctpop_tl(ret, arg1);
+    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
 }
 
 static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_unary(ctx, a, gen_cpopw);
+    ctx->w = true;
+    return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
 }
 
 static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

These operations are greatly simplified by ctx->w, which allows
us to fold gen_shiftw into gen_shift.  Split gen_shifti into
gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-13-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 110 +++++++++-----------
 target/riscv/insn_trans/trans_rvb.c.inc | 129 +++++++++++-------------
 target/riscv/insn_trans/trans_rvi.c.inc |  88 ++++------------
 3 files changed, 125 insertions(+), 202 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static inline bool is_32bit(DisasContext *ctx)
 }
 #endif
 
+/* The word size for this operation. */
+static inline int oper_len(DisasContext *ctx)
+{
+    return ctx->w ? 32 : TARGET_LONG_BITS;
+}
+
+
 /*
  * RISC-V requires NaN-boxing of narrower width floating point values.
  * This applies when a 32-bit value is assigned to a 64-bit FP register.
@@ -XXX,XX +XXX,XX @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
     return true;
 }
 
-static bool gen_shift(DisasContext *ctx, arg_r *a,
-                        void(*func)(TCGv, TCGv, TCGv))
-{
-    TCGv source1 = tcg_temp_new();
-    TCGv source2 = tcg_temp_new();
-
-    gen_get_gpr(ctx, source1, a->rs1);
-    gen_get_gpr(ctx, source2, a->rs2);
-
-    tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
-    (*func)(source1, source1, source2);
-
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
-    return true;
-}
-
-static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
+static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
+                             void (*func)(TCGv, TCGv, target_long))
 {
-    DisasContext *ctx = container_of(dcbase, DisasContext, base);
-    CPUState *cpu = ctx->cs;
-    CPURISCVState *env = cpu->env_ptr;
+    TCGv dest, src1;
+    int max_len = oper_len(ctx);
 
-    return cpu_ldl_code(env, pc);
-}
-
-static bool gen_shifti(DisasContext *ctx, arg_shift *a,
-                       void(*func)(TCGv, TCGv, TCGv))
-{
-    if (a->shamt >= TARGET_LONG_BITS) {
+    if (a->shamt >= max_len) {
         return false;
     }
 
-    TCGv source1 = tcg_temp_new();
-    TCGv source2 = tcg_temp_new();
-
-    gen_get_gpr(ctx, source1, a->rs1);
+    dest = dest_gpr(ctx, a->rd);
+    src1 = get_gpr(ctx, a->rs1, ext);
 
-    tcg_gen_movi_tl(source2, a->shamt);
-    (*func)(source1, source1, source2);
+    func(dest, src1, a->shamt);
 
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
-static bool gen_shiftw(DisasContext *ctx, arg_r *a,
-                       void(*func)(TCGv, TCGv, TCGv))
+static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
+                             void (*func)(TCGv, TCGv, TCGv))
 {
-    TCGv source1 = tcg_temp_new();
-    TCGv source2 = tcg_temp_new();
+    TCGv dest, src1, src2;
+    int max_len = oper_len(ctx);
+
+    if (a->shamt >= max_len) {
+        return false;
+    }
 
-    gen_get_gpr(ctx, source1, a->rs1);
-    gen_get_gpr(ctx, source2, a->rs2);
+    dest = dest_gpr(ctx, a->rd);
+    src1 = get_gpr(ctx, a->rs1, ext);
+    src2 = tcg_constant_tl(a->shamt);
 
-    tcg_gen_andi_tl(source2, source2, 31);
-    (*func)(source1, source1, source2);
-    tcg_gen_ext32s_tl(source1, source1);
+    func(dest, src1, src2);
 
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
-static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
-                        void(*func)(TCGv, TCGv, TCGv))
+static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
+                      void (*func)(TCGv, TCGv, TCGv))
 {
-    TCGv source1 = tcg_temp_new();
-    TCGv source2 = tcg_temp_new();
-
-    gen_get_gpr(ctx, source1, a->rs1);
-    tcg_gen_movi_tl(source2, a->shamt);
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+    TCGv ext2 = tcg_temp_new();
 
-    (*func)(source1, source1, source2);
-    tcg_gen_ext32s_tl(source1, source1);
+    tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
+    func(dest, src1, ext2);
 
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
+    gen_set_gpr(ctx, a->rd, dest);
+    tcg_temp_free(ext2);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
     return true;
 }
 
+static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
+{
+    DisasContext *ctx = container_of(dcbase, DisasContext, base);
+    CPUState *cpu = ctx->cs;
+    CPURISCVState *env = cpu->env_ptr;
+
+    return cpu_ldl_code(env, pc);
+}
+
 /* Include insn module translation function */
 #include "insn_trans/trans_rvi.c.inc"
 #include "insn_trans/trans_rvm.c.inc"
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
 static bool trans_bset(DisasContext *ctx, arg_bset *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, gen_bset);
+    return gen_shift(ctx, a, EXT_NONE, gen_bset);
 }
 
 static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shifti(ctx, a, gen_bset);
+    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
 }
 
 static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
@@ -XXX,XX +XXX,XX @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
 static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, gen_bclr);
+    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
 }
 
 static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shifti(ctx, a, gen_bclr);
+    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
 }
 
 static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
@@ -XXX,XX +XXX,XX @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
 static bool trans_binv(DisasContext *ctx, arg_binv *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, gen_binv);
+    return gen_shift(ctx, a, EXT_NONE, gen_binv);
 }
 
 static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shifti(ctx, a, gen_binv);
+    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
 }
 
 static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
@@ -XXX,XX +XXX,XX @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
 static bool trans_bext(DisasContext *ctx, arg_bext *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, gen_bext);
+    return gen_shift(ctx, a, EXT_NONE, gen_bext);
 }
 
 static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shifti(ctx, a, gen_bext);
+    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
 }
 
 static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
@@ -XXX,XX +XXX,XX @@ static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
 static bool trans_slo(DisasContext *ctx, arg_slo *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, gen_slo);
+    return gen_shift(ctx, a, EXT_NONE, gen_slo);
 }
 
 static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shifti(ctx, a, gen_slo);
+    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
 }
 
 static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
@@ -XXX,XX +XXX,XX @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
 static bool trans_sro(DisasContext *ctx, arg_sro *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, gen_sro);
+    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
 }
 
 static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shifti(ctx, a, gen_sro);
+    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
 }
 
 static bool trans_ror(DisasContext *ctx, arg_ror *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, tcg_gen_rotr_tl);
+    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
 }
 
 static bool trans_rori(DisasContext *ctx, arg_rori *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shifti(ctx, a, tcg_gen_rotr_tl);
+    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
 }
 
 static bool trans_rol(DisasContext *ctx, arg_rol *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, tcg_gen_rotl_tl);
+    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
 }
 
 static bool trans_grev(DisasContext *ctx, arg_grev *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, gen_helper_grev);
+    return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
 }
 
-static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
+static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
 {
-    TCGv source1 = tcg_temp_new();
-    TCGv source2;
-
-    gen_get_gpr(ctx, source1, a->rs1);
-
-    if (a->shamt == (TARGET_LONG_BITS - 8)) {
+    if (shamt == TARGET_LONG_BITS - 8) {
         /* rev8, byte swaps */
-        tcg_gen_bswap_tl(source1, source1);
+        tcg_gen_bswap_tl(dest, src);
     } else {
-        source2 = tcg_temp_new();
-        tcg_gen_movi_tl(source2, a->shamt);
-        gen_helper_grev(source1, source1, source2);
-        tcg_temp_free(source2);
+        gen_helper_grev(dest, src, tcg_constant_tl(shamt));
     }
-
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    return true;
 }
 
 static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
 {
     REQUIRE_EXT(ctx, RVB);
-
-    if (a->shamt >= TARGET_LONG_BITS) {
-        return false;
-    }
-
-    return gen_grevi(ctx, a);
+    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
 }
 
 static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shift(ctx, a, gen_helper_gorc);
+    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
 }
 
 static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
 {
     REQUIRE_EXT(ctx, RVB);
-    return gen_shifti(ctx, a, gen_helper_gorc);
+    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
 }
 
 #define GEN_SHADD(SHAMT)                                       \
@@ -XXX,XX +XXX,XX @@ static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftw(ctx, a, gen_bset);
+    ctx->w = true;
+    return gen_shift(ctx, a, EXT_NONE, gen_bset);
 }
 
 static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftiw(ctx, a, gen_bset);
+    ctx->w = true;
+    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
 }
 
 static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftw(ctx, a, gen_bclr);
+    ctx->w = true;
+    return gen_shift(ctx, a, EXT_NONE, gen_bclr);
 }
 
 static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftiw(ctx, a, gen_bclr);
+    ctx->w = true;
+    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
 }
 
 static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftw(ctx, a, gen_binv);
+    ctx->w = true;
+    return gen_shift(ctx, a, EXT_NONE, gen_binv);
 }
 
 static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftiw(ctx, a, gen_binv);
+    ctx->w = true;
+    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
 }
 
 static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftw(ctx, a, gen_bext);
+    ctx->w = true;
+    return gen_shift(ctx, a, EXT_NONE, gen_bext);
 }
 
 static bool trans_slow(DisasContext *ctx, arg_slow *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftw(ctx, a, gen_slo);
+    ctx->w = true;
+    return gen_shift(ctx, a, EXT_NONE, gen_slo);
 }
 
 static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftiw(ctx, a, gen_slo);
+    ctx->w = true;
+    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
 }
 
 static bool trans_srow(DisasContext *ctx, arg_srow *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftw(ctx, a, gen_sro);
+    ctx->w = true;
+    return gen_shift(ctx, a, EXT_ZERO, gen_sro);
 }
 
 static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftiw(ctx, a, gen_sro);
+    ctx->w = true;
+    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
 }
 
 static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
@@ -XXX,XX +XXX,XX @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftw(ctx, a, gen_rorw);
+    ctx->w = true;
+    return gen_shift(ctx, a, EXT_NONE, gen_rorw);
 }
 
 static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftiw(ctx, a, gen_rorw);
+    ctx->w = true;
+    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
 }
 
 static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftw(ctx, a, gen_rolw);
-}
-
-static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    tcg_gen_ext32u_tl(arg1, arg1);
-    gen_helper_grev(ret, arg1, arg2);
+    ctx->w = true;
+    return gen_shift(ctx, a, EXT_NONE, gen_rolw);
 }
 
 static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftw(ctx, a, gen_grevw);
+    ctx->w = true;
+    return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
 }
 
 static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftiw(ctx, a, gen_grevw);
-}
-
-static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    tcg_gen_ext32u_tl(arg1, arg1);
-    gen_helper_gorcw(ret, arg1, arg2);
+    ctx->w = true;
+    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
 }
 
 static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftw(ctx, a, gen_gorcw);
+    ctx->w = true;
+    return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
 }
 
 static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-    return gen_shiftiw(ctx, a, gen_gorcw);
+    ctx->w = true;
+    return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
 }
 
 #define GEN_SHADD_UW(SHAMT)                                       \
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
 
 static bool trans_slli(DisasContext *ctx, arg_slli *a)
 {
-    return gen_shifti(ctx, a, tcg_gen_shl_tl);
+    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
 }
 
 static bool trans_srli(DisasContext *ctx, arg_srli *a)
 {
-    return gen_shifti(ctx, a, tcg_gen_shr_tl);
+    return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
 }
 
 static bool trans_srai(DisasContext *ctx, arg_srai *a)
 {
-    return gen_shifti(ctx, a, tcg_gen_sar_tl);
+    return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
 }
 
 static bool trans_add(DisasContext *ctx, arg_add *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_sub(DisasContext *ctx, arg_sub *a)
 
 static bool trans_sll(DisasContext *ctx, arg_sll *a)
 {
-    return gen_shift(ctx, a, &tcg_gen_shl_tl);
+    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
 }
 
 static bool trans_slt(DisasContext *ctx, arg_slt *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_xor(DisasContext *ctx, arg_xor *a)
 
 static bool trans_srl(DisasContext *ctx, arg_srl *a)
 {
-    return gen_shift(ctx, a, &tcg_gen_shr_tl);
+    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
 }
 
 static bool trans_sra(DisasContext *ctx, arg_sra *a)
 {
-    return gen_shift(ctx, a, &tcg_gen_sar_tl);
+    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
 }
 
 static bool trans_or(DisasContext *ctx, arg_or *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
 static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
 {
     REQUIRE_64BIT(ctx);
-    return gen_shiftiw(ctx, a, tcg_gen_shl_tl);
+    ctx->w = true;
+    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
 }
 
 static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
 {
     REQUIRE_64BIT(ctx);
-    TCGv t = tcg_temp_new();
-    gen_get_gpr(ctx, t, a->rs1);
-    tcg_gen_extract_tl(t, t, a->shamt, 32 - a->shamt);
-    /* sign-extend for W instructions */
-    tcg_gen_ext32s_tl(t, t);
-    gen_set_gpr(ctx, a->rd, t);
-    tcg_temp_free(t);
-    return true;
+    ctx->w = true;
+    return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
 }
 
 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 {
     REQUIRE_64BIT(ctx);
-    TCGv t = tcg_temp_new();
-    gen_get_gpr(ctx, t, a->rs1);
-    tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
-    gen_set_gpr(ctx, a->rd, t);
-    tcg_temp_free(t);
-    return true;
+    ctx->w = true;
+    return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
 }
 
 static bool trans_addw(DisasContext *ctx, arg_addw *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_subw(DisasContext *ctx, arg_subw *a)
 static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
 {
     REQUIRE_64BIT(ctx);
-    TCGv source1 = tcg_temp_new();
-    TCGv source2 = tcg_temp_new();
-
-    gen_get_gpr(ctx, source1, a->rs1);
-    gen_get_gpr(ctx, source2, a->rs2);
-
-    tcg_gen_andi_tl(source2, source2, 0x1F);
-    tcg_gen_shl_tl(source1, source1, source2);
-
-    tcg_gen_ext32s_tl(source1, source1);
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
-    return true;
+    ctx->w = true;
+    return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
 }
 
 static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
 {
     REQUIRE_64BIT(ctx);
-    TCGv source1 = tcg_temp_new();
-    TCGv source2 = tcg_temp_new();
-
-    gen_get_gpr(ctx, source1, a->rs1);
-    gen_get_gpr(ctx, source2, a->rs2);
-
-    /* clear upper 32 */
-    tcg_gen_ext32u_tl(source1, source1);
-    tcg_gen_andi_tl(source2, source2, 0x1F);
-    tcg_gen_shr_tl(source1, source1, source2);
-
-    tcg_gen_ext32s_tl(source1, source1);
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
-    return true;
+    ctx->w = true;
+    return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
 }
 
 static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
 {
     REQUIRE_64BIT(ctx);
-    TCGv source1 = tcg_temp_new();
-    TCGv source2 = tcg_temp_new();
-
-    gen_get_gpr(ctx, source1, a->rs1);
-    gen_get_gpr(ctx, source2, a->rs2);
-
-    /*
-     * first, trick to get it to act like working on 32 bits (get rid of
-     * upper 32, sign extend to fill space)
-     */
-    tcg_gen_ext32s_tl(source1, source1);
-    tcg_gen_andi_tl(source2, source2, 0x1F);
-    tcg_gen_sar_tl(source1, source1, source2);
-
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
-
-    return true;
+    ctx->w = true;
+    return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
 }
 
 static bool trans_fence(DisasContext *ctx, arg_fence *a)
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

These operations can be done in one instruction on some hosts.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-14-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvi.c.inc | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Narrow the scope of t0 in trans_jalr.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-15-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvi.c.inc | 25 ++++++++++---------------
 1 file changed, 10 insertions(+), 15 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
 
 static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
 {
-    /* no chaining with JALR */
     TCGLabel *misaligned = NULL;
-    TCGv t0 = tcg_temp_new();
-
 
-    gen_get_gpr(ctx, cpu_pc, a->rs1);
-    tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
+    tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
     tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
 
     if (!has_ext(ctx, RVC)) {
+        TCGv t0 = tcg_temp_new();
+
         misaligned = gen_new_label();
         tcg_gen_andi_tl(t0, cpu_pc, 0x2);
         tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
+        tcg_temp_free(t0);
     }
 
     if (a->rd != 0) {
         tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
     }
+
+    /* No chaining with JALR. */
     lookup_and_goto_ptr(ctx);
 
     if (misaligned) {
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
     }
     ctx->base.is_jmp = DISAS_NORETURN;
 
-    tcg_temp_free(t0);
     return true;
 }
 
 static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
 {
     TCGLabel *l = gen_new_label();
-    TCGv source1, source2;
-    source1 = tcg_temp_new();
-    source2 = tcg_temp_new();
-    gen_get_gpr(ctx, source1, a->rs1);
-    gen_get_gpr(ctx, source2, a->rs2);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
 
-    tcg_gen_brcond_tl(cond, source1, source2, l);
+    tcg_gen_brcond_tl(cond, src1, src2, l);
     gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
+
     gen_set_label(l); /* branch taken */
 
     if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
@@ -XXX,XX +XXX,XX @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
     }
     ctx->base.is_jmp = DISAS_NORETURN;
 
-    tcg_temp_free(source1);
-    tcg_temp_free(source2);
-
     return true;
 }
 
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-16-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvi.c.inc | 38 +++++++++++++------------
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
 
 static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
 {
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
-    tcg_gen_addi_tl(t0, t0, a->imm);
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
-    gen_set_gpr(ctx, a->rd, t1);
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+
+    if (a->imm) {
+        TCGv temp = temp_new(ctx);
+        tcg_gen_addi_tl(temp, addr, a->imm);
+        addr = temp;
+    }
+
+    tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
 
 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
 {
-    TCGv t0 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
-    tcg_gen_addi_tl(t0, t0, a->imm);
-    gen_get_gpr(ctx, dat, a->rs2);
+    TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
 
-    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
-    tcg_temp_free(t0);
-    tcg_temp_free(dat);
+    if (a->imm) {
+        TCGv temp = temp_new(ctx);
+        tcg_gen_addi_tl(temp, addr, a->imm);
+        addr = temp;
+    }
+
+    tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
     return true;
 }
 
-
 static bool trans_sb(DisasContext *ctx, arg_sb *a)
 {
     return gen_store(ctx, a, MO_SB);
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

We distinguish write-only by passing ret_value as NULL.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-17-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
     /* Shift the S bits to their VS bit location in mip */
     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
                       (write_mask << 1) & vsip_writable_mask & env->hideleg);
-    *ret_value &= VS_MODE_INTERRUPTS;
-    /* Shift the VS bits to their S bit location in vsip */
-    *ret_value >>= 1;
+
+    if (ret_value) {
+        *ret_value &= VS_MODE_INTERRUPTS;
+        /* Shift the VS bits to their S bit location in vsip */
+        *ret_value >>= 1;
+    }
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
                       write_mask & env->mideleg & sip_writable_mask);
     }
 
-    *ret_value &= env->mideleg;
+    if (ret_value) {
+        *ret_value &= env->mideleg;
+    }
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
     int ret = rmw_mip(env, 0, ret_value, new_value,
                       write_mask & hvip_writable_mask);
 
-    *ret_value &= hvip_writable_mask;
-
+    if (ret_value) {
+        *ret_value &= hvip_writable_mask;
+    }
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
     int ret = rmw_mip(env, 0, ret_value, new_value,
                       write_mask & hip_writable_mask);
 
-    *ret_value &= hip_writable_mask;
-
+    if (ret_value) {
+        *ret_value &= hip_writable_mask;
+    }
     return ret;
 }
 
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

We failed to write into *val for these read functions;
replace them with read_zero.  Only warn about unsupported
non-zero value when writing a non-zero value.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-18-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 26 ++++++++------------------
 1 file changed, 8 insertions(+), 18 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
-static RISCVException read_hgeie(CPURISCVState *env, int csrno,
-                                 target_ulong *val)
-{
-    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
-    return RISCV_EXCP_NONE;
-}
-
 static RISCVException write_hgeie(CPURISCVState *env, int csrno,
                                   target_ulong val)
 {
-    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    if (val) {
+        qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    }
     return RISCV_EXCP_NONE;
 }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException write_htinst(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
-static RISCVException read_hgeip(CPURISCVState *env, int csrno,
-                                 target_ulong *val)
-{
-    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
-    return RISCV_EXCP_NONE;
-}
-
 static RISCVException write_hgeip(CPURISCVState *env, int csrno,
                                   target_ulong val)
 {
-    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    if (val) {
+        qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    }
     return RISCV_EXCP_NONE;
 }
 
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
     [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
-    [CSR_HGEIE]       = { "hgeie",       hmode,   read_hgeie,       write_hgeie       },
+    [CSR_HGEIE]       = { "hgeie",       hmode,   read_zero,        write_hgeie       },
     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
-    [CSR_HGEIP]       = { "hgeip",       hmode,   read_hgeip,       write_hgeip       },
+    [CSR_HGEIP]       = { "hgeip",       hmode,   read_zero,        write_hgeip       },
     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Introduce csrr and csrw helpers, for read-only and write-only insns.

Note that we do not properly implement this in riscv_csrrw, in that
we cannot distinguish true read-only (rs1 == 0) from any other zero
write_mask another source register -- this should still raise an
exception for read-only registers.

Only issue gen_io_start for CF_USE_ICOUNT.
Use ctx->zero for csrrc.
Use get_gpr and dest_gpr.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-19-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |   6 +-
 target/riscv/op_helper.c                |  18 +--
 target/riscv/insn_trans/trans_rvi.c.inc | 174 +++++++++++++++++-------
 3 files changed, 132 insertions(+), 66 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
 /* Special functions */
-DEF_HELPER_3(csrrw, tl, env, tl, tl)
-DEF_HELPER_4(csrrs, tl, env, tl, tl, tl)
-DEF_HELPER_4(csrrc, tl, env, tl, tl, tl)
+DEF_HELPER_2(csrr, tl, env, int)
+DEF_HELPER_3(csrw, void, env, int, tl)
+DEF_HELPER_4(csrrw, tl, env, int, tl, tl)
 #ifndef CONFIG_USER_ONLY
 DEF_HELPER_2(sret, tl, env, tl)
 DEF_HELPER_2(mret, tl, env, tl)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_raise_exception(CPURISCVState *env, uint32_t exception)
     riscv_raise_exception(env, exception, 0);
 }
 
-target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
-        target_ulong csr)
+target_ulong helper_csrr(CPURISCVState *env, int csr)
 {
     target_ulong val = 0;
-    RISCVException ret = riscv_csrrw(env, csr, &val, src, -1);
+    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
     return val;
 }
 
-target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
-        target_ulong csr, target_ulong rs1_pass)
+void helper_csrw(CPURISCVState *env, int csr, target_ulong src)
 {
-    target_ulong val = 0;
-    RISCVException ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
+    RISCVException ret = riscv_csrrw(env, csr, NULL, src, -1);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
     }
-    return val;
 }
 
-target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
-        target_ulong csr, target_ulong rs1_pass)
+target_ulong helper_csrrw(CPURISCVState *env, int csr,
+                          target_ulong src, target_ulong write_mask)
 {
     target_ulong val = 0;
-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
+    RISCVException ret = riscv_csrrw(env, csr, &val, src, write_mask);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
     return true;
 }
 
-#define RISCV_OP_CSR_PRE do {\
-    source1 = tcg_temp_new(); \
-    csr_store = tcg_temp_new(); \
-    dest = tcg_temp_new(); \
-    rs1_pass = tcg_temp_new(); \
-    gen_get_gpr(ctx, source1, a->rs1); \
-    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); \
-    tcg_gen_movi_tl(rs1_pass, a->rs1); \
-    tcg_gen_movi_tl(csr_store, a->csr); \
-    gen_io_start();\
-} while (0)
-
-#define RISCV_OP_CSR_POST do {\
-    gen_set_gpr(ctx, a->rd, dest); \
-    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
-    exit_tb(ctx); \
-    ctx->base.is_jmp = DISAS_NORETURN; \
-    tcg_temp_free(source1); \
-    tcg_temp_free(csr_store); \
-    tcg_temp_free(dest); \
-    tcg_temp_free(rs1_pass); \
-} while (0)
+static bool do_csr_post(DisasContext *ctx)
+{
+    /* We may have changed important cpu state -- exit to main loop. */
+    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+    exit_tb(ctx);
+    ctx->base.is_jmp = DISAS_NORETURN;
+    return true;
+}
+
+static bool do_csrr(DisasContext *ctx, int rd, int rc)
+{
+    TCGv dest = dest_gpr(ctx, rd);
+    TCGv_i32 csr = tcg_constant_i32(rc);
+
+    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+        gen_io_start();
+    }
+    gen_helper_csrr(dest, cpu_env, csr);
+    gen_set_gpr(ctx, rd, dest);
+    return do_csr_post(ctx);
+}
+
+static bool do_csrw(DisasContext *ctx, int rc, TCGv src)
+{
+    TCGv_i32 csr = tcg_constant_i32(rc);
 
+    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+        gen_io_start();
+    }
+    gen_helper_csrw(cpu_env, csr, src);
+    return do_csr_post(ctx);
+}
+
+static bool do_csrrw(DisasContext *ctx, int rd, int rc, TCGv src, TCGv mask)
+{
+    TCGv dest = dest_gpr(ctx, rd);
+    TCGv_i32 csr = tcg_constant_i32(rc);
+
+    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+        gen_io_start();
+    }
+    gen_helper_csrrw(dest, cpu_env, csr, src, mask);
+    gen_set_gpr(ctx, rd, dest);
+    return do_csr_post(ctx);
+}
 
 static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
 {
-    TCGv source1, csr_store, dest, rs1_pass;
-    RISCV_OP_CSR_PRE;
-    gen_helper_csrrw(dest, cpu_env, source1, csr_store);
-    RISCV_OP_CSR_POST;
-    return true;
+    TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
+
+    /*
+     * If rd == 0, the insn shall not read the csr, nor cause any of the
+     * side effects that might occur on a csr read.
+     */
+    if (a->rd == 0) {
+        return do_csrw(ctx, a->csr, src);
+    }
+
+    TCGv mask = tcg_constant_tl(-1);
+    return do_csrrw(ctx, a->rd, a->csr, src, mask);
 }
 
 static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
 {
-    TCGv source1, csr_store, dest, rs1_pass;
-    RISCV_OP_CSR_PRE;
-    gen_helper_csrrs(dest, cpu_env, source1, csr_store, rs1_pass);
-    RISCV_OP_CSR_POST;
-    return true;
+    /*
+     * If rs1 == 0, the insn shall not write to the csr at all, nor
+     * cause any of the side effects that might occur on a csr write.
+     * Note that if rs1 specifies a register other than x0, holding
+     * a zero value, the instruction will still attempt to write the
+     * unmodified value back to the csr and will cause side effects.
+     */
+    if (a->rs1 == 0) {
+        return do_csrr(ctx, a->rd, a->csr);
+    }
+
+    TCGv ones = tcg_constant_tl(-1);
+    TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
+    return do_csrrw(ctx, a->rd, a->csr, ones, mask);
 }
 
 static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
 {
-    TCGv source1, csr_store, dest, rs1_pass;
-    RISCV_OP_CSR_PRE;
-    gen_helper_csrrc(dest, cpu_env, source1, csr_store, rs1_pass);
-    RISCV_OP_CSR_POST;
-    return true;
+    /*
+     * If rs1 == 0, the insn shall not write to the csr at all, nor
+     * cause any of the side effects that might occur on a csr write.
+     * Note that if rs1 specifies a register other than x0, holding
+     * a zero value, the instruction will still attempt to write the
+     * unmodified value back to the csr and will cause side effects.
+     */
+    if (a->rs1 == 0) {
+        return do_csrr(ctx, a->rd, a->csr);
+    }
+
+    TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
+    return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
 }
 
 static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
 {
-    TCGv source1, csr_store, dest, rs1_pass;
-    RISCV_OP_CSR_PRE;
-    gen_helper_csrrw(dest, cpu_env, rs1_pass, csr_store);
-    RISCV_OP_CSR_POST;
-    return true;
+    TCGv src = tcg_constant_tl(a->rs1);
+
+    /*
+     * If rd == 0, the insn shall not read the csr, nor cause any of the
+     * side effects that might occur on a csr read.
+     */
+    if (a->rd == 0) {
+        return do_csrw(ctx, a->csr, src);
+    }
+
+    TCGv mask = tcg_constant_tl(-1);
+    return do_csrrw(ctx, a->rd, a->csr, src, mask);
 }
 
 static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
 {
-    TCGv source1, csr_store, dest, rs1_pass;
-    RISCV_OP_CSR_PRE;
-    gen_helper_csrrs(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
-    RISCV_OP_CSR_POST;
-    return true;
+    /*
+     * If rs1 == 0, the insn shall not write to the csr at all, nor
+     * cause any of the side effects that might occur on a csr write.
+     * Note that if rs1 specifies a register other than x0, holding
+     * a zero value, the instruction will still attempt to write the
+     * unmodified value back to the csr and will cause side effects.
+     */
+    if (a->rs1 == 0) {
+        return do_csrr(ctx, a->rd, a->csr);
+    }
+
+    TCGv ones = tcg_constant_tl(-1);
+    TCGv mask = tcg_constant_tl(a->rs1);
+    return do_csrrw(ctx, a->rd, a->csr, ones, mask);
 }
 
 static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
 {
-    TCGv source1, csr_store, dest, rs1_pass;
-    RISCV_OP_CSR_PRE;
-    gen_helper_csrrc(dest, cpu_env, rs1_pass, csr_store, rs1_pass);
-    RISCV_OP_CSR_POST;
-    return true;
+    /*
+     * If rs1 == 0, the insn shall not write to the csr at all, nor
+     * cause any of the side effects that might occur on a csr write.
+     * Note that if rs1 specifies a register other than x0, holding
+     * a zero value, the instruction will still attempt to write the
+     * unmodified value back to the csr and will cause side effects.
+     */
+    if (a->rs1 == 0) {
+        return do_csrr(ctx, a->rd, a->csr);
+    }
+
+    TCGv mask = tcg_constant_tl(a->rs1);
+    return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
 }
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-20-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rva.c.inc | 47 ++++++++++---------------
 1 file changed, 19 insertions(+), 28 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
+static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
 {
-    TCGv src1 = tcg_temp_new();
-    /* Put addr in load_res, data in load_val.  */
-    gen_get_gpr(ctx, src1, a->rs1);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
+
     if (a->rl) {
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
     }
@@ -XXX,XX +XXX,XX @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
     if (a->aq) {
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
     }
+
+    /* Put addr in load_res, data in load_val.  */
     tcg_gen_mov_tl(load_res, src1);
     gen_set_gpr(ctx, a->rd, load_val);
 
-    tcg_temp_free(src1);
     return true;
 }
 
-static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
+static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
 {
-    TCGv src1 = tcg_temp_new();
-    TCGv src2 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
+    TCGv dest, src1, src2;
     TCGLabel *l1 = gen_new_label();
     TCGLabel *l2 = gen_new_label();
 
-    gen_get_gpr(ctx, src1, a->rs1);
+    src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
     tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
 
-    gen_get_gpr(ctx, src2, a->rs2);
     /*
      * Note that the TCG atomic primitives are SC,
      * so we can ignore AQ/RL along this path.
      */
-    tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
+    dest = dest_gpr(ctx, a->rd);
+    src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+    tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2,
                               ctx->mem_idx, mop);
-    tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
-    gen_set_gpr(ctx, a->rd, dat);
+    tcg_gen_setcond_tl(TCG_COND_NE, dest, dest, load_val);
+    gen_set_gpr(ctx, a->rd, dest);
     tcg_gen_br(l2);
 
     gen_set_label(l1);
@@ -XXX,XX +XXX,XX @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
      * provide the memory barrier implied by AQ/RL.
      */
     tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
-    tcg_gen_movi_tl(dat, 1);
-    gen_set_gpr(ctx, a->rd, dat);
+    gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
 
     gen_set_label(l2);
     /*
@@ -XXX,XX +XXX,XX @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
      */
     tcg_gen_movi_tl(load_res, -1);
 
-    tcg_temp_free(dat);
-    tcg_temp_free(src1);
-    tcg_temp_free(src2);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
                     void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
                     MemOp mop)
 {
-    TCGv src1 = tcg_temp_new();
-    TCGv src2 = tcg_temp_new();
-
-    gen_get_gpr(ctx, src1, a->rs1);
-    gen_get_gpr(ctx, src2, a->rs2);
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
 
-    (*func)(src2, src1, src2, ctx->mem_idx, mop);
+    func(dest, src1, src2, ctx->mem_idx, mop);
 
-    gen_set_gpr(ctx, a->rd, src2);
-    tcg_temp_free(src1);
-    tcg_temp_free(src2);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Always use tcg_gen_deposit_z_tl; the special case for
shamt >= 32 is handled there.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-21-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 19 ++++++-------------
 1 file changed, 6 insertions(+), 13 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
     return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
 }
 
+static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
+{
+    tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
+}
+
 static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
-
-    TCGv source1 = tcg_temp_new();
-    gen_get_gpr(ctx, source1, a->rs1);
-
-    if (a->shamt < 32) {
-        tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
-    } else {
-        tcg_gen_shli_tl(source1, source1, a->shamt);
-    }
-
-    gen_set_gpr(ctx, a->rd, source1);
-    tcg_temp_free(source1);
-    return true;
+    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
 }
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-22-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvf.c.inc | 146 ++++++++++++------------
 1 file changed, 70 insertions(+), 76 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -XXX,XX +XXX,XX @@
 
 static bool trans_flw(DisasContext *ctx, arg_flw *a)
 {
+    TCGv_i64 dest;
+    TCGv addr;
+
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
-    tcg_gen_addi_tl(t0, t0, a->imm);
 
-    tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
-    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
+    addr = get_gpr(ctx, a->rs1, EXT_NONE);
+    if (a->imm) {
+        TCGv temp = temp_new(ctx);
+        tcg_gen_addi_tl(temp, addr, a->imm);
+        addr = temp;
+    }
+
+    dest = cpu_fpr[a->rd];
+    tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
+    gen_nanbox_s(dest, dest);
 
-    tcg_temp_free(t0);
     mark_fs_dirty(ctx);
     return true;
 }
 
 static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
 {
+    TCGv addr;
+
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
 
-    tcg_gen_addi_tl(t0, t0, a->imm);
+    addr = get_gpr(ctx, a->rs1, EXT_NONE);
+    if (a->imm) {
+        TCGv temp = tcg_temp_new();
+        tcg_gen_addi_tl(temp, addr, a->imm);
+        addr = temp;
+    }
 
-    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
+    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
 
-    tcg_temp_free(t0);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    TCGv t0 = tcg_temp_new();
-    gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+    TCGv dest = dest_gpr(ctx, a->rd);
 
+    gen_set_rm(ctx, a->rm);
+    gen_helper_fcvt_w_s(dest, cpu_env, cpu_fpr[a->rs1]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    TCGv t0 = tcg_temp_new();
-    gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+    TCGv dest = dest_gpr(ctx, a->rd);
 
+    gen_set_rm(ctx, a->rm);
+    gen_helper_fcvt_wu_s(dest, cpu_env, cpu_fpr[a->rs1]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    TCGv t0 = tcg_temp_new();
+    TCGv dest = dest_gpr(ctx, a->rd);
 
 #if defined(TARGET_RISCV64)
-    tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
+    tcg_gen_ext32s_tl(dest, cpu_fpr[a->rs1]);
 #else
-    tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
+    tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]);
 #endif
 
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
-
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
 {
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
-    TCGv t0 = tcg_temp_new();
-    gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+
+    TCGv dest = dest_gpr(ctx, a->rd);
+
+    gen_helper_feq_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
 {
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
-    TCGv t0 = tcg_temp_new();
-    gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+
+    TCGv dest = dest_gpr(ctx, a->rd);
+
+    gen_helper_flt_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
 {
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
-    TCGv t0 = tcg_temp_new();
-    gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+
+    TCGv dest = dest_gpr(ctx, a->rd);
+
+    gen_helper_fle_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    TCGv t0 = tcg_temp_new();
-
-    gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
-
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+    TCGv dest = dest_gpr(ctx, a->rd);
 
+    gen_helper_fclass_s(dest, cpu_fpr[a->rs1]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
+    TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
 
     gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
+    gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, src);
 
     mark_fs_dirty(ctx);
-    tcg_temp_free(t0);
-
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
+    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
 
     gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
+    gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, src);
 
     mark_fs_dirty(ctx);
-    tcg_temp_free(t0);
-
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
+    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
 
-    tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
+    tcg_gen_extu_tl_i64(cpu_fpr[a->rd], src);
     gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
 
     mark_fs_dirty(ctx);
-    tcg_temp_free(t0);
-
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    TCGv t0 = tcg_temp_new();
+    TCGv dest = dest_gpr(ctx, a->rd);
+
     gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+    gen_helper_fcvt_l_s(dest, cpu_env, cpu_fpr[a->rs1]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    TCGv t0 = tcg_temp_new();
+    TCGv dest = dest_gpr(ctx, a->rd);
+
     gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+    gen_helper_fcvt_lu_s(dest, cpu_env, cpu_fpr[a->rs1]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
+    TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
 
     gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+    gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, src);
 
     mark_fs_dirty(ctx);
-    tcg_temp_free(t0);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
+    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
 
     gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+    gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, src);
 
     mark_fs_dirty(ctx);
-    tcg_temp_free(t0);
     return true;
 }
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-23-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvd.c.inc | 125 ++++++++++++------------
 1 file changed, 60 insertions(+), 65 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -XXX,XX +XXX,XX @@
 
 static bool trans_fld(DisasContext *ctx, arg_fld *a)
 {
+    TCGv addr;
+
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
-    tcg_gen_addi_tl(t0, t0, a->imm);
 
-    tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
+    addr = get_gpr(ctx, a->rs1, EXT_NONE);
+    if (a->imm) {
+        TCGv temp = temp_new(ctx);
+        tcg_gen_addi_tl(temp, addr, a->imm);
+        addr = temp;
+    }
+
+    tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ);
 
     mark_fs_dirty(ctx);
-    tcg_temp_free(t0);
     return true;
 }
 
 static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
 {
+    TCGv addr;
+
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
-    tcg_gen_addi_tl(t0, t0, a->imm);
 
-    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
+    addr = get_gpr(ctx, a->rs1, EXT_NONE);
+    if (a->imm) {
+        TCGv temp = temp_new(ctx);
+        tcg_gen_addi_tl(temp, addr, a->imm);
+        addr = temp;
+    }
+
+    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ);
 
-    tcg_temp_free(t0);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    TCGv t0 = tcg_temp_new();
-    gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+    TCGv dest = dest_gpr(ctx, a->rd);
 
+    gen_helper_feq_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    TCGv t0 = tcg_temp_new();
-    gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+    TCGv dest = dest_gpr(ctx, a->rd);
 
+    gen_helper_flt_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    TCGv t0 = tcg_temp_new();
-    gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+    TCGv dest = dest_gpr(ctx, a->rd);
 
+    gen_helper_fle_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    TCGv t0 = tcg_temp_new();
-    gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+    TCGv dest = dest_gpr(ctx, a->rd);
+
+    gen_helper_fclass_d(dest, cpu_fpr[a->rs1]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    TCGv t0 = tcg_temp_new();
-    gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+    TCGv dest = dest_gpr(ctx, a->rd);
 
+    gen_set_rm(ctx, a->rm);
+    gen_helper_fcvt_w_d(dest, cpu_env, cpu_fpr[a->rs1]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    TCGv t0 = tcg_temp_new();
-    gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+    TCGv dest = dest_gpr(ctx, a->rd);
 
+    gen_set_rm(ctx, a->rm);
+    gen_helper_fcvt_wu_d(dest, cpu_env, cpu_fpr[a->rs1]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
+    TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
 
     gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
-    tcg_temp_free(t0);
+    gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, src);
 
     mark_fs_dirty(ctx);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
+    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
 
     gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
-    tcg_temp_free(t0);
+    gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, src);
 
     mark_fs_dirty(ctx);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    TCGv t0 = tcg_temp_new();
+    TCGv dest = dest_gpr(ctx, a->rd);
+
     gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+    gen_helper_fcvt_l_d(dest, cpu_env, cpu_fpr[a->rs1]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt_lu_d *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    TCGv t0 = tcg_temp_new();
+    TCGv dest = dest_gpr(ctx, a->rd);
+
     gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(ctx, a->rd, t0);
-    tcg_temp_free(t0);
+    gen_helper_fcvt_lu_d(dest, cpu_env, cpu_fpr[a->rs1]);
+    gen_set_gpr(ctx, a->rd, dest);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_d_l *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
+    TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
 
     gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
-    tcg_temp_free(t0);
+    gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, src);
+
     mark_fs_dirty(ctx);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt_d_lu *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
+    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
 
     gen_set_rm(ctx, a->rm);
-    gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
-    tcg_temp_free(t0);
+    gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, src);
+
     mark_fs_dirty(ctx);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
     REQUIRE_EXT(ctx, RVD);
 
 #ifdef TARGET_RISCV64
-    TCGv t0 = tcg_temp_new();
-    gen_get_gpr(ctx, t0, a->rs1);
-
-    tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
-    tcg_temp_free(t0);
+    tcg_gen_mov_tl(cpu_fpr[a->rd], get_gpr(ctx, a->rs1, EXT_NONE));
     mark_fs_dirty(ctx);
     return true;
 #else
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Exit early if check_access fails.
Split out do_hlv, do_hsv, do_hlvx subroutines.
Use dest_gpr, get_gpr in the new subroutines.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-24-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode              |   1 +
 target/riscv/insn_trans/trans_rvh.c.inc | 266 +++++-------------------
 2 files changed, 57 insertions(+), 210 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@
 &j    imm rd
 &r    rd rs1 rs2
 &r2   rd rs1
+&r2_s rs1 rs2
 &s    imm rs1 rs2
 &u    imm rd
 &shift     shamt rs1 rd
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -XXX,XX +XXX,XX @@
  */
 
 #ifndef CONFIG_USER_ONLY
-static void check_access(DisasContext *ctx) {
+static bool check_access(DisasContext *ctx)
+{
     if (!ctx->hlsx) {
         if (ctx->virt_enabled) {
             generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
         } else {
             generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
         }
+        return false;
     }
+    return true;
 }
 #endif
 
-static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
+static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop)
 {
-    REQUIRE_EXT(ctx, RVH);
-#ifndef CONFIG_USER_ONLY
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-
-    check_access(ctx);
-
-    gen_get_gpr(ctx, t0, a->rs1);
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_SB);
-    gen_set_gpr(ctx, a->rd, t1);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-    return true;
-#else
+#ifdef CONFIG_USER_ONLY
     return false;
+#else
+    if (check_access(ctx)) {
+        TCGv dest = dest_gpr(ctx, a->rd);
+        TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+        int mem_idx = ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
+        tcg_gen_qemu_ld_tl(dest, addr, mem_idx, mop);
+        gen_set_gpr(ctx, a->rd, dest);
+    }
+    return true;
 #endif
 }
 
-static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
+static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
 {
     REQUIRE_EXT(ctx, RVH);
-#ifndef CONFIG_USER_ONLY
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-
-    check_access(ctx);
-
-    gen_get_gpr(ctx, t0, a->rs1);
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESW);
-    gen_set_gpr(ctx, a->rd, t1);
+    return do_hlv(ctx, a, MO_SB);
+}
 
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-    return true;
-#else
-    return false;
-#endif
+static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
+{
+    REQUIRE_EXT(ctx, RVH);
+    return do_hlv(ctx, a, MO_TESW);
 }
 
 static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a)
 {
     REQUIRE_EXT(ctx, RVH);
-#ifndef CONFIG_USER_ONLY
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-
-    check_access(ctx);
-
-    gen_get_gpr(ctx, t0, a->rs1);
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESL);
-    gen_set_gpr(ctx, a->rd, t1);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-    return true;
-#else
-    return false;
-#endif
+    return do_hlv(ctx, a, MO_TESL);
 }
 
 static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a)
 {
     REQUIRE_EXT(ctx, RVH);
-#ifndef CONFIG_USER_ONLY
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-
-    check_access(ctx);
-
-    gen_get_gpr(ctx, t0, a->rs1);
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_UB);
-    gen_set_gpr(ctx, a->rd, t1);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-    return true;
-#else
-    return false;
-#endif
+    return do_hlv(ctx, a, MO_UB);
 }
 
 static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a)
 {
     REQUIRE_EXT(ctx, RVH);
-#ifndef CONFIG_USER_ONLY
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-
-    check_access(ctx);
-
-    gen_get_gpr(ctx, t0, a->rs1);
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEUW);
-    gen_set_gpr(ctx, a->rd, t1);
+    return do_hlv(ctx, a, MO_TEUW);
+}
 
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-    return true;
-#else
+static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop)
+{
+#ifdef CONFIG_USER_ONLY
     return false;
+#else
+    if (check_access(ctx)) {
+        TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+        TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
+        int mem_idx = ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK;
+        tcg_gen_qemu_st_tl(data, addr, mem_idx, mop);
+    }
+    return true;
 #endif
 }
 
 static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a)
 {
     REQUIRE_EXT(ctx, RVH);
-#ifndef CONFIG_USER_ONLY
-    TCGv t0 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
-
-    check_access(ctx);
-
-    gen_get_gpr(ctx, t0, a->rs1);
-    gen_get_gpr(ctx, dat, a->rs2);
-
-    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_SB);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(dat);
-    return true;
-#else
-    return false;
-#endif
+    return do_hsv(ctx, a, MO_SB);
 }
 
 static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a)
 {
     REQUIRE_EXT(ctx, RVH);
-#ifndef CONFIG_USER_ONLY
-    TCGv t0 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
-
-    check_access(ctx);
-
-    gen_get_gpr(ctx, t0, a->rs1);
-    gen_get_gpr(ctx, dat, a->rs2);
-
-    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESW);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(dat);
-    return true;
-#else
-    return false;
-#endif
+    return do_hsv(ctx, a, MO_TESW);
 }
 
 static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
 {
     REQUIRE_EXT(ctx, RVH);
-#ifndef CONFIG_USER_ONLY
-    TCGv t0 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
-
-    check_access(ctx);
-
-    gen_get_gpr(ctx, t0, a->rs1);
-    gen_get_gpr(ctx, dat, a->rs2);
-
-    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESL);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(dat);
-    return true;
-#else
-    return false;
-#endif
+    return do_hsv(ctx, a, MO_TESL);
 }
 
 static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVH);
-
-#ifndef CONFIG_USER_ONLY
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-
-    check_access(ctx);
-
-    gen_get_gpr(ctx, t0, a->rs1);
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEUL);
-    gen_set_gpr(ctx, a->rd, t1);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-    return true;
-#else
-    return false;
-#endif
+    return do_hlv(ctx, a, MO_TEUL);
 }
 
 static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVH);
-
-#ifndef CONFIG_USER_ONLY
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-
-    check_access(ctx);
-
-    gen_get_gpr(ctx, t0, a->rs1);
-
-    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEQ);
-    gen_set_gpr(ctx, a->rd, t1);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-    return true;
-#else
-    return false;
-#endif
+    return do_hlv(ctx, a, MO_TEQ);
 }
 
 static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVH);
+    return do_hsv(ctx, a, MO_TEQ);
+}
 
 #ifndef CONFIG_USER_ONLY
-    TCGv t0 = tcg_temp_new();
-    TCGv dat = tcg_temp_new();
-
-    check_access(ctx);
-
-    gen_get_gpr(ctx, t0, a->rs1);
-    gen_get_gpr(ctx, dat, a->rs2);
-
-    tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEQ);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(dat);
+static bool do_hlvx(DisasContext *ctx, arg_r2 *a,
+                    void (*func)(TCGv, TCGv_env, TCGv))
+{
+    if (check_access(ctx)) {
+        TCGv dest = dest_gpr(ctx, a->rd);
+        TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
+        func(dest, cpu_env, addr);
+        gen_set_gpr(ctx, a->rd, dest);
+    }
     return true;
-#else
-    return false;
-#endif
 }
+#endif
 
 static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
 {
     REQUIRE_EXT(ctx, RVH);
 #ifndef CONFIG_USER_ONLY
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-
-    check_access(ctx);
-
-    gen_get_gpr(ctx, t0, a->rs1);
-
-    gen_helper_hyp_hlvx_hu(t1, cpu_env, t0);
-    gen_set_gpr(ctx, a->rd, t1);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-    return true;
+    return do_hlvx(ctx, a, gen_helper_hyp_hlvx_hu);
 #else
     return false;
 #endif
@@ -XXX,XX +XXX,XX @@ static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a)
 {
     REQUIRE_EXT(ctx, RVH);
 #ifndef CONFIG_USER_ONLY
-    TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
-
-    check_access(ctx);
-
-    gen_get_gpr(ctx, t0, a->rs1);
-
-    gen_helper_hyp_hlvx_wu(t1, cpu_env, t0);
-    gen_set_gpr(ctx, a->rd, t1);
-
-    tcg_temp_free(t0);
-    tcg_temp_free(t1);
-    return true;
+    return do_hlvx(ctx, a, gen_helper_hyp_hlvx_wu);
 #else
     return false;
 #endif
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Remove gen_get_gpr, as the function becomes unused.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-25-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 13 ++---
 target/riscv/insn_trans/trans_rvv.c.inc | 74 +++++++------------------
 2 files changed, 26 insertions(+), 61 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
     g_assert_not_reached();
 }
 
-static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num)
-{
-    tcg_gen_mov_tl(t, get_gpr(ctx, reg_num, EXT_NONE));
-}
-
 static TCGv dest_gpr(DisasContext *ctx, int reg_num)
 {
     if (reg_num == 0 || ctx->w) {
@@ -XXX,XX +XXX,XX @@ void riscv_translate_init(void)
 {
     int i;
 
-    /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */
-    /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
-    /* registers, unless you specifically block reads/writes to reg 0 */
+    /*
+     * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
+     * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
+     * unless you specifically block reads/writes to reg 0.
+     */
     cpu_gpr[0] = NULL;
 
     for (i = 1; i < 32; i++) {
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
         return false;
     }
 
-    s2 = tcg_temp_new();
-    dst = tcg_temp_new();
+    s2 = get_gpr(ctx, a->rs2, EXT_ZERO);
+    dst = dest_gpr(ctx, a->rd);
 
     /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
     if (a->rs1 == 0) {
         /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
         s1 = tcg_constant_tl(RV_VLEN_MAX);
     } else {
-        s1 = tcg_temp_new();
-        gen_get_gpr(ctx, s1, a->rs1);
+        s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
     }
-    gen_get_gpr(ctx, s2, a->rs2);
     gen_helper_vsetvl(dst, cpu_env, s1, s2);
     gen_set_gpr(ctx, a->rd, dst);
+
     tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
     lookup_and_goto_ptr(ctx);
     ctx->base.is_jmp = DISAS_NORETURN;
-
-    tcg_temp_free(s1);
-    tcg_temp_free(s2);
-    tcg_temp_free(dst);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
     }
 
     s2 = tcg_constant_tl(a->zimm);
-    dst = tcg_temp_new();
+    dst = dest_gpr(ctx, a->rd);
 
     /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
     if (a->rs1 == 0) {
         /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
         s1 = tcg_constant_tl(RV_VLEN_MAX);
     } else {
-        s1 = tcg_temp_new();
-        gen_get_gpr(ctx, s1, a->rs1);
+        s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
     }
     gen_helper_vsetvl(dst, cpu_env, s1, s2);
     gen_set_gpr(ctx, a->rd, dst);
+
     gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
     ctx->base.is_jmp = DISAS_NORETURN;
-
-    tcg_temp_free(s1);
-    tcg_temp_free(dst);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
 
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
-    base = tcg_temp_new();
+    base = get_gpr(s, rs1, EXT_NONE);
 
     /*
      * As simd_desc supports at most 256 bytes, and in this implementation,
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
      */
     desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
-    gen_get_gpr(s, base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
 
@@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
 
     tcg_temp_free_ptr(dest);
     tcg_temp_free_ptr(mask);
-    tcg_temp_free(base);
     gen_set_label(over);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
 
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
-    base = tcg_temp_new();
-    stride = tcg_temp_new();
+    base = get_gpr(s, rs1, EXT_NONE);
+    stride = get_gpr(s, rs2, EXT_NONE);
     desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
-    gen_get_gpr(s, base, rs1);
-    gen_get_gpr(s, stride, rs2);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
 
@@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
 
     tcg_temp_free_ptr(dest);
     tcg_temp_free_ptr(mask);
-    tcg_temp_free(base);
-    tcg_temp_free(stride);
     gen_set_label(over);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
     index = tcg_temp_new_ptr();
-    base = tcg_temp_new();
+    base = get_gpr(s, rs1, EXT_NONE);
     desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
-    gen_get_gpr(s, base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
     tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     tcg_temp_free_ptr(dest);
     tcg_temp_free_ptr(mask);
     tcg_temp_free_ptr(index);
-    tcg_temp_free(base);
     gen_set_label(over);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
 
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
-    base = tcg_temp_new();
+    base = get_gpr(s, rs1, EXT_NONE);
     desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
-    gen_get_gpr(s, base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
 
@@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
 
     tcg_temp_free_ptr(dest);
     tcg_temp_free_ptr(mask);
-    tcg_temp_free(base);
     gen_set_label(over);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
     index = tcg_temp_new_ptr();
-    base = tcg_temp_new();
+    base = get_gpr(s, rs1, EXT_NONE);
     desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
-    gen_get_gpr(s, base, rs1);
     tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
     tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
     tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -XXX,XX +XXX,XX @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
     tcg_temp_free_ptr(dest);
     tcg_temp_free_ptr(mask);
     tcg_temp_free_ptr(index);
-    tcg_temp_free(base);
     gen_set_label(over);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
     dest = tcg_temp_new_ptr();
     mask = tcg_temp_new_ptr();
     src2 = tcg_temp_new_ptr();
-    src1 = tcg_temp_new();
-    gen_get_gpr(s, src1, rs1);
+    src1 = get_gpr(s, rs1, EXT_NONE);
 
     data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
     data = FIELD_DP32(data, VDATA, VM, vm);
@@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
     tcg_temp_free_ptr(dest);
     tcg_temp_free_ptr(mask);
     tcg_temp_free_ptr(src2);
-    tcg_temp_free(src1);
     gen_set_label(over);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
 
     if (a->vm && s->vl_eq_vlmax) {
         TCGv_i64 src1 = tcg_temp_new_i64();
-        TCGv tmp = tcg_temp_new();
 
-        gen_get_gpr(s, tmp, a->rs1);
-        tcg_gen_ext_tl_i64(src1, tmp);
+        tcg_gen_ext_tl_i64(src1, get_gpr(s, a->rs1, EXT_SIGN));
         gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
                 src1, MAXSZ(s), MAXSZ(s));
 
         tcg_temp_free_i64(src1);
-        tcg_temp_free(tmp);
         return true;
     }
     return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
@@ -XXX,XX +XXX,XX @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
 
     if (a->vm && s->vl_eq_vlmax) {
         TCGv_i32 src1 = tcg_temp_new_i32();
-        TCGv tmp = tcg_temp_new();
 
-        gen_get_gpr(s, tmp, a->rs1);
-        tcg_gen_trunc_tl_i32(src1, tmp);
+        tcg_gen_trunc_tl_i32(src1, get_gpr(s, a->rs1, EXT_NONE));
         tcg_gen_extract_i32(src1, src1, 0, s->sew + 3);
         gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
                 src1, MAXSZ(s), MAXSZ(s));
 
         tcg_temp_free_i32(src1);
-        tcg_temp_free(tmp);
         return true;
     }
     return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
         TCGLabel *over = gen_new_label();
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 
-        s1 = tcg_temp_new();
-        gen_get_gpr(s, s1, a->rs1);
+        s1 = get_gpr(s, a->rs1, EXT_SIGN);
 
         if (s->vl_eq_vlmax) {
             tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
             tcg_temp_free_i64(s1_i64);
         }
 
-        tcg_temp_free(s1);
         gen_set_label(over);
         return true;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
 
         mask = tcg_temp_new_ptr();
         src2 = tcg_temp_new_ptr();
-        dst = tcg_temp_new();
+        dst = dest_gpr(s, a->rd);
         desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
         tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
@@ -XXX,XX +XXX,XX @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
 
         tcg_temp_free_ptr(mask);
         tcg_temp_free_ptr(src2);
-        tcg_temp_free(dst);
         return true;
     }
     return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
 
         mask = tcg_temp_new_ptr();
         src2 = tcg_temp_new_ptr();
-        dst = tcg_temp_new();
+        dst = dest_gpr(s, a->rd);
         desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
 
         tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
@@ -XXX,XX +XXX,XX @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
 
         tcg_temp_free_ptr(mask);
         tcg_temp_free_ptr(src2);
-        tcg_temp_free(dst);
         return true;
     }
     return false;
@@ -XXX,XX +XXX,XX @@ static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
 static bool trans_vext_x_v(DisasContext *s, arg_r *a)
 {
     TCGv_i64 tmp = tcg_temp_new_i64();
-    TCGv dest = tcg_temp_new();
+    TCGv dest = dest_gpr(s, a->rd);
 
     if (a->rs1 == 0) {
         /* Special case vmv.x.s rd, vs2. */
@@ -XXX,XX +XXX,XX @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a)
         int vlmax = s->vlen >> (3 + s->sew);
         vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
     }
+
     tcg_gen_trunc_i64_tl(dest, tmp);
     gen_set_gpr(s, a->rd, dest);
 
-    tcg_temp_free(dest);
     tcg_temp_free_i64(tmp);
     return true;
 }
-- 
2.31.1

The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:

Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528

for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:

target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

* APLICs add child earlier than realize
* Fix exposure of Zkr
* Raise exceptions on wrs.nto
* Implement SBI debug console (DBCN) calls for KVM
* Support 64-bit addresses for initrd
* Change RISCV_EXCP_SEMIHOST exception number to 63
* Tolerate KVM disable ext errors
* Set tval in breakpoints
* Add support for Zve32x extension
* Add support for Zve64x extension
* Relax vector register check in RISCV gdbstub
* Fix the element agnostic Vector function problem
* Fix Zvkb extension config
* Implement dynamic establishment of custom decoder
* Add th.sxstatus CSR emulation
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
* Check single width operator for vector fp widen instructions
* Check single width operator for vfncvt.rod.f.f.w
* Remove redudant SEW checking for vector fp narrow/widen instructions
* Prioritize pmp errors in raise_mmu_exception()
* Do not set mtval2 for non guest-page faults
* Remove experimental prefix from "B" extension
* Fixup CBO extension register calculation
* Fix the hart bit setting of AIA
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
* Decode all of the pmpcfg and pmpaddr CSRs
* Raise an exception when CSRRS/CSRRC writes a read-only CSR

----------------------------------------------------------------
Alexei Filippov (1):
      target/riscv: do not set mtval2 for non guest-page faults

Alistair Francis (2):
      target/riscv: rvzicbo: Fixup CBO extension register calculation
      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs

Andrew Jones (2):
      target/riscv/kvm: Fix exposure of Zkr
      target/riscv: Raise exceptions on wrs.nto

Cheng Yang (1):
      hw/riscv/boot.c: Support 64-bit address for initrd

Christoph Müllner (1):
      riscv: thead: Add th.sxstatus CSR emulation

Clément Léger (1):
      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

Daniel Henrique Barboza (6):
      target/riscv/kvm: implement SBI debug console (DBCN) calls
      target/riscv/kvm: tolerate KVM disable ext errors
      target/riscv/debug: set tval=pc in breakpoint exceptions
      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
      target/riscv: prioritize pmp errors in raise_mmu_exception()
      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Huang Tao (2):
      target/riscv: Fix the element agnostic function problem
      target/riscv: Implement dynamic establishment of custom decoder

Jason Chien (3):
      target/riscv: Add support for Zve32x extension
      target/riscv: Add support for Zve64x extension
      target/riscv: Relax vector register check in RISCV gdbstub

Max Chou (4):
      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
      target/riscv: rvv: Check single width operator for vector fp widen instructions
      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions

Rob Bradford (1):
      target/riscv: Remove experimental prefix from "B" extension

Yangyu Chen (1):
      target/riscv/cpu.c: fix Zvkb extension config

Yong-Xuan Wang (1):
      target/riscv/kvm.c: Fix the hart bit setting of AIA

Yu-Ming Chang (1):
      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

yang.zhang (1):
      hw/intc/riscv_aplic: APLICs should add child earlier than realize

From: "yang.zhang" <yang.zhang@hexintek.com>

Since only root APLICs can have hw IRQ lines, aplic->parent should
be initialized first.

Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     qdev_prop_set_bit(dev, "msimode", msimode);
     qdev_prop_set_bit(dev, "mmode", mmode);
 
+    if (parent) {
+        riscv_aplic_add_child(parent, dev);
+    }
+
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
     if (!is_kvm_aia(msimode)) {
         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     }
 
-    if (parent) {
-        riscv_aplic_add_child(parent, dev);
-    }
-
     if (!msimode) {
         for (i = 0; i < num_harts; i++) {
             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

The Zkr extension may only be exposed to KVM guests if the VMM
implements the SEED CSR. Use the same implementation as TCG.

Without this patch, running with a KVM which does not forward the
SEED CSR access to QEMU will result in an ILL exception being
injected into the guest (this results in Linux guests crashing on
boot). And, when running with a KVM which does forward the access,
QEMU will crash, since QEMU doesn't know what to do with the exit.

Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 +++
 target/riscv/csr.c         | 18 ++++++++++++++----
 target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 3 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 
 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask);
+
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
 #endif
 
 /* Crypto Extension */
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-                               target_ulong *ret_value,
-                               target_ulong new_value,
-                               target_ulong write_mask)
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask)
 {
     uint16_t random_v;
     Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
         rval = random_v | SEED_OPST_ES16;
     }
 
+    return rval;
+}
+
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value,
+                               target_ulong write_mask)
+{
+    target_ulong rval;
+
+    rval = riscv_new_csr_seed(new_value, write_mask);
+
     if (ret_value) {
         *ret_value = rval;
     }
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
     return ret;
 }
 
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
+{
+    target_ulong csr_num = run->riscv_csr.csr_num;
+    target_ulong new_value = run->riscv_csr.new_value;
+    target_ulong write_mask = run->riscv_csr.write_mask;
+    int ret = 0;
+
+    switch (csr_num) {
+    case CSR_SEED:
+        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled CSR EXIT for CSR %lx\n",
+                      __func__, csr_num);
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
     case KVM_EXIT_RISCV_SBI:
         ret = kvm_riscv_handle_sbi(cs, run);
         break;
+    case KVM_EXIT_RISCV_CSR:
+        ret = kvm_riscv_handle_csr(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                       __func__, run->exit_reason);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

Implementing wrs.nto to always just return is consistent with the
specification, as the instruction is permitted to terminate the
stall for any reason, but it's not useful for virtualization, where
we'd like the guest to trap to the hypervisor in order to allow
scheduling of the lock holding VCPU. Change to always immediately
raise exceptions when the appropriate conditions are present,
otherwise continue to just return. Note, immediately raising
exceptions is also consistent with the specification since the
time limit that should expire prior to the exception is
implementation-specific.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                       |  1 +
 target/riscv/op_helper.c                    | 11 ++++++++
 target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
 3 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
+DEF_HELPER_1(wrs_nto, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 DEF_HELPER_1(tlb_flush_all, void, env)
 /* Native Debug */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
     }
 }
 
+void helper_wrs_nto(CPURISCVState *env)
+{
+    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
+        get_field(env->hstatus, HSTATUS_VTW) &&
+        !get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+}
+
 void helper_tlb_flush(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static bool trans_wrs(DisasContext *ctx)
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
 {
     if (!ctx->cfg_ptr->ext_zawrs) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
     return true;
 }
 
-#define GEN_TRANS_WRS(insn)                                     \
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
-{                                                               \
-    (void)a;                                                    \
-    return trans_wrs(ctx);                                      \
-}
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
+{
+    if (!ctx->cfg_ptr->ext_zawrs) {
+        return false;
+    }
 
-GEN_TRANS_WRS(wrs_nto)
-GEN_TRANS_WRS(wrs_sto)
+    /*
+     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
+     * should raise an exception when the implementation-specific bounded time
+     * limit has expired. Our time limit is zero, so we either return
+     * immediately, as does our implementation of wrs.sto, or raise an
+     * exception, as handled by the wrs.nto helper.
+     */
+#ifndef CONFIG_USER_ONLY
+    gen_helper_wrs_nto(tcg_env);
+#endif
+
+    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
+    return trans_wrs_sto(ctx, NULL);
+}
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

SBI defines a Debug Console extension "DBCN" that will, in time, replace
the legacy console putchar and getchar SBI extensions.

The appeal of the DBCN extension is that it allows multiple bytes to be
read/written in the SBI console in a single SBI call.

As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
module to userspace. But this will only happens if the KVM module
actually supports this SBI extension and we activate it.

We'll check for DBCN support during init time, checking if get-reg-list
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
kvm_set_one_reg() during kvm_arch_init_vcpu().

Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
SBI_EXT_DBCN, reading and writing as required.

A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
host, takes around 20 seconds to boot without using DBCN. With this
patch we're taking around 14 seconds to boot due to the speed-up in the
terminal output.  There's no change in boot time if the guest isn't
using earlycon.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/sbi_ecall_interface.h |  17 +++++
 target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
 2 files changed, 128 insertions(+)

diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/sbi_ecall_interface.h
+++ b/target/riscv/sbi_ecall_interface.h
@@ -XXX,XX +XXX,XX @@
 
 /* clang-format off */
 
+#define SBI_SUCCESS                      0
+#define SBI_ERR_FAILED                  -1
+#define SBI_ERR_NOT_SUPPORTED           -2
+#define SBI_ERR_INVALID_PARAM           -3
+#define SBI_ERR_DENIED                  -4
+#define SBI_ERR_INVALID_ADDRESS         -5
+#define SBI_ERR_ALREADY_AVAILABLE       -6
+#define SBI_ERR_ALREADY_STARTED         -7
+#define SBI_ERR_ALREADY_STOPPED         -8
+#define SBI_ERR_NO_SHMEM                -9
+
 /* SBI Extension IDs */
 #define SBI_EXT_0_1_SET_TIMER           0x0
 #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_IPI                     0x735049
 #define SBI_EXT_RFENCE                  0x52464E43
 #define SBI_EXT_HSM                     0x48534D
+#define SBI_EXT_DBCN                    0x4442434E
 
 /* SBI function IDs for BASE extension */
 #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_HSM_HART_STOP           0x1
 #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 
+/* SBI function IDs for DBCN extension */
+#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
+#define SBI_EXT_DBCN_CONSOLE_READ       0x1
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
+
 #define SBI_HSM_HART_STATUS_STARTED     0x0
 #define SBI_HSM_HART_STATUS_STOPPED     0x1
 #define SBI_HSM_HART_STATUS_START_PENDING   0x2
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
 };
 
+static KVMCPUConfig kvm_sbi_dbcn = {
+    .name = "sbi_dbcn",
+    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
+                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
+};
+
 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
 {
     CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
     return 0;
 }
 
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
+                                             KVMScratchCPU *kvmcpu,
+                                             struct kvm_reg_list *reglist)
+{
+    struct kvm_reg_list *reg_search;
+
+    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
+                         sizeof(uint64_t), uint64_cmp);
+
+    if (reg_search) {
+        kvm_sbi_dbcn.supported = true;
+    }
+}
+
 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                  struct kvm_reg_list *reglist)
 {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     if (riscv_has_ext(&cpu->env, RVV)) {
         kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
     }
+
+    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
 }
 
 static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
     return ret;
 }
 
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
+{
+    target_ulong reg = 1;
+
+    if (!kvm_sbi_dbcn.supported) {
+        return 0;
+    }
+
+    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
+}
+
 int kvm_arch_init_vcpu(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     kvm_riscv_update_cpu_misa_ext(cpu, cs);
     kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 
+    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
+{
+    g_autofree uint8_t *buf = NULL;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    target_ulong num_bytes;
+    uint64_t addr;
+    unsigned char ch;
+    int ret;
+
+    switch (run->riscv_sbi.function_id) {
+    case SBI_EXT_DBCN_CONSOLE_READ:
+    case SBI_EXT_DBCN_CONSOLE_WRITE:
+        num_bytes = run->riscv_sbi.args[0];
+
+        if (num_bytes == 0) {
+            run->riscv_sbi.ret[0] = SBI_SUCCESS;
+            run->riscv_sbi.ret[1] = 0;
+            break;
+        }
+
+        addr = run->riscv_sbi.args[1];
+
+        /*
+         * Handle the case where a 32 bit CPU is running in a
+         * 64 bit addressing env.
+         */
+        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
+            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
+        }
+
+        buf = g_malloc0(num_bytes);
+
+        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
+            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
+                             "reading chardev");
+                exit(1);
+            }
+
+            cpu_physical_memory_write(addr, buf, ret);
+        } else {
+            cpu_physical_memory_read(addr, buf, num_bytes);
+
+            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
+                             "writing chardev");
+                exit(1);
+            }
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = ret;
+        break;
+    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
+        ch = run->riscv_sbi.args[0];
+        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+
+        if (ret < 0) {
+            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
+                         "writing chardev");
+            exit(1);
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = 0;
+        break;
+    default:
+        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
+    }
+}
+
 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
         }
         ret = 0;
         break;
+    case SBI_EXT_DBCN:
+        kvm_riscv_handle_sbi_dbcn(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP,
                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
-- 
2.45.1

From: Cheng Yang <yangcheng.work@foxmail.com>

Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
     if (fdt) {
         end = start + size;
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
     }
 }
 
-- 
2.45.1

From: Clément Léger <cleger@rivosinc.com>

The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.

Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
-    RISCV_EXCP_SEMIHOST = 0x10,
     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+    RISCV_EXCP_SEMIHOST = 0x3f,
 } RISCVException;
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
enabled, will fail with a kernel oops SIGILL right at the start. The
reason is that we can't expose zkr without implementing the SEED CSR.
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
allow it we'll error out and never boot.

In hindsight this is too strict. If we keep proceeding, despite not
disabling the extension in the KVM vcpu, we'll not add the extension in
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
it's ok to keep booting in this case.

Change our current logic to not error out if we fail to disable an
extension in kvm_set_one_reg(), but show a warning and keep booting. It
is important to throw a warning because we must make the user aware that
the extension is still available in the vcpu, meaning that an
ill-behaved guest can ignore the riscv,isa settings and  use the
extension.

The case we're handling happens with an EINVAL error code. If we fail to
disable the extension in KVM for any other reason, error out.

We'll also keep erroring out when we fail to enable an extension in KVM,
since adding the extension in riscv,isa at this point will cause a guest
malfunction because the extension isn't enabled in the vcpu.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
         ret = kvm_set_one_reg(cs, id, &reg);
         if (ret != 0) {
-            error_report("Unable to %s extension %s in KVM, error %d",
-                         reg ? "enable" : "disable",
-                         multi_ext_cfg->name, ret);
-            exit(EXIT_FAILURE);
+            if (!reg && ret == -EINVAL) {
+                warn_report("KVM cannot disable extension %s",
+                            multi_ext_cfg->name);
+            } else {
+                error_report("Unable to enable extension %s in KVM, error %d",
+                             multi_ext_cfg->name, ret);
+                exit(EXIT_FAILURE);
+            }
         }
     }
 }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":

"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the tval CSR with either
zero or the faulting virtual address. The faulting virtual address for
an mcontrol6 trigger with action = 0 is the address being accessed and
which caused that trigger to fire."

A similar text is also found in the Debug spec section 5.7.11 w.r.t.
mcontrol.

Note that what we're doing ATM is not violating the spec, but it's
simple enough to set mtval/stval and it makes life easier for any
software that relies on this info.

Given that we always use action = 0, save the faulting address for the
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
used as as scratch area for traps with address information. 'tval' is
then set during riscv_cpu_do_interrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 1 +
 target/riscv/debug.c      | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             tval = env->bins;
             break;
         case RISCV_EXCP_BREAKPOINT:
+            tval = env->badaddr;
             if (cs->watchpoint_hit) {
                 tval = cs->watchpoint_hit->hitaddr;
                 cs->watchpoint_hit = NULL;
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
                     /* check U/S/M bit against current privilege level */
                     if ((ctrl >> 3) & BIT(env->priv)) {
+                        env->badaddr = pc;
                         return true;
                     }
                 }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                     if (env->virt_enabled) {
                         /* check VU/VS bit against current privilege level */
                         if ((ctrl >> 23) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     } else {
                         /* check U/S/M bit against current privilege level */
                         if ((ctrl >> 3) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Privileged spec section 4.1.9 mentions:

"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)

If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."

A similar text is found for mtval in section 3.1.16.

Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.

Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     } else {
+        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+                      offsetof(CPURISCVState, badaddr));
         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
     }
     return true;
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/cpu.c                      |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
 target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 6 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zhinx;
     bool ext_zhinxmin;
     bool ext_zve32f;
+    bool ext_zve32x;
     bool ext_zve64f;
     bool ext_zve64d;
     bool ext_zvbb;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
     *cs_base = 0;
 
-    if (cpu->cfg.ext_zve32f) {
+    if (cpu->cfg.ext_zve32x) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_cfg(env)->ext_zve32f) {
+    if (riscv_cpu_cfg(env)->ext_zve32x) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-        return;
+    /* The Zve32f extension depends on the Zve32x extension */
+    if (cpu->cfg.ext_zve32f) {
+        if (!riscv_has_ext(env, RVF)) {
+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+            return;
+        }
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
     }
 
     if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
     }
 
-    /*
-     * In principle Zve*x would also suffice here, were they supported
-     * in qemu
-     */
     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
-         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
+         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
         error_setg(errp,
                    "Vector crypto extensions require V or Zve* extensions");
         return;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h     |  1 +
 target/riscv/cpu.c         |  2 ++
 target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 3 files changed, 14 insertions(+), 6 deletions(-)

From: Jason Chien <jason.chien@sifive.com>

In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
                                  0);
     }
-    if (env->misa_ext & RVV) {
+    if (cpu->cfg.ext_zve32x) {
         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
                                  riscv_gdb_set_vector,
                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.

However, this function can't deal the big endian situation. This patch fixes
the problem by adding handling of such case.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_internals.c
+++ b/target/riscv/vector_internals.c
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
     if (tot - cnt == 0) {
         return ;
     }
+
+    if (HOST_BIG_ENDIAN) {
+        /*
+         * Deal the situation when the elements are insdie
+         * only one uint64 block including setting the
+         * masked-off element.
+         */
+        if (((tot - 1) ^ cnt) < 8) {
+            memset(base + H1(tot - 1), -1, tot - cnt);
+            return;
+        }
+        /*
+         * Otherwise, at least cross two uint64_t blocks.
+         * Set first unaligned block.
+         */
+        if (cnt % 8 != 0) {
+            uint32_t j = ROUND_UP(cnt, 8);
+            memset(base + H1(j - 1), -1, j - cnt);
+            cnt = j;
+        }
+        /* Set other 64bit aligend blocks */
+    }
     memset(base + cnt, -1, tot - cnt);
 }
 
-- 
2.45.1

From: Yangyu Chen <cyy@cyyself.name>

This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Vector cryptography extensions */
     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heterogeneous cpu architectures. As we add decoder in
   RISCVCPU, each cpu can have their own decoder, and the decoders can be
   different due to cpu's features.
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
   can be added to the dynamic_decoder when building up the decoder. Therefore,
   there is no need to run the guard_func when decoding each instruction. It can
   improve the decoding efficiency
3. For vendor or dynamic cpus, it allows them to customize their own decoder
   functions to improve decoding efficiency, especially when vendor-defined
   instruction sets increase. Because of dynamic building up, it can skip the other
   decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
   overhead for users that don't need this particular vendor decoder.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 +
 target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
 target/riscv/cpu.c         |  1 +
 target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
 target/riscv/translate.c   | 31 +++++++++++++++----------------
 5 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
     uint32_t pmu_avail_ctrs;
     /* Mapping of events to counters */
     GHashTable *pmu_event_ctr_map;
+    const GPtrArray *decoders;
 };
 
 /**
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 
+struct DisasContext;
+struct RISCVCPUConfig;
+typedef struct RISCVDecoder {
+    bool (*guard_func)(const struct RISCVCPUConfig *);
+    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+} RISCVDecoder;
+
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+
+extern const size_t decoder_table_size;
+
+extern const RISCVDecoder decoder_table[];
+
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
+
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
             error_propagate(errp, local_err);
             return;
         }
+        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
     } else if (kvm_enabled()) {
         riscv_kvm_cpu_finalize_features(cpu, &local_err);
         if (local_err != NULL) {
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
     }
 }
 
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
+{
+    GPtrArray *dynamic_decoders;
+    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
+    for (size_t i = 0; i < decoder_table_size; ++i) {
+        if (decoder_table[i].guard_func &&
+            decoder_table[i].guard_func(&cpu->cfg)) {
+            g_ptr_array_add(dynamic_decoders,
+                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
+        }
+    }
+
+    cpu->decoders = dynamic_decoders;
+}
+
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
 {
     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-info.c.inc"
 #undef  HELPER_H
 
+#include "tcg/tcg-cpu.h"
+
 /* global register indices */
 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* FRM is known to contain a valid value. */
     bool frm_valid;
     bool insn_start_updated;
+    const GPtrArray *decoders;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
     return (first_word & 3) == 3 ? 4 : 2;
 }
 
+const RISCVDecoder decoder_table[] = {
+    { always_true_p, decode_insn32 },
+    { has_xthead_p, decode_xthead},
+    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
+};
+
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
+
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
-    /*
-     * A table with predicate (i.e., guard) functions and decoder functions
-     * that are tested in-order until a decoder matches onto the opcode.
-     */
-    static const struct {
-        bool (*guard_func)(const RISCVCPUConfig *);
-        bool (*decode_func)(DisasContext *, uint32_t);
-    } decoders[] = {
-        { always_true_p,  decode_insn32 },
-        { has_xthead_p, decode_xthead },
-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
-    };
-
     ctx->virt_inst_excp = false;
     ctx->cur_insn_len = insn_len(opcode);
     /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                              ctx->base.pc_next + 2));
         ctx->opcode = opcode32;
 
-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
-                decoders[i].decode_func(ctx, opcode32)) {
+        for (guint i = 0; i < ctx->decoders->len; ++i) {
+            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
+            if (func(ctx, opcode32)) {
                 return;
             }
         }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
+    ctx->decoders = cpu->decoders;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.45.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc

An important property of this patch is, that the th.sxstatus MAEE field
is not set (indicating that XTheadMae is not available).
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
in PTEs that are marked as reserved. QEMU maintainers prefer to not
implement XTheadMae, so we need give kernels a mechanism to identify
if XTheadMae is available in a system or not. And this patch introduces
this mechanism in QEMU in a way that's compatible with real HW
(i.e., probing the th.sxstatus.MAEE bit).

Further context can be found on the list:
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html

Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS              |  1 +
 target/riscv/cpu.h       |  3 ++
 target/riscv/cpu.c       |  1 +
 target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |  1 +
 5 files changed, 85 insertions(+)
 create mode 100644 target/riscv/th_csr.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/insn_trans/trans_xthead.c.inc
 F: target/riscv/xthead*.decode
+F: target/riscv/th_*
 F: disas/riscv-xthead*
 
 RISC-V XVentanaCondOps extension
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
+/* Implemented in th_csr.c */
+void th_register_custom_csrs(RISCVCPU *cpu);
+
 #endif /* RISCV_CPU_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+    th_register_custom_csrs(cpu);
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/th_csr.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * T-Head-specific CSRs.
+ *
+ * Copyright (c) 2024 VRULL GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpu_vendorid.h"
+
+#define CSR_TH_SXSTATUS 0x5c0
+
+/* TH_SXSTATUS bits */
+#define TH_SXSTATUS_UCME        BIT(16)
+#define TH_SXSTATUS_MAEE        BIT(21)
+#define TH_SXSTATUS_THEADISAEE  BIT(22)
+
+typedef struct {
+    int csrno;
+    int (*insertion_test)(RISCVCPU *cpu);
+    riscv_csr_operations csr_ops;
+} riscv_csr;
+
+static RISCVException smode(CPURISCVState *env, int csrno)
+{
+    if (riscv_has_ext(env, RVS)) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
+
+static int test_thead_mvendorid(RISCVCPU *cpu)
+{
+    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
+        return -1;
+    }
+
+    return 0;
+}
+
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
+                                       target_ulong *val)
+{
+    /* We don't set MAEE here, because QEMU does not implement MAEE. */
+    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
+    return RISCV_EXCP_NONE;
+}
+
+static riscv_csr th_csr_list[] = {
+    {
+        .csrno = CSR_TH_SXSTATUS,
+        .insertion_test = test_thead_mvendorid,
+        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
+    }
+};
+
+void th_register_custom_csrs(RISCVCPU *cpu)
+{
+    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
+        int csrno = th_csr_list[i].csrno;
+        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
+        if (!th_csr_list[i].insertion_test(cpu)) {
+            riscv_set_csr_ops(csrno, csr_ops);
+        }
+    }
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
   'monitor.c',
   'machine.c',
   'pmu.c',
+  'th_csr.c',
   'time_helper.c',
   'riscv-qmp-cmds.c',
 ))
-- 
2.45.1

From: Max Chou <max.chou@sifive.com>

According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of

* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

From: Max Chou <max.chou@sifive.com>

The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.

The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
 1 file changed, 5 insertions(+)

From: Max Chou <max.chou@sifive.com>

If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_ds(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dd(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_widen_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

raise_mmu_exception(), as is today, is prioritizing guest page faults by
checking first if virt_enabled && !first_stage, and then considering the
regular inst/load/store faults.

There's no mention in the spec about guest page fault being a higher
priority that PMP faults. In fact, privileged spec section 3.7.1 says:

"Attempting to fetch an instruction from a PMP region that does not have
execute permissions raises an instruction access-fault exception.
Attempting to execute a load or load-reserved instruction which accesses
a physical address within a PMP region without read permissions raises a
load access-fault exception. Attempting to execute a store,
store-conditional, or AMO instruction which accesses a physical address
within a PMP region without write permissions raises a store
access-fault exception."

So, in fact, we're doing it wrong - PMP faults should always be thrown,
regardless of also being a first or second stage fault.

The way riscv_cpu_tlb_fill() and get_physical_address() work is
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
reflected in the 'pmp_violation' flag. What we need is to change
raise_mmu_exception() to prioritize it.

Reported-by: Joseph Chan <jchan@ventanamicro.com>
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 
     switch (access_type) {
     case MMU_INST_FETCH:
-        if (env->virt_enabled && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
+        } else if (env->virt_enabled && !first_stage) {
             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
         }
         break;
     case MMU_DATA_LOAD:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
         }
         break;
     case MMU_DATA_STORE:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-                RISCV_EXCP_STORE_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
         }
         break;
     default:
-- 
2.45.1

From: Alexei Filippov <alexei.filippov@syntacore.com>

Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation but
failed pmp check.

In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
page-fault is taken into M-mode, mtval2 is written with either zero or guest
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*

Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                               __func__, pa, ret, prot_pmp, tlb_size);
 
                 prot &= prot_pmp;
-            }
-
-            if (ret != TRANSLATE_SUCCESS) {
+            } else {
                 /*
                  * Guest physical address translation failed, this is a HS
                  * level exception
                  */
                 first_stage_error = false;
-                env->guest_phys_fault_addr = (im_address |
-                                              (address &
-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
+                if (ret != TRANSLATE_PMP_FAIL) {
+                    env->guest_phys_fault_addr = (im_address |
+                                                  (address &
+                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
+                }
             }
         }
     } else {
-- 
2.45.1

From: Rob Bradford <rbradford@rivosinc.com>

This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.

Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c         | 2 +-
 target/riscv/tcg/tcg-cpu.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
     MISA_EXT_INFO(RVV, "v", "Vector operations"),
     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
+    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
 };
 
 static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
+    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
         isa_ext_update_enabled(cpu, prop->offset, true);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

When running the instruction

```
    cbo.flush 0(x0)
```

QEMU would segfault.

The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.

In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing pointer mask
calculations on the address specified in rs1.

The pointer masking specificiation specifically states:

"""
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
"""

So this is the correct behaviour and we previously have been incorrectly
not masking the address.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -XXX,XX +XXX,XX @@
 static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_inval(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
 {
     REQUIRE_ZICBOZ(ctx);
-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_zero(tcg_env, src);
     return true;
 }
-- 
2.45.1

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
groups.

However, if the largest hart number among groups is a power of 2, QEMU
will pass an inaccurate hart-index-bit setting to Linux. For example, when
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
to represent 4 harts, but we passes 3 to Linux. The code needs to be
updated to ensure accurate hart-index-bit settings.

Additionally, a Linux patch[1] is necessary to correctly recover the hart
index when the guest OS has only 1 hart, where the hart-index-bit is 0.

[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
         }
     }
 
-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+
+    if (max_hart_per_socket > 1) {
+        max_hart_per_socket--;
+        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+    } else {
+        hart_bits = 0;
+    }
+
     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
                             &hart_bits, true, NULL);
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.

Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.

While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
clarity about what the variable represents. 'bitsize' is also used in
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
gdb_feature_builder_append_reg().

Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
-    int reg_width = cpu->cfg.vlenb;
+    int bitsize = cpu->cfg.vlenb << 3;
     GDBFeatureBuilder builder;
     int i;
 
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
+        int count = bitsize / vec_lanes[i].size;
         gdb_feature_builder_append_tag(
             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
     /* Define vector registers */
     for (i = 0; i < 32; i++) {
         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
-                                       reg_width, i, "riscv_vector", "vector");
+                                       bitsize, i, "riscv_vector", "vector");
     }
 
     gdb_feature_builder_end(&builder);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.

Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Fixes: ea10325917 ("RISC-V Disassembler")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x0383: return "mibound";
     case 0x0384: return "mdbase";
     case 0x0385: return "mdbound";
-    case 0x03a0: return "pmpcfg3";
+    case 0x03a0: return "pmpcfg0";
+    case 0x03a1: return "pmpcfg1";
+    case 0x03a2: return "pmpcfg2";
+    case 0x03a3: return "pmpcfg3";
+    case 0x03a4: return "pmpcfg4";
+    case 0x03a5: return "pmpcfg5";
+    case 0x03a6: return "pmpcfg6";
+    case 0x03a7: return "pmpcfg7";
+    case 0x03a8: return "pmpcfg8";
+    case 0x03a9: return "pmpcfg9";
+    case 0x03aa: return "pmpcfg10";
+    case 0x03ab: return "pmpcfg11";
+    case 0x03ac: return "pmpcfg12";
+    case 0x03ad: return "pmpcfg13";
+    case 0x03ae: return "pmpcfg14";
+    case 0x03af: return "pmpcfg15";
     case 0x03b0: return "pmpaddr0";
     case 0x03b1: return "pmpaddr1";
     case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x03bd: return "pmpaddr13";
     case 0x03be: return "pmpaddr14";
     case 0x03bf: return "pmpaddr15";
+    case 0x03c0: return "pmpaddr16";
+    case 0x03c1: return "pmpaddr17";
+    case 0x03c2: return "pmpaddr18";
+    case 0x03c3: return "pmpaddr19";
+    case 0x03c4: return "pmpaddr20";
+    case 0x03c5: return "pmpaddr21";
+    case 0x03c6: return "pmpaddr22";
+    case 0x03c7: return "pmpaddr23";
+    case 0x03c8: return "pmpaddr24";
+    case 0x03c9: return "pmpaddr25";
+    case 0x03ca: return "pmpaddr26";
+    case 0x03cb: return "pmpaddr27";
+    case 0x03cc: return "pmpaddr28";
+    case 0x03cd: return "pmpaddr29";
+    case 0x03ce: return "pmpaddr30";
+    case 0x03cf: return "pmpaddr31";
+    case 0x03d0: return "pmpaddr32";
+    case 0x03d1: return "pmpaddr33";
+    case 0x03d2: return "pmpaddr34";
+    case 0x03d3: return "pmpaddr35";
+    case 0x03d4: return "pmpaddr36";
+    case 0x03d5: return "pmpaddr37";
+    case 0x03d6: return "pmpaddr38";
+    case 0x03d7: return "pmpaddr39";
+    case 0x03d8: return "pmpaddr40";
+    case 0x03d9: return "pmpaddr41";
+    case 0x03da: return "pmpaddr42";
+    case 0x03db: return "pmpaddr43";
+    case 0x03dc: return "pmpaddr44";
+    case 0x03dd: return "pmpaddr45";
+    case 0x03de: return "pmpaddr46";
+    case 0x03df: return "pmpaddr47";
+    case 0x03e0: return "pmpaddr48";
+    case 0x03e1: return "pmpaddr49";
+    case 0x03e2: return "pmpaddr50";
+    case 0x03e3: return "pmpaddr51";
+    case 0x03e4: return "pmpaddr52";
+    case 0x03e5: return "pmpaddr53";
+    case 0x03e6: return "pmpaddr54";
+    case 0x03e7: return "pmpaddr55";
+    case 0x03e8: return "pmpaddr56";
+    case 0x03e9: return "pmpaddr57";
+    case 0x03ea: return "pmpaddr58";
+    case 0x03eb: return "pmpaddr59";
+    case 0x03ec: return "pmpaddr60";
+    case 0x03ed: return "pmpaddr61";
+    case 0x03ee: return "pmpaddr62";
+    case 0x03ef: return "pmpaddr63";
     case 0x0780: return "mtohost";
     case 0x0781: return "mfromhost";
     case 0x0782: return "mreset";
-- 
2.45.1

From: Yu-Ming Chang <yumin686@andestech.com>

Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
holding a zero value other than x0, the instruction will still attempt to write
the unmodified value back to the CSR and will cause any attendant side effects.

So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
a register holding a zero value, an illegal instruction exception should be
raised.

Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       |  4 ++++
 target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
 target/riscv/op_helper.c |  6 ++---
 3 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
 void riscv_cpu_update_mask(CPURISCVState *env);
 bool riscv_cpu_is_32bit(RISCVCPU *cpu);
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                          target_ulong *ret_value);
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask);
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                           target_ulong new_value,
                                           target_ulong write_mask);
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value);
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 
 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                int csrno,
-                                               bool write_mask)
+                                               bool write)
 {
     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
     bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
     }
 
     /* read / write check */
-    if (write_mask && read_only) {
+    if (write && read_only) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value)
+{
+    RISCVException ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
+}
+
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask)
 {
-    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
+    RISCVException ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value)
+{
+    RISCVException ret;
+
+    ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    if (csr_ops[csrno].read128) {
+        return riscv_csrrw_do128(env, csrno, ret_value,
+                                 int128_zero(), int128_zero());
+    }
+
+    /*
+     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
+     * at all defined.
+     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
+     * significant), for those, this fallback is correctly handling the
+     * accesses
+     */
+    target_ulong old_value;
+    ret = riscv_csrrw_do64(env, csrno, &old_value,
+                           (target_ulong)0,
+                           (target_ulong)0);
+    if (ret == RISCV_EXCP_NONE && ret_value) {
+        *ret_value = int128_make64(old_value);
+    }
+    return ret;
+}
+
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask)
 {
     RISCVException ret;
 
-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
+    ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
     }
 
     target_ulong val = 0;
-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
+    RISCVException ret = riscv_csrr(env, csr, &val);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
 target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
 {
     Int128 rv = int128_zero();
-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
-                                          int128_zero(),
-                                          int128_zero());
+    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
-- 
2.45.1