[PATCH v3 0/4] QEMU RISC-V ACLINT Support

Anup Patel posted 4 patches 2 years, 8 months ago
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There is a newer version of this series
docs/system/riscv/virt.rst     |  10 +
hw/intc/Kconfig                |   2 +-
hw/intc/meson.build            |   2 +-
hw/intc/riscv_aclint.c         | 426 ++++++++++++++++++++++
hw/intc/sifive_clint.c         | 294 ---------------
hw/riscv/Kconfig               |  12 +-
hw/riscv/microchip_pfsoc.c     |  11 +-
hw/riscv/shakti_c.c            |  13 +-
hw/riscv/sifive_e.c            |  13 +-
hw/riscv/sifive_u.c            |  11 +-
hw/riscv/spike.c               |  16 +-
hw/riscv/virt.c                | 646 ++++++++++++++++++++++-----------
include/hw/intc/riscv_aclint.h |  80 ++++
include/hw/intc/sifive_clint.h |  62 ----
include/hw/riscv/virt.h        |   2 +
15 files changed, 1010 insertions(+), 590 deletions(-)
create mode 100644 hw/intc/riscv_aclint.c
delete mode 100644 hw/intc/sifive_clint.c
create mode 100644 include/hw/intc/riscv_aclint.h
delete mode 100644 include/hw/intc/sifive_clint.h
[PATCH v3 0/4] QEMU RISC-V ACLINT Support
Posted by Anup Patel 2 years, 8 months ago
The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement
over the SiFive CLINT but also maintains backward compatibility with
the SiFive CLINT.

Latest RISC-V ACLINT specification (will be frozen soon) can be found at:
https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

This series:
1) Replaces SiFive CLINT implementation with RISC-V ACLINT
2) Refactors RISC-V virt machine FDT generation
3) Adds optional full ACLINT support in QEMU RISC-V virt machine

This series can be found in the riscv_aclint_v3 branch at:
https://github.com/avpatel/qemu.git

Changes since v2:
 - Addresed nit comments in PATCH2
 - Update SSWI device emulation to match final ACLINT draft specification

Changes since v1:
 - Split PATCH1 into two patches where one patch renames CLINT sources
   and another patch updates the implementation
 - Addressed comments from Alistar and Bin

Anup Patel (4):
  hw/intc: Rename sifive_clint sources to riscv_aclint sources
  hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
  hw/riscv: virt: Re-factor FDT generation
  hw/riscv: virt: Add optional ACLINT support to virt machine

 docs/system/riscv/virt.rst     |  10 +
 hw/intc/Kconfig                |   2 +-
 hw/intc/meson.build            |   2 +-
 hw/intc/riscv_aclint.c         | 426 ++++++++++++++++++++++
 hw/intc/sifive_clint.c         | 294 ---------------
 hw/riscv/Kconfig               |  12 +-
 hw/riscv/microchip_pfsoc.c     |  11 +-
 hw/riscv/shakti_c.c            |  13 +-
 hw/riscv/sifive_e.c            |  13 +-
 hw/riscv/sifive_u.c            |  11 +-
 hw/riscv/spike.c               |  16 +-
 hw/riscv/virt.c                | 646 ++++++++++++++++++++++-----------
 include/hw/intc/riscv_aclint.h |  80 ++++
 include/hw/intc/sifive_clint.h |  62 ----
 include/hw/riscv/virt.h        |   2 +
 15 files changed, 1010 insertions(+), 590 deletions(-)
 create mode 100644 hw/intc/riscv_aclint.c
 delete mode 100644 hw/intc/sifive_clint.c
 create mode 100644 include/hw/intc/riscv_aclint.h
 delete mode 100644 include/hw/intc/sifive_clint.h

-- 
2.25.1