[v6] target/riscv: Update QEmu for Zb[abcs] 1.0.0

[PATCH v6 10/14] target/riscv: Add a REQUIRE_32BIT macro

Posted by Philipp Tomsich 4 years, 5 months ago

With the changes to Zb[abcs], there's some encodings that are
different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,
we'll need a helper macro allowing us to select on RV32, as well.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---

(no changes since v3)

Changes in v3:
- Moved the REQUIRE_32BIT macro into a separate commit.

 target/riscv/translate.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 5c099ff007..aabdd44663 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -417,6 +417,12 @@ EX_SH(12)
     }                              \
 } while (0)
 
+#define REQUIRE_32BIT(ctx) do { \
+    if (!is_32bit(ctx)) {       \
+        return false;           \
+    }                           \
+} while (0)
+
 #define REQUIRE_64BIT(ctx) do { \
     if (is_32bit(ctx)) {        \
         return false;           \
-- 
2.25.1

Re: [PATCH v6 10/14] target/riscv: Add a REQUIRE_32BIT macro

Posted by Alistair Francis 4 years, 5 months ago

On Thu, Aug 26, 2021 at 3:15 AM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> With the changes to Zb[abcs], there's some encodings that are
> different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,
> we'll need a helper macro allowing us to select on RV32, as well.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Moved the REQUIRE_32BIT macro into a separate commit.
>
>  target/riscv/translate.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 5c099ff007..aabdd44663 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -417,6 +417,12 @@ EX_SH(12)
>      }                              \
>  } while (0)
>
> +#define REQUIRE_32BIT(ctx) do { \
> +    if (!is_32bit(ctx)) {       \
> +        return false;           \
> +    }                           \
> +} while (0)
> +
>  #define REQUIRE_64BIT(ctx) do { \
>      if (is_32bit(ctx)) {        \
>          return false;           \
> --
> 2.25.1
>
>