[PULL 00/28] MIPS patches for 2021-08-25

Philippe Mathieu-Daudé posted 28 patches 2 years, 8 months ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/20210825130211.1542338-1-f4bug@amsat.org
Maintainers: Jiaxun Yang <jiaxun.yang@flygoat.com>, Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, Aurelien Jarno <aurelien@aurel32.net>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>
target/mips/helper.h                          |  18 +-
target/mips/tcg/translate.h                   |  27 ++
target/mips/tcg/vr54xx_helper.h.inc           |  24 ++
target/mips/tcg/mips64r6.decode               |  27 --
target/mips/tcg/msa.decode                    |   4 +-
.../mips/tcg/{mips32r6.decode => rel6.decode} |  17 +-
target/mips/tcg/tx79.decode                   |  14 +-
target/mips/tcg/vr54xx.decode                 |  27 ++
target/mips/tcg/ldst_helper.c                 | 122 +++++----
target/mips/tcg/msa_translate.c               |   4 +-
target/mips/tcg/op_helper.c                   | 118 --------
target/mips/tcg/rel6_translate.c              |  20 +-
target/mips/tcg/translate.c                   | 258 ++++--------------
target/mips/tcg/tx79_translate.c              |  62 ++---
target/mips/tcg/vr54xx_helper.c               | 142 ++++++++++
target/mips/tcg/vr54xx_translate.c            |  72 +++++
target/mips/cpu-defs.c.inc                    |   6 +-
target/mips/tcg/nanomips_translate.c.inc      |  20 +-
target/mips/tcg/meson.build                   |   6 +-
19 files changed, 502 insertions(+), 486 deletions(-)
create mode 100644 target/mips/tcg/vr54xx_helper.h.inc
delete mode 100644 target/mips/tcg/mips64r6.decode
rename target/mips/tcg/{mips32r6.decode => rel6.decode} (64%)
create mode 100644 target/mips/tcg/vr54xx.decode
create mode 100644 target/mips/tcg/vr54xx_helper.c
create mode 100644 target/mips/tcg/vr54xx_translate.c
[PULL 00/28] MIPS patches for 2021-08-25
Posted by Philippe Mathieu-Daudé 2 years, 8 months ago
The following changes since commit d42685765653ec155fdf60910662f8830bdb2cef:

  Open 6.2 development tree (2021-08-25 10:25:12 +0100)

are available in the Git repository at:

  https://github.com/philmd/qemu.git tags/mips-20210825

for you to fetch changes up to bf78469cc8ddb117b6db4a353e59fb4664a96de4:

  target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian() (2021-08-25 13:02:14 +0200)

----------------------------------------------------------------
MIPS patches queue

- minor simplifications in PREF / JR opcodes
- merge 32-bit/64-bit Release6 decodetree definitions
- converted NEC Vr54xx extension opcodes to decodetree
- housekeeping in gen_helper() macros
- replace TARGET_WORDS_BIGENDIAN #ifdef'ry by cpu_is_bigendian()
- allow Loongson 3A1000 to use up to 48-bit VAddr

----------------------------------------------------------------

One false positive because whole target/mips/ is coverd in MAINTAINERS:

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?

 MIPS TCG CPUs
 F: target/mips/

Two style warnings:

WARNING: line over 80 characters

Preexisting failure (fixes from John Snow available on the list):

ERROR:   py36: commands failed
ERROR:   py37: commands failed
ERROR:   py38: commands failed
ERROR:   py39: commands failed
ERROR:   py310: commands failed
make: *** [Makefile:93: check-tox] Error 1

Philippe Mathieu-Daudé (28):
  target/mips: Remove JR opcode unused arguments
  target/mips: Simplify PREF opcode
  target/mips: Decode vendor extensions before MIPS ISAs
  target/mips: Merge 32-bit/64-bit Release6 decodetree definitions
  target/mips: Rename 'rtype' as 'r'
  target/mips: Introduce generic TRANS() macro for decodetree helpers
  target/mips: Extract NEC Vr54xx helper definitions
  target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c
  target/mips: Introduce decodetree structure for NEC Vr54xx extension
  target/mips: Convert Vr54xx MACC* opcodes to decodetree
  target/mips: Convert Vr54xx MUL* opcodes to decodetree
  target/mips: Convert Vr54xx MSA* opcodes to decodetree
  target/mips: Document Loongson-3A CPU definitions
  target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr
  target/mips: Remove duplicated check_cp1_enabled() calls in Loongson
    EXT
  target/mips: Remove gen_helper_0e3i()
  target/mips: Remove gen_helper_1e2i()
  target/mips: Use tcg_constant_i32() in gen_helper_0e2i()
  target/mips: Simplify gen_helper() macros by using tcg_constant_i32()
  target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros
  target/mips: Inline gen_helper_0e0i()
  target/mips: Use tcg_constant_i32() in generate_exception_err()
  target/mips: Define gen_helper() macros in translate.h
  target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st
    helpers
  target/mips: Replace GET_LMASK() macro by get_lmask(32) function
  target/mips: Replace GET_LMASK64() macro by get_lmask(64) function
  target/mips: Store CP0_Config0 in DisasContext
  target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()

 target/mips/helper.h                          |  18 +-
 target/mips/tcg/translate.h                   |  27 ++
 target/mips/tcg/vr54xx_helper.h.inc           |  24 ++
 target/mips/tcg/mips64r6.decode               |  27 --
 target/mips/tcg/msa.decode                    |   4 +-
 .../mips/tcg/{mips32r6.decode => rel6.decode} |  17 +-
 target/mips/tcg/tx79.decode                   |  14 +-
 target/mips/tcg/vr54xx.decode                 |  27 ++
 target/mips/tcg/ldst_helper.c                 | 122 +++++----
 target/mips/tcg/msa_translate.c               |   4 +-
 target/mips/tcg/op_helper.c                   | 118 --------
 target/mips/tcg/rel6_translate.c              |  20 +-
 target/mips/tcg/translate.c                   | 258 ++++--------------
 target/mips/tcg/tx79_translate.c              |  62 ++---
 target/mips/tcg/vr54xx_helper.c               | 142 ++++++++++
 target/mips/tcg/vr54xx_translate.c            |  72 +++++
 target/mips/cpu-defs.c.inc                    |   6 +-
 target/mips/tcg/nanomips_translate.c.inc      |  20 +-
 target/mips/tcg/meson.build                   |   6 +-
 19 files changed, 502 insertions(+), 486 deletions(-)
 create mode 100644 target/mips/tcg/vr54xx_helper.h.inc
 delete mode 100644 target/mips/tcg/mips64r6.decode
 rename target/mips/tcg/{mips32r6.decode => rel6.decode} (64%)
 create mode 100644 target/mips/tcg/vr54xx.decode
 create mode 100644 target/mips/tcg/vr54xx_helper.c
 create mode 100644 target/mips/tcg/vr54xx_translate.c

-- 
2.31.1

Re: [PULL 00/28] MIPS patches for 2021-08-25
Posted by Peter Maydell 2 years, 8 months ago
On Wed, 25 Aug 2021 at 14:06, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> The following changes since commit d42685765653ec155fdf60910662f8830bdb2cef:
>
>   Open 6.2 development tree (2021-08-25 10:25:12 +0100)
>
> are available in the Git repository at:
>
>   https://github.com/philmd/qemu.git tags/mips-20210825
>
> for you to fetch changes up to bf78469cc8ddb117b6db4a353e59fb4664a96de4:
>
>   target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian() (2021-08-25 13:02:14 +0200)
>
> ----------------------------------------------------------------
> MIPS patches queue
>
> - minor simplifications in PREF / JR opcodes
> - merge 32-bit/64-bit Release6 decodetree definitions
> - converted NEC Vr54xx extension opcodes to decodetree
> - housekeeping in gen_helper() macros
> - replace TARGET_WORDS_BIGENDIAN #ifdef'ry by cpu_is_bigendian()
> - allow Loongson 3A1000 to use up to 48-bit VAddr
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.2
for any user-visible changes.

-- PMM