[PATCH 0/2] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr

Philippe Mathieu-Daudé posted 2 patches 2 years, 8 months ago
Test checkpatch passed
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20210813110149.1432692-1-f4bug@amsat.org
Maintainers: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Aurelien Jarno <aurelien@aurel32.net>
target/mips/cpu-defs.c.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
[PATCH 0/2] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr
Posted by Philippe Mathieu-Daudé 2 years, 8 months ago
Raise Loongson-3A1000 SEGBITS from 40 to 48.

Philippe Mathieu-Daudé (2):
  target/mips: Document Loongson-3A CPU definitions
  target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr

 target/mips/cpu-defs.c.inc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

-- 
2.31.1

Re: [PATCH 0/2] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr
Posted by Philippe Mathieu-Daudé 2 years, 8 months ago
On 8/13/21 1:01 PM, Philippe Mathieu-Daudé wrote:
> Raise Loongson-3A1000 SEGBITS from 40 to 48.
> 
> Philippe Mathieu-Daudé (2):
>   target/mips: Document Loongson-3A CPU definitions
>   target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr

Thanks, applied to mips-next.