On Mon, Aug 09, 2021 at 10:10:54AM -0300, Daniel Henrique Barboza wrote:
> The PowerISA 3.1 defines the 0xFA event as instructions completed when
> the thread's CTRL register is set. Some EBB powerpc kernel tests use
> this event to exercise both the PMU and the EBB support.
Couldn't you implement this more accurately by snapshotting the count
at each CTRL write, and either adding the delta to the PMC or not
depending on the previous CTRL value?
> We don't have a way at this moment to tell whether an instruction was
> completed under those conditions. What we can do is to make it
> equivalent to the existing PM_INST_COMPL event that counts all
> instructions completed. For our current purposes with the PMU support
> this is enough.
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
> target/ppc/pmu_book3s_helper.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/target/ppc/pmu_book3s_helper.c b/target/ppc/pmu_book3s_helper.c
> index c5c5ab38c9..388263688b 100644
> --- a/target/ppc/pmu_book3s_helper.c
> +++ b/target/ppc/pmu_book3s_helper.c
> @@ -52,6 +52,20 @@ static uint8_t get_PMC_event(CPUPPCState *env, int sprn)
> break;
> case SPR_POWER_PMC4:
> event = MMCR1_PMC4SEL & env->spr[SPR_POWER_MMCR1];
> +
> + /*
> + * Event 0xFA for PMC4SEL is described as follows in
> + * PowerISA v3.1:
> + *
> + * "The thread has completed an instruction when the RUN bit of
> + * the thread’s CTRL register contained 1"
> + *
> + * Our closest equivalent for this event at this moment is plain
> + * INST_CMPL (event 0x2)
> + */
> + if (event == 0xFA) {
> + event = 0x2;
> + }
> break;
> case SPR_POWER_PMC5:
> event = 0x2;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson