Convert the following Integer Multiply-Accumulate opcodes:
* MULHI Multiply and move HI
* MULHIU Unsigned multiply and move HI
* MULS Multiply, negate, and move LO
* MULSHI Multiply, negate, and move HI
* MULSHIU Unsigned multiply, negate, and move HI
* MULSU Unsigned multiply, negate, and move LO
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/vr54xx.decode | 6 ++++++
target/mips/tcg/translate.c | 24 ------------------------
target/mips/tcg/vr54xx_translate.c | 12 ++++++++++++
3 files changed, 18 insertions(+), 24 deletions(-)
diff --git a/target/mips/tcg/vr54xx.decode b/target/mips/tcg/vr54xx.decode
index 73778f101a5..79bb5175eab 100644
--- a/target/mips/tcg/vr54xx.decode
+++ b/target/mips/tcg/vr54xx.decode
@@ -11,7 +11,13 @@
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r
+MULS 000000 ..... ..... ..... 00011011000 @rs_rt_rd
+MULSU 000000 ..... ..... ..... 00011011001 @rs_rt_rd
MACC 000000 ..... ..... ..... 00101011000 @rs_rt_rd
MACCU 000000 ..... ..... ..... 00101011001 @rs_rt_rd
+MULHI 000000 ..... ..... ..... 01001011000 @rs_rt_rd
+MULHIU 000000 ..... ..... ..... 01001011001 @rs_rt_rd
+MULSHI 000000 ..... ..... ..... 01011011000 @rs_rt_rd
+MULSHIU 000000 ..... ..... ..... 01011011001 @rs_rt_rd
MACCHI 000000 ..... ..... ..... 01101011000 @rs_rt_rd
MACCHIU 000000 ..... ..... ..... 01101011001 @rs_rt_rd
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 8d29a0d4e4b..4196319d827 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -298,14 +298,8 @@ enum {
#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6)))
enum {
- OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT,
- OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU,
OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT,
OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU,
- OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT,
- OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU,
- OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT,
- OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,
OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT,
OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,
};
@@ -3770,30 +3764,12 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc,
gen_load_gpr(t1, rt);
switch (opc) {
- case OPC_VR54XX_MULS:
- gen_helper_muls(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULSU:
- gen_helper_mulsu(t0, cpu_env, t0, t1);
- break;
case OPC_VR54XX_MSAC:
gen_helper_msac(t0, cpu_env, t0, t1);
break;
case OPC_VR54XX_MSACU:
gen_helper_msacu(t0, cpu_env, t0, t1);
break;
- case OPC_VR54XX_MULHI:
- gen_helper_mulhi(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULHIU:
- gen_helper_mulhiu(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULSHI:
- gen_helper_mulshi(t0, cpu_env, t0, t1);
- break;
- case OPC_VR54XX_MULSHIU:
- gen_helper_mulshiu(t0, cpu_env, t0, t1);
- break;
case OPC_VR54XX_MSACHI:
gen_helper_msachi(t0, cpu_env, t0, t1);
break;
diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_translate.c
index 85e2ec371b9..1e6000d3d15 100644
--- a/target/mips/tcg/vr54xx_translate.c
+++ b/target/mips/tcg/vr54xx_translate.c
@@ -25,6 +25,12 @@
* MACCHI Multiply, accumulate, and move HI
* MACCHIU Unsigned multiply, accumulate, and move HI
* MACCU Unsigned multiply, accumulate, and move LO
+ * MULHI Multiply and move HI
+ * MULHIU Unsigned multiply and move HI
+ * MULS Multiply, negate, and move LO
+ * MULSHI Multiply, negate, and move HI
+ * MULSHIU Unsigned multiply, negate, and move HI
+ * MULSU Unsigned multiply, negate, and move LO
*/
typedef void gen_helper_mult_acc_t(TCGv, TCGv_ptr, TCGv, TCGv);
@@ -57,3 +63,9 @@ MULT_ACC(MACC, gen_helper_macc);
MULT_ACC(MACCHI, gen_helper_macchi);
MULT_ACC(MACCHIU, gen_helper_macchiu);
MULT_ACC(MACCU, gen_helper_maccu);
+MULT_ACC(MULHI, gen_helper_mulhi);
+MULT_ACC(MULHIU, gen_helper_mulhiu);
+MULT_ACC(MULS, gen_helper_muls);
+MULT_ACC(MULSHI, gen_helper_mulshi);
+MULT_ACC(MULSHIU, gen_helper_mulshiu);
+MULT_ACC(MULSU, gen_helper_mulsu);
--
2.31.1