This began with Peter wanting a cpu_ldst.h interface that can handle
alignment info for Arm M-profile system mode, which will also compile
for user-only without ifdefs.  This is patch 32.

Once I had that interface, I thought I might as well enforce the
requested alignment in user-only.  There are plenty of cases where
we ought to have been doing that for quite a while.  This took rather
more work than I imagined to start.

So far only x86 host has been fully converted to handle unaligned
operations in user-only mode.  I'll get to the others later.  But
the added testcase is fairly broad, and caught lots of bugs and/or
missing code between target/ and linux-user/.

Notes:
  * For target/i386 we have no way to signal SIGBUS from user-only.
    In theory we could go through do_unaligned_access in system mode,
    via #AC.  But we don't even implement that control in tcg, probably
    because no one ever sets it.  The cmpxchg16b insn requires alignment,
    but raises #GP, which maps to SIGSEGV.

  * For target/s390x we have no way to signal SIGBUS from user-only.
    The atomic operations raise PGM_SPECIFICATION, which the linux
    kernel maps to SIGILL.

  * I think target/hexagon should be setting TARGET_ALIGNED_ONLY=y.
    In the meantime, all memory accesses are allowed to be unaligned.


r~


Richard Henderson (43):
  hw/core: Make do_unaligned_access available to user-only
  target/alpha: Implement do_unaligned_access for user-only
  target/arm: Implement do_unaligned_access for user-only
  target/hppa: Implement do_unaligned_access for user-only
  target/microblaze: Implement do_unaligned_access for user-only
  target/mips: Implement do_unaligned_access for user-only
  target/ppc: Set fault address in ppc_cpu_do_unaligned_access
  target/ppc: Implement do_unaligned_access for user-only
  target/riscv: Implement do_unaligned_access for user-only
  target/s390x: Implement do_unaligned_access for user-only
  target/sh4: Set fault address in superh_cpu_do_unaligned_access
  target/sh4: Implement do_unaligned_access for user-only
  target/sparc: Remove DEBUG_UNALIGNED
  target/sparc: Set fault address in sparc_cpu_do_unaligned_access
  target/sparc: Implement do_unaligned_access for user-only
  target/xtensa: Implement do_unaligned_access for user-only
  accel/tcg: Report unaligned atomics for user-only
  accel/tcg: Drop signness in tracing in cputlb.c
  tcg: Expand MO_SIZE to 3 bits
  tcg: Rename TCGMemOpIdx to MemOpIdx
  tcg: Split out MemOpIdx to exec/memopidx.h
  trace/mem: Pass MemOpIdx to trace_mem_get_info
  accel/tcg: Remove double bswap for helper_atomic_sto_*_mmu
  accel/tcg: Pass MemOpIdx to atomic_trace_*_post
  plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb
  trace: Split guest_mem_before
  target/arm: Use MO_128 for 16 byte atomics
  target/i386: Use MO_128 for 16 byte atomics
  target/ppc: Use MO_128 for 16 byte atomics
  target/s390x: Use MO_128 for 16 byte atomics
  target/hexagon: Implement cpu_mmu_index
  accel/tcg: Add cpu_{ld,st}*_mmu interfaces
  accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h
  target/mips: Use cpu_*_data_ra for msa load/store
  target/mips: Use 8-byte memory ops for msa load/store
  target/s390x: Use cpu_*_mmu instead of helper_*_mmu
  target/sparc: Use cpu_*_mmu instead of helper_*_mmu
  target/arm: Use cpu_*_mmu instead of helper_*_mmu
  tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h
  linux-user/alpha: Remove TARGET_ALIGNED_ONLY
  tcg: Add helper_unaligned_mmu for user-only sigbus
  tcg/i386: Support raising sigbus for user-only
  tests/tcg/multiarch: Add sigbus.c

 configs/targets/alpha-linux-user.mak |   1 -
 accel/tcg/atomic_template.h          |  74 ++--
 include/exec/cpu_ldst.h              | 332 +++++++++---------
 include/exec/memop.h                 |  14 +-
 include/exec/memopidx.h              |  55 +++
 include/hw/core/tcg-cpu-ops.h        |  14 +-
 include/qemu/plugin.h                |  26 +-
 include/tcg/tcg-ldst.h               |  79 +++++
 include/tcg/tcg.h                    | 197 +----------
 target/hexagon/cpu.h                 |   9 +
 tcg/i386/tcg-target.h                |   2 -
 trace/mem.h                          |  63 ----
 accel/tcg/cputlb.c                   | 486 +++++++++------------------
 accel/tcg/plugin-gen.c               |   5 +-
 accel/tcg/user-exec.c                | 444 ++++++++++--------------
 linux-user/aarch64/cpu_loop.c        |   4 +
 linux-user/arm/cpu_loop.c            |  43 ++-
 linux-user/hppa/cpu_loop.c           |   2 +-
 linux-user/mips/cpu_loop.c           |  20 +-
 linux-user/ppc/cpu_loop.c            |   2 +-
 linux-user/riscv/cpu_loop.c          |   7 +
 linux-user/sh4/cpu_loop.c            |   8 +
 linux-user/sparc/cpu_loop.c          |  11 +
 plugins/api.c                        |  19 +-
 plugins/core.c                       |  10 +-
 target/alpha/cpu.c                   |   2 +-
 target/alpha/mem_helper.c            |   8 +-
 target/alpha/translate.c             |   8 +-
 target/arm/cpu.c                     |   2 +-
 target/arm/cpu_tcg.c                 |   2 +-
 target/arm/helper-a64.c              |  77 ++---
 target/arm/m_helper.c                |   8 +-
 target/arm/translate-a64.c           |   2 +-
 target/hppa/cpu.c                    |   8 +-
 target/i386/tcg/mem_helper.c         |   4 +-
 target/m68k/op_helper.c              |   3 +-
 target/microblaze/cpu.c              |   2 +-
 target/mips/cpu.c                    |   2 +-
 target/mips/tcg/msa_helper.c         | 395 +++++-----------------
 target/mips/tcg/op_helper.c          |   3 +-
 target/mips/tcg/user/tlb_helper.c    |  23 +-
 target/ppc/cpu_init.c                |   2 +-
 target/ppc/excp_helper.c             |   2 +
 target/ppc/mem_helper.c              |   1 -
 target/ppc/translate.c               |  12 +-
 target/riscv/cpu.c                   |   2 +-
 target/riscv/cpu_helper.c            |   8 +-
 target/s390x/cpu.c                   |   2 +-
 target/s390x/tcg/excp_helper.c       |  28 +-
 target/s390x/tcg/mem_helper.c        |  31 +-
 target/sh4/cpu.c                     |   2 +-
 target/sh4/op_helper.c               |   8 +-
 target/sparc/cpu.c                   |   2 +-
 target/sparc/ldst_helper.c           |  33 +-
 target/xtensa/cpu.c                  |   2 +-
 target/xtensa/helper.c               |  30 +-
 tcg/optimize.c                       |   2 +-
 tcg/tcg-op.c                         |  60 ++--
 tcg/tcg.c                            |   3 +-
 tcg/tci.c                            |  15 +-
 tests/tcg/multiarch/sigbus.c         |  68 ++++
 accel/tcg/atomic_common.c.inc        |  43 +--
 accel/tcg/ldst_common.c.inc          | 307 +++++++++++++++++
 target/s390x/tcg/translate_vx.c.inc  |   2 +-
 tcg/aarch64/tcg-target.c.inc         |  18 +-
 tcg/arm/tcg-target.c.inc             |  14 +-
 tcg/i386/tcg-target.c.inc            | 128 ++++++-
 tcg/mips/tcg-target.c.inc            |  16 +-
 tcg/ppc/tcg-target.c.inc             |  18 +-
 tcg/riscv/tcg-target.c.inc           |  20 +-
 tcg/s390/tcg-target.c.inc            |  14 +-
 tcg/sparc/tcg-target.c.inc           |  20 +-
 tcg/tcg-ldst.c.inc                   |   2 +-
 trace-events                         |  18 +-
 74 files changed, 1699 insertions(+), 1710 deletions(-)
 create mode 100644 include/exec/memopidx.h
 create mode 100644 include/tcg/tcg-ldst.h
 delete mode 100644 trace/mem.h
 create mode 100644 tests/tcg/multiarch/sigbus.c
 create mode 100644 accel/tcg/ldst_common.c.inc

-- 
2.25.1

On Thu, 29 Jul 2021 at 01:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This began with Peter wanting a cpu_ldst.h interface that can handle
> alignment info for Arm M-profile system mode, which will also compile
> for user-only without ifdefs.  This is patch 32.
>
> Once I had that interface, I thought I might as well enforce the
> requested alignment in user-only.  There are plenty of cases where
> we ought to have been doing that for quite a while.  This took rather
> more work than I imagined to start.
>
> So far only x86 host has been fully converted to handle unaligned
> operations in user-only mode.  I'll get to the others later.  But
> the added testcase is fairly broad, and caught lots of bugs and/or
> missing code between target/ and linux-user/.
>
> Notes:
>   * For target/i386 we have no way to signal SIGBUS from user-only.
>     In theory we could go through do_unaligned_access in system mode,
>     via #AC.  But we don't even implement that control in tcg, probably
>     because no one ever sets it.  The cmpxchg16b insn requires alignment,
>     but raises #GP, which maps to SIGSEGV.
>
>   * For target/s390x we have no way to signal SIGBUS from user-only.
>     The atomic operations raise PGM_SPECIFICATION, which the linux
>     kernel maps to SIGILL.
>
>   * I think target/hexagon should be setting TARGET_ALIGNED_ONLY=y.
>     In the meantime, all memory accesses are allowed to be unaligned.

Could you include suitable updates to docs/devel/loads-stores.rst
as well, please?

thanks
-- PMM

On 7/29/21 2:46 AM, Richard Henderson wrote:
> This began with Peter wanting a cpu_ldst.h interface that can handle
> alignment info for Arm M-profile system mode, which will also compile
> for user-only without ifdefs.  This is patch 32.
> 
> Once I had that interface, I thought I might as well enforce the
> requested alignment in user-only.  There are plenty of cases where
> we ought to have been doing that for quite a while.  This took rather
> more work than I imagined to start.
> 
> So far only x86 host has been fully converted to handle unaligned
> operations in user-only mode.  I'll get to the others later.  But
> the added testcase is fairly broad, and caught lots of bugs and/or
> missing code between target/ and linux-user/.
> 
> Notes:
>   * For target/i386 we have no way to signal SIGBUS from user-only.
>     In theory we could go through do_unaligned_access in system mode,
>     via #AC.  But we don't even implement that control in tcg, probably
>     because no one ever sets it.  The cmpxchg16b insn requires alignment,
>     but raises #GP, which maps to SIGSEGV.
> 
>   * For target/s390x we have no way to signal SIGBUS from user-only.
>     The atomic operations raise PGM_SPECIFICATION, which the linux
>     kernel maps to SIGILL.
> 
>   * I think target/hexagon should be setting TARGET_ALIGNED_ONLY=y.
>     In the meantime, all memory accesses are allowed to be unaligned.

Now I better understand what you tried to explain me last with
TCGCPUOps. Since Claudio was also involved, Cc'ing him (not asking
for a review, just in case he wants to follow up).

On 7/29/21 8:14 AM, Philippe Mathieu-Daudé wrote:
> On 7/29/21 2:46 AM, Richard Henderson wrote:
>> This began with Peter wanting a cpu_ldst.h interface that can handle
>> alignment info for Arm M-profile system mode, which will also compile
>> for user-only without ifdefs.  This is patch 32.
>>
>> Once I had that interface, I thought I might as well enforce the
>> requested alignment in user-only.  There are plenty of cases where
>> we ought to have been doing that for quite a while.  This took rather
>> more work than I imagined to start.
>>
>> So far only x86 host has been fully converted to handle unaligned
>> operations in user-only mode.  I'll get to the others later.  But
>> the added testcase is fairly broad, and caught lots of bugs and/or
>> missing code between target/ and linux-user/.
>>
>> Notes:
>>   * For target/i386 we have no way to signal SIGBUS from user-only.
>>     In theory we could go through do_unaligned_access in system mode,
>>     via #AC.  But we don't even implement that control in tcg, probably
>>     because no one ever sets it.  The cmpxchg16b insn requires alignment,
>>     but raises #GP, which maps to SIGSEGV.
>>
>>   * For target/s390x we have no way to signal SIGBUS from user-only.
>>     The atomic operations raise PGM_SPECIFICATION, which the linux
>>     kernel maps to SIGILL.
>>
>>   * I think target/hexagon should be setting TARGET_ALIGNED_ONLY=y.
>>     In the meantime, all memory accesses are allowed to be unaligned.
> 
> Now I better understand what you tried to explain me last with
> TCGCPUOps. Since Claudio was also involved, Cc'ing him (not asking
> for a review, just in case he wants to follow up).
> 

Thanks, what I understand from glancing through the thread is that
at the time we made handling of unaligned access a sysmmu-only TCGCPUOps,
while this series corrects that and implements unaligned accesses for user-only,

so seems good to me.

Ciao,

Claudio