1 | arm pullreq for rc1. All minor bugfixes, except for the sve-default-vector-length | 1 | First arm pullreq of the cycle; this is mostly my softfloat NaN |
---|---|---|---|
2 | patches, which are somewhere between a bugfix and a new feature. | 2 | handling series. (Lots more in my to-review queue, but I don't |
3 | like pullreqs growing too close to a hundred patches at a time :-)) | ||
3 | 4 | ||
4 | thanks | 5 | thanks |
5 | -- PMM | 6 | -- PMM |
6 | 7 | ||
7 | The following changes since commit c08ccd1b53f488ac86c1f65cf7623dc91acc249a: | 8 | The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17: |
8 | 9 | ||
9 | Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210726' into staging (2021-07-27 08:35:01 +0100) | 10 | Open 10.0 development tree (2024-12-10 17:41:17 +0000) |
10 | 11 | ||
11 | are available in the Git repository at: | 12 | are available in the Git repository at: |
12 | 13 | ||
13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210727 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211 |
14 | 15 | ||
15 | for you to fetch changes up to e229a179a503f2aee43a76888cf12fbdfe8a3749: | 16 | for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8: |
16 | 17 | ||
17 | hw: aspeed_gpio: Fix memory size (2021-07-27 11:00:00 +0100) | 18 | MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000) |
18 | 19 | ||
19 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
20 | target-arm queue: | 21 | target-arm queue: |
21 | * hw/arm/smmuv3: Check 31st bit to see if CD is valid | 22 | * hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs |
22 | * qemu-options.hx: Fix formatting of -machine memory-backend option | 23 | * fpu: Make muladd NaN handling runtime-selected, not compile-time |
23 | * hw: aspeed_gpio: Fix memory size | 24 | * fpu: Make default NaN pattern runtime-selected, not compile-time |
24 | * hw/arm/nseries: Display hexadecimal value with '0x' prefix | 25 | * fpu: Minor NaN-related cleanups |
25 | * Add sve-default-vector-length cpu property | 26 | * MAINTAINERS: email address updates |
26 | * docs: Update path that mentions deprecated.rst | ||
27 | * hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS | ||
28 | * hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING | ||
29 | * hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts | ||
30 | * target/arm: Report M-profile alignment faults correctly to the guest | ||
31 | * target/arm: Add missing 'return's after calling v7m_exception_taken() | ||
32 | * target/arm: Enforce that M-profile SP low 2 bits are always zero | ||
33 | 27 | ||
34 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
35 | Joe Komlodi (1): | 29 | Bernhard Beschow (5): |
36 | hw/arm/smmuv3: Check 31st bit to see if CD is valid | 30 | hw/net/lan9118: Extract lan9118_phy |
31 | hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations | ||
32 | hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register | ||
33 | hw/net/lan9118_phy: Reuse MII constants | ||
34 | hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement | ||
37 | 35 | ||
38 | Joel Stanley (1): | 36 | Leif Lindholm (1): |
39 | hw: aspeed_gpio: Fix memory size | 37 | MAINTAINERS: update email address for Leif Lindholm |
40 | 38 | ||
41 | Mao Zhongyi (1): | 39 | Peter Maydell (54): |
42 | docs: Update path that mentions deprecated.rst | 40 | fpu: handle raising Invalid for infzero in pick_nan_muladd |
41 | fpu: Check for default_nan_mode before calling pickNaNMulAdd | ||
42 | softfloat: Allow runtime choice of inf * 0 + NaN result | ||
43 | tests/fp: Explicitly set inf-zero-nan rule | ||
44 | target/arm: Set FloatInfZeroNaNRule explicitly | ||
45 | target/s390: Set FloatInfZeroNaNRule explicitly | ||
46 | target/ppc: Set FloatInfZeroNaNRule explicitly | ||
47 | target/mips: Set FloatInfZeroNaNRule explicitly | ||
48 | target/sparc: Set FloatInfZeroNaNRule explicitly | ||
49 | target/xtensa: Set FloatInfZeroNaNRule explicitly | ||
50 | target/x86: Set FloatInfZeroNaNRule explicitly | ||
51 | target/loongarch: Set FloatInfZeroNaNRule explicitly | ||
52 | target/hppa: Set FloatInfZeroNaNRule explicitly | ||
53 | softfloat: Pass have_snan to pickNaNMulAdd | ||
54 | softfloat: Allow runtime choice of NaN propagation for muladd | ||
55 | tests/fp: Explicitly set 3-NaN propagation rule | ||
56 | target/arm: Set Float3NaNPropRule explicitly | ||
57 | target/loongarch: Set Float3NaNPropRule explicitly | ||
58 | target/ppc: Set Float3NaNPropRule explicitly | ||
59 | target/s390x: Set Float3NaNPropRule explicitly | ||
60 | target/sparc: Set Float3NaNPropRule explicitly | ||
61 | target/mips: Set Float3NaNPropRule explicitly | ||
62 | target/xtensa: Set Float3NaNPropRule explicitly | ||
63 | target/i386: Set Float3NaNPropRule explicitly | ||
64 | target/hppa: Set Float3NaNPropRule explicitly | ||
65 | fpu: Remove use_first_nan field from float_status | ||
66 | target/m68k: Don't pass NULL float_status to floatx80_default_nan() | ||
67 | softfloat: Create floatx80 default NaN from parts64_default_nan | ||
68 | target/loongarch: Use normal float_status in fclass_s and fclass_d helpers | ||
69 | target/m68k: In frem helper, initialize local float_status from env->fp_status | ||
70 | target/m68k: Init local float_status from env fp_status in gdb get/set reg | ||
71 | target/sparc: Initialize local scratch float_status from env->fp_status | ||
72 | target/ppc: Use env->fp_status in helper_compute_fprf functions | ||
73 | fpu: Allow runtime choice of default NaN value | ||
74 | tests/fp: Set default NaN pattern explicitly | ||
75 | target/microblaze: Set default NaN pattern explicitly | ||
76 | target/i386: Set default NaN pattern explicitly | ||
77 | target/hppa: Set default NaN pattern explicitly | ||
78 | target/alpha: Set default NaN pattern explicitly | ||
79 | target/arm: Set default NaN pattern explicitly | ||
80 | target/loongarch: Set default NaN pattern explicitly | ||
81 | target/m68k: Set default NaN pattern explicitly | ||
82 | target/mips: Set default NaN pattern explicitly | ||
83 | target/openrisc: Set default NaN pattern explicitly | ||
84 | target/ppc: Set default NaN pattern explicitly | ||
85 | target/sh4: Set default NaN pattern explicitly | ||
86 | target/rx: Set default NaN pattern explicitly | ||
87 | target/s390x: Set default NaN pattern explicitly | ||
88 | target/sparc: Set default NaN pattern explicitly | ||
89 | target/xtensa: Set default NaN pattern explicitly | ||
90 | target/hexagon: Set default NaN pattern explicitly | ||
91 | target/riscv: Set default NaN pattern explicitly | ||
92 | target/tricore: Set default NaN pattern explicitly | ||
93 | fpu: Remove default handling for dnan_pattern | ||
43 | 94 | ||
44 | Peter Maydell (7): | 95 | Richard Henderson (11): |
45 | qemu-options.hx: Fix formatting of -machine memory-backend option | 96 | target/arm: Copy entire float_status in is_ebf |
46 | target/arm: Enforce that M-profile SP low 2 bits are always zero | 97 | softfloat: Inline pickNaNMulAdd |
47 | target/arm: Add missing 'return's after calling v7m_exception_taken() | 98 | softfloat: Use goto for default nan case in pick_nan_muladd |
48 | target/arm: Report M-profile alignment faults correctly to the guest | 99 | softfloat: Remove which from parts_pick_nan_muladd |
49 | hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts | 100 | softfloat: Pad array size in pick_nan_muladd |
50 | hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING | 101 | softfloat: Move propagateFloatx80NaN to softfloat.c |
51 | hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS | 102 | softfloat: Use parts_pick_nan in propagateFloatx80NaN |
103 | softfloat: Inline pickNaN | ||
104 | softfloat: Share code between parts_pick_nan cases | ||
105 | softfloat: Sink frac_cmp in parts_pick_nan until needed | ||
106 | softfloat: Replace WHICH with RET in parts_pick_nan | ||
52 | 107 | ||
53 | Philippe Mathieu-Daudé (1): | 108 | Vikram Garhwal (1): |
54 | hw/arm/nseries: Display hexadecimal value with '0x' prefix | 109 | MAINTAINERS: Add correct email address for Vikram Garhwal |
55 | 110 | ||
56 | Richard Henderson (3): | 111 | MAINTAINERS | 4 +- |
57 | target/arm: Correctly bound length in sve_zcr_get_valid_len | 112 | include/fpu/softfloat-helpers.h | 38 +++- |
58 | target/arm: Export aarch64_sve_zcr_get_valid_len | 113 | include/fpu/softfloat-types.h | 89 +++++++- |
59 | target/arm: Add sve-default-vector-length cpu property | 114 | include/hw/net/imx_fec.h | 9 +- |
60 | 115 | include/hw/net/lan9118_phy.h | 37 ++++ | |
61 | docs/system/arm/cpu-features.rst | 15 ++++++++++ | 116 | include/hw/net/mii.h | 6 + |
62 | configure | 2 +- | 117 | target/mips/fpu_helper.h | 20 ++ |
63 | hw/arm/smmuv3-internal.h | 2 +- | 118 | target/sparc/helper.h | 4 +- |
64 | target/arm/cpu.h | 5 ++++ | 119 | fpu/softfloat.c | 19 ++ |
65 | target/arm/internals.h | 10 +++++++ | 120 | hw/net/imx_fec.c | 146 ++------------ |
66 | hw/arm/nseries.c | 2 +- | 121 | hw/net/lan9118.c | 137 ++----------- |
67 | hw/gpio/aspeed_gpio.c | 3 +- | 122 | hw/net/lan9118_phy.c | 222 ++++++++++++++++++++ |
68 | hw/intc/armv7m_nvic.c | 40 +++++++++++++++++++-------- | 123 | linux-user/arm/nwfpe/fpa11.c | 5 + |
69 | target/arm/cpu.c | 14 ++++++++-- | 124 | target/alpha/cpu.c | 2 + |
70 | target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++++++++++ | 125 | target/arm/cpu.c | 10 + |
71 | target/arm/gdbstub.c | 4 +++ | 126 | target/arm/tcg/vec_helper.c | 20 +- |
72 | target/arm/helper.c | 8 ++++-- | 127 | target/hexagon/cpu.c | 2 + |
73 | target/arm/m_helper.c | 24 ++++++++++++---- | 128 | target/hppa/fpu_helper.c | 12 ++ |
74 | target/arm/translate.c | 3 ++ | 129 | target/i386/tcg/fpu_helper.c | 12 ++ |
75 | target/i386/cpu.c | 2 +- | 130 | target/loongarch/tcg/fpu_helper.c | 14 +- |
76 | MAINTAINERS | 2 +- | 131 | target/m68k/cpu.c | 14 +- |
77 | qemu-options.hx | 30 +++++++++++--------- | 132 | target/m68k/fpu_helper.c | 6 +- |
78 | 17 files changed, 183 insertions(+), 43 deletions(-) | 133 | target/m68k/helper.c | 6 +- |
79 | 134 | target/microblaze/cpu.c | 2 + | |
135 | target/mips/msa.c | 10 + | ||
136 | target/openrisc/cpu.c | 2 + | ||
137 | target/ppc/cpu_init.c | 19 ++ | ||
138 | target/ppc/fpu_helper.c | 3 +- | ||
139 | target/riscv/cpu.c | 2 + | ||
140 | target/rx/cpu.c | 2 + | ||
141 | target/s390x/cpu.c | 5 + | ||
142 | target/sh4/cpu.c | 2 + | ||
143 | target/sparc/cpu.c | 6 + | ||
144 | target/sparc/fop_helper.c | 8 +- | ||
145 | target/sparc/translate.c | 4 +- | ||
146 | target/tricore/helper.c | 2 + | ||
147 | target/xtensa/cpu.c | 4 + | ||
148 | target/xtensa/fpu_helper.c | 3 +- | ||
149 | tests/fp/fp-bench.c | 7 + | ||
150 | tests/fp/fp-test-log2.c | 1 + | ||
151 | tests/fp/fp-test.c | 7 + | ||
152 | fpu/softfloat-parts.c.inc | 152 +++++++++++--- | ||
153 | fpu/softfloat-specialize.c.inc | 412 ++------------------------------------ | ||
154 | .mailmap | 5 +- | ||
155 | hw/net/Kconfig | 5 + | ||
156 | hw/net/meson.build | 1 + | ||
157 | hw/net/trace-events | 10 +- | ||
158 | 47 files changed, 778 insertions(+), 730 deletions(-) | ||
159 | create mode 100644 include/hw/net/lan9118_phy.h | ||
160 | create mode 100644 hw/net/lan9118_phy.c | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bernhard Beschow <shentey@gmail.com> | ||
1 | 2 | ||
3 | A very similar implementation of the same device exists in imx_fec. Prepare for | ||
4 | a common implementation by extracting a device model into its own files. | ||
5 | |||
6 | Some migration state has been moved into the new device model which breaks | ||
7 | migration compatibility for the following machines: | ||
8 | * smdkc210 | ||
9 | * realview-* | ||
10 | * vexpress-* | ||
11 | * kzm | ||
12 | * mps2-* | ||
13 | |||
14 | While breaking migration ABI, fix the size of the MII registers to be 16 bit, | ||
15 | as defined by IEEE 802.3u. | ||
16 | |||
17 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> | ||
18 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | Message-id: 20241102125724.532843-2-shentey@gmail.com | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | --- | ||
23 | include/hw/net/lan9118_phy.h | 37 ++++++++ | ||
24 | hw/net/lan9118.c | 137 +++++----------------------- | ||
25 | hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++ | ||
26 | hw/net/Kconfig | 4 + | ||
27 | hw/net/meson.build | 1 + | ||
28 | 5 files changed, 233 insertions(+), 115 deletions(-) | ||
29 | create mode 100644 include/hw/net/lan9118_phy.h | ||
30 | create mode 100644 hw/net/lan9118_phy.c | ||
31 | |||
32 | diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h | ||
33 | new file mode 100644 | ||
34 | index XXXXXXX..XXXXXXX | ||
35 | --- /dev/null | ||
36 | +++ b/include/hw/net/lan9118_phy.h | ||
37 | @@ -XXX,XX +XXX,XX @@ | ||
38 | +/* | ||
39 | + * SMSC LAN9118 PHY emulation | ||
40 | + * | ||
41 | + * Copyright (c) 2009 CodeSourcery, LLC. | ||
42 | + * Written by Paul Brook | ||
43 | + * | ||
44 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
45 | + * See the COPYING file in the top-level directory. | ||
46 | + */ | ||
47 | + | ||
48 | +#ifndef HW_NET_LAN9118_PHY_H | ||
49 | +#define HW_NET_LAN9118_PHY_H | ||
50 | + | ||
51 | +#include "qom/object.h" | ||
52 | +#include "hw/sysbus.h" | ||
53 | + | ||
54 | +#define TYPE_LAN9118_PHY "lan9118-phy" | ||
55 | +OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY) | ||
56 | + | ||
57 | +typedef struct Lan9118PhyState { | ||
58 | + SysBusDevice parent_obj; | ||
59 | + | ||
60 | + uint16_t status; | ||
61 | + uint16_t control; | ||
62 | + uint16_t advertise; | ||
63 | + uint16_t ints; | ||
64 | + uint16_t int_mask; | ||
65 | + qemu_irq irq; | ||
66 | + bool link_down; | ||
67 | +} Lan9118PhyState; | ||
68 | + | ||
69 | +void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down); | ||
70 | +void lan9118_phy_reset(Lan9118PhyState *s); | ||
71 | +uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg); | ||
72 | +void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val); | ||
73 | + | ||
74 | +#endif | ||
75 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | ||
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/hw/net/lan9118.c | ||
78 | +++ b/hw/net/lan9118.c | ||
79 | @@ -XXX,XX +XXX,XX @@ | ||
80 | #include "net/net.h" | ||
81 | #include "net/eth.h" | ||
82 | #include "hw/irq.h" | ||
83 | +#include "hw/net/lan9118_phy.h" | ||
84 | #include "hw/net/lan9118.h" | ||
85 | #include "hw/ptimer.h" | ||
86 | #include "hw/qdev-properties.h" | ||
87 | @@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0) | ||
88 | #define MAC_CR_RXEN 0x00000004 | ||
89 | #define MAC_CR_RESERVED 0x7f404213 | ||
90 | |||
91 | -#define PHY_INT_ENERGYON 0x80 | ||
92 | -#define PHY_INT_AUTONEG_COMPLETE 0x40 | ||
93 | -#define PHY_INT_FAULT 0x20 | ||
94 | -#define PHY_INT_DOWN 0x10 | ||
95 | -#define PHY_INT_AUTONEG_LP 0x08 | ||
96 | -#define PHY_INT_PARFAULT 0x04 | ||
97 | -#define PHY_INT_AUTONEG_PAGE 0x02 | ||
98 | - | ||
99 | #define GPT_TIMER_EN 0x20000000 | ||
100 | |||
101 | /* | ||
102 | @@ -XXX,XX +XXX,XX @@ struct lan9118_state { | ||
103 | uint32_t mac_mii_data; | ||
104 | uint32_t mac_flow; | ||
105 | |||
106 | - uint32_t phy_status; | ||
107 | - uint32_t phy_control; | ||
108 | - uint32_t phy_advertise; | ||
109 | - uint32_t phy_int; | ||
110 | - uint32_t phy_int_mask; | ||
111 | + Lan9118PhyState mii; | ||
112 | + IRQState mii_irq; | ||
113 | |||
114 | int32_t eeprom_writable; | ||
115 | uint8_t eeprom[128]; | ||
116 | @@ -XXX,XX +XXX,XX @@ struct lan9118_state { | ||
117 | |||
118 | static const VMStateDescription vmstate_lan9118 = { | ||
119 | .name = "lan9118", | ||
120 | - .version_id = 2, | ||
121 | - .minimum_version_id = 1, | ||
122 | + .version_id = 3, | ||
123 | + .minimum_version_id = 3, | ||
124 | .fields = (const VMStateField[]) { | ||
125 | VMSTATE_PTIMER(timer, lan9118_state), | ||
126 | VMSTATE_UINT32(irq_cfg, lan9118_state), | ||
127 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = { | ||
128 | VMSTATE_UINT32(mac_mii_acc, lan9118_state), | ||
129 | VMSTATE_UINT32(mac_mii_data, lan9118_state), | ||
130 | VMSTATE_UINT32(mac_flow, lan9118_state), | ||
131 | - VMSTATE_UINT32(phy_status, lan9118_state), | ||
132 | - VMSTATE_UINT32(phy_control, lan9118_state), | ||
133 | - VMSTATE_UINT32(phy_advertise, lan9118_state), | ||
134 | - VMSTATE_UINT32(phy_int, lan9118_state), | ||
135 | - VMSTATE_UINT32(phy_int_mask, lan9118_state), | ||
136 | VMSTATE_INT32(eeprom_writable, lan9118_state), | ||
137 | VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128), | ||
138 | VMSTATE_INT32(tx_fifo_size, lan9118_state), | ||
139 | @@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s) | ||
140 | lan9118_mac_changed(s); | ||
141 | } | ||
142 | |||
143 | -static void phy_update_irq(lan9118_state *s) | ||
144 | +static void lan9118_update_irq(void *opaque, int n, int level) | ||
145 | { | ||
146 | - if (s->phy_int & s->phy_int_mask) { | ||
147 | + lan9118_state *s = opaque; | ||
148 | + | ||
149 | + if (level) { | ||
150 | s->int_sts |= PHY_INT; | ||
151 | } else { | ||
152 | s->int_sts &= ~PHY_INT; | ||
153 | @@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s) | ||
154 | lan9118_update(s); | ||
155 | } | ||
156 | |||
157 | -static void phy_update_link(lan9118_state *s) | ||
158 | -{ | ||
159 | - /* Autonegotiation status mirrors link status. */ | ||
160 | - if (qemu_get_queue(s->nic)->link_down) { | ||
161 | - s->phy_status &= ~0x0024; | ||
162 | - s->phy_int |= PHY_INT_DOWN; | ||
163 | - } else { | ||
164 | - s->phy_status |= 0x0024; | ||
165 | - s->phy_int |= PHY_INT_ENERGYON; | ||
166 | - s->phy_int |= PHY_INT_AUTONEG_COMPLETE; | ||
167 | - } | ||
168 | - phy_update_irq(s); | ||
169 | -} | ||
170 | - | ||
171 | static void lan9118_set_link(NetClientState *nc) | ||
172 | { | ||
173 | - phy_update_link(qemu_get_nic_opaque(nc)); | ||
174 | -} | ||
175 | - | ||
176 | -static void phy_reset(lan9118_state *s) | ||
177 | -{ | ||
178 | - s->phy_status = 0x7809; | ||
179 | - s->phy_control = 0x3000; | ||
180 | - s->phy_advertise = 0x01e1; | ||
181 | - s->phy_int_mask = 0; | ||
182 | - s->phy_int = 0; | ||
183 | - phy_update_link(s); | ||
184 | + lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii, | ||
185 | + nc->link_down); | ||
186 | } | ||
187 | |||
188 | static void lan9118_reset(DeviceState *d) | ||
189 | @@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d) | ||
190 | s->read_word_n = 0; | ||
191 | s->write_word_n = 0; | ||
192 | |||
193 | - phy_reset(s); | ||
194 | - | ||
195 | s->eeprom_writable = 0; | ||
196 | lan9118_reload_eeprom(s); | ||
197 | } | ||
198 | @@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s) | ||
199 | uint32_t status; | ||
200 | |||
201 | /* FIXME: Honor TX disable, and allow queueing of packets. */ | ||
202 | - if (s->phy_control & 0x4000) { | ||
203 | + if (s->mii.control & 0x4000) { | ||
204 | /* This assumes the receive routine doesn't touch the VLANClient. */ | ||
205 | qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len); | ||
206 | } else { | ||
207 | @@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val) | ||
208 | } | ||
209 | } | ||
210 | |||
211 | -static uint32_t do_phy_read(lan9118_state *s, int reg) | ||
212 | -{ | ||
213 | - uint32_t val; | ||
214 | - | ||
215 | - switch (reg) { | ||
216 | - case 0: /* Basic Control */ | ||
217 | - return s->phy_control; | ||
218 | - case 1: /* Basic Status */ | ||
219 | - return s->phy_status; | ||
220 | - case 2: /* ID1 */ | ||
221 | - return 0x0007; | ||
222 | - case 3: /* ID2 */ | ||
223 | - return 0xc0d1; | ||
224 | - case 4: /* Auto-neg advertisement */ | ||
225 | - return s->phy_advertise; | ||
226 | - case 5: /* Auto-neg Link Partner Ability */ | ||
227 | - return 0x0f71; | ||
228 | - case 6: /* Auto-neg Expansion */ | ||
229 | - return 1; | ||
230 | - /* TODO 17, 18, 27, 29, 30, 31 */ | ||
231 | - case 29: /* Interrupt source. */ | ||
232 | - val = s->phy_int; | ||
233 | - s->phy_int = 0; | ||
234 | - phy_update_irq(s); | ||
235 | - return val; | ||
236 | - case 30: /* Interrupt mask */ | ||
237 | - return s->phy_int_mask; | ||
238 | - default: | ||
239 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
240 | - "do_phy_read: PHY read reg %d\n", reg); | ||
241 | - return 0; | ||
242 | - } | ||
243 | -} | ||
244 | - | ||
245 | -static void do_phy_write(lan9118_state *s, int reg, uint32_t val) | ||
246 | -{ | ||
247 | - switch (reg) { | ||
248 | - case 0: /* Basic Control */ | ||
249 | - if (val & 0x8000) { | ||
250 | - phy_reset(s); | ||
251 | - break; | ||
252 | - } | ||
253 | - s->phy_control = val & 0x7980; | ||
254 | - /* Complete autonegotiation immediately. */ | ||
255 | - if (val & 0x1000) { | ||
256 | - s->phy_status |= 0x0020; | ||
257 | - } | ||
258 | - break; | ||
259 | - case 4: /* Auto-neg advertisement */ | ||
260 | - s->phy_advertise = (val & 0x2d7f) | 0x80; | ||
261 | - break; | ||
262 | - /* TODO 17, 18, 27, 31 */ | ||
263 | - case 30: /* Interrupt mask */ | ||
264 | - s->phy_int_mask = val & 0xff; | ||
265 | - phy_update_irq(s); | ||
266 | - break; | ||
267 | - default: | ||
268 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
269 | - "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val); | ||
270 | - } | ||
271 | -} | ||
272 | - | ||
273 | static void do_mac_write(lan9118_state *s, int reg, uint32_t val) | ||
274 | { | ||
275 | switch (reg) { | ||
276 | @@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val) | ||
277 | if (val & 2) { | ||
278 | DPRINTF("PHY write %d = 0x%04x\n", | ||
279 | (val >> 6) & 0x1f, s->mac_mii_data); | ||
280 | - do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data); | ||
281 | + lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data); | ||
282 | } else { | ||
283 | - s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f); | ||
284 | + s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f); | ||
285 | DPRINTF("PHY read %d = 0x%04x\n", | ||
286 | (val >> 6) & 0x1f, s->mac_mii_data); | ||
287 | } | ||
288 | @@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset, | ||
289 | break; | ||
290 | case CSR_PMT_CTRL: | ||
291 | if (val & 0x400) { | ||
292 | - phy_reset(s); | ||
293 | + lan9118_phy_reset(&s->mii); | ||
294 | } | ||
295 | s->pmt_ctrl &= ~0x34e; | ||
296 | s->pmt_ctrl |= (val & 0x34e); | ||
297 | @@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp) | ||
298 | const MemoryRegionOps *mem_ops = | ||
299 | s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops; | ||
300 | |||
301 | + qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0); | ||
302 | + object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); | ||
303 | + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { | ||
304 | + return; | ||
305 | + } | ||
306 | + qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); | ||
307 | + | ||
308 | memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s, | ||
309 | "lan9118-mmio", 0x100); | ||
310 | sysbus_init_mmio(sbd, &s->mmio); | ||
311 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c | ||
312 | new file mode 100644 | ||
313 | index XXXXXXX..XXXXXXX | ||
314 | --- /dev/null | ||
315 | +++ b/hw/net/lan9118_phy.c | ||
316 | @@ -XXX,XX +XXX,XX @@ | ||
317 | +/* | ||
318 | + * SMSC LAN9118 PHY emulation | ||
319 | + * | ||
320 | + * Copyright (c) 2009 CodeSourcery, LLC. | ||
321 | + * Written by Paul Brook | ||
322 | + * | ||
323 | + * This code is licensed under the GNU GPL v2 | ||
324 | + * | ||
325 | + * Contributions after 2012-01-13 are licensed under the terms of the | ||
326 | + * GNU GPL, version 2 or (at your option) any later version. | ||
327 | + */ | ||
328 | + | ||
329 | +#include "qemu/osdep.h" | ||
330 | +#include "hw/net/lan9118_phy.h" | ||
331 | +#include "hw/irq.h" | ||
332 | +#include "hw/resettable.h" | ||
333 | +#include "migration/vmstate.h" | ||
334 | +#include "qemu/log.h" | ||
335 | + | ||
336 | +#define PHY_INT_ENERGYON (1 << 7) | ||
337 | +#define PHY_INT_AUTONEG_COMPLETE (1 << 6) | ||
338 | +#define PHY_INT_FAULT (1 << 5) | ||
339 | +#define PHY_INT_DOWN (1 << 4) | ||
340 | +#define PHY_INT_AUTONEG_LP (1 << 3) | ||
341 | +#define PHY_INT_PARFAULT (1 << 2) | ||
342 | +#define PHY_INT_AUTONEG_PAGE (1 << 1) | ||
343 | + | ||
344 | +static void lan9118_phy_update_irq(Lan9118PhyState *s) | ||
345 | +{ | ||
346 | + qemu_set_irq(s->irq, !!(s->ints & s->int_mask)); | ||
347 | +} | ||
348 | + | ||
349 | +uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) | ||
350 | +{ | ||
351 | + uint16_t val; | ||
352 | + | ||
353 | + switch (reg) { | ||
354 | + case 0: /* Basic Control */ | ||
355 | + return s->control; | ||
356 | + case 1: /* Basic Status */ | ||
357 | + return s->status; | ||
358 | + case 2: /* ID1 */ | ||
359 | + return 0x0007; | ||
360 | + case 3: /* ID2 */ | ||
361 | + return 0xc0d1; | ||
362 | + case 4: /* Auto-neg advertisement */ | ||
363 | + return s->advertise; | ||
364 | + case 5: /* Auto-neg Link Partner Ability */ | ||
365 | + return 0x0f71; | ||
366 | + case 6: /* Auto-neg Expansion */ | ||
367 | + return 1; | ||
368 | + /* TODO 17, 18, 27, 29, 30, 31 */ | ||
369 | + case 29: /* Interrupt source. */ | ||
370 | + val = s->ints; | ||
371 | + s->ints = 0; | ||
372 | + lan9118_phy_update_irq(s); | ||
373 | + return val; | ||
374 | + case 30: /* Interrupt mask */ | ||
375 | + return s->int_mask; | ||
376 | + default: | ||
377 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
378 | + "lan9118_phy_read: PHY read reg %d\n", reg); | ||
379 | + return 0; | ||
380 | + } | ||
381 | +} | ||
382 | + | ||
383 | +void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
384 | +{ | ||
385 | + switch (reg) { | ||
386 | + case 0: /* Basic Control */ | ||
387 | + if (val & 0x8000) { | ||
388 | + lan9118_phy_reset(s); | ||
389 | + break; | ||
390 | + } | ||
391 | + s->control = val & 0x7980; | ||
392 | + /* Complete autonegotiation immediately. */ | ||
393 | + if (val & 0x1000) { | ||
394 | + s->status |= 0x0020; | ||
395 | + } | ||
396 | + break; | ||
397 | + case 4: /* Auto-neg advertisement */ | ||
398 | + s->advertise = (val & 0x2d7f) | 0x80; | ||
399 | + break; | ||
400 | + /* TODO 17, 18, 27, 31 */ | ||
401 | + case 30: /* Interrupt mask */ | ||
402 | + s->int_mask = val & 0xff; | ||
403 | + lan9118_phy_update_irq(s); | ||
404 | + break; | ||
405 | + default: | ||
406 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
407 | + "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val); | ||
408 | + } | ||
409 | +} | ||
410 | + | ||
411 | +void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
412 | +{ | ||
413 | + s->link_down = link_down; | ||
414 | + | ||
415 | + /* Autonegotiation status mirrors link status. */ | ||
416 | + if (link_down) { | ||
417 | + s->status &= ~0x0024; | ||
418 | + s->ints |= PHY_INT_DOWN; | ||
419 | + } else { | ||
420 | + s->status |= 0x0024; | ||
421 | + s->ints |= PHY_INT_ENERGYON; | ||
422 | + s->ints |= PHY_INT_AUTONEG_COMPLETE; | ||
423 | + } | ||
424 | + lan9118_phy_update_irq(s); | ||
425 | +} | ||
426 | + | ||
427 | +void lan9118_phy_reset(Lan9118PhyState *s) | ||
428 | +{ | ||
429 | + s->control = 0x3000; | ||
430 | + s->status = 0x7809; | ||
431 | + s->advertise = 0x01e1; | ||
432 | + s->int_mask = 0; | ||
433 | + s->ints = 0; | ||
434 | + lan9118_phy_update_link(s, s->link_down); | ||
435 | +} | ||
436 | + | ||
437 | +static void lan9118_phy_reset_hold(Object *obj, ResetType type) | ||
438 | +{ | ||
439 | + Lan9118PhyState *s = LAN9118_PHY(obj); | ||
440 | + | ||
441 | + lan9118_phy_reset(s); | ||
442 | +} | ||
443 | + | ||
444 | +static void lan9118_phy_init(Object *obj) | ||
445 | +{ | ||
446 | + Lan9118PhyState *s = LAN9118_PHY(obj); | ||
447 | + | ||
448 | + qdev_init_gpio_out(DEVICE(s), &s->irq, 1); | ||
449 | +} | ||
450 | + | ||
451 | +static const VMStateDescription vmstate_lan9118_phy = { | ||
452 | + .name = "lan9118-phy", | ||
453 | + .version_id = 1, | ||
454 | + .minimum_version_id = 1, | ||
455 | + .fields = (const VMStateField[]) { | ||
456 | + VMSTATE_UINT16(control, Lan9118PhyState), | ||
457 | + VMSTATE_UINT16(status, Lan9118PhyState), | ||
458 | + VMSTATE_UINT16(advertise, Lan9118PhyState), | ||
459 | + VMSTATE_UINT16(ints, Lan9118PhyState), | ||
460 | + VMSTATE_UINT16(int_mask, Lan9118PhyState), | ||
461 | + VMSTATE_BOOL(link_down, Lan9118PhyState), | ||
462 | + VMSTATE_END_OF_LIST() | ||
463 | + } | ||
464 | +}; | ||
465 | + | ||
466 | +static void lan9118_phy_class_init(ObjectClass *klass, void *data) | ||
467 | +{ | ||
468 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
469 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
470 | + | ||
471 | + rc->phases.hold = lan9118_phy_reset_hold; | ||
472 | + dc->vmsd = &vmstate_lan9118_phy; | ||
473 | +} | ||
474 | + | ||
475 | +static const TypeInfo types[] = { | ||
476 | + { | ||
477 | + .name = TYPE_LAN9118_PHY, | ||
478 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
479 | + .instance_size = sizeof(Lan9118PhyState), | ||
480 | + .instance_init = lan9118_phy_init, | ||
481 | + .class_init = lan9118_phy_class_init, | ||
482 | + } | ||
483 | +}; | ||
484 | + | ||
485 | +DEFINE_TYPES(types) | ||
486 | diff --git a/hw/net/Kconfig b/hw/net/Kconfig | ||
487 | index XXXXXXX..XXXXXXX 100644 | ||
488 | --- a/hw/net/Kconfig | ||
489 | +++ b/hw/net/Kconfig | ||
490 | @@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI | ||
491 | config SMC91C111 | ||
492 | bool | ||
493 | |||
494 | +config LAN9118_PHY | ||
495 | + bool | ||
496 | + | ||
497 | config LAN9118 | ||
498 | bool | ||
499 | + select LAN9118_PHY | ||
500 | select PTIMER | ||
501 | |||
502 | config NE2000_ISA | ||
503 | diff --git a/hw/net/meson.build b/hw/net/meson.build | ||
504 | index XXXXXXX..XXXXXXX 100644 | ||
505 | --- a/hw/net/meson.build | ||
506 | +++ b/hw/net/meson.build | ||
507 | @@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c')) | ||
508 | |||
509 | system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c')) | ||
510 | system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c')) | ||
511 | +system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c')) | ||
512 | system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c')) | ||
513 | system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c')) | ||
514 | system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c')) | ||
515 | -- | ||
516 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bernhard Beschow <shentey@gmail.com> | ||
1 | 2 | ||
3 | imx_fec models the same PHY as lan9118_phy. The code is almost the same with | ||
4 | imx_fec having more logging and tracing. Merge these improvements into | ||
5 | lan9118_phy and reuse in imx_fec to fix the code duplication. | ||
6 | |||
7 | Some migration state how resides in the new device model which breaks migration | ||
8 | compatibility for the following machines: | ||
9 | * imx25-pdk | ||
10 | * sabrelite | ||
11 | * mcimx7d-sabre | ||
12 | * mcimx6ul-evk | ||
13 | |||
14 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> | ||
15 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | Message-id: 20241102125724.532843-3-shentey@gmail.com | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | --- | ||
20 | include/hw/net/imx_fec.h | 9 ++- | ||
21 | hw/net/imx_fec.c | 146 ++++----------------------------------- | ||
22 | hw/net/lan9118_phy.c | 82 ++++++++++++++++------ | ||
23 | hw/net/Kconfig | 1 + | ||
24 | hw/net/trace-events | 10 +-- | ||
25 | 5 files changed, 85 insertions(+), 163 deletions(-) | ||
26 | |||
27 | diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/include/hw/net/imx_fec.h | ||
30 | +++ b/include/hw/net/imx_fec.h | ||
31 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC) | ||
32 | #define TYPE_IMX_ENET "imx.enet" | ||
33 | |||
34 | #include "hw/sysbus.h" | ||
35 | +#include "hw/net/lan9118_phy.h" | ||
36 | +#include "hw/irq.h" | ||
37 | #include "net/net.h" | ||
38 | |||
39 | #define ENET_EIR 1 | ||
40 | @@ -XXX,XX +XXX,XX @@ struct IMXFECState { | ||
41 | uint32_t tx_descriptor[ENET_TX_RING_NUM]; | ||
42 | uint32_t tx_ring_num; | ||
43 | |||
44 | - uint32_t phy_status; | ||
45 | - uint32_t phy_control; | ||
46 | - uint32_t phy_advertise; | ||
47 | - uint32_t phy_int; | ||
48 | - uint32_t phy_int_mask; | ||
49 | + Lan9118PhyState mii; | ||
50 | + IRQState mii_irq; | ||
51 | uint32_t phy_num; | ||
52 | bool phy_connected; | ||
53 | struct IMXFECState *phy_consumer; | ||
54 | diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/hw/net/imx_fec.c | ||
57 | +++ b/hw/net/imx_fec.c | ||
58 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = { | ||
59 | |||
60 | static const VMStateDescription vmstate_imx_eth = { | ||
61 | .name = TYPE_IMX_FEC, | ||
62 | - .version_id = 2, | ||
63 | - .minimum_version_id = 2, | ||
64 | + .version_id = 3, | ||
65 | + .minimum_version_id = 3, | ||
66 | .fields = (const VMStateField[]) { | ||
67 | VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX), | ||
68 | VMSTATE_UINT32(rx_descriptor, IMXFECState), | ||
69 | VMSTATE_UINT32(tx_descriptor[0], IMXFECState), | ||
70 | - VMSTATE_UINT32(phy_status, IMXFECState), | ||
71 | - VMSTATE_UINT32(phy_control, IMXFECState), | ||
72 | - VMSTATE_UINT32(phy_advertise, IMXFECState), | ||
73 | - VMSTATE_UINT32(phy_int, IMXFECState), | ||
74 | - VMSTATE_UINT32(phy_int_mask, IMXFECState), | ||
75 | VMSTATE_END_OF_LIST() | ||
76 | }, | ||
77 | .subsections = (const VMStateDescription * const []) { | ||
78 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = { | ||
79 | }, | ||
80 | }; | ||
81 | |||
82 | -#define PHY_INT_ENERGYON (1 << 7) | ||
83 | -#define PHY_INT_AUTONEG_COMPLETE (1 << 6) | ||
84 | -#define PHY_INT_FAULT (1 << 5) | ||
85 | -#define PHY_INT_DOWN (1 << 4) | ||
86 | -#define PHY_INT_AUTONEG_LP (1 << 3) | ||
87 | -#define PHY_INT_PARFAULT (1 << 2) | ||
88 | -#define PHY_INT_AUTONEG_PAGE (1 << 1) | ||
89 | - | ||
90 | static void imx_eth_update(IMXFECState *s); | ||
91 | |||
92 | /* | ||
93 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s); | ||
94 | * For now we don't handle any GPIO/interrupt line, so the OS will | ||
95 | * have to poll for the PHY status. | ||
96 | */ | ||
97 | -static void imx_phy_update_irq(IMXFECState *s) | ||
98 | +static void imx_phy_update_irq(void *opaque, int n, int level) | ||
99 | { | ||
100 | - imx_eth_update(s); | ||
101 | -} | ||
102 | - | ||
103 | -static void imx_phy_update_link(IMXFECState *s) | ||
104 | -{ | ||
105 | - /* Autonegotiation status mirrors link status. */ | ||
106 | - if (qemu_get_queue(s->nic)->link_down) { | ||
107 | - trace_imx_phy_update_link("down"); | ||
108 | - s->phy_status &= ~0x0024; | ||
109 | - s->phy_int |= PHY_INT_DOWN; | ||
110 | - } else { | ||
111 | - trace_imx_phy_update_link("up"); | ||
112 | - s->phy_status |= 0x0024; | ||
113 | - s->phy_int |= PHY_INT_ENERGYON; | ||
114 | - s->phy_int |= PHY_INT_AUTONEG_COMPLETE; | ||
115 | - } | ||
116 | - imx_phy_update_irq(s); | ||
117 | + imx_eth_update(opaque); | ||
118 | } | ||
119 | |||
120 | static void imx_eth_set_link(NetClientState *nc) | ||
121 | { | ||
122 | - imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc))); | ||
123 | -} | ||
124 | - | ||
125 | -static void imx_phy_reset(IMXFECState *s) | ||
126 | -{ | ||
127 | - trace_imx_phy_reset(); | ||
128 | - | ||
129 | - s->phy_status = 0x7809; | ||
130 | - s->phy_control = 0x3000; | ||
131 | - s->phy_advertise = 0x01e1; | ||
132 | - s->phy_int_mask = 0; | ||
133 | - s->phy_int = 0; | ||
134 | - imx_phy_update_link(s); | ||
135 | + lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii, | ||
136 | + nc->link_down); | ||
137 | } | ||
138 | |||
139 | static uint32_t imx_phy_read(IMXFECState *s, int reg) | ||
140 | { | ||
141 | - uint32_t val; | ||
142 | uint32_t phy = reg / 32; | ||
143 | |||
144 | if (!s->phy_connected) { | ||
145 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg) | ||
146 | |||
147 | reg %= 32; | ||
148 | |||
149 | - switch (reg) { | ||
150 | - case 0: /* Basic Control */ | ||
151 | - val = s->phy_control; | ||
152 | - break; | ||
153 | - case 1: /* Basic Status */ | ||
154 | - val = s->phy_status; | ||
155 | - break; | ||
156 | - case 2: /* ID1 */ | ||
157 | - val = 0x0007; | ||
158 | - break; | ||
159 | - case 3: /* ID2 */ | ||
160 | - val = 0xc0d1; | ||
161 | - break; | ||
162 | - case 4: /* Auto-neg advertisement */ | ||
163 | - val = s->phy_advertise; | ||
164 | - break; | ||
165 | - case 5: /* Auto-neg Link Partner Ability */ | ||
166 | - val = 0x0f71; | ||
167 | - break; | ||
168 | - case 6: /* Auto-neg Expansion */ | ||
169 | - val = 1; | ||
170 | - break; | ||
171 | - case 29: /* Interrupt source. */ | ||
172 | - val = s->phy_int; | ||
173 | - s->phy_int = 0; | ||
174 | - imx_phy_update_irq(s); | ||
175 | - break; | ||
176 | - case 30: /* Interrupt mask */ | ||
177 | - val = s->phy_int_mask; | ||
178 | - break; | ||
179 | - case 17: | ||
180 | - case 18: | ||
181 | - case 27: | ||
182 | - case 31: | ||
183 | - qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n", | ||
184 | - TYPE_IMX_FEC, __func__, reg); | ||
185 | - val = 0; | ||
186 | - break; | ||
187 | - default: | ||
188 | - qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", | ||
189 | - TYPE_IMX_FEC, __func__, reg); | ||
190 | - val = 0; | ||
191 | - break; | ||
192 | - } | ||
193 | - | ||
194 | - trace_imx_phy_read(val, phy, reg); | ||
195 | - | ||
196 | - return val; | ||
197 | + return lan9118_phy_read(&s->mii, reg); | ||
198 | } | ||
199 | |||
200 | static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
201 | @@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
202 | |||
203 | reg %= 32; | ||
204 | |||
205 | - trace_imx_phy_write(val, phy, reg); | ||
206 | - | ||
207 | - switch (reg) { | ||
208 | - case 0: /* Basic Control */ | ||
209 | - if (val & 0x8000) { | ||
210 | - imx_phy_reset(s); | ||
211 | - } else { | ||
212 | - s->phy_control = val & 0x7980; | ||
213 | - /* Complete autonegotiation immediately. */ | ||
214 | - if (val & 0x1000) { | ||
215 | - s->phy_status |= 0x0020; | ||
216 | - } | ||
217 | - } | ||
218 | - break; | ||
219 | - case 4: /* Auto-neg advertisement */ | ||
220 | - s->phy_advertise = (val & 0x2d7f) | 0x80; | ||
221 | - break; | ||
222 | - case 30: /* Interrupt mask */ | ||
223 | - s->phy_int_mask = val & 0xff; | ||
224 | - imx_phy_update_irq(s); | ||
225 | - break; | ||
226 | - case 17: | ||
227 | - case 18: | ||
228 | - case 27: | ||
229 | - case 31: | ||
230 | - qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n", | ||
231 | - TYPE_IMX_FEC, __func__, reg); | ||
232 | - break; | ||
233 | - default: | ||
234 | - qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n", | ||
235 | - TYPE_IMX_FEC, __func__, reg); | ||
236 | - break; | ||
237 | - } | ||
238 | + lan9118_phy_write(&s->mii, reg, val); | ||
239 | } | ||
240 | |||
241 | static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr) | ||
242 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d) | ||
243 | |||
244 | s->rx_descriptor = 0; | ||
245 | memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor)); | ||
246 | - | ||
247 | - /* We also reset the PHY */ | ||
248 | - imx_phy_reset(s); | ||
249 | } | ||
250 | |||
251 | static uint32_t imx_default_read(IMXFECState *s, uint32_t index) | ||
252 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp) | ||
253 | sysbus_init_irq(sbd, &s->irq[0]); | ||
254 | sysbus_init_irq(sbd, &s->irq[1]); | ||
255 | |||
256 | + qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0); | ||
257 | + object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY); | ||
258 | + if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) { | ||
259 | + return; | ||
260 | + } | ||
261 | + qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq); | ||
262 | + | ||
263 | qemu_macaddr_default_if_unset(&s->conf.macaddr); | ||
264 | |||
265 | s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf, | ||
266 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c | ||
267 | index XXXXXXX..XXXXXXX 100644 | ||
268 | --- a/hw/net/lan9118_phy.c | ||
269 | +++ b/hw/net/lan9118_phy.c | ||
270 | @@ -XXX,XX +XXX,XX @@ | ||
271 | * Copyright (c) 2009 CodeSourcery, LLC. | ||
272 | * Written by Paul Brook | ||
273 | * | ||
274 | + * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net> | ||
275 | + * | ||
276 | * This code is licensed under the GNU GPL v2 | ||
277 | * | ||
278 | * Contributions after 2012-01-13 are licensed under the terms of the | ||
279 | @@ -XXX,XX +XXX,XX @@ | ||
280 | #include "hw/resettable.h" | ||
281 | #include "migration/vmstate.h" | ||
282 | #include "qemu/log.h" | ||
283 | +#include "trace.h" | ||
284 | |||
285 | #define PHY_INT_ENERGYON (1 << 7) | ||
286 | #define PHY_INT_AUTONEG_COMPLETE (1 << 6) | ||
287 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) | ||
288 | |||
289 | switch (reg) { | ||
290 | case 0: /* Basic Control */ | ||
291 | - return s->control; | ||
292 | + val = s->control; | ||
293 | + break; | ||
294 | case 1: /* Basic Status */ | ||
295 | - return s->status; | ||
296 | + val = s->status; | ||
297 | + break; | ||
298 | case 2: /* ID1 */ | ||
299 | - return 0x0007; | ||
300 | + val = 0x0007; | ||
301 | + break; | ||
302 | case 3: /* ID2 */ | ||
303 | - return 0xc0d1; | ||
304 | + val = 0xc0d1; | ||
305 | + break; | ||
306 | case 4: /* Auto-neg advertisement */ | ||
307 | - return s->advertise; | ||
308 | + val = s->advertise; | ||
309 | + break; | ||
310 | case 5: /* Auto-neg Link Partner Ability */ | ||
311 | - return 0x0f71; | ||
312 | + val = 0x0f71; | ||
313 | + break; | ||
314 | case 6: /* Auto-neg Expansion */ | ||
315 | - return 1; | ||
316 | - /* TODO 17, 18, 27, 29, 30, 31 */ | ||
317 | + val = 1; | ||
318 | + break; | ||
319 | case 29: /* Interrupt source. */ | ||
320 | val = s->ints; | ||
321 | s->ints = 0; | ||
322 | lan9118_phy_update_irq(s); | ||
323 | - return val; | ||
324 | + break; | ||
325 | case 30: /* Interrupt mask */ | ||
326 | - return s->int_mask; | ||
327 | + val = s->int_mask; | ||
328 | + break; | ||
329 | + case 17: | ||
330 | + case 18: | ||
331 | + case 27: | ||
332 | + case 31: | ||
333 | + qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", | ||
334 | + __func__, reg); | ||
335 | + val = 0; | ||
336 | + break; | ||
337 | default: | ||
338 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
339 | - "lan9118_phy_read: PHY read reg %d\n", reg); | ||
340 | - return 0; | ||
341 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", | ||
342 | + __func__, reg); | ||
343 | + val = 0; | ||
344 | + break; | ||
345 | } | ||
346 | + | ||
347 | + trace_lan9118_phy_read(val, reg); | ||
348 | + | ||
349 | + return val; | ||
350 | } | ||
351 | |||
352 | void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
353 | { | ||
354 | + trace_lan9118_phy_write(val, reg); | ||
355 | + | ||
356 | switch (reg) { | ||
357 | case 0: /* Basic Control */ | ||
358 | if (val & 0x8000) { | ||
359 | lan9118_phy_reset(s); | ||
360 | - break; | ||
361 | - } | ||
362 | - s->control = val & 0x7980; | ||
363 | - /* Complete autonegotiation immediately. */ | ||
364 | - if (val & 0x1000) { | ||
365 | - s->status |= 0x0020; | ||
366 | + } else { | ||
367 | + s->control = val & 0x7980; | ||
368 | + /* Complete autonegotiation immediately. */ | ||
369 | + if (val & 0x1000) { | ||
370 | + s->status |= 0x0020; | ||
371 | + } | ||
372 | } | ||
373 | break; | ||
374 | case 4: /* Auto-neg advertisement */ | ||
375 | s->advertise = (val & 0x2d7f) | 0x80; | ||
376 | break; | ||
377 | - /* TODO 17, 18, 27, 31 */ | ||
378 | case 30: /* Interrupt mask */ | ||
379 | s->int_mask = val & 0xff; | ||
380 | lan9118_phy_update_irq(s); | ||
381 | break; | ||
382 | + case 17: | ||
383 | + case 18: | ||
384 | + case 27: | ||
385 | + case 31: | ||
386 | + qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", | ||
387 | + __func__, reg); | ||
388 | + break; | ||
389 | default: | ||
390 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
391 | - "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val); | ||
392 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", | ||
393 | + __func__, reg); | ||
394 | + break; | ||
395 | } | ||
396 | } | ||
397 | |||
398 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
399 | |||
400 | /* Autonegotiation status mirrors link status. */ | ||
401 | if (link_down) { | ||
402 | + trace_lan9118_phy_update_link("down"); | ||
403 | s->status &= ~0x0024; | ||
404 | s->ints |= PHY_INT_DOWN; | ||
405 | } else { | ||
406 | + trace_lan9118_phy_update_link("up"); | ||
407 | s->status |= 0x0024; | ||
408 | s->ints |= PHY_INT_ENERGYON; | ||
409 | s->ints |= PHY_INT_AUTONEG_COMPLETE; | ||
410 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
411 | |||
412 | void lan9118_phy_reset(Lan9118PhyState *s) | ||
413 | { | ||
414 | + trace_lan9118_phy_reset(); | ||
415 | + | ||
416 | s->control = 0x3000; | ||
417 | s->status = 0x7809; | ||
418 | s->advertise = 0x01e1; | ||
419 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = { | ||
420 | .version_id = 1, | ||
421 | .minimum_version_id = 1, | ||
422 | .fields = (const VMStateField[]) { | ||
423 | - VMSTATE_UINT16(control, Lan9118PhyState), | ||
424 | VMSTATE_UINT16(status, Lan9118PhyState), | ||
425 | + VMSTATE_UINT16(control, Lan9118PhyState), | ||
426 | VMSTATE_UINT16(advertise, Lan9118PhyState), | ||
427 | VMSTATE_UINT16(ints, Lan9118PhyState), | ||
428 | VMSTATE_UINT16(int_mask, Lan9118PhyState), | ||
429 | diff --git a/hw/net/Kconfig b/hw/net/Kconfig | ||
430 | index XXXXXXX..XXXXXXX 100644 | ||
431 | --- a/hw/net/Kconfig | ||
432 | +++ b/hw/net/Kconfig | ||
433 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC | ||
434 | |||
435 | config IMX_FEC | ||
436 | bool | ||
437 | + select LAN9118_PHY | ||
438 | |||
439 | config CADENCE | ||
440 | bool | ||
441 | diff --git a/hw/net/trace-events b/hw/net/trace-events | ||
442 | index XXXXXXX..XXXXXXX 100644 | ||
443 | --- a/hw/net/trace-events | ||
444 | +++ b/hw/net/trace-events | ||
445 | @@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u" | ||
446 | allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64 | ||
447 | allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64 | ||
448 | |||
449 | +# lan9118_phy.c | ||
450 | +lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16 | ||
451 | +lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16 | ||
452 | +lan9118_phy_update_link(const char *s) "%s" | ||
453 | +lan9118_phy_reset(void) "" | ||
454 | + | ||
455 | # lance.c | ||
456 | lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x" | ||
457 | lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x" | ||
458 | @@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries" | ||
459 | i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION" | ||
460 | |||
461 | # imx_fec.c | ||
462 | -imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]" | ||
463 | imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)" | ||
464 | -imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]" | ||
465 | imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)" | ||
466 | -imx_phy_update_link(const char *s) "%s" | ||
467 | -imx_phy_reset(void) "" | ||
468 | imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" | ||
469 | imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x" | ||
470 | imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit" | ||
471 | -- | ||
472 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bernhard Beschow <shentey@gmail.com> | ||
1 | 2 | ||
3 | Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and | ||
4 | fixes the MSB of selector field to be zero, as specified in the datasheet. | ||
5 | |||
6 | Fixes: 2a424990170b "LAN9118 emulation" | ||
7 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> | ||
8 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Message-id: 20241102125724.532843-4-shentey@gmail.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | hw/net/lan9118_phy.c | 2 +- | ||
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
15 | |||
16 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/net/lan9118_phy.c | ||
19 | +++ b/hw/net/lan9118_phy.c | ||
20 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) | ||
21 | val = s->advertise; | ||
22 | break; | ||
23 | case 5: /* Auto-neg Link Partner Ability */ | ||
24 | - val = 0x0f71; | ||
25 | + val = 0x0fe1; | ||
26 | break; | ||
27 | case 6: /* Auto-neg Expansion */ | ||
28 | val = 1; | ||
29 | -- | ||
30 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bernhard Beschow <shentey@gmail.com> | ||
1 | 2 | ||
3 | Prefer named constants over magic values for better readability. | ||
4 | |||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> | ||
7 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
8 | Message-id: 20241102125724.532843-5-shentey@gmail.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | include/hw/net/mii.h | 6 +++++ | ||
12 | hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++---------------- | ||
13 | 2 files changed, 46 insertions(+), 23 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/net/mii.h | ||
18 | +++ b/include/hw/net/mii.h | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | #define MII_BMSR_JABBER (1 << 1) /* Jabber detected */ | ||
21 | #define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */ | ||
22 | |||
23 | +#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */ | ||
24 | #define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */ | ||
25 | #define MII_ANAR_PAUSE (1 << 10) /* Try for pause */ | ||
26 | #define MII_ANAR_TXFD (1 << 8) | ||
27 | @@ -XXX,XX +XXX,XX @@ | ||
28 | #define MII_ANAR_10FD (1 << 6) | ||
29 | #define MII_ANAR_10 (1 << 5) | ||
30 | #define MII_ANAR_CSMACD (1 << 0) | ||
31 | +#define MII_ANAR_SELECT (0x001f) /* Selector bits */ | ||
32 | |||
33 | #define MII_ANLPAR_ACK (1 << 14) | ||
34 | #define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */ | ||
35 | @@ -XXX,XX +XXX,XX @@ | ||
36 | #define RTL8201CP_PHYID1 0x0000 | ||
37 | #define RTL8201CP_PHYID2 0x8201 | ||
38 | |||
39 | +/* SMSC LAN9118 */ | ||
40 | +#define SMSCLAN9118_PHYID1 0x0007 | ||
41 | +#define SMSCLAN9118_PHYID2 0xc0d1 | ||
42 | + | ||
43 | /* RealTek 8211E */ | ||
44 | #define RTL8211E_PHYID1 0x001c | ||
45 | #define RTL8211E_PHYID2 0xc915 | ||
46 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/hw/net/lan9118_phy.c | ||
49 | +++ b/hw/net/lan9118_phy.c | ||
50 | @@ -XXX,XX +XXX,XX @@ | ||
51 | |||
52 | #include "qemu/osdep.h" | ||
53 | #include "hw/net/lan9118_phy.h" | ||
54 | +#include "hw/net/mii.h" | ||
55 | #include "hw/irq.h" | ||
56 | #include "hw/resettable.h" | ||
57 | #include "migration/vmstate.h" | ||
58 | @@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg) | ||
59 | uint16_t val; | ||
60 | |||
61 | switch (reg) { | ||
62 | - case 0: /* Basic Control */ | ||
63 | + case MII_BMCR: | ||
64 | val = s->control; | ||
65 | break; | ||
66 | - case 1: /* Basic Status */ | ||
67 | + case MII_BMSR: | ||
68 | val = s->status; | ||
69 | break; | ||
70 | - case 2: /* ID1 */ | ||
71 | - val = 0x0007; | ||
72 | + case MII_PHYID1: | ||
73 | + val = SMSCLAN9118_PHYID1; | ||
74 | break; | ||
75 | - case 3: /* ID2 */ | ||
76 | - val = 0xc0d1; | ||
77 | + case MII_PHYID2: | ||
78 | + val = SMSCLAN9118_PHYID2; | ||
79 | break; | ||
80 | - case 4: /* Auto-neg advertisement */ | ||
81 | + case MII_ANAR: | ||
82 | val = s->advertise; | ||
83 | break; | ||
84 | - case 5: /* Auto-neg Link Partner Ability */ | ||
85 | - val = 0x0fe1; | ||
86 | + case MII_ANLPAR: | ||
87 | + val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 | | ||
88 | + MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD | | ||
89 | + MII_ANLPAR_10 | MII_ANLPAR_CSMACD; | ||
90 | break; | ||
91 | - case 6: /* Auto-neg Expansion */ | ||
92 | - val = 1; | ||
93 | + case MII_ANER: | ||
94 | + val = MII_ANER_NWAY; | ||
95 | break; | ||
96 | case 29: /* Interrupt source. */ | ||
97 | val = s->ints; | ||
98 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
99 | trace_lan9118_phy_write(val, reg); | ||
100 | |||
101 | switch (reg) { | ||
102 | - case 0: /* Basic Control */ | ||
103 | - if (val & 0x8000) { | ||
104 | + case MII_BMCR: | ||
105 | + if (val & MII_BMCR_RESET) { | ||
106 | lan9118_phy_reset(s); | ||
107 | } else { | ||
108 | - s->control = val & 0x7980; | ||
109 | + s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | | ||
110 | + MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD | | ||
111 | + MII_BMCR_CTST); | ||
112 | /* Complete autonegotiation immediately. */ | ||
113 | - if (val & 0x1000) { | ||
114 | - s->status |= 0x0020; | ||
115 | + if (val & MII_BMCR_AUTOEN) { | ||
116 | + s->status |= MII_BMSR_AN_COMP; | ||
117 | } | ||
118 | } | ||
119 | break; | ||
120 | - case 4: /* Auto-neg advertisement */ | ||
121 | - s->advertise = (val & 0x2d7f) | 0x80; | ||
122 | + case MII_ANAR: | ||
123 | + s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM | | ||
124 | + MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 | | ||
125 | + MII_ANAR_SELECT)) | ||
126 | + | MII_ANAR_TX; | ||
127 | break; | ||
128 | case 30: /* Interrupt mask */ | ||
129 | s->int_mask = val & 0xff; | ||
130 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down) | ||
131 | /* Autonegotiation status mirrors link status. */ | ||
132 | if (link_down) { | ||
133 | trace_lan9118_phy_update_link("down"); | ||
134 | - s->status &= ~0x0024; | ||
135 | + s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST); | ||
136 | s->ints |= PHY_INT_DOWN; | ||
137 | } else { | ||
138 | trace_lan9118_phy_update_link("up"); | ||
139 | - s->status |= 0x0024; | ||
140 | + s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST; | ||
141 | s->ints |= PHY_INT_ENERGYON; | ||
142 | s->ints |= PHY_INT_AUTONEG_COMPLETE; | ||
143 | } | ||
144 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s) | ||
145 | { | ||
146 | trace_lan9118_phy_reset(); | ||
147 | |||
148 | - s->control = 0x3000; | ||
149 | - s->status = 0x7809; | ||
150 | - s->advertise = 0x01e1; | ||
151 | + s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100; | ||
152 | + s->status = MII_BMSR_100TX_FD | ||
153 | + | MII_BMSR_100TX_HD | ||
154 | + | MII_BMSR_10T_FD | ||
155 | + | MII_BMSR_10T_HD | ||
156 | + | MII_BMSR_AUTONEG | ||
157 | + | MII_BMSR_EXTCAP; | ||
158 | + s->advertise = MII_ANAR_TXFD | ||
159 | + | MII_ANAR_TX | ||
160 | + | MII_ANAR_10FD | ||
161 | + | MII_ANAR_10 | ||
162 | + | MII_ANAR_CSMACD; | ||
163 | s->int_mask = 0; | ||
164 | s->ints = 0; | ||
165 | lan9118_phy_update_link(s, s->link_down); | ||
166 | -- | ||
167 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Bernhard Beschow <shentey@gmail.com> | ||
1 | 2 | ||
3 | The real device advertises this mode and the device model already advertises | ||
4 | 100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to | ||
5 | make the model more realistic. | ||
6 | |||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Bernhard Beschow <shentey@gmail.com> | ||
9 | Tested-by: Guenter Roeck <linux@roeck-us.net> | ||
10 | Message-id: 20241102125724.532843-6-shentey@gmail.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | hw/net/lan9118_phy.c | 4 ++-- | ||
14 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
15 | |||
16 | diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/net/lan9118_phy.c | ||
19 | +++ b/hw/net/lan9118_phy.c | ||
20 | @@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val) | ||
21 | break; | ||
22 | case MII_ANAR: | ||
23 | s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM | | ||
24 | - MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 | | ||
25 | - MII_ANAR_SELECT)) | ||
26 | + MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD | | ||
27 | + MII_ANAR_10 | MII_ANAR_SELECT)) | ||
28 | | MII_ANAR_TX; | ||
29 | break; | ||
30 | case 30: /* Interrupt mask */ | ||
31 | -- | ||
32 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | For IEEE fused multiply-add, the (0 * inf) + NaN case should raise | ||
2 | Invalid for the multiplication of 0 by infinity. Currently we handle | ||
3 | this in the per-architecture ifdef ladder in pickNaNMulAdd(). | ||
4 | However, since this isn't really architecture specific we can hoist | ||
5 | it up to the generic code. | ||
1 | 6 | ||
7 | For the cases where the infzero test in pickNaNMulAdd was | ||
8 | returning 2, we can delete the check entirely and allow the | ||
9 | code to fall into the normal pick-a-NaN handling, because this | ||
10 | will return 2 anyway (input 'c' being the only NaN in this case). | ||
11 | For the cases where infzero was returning 3 to indicate "return | ||
12 | the default NaN", we must retain that "return 3". | ||
13 | |||
14 | For Arm, this looks like it might be a behaviour change because we | ||
15 | used to set float_flag_invalid | float_flag_invalid_imz only if C is | ||
16 | a quiet NaN. However, it is not, because Arm target code never looks | ||
17 | at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we | ||
18 | already raised float_flag_invalid via the "abc_mask & | ||
19 | float_cmask_snan" check in pick_nan_muladd. | ||
20 | |||
21 | For any target architecture using the "default implementation" at the | ||
22 | bottom of the ifdef, this is a behaviour change but will be fixing a | ||
23 | bug (where we failed to raise the Invalid exception for (0 * inf + | ||
24 | QNaN). The architectures using the default case are: | ||
25 | * hppa | ||
26 | * i386 | ||
27 | * sh4 | ||
28 | * tricore | ||
29 | |||
30 | The x86, Tricore and SH4 CPU architecture manuals are clear that this | ||
31 | should have raised Invalid; HPPA is a bit vaguer but still seems | ||
32 | clear enough. | ||
33 | |||
34 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
35 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
36 | Message-id: 20241202131347.498124-2-peter.maydell@linaro.org | ||
37 | --- | ||
38 | fpu/softfloat-parts.c.inc | 13 +++++++------ | ||
39 | fpu/softfloat-specialize.c.inc | 29 +---------------------------- | ||
40 | 2 files changed, 8 insertions(+), 34 deletions(-) | ||
41 | |||
42 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/fpu/softfloat-parts.c.inc | ||
45 | +++ b/fpu/softfloat-parts.c.inc | ||
46 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
47 | int ab_mask, int abc_mask) | ||
48 | { | ||
49 | int which; | ||
50 | + bool infzero = (ab_mask == float_cmask_infzero); | ||
51 | |||
52 | if (unlikely(abc_mask & float_cmask_snan)) { | ||
53 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
54 | } | ||
55 | |||
56 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, | ||
57 | - ab_mask == float_cmask_infzero, s); | ||
58 | + if (infzero) { | ||
59 | + /* This is (0 * inf) + NaN or (inf * 0) + NaN */ | ||
60 | + float_raise(float_flag_invalid | float_flag_invalid_imz, s); | ||
61 | + } | ||
62 | + | ||
63 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
64 | |||
65 | if (s->default_nan_mode || which == 3) { | ||
66 | - /* | ||
67 | - * Note that this check is after pickNaNMulAdd so that function | ||
68 | - * has an opportunity to set the Invalid flag for infzero. | ||
69 | - */ | ||
70 | parts_default_nan(a, s); | ||
71 | return a; | ||
72 | } | ||
73 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
74 | index XXXXXXX..XXXXXXX 100644 | ||
75 | --- a/fpu/softfloat-specialize.c.inc | ||
76 | +++ b/fpu/softfloat-specialize.c.inc | ||
77 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
78 | * the default NaN | ||
79 | */ | ||
80 | if (infzero && is_qnan(c_cls)) { | ||
81 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
82 | return 3; | ||
83 | } | ||
84 | |||
85 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
86 | * case sets InvalidOp and returns the default NaN | ||
87 | */ | ||
88 | if (infzero) { | ||
89 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
90 | return 3; | ||
91 | } | ||
92 | /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
93 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
94 | * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
95 | * case sets InvalidOp and returns the input value 'c' | ||
96 | */ | ||
97 | - if (infzero) { | ||
98 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
99 | - return 2; | ||
100 | - } | ||
101 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
102 | if (is_snan(c_cls)) { | ||
103 | return 2; | ||
104 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
105 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
106 | * case sets InvalidOp and returns the input value 'c' | ||
107 | */ | ||
108 | - if (infzero) { | ||
109 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
110 | - return 2; | ||
111 | - } | ||
112 | + | ||
113 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
114 | if (is_snan(c_cls)) { | ||
115 | return 2; | ||
116 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
117 | * to return an input NaN if we have one (ie c) rather than generating | ||
118 | * a default NaN | ||
119 | */ | ||
120 | - if (infzero) { | ||
121 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
122 | - return 2; | ||
123 | - } | ||
124 | |||
125 | /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
126 | * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
127 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
128 | return 1; | ||
129 | } | ||
130 | #elif defined(TARGET_RISCV) | ||
131 | - /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ | ||
132 | - if (infzero) { | ||
133 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
134 | - } | ||
135 | return 3; /* default NaN */ | ||
136 | #elif defined(TARGET_S390X) | ||
137 | if (infzero) { | ||
138 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
139 | return 3; | ||
140 | } | ||
141 | |||
142 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
143 | return 2; | ||
144 | } | ||
145 | #elif defined(TARGET_SPARC) | ||
146 | - /* For (inf,0,nan) return c. */ | ||
147 | - if (infzero) { | ||
148 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
149 | - return 2; | ||
150 | - } | ||
151 | /* Prefer SNaN over QNaN, order C, B, A. */ | ||
152 | if (is_snan(c_cls)) { | ||
153 | return 2; | ||
154 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
155 | * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns | ||
156 | * an input NaN if we have one (ie c). | ||
157 | */ | ||
158 | - if (infzero) { | ||
159 | - float_raise(float_flag_invalid | float_flag_invalid_imz, status); | ||
160 | - return 2; | ||
161 | - } | ||
162 | if (status->use_first_nan) { | ||
163 | if (is_nan(a_cls)) { | ||
164 | return 0; | ||
165 | -- | ||
166 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | If the target sets default_nan_mode then we're always going to return | ||
2 | the default NaN, and pickNaNMulAdd() no longer has any side effects. | ||
3 | For consistency with pickNaN(), check for default_nan_mode before | ||
4 | calling pickNaNMulAdd(). | ||
1 | 5 | ||
6 | When we convert pickNaNMulAdd() to allow runtime selection of the NaN | ||
7 | propagation rule, this means we won't have to make the targets which | ||
8 | use default_nan_mode also set a propagation rule. | ||
9 | |||
10 | Since RiscV always uses default_nan_mode, this allows us to remove | ||
11 | its ifdef case from pickNaNMulAdd(). | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20241202131347.498124-3-peter.maydell@linaro.org | ||
16 | --- | ||
17 | fpu/softfloat-parts.c.inc | 8 ++++++-- | ||
18 | fpu/softfloat-specialize.c.inc | 9 +++++++-- | ||
19 | 2 files changed, 13 insertions(+), 4 deletions(-) | ||
20 | |||
21 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/fpu/softfloat-parts.c.inc | ||
24 | +++ b/fpu/softfloat-parts.c.inc | ||
25 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
26 | float_raise(float_flag_invalid | float_flag_invalid_imz, s); | ||
27 | } | ||
28 | |||
29 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
30 | + if (s->default_nan_mode) { | ||
31 | + which = 3; | ||
32 | + } else { | ||
33 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
34 | + } | ||
35 | |||
36 | - if (s->default_nan_mode || which == 3) { | ||
37 | + if (which == 3) { | ||
38 | parts_default_nan(a, s); | ||
39 | return a; | ||
40 | } | ||
41 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/fpu/softfloat-specialize.c.inc | ||
44 | +++ b/fpu/softfloat-specialize.c.inc | ||
45 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
46 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
47 | bool infzero, float_status *status) | ||
48 | { | ||
49 | + /* | ||
50 | + * We guarantee not to require the target to tell us how to | ||
51 | + * pick a NaN if we're always returning the default NaN. | ||
52 | + * But if we're not in default-NaN mode then the target must | ||
53 | + * specify. | ||
54 | + */ | ||
55 | + assert(!status->default_nan_mode); | ||
56 | #if defined(TARGET_ARM) | ||
57 | /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns | ||
58 | * the default NaN | ||
59 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
60 | } else { | ||
61 | return 1; | ||
62 | } | ||
63 | -#elif defined(TARGET_RISCV) | ||
64 | - return 3; /* default NaN */ | ||
65 | #elif defined(TARGET_S390X) | ||
66 | if (infzero) { | ||
67 | return 3; | ||
68 | -- | ||
69 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | IEEE 758 does not define a fixed rule for what NaN to return in | |
2 | the case of a fused multiply-add of inf * 0 + NaN. Different | ||
3 | architectures thus do different things: | ||
4 | * some return the default NaN | ||
5 | * some return the input NaN | ||
6 | * Arm returns the default NaN if the input NaN is quiet, | ||
7 | and the input NaN if it is signalling | ||
8 | |||
9 | We want to make this logic be runtime selected rather than | ||
10 | hardcoded into the binary, because: | ||
11 | * this will let us have multiple targets in one QEMU binary | ||
12 | * the Arm FEAT_AFP architectural feature includes letting | ||
13 | the guest select a NaN propagation rule at runtime | ||
14 | |||
15 | In this commit we add an enum for the propagation rule, the field in | ||
16 | float_status, and the corresponding getters and setters. We change | ||
17 | pickNaNMulAdd to honour this, but because all targets still leave | ||
18 | this field at its default 0 value, the fallback logic will pick the | ||
19 | rule type with the old ifdef ladder. | ||
20 | |||
21 | Note that four architectures both use the muladd softfloat functions | ||
22 | and did not have a branch of the ifdef ladder to specify their | ||
23 | behaviour (and so were ending up with the "default" case, probably | ||
24 | wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set | ||
25 | default_nan_mode, and so will never get into pickNaNMulAdd(). For | ||
26 | HPPA and i386 we retain the same behaviour as the old default-case, | ||
27 | which is to not ever return the default NaN. This might not be | ||
28 | correct but it is not a behaviour change. | ||
29 | |||
30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
31 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
32 | Message-id: 20241202131347.498124-4-peter.maydell@linaro.org | ||
33 | --- | ||
34 | include/fpu/softfloat-helpers.h | 11 ++++ | ||
35 | include/fpu/softfloat-types.h | 23 +++++++++ | ||
36 | fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++----------- | ||
37 | 3 files changed, 95 insertions(+), 30 deletions(-) | ||
38 | |||
39 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/include/fpu/softfloat-helpers.h | ||
42 | +++ b/include/fpu/softfloat-helpers.h | ||
43 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, | ||
44 | status->float_2nan_prop_rule = rule; | ||
45 | } | ||
46 | |||
47 | +static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, | ||
48 | + float_status *status) | ||
49 | +{ | ||
50 | + status->float_infzeronan_rule = rule; | ||
51 | +} | ||
52 | + | ||
53 | static inline void set_flush_to_zero(bool val, float_status *status) | ||
54 | { | ||
55 | status->flush_to_zero = val; | ||
56 | @@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) | ||
57 | return status->float_2nan_prop_rule; | ||
58 | } | ||
59 | |||
60 | +static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) | ||
61 | +{ | ||
62 | + return status->float_infzeronan_rule; | ||
63 | +} | ||
64 | + | ||
65 | static inline bool get_flush_to_zero(float_status *status) | ||
66 | { | ||
67 | return status->flush_to_zero; | ||
68 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/include/fpu/softfloat-types.h | ||
71 | +++ b/include/fpu/softfloat-types.h | ||
72 | @@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) { | ||
73 | float_2nan_prop_x87, | ||
74 | } Float2NaNPropRule; | ||
75 | |||
76 | +/* | ||
77 | + * Rule for result of fused multiply-add 0 * Inf + NaN. | ||
78 | + * This must be a NaN, but implementations differ on whether this | ||
79 | + * is the input NaN or the default NaN. | ||
80 | + * | ||
81 | + * You don't need to set this if default_nan_mode is enabled. | ||
82 | + * When not in default-NaN mode, it is an error for the target | ||
83 | + * not to set the rule in float_status if it uses muladd, and we | ||
84 | + * will assert if we need to handle an input NaN and no rule was | ||
85 | + * selected. | ||
86 | + */ | ||
87 | +typedef enum __attribute__((__packed__)) { | ||
88 | + /* No propagation rule specified */ | ||
89 | + float_infzeronan_none = 0, | ||
90 | + /* Result is never the default NaN (so always the input NaN) */ | ||
91 | + float_infzeronan_dnan_never, | ||
92 | + /* Result is always the default NaN */ | ||
93 | + float_infzeronan_dnan_always, | ||
94 | + /* Result is the default NaN if the input NaN is quiet */ | ||
95 | + float_infzeronan_dnan_if_qnan, | ||
96 | +} FloatInfZeroNaNRule; | ||
97 | + | ||
98 | /* | ||
99 | * Floating Point Status. Individual architectures may maintain | ||
100 | * several versions of float_status for different functions. The | ||
101 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
102 | FloatRoundMode float_rounding_mode; | ||
103 | FloatX80RoundPrec floatx80_rounding_precision; | ||
104 | Float2NaNPropRule float_2nan_prop_rule; | ||
105 | + FloatInfZeroNaNRule float_infzeronan_rule; | ||
106 | bool tininess_before_rounding; | ||
107 | /* should denormalised results go to zero and set the inexact flag? */ | ||
108 | bool flush_to_zero; | ||
109 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
110 | index XXXXXXX..XXXXXXX 100644 | ||
111 | --- a/fpu/softfloat-specialize.c.inc | ||
112 | +++ b/fpu/softfloat-specialize.c.inc | ||
113 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
114 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
115 | bool infzero, float_status *status) | ||
116 | { | ||
117 | + FloatInfZeroNaNRule rule = status->float_infzeronan_rule; | ||
118 | + | ||
119 | /* | ||
120 | * We guarantee not to require the target to tell us how to | ||
121 | * pick a NaN if we're always returning the default NaN. | ||
122 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
123 | * specify. | ||
124 | */ | ||
125 | assert(!status->default_nan_mode); | ||
126 | + | ||
127 | + if (rule == float_infzeronan_none) { | ||
128 | + /* | ||
129 | + * Temporarily fall back to ifdef ladder | ||
130 | + */ | ||
131 | #if defined(TARGET_ARM) | ||
132 | - /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns | ||
133 | - * the default NaN | ||
134 | - */ | ||
135 | - if (infzero && is_qnan(c_cls)) { | ||
136 | - return 3; | ||
137 | + /* | ||
138 | + * For ARM, the (inf,zero,qnan) case returns the default NaN, | ||
139 | + * but (inf,zero,snan) returns the input NaN. | ||
140 | + */ | ||
141 | + rule = float_infzeronan_dnan_if_qnan; | ||
142 | +#elif defined(TARGET_MIPS) | ||
143 | + if (snan_bit_is_one(status)) { | ||
144 | + /* | ||
145 | + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
146 | + * case sets InvalidOp and returns the default NaN | ||
147 | + */ | ||
148 | + rule = float_infzeronan_dnan_always; | ||
149 | + } else { | ||
150 | + /* | ||
151 | + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
152 | + * case sets InvalidOp and returns the input value 'c' | ||
153 | + */ | ||
154 | + rule = float_infzeronan_dnan_never; | ||
155 | + } | ||
156 | +#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ | ||
157 | + defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
158 | + defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
159 | + /* | ||
160 | + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
161 | + * case sets InvalidOp and returns the input value 'c' | ||
162 | + */ | ||
163 | + /* | ||
164 | + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
165 | + * to return an input NaN if we have one (ie c) rather than generating | ||
166 | + * a default NaN | ||
167 | + */ | ||
168 | + rule = float_infzeronan_dnan_never; | ||
169 | +#elif defined(TARGET_S390X) | ||
170 | + rule = float_infzeronan_dnan_always; | ||
171 | +#endif | ||
172 | } | ||
173 | |||
174 | + if (infzero) { | ||
175 | + /* | ||
176 | + * Inf * 0 + NaN -- some implementations return the default NaN here, | ||
177 | + * and some return the input NaN. | ||
178 | + */ | ||
179 | + switch (rule) { | ||
180 | + case float_infzeronan_dnan_never: | ||
181 | + return 2; | ||
182 | + case float_infzeronan_dnan_always: | ||
183 | + return 3; | ||
184 | + case float_infzeronan_dnan_if_qnan: | ||
185 | + return is_qnan(c_cls) ? 3 : 2; | ||
186 | + default: | ||
187 | + g_assert_not_reached(); | ||
188 | + } | ||
189 | + } | ||
190 | + | ||
191 | +#if defined(TARGET_ARM) | ||
192 | + | ||
193 | /* This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
194 | * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. | ||
195 | */ | ||
196 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
197 | } | ||
198 | #elif defined(TARGET_MIPS) | ||
199 | if (snan_bit_is_one(status)) { | ||
200 | - /* | ||
201 | - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
202 | - * case sets InvalidOp and returns the default NaN | ||
203 | - */ | ||
204 | - if (infzero) { | ||
205 | - return 3; | ||
206 | - } | ||
207 | /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
208 | if (is_snan(a_cls)) { | ||
209 | return 0; | ||
210 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
211 | return 2; | ||
212 | } | ||
213 | } else { | ||
214 | - /* | ||
215 | - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
216 | - * case sets InvalidOp and returns the input value 'c' | ||
217 | - */ | ||
218 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
219 | if (is_snan(c_cls)) { | ||
220 | return 2; | ||
221 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
222 | } | ||
223 | } | ||
224 | #elif defined(TARGET_LOONGARCH64) | ||
225 | - /* | ||
226 | - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
227 | - * case sets InvalidOp and returns the input value 'c' | ||
228 | - */ | ||
229 | - | ||
230 | /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
231 | if (is_snan(c_cls)) { | ||
232 | return 2; | ||
233 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
234 | return 1; | ||
235 | } | ||
236 | #elif defined(TARGET_PPC) | ||
237 | - /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
238 | - * to return an input NaN if we have one (ie c) rather than generating | ||
239 | - * a default NaN | ||
240 | - */ | ||
241 | - | ||
242 | /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
243 | * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
244 | */ | ||
245 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
246 | return 1; | ||
247 | } | ||
248 | #elif defined(TARGET_S390X) | ||
249 | - if (infzero) { | ||
250 | - return 3; | ||
251 | - } | ||
252 | - | ||
253 | if (is_snan(a_cls)) { | ||
254 | return 0; | ||
255 | } else if (is_snan(b_cls)) { | ||
256 | -- | ||
257 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Explicitly set a rule in the softfloat tests for the inf-zero-nan | ||
2 | muladd special case. In meson.build we put -DTARGET_ARM in fpcflags, | ||
3 | and so we should select here the Arm rule of | ||
4 | float_infzeronan_dnan_if_qnan. | ||
1 | 5 | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20241202131347.498124-5-peter.maydell@linaro.org | ||
9 | --- | ||
10 | tests/fp/fp-bench.c | 5 +++++ | ||
11 | tests/fp/fp-test.c | 5 +++++ | ||
12 | 2 files changed, 10 insertions(+) | ||
13 | |||
14 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/tests/fp/fp-bench.c | ||
17 | +++ b/tests/fp/fp-bench.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) | ||
19 | { | ||
20 | bench_func_t f; | ||
21 | |||
22 | + /* | ||
23 | + * These implementation-defined choices for various things IEEE | ||
24 | + * doesn't specify match those used by the Arm architecture. | ||
25 | + */ | ||
26 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); | ||
27 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); | ||
28 | |||
29 | f = bench_funcs[operation][precision]; | ||
30 | g_assert(f); | ||
31 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/tests/fp/fp-test.c | ||
34 | +++ b/tests/fp/fp-test.c | ||
35 | @@ -XXX,XX +XXX,XX @@ void run_test(void) | ||
36 | { | ||
37 | unsigned int i; | ||
38 | |||
39 | + /* | ||
40 | + * These implementation-defined choices for various things IEEE | ||
41 | + * doesn't specify match those used by the Arm architecture. | ||
42 | + */ | ||
43 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
44 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); | ||
45 | |||
46 | genCases_setLevel(test_level); | ||
47 | verCases_maxErrorCount = n_max_errors; | ||
48 | -- | ||
49 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the Arm target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-6-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/cpu.c | 3 +++ | ||
9 | fpu/softfloat-specialize.c.inc | 8 +------- | ||
10 | 2 files changed, 4 insertions(+), 7 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/cpu.c | ||
15 | +++ b/target/arm/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, | ||
17 | * * tininess-before-rounding | ||
18 | * * 2-input NaN propagation prefers SNaN over QNaN, and then | ||
19 | * operand A over operand B (see FPProcessNaNs() pseudocode) | ||
20 | + * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, | ||
21 | + * and the input NaN if it is signalling | ||
22 | */ | ||
23 | static void arm_set_default_fp_behaviours(float_status *s) | ||
24 | { | ||
25 | set_float_detect_tininess(float_tininess_before_rounding, s); | ||
26 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); | ||
27 | + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); | ||
28 | } | ||
29 | |||
30 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) | ||
31 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/fpu/softfloat-specialize.c.inc | ||
34 | +++ b/fpu/softfloat-specialize.c.inc | ||
35 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
36 | /* | ||
37 | * Temporarily fall back to ifdef ladder | ||
38 | */ | ||
39 | -#if defined(TARGET_ARM) | ||
40 | - /* | ||
41 | - * For ARM, the (inf,zero,qnan) case returns the default NaN, | ||
42 | - * but (inf,zero,snan) returns the input NaN. | ||
43 | - */ | ||
44 | - rule = float_infzeronan_dnan_if_qnan; | ||
45 | -#elif defined(TARGET_MIPS) | ||
46 | +#if defined(TARGET_MIPS) | ||
47 | if (snan_bit_is_one(status)) { | ||
48 | /* | ||
49 | * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
50 | -- | ||
51 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for s390, so we | ||
2 | can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-7-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/s390x/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
10 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/s390x/cpu.c | ||
15 | +++ b/target/s390x/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | set_float_detect_tininess(float_tininess_before_rounding, | ||
18 | &env->fpu_status); | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); | ||
20 | + set_float_infzeronan_rule(float_infzeronan_dnan_always, | ||
21 | + &env->fpu_status); | ||
22 | /* fall through */ | ||
23 | case RESET_TYPE_S390_CPU_NORMAL: | ||
24 | env->psw.mask &= ~PSW_MASK_RI; | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
30 | * a default NaN | ||
31 | */ | ||
32 | rule = float_infzeronan_dnan_never; | ||
33 | -#elif defined(TARGET_S390X) | ||
34 | - rule = float_infzeronan_dnan_always; | ||
35 | #endif | ||
36 | } | ||
37 | |||
38 | -- | ||
39 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the PPC target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-8-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/ppc/cpu_init.c | 7 +++++++ | ||
9 | fpu/softfloat-specialize.c.inc | 7 +------ | ||
10 | 2 files changed, 8 insertions(+), 6 deletions(-) | ||
11 | |||
12 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/ppc/cpu_init.c | ||
15 | +++ b/target/ppc/cpu_init.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | */ | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); | ||
20 | + /* | ||
21 | + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
22 | + * to return an input NaN if we have one (ie c) rather than generating | ||
23 | + * a default NaN | ||
24 | + */ | ||
25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
26 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); | ||
27 | |||
28 | for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { | ||
29 | ppc_spr_t *spr = &env->spr_cb[i]; | ||
30 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/fpu/softfloat-specialize.c.inc | ||
33 | +++ b/fpu/softfloat-specialize.c.inc | ||
34 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
35 | */ | ||
36 | rule = float_infzeronan_dnan_never; | ||
37 | } | ||
38 | -#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ | ||
39 | +#elif defined(TARGET_SPARC) || \ | ||
40 | defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
41 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
42 | /* | ||
43 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
44 | * case sets InvalidOp and returns the input value 'c' | ||
45 | */ | ||
46 | - /* | ||
47 | - * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
48 | - * to return an input NaN if we have one (ie c) rather than generating | ||
49 | - * a default NaN | ||
50 | - */ | ||
51 | rule = float_infzeronan_dnan_never; | ||
52 | #endif | ||
53 | } | ||
54 | -- | ||
55 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the MIPS target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-9-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/mips/fpu_helper.h | 9 +++++++++ | ||
9 | target/mips/msa.c | 4 ++++ | ||
10 | fpu/softfloat-specialize.c.inc | 16 +--------------- | ||
11 | 3 files changed, 14 insertions(+), 15 deletions(-) | ||
12 | |||
13 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/mips/fpu_helper.h | ||
16 | +++ b/target/mips/fpu_helper.h | ||
17 | @@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env) | ||
18 | static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
19 | { | ||
20 | bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); | ||
21 | + FloatInfZeroNaNRule izn_rule; | ||
22 | |||
23 | /* | ||
24 | * With nan2008, SNaNs are silenced in the usual way. | ||
25 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
26 | */ | ||
27 | set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status); | ||
28 | set_default_nan_mode(!nan2008, &env->active_fpu.fp_status); | ||
29 | + /* | ||
30 | + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
31 | + * case sets InvalidOp and returns the default NaN. | ||
32 | + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
33 | + * case sets InvalidOp and returns the input value 'c'. | ||
34 | + */ | ||
35 | + izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; | ||
36 | + set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); | ||
37 | } | ||
38 | |||
39 | static inline void restore_fp_status(CPUMIPSState *env) | ||
40 | diff --git a/target/mips/msa.c b/target/mips/msa.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/mips/msa.c | ||
43 | +++ b/target/mips/msa.c | ||
44 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) | ||
45 | |||
46 | /* set proper signanling bit meaning ("1" means "quiet") */ | ||
47 | set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); | ||
48 | + | ||
49 | + /* Inf * 0 + NaN returns the input NaN */ | ||
50 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, | ||
51 | + &env->active_tc.msa_fp_status); | ||
52 | } | ||
53 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/fpu/softfloat-specialize.c.inc | ||
56 | +++ b/fpu/softfloat-specialize.c.inc | ||
57 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
58 | /* | ||
59 | * Temporarily fall back to ifdef ladder | ||
60 | */ | ||
61 | -#if defined(TARGET_MIPS) | ||
62 | - if (snan_bit_is_one(status)) { | ||
63 | - /* | ||
64 | - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) | ||
65 | - * case sets InvalidOp and returns the default NaN | ||
66 | - */ | ||
67 | - rule = float_infzeronan_dnan_always; | ||
68 | - } else { | ||
69 | - /* | ||
70 | - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
71 | - * case sets InvalidOp and returns the input value 'c' | ||
72 | - */ | ||
73 | - rule = float_infzeronan_dnan_never; | ||
74 | - } | ||
75 | -#elif defined(TARGET_SPARC) || \ | ||
76 | +#if defined(TARGET_SPARC) || \ | ||
77 | defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
78 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
79 | /* | ||
80 | -- | ||
81 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the SPARC target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-10-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/sparc/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 3 +-- | ||
10 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/sparc/cpu.c | ||
15 | +++ b/target/sparc/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) | ||
17 | * the CPU state struct so it won't get zeroed on reset. | ||
18 | */ | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); | ||
20 | + /* For inf * 0 + NaN, return the input NaN */ | ||
21 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
22 | |||
23 | cpu_exec_realizefn(cs, &local_err); | ||
24 | if (local_err != NULL) { | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
30 | /* | ||
31 | * Temporarily fall back to ifdef ladder | ||
32 | */ | ||
33 | -#if defined(TARGET_SPARC) || \ | ||
34 | - defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
35 | +#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
36 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
37 | /* | ||
38 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
39 | -- | ||
40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the xtensa target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-11-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/xtensa/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 2 +- | ||
10 | 2 files changed, 3 insertions(+), 1 deletion(-) | ||
11 | |||
12 | diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/xtensa/cpu.c | ||
15 | +++ b/target/xtensa/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | reset_mmu(env); | ||
18 | cs->halted = env->runstall; | ||
19 | #endif | ||
20 | + /* For inf * 0 + NaN, return the input NaN */ | ||
21 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
22 | set_no_signaling_nans(!dfpu, &env->fp_status); | ||
23 | xtensa_use_first_nan(env, !dfpu); | ||
24 | } | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
30 | /* | ||
31 | * Temporarily fall back to ifdef ladder | ||
32 | */ | ||
33 | -#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ | ||
34 | +#if defined(TARGET_HPPA) || \ | ||
35 | defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
36 | /* | ||
37 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
38 | -- | ||
39 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the x86 target. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-12-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/i386/tcg/fpu_helper.c | 7 +++++++ | ||
8 | fpu/softfloat-specialize.c.inc | 2 +- | ||
9 | 2 files changed, 8 insertions(+), 1 deletion(-) | ||
10 | |||
11 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/i386/tcg/fpu_helper.c | ||
14 | +++ b/target/i386/tcg/fpu_helper.c | ||
15 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) | ||
16 | */ | ||
17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status); | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status); | ||
19 | + /* | ||
20 | + * Only SSE has multiply-add instructions. In the SDM Section 14.5.2 | ||
21 | + * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is | ||
22 | + * specified -- for 0 * inf + NaN the input NaN is selected, and if | ||
23 | + * there are multiple input NaNs they are selected in the order a, b, c. | ||
24 | + */ | ||
25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); | ||
26 | } | ||
27 | |||
28 | static inline uint8_t save_exception_flags(CPUX86State *env) | ||
29 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/fpu/softfloat-specialize.c.inc | ||
32 | +++ b/fpu/softfloat-specialize.c.inc | ||
33 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
34 | * Temporarily fall back to ifdef ladder | ||
35 | */ | ||
36 | #if defined(TARGET_HPPA) || \ | ||
37 | - defined(TARGET_I386) || defined(TARGET_LOONGARCH) | ||
38 | + defined(TARGET_LOONGARCH) | ||
39 | /* | ||
40 | * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
41 | * case sets InvalidOp and returns the input value 'c' | ||
42 | -- | ||
43 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the loongarch target. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-13-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/loongarch/tcg/fpu_helper.c | 5 +++++ | ||
8 | fpu/softfloat-specialize.c.inc | 7 +------ | ||
9 | 2 files changed, 6 insertions(+), 6 deletions(-) | ||
10 | |||
11 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/loongarch/tcg/fpu_helper.c | ||
14 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
15 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) | ||
16 | &env->fp_status); | ||
17 | set_flush_to_zero(0, &env->fp_status); | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); | ||
19 | + /* | ||
20 | + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
21 | + * case sets InvalidOp and returns the input value 'c' | ||
22 | + */ | ||
23 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
24 | } | ||
25 | |||
26 | int ieee_ex_to_loongarch(int xcpt) | ||
27 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/fpu/softfloat-specialize.c.inc | ||
30 | +++ b/fpu/softfloat-specialize.c.inc | ||
31 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
32 | /* | ||
33 | * Temporarily fall back to ifdef ladder | ||
34 | */ | ||
35 | -#if defined(TARGET_HPPA) || \ | ||
36 | - defined(TARGET_LOONGARCH) | ||
37 | - /* | ||
38 | - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) | ||
39 | - * case sets InvalidOp and returns the input value 'c' | ||
40 | - */ | ||
41 | +#if defined(TARGET_HPPA) | ||
42 | rule = float_infzeronan_dnan_never; | ||
43 | #endif | ||
44 | } | ||
45 | -- | ||
46 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the FloatInfZeroNaNRule explicitly for the HPPA target, | ||
2 | so we can remove the ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | As this is the last target to be converted to explicitly setting | ||
5 | the rule, we can remove the fallback code in pickNaNMulAdd() | ||
6 | entirely. | ||
7 | |||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20241202131347.498124-14-peter.maydell@linaro.org | ||
11 | --- | ||
12 | target/hppa/fpu_helper.c | 2 ++ | ||
13 | fpu/softfloat-specialize.c.inc | 13 +------------ | ||
14 | 2 files changed, 3 insertions(+), 12 deletions(-) | ||
15 | |||
16 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/hppa/fpu_helper.c | ||
19 | +++ b/target/hppa/fpu_helper.c | ||
20 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) | ||
21 | * HPPA does note implement a CPU reset method at all... | ||
22 | */ | ||
23 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); | ||
24 | + /* For inf * 0 + NaN, return the input NaN */ | ||
25 | + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
26 | } | ||
27 | |||
28 | void cpu_hppa_loaded_fr0(CPUHPPAState *env) | ||
29 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/fpu/softfloat-specialize.c.inc | ||
32 | +++ b/fpu/softfloat-specialize.c.inc | ||
33 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
34 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
35 | bool infzero, float_status *status) | ||
36 | { | ||
37 | - FloatInfZeroNaNRule rule = status->float_infzeronan_rule; | ||
38 | - | ||
39 | /* | ||
40 | * We guarantee not to require the target to tell us how to | ||
41 | * pick a NaN if we're always returning the default NaN. | ||
42 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
43 | */ | ||
44 | assert(!status->default_nan_mode); | ||
45 | |||
46 | - if (rule == float_infzeronan_none) { | ||
47 | - /* | ||
48 | - * Temporarily fall back to ifdef ladder | ||
49 | - */ | ||
50 | -#if defined(TARGET_HPPA) | ||
51 | - rule = float_infzeronan_dnan_never; | ||
52 | -#endif | ||
53 | - } | ||
54 | - | ||
55 | if (infzero) { | ||
56 | /* | ||
57 | * Inf * 0 + NaN -- some implementations return the default NaN here, | ||
58 | * and some return the input NaN. | ||
59 | */ | ||
60 | - switch (rule) { | ||
61 | + switch (status->float_infzeronan_rule) { | ||
62 | case float_infzeronan_dnan_never: | ||
63 | return 2; | ||
64 | case float_infzeronan_dnan_always: | ||
65 | -- | ||
66 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The new implementation of pickNaNMulAdd() will find it convenient | ||
2 | to know whether at least one of the three arguments to the muladd | ||
3 | was a signaling NaN. We already calculate that in the caller, | ||
4 | so pass it in as a new bool have_snan. | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20241202131347.498124-15-peter.maydell@linaro.org | ||
9 | --- | ||
10 | fpu/softfloat-parts.c.inc | 5 +++-- | ||
11 | fpu/softfloat-specialize.c.inc | 2 +- | ||
12 | 2 files changed, 4 insertions(+), 3 deletions(-) | ||
13 | |||
14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/fpu/softfloat-parts.c.inc | ||
17 | +++ b/fpu/softfloat-parts.c.inc | ||
18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
19 | { | ||
20 | int which; | ||
21 | bool infzero = (ab_mask == float_cmask_infzero); | ||
22 | + bool have_snan = (abc_mask & float_cmask_snan); | ||
23 | |||
24 | - if (unlikely(abc_mask & float_cmask_snan)) { | ||
25 | + if (unlikely(have_snan)) { | ||
26 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
27 | } | ||
28 | |||
29 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
30 | if (s->default_nan_mode) { | ||
31 | which = 3; | ||
32 | } else { | ||
33 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); | ||
34 | + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); | ||
35 | } | ||
36 | |||
37 | if (which == 3) { | ||
38 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/fpu/softfloat-specialize.c.inc | ||
41 | +++ b/fpu/softfloat-specialize.c.inc | ||
42 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
43 | | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN | ||
44 | *----------------------------------------------------------------------------*/ | ||
45 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
46 | - bool infzero, float_status *status) | ||
47 | + bool infzero, bool have_snan, float_status *status) | ||
48 | { | ||
49 | /* | ||
50 | * We guarantee not to require the target to tell us how to | ||
51 | -- | ||
52 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | IEEE 758 does not define a fixed rule for which NaN to pick as the | |
2 | result if both operands of a 3-operand fused multiply-add operation | ||
3 | are NaNs. As a result different architectures have ended up with | ||
4 | different rules for propagating NaNs. | ||
5 | |||
6 | QEMU currently hardcodes the NaN propagation logic into the binary | ||
7 | because pickNaNMulAdd() has an ifdef ladder for different targets. | ||
8 | We want to make the propagation rule instead be selectable at | ||
9 | runtime, because: | ||
10 | * this will let us have multiple targets in one QEMU binary | ||
11 | * the Arm FEAT_AFP architectural feature includes letting | ||
12 | the guest select a NaN propagation rule at runtime | ||
13 | |||
14 | In this commit we add an enum for the propagation rule, the field in | ||
15 | float_status, and the corresponding getters and setters. We change | ||
16 | pickNaNMulAdd to honour this, but because all targets still leave | ||
17 | this field at its default 0 value, the fallback logic will pick the | ||
18 | rule type with the old ifdef ladder. | ||
19 | |||
20 | It's valid not to set a propagation rule if default_nan_mode is | ||
21 | enabled, because in that case there's no need to pick a NaN; all the | ||
22 | callers of pickNaNMulAdd() catch this case and skip calling it. | ||
23 | |||
24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
25 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
26 | Message-id: 20241202131347.498124-16-peter.maydell@linaro.org | ||
27 | --- | ||
28 | include/fpu/softfloat-helpers.h | 11 +++ | ||
29 | include/fpu/softfloat-types.h | 55 +++++++++++ | ||
30 | fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------ | ||
31 | 3 files changed, 107 insertions(+), 126 deletions(-) | ||
32 | |||
33 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/include/fpu/softfloat-helpers.h | ||
36 | +++ b/include/fpu/softfloat-helpers.h | ||
37 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, | ||
38 | status->float_2nan_prop_rule = rule; | ||
39 | } | ||
40 | |||
41 | +static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule, | ||
42 | + float_status *status) | ||
43 | +{ | ||
44 | + status->float_3nan_prop_rule = rule; | ||
45 | +} | ||
46 | + | ||
47 | static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, | ||
48 | float_status *status) | ||
49 | { | ||
50 | @@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) | ||
51 | return status->float_2nan_prop_rule; | ||
52 | } | ||
53 | |||
54 | +static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status) | ||
55 | +{ | ||
56 | + return status->float_3nan_prop_rule; | ||
57 | +} | ||
58 | + | ||
59 | static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) | ||
60 | { | ||
61 | return status->float_infzeronan_rule; | ||
62 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h | ||
63 | index XXXXXXX..XXXXXXX 100644 | ||
64 | --- a/include/fpu/softfloat-types.h | ||
65 | +++ b/include/fpu/softfloat-types.h | ||
66 | @@ -XXX,XX +XXX,XX @@ this code that are retained. | ||
67 | #ifndef SOFTFLOAT_TYPES_H | ||
68 | #define SOFTFLOAT_TYPES_H | ||
69 | |||
70 | +#include "hw/registerfields.h" | ||
71 | + | ||
72 | /* | ||
73 | * Software IEC/IEEE floating-point types. | ||
74 | */ | ||
75 | @@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) { | ||
76 | float_2nan_prop_x87, | ||
77 | } Float2NaNPropRule; | ||
78 | |||
79 | +/* | ||
80 | + * 3-input NaN propagation rule, for fused multiply-add. Individual | ||
81 | + * architectures have different rules for which input NaN is | ||
82 | + * propagated to the output when there is more than one NaN on the | ||
83 | + * input. | ||
84 | + * | ||
85 | + * If default_nan_mode is enabled then it is valid not to set a NaN | ||
86 | + * propagation rule, because the softfloat code guarantees not to try | ||
87 | + * to pick a NaN to propagate in default NaN mode. When not in | ||
88 | + * default-NaN mode, it is an error for the target not to set the rule | ||
89 | + * in float_status if it uses a muladd, and we will assert if we need | ||
90 | + * to handle an input NaN and no rule was selected. | ||
91 | + * | ||
92 | + * The naming scheme for Float3NaNPropRule values is: | ||
93 | + * float_3nan_prop_s_abc: | ||
94 | + * = "Prefer SNaN over QNaN, then operand A over B over C" | ||
95 | + * float_3nan_prop_abc: | ||
96 | + * = "Prefer A over B over C regardless of SNaN vs QNAN" | ||
97 | + * | ||
98 | + * For QEMU, the multiply-add operation is A * B + C. | ||
99 | + */ | ||
100 | + | ||
101 | +/* | ||
102 | + * We set the Float3NaNPropRule enum values up so we can select the | ||
103 | + * right value in pickNaNMulAdd in a data driven way. | ||
104 | + */ | ||
105 | +FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */ | ||
106 | +FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */ | ||
107 | +FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */ | ||
108 | +FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */ | ||
109 | + | ||
110 | +#define PROPRULE(X, Y, Z) \ | ||
111 | + ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT)) | ||
112 | + | ||
113 | +typedef enum __attribute__((__packed__)) { | ||
114 | + float_3nan_prop_none = 0, /* No propagation rule specified */ | ||
115 | + float_3nan_prop_abc = PROPRULE(0, 1, 2), | ||
116 | + float_3nan_prop_acb = PROPRULE(0, 2, 1), | ||
117 | + float_3nan_prop_bac = PROPRULE(1, 0, 2), | ||
118 | + float_3nan_prop_bca = PROPRULE(1, 2, 0), | ||
119 | + float_3nan_prop_cab = PROPRULE(2, 0, 1), | ||
120 | + float_3nan_prop_cba = PROPRULE(2, 1, 0), | ||
121 | + float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK, | ||
122 | + float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK, | ||
123 | + float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK, | ||
124 | + float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK, | ||
125 | + float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK, | ||
126 | + float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK, | ||
127 | +} Float3NaNPropRule; | ||
128 | + | ||
129 | +#undef PROPRULE | ||
130 | + | ||
131 | /* | ||
132 | * Rule for result of fused multiply-add 0 * Inf + NaN. | ||
133 | * This must be a NaN, but implementations differ on whether this | ||
134 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
135 | FloatRoundMode float_rounding_mode; | ||
136 | FloatX80RoundPrec floatx80_rounding_precision; | ||
137 | Float2NaNPropRule float_2nan_prop_rule; | ||
138 | + Float3NaNPropRule float_3nan_prop_rule; | ||
139 | FloatInfZeroNaNRule float_infzeronan_rule; | ||
140 | bool tininess_before_rounding; | ||
141 | /* should denormalised results go to zero and set the inexact flag? */ | ||
142 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
143 | index XXXXXXX..XXXXXXX 100644 | ||
144 | --- a/fpu/softfloat-specialize.c.inc | ||
145 | +++ b/fpu/softfloat-specialize.c.inc | ||
146 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
147 | static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
148 | bool infzero, bool have_snan, float_status *status) | ||
149 | { | ||
150 | + FloatClass cls[3] = { a_cls, b_cls, c_cls }; | ||
151 | + Float3NaNPropRule rule = status->float_3nan_prop_rule; | ||
152 | + int which; | ||
153 | + | ||
154 | /* | ||
155 | * We guarantee not to require the target to tell us how to | ||
156 | * pick a NaN if we're always returning the default NaN. | ||
157 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
158 | } | ||
159 | } | ||
160 | |||
161 | + if (rule == float_3nan_prop_none) { | ||
162 | #if defined(TARGET_ARM) | ||
163 | - | ||
164 | - /* This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
165 | - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. | ||
166 | - */ | ||
167 | - if (is_snan(c_cls)) { | ||
168 | - return 2; | ||
169 | - } else if (is_snan(a_cls)) { | ||
170 | - return 0; | ||
171 | - } else if (is_snan(b_cls)) { | ||
172 | - return 1; | ||
173 | - } else if (is_qnan(c_cls)) { | ||
174 | - return 2; | ||
175 | - } else if (is_qnan(a_cls)) { | ||
176 | - return 0; | ||
177 | - } else { | ||
178 | - return 1; | ||
179 | - } | ||
180 | + /* | ||
181 | + * This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
182 | + * puts the operands to a fused mac operation (a*b)+c in the order c,a,b | ||
183 | + */ | ||
184 | + rule = float_3nan_prop_s_cab; | ||
185 | #elif defined(TARGET_MIPS) | ||
186 | - if (snan_bit_is_one(status)) { | ||
187 | - /* Prefer sNaN over qNaN, in the a, b, c order. */ | ||
188 | - if (is_snan(a_cls)) { | ||
189 | - return 0; | ||
190 | - } else if (is_snan(b_cls)) { | ||
191 | - return 1; | ||
192 | - } else if (is_snan(c_cls)) { | ||
193 | - return 2; | ||
194 | - } else if (is_qnan(a_cls)) { | ||
195 | - return 0; | ||
196 | - } else if (is_qnan(b_cls)) { | ||
197 | - return 1; | ||
198 | + if (snan_bit_is_one(status)) { | ||
199 | + rule = float_3nan_prop_s_abc; | ||
200 | } else { | ||
201 | - return 2; | ||
202 | + rule = float_3nan_prop_s_cab; | ||
203 | } | ||
204 | - } else { | ||
205 | - /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
206 | - if (is_snan(c_cls)) { | ||
207 | - return 2; | ||
208 | - } else if (is_snan(a_cls)) { | ||
209 | - return 0; | ||
210 | - } else if (is_snan(b_cls)) { | ||
211 | - return 1; | ||
212 | - } else if (is_qnan(c_cls)) { | ||
213 | - return 2; | ||
214 | - } else if (is_qnan(a_cls)) { | ||
215 | - return 0; | ||
216 | - } else { | ||
217 | - return 1; | ||
218 | - } | ||
219 | - } | ||
220 | #elif defined(TARGET_LOONGARCH64) | ||
221 | - /* Prefer sNaN over qNaN, in the c, a, b order. */ | ||
222 | - if (is_snan(c_cls)) { | ||
223 | - return 2; | ||
224 | - } else if (is_snan(a_cls)) { | ||
225 | - return 0; | ||
226 | - } else if (is_snan(b_cls)) { | ||
227 | - return 1; | ||
228 | - } else if (is_qnan(c_cls)) { | ||
229 | - return 2; | ||
230 | - } else if (is_qnan(a_cls)) { | ||
231 | - return 0; | ||
232 | - } else { | ||
233 | - return 1; | ||
234 | - } | ||
235 | + rule = float_3nan_prop_s_cab; | ||
236 | #elif defined(TARGET_PPC) | ||
237 | - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
238 | - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
239 | - */ | ||
240 | - if (is_nan(a_cls)) { | ||
241 | - return 0; | ||
242 | - } else if (is_nan(c_cls)) { | ||
243 | - return 2; | ||
244 | - } else { | ||
245 | - return 1; | ||
246 | - } | ||
247 | + /* | ||
248 | + * If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
249 | + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
250 | + */ | ||
251 | + rule = float_3nan_prop_acb; | ||
252 | #elif defined(TARGET_S390X) | ||
253 | - if (is_snan(a_cls)) { | ||
254 | - return 0; | ||
255 | - } else if (is_snan(b_cls)) { | ||
256 | - return 1; | ||
257 | - } else if (is_snan(c_cls)) { | ||
258 | - return 2; | ||
259 | - } else if (is_qnan(a_cls)) { | ||
260 | - return 0; | ||
261 | - } else if (is_qnan(b_cls)) { | ||
262 | - return 1; | ||
263 | - } else { | ||
264 | - return 2; | ||
265 | - } | ||
266 | + rule = float_3nan_prop_s_abc; | ||
267 | #elif defined(TARGET_SPARC) | ||
268 | - /* Prefer SNaN over QNaN, order C, B, A. */ | ||
269 | - if (is_snan(c_cls)) { | ||
270 | - return 2; | ||
271 | - } else if (is_snan(b_cls)) { | ||
272 | - return 1; | ||
273 | - } else if (is_snan(a_cls)) { | ||
274 | - return 0; | ||
275 | - } else if (is_qnan(c_cls)) { | ||
276 | - return 2; | ||
277 | - } else if (is_qnan(b_cls)) { | ||
278 | - return 1; | ||
279 | - } else { | ||
280 | - return 0; | ||
281 | - } | ||
282 | + rule = float_3nan_prop_s_cba; | ||
283 | #elif defined(TARGET_XTENSA) | ||
284 | - /* | ||
285 | - * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns | ||
286 | - * an input NaN if we have one (ie c). | ||
287 | - */ | ||
288 | - if (status->use_first_nan) { | ||
289 | - if (is_nan(a_cls)) { | ||
290 | - return 0; | ||
291 | - } else if (is_nan(b_cls)) { | ||
292 | - return 1; | ||
293 | + if (status->use_first_nan) { | ||
294 | + rule = float_3nan_prop_abc; | ||
295 | } else { | ||
296 | - return 2; | ||
297 | + rule = float_3nan_prop_cba; | ||
298 | } | ||
299 | - } else { | ||
300 | - if (is_nan(c_cls)) { | ||
301 | - return 2; | ||
302 | - } else if (is_nan(b_cls)) { | ||
303 | - return 1; | ||
304 | - } else { | ||
305 | - return 0; | ||
306 | - } | ||
307 | - } | ||
308 | #else | ||
309 | - /* A default implementation: prefer a to b to c. | ||
310 | - * This is unlikely to actually match any real implementation. | ||
311 | - */ | ||
312 | - if (is_nan(a_cls)) { | ||
313 | - return 0; | ||
314 | - } else if (is_nan(b_cls)) { | ||
315 | - return 1; | ||
316 | - } else { | ||
317 | - return 2; | ||
318 | - } | ||
319 | + rule = float_3nan_prop_abc; | ||
320 | #endif | ||
321 | + } | ||
322 | + | ||
323 | + assert(rule != float_3nan_prop_none); | ||
324 | + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
325 | + /* We have at least one SNaN input and should prefer it */ | ||
326 | + do { | ||
327 | + which = rule & R_3NAN_1ST_MASK; | ||
328 | + rule >>= R_3NAN_1ST_LENGTH; | ||
329 | + } while (!is_snan(cls[which])); | ||
330 | + } else { | ||
331 | + do { | ||
332 | + which = rule & R_3NAN_1ST_MASK; | ||
333 | + rule >>= R_3NAN_1ST_LENGTH; | ||
334 | + } while (!is_nan(cls[which])); | ||
335 | + } | ||
336 | + return which; | ||
337 | } | ||
338 | |||
339 | /*---------------------------------------------------------------------------- | ||
340 | -- | ||
341 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Explicitly set a rule in the softfloat tests for propagating NaNs in | ||
2 | the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and | ||
3 | so we should select here the Arm rule of float_3nan_prop_s_cab. | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20241202131347.498124-17-peter.maydell@linaro.org | ||
8 | --- | ||
9 | tests/fp/fp-bench.c | 1 + | ||
10 | tests/fp/fp-test.c | 1 + | ||
11 | 2 files changed, 2 insertions(+) | ||
12 | |||
13 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/tests/fp/fp-bench.c | ||
16 | +++ b/tests/fp/fp-bench.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) | ||
18 | * doesn't specify match those used by the Arm architecture. | ||
19 | */ | ||
20 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); | ||
21 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); | ||
22 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); | ||
23 | |||
24 | f = bench_funcs[operation][precision]; | ||
25 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/tests/fp/fp-test.c | ||
28 | +++ b/tests/fp/fp-test.c | ||
29 | @@ -XXX,XX +XXX,XX @@ void run_test(void) | ||
30 | * doesn't specify match those used by the Arm architecture. | ||
31 | */ | ||
32 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
33 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); | ||
34 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); | ||
35 | |||
36 | genCases_setLevel(test_level); | ||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for Arm, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-18-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/cpu.c | 5 +++++ | ||
9 | fpu/softfloat-specialize.c.inc | 8 +------- | ||
10 | 2 files changed, 6 insertions(+), 7 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/cpu.c | ||
15 | +++ b/target/arm/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, | ||
17 | * * tininess-before-rounding | ||
18 | * * 2-input NaN propagation prefers SNaN over QNaN, and then | ||
19 | * operand A over operand B (see FPProcessNaNs() pseudocode) | ||
20 | + * * 3-input NaN propagation prefers SNaN over QNaN, and then | ||
21 | + * operand C over A over B (see FPProcessNaNs3() pseudocode, | ||
22 | + * but note that for QEMU muladd is a * b + c, whereas for | ||
23 | + * the pseudocode function the arguments are in the order c, a, b. | ||
24 | * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, | ||
25 | * and the input NaN if it is signalling | ||
26 | */ | ||
27 | @@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s) | ||
28 | { | ||
29 | set_float_detect_tininess(float_tininess_before_rounding, s); | ||
30 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); | ||
31 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); | ||
32 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); | ||
33 | } | ||
34 | |||
35 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/fpu/softfloat-specialize.c.inc | ||
38 | +++ b/fpu/softfloat-specialize.c.inc | ||
39 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
40 | } | ||
41 | |||
42 | if (rule == float_3nan_prop_none) { | ||
43 | -#if defined(TARGET_ARM) | ||
44 | - /* | ||
45 | - * This looks different from the ARM ARM pseudocode, because the ARM ARM | ||
46 | - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b | ||
47 | - */ | ||
48 | - rule = float_3nan_prop_s_cab; | ||
49 | -#elif defined(TARGET_MIPS) | ||
50 | +#if defined(TARGET_MIPS) | ||
51 | if (snan_bit_is_one(status)) { | ||
52 | rule = float_3nan_prop_s_abc; | ||
53 | } else { | ||
54 | -- | ||
55 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for loongarch, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-19-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/loongarch/tcg/fpu_helper.c | 1 + | ||
9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
10 | 2 files changed, 1 insertion(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/loongarch/tcg/fpu_helper.c | ||
15 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) | ||
17 | * case sets InvalidOp and returns the input value 'c' | ||
18 | */ | ||
19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
20 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); | ||
21 | } | ||
22 | |||
23 | int ieee_ex_to_loongarch(int xcpt) | ||
24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/fpu/softfloat-specialize.c.inc | ||
27 | +++ b/fpu/softfloat-specialize.c.inc | ||
28 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
29 | } else { | ||
30 | rule = float_3nan_prop_s_cab; | ||
31 | } | ||
32 | -#elif defined(TARGET_LOONGARCH64) | ||
33 | - rule = float_3nan_prop_s_cab; | ||
34 | #elif defined(TARGET_PPC) | ||
35 | /* | ||
36 | * If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for PPC, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-20-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/ppc/cpu_init.c | 8 ++++++++ | ||
9 | fpu/softfloat-specialize.c.inc | 6 ------ | ||
10 | 2 files changed, 8 insertions(+), 6 deletions(-) | ||
11 | |||
12 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/ppc/cpu_init.c | ||
15 | +++ b/target/ppc/cpu_init.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | */ | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); | ||
20 | + /* | ||
21 | + * NaN propagation for fused multiply-add: | ||
22 | + * if fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
23 | + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
24 | + * whereas QEMU labels the operands as (a * b) + c. | ||
25 | + */ | ||
26 | + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status); | ||
27 | + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status); | ||
28 | /* | ||
29 | * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer | ||
30 | * to return an input NaN if we have one (ie c) rather than generating | ||
31 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/fpu/softfloat-specialize.c.inc | ||
34 | +++ b/fpu/softfloat-specialize.c.inc | ||
35 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
36 | } else { | ||
37 | rule = float_3nan_prop_s_cab; | ||
38 | } | ||
39 | -#elif defined(TARGET_PPC) | ||
40 | - /* | ||
41 | - * If fRA is a NaN return it; otherwise if fRB is a NaN return it; | ||
42 | - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB | ||
43 | - */ | ||
44 | - rule = float_3nan_prop_acb; | ||
45 | #elif defined(TARGET_S390X) | ||
46 | rule = float_3nan_prop_s_abc; | ||
47 | #elif defined(TARGET_SPARC) | ||
48 | -- | ||
49 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for s390x, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-21-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/s390x/cpu.c | 1 + | ||
9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
10 | 2 files changed, 1 insertion(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/s390x/cpu.c | ||
15 | +++ b/target/s390x/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | set_float_detect_tininess(float_tininess_before_rounding, | ||
18 | &env->fpu_status); | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); | ||
20 | + set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); | ||
21 | set_float_infzeronan_rule(float_infzeronan_dnan_always, | ||
22 | &env->fpu_status); | ||
23 | /* fall through */ | ||
24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/fpu/softfloat-specialize.c.inc | ||
27 | +++ b/fpu/softfloat-specialize.c.inc | ||
28 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
29 | } else { | ||
30 | rule = float_3nan_prop_s_cab; | ||
31 | } | ||
32 | -#elif defined(TARGET_S390X) | ||
33 | - rule = float_3nan_prop_s_abc; | ||
34 | #elif defined(TARGET_SPARC) | ||
35 | rule = float_3nan_prop_s_cba; | ||
36 | #elif defined(TARGET_XTENSA) | ||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for SPARC, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-22-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/sparc/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 2 -- | ||
10 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/sparc/cpu.c | ||
15 | +++ b/target/sparc/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) | ||
17 | * the CPU state struct so it won't get zeroed on reset. | ||
18 | */ | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); | ||
20 | + /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ | ||
21 | + set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); | ||
22 | /* For inf * 0 + NaN, return the input NaN */ | ||
23 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
24 | |||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
30 | } else { | ||
31 | rule = float_3nan_prop_s_cab; | ||
32 | } | ||
33 | -#elif defined(TARGET_SPARC) | ||
34 | - rule = float_3nan_prop_s_cba; | ||
35 | #elif defined(TARGET_XTENSA) | ||
36 | if (status->use_first_nan) { | ||
37 | rule = float_3nan_prop_abc; | ||
38 | -- | ||
39 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for Arm, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-23-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/mips/fpu_helper.h | 4 ++++ | ||
9 | target/mips/msa.c | 3 +++ | ||
10 | fpu/softfloat-specialize.c.inc | 8 +------- | ||
11 | 3 files changed, 8 insertions(+), 7 deletions(-) | ||
12 | |||
13 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/mips/fpu_helper.h | ||
16 | +++ b/target/mips/fpu_helper.h | ||
17 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
18 | { | ||
19 | bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); | ||
20 | FloatInfZeroNaNRule izn_rule; | ||
21 | + Float3NaNPropRule nan3_rule; | ||
22 | |||
23 | /* | ||
24 | * With nan2008, SNaNs are silenced in the usual way. | ||
25 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
26 | */ | ||
27 | izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; | ||
28 | set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); | ||
29 | + nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; | ||
30 | + set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); | ||
31 | + | ||
32 | } | ||
33 | |||
34 | static inline void restore_fp_status(CPUMIPSState *env) | ||
35 | diff --git a/target/mips/msa.c b/target/mips/msa.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/mips/msa.c | ||
38 | +++ b/target/mips/msa.c | ||
39 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) | ||
40 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, | ||
41 | &env->active_tc.msa_fp_status); | ||
42 | |||
43 | + set_float_3nan_prop_rule(float_3nan_prop_s_cab, | ||
44 | + &env->active_tc.msa_fp_status); | ||
45 | + | ||
46 | /* clear float_status exception flags */ | ||
47 | set_float_exception_flags(0, &env->active_tc.msa_fp_status); | ||
48 | |||
49 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/fpu/softfloat-specialize.c.inc | ||
52 | +++ b/fpu/softfloat-specialize.c.inc | ||
53 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
54 | } | ||
55 | |||
56 | if (rule == float_3nan_prop_none) { | ||
57 | -#if defined(TARGET_MIPS) | ||
58 | - if (snan_bit_is_one(status)) { | ||
59 | - rule = float_3nan_prop_s_abc; | ||
60 | - } else { | ||
61 | - rule = float_3nan_prop_s_cab; | ||
62 | - } | ||
63 | -#elif defined(TARGET_XTENSA) | ||
64 | +#if defined(TARGET_XTENSA) | ||
65 | if (status->use_first_nan) { | ||
66 | rule = float_3nan_prop_abc; | ||
67 | } else { | ||
68 | -- | ||
69 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for xtensa, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-24-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/xtensa/fpu_helper.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 8 -------- | ||
10 | 2 files changed, 2 insertions(+), 8 deletions(-) | ||
11 | |||
12 | diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/xtensa/fpu_helper.c | ||
15 | +++ b/target/xtensa/fpu_helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) | ||
17 | set_use_first_nan(use_first, &env->fp_status); | ||
18 | set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, | ||
19 | &env->fp_status); | ||
20 | + set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, | ||
21 | + &env->fp_status); | ||
22 | } | ||
23 | |||
24 | void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
30 | } | ||
31 | |||
32 | if (rule == float_3nan_prop_none) { | ||
33 | -#if defined(TARGET_XTENSA) | ||
34 | - if (status->use_first_nan) { | ||
35 | - rule = float_3nan_prop_abc; | ||
36 | - } else { | ||
37 | - rule = float_3nan_prop_cba; | ||
38 | - } | ||
39 | -#else | ||
40 | rule = float_3nan_prop_abc; | ||
41 | -#endif | ||
42 | } | ||
43 | |||
44 | assert(rule != float_3nan_prop_none); | ||
45 | -- | ||
46 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for i386. We had no | ||
2 | i386-specific behaviour in the old ifdef ladder, so we were using the | ||
3 | default "prefer a then b then c" fallback; this is actually the | ||
4 | correct per-the-spec handling for i386. | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20241202131347.498124-25-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/i386/tcg/fpu_helper.c | 1 + | ||
11 | 1 file changed, 1 insertion(+) | ||
12 | |||
13 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/i386/tcg/fpu_helper.c | ||
16 | +++ b/target/i386/tcg/fpu_helper.c | ||
17 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) | ||
18 | * there are multiple input NaNs they are selected in the order a, b, c. | ||
19 | */ | ||
20 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); | ||
21 | + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); | ||
22 | } | ||
23 | |||
24 | static inline uint8_t save_exception_flags(CPUX86State *env) | ||
25 | -- | ||
26 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the Float3NaNPropRule explicitly for HPPA, and remove the | ||
2 | ifdef from pickNaNMulAdd(). | ||
1 | 3 | ||
4 | HPPA is the only target that was using the default branch of the | ||
5 | ifdef ladder (other targets either do not use muladd or set | ||
6 | default_nan_mode), so we can remove the ifdef fallback entirely now | ||
7 | (allowing the "rule not set" case to fall into the default of the | ||
8 | switch statement and assert). | ||
9 | |||
10 | We add a TODO note that the HPPA rule is probably wrong; this is | ||
11 | not a behavioural change for this refactoring. | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20241202131347.498124-26-peter.maydell@linaro.org | ||
16 | --- | ||
17 | target/hppa/fpu_helper.c | 8 ++++++++ | ||
18 | fpu/softfloat-specialize.c.inc | 4 ---- | ||
19 | 2 files changed, 8 insertions(+), 4 deletions(-) | ||
20 | |||
21 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/target/hppa/fpu_helper.c | ||
24 | +++ b/target/hppa/fpu_helper.c | ||
25 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) | ||
26 | * HPPA does note implement a CPU reset method at all... | ||
27 | */ | ||
28 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); | ||
29 | + /* | ||
30 | + * TODO: The HPPA architecture reference only documents its NaN | ||
31 | + * propagation rule for 2-operand operations. Testing on real hardware | ||
32 | + * might be necessary to confirm whether this order for muladd is correct. | ||
33 | + * Not preferring the SNaN is almost certainly incorrect as it diverges | ||
34 | + * from the documented rules for 2-operand operations. | ||
35 | + */ | ||
36 | + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); | ||
37 | /* For inf * 0 + NaN, return the input NaN */ | ||
38 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
39 | } | ||
40 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/fpu/softfloat-specialize.c.inc | ||
43 | +++ b/fpu/softfloat-specialize.c.inc | ||
44 | @@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
45 | } | ||
46 | } | ||
47 | |||
48 | - if (rule == float_3nan_prop_none) { | ||
49 | - rule = float_3nan_prop_abc; | ||
50 | - } | ||
51 | - | ||
52 | assert(rule != float_3nan_prop_none); | ||
53 | if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
54 | /* We have at least one SNaN input and should prefer it */ | ||
55 | -- | ||
56 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The use_first_nan field in float_status was an xtensa-specific way to | ||
2 | select at runtime from two different NaN propagation rules. Now that | ||
3 | xtensa is using the target-agnostic NaN propagation rule selection | ||
4 | that we've just added, we can remove use_first_nan, because there is | ||
5 | no longer any code that reads it. | ||
1 | 6 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20241202131347.498124-27-peter.maydell@linaro.org | ||
10 | --- | ||
11 | include/fpu/softfloat-helpers.h | 5 ----- | ||
12 | include/fpu/softfloat-types.h | 1 - | ||
13 | target/xtensa/fpu_helper.c | 1 - | ||
14 | 3 files changed, 7 deletions(-) | ||
15 | |||
16 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/include/fpu/softfloat-helpers.h | ||
19 | +++ b/include/fpu/softfloat-helpers.h | ||
20 | @@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status) | ||
21 | status->snan_bit_is_one = val; | ||
22 | } | ||
23 | |||
24 | -static inline void set_use_first_nan(bool val, float_status *status) | ||
25 | -{ | ||
26 | - status->use_first_nan = val; | ||
27 | -} | ||
28 | - | ||
29 | static inline void set_no_signaling_nans(bool val, float_status *status) | ||
30 | { | ||
31 | status->no_signaling_nans = val; | ||
32 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/include/fpu/softfloat-types.h | ||
35 | +++ b/include/fpu/softfloat-types.h | ||
36 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
37 | * softfloat-specialize.inc.c) | ||
38 | */ | ||
39 | bool snan_bit_is_one; | ||
40 | - bool use_first_nan; | ||
41 | bool no_signaling_nans; | ||
42 | /* should overflowed results subtract re_bias to its exponent? */ | ||
43 | bool rebias_overflow; | ||
44 | diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/xtensa/fpu_helper.c | ||
47 | +++ b/target/xtensa/fpu_helper.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static const struct { | ||
49 | |||
50 | void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) | ||
51 | { | ||
52 | - set_use_first_nan(use_first, &env->fp_status); | ||
53 | set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, | ||
54 | &env->fp_status); | ||
55 | set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, | ||
56 | -- | ||
57 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL) | ||
2 | to get the NaN bit pattern to reset the FPU registers. This | ||
3 | works because it happens that our implementation of | ||
4 | floatx80_default_nan() doesn't actually look at the float_status | ||
5 | pointer except for TARGET_MIPS. However, this isn't guaranteed, | ||
6 | and to be able to remove the ifdef in floatx80_default_nan() | ||
7 | we're going to need a real float_status here. | ||
1 | 8 | ||
9 | Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status | ||
10 | earlier, and thus can pass it to floatx80_default_nan(). | ||
11 | |||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20241202131347.498124-28-peter.maydell@linaro.org | ||
15 | --- | ||
16 | target/m68k/cpu.c | 12 +++++++----- | ||
17 | 1 file changed, 7 insertions(+), 5 deletions(-) | ||
18 | |||
19 | diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/m68k/cpu.c | ||
22 | +++ b/target/m68k/cpu.c | ||
23 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
24 | CPUState *cs = CPU(obj); | ||
25 | M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj); | ||
26 | CPUM68KState *env = cpu_env(cs); | ||
27 | - floatx80 nan = floatx80_default_nan(NULL); | ||
28 | + floatx80 nan; | ||
29 | int i; | ||
30 | |||
31 | if (mcc->parent_phases.hold) { | ||
32 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
33 | #else | ||
34 | cpu_m68k_set_sr(env, SR_S | SR_I); | ||
35 | #endif | ||
36 | - for (i = 0; i < 8; i++) { | ||
37 | - env->fregs[i].d = nan; | ||
38 | - } | ||
39 | - cpu_m68k_set_fpcr(env, 0); | ||
40 | /* | ||
41 | * M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL | ||
42 | * 3.4 FLOATING-POINT INSTRUCTION DETAILS | ||
43 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
44 | * preceding paragraph for nonsignaling NaNs. | ||
45 | */ | ||
46 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
47 | + | ||
48 | + nan = floatx80_default_nan(&env->fp_status); | ||
49 | + for (i = 0; i < 8; i++) { | ||
50 | + env->fregs[i].d = nan; | ||
51 | + } | ||
52 | + cpu_m68k_set_fpcr(env, 0); | ||
53 | env->fpsr = 0; | ||
54 | |||
55 | /* TODO: We should set PC from the interrupt vector. */ | ||
56 | -- | ||
57 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | We create our 128-bit default NaN by calling parts64_default_nan() | ||
2 | and then adjusting the result. We can do the same trick for creating | ||
3 | the floatx80 default NaN, which lets us drop a target ifdef. | ||
1 | 4 | ||
5 | floatx80 is used only by: | ||
6 | i386 | ||
7 | m68k | ||
8 | arm nwfpe old floating-point emulation emulation support | ||
9 | (which is essentially dead, especially the parts involving floatx80) | ||
10 | PPC (only in the xsrqpxp instruction, which just rounds an input | ||
11 | value by converting to floatx80 and back, so will never generate | ||
12 | the default NaN) | ||
13 | |||
14 | The floatx80 default NaN as currently implemented is: | ||
15 | m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1 | ||
16 | i386: sign = 1, exp = 1...1, int = 1, frac = 10...0 | ||
17 | |||
18 | These are the same as the parts64_default_nan for these architectures. | ||
19 | |||
20 | This is technically a possible behaviour change for arm linux-user | ||
21 | nwfpe emulation emulation, because the default NaN will now have the | ||
22 | sign bit clear. But we were already generating a different floatx80 | ||
23 | default NaN from the real kernel emulation we are supposedly | ||
24 | following, which appears to use an all-bits-1 value: | ||
25 | https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267 | ||
26 | |||
27 | This won't affect the only "real" use of the nwfpe emulation, which | ||
28 | is ancient binaries that used it as part of the old floating point | ||
29 | calling convention; that only uses loads and stores of 32 and 64 bit | ||
30 | floats, not any of the floatx80 behaviour the original hardware had. | ||
31 | We also get the nwfpe float64 default NaN value wrong: | ||
32 | https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166 | ||
33 | so if we ever cared about this obscure corner the right fix would be | ||
34 | to correct that so nwfpe used its own default-NaN setting rather | ||
35 | than the Arm VFP one. | ||
36 | |||
37 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
38 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
39 | Message-id: 20241202131347.498124-29-peter.maydell@linaro.org | ||
40 | --- | ||
41 | fpu/softfloat-specialize.c.inc | 20 ++++++++++---------- | ||
42 | 1 file changed, 10 insertions(+), 10 deletions(-) | ||
43 | |||
44 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/fpu/softfloat-specialize.c.inc | ||
47 | +++ b/fpu/softfloat-specialize.c.inc | ||
48 | @@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status) | ||
49 | floatx80 floatx80_default_nan(float_status *status) | ||
50 | { | ||
51 | floatx80 r; | ||
52 | + /* | ||
53 | + * Extrapolate from the choices made by parts64_default_nan to fill | ||
54 | + * in the floatx80 format. We assume that floatx80's explicit | ||
55 | + * integer bit is always set (this is true for i386 and m68k, | ||
56 | + * which are the only real users of this format). | ||
57 | + */ | ||
58 | + FloatParts64 p64; | ||
59 | + parts64_default_nan(&p64, status); | ||
60 | |||
61 | - /* None of the targets that have snan_bit_is_one use floatx80. */ | ||
62 | - assert(!snan_bit_is_one(status)); | ||
63 | -#if defined(TARGET_M68K) | ||
64 | - r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); | ||
65 | - r.high = 0x7FFF; | ||
66 | -#else | ||
67 | - /* X86 */ | ||
68 | - r.low = UINT64_C(0xC000000000000000); | ||
69 | - r.high = 0xFFFF; | ||
70 | -#endif | ||
71 | + r.high = 0x7FFF | (p64.sign << 15); | ||
72 | + r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac; | ||
73 | return r; | ||
74 | } | ||
75 | |||
76 | -- | ||
77 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass | ||
2 | a zero-initialized float_status struct to float32_is_quiet_nan() and | ||
3 | float64_is_quiet_nan(), with the cryptic comment "for | ||
4 | snan_bit_is_one". | ||
1 | 5 | ||
6 | This pattern appears to have been copied from target/riscv, where it | ||
7 | is used because the functions there do not have ready access to the | ||
8 | CPU state struct. The comment presumably refers to the fact that the | ||
9 | main reason the is_quiet_nan() functions want the float_state is | ||
10 | because they want to know about the snan_bit_is_one config. | ||
11 | |||
12 | In the loongarch helpers, though, we have the CPU state struct | ||
13 | to hand. Use the usual env->fp_status here. This avoids our needing | ||
14 | to track that we need to update the initializer of the local | ||
15 | float_status structs when the core softfloat code adds new | ||
16 | options for targets to configure their behaviour. | ||
17 | |||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Message-id: 20241202131347.498124-30-peter.maydell@linaro.org | ||
21 | --- | ||
22 | target/loongarch/tcg/fpu_helper.c | 6 ++---- | ||
23 | 1 file changed, 2 insertions(+), 4 deletions(-) | ||
24 | |||
25 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/target/loongarch/tcg/fpu_helper.c | ||
28 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
29 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj) | ||
30 | } else if (float32_is_zero_or_denormal(f)) { | ||
31 | return sign ? 1 << 4 : 1 << 8; | ||
32 | } else if (float32_is_any_nan(f)) { | ||
33 | - float_status s = { }; /* for snan_bit_is_one */ | ||
34 | - return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; | ||
35 | + return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; | ||
36 | } else { | ||
37 | return sign ? 1 << 3 : 1 << 7; | ||
38 | } | ||
39 | @@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj) | ||
40 | } else if (float64_is_zero_or_denormal(f)) { | ||
41 | return sign ? 1 << 4 : 1 << 8; | ||
42 | } else if (float64_is_any_nan(f)) { | ||
43 | - float_status s = { }; /* for snan_bit_is_one */ | ||
44 | - return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; | ||
45 | + return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; | ||
46 | } else { | ||
47 | return sign ? 1 << 3 : 1 << 7; | ||
48 | } | ||
49 | -- | ||
50 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In the frem helper, we have a local float_status because we want to | ||
2 | execute the floatx80_div() with a custom rounding mode. Instead of | ||
3 | zero-initializing the local float_status and then having to set it up | ||
4 | with the m68k standard behaviour (including the NaN propagation rule | ||
5 | and copying the rounding precision from env->fp_status), initialize | ||
6 | it as a complete copy of env->fp_status. This will avoid our having | ||
7 | to add new code in this function for every new config knob we add | ||
8 | to fp_status. | ||
1 | 9 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20241202131347.498124-31-peter.maydell@linaro.org | ||
13 | --- | ||
14 | target/m68k/fpu_helper.c | 6 ++---- | ||
15 | 1 file changed, 2 insertions(+), 4 deletions(-) | ||
16 | |||
17 | diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/m68k/fpu_helper.c | ||
20 | +++ b/target/m68k/fpu_helper.c | ||
21 | @@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) | ||
22 | |||
23 | fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status); | ||
24 | if (!floatx80_is_any_nan(fp_rem)) { | ||
25 | - float_status fp_status = { }; | ||
26 | + /* Use local temporary fp_status to set different rounding mode */ | ||
27 | + float_status fp_status = env->fp_status; | ||
28 | uint32_t quotient; | ||
29 | int sign; | ||
30 | |||
31 | /* Calculate quotient directly using round to nearest mode */ | ||
32 | - set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status); | ||
33 | set_float_rounding_mode(float_round_nearest_even, &fp_status); | ||
34 | - set_floatx80_rounding_precision( | ||
35 | - get_floatx80_rounding_precision(&env->fp_status), &fp_status); | ||
36 | fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status); | ||
37 | |||
38 | sign = extractFloatx80Sign(fp_quot.d); | ||
39 | -- | ||
40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion | ||
2 | from float64 to floatx80 using a scratch float_status, because we | ||
3 | don't want the conversion to affect the CPU's floating point exception | ||
4 | status. Currently we use a zero-initialized float_status. This will | ||
5 | get steadily more awkward as we add config knobs to float_status | ||
6 | that the target must initialize. Avoid having to add any of that | ||
7 | configuration here by instead initializing our local float_status | ||
8 | from the env->fp_status. | ||
1 | 9 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20241202131347.498124-32-peter.maydell@linaro.org | ||
13 | --- | ||
14 | target/m68k/helper.c | 6 ++++-- | ||
15 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
16 | |||
17 | diff --git a/target/m68k/helper.c b/target/m68k/helper.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/m68k/helper.c | ||
20 | +++ b/target/m68k/helper.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) | ||
22 | CPUM68KState *env = &cpu->env; | ||
23 | |||
24 | if (n < 8) { | ||
25 | - float_status s = {}; | ||
26 | + /* Use scratch float_status so any exceptions don't change CPU state */ | ||
27 | + float_status s = env->fp_status; | ||
28 | return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s)); | ||
29 | } | ||
30 | switch (n) { | ||
31 | @@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) | ||
32 | CPUM68KState *env = &cpu->env; | ||
33 | |||
34 | if (n < 8) { | ||
35 | - float_status s = {}; | ||
36 | + /* Use scratch float_status so any exceptions don't change CPU state */ | ||
37 | + float_status s = env->fp_status; | ||
38 | env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s); | ||
39 | return 8; | ||
40 | } | ||
41 | -- | ||
42 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In the helper functions flcmps and flcmpd we use a scratch float_status | ||
2 | so that we don't change the CPU state if the comparison raises any | ||
3 | floating point exception flags. Instead of zero-initializing this | ||
4 | scratch float_status, initialize it as a copy of env->fp_status. This | ||
5 | avoids the need to explicitly initialize settings like the NaN | ||
6 | propagation rule or others we might add to softfloat in future. | ||
1 | 7 | ||
8 | To do this we need to pass the CPU env pointer in to the helper. | ||
9 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20241202131347.498124-33-peter.maydell@linaro.org | ||
13 | --- | ||
14 | target/sparc/helper.h | 4 ++-- | ||
15 | target/sparc/fop_helper.c | 8 ++++---- | ||
16 | target/sparc/translate.c | 4 ++-- | ||
17 | 3 files changed, 8 insertions(+), 8 deletions(-) | ||
18 | |||
19 | diff --git a/target/sparc/helper.h b/target/sparc/helper.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/sparc/helper.h | ||
22 | +++ b/target/sparc/helper.h | ||
23 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64) | ||
24 | DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64) | ||
25 | DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128) | ||
26 | DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128) | ||
27 | -DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32) | ||
28 | -DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64) | ||
29 | +DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32) | ||
30 | +DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64) | ||
31 | DEF_HELPER_2(raise_exception, noreturn, env, int) | ||
32 | |||
33 | DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) | ||
34 | diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/sparc/fop_helper.c | ||
37 | +++ b/target/sparc/fop_helper.c | ||
38 | @@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2) | ||
39 | return finish_fcmp(env, r, GETPC()); | ||
40 | } | ||
41 | |||
42 | -uint32_t helper_flcmps(float32 src1, float32 src2) | ||
43 | +uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2) | ||
44 | { | ||
45 | /* | ||
46 | * FLCMP never raises an exception nor modifies any FSR fields. | ||
47 | * Perform the comparison with a dummy fp environment. | ||
48 | */ | ||
49 | - float_status discard = { }; | ||
50 | + float_status discard = env->fp_status; | ||
51 | FloatRelation r; | ||
52 | |||
53 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); | ||
54 | @@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2) | ||
55 | g_assert_not_reached(); | ||
56 | } | ||
57 | |||
58 | -uint32_t helper_flcmpd(float64 src1, float64 src2) | ||
59 | +uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2) | ||
60 | { | ||
61 | - float_status discard = { }; | ||
62 | + float_status discard = env->fp_status; | ||
63 | FloatRelation r; | ||
64 | |||
65 | set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); | ||
66 | diff --git a/target/sparc/translate.c b/target/sparc/translate.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/sparc/translate.c | ||
69 | +++ b/target/sparc/translate.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a) | ||
71 | |||
72 | src1 = gen_load_fpr_F(dc, a->rs1); | ||
73 | src2 = gen_load_fpr_F(dc, a->rs2); | ||
74 | - gen_helper_flcmps(cpu_fcc[a->cc], src1, src2); | ||
75 | + gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2); | ||
76 | return advance_pc(dc); | ||
77 | } | ||
78 | |||
79 | @@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a) | ||
80 | |||
81 | src1 = gen_load_fpr_D(dc, a->rs1); | ||
82 | src2 = gen_load_fpr_D(dc, a->rs2); | ||
83 | - gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2); | ||
84 | + gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2); | ||
85 | return advance_pc(dc); | ||
86 | } | ||
87 | |||
88 | -- | ||
89 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In the helper_compute_fprf functions, we pass a dummy float_status | ||
2 | in to the is_signaling_nan() function. This is unnecessary, because | ||
3 | we have convenient access to the CPU env pointer here and that | ||
4 | is already set up with the correct values for the snan_bit_is_one | ||
5 | and no_signaling_nans config settings. is_signaling_nan() doesn't | ||
6 | ever update the fp_status with any exception flags, so there is | ||
7 | no reason not to use env->fp_status here. | ||
1 | 8 | ||
9 | Use env->fp_status instead of the dummy fp_status. | ||
10 | |||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Message-id: 20241202131347.498124-34-peter.maydell@linaro.org | ||
14 | --- | ||
15 | target/ppc/fpu_helper.c | 3 +-- | ||
16 | 1 file changed, 1 insertion(+), 2 deletions(-) | ||
17 | |||
18 | diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/ppc/fpu_helper.c | ||
21 | +++ b/target/ppc/fpu_helper.c | ||
22 | @@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \ | ||
23 | } else if (tp##_is_infinity(arg)) { \ | ||
24 | fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \ | ||
25 | } else { \ | ||
26 | - float_status dummy = { }; /* snan_bit_is_one = 0 */ \ | ||
27 | - if (tp##_is_signaling_nan(arg, &dummy)) { \ | ||
28 | + if (tp##_is_signaling_nan(arg, &env->fp_status)) { \ | ||
29 | fprf = 0x00 << FPSCR_FPRF; \ | ||
30 | } else { \ | ||
31 | fprf = 0x11 << FPSCR_FPRF; \ | ||
32 | -- | ||
33 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Rename from sve_zcr_get_valid_len and make accessible | 3 | Now that float_status has a bunch of fp parameters, |
4 | from outside of helper.c. | 4 | it is easier to copy an existing structure than create |
5 | one from scratch. Begin by copying the structure that | ||
6 | corresponds to the FPSR and make only the adjustments | ||
7 | required for BFloat16 semantics. | ||
5 | 8 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20210723203344.968563-3-richard.henderson@linaro.org | 12 | Message-id: 20241203203949.483774-2-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 14 | --- |
11 | target/arm/internals.h | 10 ++++++++++ | 15 | target/arm/tcg/vec_helper.c | 20 +++++++------------- |
12 | target/arm/helper.c | 4 ++-- | 16 | 1 file changed, 7 insertions(+), 13 deletions(-) |
13 | 2 files changed, 12 insertions(+), 2 deletions(-) | ||
14 | 17 | ||
15 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 18 | diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c |
16 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/internals.h | 20 | --- a/target/arm/tcg/vec_helper.c |
18 | +++ b/target/arm/internals.h | 21 | +++ b/target/arm/tcg/vec_helper.c |
19 | @@ -XXX,XX +XXX,XX @@ void arm_translate_init(void); | 22 | @@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp) |
20 | void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); | 23 | * no effect on AArch32 instructions. |
21 | #endif /* CONFIG_TCG */ | 24 | */ |
22 | 25 | bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF; | |
23 | +/** | 26 | - *statusp = (float_status){ |
24 | + * aarch64_sve_zcr_get_valid_len: | 27 | - .tininess_before_rounding = float_tininess_before_rounding, |
25 | + * @cpu: cpu context | 28 | - .float_rounding_mode = float_round_to_odd_inf, |
26 | + * @start_len: maximum len to consider | 29 | - .flush_to_zero = true, |
27 | + * | 30 | - .flush_inputs_to_zero = true, |
28 | + * Return the maximum supported sve vector length <= @start_len. | 31 | - .default_nan_mode = true, |
29 | + * Note that both @start_len and the return value are in units | 32 | - }; |
30 | + * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128. | 33 | + |
31 | + */ | 34 | + *statusp = env->vfp.fp_status; |
32 | +uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len); | 35 | + set_default_nan_mode(true, statusp); |
33 | 36 | ||
34 | enum arm_fprounding { | 37 | if (ebf) { |
35 | FPROUNDING_TIEEVEN, | 38 | - float_status *fpst = &env->vfp.fp_status; |
36 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 39 | - set_flush_to_zero(get_flush_to_zero(fpst), statusp); |
37 | index XXXXXXX..XXXXXXX 100644 | 40 | - set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp); |
38 | --- a/target/arm/helper.c | 41 | - set_float_rounding_mode(get_float_rounding_mode(fpst), statusp); |
39 | +++ b/target/arm/helper.c | 42 | - |
40 | @@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el) | 43 | /* EBF=1 needs to do a step with round-to-odd semantics */ |
41 | return 0; | 44 | *oddstatusp = *statusp; |
45 | set_float_rounding_mode(float_round_to_odd, oddstatusp); | ||
46 | + } else { | ||
47 | + set_flush_to_zero(true, statusp); | ||
48 | + set_flush_inputs_to_zero(true, statusp); | ||
49 | + set_float_rounding_mode(float_round_to_odd_inf, statusp); | ||
50 | } | ||
51 | - | ||
52 | return ebf; | ||
42 | } | 53 | } |
43 | 54 | ||
44 | -static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) | ||
45 | +uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) | ||
46 | { | ||
47 | uint32_t end_len; | ||
48 | |||
49 | @@ -XXX,XX +XXX,XX @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) | ||
50 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); | ||
51 | } | ||
52 | |||
53 | - return sve_zcr_get_valid_len(cpu, zcr_len); | ||
54 | + return aarch64_sve_zcr_get_valid_len(cpu, zcr_len); | ||
55 | } | ||
56 | |||
57 | static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
58 | -- | 55 | -- |
59 | 2.20.1 | 56 | 2.34.1 |
60 | 57 | ||
61 | 58 | diff view generated by jsdifflib |
1 | In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if | 1 | Currently we hardcode the default NaN value in parts64_default_nan() |
---|---|---|---|
2 | the register is accessed NonSecure and the highest priority pending | 2 | using a compile-time ifdef ladder. This is awkward for two cases: |
3 | enabled exception (that would be returned in the VECTPENDING field) | 3 | * for single-QEMU-binary we can't hard-code target-specifics like this |
4 | targets Secure, then the VECTPENDING field must read 1 rather than | 4 | * for Arm FEAT_AFP the default NaN value depends on FPCR.AH |
5 | the exception number of the pending exception. Implement this. | 5 | (specifically the sign bit is different) |
6 | |||
7 | Add a field to float_status to specify the default NaN value; fall | ||
8 | back to the old ifdef behaviour if these are not set. | ||
9 | |||
10 | The default NaN value is specified by setting a uint8_t to a | ||
11 | pattern corresponding to the sign and upper fraction parts of | ||
12 | the NaN; the lower bits of the fraction are set from bit 0 of | ||
13 | the pattern. | ||
6 | 14 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20210723162146.5167-7-peter.maydell@linaro.org | 17 | Message-id: 20241202131347.498124-35-peter.maydell@linaro.org |
10 | --- | 18 | --- |
11 | hw/intc/armv7m_nvic.c | 31 ++++++++++++++++++++++++------- | 19 | include/fpu/softfloat-helpers.h | 11 +++++++ |
12 | 1 file changed, 24 insertions(+), 7 deletions(-) | 20 | include/fpu/softfloat-types.h | 10 ++++++ |
21 | fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++------------- | ||
22 | 3 files changed, 54 insertions(+), 22 deletions(-) | ||
13 | 23 | ||
14 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 24 | diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h |
15 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/intc/armv7m_nvic.c | 26 | --- a/include/fpu/softfloat-helpers.h |
17 | +++ b/hw/intc/armv7m_nvic.c | 27 | +++ b/include/fpu/softfloat-helpers.h |
18 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque) | 28 | @@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, |
19 | nvic_irq_update(s); | 29 | status->float_infzeronan_rule = rule; |
20 | } | 30 | } |
21 | 31 | ||
22 | +static bool vectpending_targets_secure(NVICState *s) | 32 | +static inline void set_float_default_nan_pattern(uint8_t dnan_pattern, |
33 | + float_status *status) | ||
23 | +{ | 34 | +{ |
24 | + /* Return true if s->vectpending targets Secure state */ | 35 | + status->default_nan_pattern = dnan_pattern; |
25 | + if (s->vectpending_is_s_banked) { | ||
26 | + return true; | ||
27 | + } | ||
28 | + return !exc_is_banked(s->vectpending) && | ||
29 | + exc_targets_secure(s, s->vectpending); | ||
30 | +} | 36 | +} |
31 | + | 37 | + |
32 | void armv7m_nvic_get_pending_irq_info(void *opaque, | 38 | static inline void set_flush_to_zero(bool val, float_status *status) |
33 | int *pirq, bool *ptargets_secure) | ||
34 | { | 39 | { |
35 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque, | 40 | status->flush_to_zero = val; |
36 | 41 | @@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status | |
37 | assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq); | 42 | return status->float_infzeronan_rule; |
38 | 43 | } | |
39 | - if (s->vectpending_is_s_banked) { | 44 | |
40 | - targets_secure = true; | 45 | +static inline uint8_t get_float_default_nan_pattern(float_status *status) |
46 | +{ | ||
47 | + return status->default_nan_pattern; | ||
48 | +} | ||
49 | + | ||
50 | static inline bool get_flush_to_zero(float_status *status) | ||
51 | { | ||
52 | return status->flush_to_zero; | ||
53 | diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/include/fpu/softfloat-types.h | ||
56 | +++ b/include/fpu/softfloat-types.h | ||
57 | @@ -XXX,XX +XXX,XX @@ typedef struct float_status { | ||
58 | /* should denormalised inputs go to zero and set the input_denormal flag? */ | ||
59 | bool flush_inputs_to_zero; | ||
60 | bool default_nan_mode; | ||
61 | + /* | ||
62 | + * The pattern to use for the default NaN. Here the high bit specifies | ||
63 | + * the default NaN's sign bit, and bits 6..0 specify the high bits of the | ||
64 | + * fractional part. The low bits of the fractional part are copies of bit 0. | ||
65 | + * The exponent of the default NaN is (as for any NaN) always all 1s. | ||
66 | + * Note that a value of 0 here is not a valid NaN. The target must set | ||
67 | + * this to the correct non-zero value, or we will assert when trying to | ||
68 | + * create a default NaN. | ||
69 | + */ | ||
70 | + uint8_t default_nan_pattern; | ||
71 | /* | ||
72 | * The flags below are not used on all specializations and may | ||
73 | * constant fold away (see snan_bit_is_one()/no_signalling_nans() in | ||
74 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
75 | index XXXXXXX..XXXXXXX 100644 | ||
76 | --- a/fpu/softfloat-specialize.c.inc | ||
77 | +++ b/fpu/softfloat-specialize.c.inc | ||
78 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
79 | { | ||
80 | bool sign = 0; | ||
81 | uint64_t frac; | ||
82 | + uint8_t dnan_pattern = status->default_nan_pattern; | ||
83 | |||
84 | + if (dnan_pattern == 0) { | ||
85 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
86 | - /* !snan_bit_is_one, set all bits */ | ||
87 | - frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; | ||
88 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ | ||
89 | + /* Sign bit clear, all frac bits set */ | ||
90 | + dnan_pattern = 0b01111111; | ||
91 | +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ | ||
92 | || defined(TARGET_MICROBLAZE) | ||
93 | - /* !snan_bit_is_one, set sign and msb */ | ||
94 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); | ||
95 | - sign = 1; | ||
96 | + /* Sign bit set, most significant frac bit set */ | ||
97 | + dnan_pattern = 0b11000000; | ||
98 | #elif defined(TARGET_HPPA) | ||
99 | - /* snan_bit_is_one, set msb-1. */ | ||
100 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); | ||
101 | + /* Sign bit clear, msb-1 frac bit set */ | ||
102 | + dnan_pattern = 0b00100000; | ||
103 | #elif defined(TARGET_HEXAGON) | ||
104 | - sign = 1; | ||
105 | - frac = ~0ULL; | ||
106 | + /* Sign bit set, all frac bits set. */ | ||
107 | + dnan_pattern = 0b11111111; | ||
108 | #else | ||
109 | - /* | ||
110 | - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
111 | - * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
112 | - * do not have floating-point. | ||
113 | - */ | ||
114 | - if (snan_bit_is_one(status)) { | ||
115 | - /* set all bits other than msb */ | ||
116 | - frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; | ||
41 | - } else { | 117 | - } else { |
42 | - targets_secure = !exc_is_banked(pending) && | 118 | - /* set msb */ |
43 | - exc_targets_secure(s, pending); | 119 | - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); |
44 | - } | 120 | - } |
45 | + targets_secure = vectpending_targets_secure(s); | 121 | + /* |
46 | 122 | + * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | |
47 | trace_nvic_get_pending_irq_info(pending, targets_secure); | 123 | + * S390, SH4, TriCore, and Xtensa. Our other supported targets |
48 | 124 | + * do not have floating-point. | |
49 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 125 | + */ |
50 | /* VECTACTIVE */ | 126 | + if (snan_bit_is_one(status)) { |
51 | val = cpu->env.v7m.exception; | 127 | + /* sign bit clear, set all frac bits other than msb */ |
52 | /* VECTPENDING */ | 128 | + dnan_pattern = 0b00111111; |
53 | - val |= (s->vectpending & 0x1ff) << 12; | 129 | + } else { |
54 | + if (s->vectpending) { | 130 | + /* sign bit clear, set frac msb */ |
55 | + /* | 131 | + dnan_pattern = 0b01000000; |
56 | + * From v8.1M VECTPENDING must read as 1 if accessed as | ||
57 | + * NonSecure and the highest priority pending and enabled | ||
58 | + * exception targets Secure. | ||
59 | + */ | ||
60 | + int vp = s->vectpending; | ||
61 | + if (!attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && | ||
62 | + vectpending_targets_secure(s)) { | ||
63 | + vp = 1; | ||
64 | + } | ||
65 | + val |= (vp & 0x1ff) << 12; | ||
66 | + } | 132 | + } |
67 | /* ISRPENDING - set if any external IRQ is pending */ | 133 | #endif |
68 | if (nvic_isrpending(s)) { | 134 | + } |
69 | val |= (1 << 22); | 135 | + assert(dnan_pattern != 0); |
136 | + | ||
137 | + sign = dnan_pattern >> 7; | ||
138 | + /* | ||
139 | + * Place default_nan_pattern [6:0] into bits [62:56], | ||
140 | + * and replecate bit [0] down into [55:0] | ||
141 | + */ | ||
142 | + frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern); | ||
143 | + frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1)); | ||
144 | |||
145 | *p = (FloatParts64) { | ||
146 | .cls = float_class_qnan, | ||
70 | -- | 147 | -- |
71 | 2.20.1 | 148 | 2.34.1 |
72 | |||
73 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for the tests/fp code. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-36-peter.maydell@linaro.org | ||
6 | --- | ||
7 | tests/fp/fp-bench.c | 1 + | ||
8 | tests/fp/fp-test-log2.c | 1 + | ||
9 | tests/fp/fp-test.c | 1 + | ||
10 | 3 files changed, 3 insertions(+) | ||
11 | |||
12 | diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/tests/fp/fp-bench.c | ||
15 | +++ b/tests/fp/fp-bench.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void run_bench(void) | ||
17 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); | ||
18 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); | ||
19 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); | ||
20 | + set_float_default_nan_pattern(0b01000000, &soft_status); | ||
21 | |||
22 | f = bench_funcs[operation][precision]; | ||
23 | g_assert(f); | ||
24 | diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/tests/fp/fp-test-log2.c | ||
27 | +++ b/tests/fp/fp-test-log2.c | ||
28 | @@ -XXX,XX +XXX,XX @@ int main(int ac, char **av) | ||
29 | int i; | ||
30 | |||
31 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
32 | + set_float_default_nan_pattern(0b01000000, &qsf); | ||
33 | set_float_rounding_mode(float_round_nearest_even, &qsf); | ||
34 | |||
35 | test.d = 0.0; | ||
36 | diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/tests/fp/fp-test.c | ||
39 | +++ b/tests/fp/fp-test.c | ||
40 | @@ -XXX,XX +XXX,XX @@ void run_test(void) | ||
41 | */ | ||
42 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); | ||
43 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); | ||
44 | + set_float_default_nan_pattern(0b01000000, &qsf); | ||
45 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); | ||
46 | |||
47 | genCases_setLevel(test_level); | ||
48 | -- | ||
49 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly, and remove the ifdef from | ||
2 | parts64_default_nan(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-37-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/microblaze/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 3 +-- | ||
10 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/microblaze/cpu.c | ||
15 | +++ b/target/microblaze/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | * this architecture. | ||
18 | */ | ||
19 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); | ||
20 | + /* Default NaN: sign bit set, most significant frac bit set */ | ||
21 | + set_float_default_nan_pattern(0b11000000, &env->fp_status); | ||
22 | |||
23 | #if defined(CONFIG_USER_ONLY) | ||
24 | /* start in user mode with interrupts enabled. */ | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
30 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
31 | /* Sign bit clear, all frac bits set */ | ||
32 | dnan_pattern = 0b01111111; | ||
33 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ | ||
34 | - || defined(TARGET_MICROBLAZE) | ||
35 | +#elif defined(TARGET_I386) || defined(TARGET_X86_64) | ||
36 | /* Sign bit set, most significant frac bit set */ | ||
37 | dnan_pattern = 0b11000000; | ||
38 | #elif defined(TARGET_HPPA) | ||
39 | -- | ||
40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly, and remove the ifdef from | ||
2 | parts64_default_nan(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-38-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/i386/tcg/fpu_helper.c | 4 ++++ | ||
9 | fpu/softfloat-specialize.c.inc | 3 --- | ||
10 | 2 files changed, 4 insertions(+), 3 deletions(-) | ||
11 | |||
12 | diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/i386/tcg/fpu_helper.c | ||
15 | +++ b/target/i386/tcg/fpu_helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env) | ||
17 | */ | ||
18 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); | ||
19 | set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); | ||
20 | + /* Default NaN: sign bit set, most significant frac bit set */ | ||
21 | + set_float_default_nan_pattern(0b11000000, &env->fp_status); | ||
22 | + set_float_default_nan_pattern(0b11000000, &env->mmx_status); | ||
23 | + set_float_default_nan_pattern(0b11000000, &env->sse_status); | ||
24 | } | ||
25 | |||
26 | static inline uint8_t save_exception_flags(CPUX86State *env) | ||
27 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/fpu/softfloat-specialize.c.inc | ||
30 | +++ b/fpu/softfloat-specialize.c.inc | ||
31 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
32 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
33 | /* Sign bit clear, all frac bits set */ | ||
34 | dnan_pattern = 0b01111111; | ||
35 | -#elif defined(TARGET_I386) || defined(TARGET_X86_64) | ||
36 | - /* Sign bit set, most significant frac bit set */ | ||
37 | - dnan_pattern = 0b11000000; | ||
38 | #elif defined(TARGET_HPPA) | ||
39 | /* Sign bit clear, msb-1 frac bit set */ | ||
40 | dnan_pattern = 0b00100000; | ||
41 | -- | ||
42 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly, and remove the ifdef from | ||
2 | parts64_default_nan(). | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-39-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/hppa/fpu_helper.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 3 --- | ||
10 | 2 files changed, 2 insertions(+), 3 deletions(-) | ||
11 | |||
12 | diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/hppa/fpu_helper.c | ||
15 | +++ b/target/hppa/fpu_helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env) | ||
17 | set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); | ||
18 | /* For inf * 0 + NaN, return the input NaN */ | ||
19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
20 | + /* Default NaN: sign bit clear, msb-1 frac bit set */ | ||
21 | + set_float_default_nan_pattern(0b00100000, &env->fp_status); | ||
22 | } | ||
23 | |||
24 | void cpu_hppa_loaded_fr0(CPUHPPAState *env) | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
30 | #if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
31 | /* Sign bit clear, all frac bits set */ | ||
32 | dnan_pattern = 0b01111111; | ||
33 | -#elif defined(TARGET_HPPA) | ||
34 | - /* Sign bit clear, msb-1 frac bit set */ | ||
35 | - dnan_pattern = 0b00100000; | ||
36 | #elif defined(TARGET_HEXAGON) | ||
37 | /* Sign bit set, all frac bits set. */ | ||
38 | dnan_pattern = 0b11111111; | ||
39 | -- | ||
40 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for the alpha target. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-40-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/alpha/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/alpha/cpu.c | ||
13 | +++ b/target/alpha/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj) | ||
15 | * operand in Fa. That is float_2nan_prop_ba. | ||
16 | */ | ||
17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); | ||
18 | + /* Default NaN: sign bit clear, msb frac bit set */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
20 | #if defined(CONFIG_USER_ONLY) | ||
21 | env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; | ||
22 | cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for the arm target. | ||
2 | This includes setting it for the old linux-user nwfpe emulation. | ||
3 | For nwfpe, our default doesn't match the real kernel, but we | ||
4 | avoid making a behaviour change in this commit. | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20241202131347.498124-41-peter.maydell@linaro.org | ||
9 | --- | ||
10 | linux-user/arm/nwfpe/fpa11.c | 5 +++++ | ||
11 | target/arm/cpu.c | 2 ++ | ||
12 | 2 files changed, 7 insertions(+) | ||
13 | |||
14 | diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/linux-user/arm/nwfpe/fpa11.c | ||
17 | +++ b/linux-user/arm/nwfpe/fpa11.c | ||
18 | @@ -XXX,XX +XXX,XX @@ void resetFPA11(void) | ||
19 | * this late date. | ||
20 | */ | ||
21 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status); | ||
22 | + /* | ||
23 | + * Use the same default NaN value as Arm VFP. This doesn't match | ||
24 | + * the Linux kernel's nwfpe emulation, which uses an all-1s value. | ||
25 | + */ | ||
26 | + set_float_default_nan_pattern(0b01000000, &fpa11->fp_status); | ||
27 | } | ||
28 | |||
29 | void SetRoundingMode(const unsigned int opcode) | ||
30 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/cpu.c | ||
33 | +++ b/target/arm/cpu.c | ||
34 | @@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, | ||
35 | * the pseudocode function the arguments are in the order c, a, b. | ||
36 | * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, | ||
37 | * and the input NaN if it is signalling | ||
38 | + * * Default NaN has sign bit clear, msb frac bit set | ||
39 | */ | ||
40 | static void arm_set_default_fp_behaviours(float_status *s) | ||
41 | { | ||
42 | @@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s) | ||
43 | set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); | ||
44 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); | ||
45 | set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); | ||
46 | + set_float_default_nan_pattern(0b01000000, s); | ||
47 | } | ||
48 | |||
49 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) | ||
50 | -- | ||
51 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for loongarch. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-42-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/loongarch/tcg/fpu_helper.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/loongarch/tcg/fpu_helper.c | ||
13 | +++ b/target/loongarch/tcg/fpu_helper.c | ||
14 | @@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env) | ||
15 | */ | ||
16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
17 | set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); | ||
18 | + /* Default NaN: sign bit clear, msb frac bit set */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
20 | } | ||
21 | |||
22 | int ieee_ex_to_loongarch(int xcpt) | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for m68k. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-43-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/m68k/cpu.c | 2 ++ | ||
8 | fpu/softfloat-specialize.c.inc | 2 +- | ||
9 | 2 files changed, 3 insertions(+), 1 deletion(-) | ||
10 | |||
11 | diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/m68k/cpu.c | ||
14 | +++ b/target/m68k/cpu.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) | ||
16 | * preceding paragraph for nonsignaling NaNs. | ||
17 | */ | ||
18 | set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); | ||
19 | + /* Default NaN: sign bit clear, all frac bits set */ | ||
20 | + set_float_default_nan_pattern(0b01111111, &env->fp_status); | ||
21 | |||
22 | nan = floatx80_default_nan(&env->fp_status); | ||
23 | for (i = 0; i < 8; i++) { | ||
24 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/fpu/softfloat-specialize.c.inc | ||
27 | +++ b/fpu/softfloat-specialize.c.inc | ||
28 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
29 | uint8_t dnan_pattern = status->default_nan_pattern; | ||
30 | |||
31 | if (dnan_pattern == 0) { | ||
32 | -#if defined(TARGET_SPARC) || defined(TARGET_M68K) | ||
33 | +#if defined(TARGET_SPARC) | ||
34 | /* Sign bit clear, all frac bits set */ | ||
35 | dnan_pattern = 0b01111111; | ||
36 | #elif defined(TARGET_HEXAGON) | ||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for MIPS. Note that this | ||
2 | is our only target which currently changes the default NaN | ||
3 | at runtime (which it was previously doing indirectly when it | ||
4 | changed the snan_bit_is_one setting). | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20241202131347.498124-44-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/mips/fpu_helper.h | 7 +++++++ | ||
11 | target/mips/msa.c | 3 +++ | ||
12 | 2 files changed, 10 insertions(+) | ||
13 | |||
14 | diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/mips/fpu_helper.h | ||
17 | +++ b/target/mips/fpu_helper.h | ||
18 | @@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) | ||
19 | set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); | ||
20 | nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; | ||
21 | set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); | ||
22 | + /* | ||
23 | + * With nan2008, the default NaN value has the sign bit clear and the | ||
24 | + * frac msb set; with the older mode, the sign bit is clear, and all | ||
25 | + * frac bits except the msb are set. | ||
26 | + */ | ||
27 | + set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111, | ||
28 | + &env->active_fpu.fp_status); | ||
29 | |||
30 | } | ||
31 | |||
32 | diff --git a/target/mips/msa.c b/target/mips/msa.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/mips/msa.c | ||
35 | +++ b/target/mips/msa.c | ||
36 | @@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env) | ||
37 | /* Inf * 0 + NaN returns the input NaN */ | ||
38 | set_float_infzeronan_rule(float_infzeronan_dnan_never, | ||
39 | &env->active_tc.msa_fp_status); | ||
40 | + /* Default NaN: sign bit clear, frac msb set */ | ||
41 | + set_float_default_nan_pattern(0b01000000, | ||
42 | + &env->active_tc.msa_fp_status); | ||
43 | } | ||
44 | -- | ||
45 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for openrisc. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-45-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/openrisc/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/openrisc/cpu.c | ||
13 | +++ b/target/openrisc/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type) | ||
15 | */ | ||
16 | set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); | ||
17 | |||
18 | + /* Default NaN: sign bit clear, frac msb set */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); | ||
20 | |||
21 | #ifndef CONFIG_USER_ONLY | ||
22 | cpu->env.picmr = 0x00000000; | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for ppc. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-46-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/ppc/cpu_init.c | 4 ++++ | ||
8 | 1 file changed, 4 insertions(+) | ||
9 | |||
10 | diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/ppc/cpu_init.c | ||
13 | +++ b/target/ppc/cpu_init.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) | ||
15 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); | ||
17 | |||
18 | + /* Default NaN: sign bit clear, set frac msb */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
20 | + set_float_default_nan_pattern(0b01000000, &env->vec_status); | ||
21 | + | ||
22 | for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { | ||
23 | ppc_spr_t *spr = &env->spr_cb[i]; | ||
24 | |||
25 | -- | ||
26 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for sh4. Note that sh4 | ||
2 | is one of the only three targets (the others being HPPA and | ||
3 | sometimes MIPS) that has snan_bit_is_one set. | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20241202131347.498124-47-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/sh4/cpu.c | 2 ++ | ||
10 | 1 file changed, 2 insertions(+) | ||
11 | |||
12 | diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/sh4/cpu.c | ||
15 | +++ b/target/sh4/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type) | ||
17 | set_flush_to_zero(1, &env->fp_status); | ||
18 | #endif | ||
19 | set_default_nan_mode(1, &env->fp_status); | ||
20 | + /* sign bit clear, set all frac bits other than msb */ | ||
21 | + set_float_default_nan_pattern(0b00111111, &env->fp_status); | ||
22 | } | ||
23 | |||
24 | static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) | ||
25 | -- | ||
26 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for rx. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-48-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/rx/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/rx/cpu.c b/target/rx/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/rx/cpu.c | ||
13 | +++ b/target/rx/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type) | ||
15 | * then prefer dest over source", which is float_2nan_prop_s_ab. | ||
16 | */ | ||
17 | set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); | ||
18 | + /* Default NaN value: sign bit clear, set frac msb */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); | ||
20 | } | ||
21 | |||
22 | static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for s390x. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20241202131347.498124-49-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/s390x/cpu.c | 2 ++ | ||
8 | 1 file changed, 2 insertions(+) | ||
9 | |||
10 | diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/target/s390x/cpu.c | ||
13 | +++ b/target/s390x/cpu.c | ||
14 | @@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) | ||
15 | set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); | ||
16 | set_float_infzeronan_rule(float_infzeronan_dnan_always, | ||
17 | &env->fpu_status); | ||
18 | + /* Default NaN value: sign bit clear, frac msb set */ | ||
19 | + set_float_default_nan_pattern(0b01000000, &env->fpu_status); | ||
20 | /* fall through */ | ||
21 | case RESET_TYPE_S390_CPU_NORMAL: | ||
22 | env->psw.mask &= ~PSW_MASK_RI; | ||
23 | -- | ||
24 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Set the default NaN pattern explicitly for SPARC, and remove | ||
2 | the ifdef from parts64_default_nan. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20241202131347.498124-50-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/sparc/cpu.c | 2 ++ | ||
9 | fpu/softfloat-specialize.c.inc | 5 +---- | ||
10 | 2 files changed, 3 insertions(+), 4 deletions(-) | ||
11 | |||
12 | diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/sparc/cpu.c | ||
15 | +++ b/target/sparc/cpu.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) | ||
17 | set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); | ||
18 | /* For inf * 0 + NaN, return the input NaN */ | ||
19 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); | ||
20 | + /* Default NaN value: sign bit clear, all frac bits set */ | ||
21 | + set_float_default_nan_pattern(0b01111111, &env->fp_status); | ||
22 | |||
23 | cpu_exec_realizefn(cs, &local_err); | ||
24 | if (local_err != NULL) { | ||
25 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/fpu/softfloat-specialize.c.inc | ||
28 | +++ b/fpu/softfloat-specialize.c.inc | ||
29 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
30 | uint8_t dnan_pattern = status->default_nan_pattern; | ||
31 | |||
32 | if (dnan_pattern == 0) { | ||
33 | -#if defined(TARGET_SPARC) | ||
34 | - /* Sign bit clear, all frac bits set */ | ||
35 | - dnan_pattern = 0b01111111; | ||
36 | -#elif defined(TARGET_HEXAGON) | ||
37 | +#if defined(TARGET_HEXAGON) | ||
38 | /* Sign bit set, all frac bits set. */ | ||
39 | dnan_pattern = 0b11111111; | ||
40 | #else | ||
41 | -- | ||
42 | 2.34.1 | diff view generated by jsdifflib |
1 | The ISCR.ISRPENDING bit is set when an external interrupt is pending. | 1 | Set the default NaN pattern explicitly for xtensa. |
---|---|---|---|
2 | This is true whether that external interrupt is enabled or not. | ||
3 | This means that we can't use 's->vectpending == 0' as a shortcut to | ||
4 | "ISRPENDING is zero", because s->vectpending indicates only the | ||
5 | highest priority pending enabled interrupt. | ||
6 | |||
7 | Remove the incorrect optimization so that if there is no pending | ||
8 | enabled interrupt we fall through to scanning through the whole | ||
9 | interrupt array. | ||
10 | 2 | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
13 | Message-id: 20210723162146.5167-5-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-51-peter.maydell@linaro.org |
14 | --- | 6 | --- |
15 | hw/intc/armv7m_nvic.c | 9 ++++----- | 7 | target/xtensa/cpu.c | 2 ++ |
16 | 1 file changed, 4 insertions(+), 5 deletions(-) | 8 | 1 file changed, 2 insertions(+) |
17 | 9 | ||
18 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 10 | diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c |
19 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/intc/armv7m_nvic.c | 12 | --- a/target/xtensa/cpu.c |
21 | +++ b/hw/intc/armv7m_nvic.c | 13 | +++ b/target/xtensa/cpu.c |
22 | @@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s) | 14 | @@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) |
23 | { | 15 | /* For inf * 0 + NaN, return the input NaN */ |
24 | int irq; | 16 | set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); |
25 | 17 | set_no_signaling_nans(!dfpu, &env->fp_status); | |
26 | - /* We can shortcut if the highest priority pending interrupt | 18 | + /* Default NaN value: sign bit clear, set frac msb */ |
27 | - * happens to be external or if there is nothing pending. | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
28 | + /* | 20 | xtensa_use_first_nan(env, !dfpu); |
29 | + * We can shortcut if the highest priority pending interrupt | 21 | } |
30 | + * happens to be external; if not we need to check the whole | 22 | |
31 | + * vectors[] array. | ||
32 | */ | ||
33 | if (s->vectpending > NVIC_FIRST_IRQ) { | ||
34 | return true; | ||
35 | } | ||
36 | - if (s->vectpending == 0) { | ||
37 | - return false; | ||
38 | - } | ||
39 | |||
40 | for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) { | ||
41 | if (s->vectors[irq].pending) { | ||
42 | -- | 23 | -- |
43 | 2.20.1 | 24 | 2.34.1 |
44 | |||
45 | diff view generated by jsdifflib |
1 | For M-profile, we weren't reporting alignment faults triggered by the | 1 | Set the default NaN pattern explicitly for hexagon. |
---|---|---|---|
2 | generic TCG code correctly to the guest. These get passed into | 2 | Remove the ifdef from parts64_default_nan(); the only |
3 | arm_v7m_cpu_do_interrupt() as an EXCP_DATA_ABORT with an A-profile | 3 | remaining unconverted targets all use the default case. |
4 | style exception.fsr value of 1. We didn't check for this, and so | ||
5 | they fell through into the default of "assume this is an MPU fault" | ||
6 | and were reported to the guest as a data access violation MPU fault. | ||
7 | |||
8 | Report these alignment faults as UsageFaults which set the UNALIGNED | ||
9 | bit in the UFSR. | ||
10 | 4 | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
13 | Message-id: 20210723162146.5167-4-peter.maydell@linaro.org | 7 | Message-id: 20241202131347.498124-52-peter.maydell@linaro.org |
14 | --- | 8 | --- |
15 | target/arm/m_helper.c | 8 ++++++++ | 9 | target/hexagon/cpu.c | 2 ++ |
16 | 1 file changed, 8 insertions(+) | 10 | fpu/softfloat-specialize.c.inc | 5 ----- |
11 | 2 files changed, 2 insertions(+), 5 deletions(-) | ||
17 | 12 | ||
18 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 13 | diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c |
19 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/m_helper.c | 15 | --- a/target/hexagon/cpu.c |
21 | +++ b/target/arm/m_helper.c | 16 | +++ b/target/hexagon/cpu.c |
22 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 17 | @@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) |
23 | env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK; | 18 | |
24 | break; | 19 | set_default_nan_mode(1, &env->fp_status); |
25 | case EXCP_UNALIGNED: | 20 | set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); |
26 | + /* Unaligned faults reported by M-profile aware code */ | 21 | + /* Default NaN value: sign bit set, all frac bits set */ |
27 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); | 22 | + set_float_default_nan_pattern(0b11111111, &env->fp_status); |
28 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK; | 23 | } |
29 | break; | 24 | |
30 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 25 | static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) |
31 | } | 26 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
32 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); | 27 | index XXXXXXX..XXXXXXX 100644 |
33 | break; | 28 | --- a/fpu/softfloat-specialize.c.inc |
34 | + case 0x1: /* Alignment fault reported by generic code */ | 29 | +++ b/fpu/softfloat-specialize.c.inc |
35 | + qemu_log_mask(CPU_LOG_INT, | 30 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) |
36 | + "...really UsageFault with UFSR.UNALIGNED\n"); | 31 | uint8_t dnan_pattern = status->default_nan_pattern; |
37 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK; | 32 | |
38 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, | 33 | if (dnan_pattern == 0) { |
39 | + env->v7m.secure); | 34 | -#if defined(TARGET_HEXAGON) |
40 | + break; | 35 | - /* Sign bit set, all frac bits set. */ |
41 | default: | 36 | - dnan_pattern = 0b11111111; |
42 | /* | 37 | -#else |
43 | * All other FSR values are either MPU faults or "can't happen | 38 | /* |
39 | * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, | ||
40 | * S390, SH4, TriCore, and Xtensa. Our other supported targets | ||
41 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) | ||
42 | /* sign bit clear, set frac msb */ | ||
43 | dnan_pattern = 0b01000000; | ||
44 | } | ||
45 | -#endif | ||
46 | } | ||
47 | assert(dnan_pattern != 0); | ||
48 | |||
44 | -- | 49 | -- |
45 | 2.20.1 | 50 | 2.34.1 |
46 | |||
47 | diff view generated by jsdifflib |
1 | The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of | 1 | Set the default NaN pattern explicitly for riscv. |
---|---|---|---|
2 | the register. We were incorrectly masking it to 8 bits, so it would | ||
3 | report the wrong value if the pending exception was greater than 256. | ||
4 | Fix the bug. | ||
5 | 2 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20210723162146.5167-6-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-53-peter.maydell@linaro.org |
9 | --- | 6 | --- |
10 | hw/intc/armv7m_nvic.c | 2 +- | 7 | target/riscv/cpu.c | 2 ++ |
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | 8 | 1 file changed, 2 insertions(+) |
12 | 9 | ||
13 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 10 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c |
14 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/intc/armv7m_nvic.c | 12 | --- a/target/riscv/cpu.c |
16 | +++ b/hw/intc/armv7m_nvic.c | 13 | +++ b/target/riscv/cpu.c |
17 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 14 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) |
18 | /* VECTACTIVE */ | 15 | cs->exception_index = RISCV_EXCP_NONE; |
19 | val = cpu->env.v7m.exception; | 16 | env->load_res = -1; |
20 | /* VECTPENDING */ | 17 | set_default_nan_mode(1, &env->fp_status); |
21 | - val |= (s->vectpending & 0xff) << 12; | 18 | + /* Default NaN value: sign bit clear, frac msb set */ |
22 | + val |= (s->vectpending & 0x1ff) << 12; | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
23 | /* ISRPENDING - set if any external IRQ is pending */ | 20 | env->vill = true; |
24 | if (nvic_isrpending(s)) { | 21 | |
25 | val |= (1 << 22); | 22 | #ifndef CONFIG_USER_ONLY |
26 | -- | 23 | -- |
27 | 2.20.1 | 24 | 2.34.1 |
28 | |||
29 | diff view generated by jsdifflib |
1 | In do_v7m_exception_exit(), we perform various checks as part of | 1 | Set the default NaN pattern explicitly for tricore. |
---|---|---|---|
2 | performing the exception return. If one of these checks fails, the | ||
3 | architecture requires that we take an appropriate exception on the | ||
4 | existing stackframe. We implement this by calling | ||
5 | v7m_exception_taken() to set up to take the new exception, and then | ||
6 | immediately returning from do_v7m_exception_exit() without proceeding | ||
7 | any further with the unstack-and-exception-return process. | ||
8 | |||
9 | In a couple of checks that are new in v8.1M, we forgot the "return" | ||
10 | statement, with the effect that if bad code in the guest tripped over | ||
11 | these checks we would set up to take a UsageFault exception but then | ||
12 | blunder on trying to also unstack and return from the original | ||
13 | exception, with the probable result that the guest would crash. | ||
14 | |||
15 | Add the missing return statements. | ||
16 | 2 | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
19 | Message-id: 20210723162146.5167-3-peter.maydell@linaro.org | 5 | Message-id: 20241202131347.498124-54-peter.maydell@linaro.org |
20 | --- | 6 | --- |
21 | target/arm/m_helper.c | 2 ++ | 7 | target/tricore/helper.c | 2 ++ |
22 | 1 file changed, 2 insertions(+) | 8 | 1 file changed, 2 insertions(+) |
23 | 9 | ||
24 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 10 | diff --git a/target/tricore/helper.c b/target/tricore/helper.c |
25 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/m_helper.c | 12 | --- a/target/tricore/helper.c |
27 | +++ b/target/arm/m_helper.c | 13 | +++ b/target/tricore/helper.c |
28 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | 14 | @@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env) |
29 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " | 15 | set_flush_to_zero(1, &env->fp_status); |
30 | "stackframe: NSACR prevents clearing FPU registers\n"); | 16 | set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); |
31 | v7m_exception_taken(cpu, excret, true, false); | 17 | set_default_nan_mode(1, &env->fp_status); |
32 | + return; | 18 | + /* Default NaN pattern: sign bit clear, frac msb set */ |
33 | } else if (!cpacr_pass) { | 19 | + set_float_default_nan_pattern(0b01000000, &env->fp_status); |
34 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, | 20 | } |
35 | exc_secure); | 21 | |
36 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | 22 | uint32_t psw_read(CPUTriCoreState *env) |
37 | qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " | ||
38 | "stackframe: CPACR prevents clearing FPU registers\n"); | ||
39 | v7m_exception_taken(cpu, excret, true, false); | ||
40 | + return; | ||
41 | } | ||
42 | } | ||
43 | /* Clear s0..s15, FPSCR and VPR */ | ||
44 | -- | 23 | -- |
45 | 2.20.1 | 24 | 2.34.1 |
46 | |||
47 | diff view generated by jsdifflib |
1 | For M-profile, unlike A-profile, the low 2 bits of SP are defined to be | 1 | Now that all our targets have bene converted to explicitly specify |
---|---|---|---|
2 | RES0H, which is to say that they must be hardwired to zero so that | 2 | their pattern for the default NaN value we can remove the remaining |
3 | guest attempts to write non-zero values to them are ignored. | 3 | fallback code in parts64_default_nan(). |
4 | |||
5 | Implement this behaviour by masking out the low bits: | ||
6 | * for writes to r13 by the gdbstub | ||
7 | * for writes to any of the various flavours of SP via MSR | ||
8 | * for writes to r13 via store_reg() in generated code | ||
9 | |||
10 | Note that all the direct uses of cpu_R[] in translate.c are in places | ||
11 | where the register is definitely not r13 (usually because that has | ||
12 | been checked for as an UNDEFINED or UNPREDICTABLE case and handled as | ||
13 | UNDEF). | ||
14 | |||
15 | All the other writes to regs[13] in C code are either: | ||
16 | * A-profile only code | ||
17 | * writes of values we can guarantee to be aligned, such as | ||
18 | - writes of previous-SP-value plus or minus a 4-aligned constant | ||
19 | - writes of the value in an SP limit register (which we already | ||
20 | enforce to be aligned) | ||
21 | 4 | ||
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
23 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
24 | Message-id: 20210723162146.5167-2-peter.maydell@linaro.org | 7 | Message-id: 20241202131347.498124-55-peter.maydell@linaro.org |
25 | --- | 8 | --- |
26 | target/arm/gdbstub.c | 4 ++++ | 9 | fpu/softfloat-specialize.c.inc | 14 -------------- |
27 | target/arm/m_helper.c | 14 ++++++++------ | 10 | 1 file changed, 14 deletions(-) |
28 | target/arm/translate.c | 3 +++ | ||
29 | 3 files changed, 15 insertions(+), 6 deletions(-) | ||
30 | 11 | ||
31 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | 12 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
32 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/target/arm/gdbstub.c | 14 | --- a/fpu/softfloat-specialize.c.inc |
34 | +++ b/target/arm/gdbstub.c | 15 | +++ b/fpu/softfloat-specialize.c.inc |
35 | @@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) | 16 | @@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) |
36 | 17 | uint64_t frac; | |
37 | if (n < 16) { | 18 | uint8_t dnan_pattern = status->default_nan_pattern; |
38 | /* Core integer register. */ | 19 | |
39 | + if (n == 13 && arm_feature(env, ARM_FEATURE_M)) { | 20 | - if (dnan_pattern == 0) { |
40 | + /* M profile SP low bits are always 0 */ | 21 | - /* |
41 | + tmp &= ~3; | 22 | - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, |
42 | + } | 23 | - * S390, SH4, TriCore, and Xtensa. Our other supported targets |
43 | env->regs[n] = tmp; | 24 | - * do not have floating-point. |
44 | return 4; | 25 | - */ |
45 | } | 26 | - if (snan_bit_is_one(status)) { |
46 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 27 | - /* sign bit clear, set all frac bits other than msb */ |
47 | index XXXXXXX..XXXXXXX 100644 | 28 | - dnan_pattern = 0b00111111; |
48 | --- a/target/arm/m_helper.c | 29 | - } else { |
49 | +++ b/target/arm/m_helper.c | 30 | - /* sign bit clear, set frac msb */ |
50 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | 31 | - dnan_pattern = 0b01000000; |
51 | if (!env->v7m.secure) { | 32 | - } |
52 | return; | 33 | - } |
53 | } | 34 | assert(dnan_pattern != 0); |
54 | - env->v7m.other_ss_msp = val; | 35 | |
55 | + env->v7m.other_ss_msp = val & ~3; | 36 | sign = dnan_pattern >> 7; |
56 | return; | ||
57 | case 0x89: /* PSP_NS */ | ||
58 | if (!env->v7m.secure) { | ||
59 | return; | ||
60 | } | ||
61 | - env->v7m.other_ss_psp = val; | ||
62 | + env->v7m.other_ss_psp = val & ~3; | ||
63 | return; | ||
64 | case 0x8a: /* MSPLIM_NS */ | ||
65 | if (!env->v7m.secure) { | ||
66 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
67 | |||
68 | limit = is_psp ? env->v7m.psplim[false] : env->v7m.msplim[false]; | ||
69 | |||
70 | + val &= ~0x3; | ||
71 | + | ||
72 | if (val < limit) { | ||
73 | raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC()); | ||
74 | } | ||
75 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
76 | break; | ||
77 | case 8: /* MSP */ | ||
78 | if (v7m_using_psp(env)) { | ||
79 | - env->v7m.other_sp = val; | ||
80 | + env->v7m.other_sp = val & ~3; | ||
81 | } else { | ||
82 | - env->regs[13] = val; | ||
83 | + env->regs[13] = val & ~3; | ||
84 | } | ||
85 | break; | ||
86 | case 9: /* PSP */ | ||
87 | if (v7m_using_psp(env)) { | ||
88 | - env->regs[13] = val; | ||
89 | + env->regs[13] = val & ~3; | ||
90 | } else { | ||
91 | - env->v7m.other_sp = val; | ||
92 | + env->v7m.other_sp = val & ~3; | ||
93 | } | ||
94 | break; | ||
95 | case 10: /* MSPLIM */ | ||
96 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
97 | index XXXXXXX..XXXXXXX 100644 | ||
98 | --- a/target/arm/translate.c | ||
99 | +++ b/target/arm/translate.c | ||
100 | @@ -XXX,XX +XXX,XX @@ void store_reg(DisasContext *s, int reg, TCGv_i32 var) | ||
101 | */ | ||
102 | tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3); | ||
103 | s->base.is_jmp = DISAS_JUMP; | ||
104 | + } else if (reg == 13 && arm_dc_feature(s, ARM_FEATURE_M)) { | ||
105 | + /* For M-profile SP bits [1:0] are always zero */ | ||
106 | + tcg_gen_andi_i32(var, var, ~3); | ||
107 | } | ||
108 | tcg_gen_mov_i32(cpu_R[reg], var); | ||
109 | tcg_temp_free_i32(var); | ||
110 | -- | 37 | -- |
111 | 2.20.1 | 38 | 2.34.1 |
112 | |||
113 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Currently, our only caller is sve_zcr_len_for_el, which has | 3 | Inline pickNaNMulAdd into its only caller. This makes |
4 | already masked the length extracted from ZCR_ELx, so the | 4 | one assert redundant with the immediately preceding IF. |
5 | masking done here is a nop. But we will shortly have uses | ||
6 | from other locations, where the length will be unmasked. | ||
7 | |||
8 | Saturate the length to ARM_MAX_VQ instead of truncating to | ||
9 | the low 4 bits. | ||
10 | 5 | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
13 | Message-id: 20210723203344.968563-2-richard.henderson@linaro.org | 8 | Message-id: 20241203203949.483774-3-richard.henderson@linaro.org |
9 | [PMM: keep comment from old code in new location] | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 11 | --- |
16 | target/arm/helper.c | 4 +++- | 12 | fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++- |
17 | 1 file changed, 3 insertions(+), 1 deletion(-) | 13 | fpu/softfloat-specialize.c.inc | 54 ---------------------------------- |
14 | 2 files changed, 40 insertions(+), 55 deletions(-) | ||
18 | 15 | ||
19 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 16 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
20 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/helper.c | 18 | --- a/fpu/softfloat-parts.c.inc |
22 | +++ b/target/arm/helper.c | 19 | +++ b/fpu/softfloat-parts.c.inc |
23 | @@ -XXX,XX +XXX,XX @@ static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) | 20 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
24 | { | 21 | } |
25 | uint32_t end_len; | 22 | |
26 | 23 | if (s->default_nan_mode) { | |
27 | - end_len = start_len &= 0xf; | 24 | + /* |
28 | + start_len = MIN(start_len, ARM_MAX_VQ - 1); | 25 | + * We guarantee not to require the target to tell us how to |
29 | + end_len = start_len; | 26 | + * pick a NaN if we're always returning the default NaN. |
27 | + * But if we're not in default-NaN mode then the target must | ||
28 | + * specify. | ||
29 | + */ | ||
30 | which = 3; | ||
31 | + } else if (infzero) { | ||
32 | + /* | ||
33 | + * Inf * 0 + NaN -- some implementations return the | ||
34 | + * default NaN here, and some return the input NaN. | ||
35 | + */ | ||
36 | + switch (s->float_infzeronan_rule) { | ||
37 | + case float_infzeronan_dnan_never: | ||
38 | + which = 2; | ||
39 | + break; | ||
40 | + case float_infzeronan_dnan_always: | ||
41 | + which = 3; | ||
42 | + break; | ||
43 | + case float_infzeronan_dnan_if_qnan: | ||
44 | + which = is_qnan(c->cls) ? 3 : 2; | ||
45 | + break; | ||
46 | + default: | ||
47 | + g_assert_not_reached(); | ||
48 | + } | ||
49 | } else { | ||
50 | - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); | ||
51 | + FloatClass cls[3] = { a->cls, b->cls, c->cls }; | ||
52 | + Float3NaNPropRule rule = s->float_3nan_prop_rule; | ||
30 | + | 53 | + |
31 | if (!test_bit(start_len, cpu->sve_vq_map)) { | 54 | + assert(rule != float_3nan_prop_none); |
32 | end_len = find_last_bit(cpu->sve_vq_map, start_len); | 55 | + if (have_snan && (rule & R_3NAN_SNAN_MASK)) { |
33 | assert(end_len < start_len); | 56 | + /* We have at least one SNaN input and should prefer it */ |
57 | + do { | ||
58 | + which = rule & R_3NAN_1ST_MASK; | ||
59 | + rule >>= R_3NAN_1ST_LENGTH; | ||
60 | + } while (!is_snan(cls[which])); | ||
61 | + } else { | ||
62 | + do { | ||
63 | + which = rule & R_3NAN_1ST_MASK; | ||
64 | + rule >>= R_3NAN_1ST_LENGTH; | ||
65 | + } while (!is_nan(cls[which])); | ||
66 | + } | ||
67 | } | ||
68 | |||
69 | if (which == 3) { | ||
70 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/fpu/softfloat-specialize.c.inc | ||
73 | +++ b/fpu/softfloat-specialize.c.inc | ||
74 | @@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
75 | } | ||
76 | } | ||
77 | |||
78 | -/*---------------------------------------------------------------------------- | ||
79 | -| Select which NaN to propagate for a three-input operation. | ||
80 | -| For the moment we assume that no CPU needs the 'larger significand' | ||
81 | -| information. | ||
82 | -| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN | ||
83 | -*----------------------------------------------------------------------------*/ | ||
84 | -static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, | ||
85 | - bool infzero, bool have_snan, float_status *status) | ||
86 | -{ | ||
87 | - FloatClass cls[3] = { a_cls, b_cls, c_cls }; | ||
88 | - Float3NaNPropRule rule = status->float_3nan_prop_rule; | ||
89 | - int which; | ||
90 | - | ||
91 | - /* | ||
92 | - * We guarantee not to require the target to tell us how to | ||
93 | - * pick a NaN if we're always returning the default NaN. | ||
94 | - * But if we're not in default-NaN mode then the target must | ||
95 | - * specify. | ||
96 | - */ | ||
97 | - assert(!status->default_nan_mode); | ||
98 | - | ||
99 | - if (infzero) { | ||
100 | - /* | ||
101 | - * Inf * 0 + NaN -- some implementations return the default NaN here, | ||
102 | - * and some return the input NaN. | ||
103 | - */ | ||
104 | - switch (status->float_infzeronan_rule) { | ||
105 | - case float_infzeronan_dnan_never: | ||
106 | - return 2; | ||
107 | - case float_infzeronan_dnan_always: | ||
108 | - return 3; | ||
109 | - case float_infzeronan_dnan_if_qnan: | ||
110 | - return is_qnan(c_cls) ? 3 : 2; | ||
111 | - default: | ||
112 | - g_assert_not_reached(); | ||
113 | - } | ||
114 | - } | ||
115 | - | ||
116 | - assert(rule != float_3nan_prop_none); | ||
117 | - if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
118 | - /* We have at least one SNaN input and should prefer it */ | ||
119 | - do { | ||
120 | - which = rule & R_3NAN_1ST_MASK; | ||
121 | - rule >>= R_3NAN_1ST_LENGTH; | ||
122 | - } while (!is_snan(cls[which])); | ||
123 | - } else { | ||
124 | - do { | ||
125 | - which = rule & R_3NAN_1ST_MASK; | ||
126 | - rule >>= R_3NAN_1ST_LENGTH; | ||
127 | - } while (!is_nan(cls[which])); | ||
128 | - } | ||
129 | - return which; | ||
130 | -} | ||
131 | - | ||
132 | /*---------------------------------------------------------------------------- | ||
133 | | Returns 1 if the double-precision floating-point value `a' is a quiet | ||
134 | | NaN; otherwise returns 0. | ||
34 | -- | 135 | -- |
35 | 2.20.1 | 136 | 2.34.1 |
36 | 137 | ||
37 | 138 | diff view generated by jsdifflib |
1 | The documentation of the -machine memory-backend has some minor | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | formatting errors: | ||
3 | * Misindentation of the initial line meant that the whole option | ||
4 | section is incorrectly indented in the HTML output compared to | ||
5 | the other -machine options | ||
6 | * The examples weren't indented, which meant that they were formatted | ||
7 | as plain run-on text including outputting the "::" as text. | ||
8 | * The a) b) list has no rst-format markup so it is rendered as | ||
9 | a single run-on paragraph | ||
10 | 2 | ||
11 | Fix the formatting. | 3 | Remove "3" as a special case for which and simply |
4 | branch to return the desired value. | ||
12 | 5 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Message-id: 20241203203949.483774-4-richard.henderson@linaro.org | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
15 | Message-id: 20210719105257.3599-1-peter.maydell@linaro.org | ||
16 | --- | 10 | --- |
17 | qemu-options.hx | 30 +++++++++++++++++------------- | 11 | fpu/softfloat-parts.c.inc | 20 ++++++++++---------- |
18 | 1 file changed, 17 insertions(+), 13 deletions(-) | 12 | 1 file changed, 10 insertions(+), 10 deletions(-) |
19 | 13 | ||
20 | diff --git a/qemu-options.hx b/qemu-options.hx | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
21 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/qemu-options.hx | 16 | --- a/fpu/softfloat-parts.c.inc |
23 | +++ b/qemu-options.hx | 17 | +++ b/fpu/softfloat-parts.c.inc |
24 | @@ -XXX,XX +XXX,XX @@ SRST | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
25 | Enables or disables ACPI Heterogeneous Memory Attribute Table | 19 | * But if we're not in default-NaN mode then the target must |
26 | (HMAT) support. The default is off. | 20 | * specify. |
27 | 21 | */ | |
28 | - ``memory-backend='id'`` | 22 | - which = 3; |
29 | + ``memory-backend='id'`` | 23 | + goto default_nan; |
30 | An alternative to legacy ``-mem-path`` and ``mem-prealloc`` options. | 24 | } else if (infzero) { |
31 | Allows to use a memory backend as main RAM. | 25 | /* |
32 | 26 | * Inf * 0 + NaN -- some implementations return the | |
33 | For example: | 27 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
34 | :: | 28 | */ |
35 | - -object memory-backend-file,id=pc.ram,size=512M,mem-path=/hugetlbfs,prealloc=on,share=on | 29 | switch (s->float_infzeronan_rule) { |
36 | - -machine memory-backend=pc.ram | 30 | case float_infzeronan_dnan_never: |
37 | - -m 512M | 31 | - which = 2; |
32 | break; | ||
33 | case float_infzeronan_dnan_always: | ||
34 | - which = 3; | ||
35 | - break; | ||
36 | + goto default_nan; | ||
37 | case float_infzeronan_dnan_if_qnan: | ||
38 | - which = is_qnan(c->cls) ? 3 : 2; | ||
39 | + if (is_qnan(c->cls)) { | ||
40 | + goto default_nan; | ||
41 | + } | ||
42 | break; | ||
43 | default: | ||
44 | g_assert_not_reached(); | ||
45 | } | ||
46 | + which = 2; | ||
47 | } else { | ||
48 | FloatClass cls[3] = { a->cls, b->cls, c->cls }; | ||
49 | Float3NaNPropRule rule = s->float_3nan_prop_rule; | ||
50 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
51 | } | ||
52 | } | ||
53 | |||
54 | - if (which == 3) { | ||
55 | - parts_default_nan(a, s); | ||
56 | - return a; | ||
57 | - } | ||
58 | - | ||
59 | switch (which) { | ||
60 | case 0: | ||
61 | break; | ||
62 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
63 | parts_silence_nan(a, s); | ||
64 | } | ||
65 | return a; | ||
38 | + | 66 | + |
39 | + -object memory-backend-file,id=pc.ram,size=512M,mem-path=/hugetlbfs,prealloc=on,share=on | 67 | + default_nan: |
40 | + -machine memory-backend=pc.ram | 68 | + parts_default_nan(a, s); |
41 | + -m 512M | 69 | + return a; |
42 | 70 | } | |
43 | Migration compatibility note: | 71 | |
44 | - a) as backend id one shall use value of 'default-ram-id', advertised by | 72 | /* |
45 | - machine type (available via ``query-machines`` QMP command), if migration | ||
46 | - to/from old QEMU (<5.0) is expected. | ||
47 | - b) for machine types 4.0 and older, user shall | ||
48 | - use ``x-use-canonical-path-for-ramblock-id=off`` backend option | ||
49 | - if migration to/from old QEMU (<5.0) is expected. | ||
50 | + | ||
51 | + * as backend id one shall use value of 'default-ram-id', advertised by | ||
52 | + machine type (available via ``query-machines`` QMP command), if migration | ||
53 | + to/from old QEMU (<5.0) is expected. | ||
54 | + * for machine types 4.0 and older, user shall | ||
55 | + use ``x-use-canonical-path-for-ramblock-id=off`` backend option | ||
56 | + if migration to/from old QEMU (<5.0) is expected. | ||
57 | + | ||
58 | For example: | ||
59 | :: | ||
60 | - -object memory-backend-ram,id=pc.ram,size=512M,x-use-canonical-path-for-ramblock-id=off | ||
61 | - -machine memory-backend=pc.ram | ||
62 | - -m 512M | ||
63 | + | ||
64 | + -object memory-backend-ram,id=pc.ram,size=512M,x-use-canonical-path-for-ramblock-id=off | ||
65 | + -machine memory-backend=pc.ram | ||
66 | + -m 512M | ||
67 | ERST | ||
68 | |||
69 | HXCOMM Deprecated by -machine | ||
70 | -- | 73 | -- |
71 | 2.20.1 | 74 | 2.34.1 |
72 | 75 | ||
73 | 76 | diff view generated by jsdifflib |
1 | From: Joel Stanley <joel@jms.id.au> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The macro used to calculate the maximum memory size of the MMIO region | 3 | Assign the pointer return value to 'a' directly, |
4 | had a mistake, causing all GPIO models to create a mapping of 0x9D8. | 4 | rather than going through an intermediary index. |
5 | The intent was to have it be 0x9D8 - 0x800. | ||
6 | 5 | ||
7 | This extra size doesn't matter on ast2400 and ast2500, which have a 4KB | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | region set aside for the GPIO controller. | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | 8 | Message-id: 20241203203949.483774-5-richard.henderson@linaro.org | |
10 | On the ast2600 the 3.3V and 1.8V GPIO controllers are 2KB apart, so the | ||
11 | regions would overlap. Worse was the 1.8V controller would map over the | ||
12 | top of the following peripheral, which happens to be the RTC. | ||
13 | |||
14 | The mmio region used by each device is a maximum of 2KB, so avoid the | ||
15 | calculations and hard code this as the maximum. | ||
16 | |||
17 | Fixes: 36d737ee82b2 ("hw/gpio: Add in AST2600 specific implementation") | ||
18 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
19 | Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com> | ||
20 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
21 | Message-id: 20210713065854.134634-2-joel@jms.id.au | ||
22 | [PMM: fix autocorrect error in commit message] | ||
23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
24 | --- | 10 | --- |
25 | hw/gpio/aspeed_gpio.c | 3 +-- | 11 | fpu/softfloat-parts.c.inc | 32 ++++++++++---------------------- |
26 | 1 file changed, 1 insertion(+), 2 deletions(-) | 12 | 1 file changed, 10 insertions(+), 22 deletions(-) |
27 | 13 | ||
28 | diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
29 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/hw/gpio/aspeed_gpio.c | 16 | --- a/fpu/softfloat-parts.c.inc |
31 | +++ b/hw/gpio/aspeed_gpio.c | 17 | +++ b/fpu/softfloat-parts.c.inc |
32 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
33 | #define GPIO_1_8V_MEM_SIZE 0x9D8 | 19 | FloatPartsN *c, float_status *s, |
34 | #define GPIO_1_8V_REG_ARRAY_SIZE ((GPIO_1_8V_MEM_SIZE - \ | 20 | int ab_mask, int abc_mask) |
35 | GPIO_1_8V_REG_OFFSET) >> 2) | ||
36 | -#define GPIO_MAX_MEM_SIZE MAX(GPIO_3_6V_MEM_SIZE, GPIO_1_8V_MEM_SIZE) | ||
37 | |||
38 | static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio) | ||
39 | { | 21 | { |
40 | @@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_realize(DeviceState *dev, Error **errp) | 22 | - int which; |
23 | bool infzero = (ab_mask == float_cmask_infzero); | ||
24 | bool have_snan = (abc_mask & float_cmask_snan); | ||
25 | + FloatPartsN *ret; | ||
26 | |||
27 | if (unlikely(have_snan)) { | ||
28 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
29 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
30 | default: | ||
31 | g_assert_not_reached(); | ||
32 | } | ||
33 | - which = 2; | ||
34 | + ret = c; | ||
35 | } else { | ||
36 | - FloatClass cls[3] = { a->cls, b->cls, c->cls }; | ||
37 | + FloatPartsN *val[3] = { a, b, c }; | ||
38 | Float3NaNPropRule rule = s->float_3nan_prop_rule; | ||
39 | |||
40 | assert(rule != float_3nan_prop_none); | ||
41 | if (have_snan && (rule & R_3NAN_SNAN_MASK)) { | ||
42 | /* We have at least one SNaN input and should prefer it */ | ||
43 | do { | ||
44 | - which = rule & R_3NAN_1ST_MASK; | ||
45 | + ret = val[rule & R_3NAN_1ST_MASK]; | ||
46 | rule >>= R_3NAN_1ST_LENGTH; | ||
47 | - } while (!is_snan(cls[which])); | ||
48 | + } while (!is_snan(ret->cls)); | ||
49 | } else { | ||
50 | do { | ||
51 | - which = rule & R_3NAN_1ST_MASK; | ||
52 | + ret = val[rule & R_3NAN_1ST_MASK]; | ||
53 | rule >>= R_3NAN_1ST_LENGTH; | ||
54 | - } while (!is_nan(cls[which])); | ||
55 | + } while (!is_nan(ret->cls)); | ||
56 | } | ||
41 | } | 57 | } |
42 | 58 | ||
43 | memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, | 59 | - switch (which) { |
44 | - TYPE_ASPEED_GPIO, GPIO_MAX_MEM_SIZE); | 60 | - case 0: |
45 | + TYPE_ASPEED_GPIO, 0x800); | 61 | - break; |
46 | 62 | - case 1: | |
47 | sysbus_init_mmio(sbd, &s->iomem); | 63 | - a = b; |
48 | } | 64 | - break; |
65 | - case 2: | ||
66 | - a = c; | ||
67 | - break; | ||
68 | - default: | ||
69 | - g_assert_not_reached(); | ||
70 | + if (is_snan(ret->cls)) { | ||
71 | + parts_silence_nan(ret, s); | ||
72 | } | ||
73 | - if (is_snan(a->cls)) { | ||
74 | - parts_silence_nan(a, s); | ||
75 | - } | ||
76 | - return a; | ||
77 | + return ret; | ||
78 | |||
79 | default_nan: | ||
80 | parts_default_nan(a, s); | ||
49 | -- | 81 | -- |
50 | 2.20.1 | 82 | 2.34.1 |
51 | 83 | ||
52 | 84 | diff view generated by jsdifflib |
1 | From: Joe Komlodi <joe.komlodi@xilinx.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The bit to see if a CD is valid is the last bit of the first word of the CD. | 3 | While all indices into val[] should be in [0-2], the mask |
4 | applied is two bits. To help static analysis see there is | ||
5 | no possibility of read beyond the end of the array, pad the | ||
6 | array to 4 entries, with the final being (implicitly) NULL. | ||
4 | 7 | ||
5 | Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 1626728232-134665-2-git-send-email-joe.komlodi@xilinx.com | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Message-id: 20241203203949.483774-6-richard.henderson@linaro.org |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 12 | --- |
10 | hw/arm/smmuv3-internal.h | 2 +- | 13 | fpu/softfloat-parts.c.inc | 2 +- |
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | 15 | ||
13 | diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h | 16 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
14 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/arm/smmuv3-internal.h | 18 | --- a/fpu/softfloat-parts.c.inc |
16 | +++ b/hw/arm/smmuv3-internal.h | 19 | +++ b/fpu/softfloat-parts.c.inc |
17 | @@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste) | 20 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, |
18 | 21 | } | |
19 | /* CD fields */ | 22 | ret = c; |
20 | 23 | } else { | |
21 | -#define CD_VALID(x) extract32((x)->word[0], 30, 1) | 24 | - FloatPartsN *val[3] = { a, b, c }; |
22 | +#define CD_VALID(x) extract32((x)->word[0], 31, 1) | 25 | + FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c }; |
23 | #define CD_ASID(x) extract32((x)->word[1], 16, 16) | 26 | Float3NaNPropRule rule = s->float_3nan_prop_rule; |
24 | #define CD_TTB(x, sel) \ | 27 | |
25 | ({ \ | 28 | assert(rule != float_3nan_prop_none); |
26 | -- | 29 | -- |
27 | 2.20.1 | 30 | 2.34.1 |
28 | 31 | ||
29 | 32 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Mirror the behavour of /proc/sys/abi/sve_default_vector_length | 3 | This function is part of the public interface and |
4 | under the real linux kernel. We have no way of passing along | 4 | is not "specialized" to any target in any way. |
5 | a real default across exec like the kernel can, but this is a | ||
6 | decent way of adjusting the startup vector length of a process. | ||
7 | 5 | ||
8 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/482 | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Message-id: 20210723203344.968563-4-richard.henderson@linaro.org | 8 | Message-id: 20241203203949.483774-7-richard.henderson@linaro.org |
12 | [PMM: tweaked docs formatting, document -1 special-case, | ||
13 | added fixup patch from RTH mentioning QEMU's maximum veclen.] | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 10 | --- |
16 | docs/system/arm/cpu-features.rst | 15 ++++++++ | 11 | fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++ |
17 | target/arm/cpu.h | 5 +++ | 12 | fpu/softfloat-specialize.c.inc | 52 ---------------------------------- |
18 | target/arm/cpu.c | 14 ++++++-- | 13 | 2 files changed, 52 insertions(+), 52 deletions(-) |
19 | target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++ | ||
20 | 4 files changed, 92 insertions(+), 2 deletions(-) | ||
21 | 14 | ||
22 | diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst | 15 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c |
23 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/docs/system/arm/cpu-features.rst | 17 | --- a/fpu/softfloat.c |
25 | +++ b/docs/system/arm/cpu-features.rst | 18 | +++ b/fpu/softfloat.c |
26 | @@ -XXX,XX +XXX,XX @@ verbose command lines. However, the recommended way to select vector | 19 | @@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, |
27 | lengths is to explicitly enable each desired length. Therefore only | 20 | *zExpPtr = 1 - shiftCount; |
28 | example's (1), (4), and (6) exhibit recommended uses of the properties. | 21 | } |
29 | 22 | ||
30 | +SVE User-mode Default Vector Length Property | 23 | +/*---------------------------------------------------------------------------- |
31 | +-------------------------------------------- | 24 | +| Takes two extended double-precision floating-point values `a' and `b', one |
25 | +| of which is a NaN, and returns the appropriate NaN result. If either `a' or | ||
26 | +| `b' is a signaling NaN, the invalid exception is raised. | ||
27 | +*----------------------------------------------------------------------------*/ | ||
32 | + | 28 | + |
33 | +For qemu-aarch64, the cpu property ``sve-default-vector-length=N`` is | 29 | +floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) |
34 | +defined to mirror the Linux kernel parameter file | 30 | +{ |
35 | +``/proc/sys/abi/sve_default_vector_length``. The default length, ``N``, | 31 | + bool aIsLargerSignificand; |
36 | +is in units of bytes and must be between 16 and 8192. | 32 | + FloatClass a_cls, b_cls; |
37 | +If not specified, the default vector length is 64. | ||
38 | + | 33 | + |
39 | +If the default length is larger than the maximum vector length enabled, | 34 | + /* This is not complete, but is good enough for pickNaN. */ |
40 | +the actual vector length will be reduced. Note that the maximum vector | 35 | + a_cls = (!floatx80_is_any_nan(a) |
41 | +length supported by QEMU is 256. | 36 | + ? float_class_normal |
37 | + : floatx80_is_signaling_nan(a, status) | ||
38 | + ? float_class_snan | ||
39 | + : float_class_qnan); | ||
40 | + b_cls = (!floatx80_is_any_nan(b) | ||
41 | + ? float_class_normal | ||
42 | + : floatx80_is_signaling_nan(b, status) | ||
43 | + ? float_class_snan | ||
44 | + : float_class_qnan); | ||
42 | + | 45 | + |
43 | +If this property is set to ``-1`` then the default vector length | 46 | + if (is_snan(a_cls) || is_snan(b_cls)) { |
44 | +is set to the maximum possible length. | 47 | + float_raise(float_flag_invalid, status); |
45 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/target/arm/cpu.h | ||
48 | +++ b/target/arm/cpu.h | ||
49 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | ||
50 | /* Used to set the maximum vector length the cpu will support. */ | ||
51 | uint32_t sve_max_vq; | ||
52 | |||
53 | +#ifdef CONFIG_USER_ONLY | ||
54 | + /* Used to set the default vector length at process start. */ | ||
55 | + uint32_t sve_default_vq; | ||
56 | +#endif | ||
57 | + | ||
58 | /* | ||
59 | * In sve_vq_map each set bit is a supported vector length of | ||
60 | * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector | ||
61 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/target/arm/cpu.c | ||
64 | +++ b/target/arm/cpu.c | ||
65 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) | ||
66 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); | ||
67 | /* with reasonable vector length */ | ||
68 | if (cpu_isar_feature(aa64_sve, cpu)) { | ||
69 | - env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); | ||
70 | + env->vfp.zcr_el[1] = | ||
71 | + aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); | ||
72 | } | ||
73 | /* | ||
74 | * Enable TBI0 but not TBI1. | ||
75 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj) | ||
76 | QLIST_INIT(&cpu->pre_el_change_hooks); | ||
77 | QLIST_INIT(&cpu->el_change_hooks); | ||
78 | |||
79 | -#ifndef CONFIG_USER_ONLY | ||
80 | +#ifdef CONFIG_USER_ONLY | ||
81 | +# ifdef TARGET_AARCH64 | ||
82 | + /* | ||
83 | + * The linux kernel defaults to 512-bit vectors, when sve is supported. | ||
84 | + * See documentation for /proc/sys/abi/sve_default_vector_length, and | ||
85 | + * our corresponding sve-default-vector-length cpu property. | ||
86 | + */ | ||
87 | + cpu->sve_default_vq = 4; | ||
88 | +# endif | ||
89 | +#else | ||
90 | /* Our inbound IRQ and FIQ lines */ | ||
91 | if (kvm_enabled()) { | ||
92 | /* VIRQ and VFIQ are unused with KVM but we add them to maintain | ||
93 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
94 | index XXXXXXX..XXXXXXX 100644 | ||
95 | --- a/target/arm/cpu64.c | ||
96 | +++ b/target/arm/cpu64.c | ||
97 | @@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) | ||
98 | cpu->isar.id_aa64pfr0 = t; | ||
99 | } | ||
100 | |||
101 | +#ifdef CONFIG_USER_ONLY | ||
102 | +/* Mirror linux /proc/sys/abi/sve_default_vector_length. */ | ||
103 | +static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v, | ||
104 | + const char *name, void *opaque, | ||
105 | + Error **errp) | ||
106 | +{ | ||
107 | + ARMCPU *cpu = ARM_CPU(obj); | ||
108 | + int32_t default_len, default_vq, remainder; | ||
109 | + | ||
110 | + if (!visit_type_int32(v, name, &default_len, errp)) { | ||
111 | + return; | ||
112 | + } | 48 | + } |
113 | + | 49 | + |
114 | + /* Undocumented, but the kernel allows -1 to indicate "maximum". */ | 50 | + if (status->default_nan_mode) { |
115 | + if (default_len == -1) { | 51 | + return floatx80_default_nan(status); |
116 | + cpu->sve_default_vq = ARM_MAX_VQ; | ||
117 | + return; | ||
118 | + } | 52 | + } |
119 | + | 53 | + |
120 | + default_vq = default_len / 16; | 54 | + if (a.low < b.low) { |
121 | + remainder = default_len % 16; | 55 | + aIsLargerSignificand = 0; |
122 | + | 56 | + } else if (b.low < a.low) { |
123 | + /* | 57 | + aIsLargerSignificand = 1; |
124 | + * Note that the 512 max comes from include/uapi/asm/sve_context.h | 58 | + } else { |
125 | + * and is the maximum architectural width of ZCR_ELx.LEN. | 59 | + aIsLargerSignificand = (a.high < b.high) ? 1 : 0; |
126 | + */ | ||
127 | + if (remainder || default_vq < 1 || default_vq > 512) { | ||
128 | + error_setg(errp, "cannot set sve-default-vector-length"); | ||
129 | + if (remainder) { | ||
130 | + error_append_hint(errp, "Vector length not a multiple of 16\n"); | ||
131 | + } else if (default_vq < 1) { | ||
132 | + error_append_hint(errp, "Vector length smaller than 16\n"); | ||
133 | + } else { | ||
134 | + error_append_hint(errp, "Vector length larger than %d\n", | ||
135 | + 512 * 16); | ||
136 | + } | ||
137 | + return; | ||
138 | + } | 60 | + } |
139 | + | 61 | + |
140 | + cpu->sve_default_vq = default_vq; | 62 | + if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { |
63 | + if (is_snan(b_cls)) { | ||
64 | + return floatx80_silence_nan(b, status); | ||
65 | + } | ||
66 | + return b; | ||
67 | + } else { | ||
68 | + if (is_snan(a_cls)) { | ||
69 | + return floatx80_silence_nan(a, status); | ||
70 | + } | ||
71 | + return a; | ||
72 | + } | ||
141 | +} | 73 | +} |
142 | + | 74 | + |
143 | +static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v, | 75 | /*---------------------------------------------------------------------------- |
144 | + const char *name, void *opaque, | 76 | | Takes an abstract floating-point value having sign `zSign', exponent `zExp', |
145 | + Error **errp) | 77 | | and extended significand formed by the concatenation of `zSig0' and `zSig1', |
146 | +{ | 78 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc |
147 | + ARMCPU *cpu = ARM_CPU(obj); | 79 | index XXXXXXX..XXXXXXX 100644 |
148 | + int32_t value = cpu->sve_default_vq * 16; | 80 | --- a/fpu/softfloat-specialize.c.inc |
149 | + | 81 | +++ b/fpu/softfloat-specialize.c.inc |
150 | + visit_type_int32(v, name, &value, errp); | 82 | @@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) |
151 | +} | 83 | return a; |
152 | +#endif | ||
153 | + | ||
154 | void aarch64_add_sve_properties(Object *obj) | ||
155 | { | ||
156 | uint32_t vq; | ||
157 | @@ -XXX,XX +XXX,XX @@ void aarch64_add_sve_properties(Object *obj) | ||
158 | object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, | ||
159 | cpu_arm_set_sve_vq, NULL, NULL); | ||
160 | } | ||
161 | + | ||
162 | +#ifdef CONFIG_USER_ONLY | ||
163 | + /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ | ||
164 | + object_property_add(obj, "sve-default-vector-length", "int32", | ||
165 | + cpu_arm_get_sve_default_vec_len, | ||
166 | + cpu_arm_set_sve_default_vec_len, NULL, NULL); | ||
167 | +#endif | ||
168 | } | 84 | } |
169 | 85 | ||
170 | void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) | 86 | -/*---------------------------------------------------------------------------- |
87 | -| Takes two extended double-precision floating-point values `a' and `b', one | ||
88 | -| of which is a NaN, and returns the appropriate NaN result. If either `a' or | ||
89 | -| `b' is a signaling NaN, the invalid exception is raised. | ||
90 | -*----------------------------------------------------------------------------*/ | ||
91 | - | ||
92 | -floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) | ||
93 | -{ | ||
94 | - bool aIsLargerSignificand; | ||
95 | - FloatClass a_cls, b_cls; | ||
96 | - | ||
97 | - /* This is not complete, but is good enough for pickNaN. */ | ||
98 | - a_cls = (!floatx80_is_any_nan(a) | ||
99 | - ? float_class_normal | ||
100 | - : floatx80_is_signaling_nan(a, status) | ||
101 | - ? float_class_snan | ||
102 | - : float_class_qnan); | ||
103 | - b_cls = (!floatx80_is_any_nan(b) | ||
104 | - ? float_class_normal | ||
105 | - : floatx80_is_signaling_nan(b, status) | ||
106 | - ? float_class_snan | ||
107 | - : float_class_qnan); | ||
108 | - | ||
109 | - if (is_snan(a_cls) || is_snan(b_cls)) { | ||
110 | - float_raise(float_flag_invalid, status); | ||
111 | - } | ||
112 | - | ||
113 | - if (status->default_nan_mode) { | ||
114 | - return floatx80_default_nan(status); | ||
115 | - } | ||
116 | - | ||
117 | - if (a.low < b.low) { | ||
118 | - aIsLargerSignificand = 0; | ||
119 | - } else if (b.low < a.low) { | ||
120 | - aIsLargerSignificand = 1; | ||
121 | - } else { | ||
122 | - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; | ||
123 | - } | ||
124 | - | ||
125 | - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { | ||
126 | - if (is_snan(b_cls)) { | ||
127 | - return floatx80_silence_nan(b, status); | ||
128 | - } | ||
129 | - return b; | ||
130 | - } else { | ||
131 | - if (is_snan(a_cls)) { | ||
132 | - return floatx80_silence_nan(a, status); | ||
133 | - } | ||
134 | - return a; | ||
135 | - } | ||
136 | -} | ||
137 | - | ||
138 | /*---------------------------------------------------------------------------- | ||
139 | | Returns 1 if the quadruple-precision floating-point value `a' is a quiet | ||
140 | | NaN; otherwise returns 0. | ||
171 | -- | 141 | -- |
172 | 2.20.1 | 142 | 2.34.1 |
173 | |||
174 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Unpacking and repacking the parts may be slightly more work | ||
4 | than we did before, but we get to reuse more code. For a | ||
5 | code path handling exceptional values, this is an improvement. | ||
6 | |||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20241203203949.483774-8-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | fpu/softfloat.c | 43 +++++-------------------------------------- | ||
13 | 1 file changed, 5 insertions(+), 38 deletions(-) | ||
14 | |||
15 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/fpu/softfloat.c | ||
18 | +++ b/fpu/softfloat.c | ||
19 | @@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr, | ||
20 | |||
21 | floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) | ||
22 | { | ||
23 | - bool aIsLargerSignificand; | ||
24 | - FloatClass a_cls, b_cls; | ||
25 | + FloatParts128 pa, pb, *pr; | ||
26 | |||
27 | - /* This is not complete, but is good enough for pickNaN. */ | ||
28 | - a_cls = (!floatx80_is_any_nan(a) | ||
29 | - ? float_class_normal | ||
30 | - : floatx80_is_signaling_nan(a, status) | ||
31 | - ? float_class_snan | ||
32 | - : float_class_qnan); | ||
33 | - b_cls = (!floatx80_is_any_nan(b) | ||
34 | - ? float_class_normal | ||
35 | - : floatx80_is_signaling_nan(b, status) | ||
36 | - ? float_class_snan | ||
37 | - : float_class_qnan); | ||
38 | - | ||
39 | - if (is_snan(a_cls) || is_snan(b_cls)) { | ||
40 | - float_raise(float_flag_invalid, status); | ||
41 | - } | ||
42 | - | ||
43 | - if (status->default_nan_mode) { | ||
44 | + if (!floatx80_unpack_canonical(&pa, a, status) || | ||
45 | + !floatx80_unpack_canonical(&pb, b, status)) { | ||
46 | return floatx80_default_nan(status); | ||
47 | } | ||
48 | |||
49 | - if (a.low < b.low) { | ||
50 | - aIsLargerSignificand = 0; | ||
51 | - } else if (b.low < a.low) { | ||
52 | - aIsLargerSignificand = 1; | ||
53 | - } else { | ||
54 | - aIsLargerSignificand = (a.high < b.high) ? 1 : 0; | ||
55 | - } | ||
56 | - | ||
57 | - if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) { | ||
58 | - if (is_snan(b_cls)) { | ||
59 | - return floatx80_silence_nan(b, status); | ||
60 | - } | ||
61 | - return b; | ||
62 | - } else { | ||
63 | - if (is_snan(a_cls)) { | ||
64 | - return floatx80_silence_nan(a, status); | ||
65 | - } | ||
66 | - return a; | ||
67 | - } | ||
68 | + pr = parts_pick_nan(&pa, &pb, status); | ||
69 | + return floatx80_round_pack_canonical(pr, status); | ||
70 | } | ||
71 | |||
72 | /*---------------------------------------------------------------------------- | ||
73 | -- | ||
74 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Richard Henderson <richard.henderson@linaro.org> | |
2 | |||
3 | Inline pickNaN into its only caller. This makes one assert | ||
4 | redundant with the immediately preceding IF. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Message-id: 20241203203949.483774-9-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++---- | ||
12 | fpu/softfloat-specialize.c.inc | 96 ---------------------------------- | ||
13 | 2 files changed, 73 insertions(+), 105 deletions(-) | ||
14 | |||
15 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/fpu/softfloat-parts.c.inc | ||
18 | +++ b/fpu/softfloat-parts.c.inc | ||
19 | @@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) | ||
20 | static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | ||
21 | float_status *s) | ||
22 | { | ||
23 | + int cmp, which; | ||
24 | + | ||
25 | if (is_snan(a->cls) || is_snan(b->cls)) { | ||
26 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
27 | } | ||
28 | |||
29 | if (s->default_nan_mode) { | ||
30 | parts_default_nan(a, s); | ||
31 | - } else { | ||
32 | - int cmp = frac_cmp(a, b); | ||
33 | - if (cmp == 0) { | ||
34 | - cmp = a->sign < b->sign; | ||
35 | - } | ||
36 | + return a; | ||
37 | + } | ||
38 | |||
39 | - if (pickNaN(a->cls, b->cls, cmp > 0, s)) { | ||
40 | - a = b; | ||
41 | - } | ||
42 | + cmp = frac_cmp(a, b); | ||
43 | + if (cmp == 0) { | ||
44 | + cmp = a->sign < b->sign; | ||
45 | + } | ||
46 | + | ||
47 | + switch (s->float_2nan_prop_rule) { | ||
48 | + case float_2nan_prop_s_ab: | ||
49 | if (is_snan(a->cls)) { | ||
50 | - parts_silence_nan(a, s); | ||
51 | + which = 0; | ||
52 | + } else if (is_snan(b->cls)) { | ||
53 | + which = 1; | ||
54 | + } else if (is_qnan(a->cls)) { | ||
55 | + which = 0; | ||
56 | + } else { | ||
57 | + which = 1; | ||
58 | } | ||
59 | + break; | ||
60 | + case float_2nan_prop_s_ba: | ||
61 | + if (is_snan(b->cls)) { | ||
62 | + which = 1; | ||
63 | + } else if (is_snan(a->cls)) { | ||
64 | + which = 0; | ||
65 | + } else if (is_qnan(b->cls)) { | ||
66 | + which = 1; | ||
67 | + } else { | ||
68 | + which = 0; | ||
69 | + } | ||
70 | + break; | ||
71 | + case float_2nan_prop_ab: | ||
72 | + which = is_nan(a->cls) ? 0 : 1; | ||
73 | + break; | ||
74 | + case float_2nan_prop_ba: | ||
75 | + which = is_nan(b->cls) ? 1 : 0; | ||
76 | + break; | ||
77 | + case float_2nan_prop_x87: | ||
78 | + /* | ||
79 | + * This implements x87 NaN propagation rules: | ||
80 | + * SNaN + QNaN => return the QNaN | ||
81 | + * two SNaNs => return the one with the larger significand, silenced | ||
82 | + * two QNaNs => return the one with the larger significand | ||
83 | + * SNaN and a non-NaN => return the SNaN, silenced | ||
84 | + * QNaN and a non-NaN => return the QNaN | ||
85 | + * | ||
86 | + * If we get down to comparing significands and they are the same, | ||
87 | + * return the NaN with the positive sign bit (if any). | ||
88 | + */ | ||
89 | + if (is_snan(a->cls)) { | ||
90 | + if (is_snan(b->cls)) { | ||
91 | + which = cmp > 0 ? 0 : 1; | ||
92 | + } else { | ||
93 | + which = is_qnan(b->cls) ? 1 : 0; | ||
94 | + } | ||
95 | + } else if (is_qnan(a->cls)) { | ||
96 | + if (is_snan(b->cls) || !is_qnan(b->cls)) { | ||
97 | + which = 0; | ||
98 | + } else { | ||
99 | + which = cmp > 0 ? 0 : 1; | ||
100 | + } | ||
101 | + } else { | ||
102 | + which = 1; | ||
103 | + } | ||
104 | + break; | ||
105 | + default: | ||
106 | + g_assert_not_reached(); | ||
107 | + } | ||
108 | + | ||
109 | + if (which) { | ||
110 | + a = b; | ||
111 | + } | ||
112 | + if (is_snan(a->cls)) { | ||
113 | + parts_silence_nan(a, s); | ||
114 | } | ||
115 | return a; | ||
116 | } | ||
117 | diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc | ||
118 | index XXXXXXX..XXXXXXX 100644 | ||
119 | --- a/fpu/softfloat-specialize.c.inc | ||
120 | +++ b/fpu/softfloat-specialize.c.inc | ||
121 | @@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status) | ||
122 | } | ||
123 | } | ||
124 | |||
125 | -/*---------------------------------------------------------------------------- | ||
126 | -| Select which NaN to propagate for a two-input operation. | ||
127 | -| IEEE754 doesn't specify all the details of this, so the | ||
128 | -| algorithm is target-specific. | ||
129 | -| The routine is passed various bits of information about the | ||
130 | -| two NaNs and should return 0 to select NaN a and 1 for NaN b. | ||
131 | -| Note that signalling NaNs are always squashed to quiet NaNs | ||
132 | -| by the caller, by calling floatXX_silence_nan() before | ||
133 | -| returning them. | ||
134 | -| | ||
135 | -| aIsLargerSignificand is only valid if both a and b are NaNs | ||
136 | -| of some kind, and is true if a has the larger significand, | ||
137 | -| or if both a and b have the same significand but a is | ||
138 | -| positive but b is negative. It is only needed for the x87 | ||
139 | -| tie-break rule. | ||
140 | -*----------------------------------------------------------------------------*/ | ||
141 | - | ||
142 | -static int pickNaN(FloatClass a_cls, FloatClass b_cls, | ||
143 | - bool aIsLargerSignificand, float_status *status) | ||
144 | -{ | ||
145 | - /* | ||
146 | - * We guarantee not to require the target to tell us how to | ||
147 | - * pick a NaN if we're always returning the default NaN. | ||
148 | - * But if we're not in default-NaN mode then the target must | ||
149 | - * specify via set_float_2nan_prop_rule(). | ||
150 | - */ | ||
151 | - assert(!status->default_nan_mode); | ||
152 | - | ||
153 | - switch (status->float_2nan_prop_rule) { | ||
154 | - case float_2nan_prop_s_ab: | ||
155 | - if (is_snan(a_cls)) { | ||
156 | - return 0; | ||
157 | - } else if (is_snan(b_cls)) { | ||
158 | - return 1; | ||
159 | - } else if (is_qnan(a_cls)) { | ||
160 | - return 0; | ||
161 | - } else { | ||
162 | - return 1; | ||
163 | - } | ||
164 | - break; | ||
165 | - case float_2nan_prop_s_ba: | ||
166 | - if (is_snan(b_cls)) { | ||
167 | - return 1; | ||
168 | - } else if (is_snan(a_cls)) { | ||
169 | - return 0; | ||
170 | - } else if (is_qnan(b_cls)) { | ||
171 | - return 1; | ||
172 | - } else { | ||
173 | - return 0; | ||
174 | - } | ||
175 | - break; | ||
176 | - case float_2nan_prop_ab: | ||
177 | - if (is_nan(a_cls)) { | ||
178 | - return 0; | ||
179 | - } else { | ||
180 | - return 1; | ||
181 | - } | ||
182 | - break; | ||
183 | - case float_2nan_prop_ba: | ||
184 | - if (is_nan(b_cls)) { | ||
185 | - return 1; | ||
186 | - } else { | ||
187 | - return 0; | ||
188 | - } | ||
189 | - break; | ||
190 | - case float_2nan_prop_x87: | ||
191 | - /* | ||
192 | - * This implements x87 NaN propagation rules: | ||
193 | - * SNaN + QNaN => return the QNaN | ||
194 | - * two SNaNs => return the one with the larger significand, silenced | ||
195 | - * two QNaNs => return the one with the larger significand | ||
196 | - * SNaN and a non-NaN => return the SNaN, silenced | ||
197 | - * QNaN and a non-NaN => return the QNaN | ||
198 | - * | ||
199 | - * If we get down to comparing significands and they are the same, | ||
200 | - * return the NaN with the positive sign bit (if any). | ||
201 | - */ | ||
202 | - if (is_snan(a_cls)) { | ||
203 | - if (is_snan(b_cls)) { | ||
204 | - return aIsLargerSignificand ? 0 : 1; | ||
205 | - } | ||
206 | - return is_qnan(b_cls) ? 1 : 0; | ||
207 | - } else if (is_qnan(a_cls)) { | ||
208 | - if (is_snan(b_cls) || !is_qnan(b_cls)) { | ||
209 | - return 0; | ||
210 | - } else { | ||
211 | - return aIsLargerSignificand ? 0 : 1; | ||
212 | - } | ||
213 | - } else { | ||
214 | - return 1; | ||
215 | - } | ||
216 | - default: | ||
217 | - g_assert_not_reached(); | ||
218 | - } | ||
219 | -} | ||
220 | - | ||
221 | /*---------------------------------------------------------------------------- | ||
222 | | Returns 1 if the double-precision floating-point value `a' is a quiet | ||
223 | | NaN; otherwise returns 0. | ||
224 | -- | ||
225 | 2.34.1 | ||
226 | |||
227 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Remember if there was an SNaN, and use that to simplify | ||
4 | float_2nan_prop_s_{ab,ba} to only the snan component. | ||
5 | Then, fall through to the corresponding | ||
6 | float_2nan_prop_{ab,ba} case to handle any remaining | ||
7 | nans, which must be quiet. | ||
8 | |||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Message-id: 20241203203949.483774-10-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | fpu/softfloat-parts.c.inc | 32 ++++++++++++-------------------- | ||
15 | 1 file changed, 12 insertions(+), 20 deletions(-) | ||
16 | |||
17 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/fpu/softfloat-parts.c.inc | ||
20 | +++ b/fpu/softfloat-parts.c.inc | ||
21 | @@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) | ||
22 | static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | ||
23 | float_status *s) | ||
24 | { | ||
25 | + bool have_snan = false; | ||
26 | int cmp, which; | ||
27 | |||
28 | if (is_snan(a->cls) || is_snan(b->cls)) { | ||
29 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
30 | + have_snan = true; | ||
31 | } | ||
32 | |||
33 | if (s->default_nan_mode) { | ||
34 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | ||
35 | |||
36 | switch (s->float_2nan_prop_rule) { | ||
37 | case float_2nan_prop_s_ab: | ||
38 | - if (is_snan(a->cls)) { | ||
39 | - which = 0; | ||
40 | - } else if (is_snan(b->cls)) { | ||
41 | - which = 1; | ||
42 | - } else if (is_qnan(a->cls)) { | ||
43 | - which = 0; | ||
44 | - } else { | ||
45 | - which = 1; | ||
46 | + if (have_snan) { | ||
47 | + which = is_snan(a->cls) ? 0 : 1; | ||
48 | + break; | ||
49 | } | ||
50 | - break; | ||
51 | - case float_2nan_prop_s_ba: | ||
52 | - if (is_snan(b->cls)) { | ||
53 | - which = 1; | ||
54 | - } else if (is_snan(a->cls)) { | ||
55 | - which = 0; | ||
56 | - } else if (is_qnan(b->cls)) { | ||
57 | - which = 1; | ||
58 | - } else { | ||
59 | - which = 0; | ||
60 | - } | ||
61 | - break; | ||
62 | + /* fall through */ | ||
63 | case float_2nan_prop_ab: | ||
64 | which = is_nan(a->cls) ? 0 : 1; | ||
65 | break; | ||
66 | + case float_2nan_prop_s_ba: | ||
67 | + if (have_snan) { | ||
68 | + which = is_snan(b->cls) ? 1 : 0; | ||
69 | + break; | ||
70 | + } | ||
71 | + /* fall through */ | ||
72 | case float_2nan_prop_ba: | ||
73 | which = is_nan(b->cls) ? 1 : 0; | ||
74 | break; | ||
75 | -- | ||
76 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Move the fractional comparison to the end of the | ||
4 | float_2nan_prop_x87 case. This is not required for | ||
5 | any other 2nan propagation rule. Reorganize the | ||
6 | x87 case itself to break out of the switch when the | ||
7 | fractional comparison is not required. | ||
8 | |||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Message-id: 20241203203949.483774-11-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | fpu/softfloat-parts.c.inc | 19 +++++++++---------- | ||
15 | 1 file changed, 9 insertions(+), 10 deletions(-) | ||
16 | |||
17 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/fpu/softfloat-parts.c.inc | ||
20 | +++ b/fpu/softfloat-parts.c.inc | ||
21 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | ||
22 | return a; | ||
23 | } | ||
24 | |||
25 | - cmp = frac_cmp(a, b); | ||
26 | - if (cmp == 0) { | ||
27 | - cmp = a->sign < b->sign; | ||
28 | - } | ||
29 | - | ||
30 | switch (s->float_2nan_prop_rule) { | ||
31 | case float_2nan_prop_s_ab: | ||
32 | if (have_snan) { | ||
33 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | ||
34 | * return the NaN with the positive sign bit (if any). | ||
35 | */ | ||
36 | if (is_snan(a->cls)) { | ||
37 | - if (is_snan(b->cls)) { | ||
38 | - which = cmp > 0 ? 0 : 1; | ||
39 | - } else { | ||
40 | + if (!is_snan(b->cls)) { | ||
41 | which = is_qnan(b->cls) ? 1 : 0; | ||
42 | + break; | ||
43 | } | ||
44 | } else if (is_qnan(a->cls)) { | ||
45 | if (is_snan(b->cls) || !is_qnan(b->cls)) { | ||
46 | which = 0; | ||
47 | - } else { | ||
48 | - which = cmp > 0 ? 0 : 1; | ||
49 | + break; | ||
50 | } | ||
51 | } else { | ||
52 | which = 1; | ||
53 | + break; | ||
54 | } | ||
55 | + cmp = frac_cmp(a, b); | ||
56 | + if (cmp == 0) { | ||
57 | + cmp = a->sign < b->sign; | ||
58 | + } | ||
59 | + which = cmp > 0 ? 0 : 1; | ||
60 | break; | ||
61 | default: | ||
62 | g_assert_not_reached(); | ||
63 | -- | ||
64 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 3 | Replace the "index" selecting between A and B with a result variable |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | of the proper type. This improves clarity within the function. |
5 | Message-id: 20210726150953.1218690-1-f4bug@amsat.org | 5 | |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Message-id: 20241203203949.483774-12-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 10 | --- |
8 | hw/arm/nseries.c | 2 +- | 11 | fpu/softfloat-parts.c.inc | 28 +++++++++++++--------------- |
9 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | 1 file changed, 13 insertions(+), 15 deletions(-) |
10 | 13 | ||
11 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | 14 | diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc |
12 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/arm/nseries.c | 16 | --- a/fpu/softfloat-parts.c.inc |
14 | +++ b/hw/arm/nseries.c | 17 | +++ b/fpu/softfloat-parts.c.inc |
15 | @@ -XXX,XX +XXX,XX @@ static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len) | 18 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, |
19 | float_status *s) | ||
20 | { | ||
21 | bool have_snan = false; | ||
22 | - int cmp, which; | ||
23 | + FloatPartsN *ret; | ||
24 | + int cmp; | ||
25 | |||
26 | if (is_snan(a->cls) || is_snan(b->cls)) { | ||
27 | float_raise(float_flag_invalid | float_flag_invalid_snan, s); | ||
28 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | ||
29 | switch (s->float_2nan_prop_rule) { | ||
30 | case float_2nan_prop_s_ab: | ||
31 | if (have_snan) { | ||
32 | - which = is_snan(a->cls) ? 0 : 1; | ||
33 | + ret = is_snan(a->cls) ? a : b; | ||
34 | break; | ||
35 | } | ||
36 | /* fall through */ | ||
37 | case float_2nan_prop_ab: | ||
38 | - which = is_nan(a->cls) ? 0 : 1; | ||
39 | + ret = is_nan(a->cls) ? a : b; | ||
40 | break; | ||
41 | case float_2nan_prop_s_ba: | ||
42 | if (have_snan) { | ||
43 | - which = is_snan(b->cls) ? 1 : 0; | ||
44 | + ret = is_snan(b->cls) ? b : a; | ||
45 | break; | ||
46 | } | ||
47 | /* fall through */ | ||
48 | case float_2nan_prop_ba: | ||
49 | - which = is_nan(b->cls) ? 1 : 0; | ||
50 | + ret = is_nan(b->cls) ? b : a; | ||
51 | break; | ||
52 | case float_2nan_prop_x87: | ||
53 | /* | ||
54 | @@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, | ||
55 | */ | ||
56 | if (is_snan(a->cls)) { | ||
57 | if (!is_snan(b->cls)) { | ||
58 | - which = is_qnan(b->cls) ? 1 : 0; | ||
59 | + ret = is_qnan(b->cls) ? b : a; | ||
60 | break; | ||
61 | } | ||
62 | } else if (is_qnan(a->cls)) { | ||
63 | if (is_snan(b->cls) || !is_qnan(b->cls)) { | ||
64 | - which = 0; | ||
65 | + ret = a; | ||
66 | break; | ||
67 | } | ||
68 | } else { | ||
69 | - which = 1; | ||
70 | + ret = b; | ||
71 | break; | ||
72 | } | ||
73 | cmp = frac_cmp(a, b); | ||
74 | if (cmp == 0) { | ||
75 | cmp = a->sign < b->sign; | ||
76 | } | ||
77 | - which = cmp > 0 ? 0 : 1; | ||
78 | + ret = cmp > 0 ? a : b; | ||
79 | break; | ||
16 | default: | 80 | default: |
17 | bad_cmd: | 81 | g_assert_not_reached(); |
18 | qemu_log_mask(LOG_GUEST_ERROR, | ||
19 | - "%s: unknown command %02x\n", __func__, s->cmd); | ||
20 | + "%s: unknown command 0x%02x\n", __func__, s->cmd); | ||
21 | break; | ||
22 | } | 82 | } |
23 | 83 | ||
84 | - if (which) { | ||
85 | - a = b; | ||
86 | + if (is_snan(ret->cls)) { | ||
87 | + parts_silence_nan(ret, s); | ||
88 | } | ||
89 | - if (is_snan(a->cls)) { | ||
90 | - parts_silence_nan(a, s); | ||
91 | - } | ||
92 | - return a; | ||
93 | + return ret; | ||
94 | } | ||
95 | |||
96 | static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, | ||
24 | -- | 97 | -- |
25 | 2.20.1 | 98 | 2.34.1 |
26 | 99 | ||
27 | 100 | diff view generated by jsdifflib |
1 | From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com> | 1 | From: Leif Lindholm <quic_llindhol@quicinc.com> |
---|---|---|---|
2 | 2 | ||
3 | Missed in commit f3478392 "docs: Move deprecation, build | 3 | I'm migrating to Qualcomm's new open source email infrastructure, so |
4 | and license info out of system/" | 4 | update my email address, and update the mailmap to match. |
5 | 5 | ||
6 | Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com> | 6 | Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com> |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> |
8 | Message-id: 20210723065828.1336760-1-maozhongyi@cmss.chinamobile.com | 8 | Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com> |
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
10 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 13 | --- |
11 | configure | 2 +- | 14 | MAINTAINERS | 2 +- |
12 | target/i386/cpu.c | 2 +- | 15 | .mailmap | 5 +++-- |
13 | MAINTAINERS | 2 +- | 16 | 2 files changed, 4 insertions(+), 3 deletions(-) |
14 | 3 files changed, 3 insertions(+), 3 deletions(-) | ||
15 | 17 | ||
16 | diff --git a/configure b/configure | ||
17 | index XXXXXXX..XXXXXXX 100755 | ||
18 | --- a/configure | ||
19 | +++ b/configure | ||
20 | @@ -XXX,XX +XXX,XX @@ fi | ||
21 | |||
22 | if test -n "${deprecated_features}"; then | ||
23 | echo "Warning, deprecated features enabled." | ||
24 | - echo "Please see docs/system/deprecated.rst" | ||
25 | + echo "Please see docs/about/deprecated.rst" | ||
26 | echo " features: ${deprecated_features}" | ||
27 | fi | ||
28 | |||
29 | diff --git a/target/i386/cpu.c b/target/i386/cpu.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/i386/cpu.c | ||
32 | +++ b/target/i386/cpu.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static const X86CPUDefinition builtin_x86_defs[] = { | ||
34 | * none", but this is just for compatibility while libvirt isn't | ||
35 | * adapted to resolve CPU model versions before creating VMs. | ||
36 | * See "Runnability guarantee of CPU models" at | ||
37 | - * docs/system/deprecated.rst. | ||
38 | + * docs/about/deprecated.rst. | ||
39 | */ | ||
40 | X86CPUVersion default_cpu_version = 1; | ||
41 | |||
42 | diff --git a/MAINTAINERS b/MAINTAINERS | 18 | diff --git a/MAINTAINERS b/MAINTAINERS |
43 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
44 | --- a/MAINTAINERS | 20 | --- a/MAINTAINERS |
45 | +++ b/MAINTAINERS | 21 | +++ b/MAINTAINERS |
46 | @@ -XXX,XX +XXX,XX @@ F: contrib/gitdm/* | 22 | @@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h |
47 | 23 | SBSA-REF | |
48 | Incompatible changes | 24 | M: Radoslaw Biernacki <rad@semihalf.com> |
49 | R: libvir-list@redhat.com | 25 | M: Peter Maydell <peter.maydell@linaro.org> |
50 | -F: docs/system/deprecated.rst | 26 | -R: Leif Lindholm <quic_llindhol@quicinc.com> |
51 | +F: docs/about/deprecated.rst | 27 | +R: Leif Lindholm <leif.lindholm@oss.qualcomm.com> |
52 | 28 | R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | |
53 | Build System | 29 | L: qemu-arm@nongnu.org |
54 | ------------ | 30 | S: Maintained |
31 | diff --git a/.mailmap b/.mailmap | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/.mailmap | ||
34 | +++ b/.mailmap | ||
35 | @@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com> | ||
36 | Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn> | ||
37 | James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com> | ||
38 | Juan Quintela <quintela@trasno.org> <quintela@redhat.com> | ||
39 | -Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org> | ||
40 | -Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com> | ||
41 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com> | ||
42 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org> | ||
43 | +Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com> | ||
44 | Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr> | ||
45 | Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com> | ||
46 | Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu> | ||
55 | -- | 47 | -- |
56 | 2.20.1 | 48 | 2.34.1 |
57 | 49 | ||
58 | 50 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Vikram Garhwal <vikram.garhwal@bytedance.com> | ||
1 | 2 | ||
3 | Previously, maintainer role was paused due to inactive email id. Commit id: | ||
4 | c009d715721861984c4987bcc78b7ee183e86d75. | ||
5 | |||
6 | Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com> | ||
7 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
8 | Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | MAINTAINERS | 2 ++ | ||
12 | 1 file changed, 2 insertions(+) | ||
13 | |||
14 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/MAINTAINERS | ||
17 | +++ b/MAINTAINERS | ||
18 | @@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c | ||
19 | |||
20 | Xilinx CAN | ||
21 | M: Francisco Iglesias <francisco.iglesias@amd.com> | ||
22 | +M: Vikram Garhwal <vikram.garhwal@bytedance.com> | ||
23 | S: Maintained | ||
24 | F: hw/net/can/xlnx-* | ||
25 | F: include/hw/net/xlnx-* | ||
26 | @@ -XXX,XX +XXX,XX @@ F: include/hw/rx/ | ||
27 | CAN bus subsystem and hardware | ||
28 | M: Pavel Pisa <pisa@cmp.felk.cvut.cz> | ||
29 | M: Francisco Iglesias <francisco.iglesias@amd.com> | ||
30 | +M: Vikram Garhwal <vikram.garhwal@bytedance.com> | ||
31 | S: Maintained | ||
32 | W: https://canbus.pages.fel.cvut.cz/ | ||
33 | F: net/can/* | ||
34 | -- | ||
35 | 2.34.1 | diff view generated by jsdifflib |