arm pullreq for rc1. All minor bugfixes, except for the sve-default-vector-length

patches, which are somewhere between a bugfix and a new feature.

The following changes since commit c08ccd1b53f488ac86c1f65cf7623dc91acc249a:

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210726' into staging (2021-07-27 08:35:01 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210727

for you to fetch changes up to e229a179a503f2aee43a76888cf12fbdfe8a3749:

hw: aspeed_gpio: Fix memory size (2021-07-27 11:00:00 +0100)

* hw/arm/smmuv3: Check 31st bit to see if CD is valid

* qemu-options.hx: Fix formatting of -machine memory-backend option

* hw: aspeed_gpio: Fix memory size

* hw/arm/nseries: Display hexadecimal value with '0x' prefix

* Add sve-default-vector-length cpu property

* docs: Update path that mentions deprecated.rst

* hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS

* hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING

* hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts

* target/arm: Report M-profile alignment faults correctly to the guest

* target/arm: Add missing 'return's after calling v7m_exception_taken()

* target/arm: Enforce that M-profile SP low 2 bits are always zero

Joe Komlodi (1):

hw/arm/smmuv3: Check 31st bit to see if CD is valid

Joel Stanley (1):

hw: aspeed_gpio: Fix memory size

Mao Zhongyi (1):

docs: Update path that mentions deprecated.rst

Peter Maydell (7):

qemu-options.hx: Fix formatting of -machine memory-backend option

target/arm: Enforce that M-profile SP low 2 bits are always zero

target/arm: Add missing 'return's after calling v7m_exception_taken()

target/arm: Report M-profile alignment faults correctly to the guest

hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts

hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING

hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS

hw/arm/nseries: Display hexadecimal value with '0x' prefix

Richard Henderson (3):

target/arm: Correctly bound length in sve_zcr_get_valid_len

target/arm: Export aarch64_sve_zcr_get_valid_len

target/arm: Add sve-default-vector-length cpu property

docs/system/arm/cpu-features.rst | 15 ++++++++++

configure | 2 +-

hw/arm/smmuv3-internal.h | 2 +-

target/arm/cpu.h | 5 ++++

target/arm/internals.h | 10 +++++++

hw/arm/nseries.c | 2 +-

hw/gpio/aspeed_gpio.c | 3 +-

hw/intc/armv7m_nvic.c | 40 +++++++++++++++++++--------

target/arm/cpu.c | 14 ++++++++--

target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++++++++++

target/arm/gdbstub.c | 4 +++

target/arm/helper.c | 8 ++++--

target/arm/m_helper.c | 24 ++++++++++++----

target/arm/translate.c | 3 ++

target/i386/cpu.c | 2 +-

MAINTAINERS | 2 +-

qemu-options.hx | 30 +++++++++++---------

17 files changed, 183 insertions(+), 43 deletions(-)

From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>

Missed in commit f3478392 "docs: Move deprecation, build

and license info out of system/"

Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20210723065828.1336760-1-maozhongyi@cmss.chinamobile.com

configure | 2 +-

target/i386/cpu.c | 2 +-

MAINTAINERS | 2 +-

3 files changed, 3 insertions(+), 3 deletions(-)

@@ -XXX,XX +XXX,XX @@ F: contrib/gitdm/*

Incompatible changes

R: libvir-list@redhat.com

-F: docs/system/deprecated.rst

+F: docs/about/deprecated.rst

Build System

------------

2.20.1

In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if

the register is accessed NonSecure and the highest priority pending

enabled exception (that would be returned in the VECTPENDING field)

targets Secure, then the VECTPENDING field must read 1 rather than

the exception number of the pending exception. Implement this.

hw/intc/armv7m_nvic.c | 31 ++++++++++++++++++++++++-------

1 file changed, 24 insertions(+), 7 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)

nvic_irq_update(s);

}

+static bool vectpending_targets_secure(NVICState *s)

+{

+ /* Return true if s->vectpending targets Secure state */

+ if (s->vectpending_is_s_banked) {

+ return true;

+ }

+ return !exc_is_banked(s->vectpending) &&

+ exc_targets_secure(s, s->vectpending);

+}

+

void armv7m_nvic_get_pending_irq_info(void *opaque,

int *pirq, bool *ptargets_secure)

{

@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,

assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);

- if (s->vectpending_is_s_banked) {

- targets_secure = true;

- } else {

- targets_secure = !exc_is_banked(pending) &&

- exc_targets_secure(s, pending);

- }

+ targets_secure = vectpending_targets_secure(s);

trace_nvic_get_pending_irq_info(pending, targets_secure);

@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

/* VECTACTIVE */

val = cpu->env.v7m.exception;

/* VECTPENDING */

- val |= (s->vectpending & 0x1ff) << 12;

+ if (s->vectpending) {

+ /*

+ * From v8.1M VECTPENDING must read as 1 if accessed as

+ * NonSecure and the highest priority pending and enabled

+ * exception targets Secure.

+ */

+ int vp = s->vectpending;

+ if (!attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_V8_1M) &&

+ vectpending_targets_secure(s)) {

+ vp = 1;

+ }

+ val |= (vp & 0x1ff) << 12;

+ }

/* ISRPENDING - set if any external IRQ is pending */

if (nvic_isrpending(s)) {

val |= (1 << 22);

2.20.1

The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of

the register. We were incorrectly masking it to 8 bits, so it would

report the wrong value if the pending exception was greater than 256.

Fix the bug.

hw/intc/armv7m_nvic.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

/* VECTACTIVE */

val = cpu->env.v7m.exception;

/* VECTPENDING */

- val |= (s->vectpending & 0xff) << 12;

+ val |= (s->vectpending & 0x1ff) << 12;

/* ISRPENDING - set if any external IRQ is pending */

if (nvic_isrpending(s)) {

val |= (1 << 22);

2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210726150953.1218690-1-f4bug@amsat.org

hw/arm/nseries.c | 2 +-

diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c

--- a/hw/arm/nseries.c

+++ b/hw/arm/nseries.c

@@ -XXX,XX +XXX,XX @@ static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)

default:

bad_cmd:

qemu_log_mask(LOG_GUEST_ERROR,

- "%s: unknown command %02x\n", __func__, s->cmd);

+ "%s: unknown command 0x%02x\n", __func__, s->cmd);

break;

2.20.1

From: Joel Stanley <joel@jms.id.au>

The macro used to calculate the maximum memory size of the MMIO region

had a mistake, causing all GPIO models to create a mapping of 0x9D8.

The intent was to have it be 0x9D8 - 0x800.

This extra size doesn't matter on ast2400 and ast2500, which have a 4KB

region set aside for the GPIO controller.

On the ast2600 the 3.3V and 1.8V GPIO controllers are 2KB apart, so the

regions would overlap. Worse was the 1.8V controller would map over the

top of the following peripheral, which happens to be the RTC.

The mmio region used by each device is a maximum of 2KB, so avoid the

calculations and hard code this as the maximum.

Fixes: 36d737ee82b2 ("hw/gpio: Add in AST2600 specific implementation")

Signed-off-by: Joel Stanley <joel@jms.id.au>

Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Message-id: 20210713065854.134634-2-joel@jms.id.au

[PMM: fix autocorrect error in commit message]

hw/gpio/aspeed_gpio.c | 3 +--

1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c

--- a/hw/gpio/aspeed_gpio.c

+++ b/hw/gpio/aspeed_gpio.c

#define GPIO_1_8V_MEM_SIZE 0x9D8

#define GPIO_1_8V_REG_ARRAY_SIZE ((GPIO_1_8V_MEM_SIZE - \

GPIO_1_8V_REG_OFFSET) >> 2)

-#define GPIO_MAX_MEM_SIZE MAX(GPIO_3_6V_MEM_SIZE, GPIO_1_8V_MEM_SIZE)

static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio)

@@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_realize(DeviceState *dev, Error **errp)

memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s,

- TYPE_ASPEED_GPIO, GPIO_MAX_MEM_SIZE);

+ TYPE_ASPEED_GPIO, 0x800);

sysbus_init_mmio(sbd, &s->iomem);

2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Currently, our only caller is sve_zcr_len_for_el, which has

already masked the length extracted from ZCR_ELx, so the

masking done here is a nop. But we will shortly have uses

from other locations, where the length will be unmasked.

Saturate the length to ARM_MAX_VQ instead of truncating to

the low 4 bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/arm/helper.c | 4 +++-

1 file changed, 3 insertions(+), 1 deletion(-)

@@ -XXX,XX +XXX,XX @@ static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)

{

uint32_t end_len;

- end_len = start_len &= 0xf;

+ start_len = MIN(start_len, ARM_MAX_VQ - 1);

+ end_len = start_len;

+

if (!test_bit(start_len, cpu->sve_vq_map)) {

end_len = find_last_bit(cpu->sve_vq_map, start_len);

assert(end_len < start_len);

2.20.1