1
arm pullreq for rc1. All minor bugfixes, except for the sve-default-vector-length
1
target-arm queue: just bugfixes, mostly mine.
2
patches, which are somewhere between a bugfix and a new feature.
3
2
4
thanks
3
thanks
5
-- PMM
4
-- PMM
6
5
7
The following changes since commit c08ccd1b53f488ac86c1f65cf7623dc91acc249a:
6
The following changes since commit 885fc169f09f5915ce037263d20a59eb226d473d:
8
7
9
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210726' into staging (2021-07-27 08:35:01 +0100)
8
Merge tag 'pull-riscv-to-apply-20230723-3' of https://github.com/alistair23/qemu into staging (2023-07-24 11:34:35 +0100)
10
9
11
are available in the Git repository at:
10
are available in the Git repository at:
12
11
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210727
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230725
14
13
15
for you to fetch changes up to e229a179a503f2aee43a76888cf12fbdfe8a3749:
14
for you to fetch changes up to 78cc90346ec680a7f1bb9f138bf7c9654cf526d5:
16
15
17
hw: aspeed_gpio: Fix memory size (2021-07-27 11:00:00 +0100)
16
tests/decode: Suppress "error: " string for expected-failure tests (2023-07-25 10:56:52 +0100)
18
17
19
----------------------------------------------------------------
18
----------------------------------------------------------------
20
target-arm queue:
19
target-arm queue:
21
* hw/arm/smmuv3: Check 31st bit to see if CD is valid
20
* tests/decode: Suppress "error: " string for expected-failure tests
22
* qemu-options.hx: Fix formatting of -machine memory-backend option
21
* ui/curses: For curses display, recognize a few more control keys
23
* hw: aspeed_gpio: Fix memory size
22
* target/arm: Special case M-profile in debug_helper.c code
24
* hw/arm/nseries: Display hexadecimal value with '0x' prefix
23
* scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour
25
* Add sve-default-vector-length cpu property
24
* hw/arm/smmu: Handle big-endian hosts correctly
26
* docs: Update path that mentions deprecated.rst
27
* hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
28
* hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
29
* hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
30
* target/arm: Report M-profile alignment faults correctly to the guest
31
* target/arm: Add missing 'return's after calling v7m_exception_taken()
32
* target/arm: Enforce that M-profile SP low 2 bits are always zero
33
25
34
----------------------------------------------------------------
26
----------------------------------------------------------------
35
Joe Komlodi (1):
27
Peter Maydell (4):
36
hw/arm/smmuv3: Check 31st bit to see if CD is valid
28
hw/arm/smmu: Handle big-endian hosts correctly
29
scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour
30
target/arm: Special case M-profile in debug_helper.c code
31
tests/decode: Suppress "error: " string for expected-failure tests
37
32
38
Joel Stanley (1):
33
Sean Estabrooks (1):
39
hw: aspeed_gpio: Fix memory size
34
For curses display, recognize a few more control keys
40
35
41
Mao Zhongyi (1):
36
ui/curses_keys.h | 6 ++++++
42
docs: Update path that mentions deprecated.rst
37
hw/arm/smmu-common.c | 3 +--
43
38
hw/arm/smmuv3.c | 39 +++++++++++++++++++++++++++++++--------
44
Peter Maydell (7):
39
target/arm/debug_helper.c | 18 ++++++++++++------
45
qemu-options.hx: Fix formatting of -machine memory-backend option
40
scripts/decodetree.py | 6 +++++-
46
target/arm: Enforce that M-profile SP low 2 bits are always zero
41
scripts/git-submodule.sh | 2 +-
47
target/arm: Add missing 'return's after calling v7m_exception_taken()
42
6 files changed, 56 insertions(+), 18 deletions(-)
48
target/arm: Report M-profile alignment faults correctly to the guest
49
hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
50
hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
51
hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
52
53
Philippe Mathieu-Daudé (1):
54
hw/arm/nseries: Display hexadecimal value with '0x' prefix
55
56
Richard Henderson (3):
57
target/arm: Correctly bound length in sve_zcr_get_valid_len
58
target/arm: Export aarch64_sve_zcr_get_valid_len
59
target/arm: Add sve-default-vector-length cpu property
60
61
docs/system/arm/cpu-features.rst | 15 ++++++++++
62
configure | 2 +-
63
hw/arm/smmuv3-internal.h | 2 +-
64
target/arm/cpu.h | 5 ++++
65
target/arm/internals.h | 10 +++++++
66
hw/arm/nseries.c | 2 +-
67
hw/gpio/aspeed_gpio.c | 3 +-
68
hw/intc/armv7m_nvic.c | 40 +++++++++++++++++++--------
69
target/arm/cpu.c | 14 ++++++++--
70
target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++++++++++
71
target/arm/gdbstub.c | 4 +++
72
target/arm/helper.c | 8 ++++--
73
target/arm/m_helper.c | 24 ++++++++++++----
74
target/arm/translate.c | 3 ++
75
target/i386/cpu.c | 2 +-
76
MAINTAINERS | 2 +-
77
qemu-options.hx | 30 +++++++++++---------
78
17 files changed, 183 insertions(+), 43 deletions(-)
79
diff view generated by jsdifflib
1
In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if
1
The implementation of the SMMUv3 has multiple places where it reads a
2
the register is accessed NonSecure and the highest priority pending
2
data structure from the guest and directly operates on it without
3
enabled exception (that would be returned in the VECTPENDING field)
3
doing a guest-to-host endianness conversion. Since all SMMU data
4
targets Secure, then the VECTPENDING field must read 1 rather than
4
structures are little-endian, this means that the SMMU doesn't work
5
the exception number of the pending exception. Implement this.
5
on a big-endian host. In particular, this causes the Avocado test
6
machine_aarch64_virt.py:Aarch64VirtMachine.test_alpine_virt_tcg_gic_max
7
to fail on an s390x host.
8
9
Add appropriate byte-swapping on reads and writes of guest in-memory
10
data structures so that the device works correctly on big-endian
11
hosts.
12
13
As part of this we constrain queue_read() to operate only on Cmd
14
structs and queue_write() on Evt structs, because in practice these
15
are the only data structures the two functions are used with, and we
16
need to know what the data structure is to be able to byte-swap its
17
parts correctly.
6
18
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Tested-by: Thomas Huth <thuth@redhat.com>
9
Message-id: 20210723162146.5167-7-peter.maydell@linaro.org
21
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
22
Reviewed-by: Eric Auger <eric.auger@redhat.com>
23
Message-id: 20230717132641.764660-1-peter.maydell@linaro.org
24
Cc: qemu-stable@nongnu.org
10
---
25
---
11
hw/intc/armv7m_nvic.c | 31 ++++++++++++++++++++++++-------
26
hw/arm/smmu-common.c | 3 +--
12
1 file changed, 24 insertions(+), 7 deletions(-)
27
hw/arm/smmuv3.c | 39 +++++++++++++++++++++++++++++++--------
28
2 files changed, 32 insertions(+), 10 deletions(-)
13
29
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
30
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
15
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
32
--- a/hw/arm/smmu-common.c
17
+++ b/hw/intc/armv7m_nvic.c
33
+++ b/hw/arm/smmu-common.c
18
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
34
@@ -XXX,XX +XXX,XX @@ static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte,
19
nvic_irq_update(s);
35
dma_addr_t addr = baseaddr + index * sizeof(*pte);
36
37
/* TODO: guarantee 64-bit single-copy atomicity */
38
- ret = dma_memory_read(&address_space_memory, addr, pte, sizeof(*pte),
39
- MEMTXATTRS_UNSPECIFIED);
40
+ ret = ldq_le_dma(&address_space_memory, addr, pte, MEMTXATTRS_UNSPECIFIED);
41
42
if (ret != MEMTX_OK) {
43
info->type = SMMU_PTW_ERR_WALK_EABT;
44
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/arm/smmuv3.c
47
+++ b/hw/arm/smmuv3.c
48
@@ -XXX,XX +XXX,XX @@ static void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn)
49
trace_smmuv3_write_gerrorn(toggled & pending, s->gerrorn);
20
}
50
}
21
51
22
+static bool vectpending_targets_secure(NVICState *s)
52
-static inline MemTxResult queue_read(SMMUQueue *q, void *data)
23
+{
53
+static inline MemTxResult queue_read(SMMUQueue *q, Cmd *cmd)
24
+ /* Return true if s->vectpending targets Secure state */
54
{
25
+ if (s->vectpending_is_s_banked) {
55
dma_addr_t addr = Q_CONS_ENTRY(q);
26
+ return true;
56
+ MemTxResult ret;
57
+ int i;
58
59
- return dma_memory_read(&address_space_memory, addr, data, q->entry_size,
60
- MEMTXATTRS_UNSPECIFIED);
61
+ ret = dma_memory_read(&address_space_memory, addr, cmd, sizeof(Cmd),
62
+ MEMTXATTRS_UNSPECIFIED);
63
+ if (ret != MEMTX_OK) {
64
+ return ret;
27
+ }
65
+ }
28
+ return !exc_is_banked(s->vectpending) &&
66
+ for (i = 0; i < ARRAY_SIZE(cmd->word); i++) {
29
+ exc_targets_secure(s, s->vectpending);
67
+ le32_to_cpus(&cmd->word[i]);
30
+}
68
+ }
31
+
69
+ return ret;
32
void armv7m_nvic_get_pending_irq_info(void *opaque,
70
}
33
int *pirq, bool *ptargets_secure)
71
72
-static MemTxResult queue_write(SMMUQueue *q, void *data)
73
+static MemTxResult queue_write(SMMUQueue *q, Evt *evt_in)
34
{
74
{
35
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,
75
dma_addr_t addr = Q_PROD_ENTRY(q);
36
76
MemTxResult ret;
37
assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
77
+ Evt evt = *evt_in;
38
78
+ int i;
39
- if (s->vectpending_is_s_banked) {
79
40
- targets_secure = true;
80
- ret = dma_memory_write(&address_space_memory, addr, data, q->entry_size,
41
- } else {
81
+ for (i = 0; i < ARRAY_SIZE(evt.word); i++) {
42
- targets_secure = !exc_is_banked(pending) &&
82
+ cpu_to_le32s(&evt.word[i]);
43
- exc_targets_secure(s, pending);
83
+ }
44
- }
84
+ ret = dma_memory_write(&address_space_memory, addr, &evt, sizeof(Evt),
45
+ targets_secure = vectpending_targets_secure(s);
85
MEMTXATTRS_UNSPECIFIED);
46
86
if (ret != MEMTX_OK) {
47
trace_nvic_get_pending_irq_info(pending, targets_secure);
87
return ret;
48
88
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
49
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
89
static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
50
/* VECTACTIVE */
90
SMMUEventInfo *event)
51
val = cpu->env.v7m.exception;
91
{
52
/* VECTPENDING */
92
- int ret;
53
- val |= (s->vectpending & 0x1ff) << 12;
93
+ int ret, i;
54
+ if (s->vectpending) {
94
55
+ /*
95
trace_smmuv3_get_ste(addr);
56
+ * From v8.1M VECTPENDING must read as 1 if accessed as
96
/* TODO: guarantee 64-bit single-copy atomicity */
57
+ * NonSecure and the highest priority pending and enabled
97
@@ -XXX,XX +XXX,XX @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
58
+ * exception targets Secure.
98
event->u.f_ste_fetch.addr = addr;
59
+ */
99
return -EINVAL;
60
+ int vp = s->vectpending;
100
}
61
+ if (!attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_V8_1M) &&
101
+ for (i = 0; i < ARRAY_SIZE(buf->word); i++) {
62
+ vectpending_targets_secure(s)) {
102
+ le32_to_cpus(&buf->word[i]);
63
+ vp = 1;
103
+ }
64
+ }
104
return 0;
65
+ val |= (vp & 0x1ff) << 12;
105
106
}
107
@@ -XXX,XX +XXX,XX @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
108
CD *buf, SMMUEventInfo *event)
109
{
110
dma_addr_t addr = STE_CTXPTR(ste);
111
- int ret;
112
+ int ret, i;
113
114
trace_smmuv3_get_cd(addr);
115
/* TODO: guarantee 64-bit single-copy atomicity */
116
@@ -XXX,XX +XXX,XX @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid,
117
event->u.f_ste_fetch.addr = addr;
118
return -EINVAL;
119
}
120
+ for (i = 0; i < ARRAY_SIZE(buf->word); i++) {
121
+ le32_to_cpus(&buf->word[i]);
122
+ }
123
return 0;
124
}
125
126
@@ -XXX,XX +XXX,XX @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste,
127
return -EINVAL;
128
}
129
if (s->features & SMMU_FEATURE_2LVL_STE) {
130
- int l1_ste_offset, l2_ste_offset, max_l2_ste, span;
131
+ int l1_ste_offset, l2_ste_offset, max_l2_ste, span, i;
132
dma_addr_t l1ptr, l2ptr;
133
STEDesc l1std;
134
135
@@ -XXX,XX +XXX,XX @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste,
136
event->u.f_ste_fetch.addr = l1ptr;
137
return -EINVAL;
138
}
139
+ for (i = 0; i < ARRAY_SIZE(l1std.word); i++) {
140
+ le32_to_cpus(&l1std.word[i]);
66
+ }
141
+ }
67
/* ISRPENDING - set if any external IRQ is pending */
142
68
if (nvic_isrpending(s)) {
143
span = L1STD_SPAN(&l1std);
69
val |= (1 << 22);
144
70
--
145
--
71
2.20.1
146
2.34.1
72
147
73
148
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
The POSIX definition of the 'read' utility requires that you
2
specify the variable name to set; omitting the name and
3
having it default to 'REPLY' is a bashism. If your system
4
sh is dash, then it will print an error message during build:
2
5
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
qemu/pc-bios/s390-ccw/../../scripts/git-submodule.sh: 106: read: arg count
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
5
Message-id: 20210726150953.1218690-1-f4bug@amsat.org
8
Specify the variable name explicitly.
9
10
Fixes: fdb8fd8cb915647b ("git-submodule: allow partial update of .git-submodule-status")
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Message-id: 20230720153038.1587196-1-peter.maydell@linaro.org
7
---
15
---
8
hw/arm/nseries.c | 2 +-
16
scripts/git-submodule.sh | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
17
1 file changed, 1 insertion(+), 1 deletion(-)
10
18
11
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
19
diff --git a/scripts/git-submodule.sh b/scripts/git-submodule.sh
12
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100755
13
--- a/hw/arm/nseries.c
21
--- a/scripts/git-submodule.sh
14
+++ b/hw/arm/nseries.c
22
+++ b/scripts/git-submodule.sh
15
@@ -XXX,XX +XXX,XX @@ static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
23
@@ -XXX,XX +XXX,XX @@ update)
16
default:
24
check_updated $module || echo Updated "$module"
17
bad_cmd:
25
done
18
qemu_log_mask(LOG_GUEST_ERROR,
26
19
- "%s: unknown command %02x\n", __func__, s->cmd);
27
- (while read -r; do
20
+ "%s: unknown command 0x%02x\n", __func__, s->cmd);
28
+ (while read -r REPLY; do
21
break;
29
for module in $modules; do
22
}
30
case $REPLY in
23
31
*" $module "*) continue 2 ;;
24
--
32
--
25
2.20.1
33
2.34.1
26
34
27
35
diff view generated by jsdifflib
1
From: Joel Stanley <joel@jms.id.au>
1
A lot of the code called from helper_exception_bkpt_insn() is written
2
assuming A-profile, but we will also call this helper on M-profile
3
CPUs when they execute a BKPT insn. This used to work by accident,
4
but recent changes mean that we will hit an assert when some of this
5
code calls down into lower level functions that end up calling
6
arm_security_space_below_el3(), arm_el_is_aa64(), and other functions
7
that now explicitly assert that the guest CPU is not M-profile.
2
8
3
The macro used to calculate the maximum memory size of the MMIO region
9
Handle M-profile directly to avoid the assertions:
4
had a mistake, causing all GPIO models to create a mapping of 0x9D8.
10
* in arm_debug_target_el(), M-profile debug exceptions always
5
The intent was to have it be 0x9D8 - 0x800.
11
go to EL1
12
* in arm_debug_exception_fsr(), M-profile always uses the short
13
format FSR (compare commit d7fe699be54b2, though in this case
14
the code in arm_v7m_cpu_do_interrupt() does not need to
15
look at the FSR value at all)
6
16
7
This extra size doesn't matter on ast2400 and ast2500, which have a 4KB
17
Cc: qemu-stable@nongnu.org
8
region set aside for the GPIO controller.
18
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1775
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20230721143239.1753066-1-peter.maydell@linaro.org
22
---
23
target/arm/debug_helper.c | 18 ++++++++++++------
24
1 file changed, 12 insertions(+), 6 deletions(-)
9
25
10
On the ast2600 the 3.3V and 1.8V GPIO controllers are 2KB apart, so the
26
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
11
regions would overlap. Worse was the 1.8V controller would map over the
12
top of the following peripheral, which happens to be the RTC.
13
14
The mmio region used by each device is a maximum of 2KB, so avoid the
15
calculations and hard code this as the maximum.
16
17
Fixes: 36d737ee82b2 ("hw/gpio: Add in AST2600 specific implementation")
18
Signed-off-by: Joel Stanley <joel@jms.id.au>
19
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
20
Reviewed-by: Cédric Le Goater <clg@kaod.org>
21
Message-id: 20210713065854.134634-2-joel@jms.id.au
22
[PMM: fix autocorrect error in commit message]
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
25
hw/gpio/aspeed_gpio.c | 3 +--
26
1 file changed, 1 insertion(+), 2 deletions(-)
27
28
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
29
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/gpio/aspeed_gpio.c
28
--- a/target/arm/debug_helper.c
31
+++ b/hw/gpio/aspeed_gpio.c
29
+++ b/target/arm/debug_helper.c
32
@@ -XXX,XX +XXX,XX @@
30
@@ -XXX,XX +XXX,XX @@ static int arm_debug_target_el(CPUARMState *env)
33
#define GPIO_1_8V_MEM_SIZE 0x9D8
31
bool secure = arm_is_secure(env);
34
#define GPIO_1_8V_REG_ARRAY_SIZE ((GPIO_1_8V_MEM_SIZE - \
32
bool route_to_el2 = false;
35
GPIO_1_8V_REG_OFFSET) >> 2)
33
36
-#define GPIO_MAX_MEM_SIZE MAX(GPIO_3_6V_MEM_SIZE, GPIO_1_8V_MEM_SIZE)
34
+ if (arm_feature(env, ARM_FEATURE_M)) {
37
35
+ return 1;
38
static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio)
36
+ }
37
+
38
if (arm_is_el2_enabled(env)) {
39
route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
40
env->cp15.mdcr_el2 & MDCR_TDE;
41
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env)
39
{
42
{
40
@@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_realize(DeviceState *dev, Error **errp)
43
ARMMMUFaultInfo fi = { .type = ARMFault_Debug };
44
int target_el = arm_debug_target_el(env);
45
- bool using_lpae = false;
46
+ bool using_lpae;
47
48
- if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
49
+ if (arm_feature(env, ARM_FEATURE_M)) {
50
+ using_lpae = false;
51
+ } else if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
52
using_lpae = true;
53
} else if (arm_feature(env, ARM_FEATURE_PMSA) &&
54
arm_feature(env, ARM_FEATURE_V8)) {
55
using_lpae = true;
56
+ } else if (arm_feature(env, ARM_FEATURE_LPAE) &&
57
+ (env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
58
+ using_lpae = true;
59
} else {
60
- if (arm_feature(env, ARM_FEATURE_LPAE) &&
61
- (env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
62
- using_lpae = true;
63
- }
64
+ using_lpae = false;
41
}
65
}
42
66
43
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s,
67
if (using_lpae) {
44
- TYPE_ASPEED_GPIO, GPIO_MAX_MEM_SIZE);
45
+ TYPE_ASPEED_GPIO, 0x800);
46
47
sysbus_init_mmio(sbd, &s->iomem);
48
}
49
--
68
--
50
2.20.1
69
2.34.1
51
52
diff view generated by jsdifflib
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
1
From: Sean Estabrooks <sean.estabrooks@gmail.com>
2
2
3
The bit to see if a CD is valid is the last bit of the first word of the CD.
3
The curses display handles most control-X keys, and translates
4
them into their corresponding keycode. Here we recognize
5
a few that are missing, Ctrl-@ (null), Ctrl-\ (backslash),
6
Ctrl-] (right bracket), Ctrl-^ (caret), Ctrl-_ (underscore).
4
7
5
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
8
Signed-off-by: Sean Estabrooks <sean.estabrooks@gmail.com>
6
Message-id: 1626728232-134665-2-git-send-email-joe.komlodi@xilinx.com
9
Message-id: CAHyVn3Bh9CRgDuOmf7G7Ngwamu8d4cVozAcB2i4ymnnggBXNmg@mail.gmail.com
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
hw/arm/smmuv3-internal.h | 2 +-
13
ui/curses_keys.h | 6 ++++++
11
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 6 insertions(+)
12
15
13
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
16
diff --git a/ui/curses_keys.h b/ui/curses_keys.h
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/smmuv3-internal.h
18
--- a/ui/curses_keys.h
16
+++ b/hw/arm/smmuv3-internal.h
19
+++ b/ui/curses_keys.h
17
@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)
20
@@ -XXX,XX +XXX,XX @@ static const int _curses2keycode[CURSES_CHARS] = {
18
21
['N' - '@'] = 49 | CNTRL, /* Control + n */
19
/* CD fields */
22
/* Control + m collides with the keycode for Enter */
20
23
21
-#define CD_VALID(x) extract32((x)->word[0], 30, 1)
24
+ ['@' - '@'] = 3 | CNTRL, /* Control + @ */
22
+#define CD_VALID(x) extract32((x)->word[0], 31, 1)
25
+ /* Control + [ collides with the keycode for Escape */
23
#define CD_ASID(x) extract32((x)->word[1], 16, 16)
26
+ ['\\' - '@'] = 43 | CNTRL, /* Control + Backslash */
24
#define CD_TTB(x, sel) \
27
+ [']' - '@'] = 27 | CNTRL, /* Control + ] */
25
({ \
28
+ ['^' - '@'] = 7 | CNTRL, /* Control + ^ */
29
+ ['_' - '@'] = 12 | CNTRL, /* Control + Underscore */
30
};
31
32
static const int _curseskey2keycode[CURSES_KEYS] = {
26
--
33
--
27
2.20.1
34
2.34.1
28
29
diff view generated by jsdifflib
Deleted patch
1
The documentation of the -machine memory-backend has some minor
2
formatting errors:
3
* Misindentation of the initial line meant that the whole option
4
section is incorrectly indented in the HTML output compared to
5
the other -machine options
6
* The examples weren't indented, which meant that they were formatted
7
as plain run-on text including outputting the "::" as text.
8
* The a) b) list has no rst-format markup so it is rendered as
9
a single run-on paragraph
10
1
11
Fix the formatting.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
15
Message-id: 20210719105257.3599-1-peter.maydell@linaro.org
16
---
17
qemu-options.hx | 30 +++++++++++++++++-------------
18
1 file changed, 17 insertions(+), 13 deletions(-)
19
20
diff --git a/qemu-options.hx b/qemu-options.hx
21
index XXXXXXX..XXXXXXX 100644
22
--- a/qemu-options.hx
23
+++ b/qemu-options.hx
24
@@ -XXX,XX +XXX,XX @@ SRST
25
Enables or disables ACPI Heterogeneous Memory Attribute Table
26
(HMAT) support. The default is off.
27
28
- ``memory-backend='id'``
29
+ ``memory-backend='id'``
30
An alternative to legacy ``-mem-path`` and ``mem-prealloc`` options.
31
Allows to use a memory backend as main RAM.
32
33
For example:
34
::
35
- -object memory-backend-file,id=pc.ram,size=512M,mem-path=/hugetlbfs,prealloc=on,share=on
36
- -machine memory-backend=pc.ram
37
- -m 512M
38
+
39
+ -object memory-backend-file,id=pc.ram,size=512M,mem-path=/hugetlbfs,prealloc=on,share=on
40
+ -machine memory-backend=pc.ram
41
+ -m 512M
42
43
Migration compatibility note:
44
- a) as backend id one shall use value of 'default-ram-id', advertised by
45
- machine type (available via ``query-machines`` QMP command), if migration
46
- to/from old QEMU (<5.0) is expected.
47
- b) for machine types 4.0 and older, user shall
48
- use ``x-use-canonical-path-for-ramblock-id=off`` backend option
49
- if migration to/from old QEMU (<5.0) is expected.
50
+
51
+ * as backend id one shall use value of 'default-ram-id', advertised by
52
+ machine type (available via ``query-machines`` QMP command), if migration
53
+ to/from old QEMU (<5.0) is expected.
54
+ * for machine types 4.0 and older, user shall
55
+ use ``x-use-canonical-path-for-ramblock-id=off`` backend option
56
+ if migration to/from old QEMU (<5.0) is expected.
57
+
58
For example:
59
::
60
- -object memory-backend-ram,id=pc.ram,size=512M,x-use-canonical-path-for-ramblock-id=off
61
- -machine memory-backend=pc.ram
62
- -m 512M
63
+
64
+ -object memory-backend-ram,id=pc.ram,size=512M,x-use-canonical-path-for-ramblock-id=off
65
+ -machine memory-backend=pc.ram
66
+ -m 512M
67
ERST
68
69
HXCOMM Deprecated by -machine
70
--
71
2.20.1
72
73
diff view generated by jsdifflib
Deleted patch
1
For M-profile, unlike A-profile, the low 2 bits of SP are defined to be
2
RES0H, which is to say that they must be hardwired to zero so that
3
guest attempts to write non-zero values to them are ignored.
4
1
5
Implement this behaviour by masking out the low bits:
6
* for writes to r13 by the gdbstub
7
* for writes to any of the various flavours of SP via MSR
8
* for writes to r13 via store_reg() in generated code
9
10
Note that all the direct uses of cpu_R[] in translate.c are in places
11
where the register is definitely not r13 (usually because that has
12
been checked for as an UNDEFINED or UNPREDICTABLE case and handled as
13
UNDEF).
14
15
All the other writes to regs[13] in C code are either:
16
* A-profile only code
17
* writes of values we can guarantee to be aligned, such as
18
- writes of previous-SP-value plus or minus a 4-aligned constant
19
- writes of the value in an SP limit register (which we already
20
enforce to be aligned)
21
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
24
Message-id: 20210723162146.5167-2-peter.maydell@linaro.org
25
---
26
target/arm/gdbstub.c | 4 ++++
27
target/arm/m_helper.c | 14 ++++++++------
28
target/arm/translate.c | 3 +++
29
3 files changed, 15 insertions(+), 6 deletions(-)
30
31
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/gdbstub.c
34
+++ b/target/arm/gdbstub.c
35
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
36
37
if (n < 16) {
38
/* Core integer register. */
39
+ if (n == 13 && arm_feature(env, ARM_FEATURE_M)) {
40
+ /* M profile SP low bits are always 0 */
41
+ tmp &= ~3;
42
+ }
43
env->regs[n] = tmp;
44
return 4;
45
}
46
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/m_helper.c
49
+++ b/target/arm/m_helper.c
50
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
51
if (!env->v7m.secure) {
52
return;
53
}
54
- env->v7m.other_ss_msp = val;
55
+ env->v7m.other_ss_msp = val & ~3;
56
return;
57
case 0x89: /* PSP_NS */
58
if (!env->v7m.secure) {
59
return;
60
}
61
- env->v7m.other_ss_psp = val;
62
+ env->v7m.other_ss_psp = val & ~3;
63
return;
64
case 0x8a: /* MSPLIM_NS */
65
if (!env->v7m.secure) {
66
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
67
68
limit = is_psp ? env->v7m.psplim[false] : env->v7m.msplim[false];
69
70
+ val &= ~0x3;
71
+
72
if (val < limit) {
73
raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC());
74
}
75
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
76
break;
77
case 8: /* MSP */
78
if (v7m_using_psp(env)) {
79
- env->v7m.other_sp = val;
80
+ env->v7m.other_sp = val & ~3;
81
} else {
82
- env->regs[13] = val;
83
+ env->regs[13] = val & ~3;
84
}
85
break;
86
case 9: /* PSP */
87
if (v7m_using_psp(env)) {
88
- env->regs[13] = val;
89
+ env->regs[13] = val & ~3;
90
} else {
91
- env->v7m.other_sp = val;
92
+ env->v7m.other_sp = val & ~3;
93
}
94
break;
95
case 10: /* MSPLIM */
96
diff --git a/target/arm/translate.c b/target/arm/translate.c
97
index XXXXXXX..XXXXXXX 100644
98
--- a/target/arm/translate.c
99
+++ b/target/arm/translate.c
100
@@ -XXX,XX +XXX,XX @@ void store_reg(DisasContext *s, int reg, TCGv_i32 var)
101
*/
102
tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3);
103
s->base.is_jmp = DISAS_JUMP;
104
+ } else if (reg == 13 && arm_dc_feature(s, ARM_FEATURE_M)) {
105
+ /* For M-profile SP bits [1:0] are always zero */
106
+ tcg_gen_andi_i32(var, var, ~3);
107
}
108
tcg_gen_mov_i32(cpu_R[reg], var);
109
tcg_temp_free_i32(var);
110
--
111
2.20.1
112
113
diff view generated by jsdifflib
Deleted patch
1
In do_v7m_exception_exit(), we perform various checks as part of
2
performing the exception return. If one of these checks fails, the
3
architecture requires that we take an appropriate exception on the
4
existing stackframe. We implement this by calling
5
v7m_exception_taken() to set up to take the new exception, and then
6
immediately returning from do_v7m_exception_exit() without proceeding
7
any further with the unstack-and-exception-return process.
8
1
9
In a couple of checks that are new in v8.1M, we forgot the "return"
10
statement, with the effect that if bad code in the guest tripped over
11
these checks we would set up to take a UsageFault exception but then
12
blunder on trying to also unstack and return from the original
13
exception, with the probable result that the guest would crash.
14
15
Add the missing return statements.
16
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20210723162146.5167-3-peter.maydell@linaro.org
20
---
21
target/arm/m_helper.c | 2 ++
22
1 file changed, 2 insertions(+)
23
24
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/m_helper.c
27
+++ b/target/arm/m_helper.c
28
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
29
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
30
"stackframe: NSACR prevents clearing FPU registers\n");
31
v7m_exception_taken(cpu, excret, true, false);
32
+ return;
33
} else if (!cpacr_pass) {
34
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
35
exc_secure);
36
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
37
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
38
"stackframe: CPACR prevents clearing FPU registers\n");
39
v7m_exception_taken(cpu, excret, true, false);
40
+ return;
41
}
42
}
43
/* Clear s0..s15, FPSCR and VPR */
44
--
45
2.20.1
46
47
diff view generated by jsdifflib
Deleted patch
1
For M-profile, we weren't reporting alignment faults triggered by the
2
generic TCG code correctly to the guest. These get passed into
3
arm_v7m_cpu_do_interrupt() as an EXCP_DATA_ABORT with an A-profile
4
style exception.fsr value of 1. We didn't check for this, and so
5
they fell through into the default of "assume this is an MPU fault"
6
and were reported to the guest as a data access violation MPU fault.
7
1
8
Report these alignment faults as UsageFaults which set the UNALIGNED
9
bit in the UFSR.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20210723162146.5167-4-peter.maydell@linaro.org
14
---
15
target/arm/m_helper.c | 8 ++++++++
16
1 file changed, 8 insertions(+)
17
18
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/m_helper.c
21
+++ b/target/arm/m_helper.c
22
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
23
env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK;
24
break;
25
case EXCP_UNALIGNED:
26
+ /* Unaligned faults reported by M-profile aware code */
27
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
28
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;
29
break;
30
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
31
}
32
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
33
break;
34
+ case 0x1: /* Alignment fault reported by generic code */
35
+ qemu_log_mask(CPU_LOG_INT,
36
+ "...really UsageFault with UFSR.UNALIGNED\n");
37
+ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;
38
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
39
+ env->v7m.secure);
40
+ break;
41
default:
42
/*
43
* All other FSR values are either MPU faults or "can't happen
44
--
45
2.20.1
46
47
diff view generated by jsdifflib
Deleted patch
1
The ISCR.ISRPENDING bit is set when an external interrupt is pending.
2
This is true whether that external interrupt is enabled or not.
3
This means that we can't use 's->vectpending == 0' as a shortcut to
4
"ISRPENDING is zero", because s->vectpending indicates only the
5
highest priority pending enabled interrupt.
6
1
7
Remove the incorrect optimization so that if there is no pending
8
enabled interrupt we fall through to scanning through the whole
9
interrupt array.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20210723162146.5167-5-peter.maydell@linaro.org
14
---
15
hw/intc/armv7m_nvic.c | 9 ++++-----
16
1 file changed, 4 insertions(+), 5 deletions(-)
17
18
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/intc/armv7m_nvic.c
21
+++ b/hw/intc/armv7m_nvic.c
22
@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
23
{
24
int irq;
25
26
- /* We can shortcut if the highest priority pending interrupt
27
- * happens to be external or if there is nothing pending.
28
+ /*
29
+ * We can shortcut if the highest priority pending interrupt
30
+ * happens to be external; if not we need to check the whole
31
+ * vectors[] array.
32
*/
33
if (s->vectpending > NVIC_FIRST_IRQ) {
34
return true;
35
}
36
- if (s->vectpending == 0) {
37
- return false;
38
- }
39
40
for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) {
41
if (s->vectors[irq].pending) {
42
--
43
2.20.1
44
45
diff view generated by jsdifflib
1
The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of
1
The "expected failure" tests for decodetree result in the
2
the register. We were incorrectly masking it to 8 bits, so it would
2
error messages from decodetree ending up in logs and in
3
report the wrong value if the pending exception was greater than 256.
3
V=1 output:
4
Fix the bug.
4
5
>>> MALLOC_PERTURB_=226 /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/pyvenv/bin/python3 /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/scripts/decodetree.py --output-null --test-for-error /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/../../tests/decode/err_argset1.decode
6
――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――― ✀ ――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――
7
/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/x86/../../tests/decode/err_argset1.decode:5: error: duplicate argument "a"
8
―――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――
9
1/44 qemu:decodetree / err_argset1 OK 0.05s
10
11
This then produces false positives when scanning the
12
logfiles for strings like "error: ".
13
14
For the expected-failure tests, make decodetree print
15
"detected:" instead of "error:".
5
16
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210723162146.5167-6-peter.maydell@linaro.org
20
Message-id: 20230720131521.1325905-1-peter.maydell@linaro.org
9
---
21
---
10
hw/intc/armv7m_nvic.c | 2 +-
22
scripts/decodetree.py | 6 +++++-
11
1 file changed, 1 insertion(+), 1 deletion(-)
23
1 file changed, 5 insertions(+), 1 deletion(-)
12
24
13
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
25
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
14
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/armv7m_nvic.c
27
--- a/scripts/decodetree.py
16
+++ b/hw/intc/armv7m_nvic.c
28
+++ b/scripts/decodetree.py
17
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
29
@@ -XXX,XX +XXX,XX @@ def error_with_file(file, lineno, *args):
18
/* VECTACTIVE */
30
global output_file
19
val = cpu->env.v7m.exception;
31
global output_fd
20
/* VECTPENDING */
32
21
- val |= (s->vectpending & 0xff) << 12;
33
+ # For the test suite expected-errors case, don't print the
22
+ val |= (s->vectpending & 0x1ff) << 12;
34
+ # string "error: ", so they don't turn up as false positives
23
/* ISRPENDING - set if any external IRQ is pending */
35
+ # if you grep the meson logs for strings like that.
24
if (nvic_isrpending(s)) {
36
+ end = 'error: ' if not testforerror else 'detected: '
25
val |= (1 << 22);
37
prefix = ''
38
if file:
39
prefix += f'{file}:'
40
@@ -XXX,XX +XXX,XX @@ def error_with_file(file, lineno, *args):
41
prefix += f'{lineno}:'
42
if prefix:
43
prefix += ' '
44
- print(prefix, end='error: ', file=sys.stderr)
45
+ print(prefix, end=end, file=sys.stderr)
46
print(*args, file=sys.stderr)
47
48
if output_file and output_fd:
26
--
49
--
27
2.20.1
50
2.34.1
28
51
29
52
diff view generated by jsdifflib
Deleted patch
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
2
1
3
Missed in commit f3478392 "docs: Move deprecation, build
4
and license info out of system/"
5
6
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20210723065828.1336760-1-maozhongyi@cmss.chinamobile.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
configure | 2 +-
12
target/i386/cpu.c | 2 +-
13
MAINTAINERS | 2 +-
14
3 files changed, 3 insertions(+), 3 deletions(-)
15
16
diff --git a/configure b/configure
17
index XXXXXXX..XXXXXXX 100755
18
--- a/configure
19
+++ b/configure
20
@@ -XXX,XX +XXX,XX @@ fi
21
22
if test -n "${deprecated_features}"; then
23
echo "Warning, deprecated features enabled."
24
- echo "Please see docs/system/deprecated.rst"
25
+ echo "Please see docs/about/deprecated.rst"
26
echo " features: ${deprecated_features}"
27
fi
28
29
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/i386/cpu.c
32
+++ b/target/i386/cpu.c
33
@@ -XXX,XX +XXX,XX @@ static const X86CPUDefinition builtin_x86_defs[] = {
34
* none", but this is just for compatibility while libvirt isn't
35
* adapted to resolve CPU model versions before creating VMs.
36
* See "Runnability guarantee of CPU models" at
37
- * docs/system/deprecated.rst.
38
+ * docs/about/deprecated.rst.
39
*/
40
X86CPUVersion default_cpu_version = 1;
41
42
diff --git a/MAINTAINERS b/MAINTAINERS
43
index XXXXXXX..XXXXXXX 100644
44
--- a/MAINTAINERS
45
+++ b/MAINTAINERS
46
@@ -XXX,XX +XXX,XX @@ F: contrib/gitdm/*
47
48
Incompatible changes
49
R: libvir-list@redhat.com
50
-F: docs/system/deprecated.rst
51
+F: docs/about/deprecated.rst
52
53
Build System
54
------------
55
--
56
2.20.1
57
58
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Currently, our only caller is sve_zcr_len_for_el, which has
4
already masked the length extracted from ZCR_ELx, so the
5
masking done here is a nop. But we will shortly have uses
6
from other locations, where the length will be unmasked.
7
8
Saturate the length to ARM_MAX_VQ instead of truncating to
9
the low 4 bits.
10
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Message-id: 20210723203344.968563-2-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/helper.c | 4 +++-
17
1 file changed, 3 insertions(+), 1 deletion(-)
18
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
22
+++ b/target/arm/helper.c
23
@@ -XXX,XX +XXX,XX @@ static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
24
{
25
uint32_t end_len;
26
27
- end_len = start_len &= 0xf;
28
+ start_len = MIN(start_len, ARM_MAX_VQ - 1);
29
+ end_len = start_len;
30
+
31
if (!test_bit(start_len, cpu->sve_vq_map)) {
32
end_len = find_last_bit(cpu->sve_vq_map, start_len);
33
assert(end_len < start_len);
34
--
35
2.20.1
36
37
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Rename from sve_zcr_get_valid_len and make accessible
4
from outside of helper.c.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20210723203344.968563-3-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/internals.h | 10 ++++++++++
12
target/arm/helper.c | 4 ++--
13
2 files changed, 12 insertions(+), 2 deletions(-)
14
15
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/internals.h
18
+++ b/target/arm/internals.h
19
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void);
20
void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
21
#endif /* CONFIG_TCG */
22
23
+/**
24
+ * aarch64_sve_zcr_get_valid_len:
25
+ * @cpu: cpu context
26
+ * @start_len: maximum len to consider
27
+ *
28
+ * Return the maximum supported sve vector length <= @start_len.
29
+ * Note that both @start_len and the return value are in units
30
+ * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128.
31
+ */
32
+uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len);
33
34
enum arm_fprounding {
35
FPROUNDING_TIEEVEN,
36
diff --git a/target/arm/helper.c b/target/arm/helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/helper.c
39
+++ b/target/arm/helper.c
40
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
41
return 0;
42
}
43
44
-static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
45
+uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
46
{
47
uint32_t end_len;
48
49
@@ -XXX,XX +XXX,XX @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
50
zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
51
}
52
53
- return sve_zcr_get_valid_len(cpu, zcr_len);
54
+ return aarch64_sve_zcr_get_valid_len(cpu, zcr_len);
55
}
56
57
static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
58
--
59
2.20.1
60
61
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Mirror the behavour of /proc/sys/abi/sve_default_vector_length
4
under the real linux kernel. We have no way of passing along
5
a real default across exec like the kernel can, but this is a
6
decent way of adjusting the startup vector length of a process.
7
8
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/482
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20210723203344.968563-4-richard.henderson@linaro.org
12
[PMM: tweaked docs formatting, document -1 special-case,
13
added fixup patch from RTH mentioning QEMU's maximum veclen.]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
docs/system/arm/cpu-features.rst | 15 ++++++++
17
target/arm/cpu.h | 5 +++
18
target/arm/cpu.c | 14 ++++++--
19
target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++
20
4 files changed, 92 insertions(+), 2 deletions(-)
21
22
diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
23
index XXXXXXX..XXXXXXX 100644
24
--- a/docs/system/arm/cpu-features.rst
25
+++ b/docs/system/arm/cpu-features.rst
26
@@ -XXX,XX +XXX,XX @@ verbose command lines. However, the recommended way to select vector
27
lengths is to explicitly enable each desired length. Therefore only
28
example's (1), (4), and (6) exhibit recommended uses of the properties.
29
30
+SVE User-mode Default Vector Length Property
31
+--------------------------------------------
32
+
33
+For qemu-aarch64, the cpu property ``sve-default-vector-length=N`` is
34
+defined to mirror the Linux kernel parameter file
35
+``/proc/sys/abi/sve_default_vector_length``. The default length, ``N``,
36
+is in units of bytes and must be between 16 and 8192.
37
+If not specified, the default vector length is 64.
38
+
39
+If the default length is larger than the maximum vector length enabled,
40
+the actual vector length will be reduced. Note that the maximum vector
41
+length supported by QEMU is 256.
42
+
43
+If this property is set to ``-1`` then the default vector length
44
+is set to the maximum possible length.
45
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/cpu.h
48
+++ b/target/arm/cpu.h
49
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
50
/* Used to set the maximum vector length the cpu will support. */
51
uint32_t sve_max_vq;
52
53
+#ifdef CONFIG_USER_ONLY
54
+ /* Used to set the default vector length at process start. */
55
+ uint32_t sve_default_vq;
56
+#endif
57
+
58
/*
59
* In sve_vq_map each set bit is a supported vector length of
60
* (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
61
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/arm/cpu.c
64
+++ b/target/arm/cpu.c
65
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
66
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
67
/* with reasonable vector length */
68
if (cpu_isar_feature(aa64_sve, cpu)) {
69
- env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3);
70
+ env->vfp.zcr_el[1] =
71
+ aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1);
72
}
73
/*
74
* Enable TBI0 but not TBI1.
75
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
76
QLIST_INIT(&cpu->pre_el_change_hooks);
77
QLIST_INIT(&cpu->el_change_hooks);
78
79
-#ifndef CONFIG_USER_ONLY
80
+#ifdef CONFIG_USER_ONLY
81
+# ifdef TARGET_AARCH64
82
+ /*
83
+ * The linux kernel defaults to 512-bit vectors, when sve is supported.
84
+ * See documentation for /proc/sys/abi/sve_default_vector_length, and
85
+ * our corresponding sve-default-vector-length cpu property.
86
+ */
87
+ cpu->sve_default_vq = 4;
88
+# endif
89
+#else
90
/* Our inbound IRQ and FIQ lines */
91
if (kvm_enabled()) {
92
/* VIRQ and VFIQ are unused with KVM but we add them to maintain
93
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
94
index XXXXXXX..XXXXXXX 100644
95
--- a/target/arm/cpu64.c
96
+++ b/target/arm/cpu64.c
97
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)
98
cpu->isar.id_aa64pfr0 = t;
99
}
100
101
+#ifdef CONFIG_USER_ONLY
102
+/* Mirror linux /proc/sys/abi/sve_default_vector_length. */
103
+static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v,
104
+ const char *name, void *opaque,
105
+ Error **errp)
106
+{
107
+ ARMCPU *cpu = ARM_CPU(obj);
108
+ int32_t default_len, default_vq, remainder;
109
+
110
+ if (!visit_type_int32(v, name, &default_len, errp)) {
111
+ return;
112
+ }
113
+
114
+ /* Undocumented, but the kernel allows -1 to indicate "maximum". */
115
+ if (default_len == -1) {
116
+ cpu->sve_default_vq = ARM_MAX_VQ;
117
+ return;
118
+ }
119
+
120
+ default_vq = default_len / 16;
121
+ remainder = default_len % 16;
122
+
123
+ /*
124
+ * Note that the 512 max comes from include/uapi/asm/sve_context.h
125
+ * and is the maximum architectural width of ZCR_ELx.LEN.
126
+ */
127
+ if (remainder || default_vq < 1 || default_vq > 512) {
128
+ error_setg(errp, "cannot set sve-default-vector-length");
129
+ if (remainder) {
130
+ error_append_hint(errp, "Vector length not a multiple of 16\n");
131
+ } else if (default_vq < 1) {
132
+ error_append_hint(errp, "Vector length smaller than 16\n");
133
+ } else {
134
+ error_append_hint(errp, "Vector length larger than %d\n",
135
+ 512 * 16);
136
+ }
137
+ return;
138
+ }
139
+
140
+ cpu->sve_default_vq = default_vq;
141
+}
142
+
143
+static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v,
144
+ const char *name, void *opaque,
145
+ Error **errp)
146
+{
147
+ ARMCPU *cpu = ARM_CPU(obj);
148
+ int32_t value = cpu->sve_default_vq * 16;
149
+
150
+ visit_type_int32(v, name, &value, errp);
151
+}
152
+#endif
153
+
154
void aarch64_add_sve_properties(Object *obj)
155
{
156
uint32_t vq;
157
@@ -XXX,XX +XXX,XX @@ void aarch64_add_sve_properties(Object *obj)
158
object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
159
cpu_arm_set_sve_vq, NULL, NULL);
160
}
161
+
162
+#ifdef CONFIG_USER_ONLY
163
+ /* Mirror linux /proc/sys/abi/sve_default_vector_length. */
164
+ object_property_add(obj, "sve-default-vector-length", "int32",
165
+ cpu_arm_get_sve_default_vec_len,
166
+ cpu_arm_set_sve_default_vec_len, NULL, NULL);
167
+#endif
168
}
169
170
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
171
--
172
2.20.1
173
174
diff view generated by jsdifflib