arm pullreq for rc1. All minor bugfixes, except for the sve-default-vector-length

patches, which are somewhere between a bugfix and a new feature.

The following changes since commit c08ccd1b53f488ac86c1f65cf7623dc91acc249a:

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210726' into staging (2021-07-27 08:35:01 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210727

for you to fetch changes up to e229a179a503f2aee43a76888cf12fbdfe8a3749:

hw: aspeed_gpio: Fix memory size (2021-07-27 11:00:00 +0100)

* hw/arm/smmuv3: Check 31st bit to see if CD is valid

* qemu-options.hx: Fix formatting of -machine memory-backend option

* hw: aspeed_gpio: Fix memory size

* hw/arm/nseries: Display hexadecimal value with '0x' prefix

* Add sve-default-vector-length cpu property

* docs: Update path that mentions deprecated.rst

* hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS

* hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING

* hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts

* target/arm: Report M-profile alignment faults correctly to the guest

* target/arm: Add missing 'return's after calling v7m_exception_taken()

* target/arm: Enforce that M-profile SP low 2 bits are always zero

Joe Komlodi (1):

hw/arm/smmuv3: Check 31st bit to see if CD is valid

Joel Stanley (1):

hw: aspeed_gpio: Fix memory size

Mao Zhongyi (1):

docs: Update path that mentions deprecated.rst

Peter Maydell (7):

qemu-options.hx: Fix formatting of -machine memory-backend option

target/arm: Enforce that M-profile SP low 2 bits are always zero

target/arm: Add missing 'return's after calling v7m_exception_taken()

target/arm: Report M-profile alignment faults correctly to the guest

hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts

hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING

hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS

Philippe Mathieu-Daudé (1):

hw/arm/nseries: Display hexadecimal value with '0x' prefix

Richard Henderson (3):

target/arm: Correctly bound length in sve_zcr_get_valid_len

target/arm: Export aarch64_sve_zcr_get_valid_len

target/arm: Add sve-default-vector-length cpu property

docs/system/arm/cpu-features.rst | 15 ++++++++++

configure | 2 +-

hw/arm/smmuv3-internal.h | 2 +-

target/arm/cpu.h | 5 ++++

target/arm/internals.h | 10 +++++++

hw/arm/nseries.c | 2 +-

hw/gpio/aspeed_gpio.c | 3 +-

hw/intc/armv7m_nvic.c | 40 +++++++++++++++++++--------

target/arm/cpu.c | 14 ++++++++--

target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++++++++++

target/arm/gdbstub.c | 4 +++

target/arm/helper.c | 8 ++++--

target/arm/m_helper.c | 24 ++++++++++++----

target/arm/translate.c | 3 ++

target/i386/cpu.c | 2 +-

MAINTAINERS | 2 +-

qemu-options.hx | 30 +++++++++++---------

17 files changed, 183 insertions(+), 43 deletions(-)

From: Joel Stanley <joel@jms.id.au>

The macro used to calculate the maximum memory size of the MMIO region

had a mistake, causing all GPIO models to create a mapping of 0x9D8.

The intent was to have it be 0x9D8 - 0x800.

This extra size doesn't matter on ast2400 and ast2500, which have a 4KB

region set aside for the GPIO controller.

On the ast2600 the 3.3V and 1.8V GPIO controllers are 2KB apart, so the

regions would overlap. Worse was the 1.8V controller would map over the

top of the following peripheral, which happens to be the RTC.

The mmio region used by each device is a maximum of 2KB, so avoid the

calculations and hard code this as the maximum.

Fixes: 36d737ee82b2 ("hw/gpio: Add in AST2600 specific implementation")

Signed-off-by: Joel Stanley <joel@jms.id.au>

Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Message-id: 20210713065854.134634-2-joel@jms.id.au

[PMM: fix autocorrect error in commit message]

hw/gpio/aspeed_gpio.c | 3 +--

1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/gpio/aspeed_gpio.c

+++ b/hw/gpio/aspeed_gpio.c

@@ -XXX,XX +XXX,XX @@

#define GPIO_1_8V_MEM_SIZE 0x9D8

#define GPIO_1_8V_REG_ARRAY_SIZE ((GPIO_1_8V_MEM_SIZE - \

GPIO_1_8V_REG_OFFSET) >> 2)

-#define GPIO_MAX_MEM_SIZE MAX(GPIO_3_6V_MEM_SIZE, GPIO_1_8V_MEM_SIZE)

static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio)

{

@@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_realize(DeviceState *dev, Error **errp)

}

memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s,

- TYPE_ASPEED_GPIO, GPIO_MAX_MEM_SIZE);

+ TYPE_ASPEED_GPIO, 0x800);

sysbus_init_mmio(sbd, &s->iomem);

}

2.20.1

Currently, our only caller is sve_zcr_len_for_el, which has

already masked the length extracted from ZCR_ELx, so the

masking done here is a nop. But we will shortly have uses

from other locations, where the length will be unmasked.

Saturate the length to ARM_MAX_VQ instead of truncating to

the low 4 bits.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20210723203344.968563-2-richard.henderson@linaro.org

target/arm/helper.c | 4 +++-

1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)

{

uint32_t end_len;

- end_len = start_len &= 0xf;

+ start_len = MIN(start_len, ARM_MAX_VQ - 1);

+ end_len = start_len;

+

if (!test_bit(start_len, cpu->sve_vq_map)) {

end_len = find_last_bit(cpu->sve_vq_map, start_len);

assert(end_len < start_len);

2.20.1

The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of

the register. We were incorrectly masking it to 8 bits, so it would

report the wrong value if the pending exception was greater than 256.

Fix the bug.

Message-id: 20210723162146.5167-6-peter.maydell@linaro.org

hw/intc/armv7m_nvic.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

/* VECTACTIVE */

val = cpu->env.v7m.exception;

/* VECTPENDING */

- val |= (s->vectpending & 0xff) << 12;

+ val |= (s->vectpending & 0x1ff) << 12;

/* ISRPENDING - set if any external IRQ is pending */

if (nvic_isrpending(s)) {

val |= (1 << 22);

2.20.1

In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if

the register is accessed NonSecure and the highest priority pending

enabled exception (that would be returned in the VECTPENDING field)

targets Secure, then the VECTPENDING field must read 1 rather than

the exception number of the pending exception. Implement this.

Message-id: 20210723162146.5167-7-peter.maydell@linaro.org

hw/intc/armv7m_nvic.c | 31 ++++++++++++++++++++++++-------

1 file changed, 24 insertions(+), 7 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)

nvic_irq_update(s);

+static bool vectpending_targets_secure(NVICState *s)

+ /* Return true if s->vectpending targets Secure state */

+ if (s->vectpending_is_s_banked) {

+ return true;

+ return !exc_is_banked(s->vectpending) &&

+ exc_targets_secure(s, s->vectpending);

void armv7m_nvic_get_pending_irq_info(void *opaque,

int *pirq, bool *ptargets_secure)

@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,

assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);

- if (s->vectpending_is_s_banked) {

- targets_secure = true;

- targets_secure = !exc_is_banked(pending) &&

- exc_targets_secure(s, pending);

+ targets_secure = vectpending_targets_secure(s);

trace_nvic_get_pending_irq_info(pending, targets_secure);

@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)

/* VECTACTIVE */

val = cpu->env.v7m.exception;

/* VECTPENDING */

- val |= (s->vectpending & 0x1ff) << 12;

+ if (s->vectpending) {

+ /*

+ * From v8.1M VECTPENDING must read as 1 if accessed as

+ * NonSecure and the highest priority pending and enabled

+ * exception targets Secure.

+ */

+ int vp = s->vectpending;

+ if (!attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_V8_1M) &&

+ vectpending_targets_secure(s)) {

+ vp = 1;

+ }

+ val |= (vp & 0x1ff) << 12;

+ }

/* ISRPENDING - set if any external IRQ is pending */

if (nvic_isrpending(s)) {

val |= (1 << 22);

2.20.1

From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>

Missed in commit f3478392 "docs: Move deprecation, build

and license info out of system/"

Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20210723065828.1336760-1-maozhongyi@cmss.chinamobile.com

configure | 2 +-

target/i386/cpu.c | 2 +-

MAINTAINERS | 2 +-

3 files changed, 3 insertions(+), 3 deletions(-)

@@ -XXX,XX +XXX,XX @@ F: contrib/gitdm/*

Incompatible changes

R: libvir-list@redhat.com

-F: docs/system/deprecated.rst

+F: docs/about/deprecated.rst

Build System

------------

2.20.1

The ISCR.ISRPENDING bit is set when an external interrupt is pending.

This is true whether that external interrupt is enabled or not.

This means that we can't use 's->vectpending == 0' as a shortcut to

"ISRPENDING is zero", because s->vectpending indicates only the

highest priority pending enabled interrupt.

Remove the incorrect optimization so that if there is no pending

enabled interrupt we fall through to scanning through the whole

interrupt array.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210723162146.5167-5-peter.maydell@linaro.org

hw/intc/armv7m_nvic.c | 9 ++++-----

1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c

--- a/hw/intc/armv7m_nvic.c

+++ b/hw/intc/armv7m_nvic.c

@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)

{

int irq;

- /* We can shortcut if the highest priority pending interrupt

- * happens to be external or if there is nothing pending.

+ /*

+ * We can shortcut if the highest priority pending interrupt

+ * happens to be external; if not we need to check the whole

+ * vectors[] array.

*/

if (s->vectpending > NVIC_FIRST_IRQ) {

return true;

}

- if (s->vectpending == 0) {

- return false;

- }

for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) {

if (s->vectors[irq].pending) {

2.20.1

For M-profile, we weren't reporting alignment faults triggered by the

generic TCG code correctly to the guest. These get passed into

arm_v7m_cpu_do_interrupt() as an EXCP_DATA_ABORT with an A-profile

style exception.fsr value of 1. We didn't check for this, and so

they fell through into the default of "assume this is an MPU fault"

and were reported to the guest as a data access violation MPU fault.

Report these alignment faults as UsageFaults which set the UNALIGNED

bit in the UFSR.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210723162146.5167-4-peter.maydell@linaro.org

target/arm/m_helper.c | 8 ++++++++

1 file changed, 8 insertions(+)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c

--- a/target/arm/m_helper.c

+++ b/target/arm/m_helper.c

@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)

env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK;

break;

case EXCP_UNALIGNED:

+ /* Unaligned faults reported by M-profile aware code */

armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);

env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;

break;

@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)

}

armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);

break;

+ case 0x1: /* Alignment fault reported by generic code */

+ qemu_log_mask(CPU_LOG_INT,

+ "...really UsageFault with UFSR.UNALIGNED\n");

+ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;

+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,

+ env->v7m.secure);

+ break;

default:

/*

* All other FSR values are either MPU faults or "can't happen

2.20.1

In do_v7m_exception_exit(), we perform various checks as part of

performing the exception return. If one of these checks fails, the

architecture requires that we take an appropriate exception on the

existing stackframe. We implement this by calling

v7m_exception_taken() to set up to take the new exception, and then

immediately returning from do_v7m_exception_exit() without proceeding

any further with the unstack-and-exception-return process.

In a couple of checks that are new in v8.1M, we forgot the "return"

statement, with the effect that if bad code in the guest tripped over

these checks we would set up to take a UsageFault exception but then

blunder on trying to also unstack and return from the original

exception, with the probable result that the guest would crash.

Add the missing return statements.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210723162146.5167-3-peter.maydell@linaro.org

target/arm/m_helper.c | 2 ++

1 file changed, 2 insertions(+)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c

--- a/target/arm/m_helper.c

+++ b/target/arm/m_helper.c

@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)

qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "

"stackframe: NSACR prevents clearing FPU registers\n");

v7m_exception_taken(cpu, excret, true, false);

+ return;

} else if (!cpacr_pass) {

armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,

exc_secure);

@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)

qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "

"stackframe: CPACR prevents clearing FPU registers\n");

v7m_exception_taken(cpu, excret, true, false);

+ return;

}

}

/* Clear s0..s15, FPSCR and VPR */

2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20210726150953.1218690-1-f4bug@amsat.org

hw/arm/nseries.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c

--- a/hw/arm/nseries.c

+++ b/hw/arm/nseries.c

@@ -XXX,XX +XXX,XX @@ static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)

default:

bad_cmd:

qemu_log_mask(LOG_GUEST_ERROR,

- "%s: unknown command %02x\n", __func__, s->cmd);

+ "%s: unknown command 0x%02x\n", __func__, s->cmd);

break;

}

2.20.1

From: Joe Komlodi <joe.komlodi@xilinx.com>

The bit to see if a CD is valid is the last bit of the first word of the CD.

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>

Message-id: 1626728232-134665-2-git-send-email-joe.komlodi@xilinx.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

hw/arm/smmuv3-internal.h | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h

--- a/hw/arm/smmuv3-internal.h

+++ b/hw/arm/smmuv3-internal.h

@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)

/* CD fields */

-#define CD_VALID(x) extract32((x)->word[0], 30, 1)

+#define CD_VALID(x) extract32((x)->word[0], 31, 1)

#define CD_ASID(x) extract32((x)->word[1], 16, 16)

#define CD_TTB(x, sel) \

({ \

2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Mirror the behavour of /proc/sys/abi/sve_default_vector_length

under the real linux kernel. We have no way of passing along

a real default across exec like the kernel can, but this is a

decent way of adjusting the startup vector length of a process.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/482

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20210723203344.968563-4-richard.henderson@linaro.org

[PMM: tweaked docs formatting, document -1 special-case,

added fixup patch from RTH mentioning QEMU's maximum veclen.]

docs/system/arm/cpu-features.rst | 15 ++++++++

target/arm/cpu.h | 5 +++

target/arm/cpu.c | 14 ++++++--

target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++

4 files changed, 92 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst

--- a/docs/system/arm/cpu-features.rst

+++ b/docs/system/arm/cpu-features.rst

@@ -XXX,XX +XXX,XX @@ verbose command lines. However, the recommended way to select vector

lengths is to explicitly enable each desired length. Therefore only

example's (1), (4), and (6) exhibit recommended uses of the properties.

+SVE User-mode Default Vector Length Property

+--------------------------------------------

+

+For qemu-aarch64, the cpu property ``sve-default-vector-length=N`` is

+defined to mirror the Linux kernel parameter file

+``/proc/sys/abi/sve_default_vector_length``. The default length, ``N``,

+is in units of bytes and must be between 16 and 8192.

+If not specified, the default vector length is 64.

+

+If the default length is larger than the maximum vector length enabled,

+the actual vector length will be reduced. Note that the maximum vector

+length supported by QEMU is 256.

+

+If this property is set to ``-1`` then the default vector length

+is set to the maximum possible length.

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ struct ARMCPU {

/* Used to set the maximum vector length the cpu will support. */

uint32_t sve_max_vq;

+#ifdef CONFIG_USER_ONLY

+ /* Used to set the default vector length at process start. */

+ uint32_t sve_default_vq;

+#endif

+

/*

* In sve_vq_map each set bit is a supported vector length of

* (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)

env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);

/* with reasonable vector length */

if (cpu_isar_feature(aa64_sve, cpu)) {

- env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3);

+ env->vfp.zcr_el[1] =

+ aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1);

}

/*

* Enable TBI0 but not TBI1.

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)

QLIST_INIT(&cpu->pre_el_change_hooks);

QLIST_INIT(&cpu->el_change_hooks);

-#ifndef CONFIG_USER_ONLY

+#ifdef CONFIG_USER_ONLY

+# ifdef TARGET_AARCH64

+ /*

+ * The linux kernel defaults to 512-bit vectors, when sve is supported.

+ * See documentation for /proc/sys/abi/sve_default_vector_length, and

+ * our corresponding sve-default-vector-length cpu property.

+ */

+ cpu->sve_default_vq = 4;

+# endif

+#else

/* Our inbound IRQ and FIQ lines */

if (kvm_enabled()) {

/* VIRQ and VFIQ are unused with KVM but we add them to maintain

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)

cpu->isar.id_aa64pfr0 = t;

}

+#ifdef CONFIG_USER_ONLY

+/* Mirror linux /proc/sys/abi/sve_default_vector_length. */

+static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v,

+ const char *name, void *opaque,

+ Error **errp)

+{

+ ARMCPU *cpu = ARM_CPU(obj);

+ int32_t default_len, default_vq, remainder;

+

+ if (!visit_type_int32(v, name, &default_len, errp)) {

+ /* Undocumented, but the kernel allows -1 to indicate "maximum". */

+ if (default_len == -1) {

+ cpu->sve_default_vq = ARM_MAX_VQ;

+ default_vq = default_len / 16;

+ remainder = default_len % 16;

+

+ /*

+ * Note that the 512 max comes from include/uapi/asm/sve_context.h

+ * and is the maximum architectural width of ZCR_ELx.LEN.

+ */

+ if (remainder || default_vq < 1 || default_vq > 512) {

+ error_setg(errp, "cannot set sve-default-vector-length");

+ if (remainder) {

+ error_append_hint(errp, "Vector length not a multiple of 16\n");

+ } else if (default_vq < 1) {

+ error_append_hint(errp, "Vector length smaller than 16\n");

+ } else {

+ error_append_hint(errp, "Vector length larger than %d\n",

+ 512 * 16);

+ }

+ return;

+ }

+

+ cpu->sve_default_vq = default_vq;

+}

+

+static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v,

+ const char *name, void *opaque,

+ Error **errp)

+{

+ ARMCPU *cpu = ARM_CPU(obj);

+ int32_t value = cpu->sve_default_vq * 16;

+

+ visit_type_int32(v, name, &value, errp);

+}

+#endif

+

void aarch64_add_sve_properties(Object *obj)

{

uint32_t vq;

@@ -XXX,XX +XXX,XX @@ void aarch64_add_sve_properties(Object *obj)

object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,

cpu_arm_set_sve_vq, NULL, NULL);

}

+

+#ifdef CONFIG_USER_ONLY

+ /* Mirror linux /proc/sys/abi/sve_default_vector_length. */

+ object_property_add(obj, "sve-default-vector-length", "int32",

+ cpu_arm_get_sve_default_vec_len,

+ cpu_arm_set_sve_default_vec_len, NULL, NULL);

+#endif

}

void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)

2.20.1