Series comparison

-[PULL 00/14] target-arm queue
+[PULL 00/21] target-arm queue
-arm pullreq for rc1. All minor bugfixes, except for the sve-default-vector-length
+The following changes since commit f003dd8d81f7d88f4b1f8802309eaa76f6eb223a:
 patches, which are somewhere between a bugfix and a new feature.
-thanks
+  Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging (2023-03-06 10:20:04 +0000)
 -- PMM
 The following changes since commit c08ccd1b53f488ac86c1f65cf7623dc91acc249a:
   Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210726' into staging (2021-07-27 08:35:01 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210727
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230306
-for you to fetch changes up to e229a179a503f2aee43a76888cf12fbdfe8a3749:
+for you to fetch changes up to 2ddc45954f97cd1d7ee5cbca0def05e980d1da9f:
-  hw: aspeed_gpio: Fix memory size (2021-07-27 11:00:00 +0100)
+  hw: arm: allwinner-h3: Fix and complete H3 i2c devices (2023-03-06 15:31:24 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * hw/arm/smmuv3: Check 31st bit to see if CD is valid
+ * allwinner-h3: Fix I2C controller model for Sun6i SoCs
- * qemu-options.hx: Fix formatting of -machine memory-backend option
+ * allwinner-h3: Add missing i2c controllers
- * hw: aspeed_gpio: Fix memory size
+ * Expose M-profile system registers to gdbstub
- * hw/arm/nseries: Display hexadecimal value with '0x' prefix
+ * Expose pauth information to gdbstub
- * Add sve-default-vector-length cpu property
+ * Support direct boot for Linux/arm64 EFI zboot images
- * docs: Update path that mentions deprecated.rst
+ * Fix incorrect stage 2 MMU setup validation
  * hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
  * hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
  * hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
  * target/arm: Report M-profile alignment faults correctly to the guest
  * target/arm: Add missing 'return's after calling v7m_exception_taken()
  * target/arm: Enforce that M-profile SP low 2 bits are always zero
 ----------------------------------------------------------------
-Joe Komlodi (1):
+Ard Biesheuvel (1):
-      hw/arm/smmuv3: Check 31st bit to see if CD is valid
+      hw: arm: Support direct boot for Linux/arm64 EFI zboot images
-Joel Stanley (1):
+David Reiss (2):
-      hw: aspeed_gpio: Fix memory size
+      target/arm: Export arm_v7m_mrs_control
       target/arm: Export arm_v7m_get_sp_ptr
-Mao Zhongyi (1):
+Richard Henderson (16):
-      docs: Update path that mentions deprecated.rst
+      target/arm: Normalize aarch64 gdbstub get/set function names
       target/arm: Unexport arm_gen_dynamic_sysreg_xml
       target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
       target/arm: Split out output_vector_union_type
       target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
       target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
       target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
       target/arm: Add name argument to output_vector_union_type
       target/arm: Simplify iteration over bit widths
       target/arm: Create pauth_ptr_mask
       target/arm: Implement gdbstub pauth extension
       target/arm: Implement gdbstub m-profile systemreg and secext
       target/arm: Handle m-profile in arm_is_secure
       target/arm: Stub arm_hcr_el2_eff for m-profile
       target/arm: Diagnose incorrect usage of arm_is_secure subroutines
       target/arm: Rewrite check_s2_mmu_setup
-Peter Maydell (7):
+qianfan Zhao (2):
-      qemu-options.hx: Fix formatting of -machine memory-backend option
+      hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
-      target/arm: Enforce that M-profile SP low 2 bits are always zero
+      hw: arm: allwinner-h3: Fix and complete H3 i2c devices
       target/arm: Add missing 'return's after calling v7m_exception_taken()
       target/arm: Report M-profile alignment faults correctly to the guest
       hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
       hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
       hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
-Philippe Mathieu-Daudé (1):
+ configs/targets/aarch64-linux-user.mak    |   2 +-
-      hw/arm/nseries: Display hexadecimal value with '0x' prefix
+ configs/targets/aarch64-softmmu.mak       |   2 +-
+ configs/targets/aarch64_be-linux-user.mak |   2 +-
-Richard Henderson (3):
+ include/hw/arm/allwinner-h3.h             |   6 +
-      target/arm: Correctly bound length in sve_zcr_get_valid_len
+ include/hw/i2c/allwinner-i2c.h            |   6 +
-      target/arm: Export aarch64_sve_zcr_get_valid_len
+ include/hw/loader.h                       |  19 ++
-      target/arm: Add sve-default-vector-length cpu property
+ target/arm/cpu.h                          |  17 +-
+ target/arm/internals.h                    |  34 +++-
- docs/system/arm/cpu-features.rst | 15 ++++++++++
+ hw/arm/allwinner-h3.c                     |  29 +++-
- configure                        |  2 +-
+ hw/arm/boot.c                             |   6 +
- hw/arm/smmuv3-internal.h         |  2 +-
+ hw/core/loader.c                          |  91 ++++++++++
- target/arm/cpu.h                 |  5 ++++
+ hw/i2c/allwinner-i2c.c                    |  26 ++-
- target/arm/internals.h           | 10 +++++++
+ target/arm/gdbstub.c                      | 278 ++++++++++++++++++------------
- hw/arm/nseries.c                 |  2 +-
+ target/arm/gdbstub64.c                    | 175 ++++++++++++++++++-
- hw/gpio/aspeed_gpio.c            |  3 +-
+ target/arm/helper.c                       |   3 +
- hw/intc/armv7m_nvic.c            | 40 +++++++++++++++++++--------
+ target/arm/ptw.c                          | 173 +++++++++++--------
- target/arm/cpu.c                 | 14 ++++++++--
+ target/arm/tcg/m_helper.c                 |  90 +++++-----
- target/arm/cpu64.c               | 60 ++++++++++++++++++++++++++++++++++++++++
+ target/arm/tcg/pauth_helper.c             |  26 ++-
- target/arm/gdbstub.c             |  4 +++
+ gdb-xml/aarch64-pauth.xml                 |  15 ++
- target/arm/helper.c              |  8 ++++--
+files changed, 742 insertions(+), 258 deletions(-)
- target/arm/m_helper.c            | 24 ++++++++++++----
+ create mode 100644 gdb-xml/aarch64-pauth.xml
  target/arm/translate.c           |  3 ++
  target/i386/cpu.c                |  2 +-
  MAINTAINERS                      |  2 +-
  qemu-options.hx                  | 30 +++++++++++---------
 files changed, 183 insertions(+), 43 deletions(-)

-[PULL 11/14] target/arm: Export aarch64_sve_zcr_get_valid_len
+[PULL 01/21] target/arm: Normalize aarch64 gdbstub get/set function names
 From: Richard Henderson <richard.henderson@linaro.org>
-Rename from sve_zcr_get_valid_len and make accessible
+Make the form of the function names between fp and sve the same:
-from outside of helper.c.
+  - arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg.
   - aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg.
+Reviewed-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230227213329.793795-2-richard.henderson@linaro.org
 Message-id: 20210723203344.968563-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/internals.h | 10 ++++++++++
+ target/arm/internals.h | 8 ++++----
- target/arm/helper.c    |  4 ++--
+ target/arm/gdbstub.c   | 9 +++++----
-files changed, 12 insertions(+), 2 deletions(-)
+ target/arm/gdbstub64.c | 8 ++++----
 files changed, 13 insertions(+), 12 deletions(-)
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void);
+@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
- void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
+ }
- #endif /* CONFIG_TCG */
+ #ifdef TARGET_AARCH64
-+/**
+-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);
-+ * aarch64_sve_zcr_get_valid_len:
+-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);
-+ * @cpu: cpu context
+-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
-+ * @start_len: maximum len to consider
+-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
-+ *
++int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
-+ * Return the maximum supported sve vector length <= @start_len.
++int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
-+ * Note that both @start_len and the return value are in units
++int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
-+ * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128.
++int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
-+ */
+ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
-+uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len);
+ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
+ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
- enum arm_fprounding {
+diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
      FPROUNDING_TIEEVEN,
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/target/arm/gdbstub.c
-+++ b/target/arm/helper.c
++++ b/target/arm/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
           */
  #ifdef TARGET_AARCH64
          if (isar_feature_aa64_sve(&cpu->isar)) {
 -            gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
 -                                     arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
 +            int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs);
 +            gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
 +                                     aarch64_gdb_set_sve_reg, nreg,
                                       "sve-registers.xml", 0);
          } else {
 -            gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
 -                                     aarch64_fpu_gdb_set_reg,
 +            gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,
 +                                     aarch64_gdb_set_fpu_reg,
 , "aarch64-fpu.xml", 0);
          }
  #endif
 diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub64.c
 +++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
      return 0;
  }
--static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
+-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
-+uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
++int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)
  {
-     uint32_t end_len;
+     switch (reg) {
+     case 0 ... 31:
-@@ -XXX,XX +XXX,XX @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
+@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
          zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
      }
--    return sve_zcr_get_valid_len(cpu, zcr_len);
-+    return aarch64_sve_zcr_get_valid_len(cpu, zcr_len);
  }
- static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 +int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)
  {
      switch (reg) {
      case 0 ... 31:
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
      }
  }
 -int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
 +int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)
  {
      ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
      return 0;
  }
 -int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
 +int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
  {
      ARMCPU *cpu = env_archcpu(env);
 --
-.20.1
+.34.1

-[PULL 03/14] target/arm: Enforce that M-profile SP low 2 bits are always zero
+[PULL 02/21] target/arm: Unexport arm_gen_dynamic_sysreg_xml
-For M-profile, unlike A-profile, the low 2 bits of SP are defined to be
+From: Richard Henderson <richard.henderson@linaro.org>
 RES0H, which is to say that they must be hardwired to zero so that
 guest attempts to write non-zero values to them are ignored.
-Implement this behaviour by masking out the low bits:
+This function is not used outside gdbstub.c.
  * for writes to r13 by the gdbstub
  * for writes to any of the various flavours of SP via MSR
  * for writes to r13 via store_reg() in generated code
-Note that all the direct uses of cpu_R[] in translate.c are in places
+Reviewed-by: Fabiano Rosas <farosas@suse.de>
-where the register is definitely not r13 (usually because that has
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-been checked for as an UNDEFINED or UNPREDICTABLE case and handled as
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-UNDEF).
+Message-id: 20230227213329.793795-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h     | 1 -
  target/arm/gdbstub.c | 2 +-
 files changed, 1 insertion(+), 2 deletions(-)
-All the other writes to regs[13] in C code are either:
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
- * A-profile only code
+index XXXXXXX..XXXXXXX 100644
- * writes of values we can guarantee to be aligned, such as
+--- a/target/arm/cpu.h
-   - writes of previous-SP-value plus or minus a 4-aligned constant
++++ b/target/arm/cpu.h
-   - writes of the value in an SP limit register (which we already
+@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-     enforce to be aligned)
+  * Helpers to dynamically generates XML descriptions of the sysregs
+  * and SVE registers. Returns the number of registers in each set.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+  */
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+-int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
-Message-id: 20210723162146.5167-2-peter.maydell@linaro.org
+ int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
----
- target/arm/gdbstub.c   |  4 ++++
+ /* Returns the dynamically generated XML for the gdb stub.
  target/arm/m_helper.c  | 14 ++++++++------
  target/arm/translate.c |  3 +++
 files changed, 15 insertions(+), 6 deletions(-)
 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub.c
 +++ b/target/arm/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+@@ -XXX,XX +XXX,XX @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
      if (n < 16) {
          /* Core integer register.  */
 +        if (n == 13 && arm_feature(env, ARM_FEATURE_M)) {
 +            /* M profile SP low bits are always 0 */
 +            tmp &= ~3;
 +        }
          env->regs[n] = tmp;
          return 4;
      }
-diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
+ }
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/m_helper.c
+-int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
-+++ b/target/arm/m_helper.c
++static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
-@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
+ {
-             if (!env->v7m.secure) {
+     ARMCPU *cpu = ARM_CPU(cs);
-                 return;
+     GString *s = g_string_new(NULL);
              }
 -            env->v7m.other_ss_msp = val;
 +            env->v7m.other_ss_msp = val & ~3;
              return;
          case 0x89: /* PSP_NS */
              if (!env->v7m.secure) {
                  return;
              }
 -            env->v7m.other_ss_psp = val;
 +            env->v7m.other_ss_psp = val & ~3;
              return;
          case 0x8a: /* MSPLIM_NS */
              if (!env->v7m.secure) {
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
              limit = is_psp ? env->v7m.psplim[false] : env->v7m.msplim[false];
 +            val &= ~0x3;
 +
              if (val < limit) {
                  raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC());
              }
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
          break;
      case 8: /* MSP */
          if (v7m_using_psp(env)) {
 -            env->v7m.other_sp = val;
 +            env->v7m.other_sp = val & ~3;
          } else {
 -            env->regs[13] = val;
 +            env->regs[13] = val & ~3;
          }
          break;
      case 9: /* PSP */
          if (v7m_using_psp(env)) {
 -            env->regs[13] = val;
 +            env->regs[13] = val & ~3;
          } else {
 -            env->v7m.other_sp = val;
 +            env->v7m.other_sp = val & ~3;
          }
          break;
      case 10: /* MSPLIM */
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void store_reg(DisasContext *s, int reg, TCGv_i32 var)
           */
          tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3);
          s->base.is_jmp = DISAS_JUMP;
 +    } else if (reg == 13 && arm_dc_feature(s, ARM_FEATURE_M)) {
 +        /* For M-profile SP bits [1:0] are always zero */
 +        tcg_gen_andi_i32(var, var, ~3);
      }
      tcg_gen_mov_i32(cpu_R[reg], var);
      tcg_temp_free_i32(var);
 --
-.20.1
+.34.1

-New patch
+[PULL 03/21] target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
+From: Richard Henderson <richard.henderson@linaro.org>
 The function is only used for aarch64, so move it to the
 file that has the other aarch64 gdbstub stuff.  Move the
 declaration to internals.h.
 Reviewed-by: Fabiano Rosas <farosas@suse.de>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230227213329.793795-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h       |   6 ---
  target/arm/internals.h |   1 +
  target/arm/gdbstub.c   | 120 -----------------------------------------
  target/arm/gdbstub64.c | 118 ++++++++++++++++++++++++++++++++++++++++
 files changed, 119 insertions(+), 126 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
  int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
  int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 -/*
 - * Helpers to dynamically generates XML descriptions of the sysregs
 - * and SVE registers. Returns the number of registers in each set.
 - */
 -int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
 -
  /* Returns the dynamically generated XML for the gdb stub.
   * Returns a pointer to the XML contents for the specified XML file or NULL
   * if the XML name doesn't match the predefined one.
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
  }
  #ifdef TARGET_AARCH64
 +int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
  int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
  int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
  int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub.c
 +++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
      return cpu->dyn_sysreg_xml.num;
  }
 -struct TypeSize {
 -    const char *gdb_type;
 -    int  size;
 -    const char sz, suffix;
 -};
 -
 -static const struct TypeSize vec_lanes[] = {
 -    /* quads */
 -    { "uint128", 128, 'q', 'u' },
 -    { "int128", 128, 'q', 's' },
 -    /* 64 bit */
 -    { "ieee_double", 64, 'd', 'f' },
 -    { "uint64", 64, 'd', 'u' },
 -    { "int64", 64, 'd', 's' },
 -    /* 32 bit */
 -    { "ieee_single", 32, 's', 'f' },
 -    { "uint32", 32, 's', 'u' },
 -    { "int32", 32, 's', 's' },
 -    /* 16 bit */
 -    { "ieee_half", 16, 'h', 'f' },
 -    { "uint16", 16, 'h', 'u' },
 -    { "int16", 16, 'h', 's' },
 -    /* bytes */
 -    { "uint8", 8, 'b', 'u' },
 -    { "int8", 8, 'b', 's' },
 -};
 -
 -
 -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
 -{
 -    ARMCPU *cpu = ARM_CPU(cs);
 -    GString *s = g_string_new(NULL);
 -    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
 -    g_autoptr(GString) ts = g_string_new("");
 -    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
 -    info->num = 0;
 -    g_string_printf(s, "<?xml version=\"1.0\"?>");
 -    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 -    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 -
 -    /* First define types and totals in a whole VL */
 -    for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 -        int count = reg_width / vec_lanes[i].size;
 -        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
 -        g_string_append_printf(s,
 -                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
 -                               ts->str, vec_lanes[i].gdb_type, count);
 -    }
 -    /*
 -     * Now define a union for each size group containing unsigned and
 -     * signed and potentially float versions of each size from 128 to
 -     * 8 bits.
 -     */
 -    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 -        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
 -        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
 -        for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
 -            if (vec_lanes[j].size == bits) {
 -                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
 -                                       vec_lanes[j].suffix,
 -                                       vec_lanes[j].sz, vec_lanes[j].suffix);
 -            }
 -        }
 -        g_string_append(s, "</union>");
 -    }
 -    /* And now the final union of unions */
 -    g_string_append(s, "<union id=\"svev\">");
 -    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 -        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
 -        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
 -                               suf[i], suf[i]);
 -    }
 -    g_string_append(s, "</union>");
 -
 -    /* Finally the sve prefix type */
 -    g_string_append_printf(s,
 -                           "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
 -                           reg_width / 8);
 -
 -    /* Then define each register in parts for each vq */
 -    for (i = 0; i < 32; i++) {
 -        g_string_append_printf(s,
 -                               "<reg name=\"z%d\" bitsize=\"%d\""
 -                               " regnum=\"%d\" type=\"svev\"/>",
 -                               i, reg_width, base_reg++);
 -        info->num++;
 -    }
 -    /* fpscr & status registers */
 -    g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
 -                           " regnum=\"%d\" group=\"float\""
 -                           " type=\"int\"/>", base_reg++);
 -    g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
 -                           " regnum=\"%d\" group=\"float\""
 -                           " type=\"int\"/>", base_reg++);
 -    info->num += 2;
 -
 -    for (i = 0; i < 16; i++) {
 -        g_string_append_printf(s,
 -                               "<reg name=\"p%d\" bitsize=\"%d\""
 -                               " regnum=\"%d\" type=\"svep\"/>",
 -                               i, cpu->sve_max_vq * 16, base_reg++);
 -        info->num++;
 -    }
 -    g_string_append_printf(s,
 -                           "<reg name=\"ffr\" bitsize=\"%d\""
 -                           " regnum=\"%d\" group=\"vector\""
 -                           " type=\"svep\"/>",
 -                           cpu->sve_max_vq * 16, base_reg++);
 -    g_string_append_printf(s,
 -                           "<reg name=\"vg\" bitsize=\"64\""
 -                           " regnum=\"%d\" type=\"int\"/>",
 -                           base_reg++);
 -    info->num += 2;
 -    g_string_append_printf(s, "</feature>");
 -    cpu->dyn_svereg_xml.desc = g_string_free(s, false);
 -
 -    return cpu->dyn_svereg_xml.num;
 -}
 -
 -
  const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
  {
      ARMCPU *cpu = ARM_CPU(cs);
 diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub64.c
 +++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
      return 0;
  }
 +
 +struct TypeSize {
 +    const char *gdb_type;
 +    short size;
 +    char sz, suffix;
 +};
 +
 +static const struct TypeSize vec_lanes[] = {
 +    /* quads */
 +    { "uint128", 128, 'q', 'u' },
 +    { "int128", 128, 'q', 's' },
 +    /* 64 bit */
 +    { "ieee_double", 64, 'd', 'f' },
 +    { "uint64", 64, 'd', 'u' },
 +    { "int64", 64, 'd', 's' },
 +    /* 32 bit */
 +    { "ieee_single", 32, 's', 'f' },
 +    { "uint32", 32, 's', 'u' },
 +    { "int32", 32, 's', 's' },
 +    /* 16 bit */
 +    { "ieee_half", 16, 'h', 'f' },
 +    { "uint16", 16, 'h', 'u' },
 +    { "int16", 16, 'h', 's' },
 +    /* bytes */
 +    { "uint8", 8, 'b', 'u' },
 +    { "int8", 8, 'b', 's' },
 +};
 +
 +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    GString *s = g_string_new(NULL);
 +    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
 +    g_autoptr(GString) ts = g_string_new("");
 +    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
 +    info->num = 0;
 +    g_string_printf(s, "<?xml version=\"1.0\"?>");
 +    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 +    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 +
 +    /* First define types and totals in a whole VL */
 +    for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 +        int count = reg_width / vec_lanes[i].size;
 +        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
 +        g_string_append_printf(s,
 +                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
 +                               ts->str, vec_lanes[i].gdb_type, count);
 +    }
 +    /*
 +     * Now define a union for each size group containing unsigned and
 +     * signed and potentially float versions of each size from 128 to
 +     * 8 bits.
 +     */
 +    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 +        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
 +        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
 +        for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
 +            if (vec_lanes[j].size == bits) {
 +                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
 +                                       vec_lanes[j].suffix,
 +                                       vec_lanes[j].sz, vec_lanes[j].suffix);
 +            }
 +        }
 +        g_string_append(s, "</union>");
 +    }
 +    /* And now the final union of unions */
 +    g_string_append(s, "<union id=\"svev\">");
 +    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 +        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
 +        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
 +                               suf[i], suf[i]);
 +    }
 +    g_string_append(s, "</union>");
 +
 +    /* Finally the sve prefix type */
 +    g_string_append_printf(s,
 +                           "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
 +                           reg_width / 8);
 +
 +    /* Then define each register in parts for each vq */
 +    for (i = 0; i < 32; i++) {
 +        g_string_append_printf(s,
 +                               "<reg name=\"z%d\" bitsize=\"%d\""
 +                               " regnum=\"%d\" type=\"svev\"/>",
 +                               i, reg_width, base_reg++);
 +        info->num++;
 +    }
 +    /* fpscr & status registers */
 +    g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
 +                           " regnum=\"%d\" group=\"float\""
 +                           " type=\"int\"/>", base_reg++);
 +    g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
 +                           " regnum=\"%d\" group=\"float\""
 +                           " type=\"int\"/>", base_reg++);
 +    info->num += 2;
 +
 +    for (i = 0; i < 16; i++) {
 +        g_string_append_printf(s,
 +                               "<reg name=\"p%d\" bitsize=\"%d\""
 +                               " regnum=\"%d\" type=\"svep\"/>",
 +                               i, cpu->sve_max_vq * 16, base_reg++);
 +        info->num++;
 +    }
 +    g_string_append_printf(s,
 +                           "<reg name=\"ffr\" bitsize=\"%d\""
 +                           " regnum=\"%d\" group=\"vector\""
 +                           " type=\"svep\"/>",
 +                           cpu->sve_max_vq * 16, base_reg++);
 +    g_string_append_printf(s,
 +                           "<reg name=\"vg\" bitsize=\"64\""
 +                           " regnum=\"%d\" type=\"int\"/>",
 +                           base_reg++);
 +    info->num += 2;
 +    g_string_append_printf(s, "</feature>");
 +    info->desc = g_string_free(s, false);
 +
 +    return info->num;
 +}
 --
 .34.1

-New patch
+[PULL 04/21] target/arm: Split out output_vector_union_type
+From: Richard Henderson <richard.henderson@linaro.org>
+Create a subroutine for creating the union of unions
+of the various type sizes that a vector may contain.
+Reviewed-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-5-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/gdbstub64.c | 83 +++++++++++++++++++++++-------------------
+file changed, 45 insertions(+), 38 deletions(-)
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub64.c
++++ b/target/arm/gdbstub64.c
+@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
+     return 0;
+ }
+-struct TypeSize {
+-    const char *gdb_type;
+-    short size;
+-    char sz, suffix;
+-};
+-
+-static const struct TypeSize vec_lanes[] = {
+-    /* quads */
+-    { "uint128", 128, 'q', 'u' },
+-    { "int128", 128, 'q', 's' },
+-    /* 64 bit */
+-    { "ieee_double", 64, 'd', 'f' },
+-    { "uint64", 64, 'd', 'u' },
+-    { "int64", 64, 'd', 's' },
+-    /* 32 bit */
+-    { "ieee_single", 32, 's', 'f' },
+-    { "uint32", 32, 's', 'u' },
+-    { "int32", 32, 's', 's' },
+-    /* 16 bit */
+-    { "ieee_half", 16, 'h', 'f' },
+-    { "uint16", 16, 'h', 'u' },
+-    { "int16", 16, 'h', 's' },
+-    /* bytes */
+-    { "uint8", 8, 'b', 'u' },
+-    { "int8", 8, 'b', 's' },
+-};
+-
+-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
++static void output_vector_union_type(GString *s, int reg_width)
+ {
+-    ARMCPU *cpu = ARM_CPU(cs);
+-    GString *s = g_string_new(NULL);
+-    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
++    struct TypeSize {
++        const char *gdb_type;
++        short size;
++        char sz, suffix;
++    };
++
++    static const struct TypeSize vec_lanes[] = {
++        /* quads */
++        { "uint128", 128, 'q', 'u' },
++        { "int128", 128, 'q', 's' },
++        /* 64 bit */
++        { "ieee_double", 64, 'd', 'f' },
++        { "uint64", 64, 'd', 'u' },
++        { "int64", 64, 'd', 's' },
++        /* 32 bit */
++        { "ieee_single", 32, 's', 'f' },
++        { "uint32", 32, 's', 'u' },
++        { "int32", 32, 's', 's' },
++        /* 16 bit */
++        { "ieee_half", 16, 'h', 'f' },
++        { "uint16", 16, 'h', 'u' },
++        { "int16", 16, 'h', 's' },
++        /* bytes */
++        { "uint8", 8, 'b', 'u' },
++        { "int8", 8, 'b', 's' },
++    };
++
++    static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
++
+     g_autoptr(GString) ts = g_string_new("");
+-    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
+-    info->num = 0;
+-    g_string_printf(s, "<?xml version=\"1.0\"?>");
+-    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+-    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
++    int i, j, bits;
+     /* First define types and totals in a whole VL */
+     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+      * 8 bits.
+      */
+     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+         g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
+         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
+             if (vec_lanes[j].size == bits) {
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+     /* And now the final union of unions */
+     g_string_append(s, "<union id=\"svev\">");
+     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+         g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
+                                suf[i], suf[i]);
+     }
+     g_string_append(s, "</union>");
++}
++
++int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
++{
++    ARMCPU *cpu = ARM_CPU(cs);
++    GString *s = g_string_new(NULL);
++    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
++    int i, reg_width = (cpu->sve_max_vq * 128);
++    info->num = 0;
++    g_string_printf(s, "<?xml version=\"1.0\"?>");
++    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
++    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
++
++    output_vector_union_type(s, reg_width);
+     /* Finally the sve prefix type */
+     g_string_append_printf(s,
+--
+.34.1

-[PULL 14/14] hw: aspeed_gpio: Fix memory size
+[PULL 05/21] target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
-From: Joel Stanley <joel@jms.id.au>
+From: Richard Henderson <richard.henderson@linaro.org>
-The macro used to calculate the maximum memory size of the MMIO region
+Rather than increment base_reg and num, compute num from the change
-had a mistake, causing all GPIO models to create a mapping of 0x9D8.
+to base_reg at the end.  Clean up some nearby comments.
 The intent was to have it be 0x9D8 - 0x800.
-This extra size doesn't matter on ast2400 and ast2500, which have a 4KB
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-region set aside for the GPIO controller.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-6-richard.henderson@linaro.org
 On the ast2600 the 3.3V and 1.8V GPIO controllers are 2KB apart, so the
 regions would overlap. Worse was the 1.8V controller would map over the
 top of the following peripheral, which happens to be the RTC.
 The mmio region used by each device is a maximum of 2KB, so avoid the
 calculations and hard code this as the maximum.
 Fixes: 36d737ee82b2 ("hw/gpio: Add in AST2600 specific implementation")
 Signed-off-by: Joel Stanley <joel@jms.id.au>
 Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Message-id: 20210713065854.134634-2-joel@jms.id.au
 [PMM: fix autocorrect error in commit message]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/gpio/aspeed_gpio.c | 3 +--
+ target/arm/gdbstub64.c | 27 ++++++++++++++++-----------
-file changed, 1 insertion(+), 2 deletions(-)
+file changed, 16 insertions(+), 11 deletions(-)
-diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/gpio/aspeed_gpio.c
+--- a/target/arm/gdbstub64.c
-+++ b/hw/gpio/aspeed_gpio.c
++++ b/target/arm/gdbstub64.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
- #define GPIO_1_8V_MEM_SIZE            0x9D8
+     g_string_append(s, "</union>");
- #define GPIO_1_8V_REG_ARRAY_SIZE      ((GPIO_1_8V_MEM_SIZE - \
+ }
-                                       GPIO_1_8V_REG_OFFSET) >> 2)
--#define GPIO_MAX_MEM_SIZE           MAX(GPIO_3_6V_MEM_SIZE, GPIO_1_8V_MEM_SIZE)
+-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
++int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
  static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio)
  {
-@@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_realize(DeviceState *dev, Error **errp)
+     ARMCPU *cpu = ARM_CPU(cs);
      GString *s = g_string_new(NULL);
      DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
 -    int i, reg_width = (cpu->sve_max_vq * 128);
 -    info->num = 0;
 +    int reg_width = cpu->sve_max_vq * 128;
 +    int base_reg = orig_base_reg;
 +    int i;
 +
      g_string_printf(s, "<?xml version=\"1.0\"?>");
      g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
      g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 +    /* Create the vector union type. */
      output_vector_union_type(s, reg_width);
 -    /* Finally the sve prefix type */
 +    /* Create the predicate vector type. */
      g_string_append_printf(s,
                             "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
                             reg_width / 8);
 -    /* Then define each register in parts for each vq */
 +    /* Define the vector registers. */
      for (i = 0; i < 32; i++) {
          g_string_append_printf(s,
                                 "<reg name=\"z%d\" bitsize=\"%d\""
                                 " regnum=\"%d\" type=\"svev\"/>",
                                 i, reg_width, base_reg++);
 -        info->num++;
      }
++
-     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s,
+     /* fpscr & status registers */
--            TYPE_ASPEED_GPIO, GPIO_MAX_MEM_SIZE);
+     g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
-+            TYPE_ASPEED_GPIO, 0x800);
+                            " regnum=\"%d\" group=\"float\""
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
-     sysbus_init_mmio(sbd, &s->iomem);
+     g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
                             " regnum=\"%d\" group=\"float\""
                             " type=\"int\"/>", base_reg++);
 -    info->num += 2;
 +    /* Define the predicate registers. */
      for (i = 0; i < 16; i++) {
          g_string_append_printf(s,
                                 "<reg name=\"p%d\" bitsize=\"%d\""
                                 " regnum=\"%d\" type=\"svep\"/>",
                                 i, cpu->sve_max_vq * 16, base_reg++);
 -        info->num++;
      }
      g_string_append_printf(s,
                             "<reg name=\"ffr\" bitsize=\"%d\""
                             " regnum=\"%d\" group=\"vector\""
                             " type=\"svep\"/>",
                             cpu->sve_max_vq * 16, base_reg++);
 +
 +    /* Define the vector length pseudo-register. */
      g_string_append_printf(s,
                             "<reg name=\"vg\" bitsize=\"64\""
                             " regnum=\"%d\" type=\"int\"/>",
                             base_reg++);
 -    info->num += 2;
 -    g_string_append_printf(s, "</feature>");
 -    info->desc = g_string_free(s, false);
 +    g_string_append_printf(s, "</feature>");
 +
 +    info->desc = g_string_free(s, false);
 +    info->num = base_reg - orig_base_reg;
      return info->num;
  }
 --
-.20.1
+.34.1

-[PULL 09/14] docs: Update path that mentions deprecated.rst
+[PULL 06/21] target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
-From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Missed in commit f3478392 "docs: Move deprecation, build
+Reviewed-by: Fabiano Rosas <farosas@suse.de>
-and license info out of system/"
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
+Message-id: 20230227213329.793795-7-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20210723065828.1336760-1-maozhongyi@cmss.chinamobile.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- configure         | 2 +-
+ target/arm/gdbstub64.c | 5 +++--
- target/i386/cpu.c | 2 +-
+file changed, 3 insertions(+), 2 deletions(-)
  MAINTAINERS       | 2 +-
 files changed, 3 insertions(+), 3 deletions(-)
-diff --git a/configure b/configure
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100755
 --- a/configure
 +++ b/configure
@@ -XXX,XX +XXX,XX @@ fi
  if test -n "${deprecated_features}"; then
      echo "Warning, deprecated features enabled."
 -    echo "Please see docs/system/deprecated.rst"
 +    echo "Please see docs/about/deprecated.rst"
      echo "  features: ${deprecated_features}"
  fi
 diff --git a/target/i386/cpu.c b/target/i386/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/i386/cpu.c
+--- a/target/arm/gdbstub64.c
-+++ b/target/i386/cpu.c
++++ b/target/arm/gdbstub64.c
-@@ -XXX,XX +XXX,XX @@ static const X86CPUDefinition builtin_x86_defs[] = {
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
-  * none", but this is just for compatibility while libvirt isn't
+     GString *s = g_string_new(NULL);
-  * adapted to resolve CPU model versions before creating VMs.
+     DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
-  * See "Runnability guarantee of CPU models" at
+     int reg_width = cpu->sve_max_vq * 128;
-- * docs/system/deprecated.rst.
++    int pred_width = cpu->sve_max_vq * 16;
-+ * docs/about/deprecated.rst.
+     int base_reg = orig_base_reg;
-  */
+     int i;
- X86CPUVersion default_cpu_version = 1;
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
-diff --git a/MAINTAINERS b/MAINTAINERS
+         g_string_append_printf(s,
-index XXXXXXX..XXXXXXX 100644
+                                "<reg name=\"p%d\" bitsize=\"%d\""
---- a/MAINTAINERS
+                                " regnum=\"%d\" type=\"svep\"/>",
-+++ b/MAINTAINERS
+-                               i, cpu->sve_max_vq * 16, base_reg++);
-@@ -XXX,XX +XXX,XX @@ F: contrib/gitdm/*
++                               i, pred_width, base_reg++);
+     }
- Incompatible changes
+     g_string_append_printf(s,
- R: libvir-list@redhat.com
+                            "<reg name=\"ffr\" bitsize=\"%d\""
--F: docs/system/deprecated.rst
+                            " regnum=\"%d\" group=\"vector\""
-+F: docs/about/deprecated.rst
+                            " type=\"svep\"/>",
+-                           cpu->sve_max_vq * 16, base_reg++);
- Build System
++                           pred_width, base_reg++);
- ------------
      /* Define the vector length pseudo-register. */
      g_string_append_printf(s,
 --
-.20.1
+.34.1

-New patch
+[PULL 07/21] target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
+From: Richard Henderson <richard.henderson@linaro.org>
+Define svep based on the size of the predicates,
+not the primary vector registers.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-8-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/gdbstub64.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub64.c
++++ b/target/arm/gdbstub64.c
+@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
+     /* Create the predicate vector type. */
+     g_string_append_printf(s,
+                            "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
+-                           reg_width / 8);
++                           pred_width / 8);
+     /* Define the vector registers. */
+     for (i = 0; i < 32; i++) {
+--
+.34.1

-[PULL 07/14] hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
+[PULL 08/21] target/arm: Add name argument to output_vector_union_type
-The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of
+From: Richard Henderson <richard.henderson@linaro.org>
 the register.  We were incorrectly masking it to 8 bits, so it would
 report the wrong value if the pending exception was greater than 256.
 Fix the bug.
+This will make the function usable between SVE and SME.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-9-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210723162146.5167-6-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 2 +-
+ target/arm/gdbstub64.c | 28 ++++++++++++++--------------
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 14 insertions(+), 14 deletions(-)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/target/arm/gdbstub64.c
-+++ b/hw/intc/armv7m_nvic.c
++++ b/target/arm/gdbstub64.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
+@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
-         /* VECTACTIVE */
+     return 0;
-         val = cpu->env.v7m.exception;
+ }
-         /* VECTPENDING */
--        val |= (s->vectpending & 0xff) << 12;
+-static void output_vector_union_type(GString *s, int reg_width)
-+        val |= (s->vectpending & 0x1ff) << 12;
++static void output_vector_union_type(GString *s, int reg_width,
-         /* ISRPENDING - set if any external IRQ is pending */
++                                     const char *name)
-         if (nvic_isrpending(s)) {
+ {
-             val |= (1 << 22);
+     struct TypeSize {
          const char *gdb_type;
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
      };
      static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
 -
 -    g_autoptr(GString) ts = g_string_new("");
      int i, j, bits;
      /* First define types and totals in a whole VL */
      for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 -        int count = reg_width / vec_lanes[i].size;
 -        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
          g_string_append_printf(s,
 -                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
 -                               ts->str, vec_lanes[i].gdb_type, count);
 +                               "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",
 +                               name, vec_lanes[i].sz, vec_lanes[i].suffix,
 +                               vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);
      }
 +
      /*
       * Now define a union for each size group containing unsigned and
       * signed and potentially float versions of each size from 128 to
       * 8 bits.
       */
      for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 -        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
 +        g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
          for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
              if (vec_lanes[j].size == bits) {
 -                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
 -                                       vec_lanes[j].suffix,
 +                g_string_append_printf(s, "<field name=\"%c\" type=\"%s%c%c\"/>",
 +                                       vec_lanes[j].suffix, name,
                                         vec_lanes[j].sz, vec_lanes[j].suffix);
              }
          }
          g_string_append(s, "</union>");
      }
 +
      /* And now the final union of unions */
 -    g_string_append(s, "<union id=\"svev\">");
 +    g_string_append_printf(s, "<union id=\"%s\">", name);
      for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
 -        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
 -                               suf[i], suf[i]);
 +        g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
 +                               suf[i], name, suf[i]);
      }
      g_string_append(s, "</union>");
  }
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
      g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
      /* Create the vector union type. */
 -    output_vector_union_type(s, reg_width);
 +    output_vector_union_type(s, reg_width, "svev");
      /* Create the predicate vector type. */
      g_string_append_printf(s,
 --
-.20.1
+.34.1

-New patch
+[PULL 09/21] target/arm: Simplify iteration over bit widths
+From: Richard Henderson <richard.henderson@linaro.org>
+Order suf[] by the log8 of the width.
+Use ARRAY_SIZE instead of hard-coding 128.
+This changes the order of the union definitions,
+but retains the order of the union-of-union members.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-10-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/gdbstub64.c | 10 ++++++----
+file changed, 6 insertions(+), 4 deletions(-)
+diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/gdbstub64.c
++++ b/target/arm/gdbstub64.c
+@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
+         { "int8", 8, 'b', 's' },
+     };
+-    static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+-    int i, j, bits;
++    static const char suf[] = { 'b', 'h', 's', 'd', 'q' };
++    int i, j;
+     /* First define types and totals in a whole VL */
+     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
+      * signed and potentially float versions of each size from 128 to
+      * 8 bits.
+      */
+-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
++    for (i = 0; i < ARRAY_SIZE(suf); i++) {
++        int bits = 8 << i;
++
+         g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
+         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
+             if (vec_lanes[j].size == bits) {
+@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
+     /* And now the final union of unions */
+     g_string_append_printf(s, "<union id=\"%s\">", name);
+-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
++    for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {
+         g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
+                                suf[i], name, suf[i]);
+     }
+--
+.34.1

-New patch
+[PULL 10/21] target/arm: Create pauth_ptr_mask
+From: Richard Henderson <richard.henderson@linaro.org>
+Keep the logic for pauth within pauth_helper.c, and expose
+a helper function for use with the gdbstub pac extension.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-11-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/internals.h        | 10 ++++++++++
+ target/arm/tcg/pauth_helper.c | 26 ++++++++++++++++++++++----
+files changed, 32 insertions(+), 4 deletions(-)
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ int exception_target_el(CPUARMState *env);
+ bool arm_singlestep_active(CPUARMState *env);
+ bool arm_generate_debug_exceptions(CPUARMState *env);
++/**
++ * pauth_ptr_mask:
++ * @env: cpu context
++ * @ptr: selects between TTBR0 and TTBR1
++ * @data: selects between TBI and TBID
++ *
++ * Return a mask of the bits of @ptr that contain the authentication code.
++ */
++uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data);
++
+ /* Add the cpreg definitions for debug related system registers */
+ void define_debug_regs(ARMCPU *cpu);
+diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/pauth_helper.c
++++ b/target/arm/tcg/pauth_helper.c
+@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
+     return pac | ext | ptr;
+ }
+-static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
++static uint64_t pauth_ptr_mask_internal(ARMVAParameters param)
+ {
+-    /* Note that bit 55 is used whether or not the regime has 2 ranges. */
+-    uint64_t extfield = sextract64(ptr, 55, 1);
+     int bot_pac_bit = 64 - param.tsz;
+     int top_pac_bit = 64 - 8 * param.tbi;
+-    return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield);
++    return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);
++}
++
++static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
++{
++    uint64_t mask = pauth_ptr_mask_internal(param);
++
++    /* Note that bit 55 is used whether or not the regime has 2 ranges. */
++    if (extract64(ptr, 55, 1)) {
++        return ptr | mask;
++    } else {
++        return ptr & ~mask;
++    }
++}
++
++uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data)
++{
++    ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
++    ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
++
++    return pauth_ptr_mask_internal(param);
+ }
+ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
+--
+.34.1

-[PULL 08/14] hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
+[PULL 11/21] target/arm: Implement gdbstub pauth extension
-In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if
+From: Richard Henderson <richard.henderson@linaro.org>
 the register is accessed NonSecure and the highest priority pending
 enabled exception (that would be returned in the VECTPENDING field)
 targets Secure, then the VECTPENDING field must read 1 rather than
 the exception number of the pending exception. Implement this.
+The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK
+ptrace register set.
+The original gdb feature consists of two masks, data and code, which are
+used to mask out the authentication code within a pointer.  Following
+discussion with Luis Machado, add two more masks in order to support
+pointers within the high half of the address space (i.e. TTBR1 vs TTBR0).
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-12-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210723162146.5167-7-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 31 ++++++++++++++++++++++++-------
+ configs/targets/aarch64-linux-user.mak    |  2 +-
-file changed, 24 insertions(+), 7 deletions(-)
+ configs/targets/aarch64-softmmu.mak       |  2 +-
  configs/targets/aarch64_be-linux-user.mak |  2 +-
  target/arm/internals.h                    |  2 ++
  target/arm/gdbstub.c                      |  5 ++++
  target/arm/gdbstub64.c                    | 34 +++++++++++++++++++++++
  gdb-xml/aarch64-pauth.xml                 | 15 ++++++++++
 files changed, 59 insertions(+), 3 deletions(-)
  create mode 100644 gdb-xml/aarch64-pauth.xml
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/configs/targets/aarch64-linux-user.mak
-+++ b/hw/intc/armv7m_nvic.c
++++ b/configs/targets/aarch64-linux-user.mak
-@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
+@@ -XXX,XX +XXX,XX @@
-     nvic_irq_update(s);
+ TARGET_ARCH=aarch64
  TARGET_BASE_ARCH=arm
 -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
 +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
  TARGET_HAS_BFLT=y
  CONFIG_SEMIHOSTING=y
  CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
 diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
 index XXXXXXX..XXXXXXX 100644
 --- a/configs/targets/aarch64-softmmu.mak
 +++ b/configs/targets/aarch64-softmmu.mak
@@ -XXX,XX +XXX,XX @@
  TARGET_ARCH=aarch64
  TARGET_BASE_ARCH=arm
  TARGET_SUPPORTS_MTTCG=y
 -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml
 +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml
  TARGET_NEED_FDT=y
 diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak
 index XXXXXXX..XXXXXXX 100644
 --- a/configs/targets/aarch64_be-linux-user.mak
 +++ b/configs/targets/aarch64_be-linux-user.mak
@@ -XXX,XX +XXX,XX @@
  TARGET_ARCH=aarch64
  TARGET_BASE_ARCH=arm
  TARGET_BIG_ENDIAN=y
 -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
 +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
  TARGET_HAS_BFLT=y
  CONFIG_SEMIHOSTING=y
  CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
  int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
  int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
  int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
 +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);
 +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);
  void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
  void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
  void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub.c
 +++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
                                       aarch64_gdb_set_fpu_reg,
 , "aarch64-fpu.xml", 0);
          }
 +        if (isar_feature_aa64_pauth(&cpu->isar)) {
 +            gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
 +                                     aarch64_gdb_set_pauth_reg,
 +                                     4, "aarch64-pauth.xml", 0);
 +        }
  #endif
      } else {
          if (arm_feature(env, ARM_FEATURE_NEON)) {
 diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub64.c
 +++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
      return 0;
  }
-+static bool vectpending_targets_secure(NVICState *s)
++int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
 +{
-+    /* Return true if s->vectpending targets Secure state */
++    switch (reg) {
-+    if (s->vectpending_is_s_banked) {
++    case 0: /* pauth_dmask */
-+        return true;
++    case 1: /* pauth_cmask */
 +    case 2: /* pauth_dmask_high */
 +    case 3: /* pauth_cmask_high */
 +        /*
 +         * Note that older versions of this feature only contained
 +         * pauth_{d,c}mask, for use with Linux user processes, and
 +         * thus exclusively in the low half of the address space.
 +         *
 +         * To support system mode, and to debug kernels, two new regs
 +         * were added to cover the high half of the address space.
 +         * For the purpose of pauth_ptr_mask, we can use any well-formed
 +         * address within the address space half -- here, 0 and -1.
 +         */
 +        {
 +            bool is_data = !(reg & 1);
 +            bool is_high = reg & 2;
 +            uint64_t mask = pauth_ptr_mask(env, -is_high, is_data);
 +            return gdb_get_reg64(buf, mask);
 +        }
 +    default:
 +        return 0;
 +    }
-+    return !exc_is_banked(s->vectpending) &&
-+        exc_targets_secure(s, s->vectpending);
 +}
 +
- void armv7m_nvic_get_pending_irq_info(void *opaque,
++int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)
-                                       int *pirq, bool *ptargets_secure)
++{
 +    /* All pseudo registers are read-only. */
 +    return 0;
 +}
 +
  static void output_vector_union_type(GString *s, int reg_width,
                                       const char *name)
  {
-@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,
+diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml
+new file mode 100644
-     assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
+index XXXXXXX..XXXXXXX
+--- /dev/null
--    if (s->vectpending_is_s_banked) {
++++ b/gdb-xml/aarch64-pauth.xml
--        targets_secure = true;
+@@ -XXX,XX +XXX,XX @@
--    } else {
++<?xml version="1.0"?>
--        targets_secure = !exc_is_banked(pending) &&
++<!-- Copyright (C) 2018-2022 Free Software Foundation, Inc.
--            exc_targets_secure(s, pending);
++
--    }
++     Copying and distribution of this file, with or without modification,
-+    targets_secure = vectpending_targets_secure(s);
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
-     trace_nvic_get_pending_irq_info(pending, targets_secure);
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
++<feature name="org.gnu.gdb.aarch64.pauth">
-         /* VECTACTIVE */
++  <reg name="pauth_dmask" bitsize="64"/>
-         val = cpu->env.v7m.exception;
++  <reg name="pauth_cmask" bitsize="64"/>
-         /* VECTPENDING */
++  <reg name="pauth_dmask_high" bitsize="64"/>
--        val |= (s->vectpending & 0x1ff) << 12;
++  <reg name="pauth_cmask_high" bitsize="64"/>
-+        if (s->vectpending) {
++</feature>
-+            /*
++
 +             * From v8.1M VECTPENDING must read as 1 if accessed as
 +             * NonSecure and the highest priority pending and enabled
 +             * exception targets Secure.
 +             */
 +            int vp = s->vectpending;
 +            if (!attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_V8_1M) &&
 +                vectpending_targets_secure(s)) {
 +                vp = 1;
 +            }
 +            val |= (vp & 0x1ff) << 12;
 +        }
          /* ISRPENDING - set if any external IRQ is pending */
          if (nvic_isrpending(s)) {
              val |= (1 << 22);
 --
-.20.1
+.34.1

-[PULL 05/14] target/arm: Report M-profile alignment faults correctly to the guest
+[PULL 12/21] target/arm: Export arm_v7m_mrs_control
-For M-profile, we weren't reporting alignment faults triggered by the
+From: David Reiss <dreiss@meta.com>
 generic TCG code correctly to the guest.  These get passed into
 arm_v7m_cpu_do_interrupt() as an EXCP_DATA_ABORT with an A-profile
 style exception.fsr value of 1.  We didn't check for this, and so
 they fell through into the default of "assume this is an MPU fault"
 and were reported to the guest as a data access violation MPU fault.
-Report these alignment faults as UsageFaults which set the UNALIGNED
+Allow the function to be used outside of m_helper.c.
-bit in the UFSR.
+Rename with an "arm_" prefix.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: David Reiss <dreiss@meta.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227213329.793795-13-richard.henderson@linaro.org
+[rth: Split out of a larger patch]
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210723162146.5167-4-peter.maydell@linaro.org
 ---
- target/arm/m_helper.c | 8 ++++++++
+ target/arm/internals.h    | 3 +++
-file changed, 8 insertions(+)
+ target/arm/tcg/m_helper.c | 6 +++---
 files changed, 6 insertions(+), 3 deletions(-)
-diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
+diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/m_helper.c
+--- a/target/arm/internals.h
-+++ b/target/arm/m_helper.c
++++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
-         env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK;
+ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
-         break;
+ #endif
-     case EXCP_UNALIGNED:
-+        /* Unaligned faults reported by M-profile aware code */
++/* Read the CONTROL register as the MRS instruction would. */
-         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
++uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
-         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;
++
-         break;
+ #ifdef CONFIG_USER_ONLY
-@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
+ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
-             }
+ #else
-             armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
+diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
-             break;
+index XXXXXXX..XXXXXXX 100644
-+        case 0x1: /* Alignment fault reported by generic code */
+--- a/target/arm/tcg/m_helper.c
-+            qemu_log_mask(CPU_LOG_INT,
++++ b/target/arm/tcg/m_helper.c
-+                          "...really UsageFault with UFSR.UNALIGNED\n");
+@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el)
-+            env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;
+     return xpsr_read(env) & mask;
-+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
+ }
-+                                    env->v7m.secure);
-+            break;
+-static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure)
-         default:
++uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure)
-             /*
+ {
-              * All other FSR values are either MPU faults or "can't happen
+     uint32_t value = env->v7m.control[secure];
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
      case 0 ... 7: /* xPSR sub-fields */
          return v7m_mrs_xpsr(env, reg, 0);
      case 20: /* CONTROL */
 -        return v7m_mrs_control(env, 0);
 +        return arm_v7m_mrs_control(env, 0);
      default:
          /* Unprivileged reads others as zero.  */
          return 0;
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
      case 0 ... 7: /* xPSR sub-fields */
          return v7m_mrs_xpsr(env, reg, el);
      case 20: /* CONTROL */
 -        return v7m_mrs_control(env, env->v7m.secure);
 +        return arm_v7m_mrs_control(env, env->v7m.secure);
      case 0x94: /* CONTROL_NS */
          /*
           * We have to handle this here because unprivileged Secure code
 --
-.20.1
+.34.1

-[PULL 04/14] target/arm: Add missing 'return's after calling v7m_exception_taken()
+[PULL 13/21] target/arm: Export arm_v7m_get_sp_ptr
-In do_v7m_exception_exit(), we perform various checks as part of
+From: David Reiss <dreiss@meta.com>
 performing the exception return.  If one of these checks fails, the
 architecture requires that we take an appropriate exception on the
 existing stackframe.  We implement this by calling
 v7m_exception_taken() to set up to take the new exception, and then
 immediately returning from do_v7m_exception_exit() without proceeding
 any further with the unstack-and-exception-return process.
-In a couple of checks that are new in v8.1M, we forgot the "return"
+Allow the function to be used outside of m_helper.c.
-statement, with the effect that if bad code in the guest tripped over
+Move to be outside of ifndef CONFIG_USER_ONLY block.
-these checks we would set up to take a UsageFault exception but then
+Rename from get_v7m_sp_ptr.
 blunder on trying to also unstack and return from the original
 exception, with the probable result that the guest would crash.
-Add the missing return statements.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: David Reiss <dreiss@meta.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230227213329.793795-14-richard.henderson@linaro.org
 [rth: Split out of a larger patch]
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/internals.h    | 10 +++++
  target/arm/tcg/m_helper.c | 84 +++++++++++++++++++--------------------
 files changed, 51 insertions(+), 43 deletions(-)
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+diff --git a/target/arm/internals.h b/target/arm/internals.h
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20210723162146.5167-3-peter.maydell@linaro.org
 ---
  target/arm/m_helper.c | 2 ++
 file changed, 2 insertions(+)
 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/m_helper.c
+--- a/target/arm/internals.h
-+++ b/target/arm/m_helper.c
++++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
  /* Read the CONTROL register as the MRS instruction would. */
  uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
 +/*
 + * Return a pointer to the location where we currently store the
 + * stack pointer for the requested security state and thread mode.
 + * This pointer will become invalid if the CPU state is updated
 + * such that the stack pointers are switched around (eg changing
 + * the SPSEL control bit).
 + */
 +uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,
 +                             bool threadmode, bool spsel);
 +
  #ifdef CONFIG_USER_ONLY
  static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
  #else
 diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/m_helper.c
 +++ b/target/arm/tcg/m_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
      arm_rebuild_hflags(env);
  }
 -static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
 -                                bool spsel)
 -{
 -    /*
 -     * Return a pointer to the location where we currently store the
 -     * stack pointer for the requested security state and thread mode.
 -     * This pointer will become invalid if the CPU state is updated
 -     * such that the stack pointers are switched around (eg changing
 -     * the SPSEL control bit).
 -     * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
 -     * Unlike that pseudocode, we require the caller to pass us in the
 -     * SPSEL control bit value; this is because we also use this
 -     * function in handling of pushing of the callee-saves registers
 -     * part of the v8M stack frame (pseudocode PushCalleeStack()),
 -     * and in the tailchain codepath the SPSEL bit comes from the exception
 -     * return magic LR value from the previous exception. The pseudocode
 -     * opencodes the stack-selection in PushCalleeStack(), but we prefer
 -     * to make this utility function generic enough to do the job.
 -     */
 -    bool want_psp = threadmode && spsel;
 -
 -    if (secure == env->v7m.secure) {
 -        if (want_psp == v7m_using_psp(env)) {
 -            return &env->regs[13];
 -        } else {
 -            return &env->v7m.other_sp;
 -        }
 -    } else {
 -        if (want_psp) {
 -            return &env->v7m.other_ss_psp;
 -        } else {
 -            return &env->v7m.other_ss_msp;
 -        }
 -    }
 -}
 -
  static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
                                  uint32_t *pvec)
  {
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
              !mode;
          mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv);
 -        frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode,
 -                                    lr & R_V7M_EXCRET_SPSEL_MASK);
 +        frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode,
 +                                        lr & R_V7M_EXCRET_SPSEL_MASK);
          want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK);
          if (want_psp) {
              limit = env->v7m.psplim[M_REG_S];
 @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
-                     qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
+          * use 'frame_sp_p' after we do something that makes it invalid.
-                         "stackframe: NSACR prevents clearing FPU registers\n");
+          */
-                     v7m_exception_taken(cpu, excret, true, false);
+         bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK;
-+                    return;
+-        uint32_t *frame_sp_p = get_v7m_sp_ptr(env,
-                 } else if (!cpacr_pass) {
+-                                              return_to_secure,
-                     armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
+-                                              !return_to_handler,
-                                             exc_secure);
+-                                              spsel);
-@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
++        uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure,
-                     qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
++                                                  !return_to_handler, spsel);
-                         "stackframe: CPACR prevents clearing FPU registers\n");
+         uint32_t frameptr = *frame_sp_p;
-                     v7m_exception_taken(cpu, excret, true, false);
+         bool pop_ok = true;
-+                    return;
+         ARMMMUIdx mmu_idx;
-                 }
+@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
-             }
+         threadmode = !arm_v7m_is_handler_mode(env);
-             /* Clear s0..s15, FPSCR and VPR */
+         spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
 -        frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
 +        frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel);
          frameptr = *frame_sp_p;
          /*
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
  }
  #endif /* !CONFIG_USER_ONLY */
 +
 +uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
 +                             bool spsel)
 +{
 +    /*
 +     * Return a pointer to the location where we currently store the
 +     * stack pointer for the requested security state and thread mode.
 +     * This pointer will become invalid if the CPU state is updated
 +     * such that the stack pointers are switched around (eg changing
 +     * the SPSEL control bit).
 +     * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
 +     * Unlike that pseudocode, we require the caller to pass us in the
 +     * SPSEL control bit value; this is because we also use this
 +     * function in handling of pushing of the callee-saves registers
 +     * part of the v8M stack frame (pseudocode PushCalleeStack()),
 +     * and in the tailchain codepath the SPSEL bit comes from the exception
 +     * return magic LR value from the previous exception. The pseudocode
 +     * opencodes the stack-selection in PushCalleeStack(), but we prefer
 +     * to make this utility function generic enough to do the job.
 +     */
 +    bool want_psp = threadmode && spsel;
 +
 +    if (secure == env->v7m.secure) {
 +        if (want_psp == v7m_using_psp(env)) {
 +            return &env->regs[13];
 +        } else {
 +            return &env->v7m.other_sp;
 +        }
 +    } else {
 +        if (want_psp) {
 +            return &env->v7m.other_ss_psp;
 +        } else {
 +            return &env->v7m.other_ss_msp;
 +        }
 +    }
 +}
 --
-.20.1
+.34.1

-[PULL 12/14] target/arm: Add sve-default-vector-length cpu property
+[PULL 14/21] target/arm: Implement gdbstub m-profile systemreg and secext
 From: Richard Henderson <richard.henderson@linaro.org>
-Mirror the behavour of /proc/sys/abi/sve_default_vector_length
+The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but
-under the real linux kernel.  We have no way of passing along
+go ahead and implement the other system registers as well.
-a real default across exec like the kernel can, but this is a
-decent way of adjusting the startup vector length of a process.
+Since there is significant overlap between the two, implement
+them with common code.  The only exception is the systemreg
-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/482
+view of CONTROL, which merges the banked bits as per MRS.
 Signed-off-by: David Reiss <dreiss@meta.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230227213329.793795-15-richard.henderson@linaro.org
 [rth: Substatial rewrite using enumerator and shared code.]
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20210723203344.968563-4-richard.henderson@linaro.org
-[PMM: tweaked docs formatting, document -1 special-case,
- added fixup patch from RTH mentioning QEMU's maximum veclen.]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/cpu-features.rst | 15 ++++++++
+ target/arm/cpu.h     |   2 +
- target/arm/cpu.h                 |  5 +++
+ target/arm/gdbstub.c | 178 +++++++++++++++++++++++++++++++++++++++++++
- target/arm/cpu.c                 | 14 ++++++--
+files changed, 180 insertions(+)
- target/arm/cpu64.c               | 60 ++++++++++++++++++++++++++++++++
 files changed, 92 insertions(+), 2 deletions(-)
 diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/arm/cpu-features.rst
 +++ b/docs/system/arm/cpu-features.rst
@@ -XXX,XX +XXX,XX @@ verbose command lines.  However, the recommended way to select vector
  lengths is to explicitly enable each desired length.  Therefore only
  example's (1), (4), and (6) exhibit recommended uses of the properties.
 +SVE User-mode Default Vector Length Property
 +--------------------------------------------
 +
 +For qemu-aarch64, the cpu property ``sve-default-vector-length=N`` is
 +defined to mirror the Linux kernel parameter file
 +``/proc/sys/abi/sve_default_vector_length``.  The default length, ``N``,
 +is in units of bytes and must be between 16 and 8192.
 +If not specified, the default vector length is 64.
 +
 +If the default length is larger than the maximum vector length enabled,
 +the actual vector length will be reduced.  Note that the maximum vector
 +length supported by QEMU is 256.
 +
 +If this property is set to ``-1`` then the default vector length
 +is set to the maximum possible length.
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
-     /* Used to set the maximum vector length the cpu will support.  */
-     uint32_t sve_max_vq;
+     DynamicGDBXMLInfo dyn_sysreg_xml;
+     DynamicGDBXMLInfo dyn_svereg_xml;
-+#ifdef CONFIG_USER_ONLY
++    DynamicGDBXMLInfo dyn_m_systemreg_xml;
-+    /* Used to set the default vector length at process start. */
++    DynamicGDBXMLInfo dyn_m_secextreg_xml;
-+    uint32_t sve_default_vq;
      /* Timers used by the generic (architected) timer */
      QEMUTimer *gt_timer[NUM_GTIMERS];
 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gdbstub.c
 +++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
      return cpu->dyn_sysreg_xml.num;
  }
 +typedef enum {
 +    M_SYSREG_MSP,
 +    M_SYSREG_PSP,
 +    M_SYSREG_PRIMASK,
 +    M_SYSREG_CONTROL,
 +    M_SYSREG_BASEPRI,
 +    M_SYSREG_FAULTMASK,
 +    M_SYSREG_MSPLIM,
 +    M_SYSREG_PSPLIM,
 +} MProfileSysreg;
 +
 +static const struct {
 +    const char *name;
 +    int feature;
 +} m_sysreg_def[] = {
 +    [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M },
 +    [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M },
 +    [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M },
 +    [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M },
 +    [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN },
 +    [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN },
 +    [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 },
 +    [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 },
 +};
 +
 +static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec)
 +{
 +    uint32_t *ptr;
 +
 +    switch (reg) {
 +    case M_SYSREG_MSP:
 +        ptr = arm_v7m_get_sp_ptr(env, sec, false, true);
 +        break;
 +    case M_SYSREG_PSP:
 +        ptr = arm_v7m_get_sp_ptr(env, sec, true, true);
 +        break;
 +    case M_SYSREG_MSPLIM:
 +        ptr = &env->v7m.msplim[sec];
 +        break;
 +    case M_SYSREG_PSPLIM:
 +        ptr = &env->v7m.psplim[sec];
 +        break;
 +    case M_SYSREG_PRIMASK:
 +        ptr = &env->v7m.primask[sec];
 +        break;
 +    case M_SYSREG_BASEPRI:
 +        ptr = &env->v7m.basepri[sec];
 +        break;
 +    case M_SYSREG_FAULTMASK:
 +        ptr = &env->v7m.faultmask[sec];
 +        break;
 +    case M_SYSREG_CONTROL:
 +        ptr = &env->v7m.control[sec];
 +        break;
 +    default:
 +        return NULL;
 +    }
 +    return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL;
 +}
 +
 +static int m_sysreg_get(CPUARMState *env, GByteArray *buf,
 +                        MProfileSysreg reg, bool secure)
 +{
 +    uint32_t *ptr = m_sysreg_ptr(env, reg, secure);
 +
 +    if (ptr == NULL) {
 +        return 0;
 +    }
 +    return gdb_get_reg32(buf, *ptr);
 +}
 +
 +static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)
 +{
 +    /*
 +     * Here, we emulate MRS instruction, where CONTROL has a mix of
 +     * banked and non-banked bits.
 +     */
 +    if (reg == M_SYSREG_CONTROL) {
 +        return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure));
 +    }
 +    return m_sysreg_get(env, buf, reg, env->v7m.secure);
 +}
 +
 +static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)
 +{
 +    return 0; /* TODO */
 +}
 +
 +static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    CPUARMState *env = &cpu->env;
 +    GString *s = g_string_new(NULL);
 +    int base_reg = orig_base_reg;
 +    int i;
 +
 +    g_string_printf(s, "<?xml version=\"1.0\"?>");
 +    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 +    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.m-system\">\n");
 +
 +    for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
 +        if (arm_feature(env, m_sysreg_def[i].feature)) {
 +            g_string_append_printf(s,
 +                "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n",
 +                m_sysreg_def[i].name, base_reg++);
 +        }
 +    }
 +
 +    g_string_append_printf(s, "</feature>");
 +    cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false);
 +    cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg;
 +
 +    return cpu->dyn_m_systemreg_xml.num;
 +}
 +
 +#ifndef CONFIG_USER_ONLY
 +/*
 + * For user-only, we see the non-secure registers via m_systemreg above.
 + * For secext, encode the non-secure view as even and secure view as odd.
 + */
 +static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg)
 +{
 +    return m_sysreg_get(env, buf, reg >> 1, reg & 1);
 +}
 +
 +static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)
 +{
 +    return 0; /* TODO */
 +}
 +
 +static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    GString *s = g_string_new(NULL);
 +    int base_reg = orig_base_reg;
 +    int i;
 +
 +    g_string_printf(s, "<?xml version=\"1.0\"?>");
 +    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 +    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.secext\">\n");
 +
 +    for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
 +        g_string_append_printf(s,
 +            "<reg name=\"%s_ns\" bitsize=\"32\" regnum=\"%d\"/>\n",
 +            m_sysreg_def[i].name, base_reg++);
 +        g_string_append_printf(s,
 +            "<reg name=\"%s_s\" bitsize=\"32\" regnum=\"%d\"/>\n",
 +            m_sysreg_def[i].name, base_reg++);
 +    }
 +
 +    g_string_append_printf(s, "</feature>");
 +    cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false);
 +    cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg;
 +
 +    return cpu->dyn_m_secextreg_xml.num;
 +}
 +#endif
 +
-     /*
+ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
-      * In sve_vq_map each set bit is a supported vector length of
+ {
-      * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
+     ARMCPU *cpu = ARM_CPU(cs);
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
-index XXXXXXX..XXXXXXX 100644
+         return cpu->dyn_sysreg_xml.desc;
---- a/target/arm/cpu.c
+     } else if (strcmp(xmlname, "sve-registers.xml") == 0) {
-+++ b/target/arm/cpu.c
+         return cpu->dyn_svereg_xml.desc;
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
++    } else if (strcmp(xmlname, "arm-m-system.xml") == 0) {
-         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
++        return cpu->dyn_m_systemreg_xml.desc;
-         /* with reasonable vector length */
++#ifndef CONFIG_USER_ONLY
-         if (cpu_isar_feature(aa64_sve, cpu)) {
++    } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) {
--            env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3);
++        return cpu->dyn_m_secextreg_xml.desc;
-+            env->vfp.zcr_el[1] =
++#endif
-+                aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1);
+     }
-         }
+     return NULL;
          /*
           * Enable TBI0 but not TBI1.
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
      QLIST_INIT(&cpu->pre_el_change_hooks);
      QLIST_INIT(&cpu->el_change_hooks);
 -#ifndef CONFIG_USER_ONLY
 +#ifdef CONFIG_USER_ONLY
 +# ifdef TARGET_AARCH64
 +    /*
 +     * The linux kernel defaults to 512-bit vectors, when sve is supported.
 +     * See documentation for /proc/sys/abi/sve_default_vector_length, and
 +     * our corresponding sve-default-vector-length cpu property.
 +     */
 +    cpu->sve_default_vq = 4;
 +# endif
 +#else
      /* Our inbound IRQ and FIQ lines */
      if (kvm_enabled()) {
          /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)
      cpu->isar.id_aa64pfr0 = t;
  }
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
-+#ifdef CONFIG_USER_ONLY
+                              arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
-+/* Mirror linux /proc/sys/abi/sve_default_vector_length. */
+                              "system-registers.xml", 0);
-+static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v,
-+                                            const char *name, void *opaque,
++    if (arm_feature(env, ARM_FEATURE_M)) {
-+                                            Error **errp)
++        gdb_register_coprocessor(cs,
-+{
++            arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
-+    ARMCPU *cpu = ARM_CPU(obj);
++            arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
-+    int32_t default_len, default_vq, remainder;
++            "arm-m-system.xml", 0);
-+
++#ifndef CONFIG_USER_ONLY
-+    if (!visit_type_int32(v, name, &default_len, errp)) {
++        if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
-+        return;
++            gdb_register_coprocessor(cs,
-+    }
++                arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,
-+
++                arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs),
-+    /* Undocumented, but the kernel allows -1 to indicate "maximum". */
++                "arm-m-secext.xml", 0);
 +    if (default_len == -1) {
 +        cpu->sve_default_vq = ARM_MAX_VQ;
 +        return;
 +    }
 +
 +    default_vq = default_len / 16;
 +    remainder = default_len % 16;
 +
 +    /*
 +     * Note that the 512 max comes from include/uapi/asm/sve_context.h
 +     * and is the maximum architectural width of ZCR_ELx.LEN.
 +     */
 +    if (remainder || default_vq < 1 || default_vq > 512) {
 +        error_setg(errp, "cannot set sve-default-vector-length");
 +        if (remainder) {
 +            error_append_hint(errp, "Vector length not a multiple of 16\n");
 +        } else if (default_vq < 1) {
 +            error_append_hint(errp, "Vector length smaller than 16\n");
 +        } else {
 +            error_append_hint(errp, "Vector length larger than %d\n",
 +                              512 * 16);
 +        }
-+        return;
-+    }
-+
-+    cpu->sve_default_vq = default_vq;
-+}
-+
-+static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v,
-+                                            const char *name, void *opaque,
-+                                            Error **errp)
-+{
-+    ARMCPU *cpu = ARM_CPU(obj);
-+    int32_t value = cpu->sve_default_vq * 16;
-+
-+    visit_type_int32(v, name, &value, errp);
-+}
 +#endif
-+
++    }
  void aarch64_add_sve_properties(Object *obj)
  {
      uint32_t vq;
@@ -XXX,XX +XXX,XX @@ void aarch64_add_sve_properties(Object *obj)
          object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
                              cpu_arm_set_sve_vq, NULL, NULL);
      }
 +
 +#ifdef CONFIG_USER_ONLY
 +    /* Mirror linux /proc/sys/abi/sve_default_vector_length. */
 +    object_property_add(obj, "sve-default-vector-length", "int32",
 +                        cpu_arm_get_sve_default_vec_len,
 +                        cpu_arm_set_sve_default_vec_len, NULL, NULL);
 +#endif
  }
- void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
 --
-.20.1
+.34.1

-New patch
+[PULL 15/21] target/arm: Handle m-profile in arm_is_secure
+From: Richard Henderson <richard.henderson@linaro.org>
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1421
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227225832.816605-2-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 3 +++
+file changed, 3 insertions(+)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el3_or_mon(CPUARMState *env)
+ /* Return true if the processor is in secure state */
+ static inline bool arm_is_secure(CPUARMState *env)
+ {
++    if (arm_feature(env, ARM_FEATURE_M)) {
++        return env->v7m.secure;
++    }
+     if (arm_is_el3_or_mon(env)) {
+         return true;
+     }
+--
+.34.1

-[PULL 10/14] target/arm: Correctly bound length in sve_zcr_get_valid_len
+[PULL 16/21] target/arm: Stub arm_hcr_el2_eff for m-profile
 From: Richard Henderson <richard.henderson@linaro.org>
-Currently, our only caller is sve_zcr_len_for_el, which has
+M-profile doesn't have HCR_EL2.  While we could test features
-already masked the length extracted from ZCR_ELx, so the
+before each call, zero is a generally safe return value to
-masking done here is a nop.  But we will shortly have uses
+disable the code in the caller.  This test is required to
-from other locations, where the length will be unmasked.
+avoid an assert in arm_is_secure_below_el3.
-Saturate the length to ARM_MAX_VQ instead of truncating to
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 the low 4 bits.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230227225832.816605-3-richard.henderson@linaro.org
 Message-id: 20210723203344.968563-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 4 +++-
+ target/arm/helper.c | 3 +++
-file changed, 3 insertions(+), 1 deletion(-)
+file changed, 3 insertions(+)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
+@@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure)
  uint64_t arm_hcr_el2_eff(CPUARMState *env)
  {
-     uint32_t end_len;
++    if (arm_feature(env, ARM_FEATURE_M)) {
++        return 0;
--    end_len = start_len &= 0xf;
++    }
-+    start_len = MIN(start_len, ARM_MAX_VQ - 1);
+     return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env));
-+    end_len = start_len;
+ }
-+
      if (!test_bit(start_len, cpu->sve_vq_map)) {
          end_len = find_last_bit(cpu->sve_vq_map, start_len);
          assert(end_len < start_len);
 --
-.20.1
+.34.1

-[PULL 02/14] qemu-options.hx: Fix formatting of -machine memory-backend option
+[PULL 17/21] target/arm: Diagnose incorrect usage of arm_is_secure subroutines
-The documentation of the -machine memory-backend has some minor
+From: Richard Henderson <richard.henderson@linaro.org>
 formatting errors:
  * Misindentation of the initial line meant that the whole option
    section is incorrectly indented in the HTML output compared to
    the other -machine options
  * The examples weren't indented, which meant that they were formatted
    as plain run-on text including outputting the "::" as text.
  * The a) b) list has no rst-format markup so it is rendered as
    a single run-on paragraph
-Fix the formatting.
+In several places we use arm_is_secure_below_el3 and
 arm_is_el3_or_mon separately from arm_is_secure.
 These functions make no sense for m-profile, and
 would indicate prior incorrect feature testing.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230227225832.816605-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Igor Mammedov <imammedo@redhat.com>
-Message-id: 20210719105257.3599-1-peter.maydell@linaro.org
 ---
- qemu-options.hx | 30 +++++++++++++++++-------------
+ target/arm/cpu.h | 5 ++++-
-file changed, 17 insertions(+), 13 deletions(-)
+file changed, 4 insertions(+), 1 deletion(-)
-diff --git a/qemu-options.hx b/qemu-options.hx
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/qemu-options.hx
+--- a/target/arm/cpu.h
-+++ b/qemu-options.hx
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ SRST
+@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
-         Enables or disables ACPI Heterogeneous Memory Attribute Table
+ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
-         (HMAT) support. The default is off.
+ #if !defined(CONFIG_USER_ONLY)
--     ``memory-backend='id'``
+-/* Return true if exception levels below EL3 are in secure state,
-+    ``memory-backend='id'``
++/*
-         An alternative to legacy ``-mem-path`` and ``mem-prealloc`` options.
++ * Return true if exception levels below EL3 are in secure state,
-         Allows to use a memory backend as main RAM.
+  * or would be following an exception return to that level.
+  * Unlike arm_is_secure() (which is always a question about the
-         For example:
+  * _current_ state of the CPU) this doesn't care about the current
-         ::
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
--        -object memory-backend-file,id=pc.ram,size=512M,mem-path=/hugetlbfs,prealloc=on,share=on
+  */
--        -machine memory-backend=pc.ram
+ static inline bool arm_is_secure_below_el3(CPUARMState *env)
--        -m 512M
+ {
-+
++    assert(!arm_feature(env, ARM_FEATURE_M));
-+            -object memory-backend-file,id=pc.ram,size=512M,mem-path=/hugetlbfs,prealloc=on,share=on
+     if (arm_feature(env, ARM_FEATURE_EL3)) {
-+            -machine memory-backend=pc.ram
+         return !(env->cp15.scr_el3 & SCR_NS);
-+            -m 512M
+     } else {
+@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
-         Migration compatibility note:
+ /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
--        a) as backend id one shall use value of 'default-ram-id', advertised by
+ static inline bool arm_is_el3_or_mon(CPUARMState *env)
--        machine type (available via ``query-machines`` QMP command), if migration
+ {
--        to/from old QEMU (<5.0) is expected.
++    assert(!arm_feature(env, ARM_FEATURE_M));
--        b) for machine types 4.0 and older, user shall
+     if (arm_feature(env, ARM_FEATURE_EL3)) {
--        use ``x-use-canonical-path-for-ramblock-id=off`` backend option
+         if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
--        if migration to/from old QEMU (<5.0) is expected.
+             /* CPU currently in AArch64 state and EL3 */
 +
 +        * as backend id one shall use value of 'default-ram-id', advertised by
 +          machine type (available via ``query-machines`` QMP command), if migration
 +          to/from old QEMU (<5.0) is expected.
 +        * for machine types 4.0 and older, user shall
 +          use ``x-use-canonical-path-for-ramblock-id=off`` backend option
 +          if migration to/from old QEMU (<5.0) is expected.
 +
          For example:
          ::
 -        -object memory-backend-ram,id=pc.ram,size=512M,x-use-canonical-path-for-ramblock-id=off
 -        -machine memory-backend=pc.ram
 -        -m 512M
 +
 +            -object memory-backend-ram,id=pc.ram,size=512M,x-use-canonical-path-for-ramblock-id=off
 +            -machine memory-backend=pc.ram
 +            -m 512M
  ERST
  HXCOMM Deprecated by -machine
 --
-.20.1
+.34.1

-[PULL 06/14] hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
+[PULL 18/21] target/arm: Rewrite check_s2_mmu_setup
-The ISCR.ISRPENDING bit is set when an external interrupt is pending.
+From: Richard Henderson <richard.henderson@linaro.org>
-This is true whether that external interrupt is enabled or not.
-This means that we can't use 's->vectpending == 0' as a shortcut to
+Integrate neighboring code from get_phys_addr_lpae which computed
-"ISRPENDING is zero", because s->vectpending indicates only the
+starting level, as it is easier to validate when doing both at the
-highest priority pending enabled interrupt.
+same time.  Mirror the checks at the start of AArch{64,32}.S2Walk,
+especially S2InvalidSL and S2InconsistentSL.
-Remove the incorrect optimization so that if there is no pending
-enabled interrupt we fall through to scanning through the whole
+This reverts 49ba115bb74, which was incorrect -- there is nothing
-interrupt array.
+in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the
+pseudocode is consistent in referencing PAMax.
 Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup")
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230227225832.816605-5-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210723162146.5167-5-peter.maydell@linaro.org
 ---
- hw/intc/armv7m_nvic.c | 9 ++++-----
+ target/arm/ptw.c | 173 ++++++++++++++++++++++++++---------------------
-file changed, 4 insertions(+), 5 deletions(-)
+file changed, 97 insertions(+), 76 deletions(-)
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/armv7m_nvic.c
+--- a/target/arm/ptw.c
-+++ b/hw/intc/armv7m_nvic.c
++++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
+@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
   * check_s2_mmu_setup
   * @cpu:        ARMCPU
   * @is_aa64:    True if the translation regime is in AArch64 state
 - * @startlevel: Suggested starting level
 - * @inputsize:  Bitsize of IPAs
 + * @tcr:        VTCR_EL2 or VSTCR_EL2
 + * @ds:         Effective value of TCR.DS.
 + * @iasize:     Bitsize of IPAs
   * @stride:     Page-table stride (See the ARM ARM)
   *
 - * Returns true if the suggested S2 translation parameters are OK and
 - * false otherwise.
 + * Decode the starting level of the S2 lookup, returning INT_MIN if
 + * the configuration is invalid.
   */
 -static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
 -                               int inputsize, int stride, int outputsize)
 +static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr,
 +                              bool ds, int iasize, int stride)
  {
-     int irq;
+-    const int grainsize = stride + 3;
+-    int startsizecheck;
--    /* We can shortcut if the highest priority pending interrupt
+-
--     * happens to be external or if there is nothing pending.
+-    /*
-+    /*
+-     * Negative levels are usually not allowed...
-+     * We can shortcut if the highest priority pending interrupt
+-     * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
-+     * happens to be external; if not we need to check the whole
+-     * begins with level -1.  Note that previous feature tests will have
-+     * vectors[] array.
+-     * eliminated this combination if it is not enabled.
-      */
+-     */
-     if (s->vectpending > NVIC_FIRST_IRQ) {
+-    if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) {
          return true;
      }
 -    if (s->vectpending == 0) {
 -        return false;
 -    }
+-
-     for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) {
+-    startsizecheck = inputsize - ((3 - level) * stride + grainsize);
-         if (s->vectors[irq].pending) {
+-    if (startsizecheck < 1 || startsizecheck > stride + 4) {
 -        return false;
 -    }
 +    int sl0, sl2, startlevel, granulebits, levels;
 +    int s1_min_iasize, s1_max_iasize;
 +    sl0 = extract32(tcr, 6, 2);
      if (is_aa64) {
 +        /*
 +         * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of
 +         * get_phys_addr_lpae, that used aa64_va_parameters which apply
 +         * to aarch64.  If Stage1 is aarch32, the min_txsz is larger.
 +         * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to
 +         * inputsize is 64 - 24 = 40.
 +         */
 +        if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) {
 +            goto fail;
 +        }
 +
 +        /*
 +         * AArch64.S2InvalidSL: Interpretation of SL depends on the page size,
 +         * so interleave AArch64.S2StartLevel.
 +         */
          switch (stride) {
 -        case 13: /* 64KB Pages.  */
 -            if (level == 0 || (level == 1 && outputsize <= 42)) {
 -                return false;
 +        case 9: /* 4KB */
 +            /* SL2 is RES0 unless DS=1 & 4KB granule. */
 +            sl2 = extract64(tcr, 33, 1);
 +            if (ds && sl2) {
 +                if (sl0 != 0) {
 +                    goto fail;
 +                }
 +                startlevel = -1;
 +            } else {
 +                startlevel = 2 - sl0;
 +                switch (sl0) {
 +                case 2:
 +                    if (arm_pamax(cpu) < 44) {
 +                        goto fail;
 +                    }
 +                    break;
 +                case 3:
 +                    if (!cpu_isar_feature(aa64_st, cpu)) {
 +                        goto fail;
 +                    }
 +                    startlevel = 3;
 +                    break;
 +                }
              }
              break;
 -        case 11: /* 16KB Pages.  */
 -            if (level == 0 || (level == 1 && outputsize <= 40)) {
 -                return false;
 +        case 11: /* 16KB */
 +            switch (sl0) {
 +            case 2:
 +                if (arm_pamax(cpu) < 42) {
 +                    goto fail;
 +                }
 +                break;
 +            case 3:
 +                if (!ds) {
 +                    goto fail;
 +                }
 +                break;
              }
 +            startlevel = 3 - sl0;
              break;
 -        case 9: /* 4KB Pages.  */
 -            if (level == 0 && outputsize <= 42) {
 -                return false;
 +        case 13: /* 64KB */
 +            switch (sl0) {
 +            case 2:
 +                if (arm_pamax(cpu) < 44) {
 +                    goto fail;
 +                }
 +                break;
 +            case 3:
 +                goto fail;
              }
 +            startlevel = 3 - sl0;
              break;
          default:
              g_assert_not_reached();
          }
 -
 -        /* Inputsize checks.  */
 -        if (inputsize > outputsize &&
 -            (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) {
 -            /* This is CONSTRAINED UNPREDICTABLE and we choose to fault.  */
 -            return false;
 -        }
      } else {
 -        /* AArch32 only supports 4KB pages. Assert on that.  */
 +        /*
 +         * Things are simpler for AArch32 EL2, with only 4k pages.
 +         * There is no separate S2InvalidSL function, but AArch32.S2Walk
 +         * begins with walkparms.sl0 in {'1x'}.
 +         */
          assert(stride == 9);
 -
 -        if (level == 0) {
 -            return false;
 +        if (sl0 >= 2) {
 +            goto fail;
          }
 +        startlevel = 2 - sl0;
      }
 -    return true;
 +
 +    /* AArch{64,32}.S2InconsistentSL are functionally equivalent.  */
 +    levels = 3 - startlevel;
 +    granulebits = stride + 3;
 +
 +    s1_min_iasize = levels * stride + granulebits + 1;
 +    s1_max_iasize = s1_min_iasize + (stride - 1) + 4;
 +
 +    if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) {
 +        return startlevel;
 +    }
 +
 + fail:
 +    return INT_MIN;
  }
  /**
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
           */
          level = 4 - (inputsize - 4) / stride;
      } else {
 -        /*
 -         * For stage 2 translations the starting level is specified by the
 -         * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
 -         */
 -        uint32_t sl0 = extract32(tcr, 6, 2);
 -        uint32_t sl2 = extract64(tcr, 33, 1);
 -        int32_t startlevel;
 -        bool ok;
 -
 -        /* SL2 is RES0 unless DS=1 & 4kb granule. */
 -        if (param.ds && stride == 9 && sl2) {
 -            if (sl0 != 0) {
 -                level = 0;
 -                goto do_translation_fault;
 -            }
 -            startlevel = -1;
 -        } else if (!aarch64 || stride == 9) {
 -            /* AArch32 or 4KB pages */
 -            startlevel = 2 - sl0;
 -
 -            if (cpu_isar_feature(aa64_st, cpu)) {
 -                startlevel &= 3;
 -            }
 -        } else {
 -            /* 16KB or 64KB pages */
 -            startlevel = 3 - sl0;
 -        }
 -
 -        /* Check that the starting level is valid. */
 -        ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
 -                                inputsize, stride, outputsize);
 -        if (!ok) {
 +        int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds,
 +                                            inputsize, stride);
 +        if (startlevel == INT_MIN) {
 +            level = 0;
              goto do_translation_fault;
          }
          level = startlevel;
 --
-.20.1
+.34.1

-[PULL 13/14] hw/arm/nseries: Display hexadecimal value with '0x' prefix
+[PULL 19/21] hw: arm: Support direct boot for Linux/arm64 EFI zboot images
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Ard Biesheuvel <ardb@kernel.org>
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Fedora 39 will ship its arm64 kernels in the new generic EFI zboot
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+format, using gzip compression for the payload.
-Message-id: 20210726150953.1218690-1-f4bug@amsat.org
 For doing EFI boot in QEMU, this is completely transparent, as the
 firmware or bootloader will take care of this. However, for direct
 kernel boot without firmware, we will lose the ability to boot such
 distro kernels unless we deal with the new format directly.
 EFI zboot images contain metadata in the header regarding the placement
 of the compressed payload inside the image, and the type of compression
 used. This means we can wire up the existing gzip support without too
 much hassle, by parsing the header and grabbing the payload from inside
 the loaded zboot image.
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Cc: Alex Bennée <alex.bennee@linaro.org>
 Cc: Richard Henderson <richard.henderson@linaro.org>
 Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
 Message-id: 20230303160109.3626966-1-ardb@kernel.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 [PMM: tweaked comment formatting, fixed checkpatch nits]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/nseries.c | 2 +-
+ include/hw/loader.h | 19 ++++++++++
-file changed, 1 insertion(+), 1 deletion(-)
+ hw/arm/boot.c       |  6 +++
  hw/core/loader.c    | 91 +++++++++++++++++++++++++++++++++++++++++++++
 files changed, 116 insertions(+)
-diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
+diff --git a/include/hw/loader.h b/include/hw/loader.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/nseries.c
+--- a/include/hw/loader.h
-+++ b/hw/arm/nseries.c
++++ b/include/hw/loader.h
-@@ -XXX,XX +XXX,XX @@ static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
+@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
-     default:
+                                   uint8_t **buffer);
-     bad_cmd:
+ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz);
-         qemu_log_mask(LOG_GUEST_ERROR,
--                      "%s: unknown command %02x\n", __func__, s->cmd);
++/**
-+                      "%s: unknown command 0x%02x\n", __func__, s->cmd);
++ * unpack_efi_zboot_image:
-         break;
++ * @buffer: pointer to a variable holding the address of a buffer containing the
 + *          image
 + * @size: pointer to a variable holding the size of the buffer
 + *
 + * Check whether the buffer contains a EFI zboot image, and if it does, extract
 + * the compressed payload and decompress it into a new buffer. If successful,
 + * the old buffer is freed, and the *buffer and size variables pointed to by the
 + * function arguments are updated to refer to the newly populated buffer.
 + *
 + * Returns 0 if the image could not be identified as a EFI zboot image.
 + * Returns -1 if the buffer contents were identified as a EFI zboot image, but
 + * unpacking failed for any reason.
 + * Returns the size of the decompressed payload if decompression was performed
 + * successfully.
 + */
 +ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size);
 +
  #define ELF_LOAD_FAILED       -1
  #define ELF_LOAD_NOT_ELF      -2
  #define ELF_LOAD_WRONG_ARCH   -3
 diff --git a/hw/arm/boot.c b/hw/arm/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/boot.c
 +++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
              return -1;
          }
          size = len;
 +
 +        /* Unpack the image if it is a EFI zboot image */
 +        if (unpack_efi_zboot_image(&buffer, &size) < 0) {
 +            g_free(buffer);
 +            return -1;
 +        }
      }
+     /* check the arm64 magic header value -- very old kernels may not have it */
+diff --git a/hw/core/loader.c b/hw/core/loader.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/core/loader.c
++++ b/hw/core/loader.c
+@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz)
+     return bytes;
+ }
++/* The PE/COFF MS-DOS stub magic number */
++#define EFI_PE_MSDOS_MAGIC        "MZ"
++
++/*
++ * The Linux header magic number for a EFI PE/COFF
++ * image targetting an unspecified architecture.
++ */
++#define EFI_PE_LINUX_MAGIC        "\xcd\x23\x82\x81"
++
++/*
++ * Bootable Linux kernel images may be packaged as EFI zboot images, which are
++ * self-decompressing executables when loaded via EFI. The compressed payload
++ * can also be extracted from the image and decompressed by a non-EFI loader.
++ *
++ * The de facto specification for this format is at the following URL:
++ *
++ * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/efi/libstub/zboot-header.S
++ *
++ * This definition is based on Linux upstream commit 29636a5ce87beba.
++ */
++struct linux_efi_zboot_header {
++    uint8_t     msdos_magic[2];         /* PE/COFF 'MZ' magic number */
++    uint8_t     reserved0[2];
++    uint8_t     zimg[4];                /* "zimg" for Linux EFI zboot images */
++    uint32_t    payload_offset;         /* LE offset to compressed payload */
++    uint32_t    payload_size;           /* LE size of the compressed payload */
++    uint8_t     reserved1[8];
++    char        compression_type[32];   /* Compression type, NUL terminated */
++    uint8_t     linux_magic[4];         /* Linux header magic */
++    uint32_t    pe_header_offset;       /* LE offset to the PE header */
++};
++
++/*
++ * Check whether *buffer points to a Linux EFI zboot image in memory.
++ *
++ * If it does, attempt to decompress it to a new buffer, and free the old one.
++ * If any of this fails, return an error to the caller.
++ *
++ * If the image is not a Linux EFI zboot image, do nothing and return success.
++ */
++ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size)
++{
++    const struct linux_efi_zboot_header *header;
++    uint8_t *data = NULL;
++    int ploff, plsize;
++    ssize_t bytes;
++
++    /* ignore if this is too small to be a EFI zboot image */
++    if (*size < sizeof(*header)) {
++        return 0;
++    }
++
++    header = (struct linux_efi_zboot_header *)*buffer;
++
++    /* ignore if this is not a Linux EFI zboot image */
++    if (memcmp(&header->msdos_magic, EFI_PE_MSDOS_MAGIC, 2) != 0 ||
++        memcmp(&header->zimg, "zimg", 4) != 0 ||
++        memcmp(&header->linux_magic, EFI_PE_LINUX_MAGIC, 4) != 0) {
++        return 0;
++    }
++
++    if (strcmp(header->compression_type, "gzip") != 0) {
++        fprintf(stderr,
++                "unable to handle EFI zboot image with \"%.*s\" compression\n",
++                (int)sizeof(header->compression_type) - 1,
++                header->compression_type);
++        return -1;
++    }
++
++    ploff = ldl_le_p(&header->payload_offset);
++    plsize = ldl_le_p(&header->payload_size);
++
++    if (ploff < 0 || plsize < 0 || ploff + plsize > *size) {
++        fprintf(stderr, "unable to handle corrupt EFI zboot image\n");
++        return -1;
++    }
++
++    data = g_malloc(LOAD_IMAGE_MAX_GUNZIP_BYTES);
++    bytes = gunzip(data, LOAD_IMAGE_MAX_GUNZIP_BYTES, *buffer + ploff, plsize);
++    if (bytes < 0) {
++        fprintf(stderr, "failed to decompress EFI zboot image\n");
++        g_free(data);
++        return -1;
++    }
++
++    g_free(*buffer);
++    *buffer = g_realloc(data, bytes);
++    *size = bytes;
++    return bytes;
++}
++
+ /*
+  * Functions for reboot-persistent memory regions.
+  *  - used for vga bios and option roms.
 --
-.20.1
+.34.1

-New patch
+[PULL 20/21] hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
+From: qianfan Zhao <qianfanguijin@163.com>
+TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect)
+register on SUN6i based SoCs, we should lower interrupt when the guest
+set this bit.
+The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no
+device connected on the i2c bus, next is the trace log:
+allwinner_i2c_write write   CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN
+allwinner_i2c_write write   CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
+allwinner_i2c_read  read    CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
+allwinner_i2c_read  read    STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK
+allwinner_i2c_write write   CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
+allwinner_i2c_write write   CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
+allwinner_i2c_read  read    CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
+allwinner_i2c_read  read    STAT(0x10): 0xf8 STAT_IDLE
+allwinner_i2c_write write   CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
+allwinner_i2c_write write   CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
+allwinner_i2c_read  read    CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
+allwinner_i2c_read  read    STAT(0x10): 0xf8 STAT_IDLE
+...
+Fix it.
+Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
+Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+Tested-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/i2c/allwinner-i2c.h |  6 ++++++
+ hw/i2c/allwinner-i2c.c         | 26 ++++++++++++++++++++++++--
+files changed, 30 insertions(+), 2 deletions(-)
+diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/i2c/allwinner-i2c.h
++++ b/include/hw/i2c/allwinner-i2c.h
+@@ -XXX,XX +XXX,XX @@
+ #include "qom/object.h"
+ #define TYPE_AW_I2C "allwinner.i2c"
++
++/** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */
++#define TYPE_AW_I2C_SUN6I    TYPE_AW_I2C "-sun6i"
++
+ OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
+ #define AW_I2C_MEM_SIZE         0x24
+@@ -XXX,XX +XXX,XX @@ struct AWI2CState {
+     uint8_t srst;
+     uint8_t efr;
+     uint8_t lcr;
++
++    bool irq_clear_inverted;
+ };
+ #endif /* ALLWINNER_I2C_H */
+diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/i2c/allwinner-i2c.c
++++ b/hw/i2c/allwinner-i2c.c
+@@ -XXX,XX +XXX,XX @@ static void allwinner_i2c_write(void *opaque, hwaddr offset,
+                 s->stat = STAT_FROM_STA(STAT_IDLE);
+                 s->cntr &= ~TWI_CNTR_M_STP;
+             }
+-            if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
+-                /* Interrupt flag cleared */
++
++            if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) {
++                /* Write 0 to clear this flag */
++                qemu_irq_lower(s->irq);
++            } else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) {
++                /* Write 1 to clear this flag */
++                s->cntr &= ~TWI_CNTR_INT_FLAG;
+                 qemu_irq_lower(s->irq);
+             }
++
+             if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
+                 if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
+                     s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo allwinner_i2c_type_info = {
+     .class_init = allwinner_i2c_class_init,
+ };
++static void allwinner_i2c_sun6i_init(Object *obj)
++{
++    AWI2CState *s = AW_I2C(obj);
++
++    s->irq_clear_inverted = true;
++}
++
++static const TypeInfo allwinner_i2c_sun6i_type_info = {
++    .name = TYPE_AW_I2C_SUN6I,
++    .parent = TYPE_SYS_BUS_DEVICE,
++    .instance_size = sizeof(AWI2CState),
++    .instance_init = allwinner_i2c_sun6i_init,
++    .class_init = allwinner_i2c_class_init,
++};
++
+ static void allwinner_i2c_register_types(void)
+ {
+     type_register_static(&allwinner_i2c_type_info);
++    type_register_static(&allwinner_i2c_sun6i_type_info);
+ }
+ type_init(allwinner_i2c_register_types)
+--
+.34.1

-[PULL 01/14] hw/arm/smmuv3: Check 31st bit to see if CD is valid
+[PULL 21/21] hw: arm: allwinner-h3: Fix and complete H3 i2c devices
-From: Joe Komlodi <joe.komlodi@xilinx.com>
+From: qianfan Zhao <qianfanguijin@163.com>
-The bit to see if a CD is valid is the last bit of the first word of the CD.
+Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi.
 The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear
 control register's INT_FLAG bit.
-Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
+Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
-Message-id: 1626728232-134665-2-git-send-email-joe.komlodi@xilinx.com
+Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/smmuv3-internal.h | 2 +-
+ include/hw/arm/allwinner-h3.h |  6 ++++++
-file changed, 1 insertion(+), 1 deletion(-)
+ hw/arm/allwinner-h3.c         | 29 +++++++++++++++++++++++++----
 files changed, 31 insertions(+), 4 deletions(-)
-diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
+diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/smmuv3-internal.h
+--- a/include/hw/arm/allwinner-h3.h
-+++ b/hw/arm/smmuv3-internal.h
++++ b/include/hw/arm/allwinner-h3.h
-@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)
+@@ -XXX,XX +XXX,XX @@ enum {
+     AW_H3_DEV_UART3,
- /* CD fields */
+     AW_H3_DEV_EMAC,
+     AW_H3_DEV_TWI0,
--#define CD_VALID(x)   extract32((x)->word[0], 30, 1)
++    AW_H3_DEV_TWI1,
-+#define CD_VALID(x)   extract32((x)->word[0], 31, 1)
++    AW_H3_DEV_TWI2,
- #define CD_ASID(x)    extract32((x)->word[1], 16, 16)
+     AW_H3_DEV_DRAMCOM,
- #define CD_TTB(x, sel)                                      \
+     AW_H3_DEV_DRAMCTL,
-     ({                                                      \
+     AW_H3_DEV_DRAMPHY,
@@ -XXX,XX +XXX,XX @@ enum {
      AW_H3_DEV_GIC_VCPU,
      AW_H3_DEV_RTC,
      AW_H3_DEV_CPUCFG,
 +    AW_H3_DEV_R_TWI,
      AW_H3_DEV_SDRAM
  };
@@ -XXX,XX +XXX,XX @@ struct AwH3State {
      AwSidState sid;
      AwSdHostState mmc0;
      AWI2CState i2c0;
 +    AWI2CState i2c1;
 +    AWI2CState i2c2;
 +    AWI2CState r_twi;
      AwSun8iEmacState emac;
      AwRtcState rtc;
      GICState gic;
 diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/allwinner-h3.c
 +++ b/hw/arm/allwinner-h3.c
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
      [AW_H3_DEV_UART2]      = 0x01c28800,
      [AW_H3_DEV_UART3]      = 0x01c28c00,
      [AW_H3_DEV_TWI0]       = 0x01c2ac00,
 +    [AW_H3_DEV_TWI1]       = 0x01c2b000,
 +    [AW_H3_DEV_TWI2]       = 0x01c2b400,
      [AW_H3_DEV_EMAC]       = 0x01c30000,
      [AW_H3_DEV_DRAMCOM]    = 0x01c62000,
      [AW_H3_DEV_DRAMCTL]    = 0x01c63000,
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
      [AW_H3_DEV_GIC_VCPU]   = 0x01c86000,
      [AW_H3_DEV_RTC]        = 0x01f00000,
      [AW_H3_DEV_CPUCFG]     = 0x01f01c00,
 +    [AW_H3_DEV_R_TWI]      = 0x01f02400,
      [AW_H3_DEV_SDRAM]      = 0x40000000
  };
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
      { "uart1",     0x01c28400, 1 * KiB },
      { "uart2",     0x01c28800, 1 * KiB },
      { "uart3",     0x01c28c00, 1 * KiB },
 -    { "twi1",      0x01c2b000, 1 * KiB },
 -    { "twi2",      0x01c2b400, 1 * KiB },
      { "scr",       0x01c2c400, 1 * KiB },
      { "gpu",       0x01c40000, 64 * KiB },
      { "hstmr",     0x01c60000, 4 * KiB },
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
      { "r_prcm",    0x01f01400, 1 * KiB },
      { "r_twd",     0x01f01800, 1 * KiB },
      { "r_cir-rx",  0x01f02000, 1 * KiB },
 -    { "r_twi",     0x01f02400, 1 * KiB },
      { "r_uart",    0x01f02800, 1 * KiB },
      { "r_pio",     0x01f02c00, 1 * KiB },
      { "r_pwm",     0x01f03800, 1 * KiB },
@@ -XXX,XX +XXX,XX @@ enum {
      AW_H3_GIC_SPI_UART2     =  2,
      AW_H3_GIC_SPI_UART3     =  3,
      AW_H3_GIC_SPI_TWI0      =  6,
 +    AW_H3_GIC_SPI_TWI1      =  7,
 +    AW_H3_GIC_SPI_TWI2      =  8,
      AW_H3_GIC_SPI_TIMER0    = 18,
      AW_H3_GIC_SPI_TIMER1    = 19,
 +    AW_H3_GIC_SPI_R_TWI     = 44,
      AW_H3_GIC_SPI_MMC0      = 60,
      AW_H3_GIC_SPI_EHCI0     = 72,
      AW_H3_GIC_SPI_OHCI0     = 73,
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
      object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
 -    object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
 +    object_initialize_child(obj, "twi0",  &s->i2c0,  TYPE_AW_I2C_SUN6I);
 +    object_initialize_child(obj, "twi1",  &s->i2c1,  TYPE_AW_I2C_SUN6I);
 +    object_initialize_child(obj, "twi2",  &s->i2c2,  TYPE_AW_I2C_SUN6I);
 +    object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I);
  }
  static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
                         qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
 +    sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0,
 +                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1));
 +
 +    sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0,
 +                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2));
 +
 +    sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0,
 +                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI));
 +
      /* Unimplemented devices */
      for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
          create_unimplemented_device(unimplemented[i].device_name,
 --
-.20.1
+.34.1

arm pullreq for rc1. All minor bugfixes, except for the sve-default-vector-length
patches, which are somewhere between a bugfix and a new feature.

thanks
-- PMM

The following changes since commit c08ccd1b53f488ac86c1f65cf7623dc91acc249a:

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210726' into staging (2021-07-27 08:35:01 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210727

for you to fetch changes up to e229a179a503f2aee43a76888cf12fbdfe8a3749:

hw: aspeed_gpio: Fix memory size (2021-07-27 11:00:00 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/smmuv3: Check 31st bit to see if CD is valid
 * qemu-options.hx: Fix formatting of -machine memory-backend option
 * hw: aspeed_gpio: Fix memory size
 * hw/arm/nseries: Display hexadecimal value with '0x' prefix
 * Add sve-default-vector-length cpu property
 * docs: Update path that mentions deprecated.rst
 * hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
 * hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
 * hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
 * target/arm: Report M-profile alignment faults correctly to the guest
 * target/arm: Add missing 'return's after calling v7m_exception_taken()
 * target/arm: Enforce that M-profile SP low 2 bits are always zero

----------------------------------------------------------------
Joe Komlodi (1):
      hw/arm/smmuv3: Check 31st bit to see if CD is valid

Joel Stanley (1):
      hw: aspeed_gpio: Fix memory size

Mao Zhongyi (1):
      docs: Update path that mentions deprecated.rst

Peter Maydell (7):
      qemu-options.hx: Fix formatting of -machine memory-backend option
      target/arm: Enforce that M-profile SP low 2 bits are always zero
      target/arm: Add missing 'return's after calling v7m_exception_taken()
      target/arm: Report M-profile alignment faults correctly to the guest
      hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
      hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
      hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS

Philippe Mathieu-Daudé (1):
      hw/arm/nseries: Display hexadecimal value with '0x' prefix

Richard Henderson (3):
      target/arm: Correctly bound length in sve_zcr_get_valid_len
      target/arm: Export aarch64_sve_zcr_get_valid_len
      target/arm: Add sve-default-vector-length cpu property

The documentation of the -machine memory-backend has some minor
formatting errors:
 * Misindentation of the initial line meant that the whole option
   section is incorrectly indented in the HTML output compared to
   the other -machine options
 * The examples weren't indented, which meant that they were formatted
   as plain run-on text including outputting the "::" as text.
 * The a) b) list has no rst-format markup so it is rendered as
   a single run-on paragraph

Fix the formatting.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20210719105257.3599-1-peter.maydell@linaro.org
---
 qemu-options.hx | 30 +++++++++++++++++-------------
 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/qemu-options.hx b/qemu-options.hx
index XXXXXXX..XXXXXXX 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -XXX,XX +XXX,XX @@ SRST
         Enables or disables ACPI Heterogeneous Memory Attribute Table
         (HMAT) support. The default is off.
 
-     ``memory-backend='id'``
+    ``memory-backend='id'``
         An alternative to legacy ``-mem-path`` and ``mem-prealloc`` options.
         Allows to use a memory backend as main RAM.
 
         For example:
         ::
-        -object memory-backend-file,id=pc.ram,size=512M,mem-path=/hugetlbfs,prealloc=on,share=on
-        -machine memory-backend=pc.ram
-        -m 512M
+
+            -object memory-backend-file,id=pc.ram,size=512M,mem-path=/hugetlbfs,prealloc=on,share=on
+            -machine memory-backend=pc.ram
+            -m 512M
 
         Migration compatibility note:
-        a) as backend id one shall use value of 'default-ram-id', advertised by
-        machine type (available via ``query-machines`` QMP command), if migration
-        to/from old QEMU (<5.0) is expected.
-        b) for machine types 4.0 and older, user shall
-        use ``x-use-canonical-path-for-ramblock-id=off`` backend option
-        if migration to/from old QEMU (<5.0) is expected.
+
+        * as backend id one shall use value of 'default-ram-id', advertised by
+          machine type (available via ``query-machines`` QMP command), if migration
+          to/from old QEMU (<5.0) is expected.
+        * for machine types 4.0 and older, user shall
+          use ``x-use-canonical-path-for-ramblock-id=off`` backend option
+          if migration to/from old QEMU (<5.0) is expected.
+
         For example:
         ::
-        -object memory-backend-ram,id=pc.ram,size=512M,x-use-canonical-path-for-ramblock-id=off
-        -machine memory-backend=pc.ram
-        -m 512M
+
+            -object memory-backend-ram,id=pc.ram,size=512M,x-use-canonical-path-for-ramblock-id=off
+            -machine memory-backend=pc.ram
+            -m 512M
 ERST
 
 HXCOMM Deprecated by -machine
-- 
2.20.1

For M-profile, unlike A-profile, the low 2 bits of SP are defined to be
RES0H, which is to say that they must be hardwired to zero so that
guest attempts to write non-zero values to them are ignored.

Implement this behaviour by masking out the low bits:
 * for writes to r13 by the gdbstub
 * for writes to any of the various flavours of SP via MSR
 * for writes to r13 via store_reg() in generated code

Note that all the direct uses of cpu_R[] in translate.c are in places
where the register is definitely not r13 (usually because that has
been checked for as an UNDEFINED or UNPREDICTABLE case and handled as
UNDEF).

All the other writes to regs[13] in C code are either:
 * A-profile only code
 * writes of values we can guarantee to be aligned, such as
   - writes of previous-SP-value plus or minus a 4-aligned constant
   - writes of the value in an SP limit register (which we already
     enforce to be aligned)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-2-peter.maydell@linaro.org
---
 target/arm/gdbstub.c   |  4 ++++
 target/arm/m_helper.c  | 14 ++++++++------
 target/arm/translate.c |  3 +++
 3 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 
     if (n < 16) {
         /* Core integer register.  */
+        if (n == 13 && arm_feature(env, ARM_FEATURE_M)) {
+            /* M profile SP low bits are always 0 */
+            tmp &= ~3;
+        }
         env->regs[n] = tmp;
         return 4;
     }
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
             if (!env->v7m.secure) {
                 return;
             }
-            env->v7m.other_ss_msp = val;
+            env->v7m.other_ss_msp = val & ~3;
             return;
         case 0x89: /* PSP_NS */
             if (!env->v7m.secure) {
                 return;
             }
-            env->v7m.other_ss_psp = val;
+            env->v7m.other_ss_psp = val & ~3;
             return;
         case 0x8a: /* MSPLIM_NS */
             if (!env->v7m.secure) {
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
 
             limit = is_psp ? env->v7m.psplim[false] : env->v7m.msplim[false];
 
+            val &= ~0x3;
+
             if (val < limit) {
                 raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC());
             }
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
         break;
     case 8: /* MSP */
         if (v7m_using_psp(env)) {
-            env->v7m.other_sp = val;
+            env->v7m.other_sp = val & ~3;
         } else {
-            env->regs[13] = val;
+            env->regs[13] = val & ~3;
         }
         break;
     case 9: /* PSP */
         if (v7m_using_psp(env)) {
-            env->regs[13] = val;
+            env->regs[13] = val & ~3;
         } else {
-            env->v7m.other_sp = val;
+            env->v7m.other_sp = val & ~3;
         }
         break;
     case 10: /* MSPLIM */
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void store_reg(DisasContext *s, int reg, TCGv_i32 var)
          */
         tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3);
         s->base.is_jmp = DISAS_JUMP;
+    } else if (reg == 13 && arm_dc_feature(s, ARM_FEATURE_M)) {
+        /* For M-profile SP bits [1:0] are always zero */
+        tcg_gen_andi_i32(var, var, ~3);
     }
     tcg_gen_mov_i32(cpu_R[reg], var);
     tcg_temp_free_i32(var);
-- 
2.20.1

In do_v7m_exception_exit(), we perform various checks as part of
performing the exception return.  If one of these checks fails, the
architecture requires that we take an appropriate exception on the
existing stackframe.  We implement this by calling
v7m_exception_taken() to set up to take the new exception, and then
immediately returning from do_v7m_exception_exit() without proceeding
any further with the unstack-and-exception-return process.

In a couple of checks that are new in v8.1M, we forgot the "return"
statement, with the effect that if bad code in the guest tripped over
these checks we would set up to take a UsageFault exception but then
blunder on trying to also unstack and return from the original
exception, with the probable result that the guest would crash.

Add the missing return statements.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-3-peter.maydell@linaro.org
---
 target/arm/m_helper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
                     qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
                         "stackframe: NSACR prevents clearing FPU registers\n");
                     v7m_exception_taken(cpu, excret, true, false);
+                    return;
                 } else if (!cpacr_pass) {
                     armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
                                             exc_secure);
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
                     qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
                         "stackframe: CPACR prevents clearing FPU registers\n");
                     v7m_exception_taken(cpu, excret, true, false);
+                    return;
                 }
             }
             /* Clear s0..s15, FPSCR and VPR */
-- 
2.20.1

For M-profile, we weren't reporting alignment faults triggered by the
generic TCG code correctly to the guest.  These get passed into
arm_v7m_cpu_do_interrupt() as an EXCP_DATA_ABORT with an A-profile
style exception.fsr value of 1.  We didn't check for this, and so
they fell through into the default of "assume this is an MPU fault"
and were reported to the guest as a data access violation MPU fault.

Report these alignment faults as UsageFaults which set the UNALIGNED
bit in the UFSR.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-4-peter.maydell@linaro.org
---
 target/arm/m_helper.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
         env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK;
         break;
     case EXCP_UNALIGNED:
+        /* Unaligned faults reported by M-profile aware code */
         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
         env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;
         break;
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
             }
             armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
             break;
+        case 0x1: /* Alignment fault reported by generic code */
+            qemu_log_mask(CPU_LOG_INT,
+                          "...really UsageFault with UFSR.UNALIGNED\n");
+            env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;
+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
+                                    env->v7m.secure);
+            break;
         default:
             /*
              * All other FSR values are either MPU faults or "can't happen
-- 
2.20.1

The ISCR.ISRPENDING bit is set when an external interrupt is pending.
This is true whether that external interrupt is enabled or not.
This means that we can't use 's->vectpending == 0' as a shortcut to
"ISRPENDING is zero", because s->vectpending indicates only the
highest priority pending enabled interrupt.

Remove the incorrect optimization so that if there is no pending
enabled interrupt we fall through to scanning through the whole
interrupt array.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-5-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
 {
     int irq;
 
-    /* We can shortcut if the highest priority pending interrupt
-     * happens to be external or if there is nothing pending.
+    /*
+     * We can shortcut if the highest priority pending interrupt
+     * happens to be external; if not we need to check the whole
+     * vectors[] array.
      */
     if (s->vectpending > NVIC_FIRST_IRQ) {
         return true;
     }
-    if (s->vectpending == 0) {
-        return false;
-    }
 
     for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) {
         if (s->vectors[irq].pending) {
-- 
2.20.1

The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of
the register.  We were incorrectly masking it to 8 bits, so it would
report the wrong value if the pending exception was greater than 256.
Fix the bug.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-6-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
         /* VECTACTIVE */
         val = cpu->env.v7m.exception;
         /* VECTPENDING */
-        val |= (s->vectpending & 0xff) << 12;
+        val |= (s->vectpending & 0x1ff) << 12;
         /* ISRPENDING - set if any external IRQ is pending */
         if (nvic_isrpending(s)) {
             val |= (1 << 22);
-- 
2.20.1

In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if
the register is accessed NonSecure and the highest priority pending
enabled exception (that would be returned in the VECTPENDING field)
targets Secure, then the VECTPENDING field must read 1 rather than
the exception number of the pending exception. Implement this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-7-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 31 ++++++++++++++++++++++++-------
 1 file changed, 24 insertions(+), 7 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
     nvic_irq_update(s);
 }
 
+static bool vectpending_targets_secure(NVICState *s)
+{
+    /* Return true if s->vectpending targets Secure state */
+    if (s->vectpending_is_s_banked) {
+        return true;
+    }
+    return !exc_is_banked(s->vectpending) &&
+        exc_targets_secure(s, s->vectpending);
+}
+
 void armv7m_nvic_get_pending_irq_info(void *opaque,
                                       int *pirq, bool *ptargets_secure)
 {
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,
 
     assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
 
-    if (s->vectpending_is_s_banked) {
-        targets_secure = true;
-    } else {
-        targets_secure = !exc_is_banked(pending) &&
-            exc_targets_secure(s, pending);
-    }
+    targets_secure = vectpending_targets_secure(s);
 
     trace_nvic_get_pending_irq_info(pending, targets_secure);
 
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
         /* VECTACTIVE */
         val = cpu->env.v7m.exception;
         /* VECTPENDING */
-        val |= (s->vectpending & 0x1ff) << 12;
+        if (s->vectpending) {
+            /*
+             * From v8.1M VECTPENDING must read as 1 if accessed as
+             * NonSecure and the highest priority pending and enabled
+             * exception targets Secure.
+             */
+            int vp = s->vectpending;
+            if (!attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_V8_1M) &&
+                vectpending_targets_secure(s)) {
+                vp = 1;
+            }
+            val |= (vp & 0x1ff) << 12;
+        }
         /* ISRPENDING - set if any external IRQ is pending */
         if (nvic_isrpending(s)) {
             val |= (1 << 22);
-- 
2.20.1

From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>

Missed in commit f3478392 "docs: Move deprecation, build
and license info out of system/"

Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210723065828.1336760-1-maozhongyi@cmss.chinamobile.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 configure         | 2 +-
 target/i386/cpu.c | 2 +-
 MAINTAINERS       | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/configure b/configure
index XXXXXXX..XXXXXXX 100755
--- a/configure
+++ b/configure
@@ -XXX,XX +XXX,XX @@ fi
 
 if test -n "${deprecated_features}"; then
     echo "Warning, deprecated features enabled."
-    echo "Please see docs/system/deprecated.rst"
+    echo "Please see docs/about/deprecated.rst"
     echo "  features: ${deprecated_features}"
 fi
 
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -XXX,XX +XXX,XX @@ static const X86CPUDefinition builtin_x86_defs[] = {
  * none", but this is just for compatibility while libvirt isn't
  * adapted to resolve CPU model versions before creating VMs.
  * See "Runnability guarantee of CPU models" at
- * docs/system/deprecated.rst.
+ * docs/about/deprecated.rst.
  */
 X86CPUVersion default_cpu_version = 1;
 
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: contrib/gitdm/*
 
 Incompatible changes
 R: libvir-list@redhat.com
-F: docs/system/deprecated.rst
+F: docs/about/deprecated.rst
 
 Build System
 ------------
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Currently, our only caller is sve_zcr_len_for_el, which has
already masked the length extracted from ZCR_ELx, so the
masking done here is a nop.  But we will shortly have uses
from other locations, where the length will be unmasked.

Saturate the length to ARM_MAX_VQ instead of truncating to
the low 4 bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210723203344.968563-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
 {
     uint32_t end_len;
 
-    end_len = start_len &= 0xf;
+    start_len = MIN(start_len, ARM_MAX_VQ - 1);
+    end_len = start_len;
+
     if (!test_bit(start_len, cpu->sve_vq_map)) {
         end_len = find_last_bit(cpu->sve_vq_map, start_len);
         assert(end_len < start_len);
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Rename from sve_zcr_get_valid_len and make accessible
from outside of helper.c.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210723203344.968563-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h | 10 ++++++++++
 target/arm/helper.c    |  4 ++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void);
 void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
 #endif /* CONFIG_TCG */
 
+/**
+ * aarch64_sve_zcr_get_valid_len:
+ * @cpu: cpu context
+ * @start_len: maximum len to consider
+ *
+ * Return the maximum supported sve vector length <= @start_len.
+ * Note that both @start_len and the return value are in units
+ * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128.
+ */
+uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len);
 
 enum arm_fprounding {
     FPROUNDING_TIEEVEN,
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
     return 0;
 }
 
-static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
+uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
 {
     uint32_t end_len;
 
@@ -XXX,XX +XXX,XX @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
         zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
     }
 
-    return sve_zcr_get_valid_len(cpu, zcr_len);
+    return aarch64_sve_zcr_get_valid_len(cpu, zcr_len);
 }
 
 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Mirror the behavour of /proc/sys/abi/sve_default_vector_length
under the real linux kernel.  We have no way of passing along
a real default across exec like the kernel can, but this is a
decent way of adjusting the startup vector length of a process.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/482
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210723203344.968563-4-richard.henderson@linaro.org
[PMM: tweaked docs formatting, document -1 special-case,
 added fixup patch from RTH mentioning QEMU's maximum veclen.]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/cpu-features.rst | 15 ++++++++
 target/arm/cpu.h                 |  5 +++
 target/arm/cpu.c                 | 14 ++++++--
 target/arm/cpu64.c               | 60 ++++++++++++++++++++++++++++++++
 4 files changed, 92 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/cpu-features.rst
+++ b/docs/system/arm/cpu-features.rst
@@ -XXX,XX +XXX,XX @@ verbose command lines.  However, the recommended way to select vector
 lengths is to explicitly enable each desired length.  Therefore only
 example's (1), (4), and (6) exhibit recommended uses of the properties.
 
+SVE User-mode Default Vector Length Property
+--------------------------------------------
+
+For qemu-aarch64, the cpu property ``sve-default-vector-length=N`` is
+defined to mirror the Linux kernel parameter file
+``/proc/sys/abi/sve_default_vector_length``.  The default length, ``N``,
+is in units of bytes and must be between 16 and 8192.
+If not specified, the default vector length is 64.
+
+If the default length is larger than the maximum vector length enabled,
+the actual vector length will be reduced.  Note that the maximum vector
+length supported by QEMU is 256.
+
+If this property is set to ``-1`` then the default vector length
+is set to the maximum possible length.
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
     /* Used to set the maximum vector length the cpu will support.  */
     uint32_t sve_max_vq;
 
+#ifdef CONFIG_USER_ONLY
+    /* Used to set the default vector length at process start. */
+    uint32_t sve_default_vq;
+#endif
+
     /*
      * In sve_vq_map each set bit is a supported vector length of
      * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
         /* with reasonable vector length */
         if (cpu_isar_feature(aa64_sve, cpu)) {
-            env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3);
+            env->vfp.zcr_el[1] =
+                aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1);
         }
         /*
          * Enable TBI0 but not TBI1.
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
     QLIST_INIT(&cpu->pre_el_change_hooks);
     QLIST_INIT(&cpu->el_change_hooks);
 
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+# ifdef TARGET_AARCH64
+    /*
+     * The linux kernel defaults to 512-bit vectors, when sve is supported.
+     * See documentation for /proc/sys/abi/sve_default_vector_length, and
+     * our corresponding sve-default-vector-length cpu property.
+     */
+    cpu->sve_default_vq = 4;
+# endif
+#else
     /* Our inbound IRQ and FIQ lines */
     if (kvm_enabled()) {
         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)
     cpu->isar.id_aa64pfr0 = t;
 }
 
+#ifdef CONFIG_USER_ONLY
+/* Mirror linux /proc/sys/abi/sve_default_vector_length. */
+static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v,
+                                            const char *name, void *opaque,
+                                            Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    int32_t default_len, default_vq, remainder;
+
+    if (!visit_type_int32(v, name, &default_len, errp)) {
+        return;
+    }
+
+    /* Undocumented, but the kernel allows -1 to indicate "maximum". */
+    if (default_len == -1) {
+        cpu->sve_default_vq = ARM_MAX_VQ;
+        return;
+    }
+
+    default_vq = default_len / 16;
+    remainder = default_len % 16;
+
+    /*
+     * Note that the 512 max comes from include/uapi/asm/sve_context.h
+     * and is the maximum architectural width of ZCR_ELx.LEN.
+     */
+    if (remainder || default_vq < 1 || default_vq > 512) {
+        error_setg(errp, "cannot set sve-default-vector-length");
+        if (remainder) {
+            error_append_hint(errp, "Vector length not a multiple of 16\n");
+        } else if (default_vq < 1) {
+            error_append_hint(errp, "Vector length smaller than 16\n");
+        } else {
+            error_append_hint(errp, "Vector length larger than %d\n",
+                              512 * 16);
+        }
+        return;
+    }
+
+    cpu->sve_default_vq = default_vq;
+}
+
+static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v,
+                                            const char *name, void *opaque,
+                                            Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    int32_t value = cpu->sve_default_vq * 16;
+
+    visit_type_int32(v, name, &value, errp);
+}
+#endif
+
 void aarch64_add_sve_properties(Object *obj)
 {
     uint32_t vq;
@@ -XXX,XX +XXX,XX @@ void aarch64_add_sve_properties(Object *obj)
         object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
                             cpu_arm_set_sve_vq, NULL, NULL);
     }
+
+#ifdef CONFIG_USER_ONLY
+    /* Mirror linux /proc/sys/abi/sve_default_vector_length. */
+    object_property_add(obj, "sve-default-vector-length", "int32",
+                        cpu_arm_get_sve_default_vec_len,
+                        cpu_arm_set_sve_default_vec_len, NULL, NULL);
+#endif
 }
 
 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
-- 
2.20.1

From: Joel Stanley <joel@jms.id.au>

The macro used to calculate the maximum memory size of the MMIO region
had a mistake, causing all GPIO models to create a mapping of 0x9D8.
The intent was to have it be 0x9D8 - 0x800.

This extra size doesn't matter on ast2400 and ast2500, which have a 4KB
region set aside for the GPIO controller.

On the ast2600 the 3.3V and 1.8V GPIO controllers are 2KB apart, so the
regions would overlap. Worse was the 1.8V controller would map over the
top of the following peripheral, which happens to be the RTC.

The mmio region used by each device is a maximum of 2KB, so avoid the
calculations and hard code this as the maximum.

Fixes: 36d737ee82b2 ("hw/gpio: Add in AST2600 specific implementation")
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20210713065854.134634-2-joel@jms.id.au
[PMM: fix autocorrect error in commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/gpio/aspeed_gpio.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/aspeed_gpio.c
+++ b/hw/gpio/aspeed_gpio.c
@@ -XXX,XX +XXX,XX @@
 #define GPIO_1_8V_MEM_SIZE            0x9D8
 #define GPIO_1_8V_REG_ARRAY_SIZE      ((GPIO_1_8V_MEM_SIZE - \
                                       GPIO_1_8V_REG_OFFSET) >> 2)
-#define GPIO_MAX_MEM_SIZE           MAX(GPIO_3_6V_MEM_SIZE, GPIO_1_8V_MEM_SIZE)
 
 static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio)
 {
@@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_realize(DeviceState *dev, Error **errp)
     }
 
     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s,
-            TYPE_ASPEED_GPIO, GPIO_MAX_MEM_SIZE);
+            TYPE_ASPEED_GPIO, 0x800);
 
     sysbus_init_mmio(sbd, &s->iomem);
 }
-- 
2.20.1

The following changes since commit f003dd8d81f7d88f4b1f8802309eaa76f6eb223a:

Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging (2023-03-06 10:20:04 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230306

for you to fetch changes up to 2ddc45954f97cd1d7ee5cbca0def05e980d1da9f:

hw: arm: allwinner-h3: Fix and complete H3 i2c devices (2023-03-06 15:31:24 +0000)

----------------------------------------------------------------
target-arm queue:
 * allwinner-h3: Fix I2C controller model for Sun6i SoCs
 * allwinner-h3: Add missing i2c controllers
 * Expose M-profile system registers to gdbstub
 * Expose pauth information to gdbstub
 * Support direct boot for Linux/arm64 EFI zboot images
 * Fix incorrect stage 2 MMU setup validation

----------------------------------------------------------------
Ard Biesheuvel (1):
      hw: arm: Support direct boot for Linux/arm64 EFI zboot images

David Reiss (2):
      target/arm: Export arm_v7m_mrs_control
      target/arm: Export arm_v7m_get_sp_ptr

Richard Henderson (16):
      target/arm: Normalize aarch64 gdbstub get/set function names
      target/arm: Unexport arm_gen_dynamic_sysreg_xml
      target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
      target/arm: Split out output_vector_union_type
      target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
      target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
      target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
      target/arm: Add name argument to output_vector_union_type
      target/arm: Simplify iteration over bit widths
      target/arm: Create pauth_ptr_mask
      target/arm: Implement gdbstub pauth extension
      target/arm: Implement gdbstub m-profile systemreg and secext
      target/arm: Handle m-profile in arm_is_secure
      target/arm: Stub arm_hcr_el2_eff for m-profile
      target/arm: Diagnose incorrect usage of arm_is_secure subroutines
      target/arm: Rewrite check_s2_mmu_setup

qianfan Zhao (2):
      hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
      hw: arm: allwinner-h3: Fix and complete H3 i2c devices

From: Richard Henderson <richard.henderson@linaro.org>

Make the form of the function names between fp and sve the same:
  - arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg.
  - aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h | 8 ++++----
 target/arm/gdbstub.c   | 9 +++++----
 target/arm/gdbstub64.c | 8 ++++----
 3 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
 }
 
 #ifdef TARGET_AARCH64
-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);
-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);
-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
+int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
+int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
+int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
+int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
          */
 #ifdef TARGET_AARCH64
         if (isar_feature_aa64_sve(&cpu->isar)) {
-            gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
-                                     arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
+            int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs);
+            gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
+                                     aarch64_gdb_set_sve_reg, nreg,
                                      "sve-registers.xml", 0);
         } else {
-            gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
-                                     aarch64_fpu_gdb_set_reg,
+            gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,
+                                     aarch64_gdb_set_fpu_reg,
                                      34, "aarch64-fpu.xml", 0);
         }
 #endif
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
     return 0;
 }
 
-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
+int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)
 {
     switch (reg) {
     case 0 ... 31:
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
     }
 }
 
-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
+int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)
 {
     switch (reg) {
     case 0 ... 31:
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
     }
 }
 
-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
+int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)
 {
     ARMCPU *cpu = env_archcpu(env);
 
@@ -XXX,XX +XXX,XX @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
     return 0;
 }
 
-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
+int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
 {
     ARMCPU *cpu = env_archcpu(env);
 
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

This function is not used outside gdbstub.c.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     | 1 -
 target/arm/gdbstub.c | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  * Helpers to dynamically generates XML descriptions of the sysregs
  * and SVE registers. Returns the number of registers in each set.
  */
-int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
 
 /* Returns the dynamically generated XML for the gdb stub.
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
     }
 }
 
-int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
+static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     GString *s = g_string_new(NULL);
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

The function is only used for aarch64, so move it to the
file that has the other aarch64 gdbstub stuff.  Move the
declaration to internals.h.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h       |   6 ---
 target/arm/internals.h |   1 +
 target/arm/gdbstub.c   | 120 -----------------------------------------
 target/arm/gdbstub64.c | 118 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 119 insertions(+), 126 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 
-/*
- * Helpers to dynamically generates XML descriptions of the sysregs
- * and SVE registers. Returns the number of registers in each set.
- */
-int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
-
 /* Returns the dynamically generated XML for the gdb stub.
  * Returns a pointer to the XML contents for the specified XML file or NULL
  * if the XML name doesn't match the predefined one.
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
 }
 
 #ifdef TARGET_AARCH64
+int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
 int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
 int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
 int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
     return cpu->dyn_sysreg_xml.num;
 }
 
-struct TypeSize {
-    const char *gdb_type;
-    int  size;
-    const char sz, suffix;
-};
-
-static const struct TypeSize vec_lanes[] = {
-    /* quads */
-    { "uint128", 128, 'q', 'u' },
-    { "int128", 128, 'q', 's' },
-    /* 64 bit */
-    { "ieee_double", 64, 'd', 'f' },
-    { "uint64", 64, 'd', 'u' },
-    { "int64", 64, 'd', 's' },
-    /* 32 bit */
-    { "ieee_single", 32, 's', 'f' },
-    { "uint32", 32, 's', 'u' },
-    { "int32", 32, 's', 's' },
-    /* 16 bit */
-    { "ieee_half", 16, 'h', 'f' },
-    { "uint16", 16, 'h', 'u' },
-    { "int16", 16, 'h', 's' },
-    /* bytes */
-    { "uint8", 8, 'b', 'u' },
-    { "int8", 8, 'b', 's' },
-};
-
-
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
-{
-    ARMCPU *cpu = ARM_CPU(cs);
-    GString *s = g_string_new(NULL);
-    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
-    g_autoptr(GString) ts = g_string_new("");
-    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
-    info->num = 0;
-    g_string_printf(s, "<?xml version=\"1.0\"?>");
-    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
-    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
-
-    /* First define types and totals in a whole VL */
-    for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
-        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
-        g_string_append_printf(s,
-                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
-                               ts->str, vec_lanes[i].gdb_type, count);
-    }
-    /*
-     * Now define a union for each size group containing unsigned and
-     * signed and potentially float versions of each size from 128 to
-     * 8 bits.
-     */
-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
-        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
-        for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
-            if (vec_lanes[j].size == bits) {
-                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
-                                       vec_lanes[j].suffix,
-                                       vec_lanes[j].sz, vec_lanes[j].suffix);
-            }
-        }
-        g_string_append(s, "</union>");
-    }
-    /* And now the final union of unions */
-    g_string_append(s, "<union id=\"svev\">");
-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
-        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
-                               suf[i], suf[i]);
-    }
-    g_string_append(s, "</union>");
-
-    /* Finally the sve prefix type */
-    g_string_append_printf(s,
-                           "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
-                           reg_width / 8);
-
-    /* Then define each register in parts for each vq */
-    for (i = 0; i < 32; i++) {
-        g_string_append_printf(s,
-                               "<reg name=\"z%d\" bitsize=\"%d\""
-                               " regnum=\"%d\" type=\"svev\"/>",
-                               i, reg_width, base_reg++);
-        info->num++;
-    }
-    /* fpscr & status registers */
-    g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
-                           " regnum=\"%d\" group=\"float\""
-                           " type=\"int\"/>", base_reg++);
-    g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
-                           " regnum=\"%d\" group=\"float\""
-                           " type=\"int\"/>", base_reg++);
-    info->num += 2;
-
-    for (i = 0; i < 16; i++) {
-        g_string_append_printf(s,
-                               "<reg name=\"p%d\" bitsize=\"%d\""
-                               " regnum=\"%d\" type=\"svep\"/>",
-                               i, cpu->sve_max_vq * 16, base_reg++);
-        info->num++;
-    }
-    g_string_append_printf(s,
-                           "<reg name=\"ffr\" bitsize=\"%d\""
-                           " regnum=\"%d\" group=\"vector\""
-                           " type=\"svep\"/>",
-                           cpu->sve_max_vq * 16, base_reg++);
-    g_string_append_printf(s,
-                           "<reg name=\"vg\" bitsize=\"64\""
-                           " regnum=\"%d\" type=\"int\"/>",
-                           base_reg++);
-    info->num += 2;
-    g_string_append_printf(s, "</feature>");
-    cpu->dyn_svereg_xml.desc = g_string_free(s, false);
-
-    return cpu->dyn_svereg_xml.num;
-}
-
-
 const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 {
     ARMCPU *cpu = ARM_CPU(cs);
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
 
     return 0;
 }
+
+struct TypeSize {
+    const char *gdb_type;
+    short size;
+    char sz, suffix;
+};
+
+static const struct TypeSize vec_lanes[] = {
+    /* quads */
+    { "uint128", 128, 'q', 'u' },
+    { "int128", 128, 'q', 's' },
+    /* 64 bit */
+    { "ieee_double", 64, 'd', 'f' },
+    { "uint64", 64, 'd', 'u' },
+    { "int64", 64, 'd', 's' },
+    /* 32 bit */
+    { "ieee_single", 32, 's', 'f' },
+    { "uint32", 32, 's', 'u' },
+    { "int32", 32, 's', 's' },
+    /* 16 bit */
+    { "ieee_half", 16, 'h', 'f' },
+    { "uint16", 16, 'h', 'u' },
+    { "int16", 16, 'h', 's' },
+    /* bytes */
+    { "uint8", 8, 'b', 'u' },
+    { "int8", 8, 'b', 's' },
+};
+
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    GString *s = g_string_new(NULL);
+    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
+    g_autoptr(GString) ts = g_string_new("");
+    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
+    info->num = 0;
+    g_string_printf(s, "<?xml version=\"1.0\"?>");
+    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
+
+    /* First define types and totals in a whole VL */
+    for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+        int count = reg_width / vec_lanes[i].size;
+        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
+        g_string_append_printf(s,
+                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
+                               ts->str, vec_lanes[i].gdb_type, count);
+    }
+    /*
+     * Now define a union for each size group containing unsigned and
+     * signed and potentially float versions of each size from 128 to
+     * 8 bits.
+     */
+    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
+        for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
+            if (vec_lanes[j].size == bits) {
+                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
+                                       vec_lanes[j].suffix,
+                                       vec_lanes[j].sz, vec_lanes[j].suffix);
+            }
+        }
+        g_string_append(s, "</union>");
+    }
+    /* And now the final union of unions */
+    g_string_append(s, "<union id=\"svev\">");
+    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
+                               suf[i], suf[i]);
+    }
+    g_string_append(s, "</union>");
+
+    /* Finally the sve prefix type */
+    g_string_append_printf(s,
+                           "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
+                           reg_width / 8);
+
+    /* Then define each register in parts for each vq */
+    for (i = 0; i < 32; i++) {
+        g_string_append_printf(s,
+                               "<reg name=\"z%d\" bitsize=\"%d\""
+                               " regnum=\"%d\" type=\"svev\"/>",
+                               i, reg_width, base_reg++);
+        info->num++;
+    }
+    /* fpscr & status registers */
+    g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
+                           " regnum=\"%d\" group=\"float\""
+                           " type=\"int\"/>", base_reg++);
+    g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
+                           " regnum=\"%d\" group=\"float\""
+                           " type=\"int\"/>", base_reg++);
+    info->num += 2;
+
+    for (i = 0; i < 16; i++) {
+        g_string_append_printf(s,
+                               "<reg name=\"p%d\" bitsize=\"%d\""
+                               " regnum=\"%d\" type=\"svep\"/>",
+                               i, cpu->sve_max_vq * 16, base_reg++);
+        info->num++;
+    }
+    g_string_append_printf(s,
+                           "<reg name=\"ffr\" bitsize=\"%d\""
+                           " regnum=\"%d\" group=\"vector\""
+                           " type=\"svep\"/>",
+                           cpu->sve_max_vq * 16, base_reg++);
+    g_string_append_printf(s,
+                           "<reg name=\"vg\" bitsize=\"64\""
+                           " regnum=\"%d\" type=\"int\"/>",
+                           base_reg++);
+    info->num += 2;
+    g_string_append_printf(s, "</feature>");
+    info->desc = g_string_free(s, false);
+
+    return info->num;
+}
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Create a subroutine for creating the union of unions
of the various type sizes that a vector may contain.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 83 +++++++++++++++++++++++-------------------
 1 file changed, 45 insertions(+), 38 deletions(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
     return 0;
 }
 
-struct TypeSize {
-    const char *gdb_type;
-    short size;
-    char sz, suffix;
-};
-
-static const struct TypeSize vec_lanes[] = {
-    /* quads */
-    { "uint128", 128, 'q', 'u' },
-    { "int128", 128, 'q', 's' },
-    /* 64 bit */
-    { "ieee_double", 64, 'd', 'f' },
-    { "uint64", 64, 'd', 'u' },
-    { "int64", 64, 'd', 's' },
-    /* 32 bit */
-    { "ieee_single", 32, 's', 'f' },
-    { "uint32", 32, 's', 'u' },
-    { "int32", 32, 's', 's' },
-    /* 16 bit */
-    { "ieee_half", 16, 'h', 'f' },
-    { "uint16", 16, 'h', 'u' },
-    { "int16", 16, 'h', 's' },
-    /* bytes */
-    { "uint8", 8, 'b', 'u' },
-    { "int8", 8, 'b', 's' },
-};
-
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+static void output_vector_union_type(GString *s, int reg_width)
 {
-    ARMCPU *cpu = ARM_CPU(cs);
-    GString *s = g_string_new(NULL);
-    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
+    struct TypeSize {
+        const char *gdb_type;
+        short size;
+        char sz, suffix;
+    };
+
+    static const struct TypeSize vec_lanes[] = {
+        /* quads */
+        { "uint128", 128, 'q', 'u' },
+        { "int128", 128, 'q', 's' },
+        /* 64 bit */
+        { "ieee_double", 64, 'd', 'f' },
+        { "uint64", 64, 'd', 'u' },
+        { "int64", 64, 'd', 's' },
+        /* 32 bit */
+        { "ieee_single", 32, 's', 'f' },
+        { "uint32", 32, 's', 'u' },
+        { "int32", 32, 's', 's' },
+        /* 16 bit */
+        { "ieee_half", 16, 'h', 'f' },
+        { "uint16", 16, 'h', 'u' },
+        { "int16", 16, 'h', 's' },
+        /* bytes */
+        { "uint8", 8, 'b', 'u' },
+        { "int8", 8, 'b', 's' },
+    };
+
+    static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
+
     g_autoptr(GString) ts = g_string_new("");
-    int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
-    info->num = 0;
-    g_string_printf(s, "<?xml version=\"1.0\"?>");
-    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
-    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
+    int i, j, bits;
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
      * 8 bits.
      */
     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
         g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
             if (vec_lanes[j].size == bits) {
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
     /* And now the final union of unions */
     g_string_append(s, "<union id=\"svev\">");
     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        const char suf[] = { 'q', 'd', 's', 'h', 'b' };
         g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
                                suf[i], suf[i]);
     }
     g_string_append(s, "</union>");
+}
+
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    GString *s = g_string_new(NULL);
+    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
+    int i, reg_width = (cpu->sve_max_vq * 128);
+    info->num = 0;
+    g_string_printf(s, "<?xml version=\"1.0\"?>");
+    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
+
+    output_vector_union_type(s, reg_width);
 
     /* Finally the sve prefix type */
     g_string_append_printf(s,
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Rather than increment base_reg and num, compute num from the change
to base_reg at the end.  Clean up some nearby comments.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 27 ++++++++++++++++-----------
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
     g_string_append(s, "</union>");
 }
 
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     GString *s = g_string_new(NULL);
     DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
-    int i, reg_width = (cpu->sve_max_vq * 128);
-    info->num = 0;
+    int reg_width = cpu->sve_max_vq * 128;
+    int base_reg = orig_base_reg;
+    int i;
+
     g_string_printf(s, "<?xml version=\"1.0\"?>");
     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
     g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 
+    /* Create the vector union type. */
     output_vector_union_type(s, reg_width);
 
-    /* Finally the sve prefix type */
+    /* Create the predicate vector type. */
     g_string_append_printf(s,
                            "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
                            reg_width / 8);
 
-    /* Then define each register in parts for each vq */
+    /* Define the vector registers. */
     for (i = 0; i < 32; i++) {
         g_string_append_printf(s,
                                "<reg name=\"z%d\" bitsize=\"%d\""
                                " regnum=\"%d\" type=\"svev\"/>",
                                i, reg_width, base_reg++);
-        info->num++;
     }
+
     /* fpscr & status registers */
     g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
                            " regnum=\"%d\" group=\"float\""
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
     g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
                            " regnum=\"%d\" group=\"float\""
                            " type=\"int\"/>", base_reg++);
-    info->num += 2;
 
+    /* Define the predicate registers. */
     for (i = 0; i < 16; i++) {
         g_string_append_printf(s,
                                "<reg name=\"p%d\" bitsize=\"%d\""
                                " regnum=\"%d\" type=\"svep\"/>",
                                i, cpu->sve_max_vq * 16, base_reg++);
-        info->num++;
     }
     g_string_append_printf(s,
                            "<reg name=\"ffr\" bitsize=\"%d\""
                            " regnum=\"%d\" group=\"vector\""
                            " type=\"svep\"/>",
                            cpu->sve_max_vq * 16, base_reg++);
+
+    /* Define the vector length pseudo-register. */
     g_string_append_printf(s,
                            "<reg name=\"vg\" bitsize=\"64\""
                            " regnum=\"%d\" type=\"int\"/>",
                            base_reg++);
-    info->num += 2;
-    g_string_append_printf(s, "</feature>");
-    info->desc = g_string_free(s, false);
 
+    g_string_append_printf(s, "</feature>");
+
+    info->desc = g_string_free(s, false);
+    info->num = base_reg - orig_base_reg;
     return info->num;
 }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
     GString *s = g_string_new(NULL);
     DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
     int reg_width = cpu->sve_max_vq * 128;
+    int pred_width = cpu->sve_max_vq * 16;
     int base_reg = orig_base_reg;
     int i;
 
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
         g_string_append_printf(s,
                                "<reg name=\"p%d\" bitsize=\"%d\""
                                " regnum=\"%d\" type=\"svep\"/>",
-                               i, cpu->sve_max_vq * 16, base_reg++);
+                               i, pred_width, base_reg++);
     }
     g_string_append_printf(s,
                            "<reg name=\"ffr\" bitsize=\"%d\""
                            " regnum=\"%d\" group=\"vector\""
                            " type=\"svep\"/>",
-                           cpu->sve_max_vq * 16, base_reg++);
+                           pred_width, base_reg++);
 
     /* Define the vector length pseudo-register. */
     g_string_append_printf(s,
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Define svep based on the size of the predicates,
not the primary vector registers.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
     /* Create the predicate vector type. */
     g_string_append_printf(s,
                            "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
-                           reg_width / 8);
+                           pred_width / 8);
 
     /* Define the vector registers. */
     for (i = 0; i < 32; i++) {
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

This will make the function usable between SVE and SME.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
     return 0;
 }
 
-static void output_vector_union_type(GString *s, int reg_width)
+static void output_vector_union_type(GString *s, int reg_width,
+                                     const char *name)
 {
     struct TypeSize {
         const char *gdb_type;
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
     };
 
     static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
-
-    g_autoptr(GString) ts = g_string_new("");
     int i, j, bits;
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
-        g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
         g_string_append_printf(s,
-                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
-                               ts->str, vec_lanes[i].gdb_type, count);
+                               "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",
+                               name, vec_lanes[i].sz, vec_lanes[i].suffix,
+                               vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);
     }
+
     /*
      * Now define a union for each size group containing unsigned and
      * signed and potentially float versions of each size from 128 to
      * 8 bits.
      */
     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
+        g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
             if (vec_lanes[j].size == bits) {
-                g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
-                                       vec_lanes[j].suffix,
+                g_string_append_printf(s, "<field name=\"%c\" type=\"%s%c%c\"/>",
+                                       vec_lanes[j].suffix, name,
                                        vec_lanes[j].sz, vec_lanes[j].suffix);
             }
         }
         g_string_append(s, "</union>");
     }
+
     /* And now the final union of unions */
-    g_string_append(s, "<union id=\"svev\">");
+    g_string_append_printf(s, "<union id=\"%s\">", name);
     for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
-        g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
-                               suf[i], suf[i]);
+        g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
+                               suf[i], name, suf[i]);
     }
     g_string_append(s, "</union>");
 }
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
     g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
 
     /* Create the vector union type. */
-    output_vector_union_type(s, reg_width);
+    output_vector_union_type(s, reg_width, "svev");
 
     /* Create the predicate vector type. */
     g_string_append_printf(s,
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Order suf[] by the log8 of the width.
Use ARRAY_SIZE instead of hard-coding 128.

This changes the order of the union definitions,
but retains the order of the union-of-union members.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub64.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
         { "int8", 8, 'b', 's' },
     };
 
-    static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
-    int i, j, bits;
+    static const char suf[] = { 'b', 'h', 's', 'd', 'q' };
+    int i, j;
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
      * signed and potentially float versions of each size from 128 to
      * 8 bits.
      */
-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+    for (i = 0; i < ARRAY_SIZE(suf); i++) {
+        int bits = 8 << i;
+
         g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
         for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
             if (vec_lanes[j].size == bits) {
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
 
     /* And now the final union of unions */
     g_string_append_printf(s, "<union id=\"%s\">", name);
-    for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
+    for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {
         g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
                                suf[i], name, suf[i]);
     }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Keep the logic for pauth within pauth_helper.c, and expose
a helper function for use with the gdbstub pac extension.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h        | 10 ++++++++++
 target/arm/tcg/pauth_helper.c | 26 ++++++++++++++++++++++----
 2 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ int exception_target_el(CPUARMState *env);
 bool arm_singlestep_active(CPUARMState *env);
 bool arm_generate_debug_exceptions(CPUARMState *env);
 
+/**
+ * pauth_ptr_mask:
+ * @env: cpu context
+ * @ptr: selects between TTBR0 and TTBR1
+ * @data: selects between TBI and TBID
+ *
+ * Return a mask of the bits of @ptr that contain the authentication code.
+ */
+uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data);
+
 /* Add the cpreg definitions for debug related system registers */
 void define_debug_regs(ARMCPU *cpu);
 
diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/pauth_helper.c
+++ b/target/arm/tcg/pauth_helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
     return pac | ext | ptr;
 }
 
-static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
+static uint64_t pauth_ptr_mask_internal(ARMVAParameters param)
 {
-    /* Note that bit 55 is used whether or not the regime has 2 ranges. */
-    uint64_t extfield = sextract64(ptr, 55, 1);
     int bot_pac_bit = 64 - param.tsz;
     int top_pac_bit = 64 - 8 * param.tbi;
 
-    return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield);
+    return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);
+}
+
+static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
+{
+    uint64_t mask = pauth_ptr_mask_internal(param);
+
+    /* Note that bit 55 is used whether or not the regime has 2 ranges. */
+    if (extract64(ptr, 55, 1)) {
+        return ptr | mask;
+    } else {
+        return ptr & ~mask;
+    }
+}
+
+uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data)
+{
+    ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
+    ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
+
+    return pauth_ptr_mask_internal(param);
 }
 
 static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK
ptrace register set.

The original gdb feature consists of two masks, data and code, which are
used to mask out the authentication code within a pointer.  Following
discussion with Luis Machado, add two more masks in order to support
pointers within the high half of the address space (i.e. TTBR1 vs TTBR0).

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 configs/targets/aarch64-linux-user.mak    |  2 +-
 configs/targets/aarch64-softmmu.mak       |  2 +-
 configs/targets/aarch64_be-linux-user.mak |  2 +-
 target/arm/internals.h                    |  2 ++
 target/arm/gdbstub.c                      |  5 ++++
 target/arm/gdbstub64.c                    | 34 +++++++++++++++++++++++
 gdb-xml/aarch64-pauth.xml                 | 15 ++++++++++
 7 files changed, 59 insertions(+), 3 deletions(-)
 create mode 100644 gdb-xml/aarch64-pauth.xml

diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak
index XXXXXXX..XXXXXXX 100644
--- a/configs/targets/aarch64-linux-user.mak
+++ b/configs/targets/aarch64-linux-user.mak
@@ -XXX,XX +XXX,XX @@
 TARGET_ARCH=aarch64
 TARGET_BASE_ARCH=arm
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
 TARGET_HAS_BFLT=y
 CONFIG_SEMIHOSTING=y
 CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/configs/targets/aarch64-softmmu.mak
+++ b/configs/targets/aarch64-softmmu.mak
@@ -XXX,XX +XXX,XX @@
 TARGET_ARCH=aarch64
 TARGET_BASE_ARCH=arm
 TARGET_SUPPORTS_MTTCG=y
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml
 TARGET_NEED_FDT=y
diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak
index XXXXXXX..XXXXXXX 100644
--- a/configs/targets/aarch64_be-linux-user.mak
+++ b/configs/targets/aarch64_be-linux-user.mak
@@ -XXX,XX +XXX,XX @@
 TARGET_ARCH=aarch64
 TARGET_BASE_ARCH=arm
 TARGET_BIG_ENDIAN=y
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
 TARGET_HAS_BFLT=y
 CONFIG_SEMIHOSTING=y
 CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
 int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
 int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
 int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);
+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
                                      aarch64_gdb_set_fpu_reg,
                                      34, "aarch64-fpu.xml", 0);
         }
+        if (isar_feature_aa64_pauth(&cpu->isar)) {
+            gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
+                                     aarch64_gdb_set_pauth_reg,
+                                     4, "aarch64-pauth.xml", 0);
+        }
 #endif
     } else {
         if (arm_feature(env, ARM_FEATURE_NEON)) {
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
     return 0;
 }
 
+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
+{
+    switch (reg) {
+    case 0: /* pauth_dmask */
+    case 1: /* pauth_cmask */
+    case 2: /* pauth_dmask_high */
+    case 3: /* pauth_cmask_high */
+        /*
+         * Note that older versions of this feature only contained
+         * pauth_{d,c}mask, for use with Linux user processes, and
+         * thus exclusively in the low half of the address space.
+         *
+         * To support system mode, and to debug kernels, two new regs
+         * were added to cover the high half of the address space.
+         * For the purpose of pauth_ptr_mask, we can use any well-formed
+         * address within the address space half -- here, 0 and -1.
+         */
+        {
+            bool is_data = !(reg & 1);
+            bool is_high = reg & 2;
+            uint64_t mask = pauth_ptr_mask(env, -is_high, is_data);
+            return gdb_get_reg64(buf, mask);
+        }
+    default:
+        return 0;
+    }
+}
+
+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)
+{
+    /* All pseudo registers are read-only. */
+    return 0;
+}
+
 static void output_vector_union_type(GString *s, int reg_width,
                                      const char *name)
 {
diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/gdb-xml/aarch64-pauth.xml
@@ -XXX,XX +XXX,XX @@
+<?xml version="1.0"?>
+
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.aarch64.pauth">
+  <reg name="pauth_dmask" bitsize="64"/>
+  <reg name="pauth_cmask" bitsize="64"/>
+  <reg name="pauth_dmask_high" bitsize="64"/>
+  <reg name="pauth_cmask_high" bitsize="64"/>
+</feature>
+
-- 
2.34.1

From: David Reiss <dreiss@meta.com>

Allow the function to be used outside of m_helper.c.
Rename with an "arm_" prefix.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: David Reiss <dreiss@meta.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-13-richard.henderson@linaro.org
[rth: Split out of a larger patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h    | 3 +++
 target/arm/tcg/m_helper.c | 6 +++---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
 #endif
 
+/* Read the CONTROL register as the MRS instruction would. */
+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
+
 #ifdef CONFIG_USER_ONLY
 static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 #else
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/m_helper.c
+++ b/target/arm/tcg/m_helper.c
@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el)
     return xpsr_read(env) & mask;
 }
 
-static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure)
+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure)
 {
     uint32_t value = env->v7m.control[secure];
 
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
     case 0 ... 7: /* xPSR sub-fields */
         return v7m_mrs_xpsr(env, reg, 0);
     case 20: /* CONTROL */
-        return v7m_mrs_control(env, 0);
+        return arm_v7m_mrs_control(env, 0);
     default:
         /* Unprivileged reads others as zero.  */
         return 0;
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
     case 0 ... 7: /* xPSR sub-fields */
         return v7m_mrs_xpsr(env, reg, el);
     case 20: /* CONTROL */
-        return v7m_mrs_control(env, env->v7m.secure);
+        return arm_v7m_mrs_control(env, env->v7m.secure);
     case 0x94: /* CONTROL_NS */
         /*
          * We have to handle this here because unprivileged Secure code
-- 
2.34.1

From: David Reiss <dreiss@meta.com>

Allow the function to be used outside of m_helper.c.
Move to be outside of ifndef CONFIG_USER_ONLY block.
Rename from get_v7m_sp_ptr.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: David Reiss <dreiss@meta.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-14-richard.henderson@linaro.org
[rth: Split out of a larger patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h    | 10 +++++
 target/arm/tcg/m_helper.c | 84 +++++++++++++++++++--------------------
 2 files changed, 51 insertions(+), 43 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
 /* Read the CONTROL register as the MRS instruction would. */
 uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
 
+/*
+ * Return a pointer to the location where we currently store the
+ * stack pointer for the requested security state and thread mode.
+ * This pointer will become invalid if the CPU state is updated
+ * such that the stack pointers are switched around (eg changing
+ * the SPSEL control bit).
+ */
+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,
+                             bool threadmode, bool spsel);
+
 #ifdef CONFIG_USER_ONLY
 static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 #else
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/m_helper.c
+++ b/target/arm/tcg/m_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
     arm_rebuild_hflags(env);
 }
 
-static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
-                                bool spsel)
-{
-    /*
-     * Return a pointer to the location where we currently store the
-     * stack pointer for the requested security state and thread mode.
-     * This pointer will become invalid if the CPU state is updated
-     * such that the stack pointers are switched around (eg changing
-     * the SPSEL control bit).
-     * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
-     * Unlike that pseudocode, we require the caller to pass us in the
-     * SPSEL control bit value; this is because we also use this
-     * function in handling of pushing of the callee-saves registers
-     * part of the v8M stack frame (pseudocode PushCalleeStack()),
-     * and in the tailchain codepath the SPSEL bit comes from the exception
-     * return magic LR value from the previous exception. The pseudocode
-     * opencodes the stack-selection in PushCalleeStack(), but we prefer
-     * to make this utility function generic enough to do the job.
-     */
-    bool want_psp = threadmode && spsel;
-
-    if (secure == env->v7m.secure) {
-        if (want_psp == v7m_using_psp(env)) {
-            return &env->regs[13];
-        } else {
-            return &env->v7m.other_sp;
-        }
-    } else {
-        if (want_psp) {
-            return &env->v7m.other_ss_psp;
-        } else {
-            return &env->v7m.other_ss_msp;
-        }
-    }
-}
-
 static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
                                 uint32_t *pvec)
 {
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
             !mode;
 
         mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv);
-        frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode,
-                                    lr & R_V7M_EXCRET_SPSEL_MASK);
+        frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode,
+                                        lr & R_V7M_EXCRET_SPSEL_MASK);
         want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK);
         if (want_psp) {
             limit = env->v7m.psplim[M_REG_S];
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
          * use 'frame_sp_p' after we do something that makes it invalid.
          */
         bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK;
-        uint32_t *frame_sp_p = get_v7m_sp_ptr(env,
-                                              return_to_secure,
-                                              !return_to_handler,
-                                              spsel);
+        uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure,
+                                                  !return_to_handler, spsel);
         uint32_t frameptr = *frame_sp_p;
         bool pop_ok = true;
         ARMMMUIdx mmu_idx;
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
         threadmode = !arm_v7m_is_handler_mode(env);
         spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
 
-        frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
+        frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel);
         frameptr = *frame_sp_p;
 
         /*
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
 }
 
 #endif /* !CONFIG_USER_ONLY */
+
+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
+                             bool spsel)
+{
+    /*
+     * Return a pointer to the location where we currently store the
+     * stack pointer for the requested security state and thread mode.
+     * This pointer will become invalid if the CPU state is updated
+     * such that the stack pointers are switched around (eg changing
+     * the SPSEL control bit).
+     * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
+     * Unlike that pseudocode, we require the caller to pass us in the
+     * SPSEL control bit value; this is because we also use this
+     * function in handling of pushing of the callee-saves registers
+     * part of the v8M stack frame (pseudocode PushCalleeStack()),
+     * and in the tailchain codepath the SPSEL bit comes from the exception
+     * return magic LR value from the previous exception. The pseudocode
+     * opencodes the stack-selection in PushCalleeStack(), but we prefer
+     * to make this utility function generic enough to do the job.
+     */
+    bool want_psp = threadmode && spsel;
+
+    if (secure == env->v7m.secure) {
+        if (want_psp == v7m_using_psp(env)) {
+            return &env->regs[13];
+        } else {
+            return &env->v7m.other_sp;
+        }
+    } else {
+        if (want_psp) {
+            return &env->v7m.other_ss_psp;
+        } else {
+            return &env->v7m.other_ss_msp;
+        }
+    }
+}
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but
go ahead and implement the other system registers as well.

Since there is significant overlap between the two, implement
them with common code.  The only exception is the systemreg
view of CONTROL, which merges the banked bits as per MRS.

Signed-off-by: David Reiss <dreiss@meta.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-15-richard.henderson@linaro.org
[rth: Substatial rewrite using enumerator and shared code.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     |   2 +
 target/arm/gdbstub.c | 178 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 180 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
 
     DynamicGDBXMLInfo dyn_sysreg_xml;
     DynamicGDBXMLInfo dyn_svereg_xml;
+    DynamicGDBXMLInfo dyn_m_systemreg_xml;
+    DynamicGDBXMLInfo dyn_m_secextreg_xml;
 
     /* Timers used by the generic (architected) timer */
     QEMUTimer *gt_timer[NUM_GTIMERS];
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
     return cpu->dyn_sysreg_xml.num;
 }
 
+typedef enum {
+    M_SYSREG_MSP,
+    M_SYSREG_PSP,
+    M_SYSREG_PRIMASK,
+    M_SYSREG_CONTROL,
+    M_SYSREG_BASEPRI,
+    M_SYSREG_FAULTMASK,
+    M_SYSREG_MSPLIM,
+    M_SYSREG_PSPLIM,
+} MProfileSysreg;
+
+static const struct {
+    const char *name;
+    int feature;
+} m_sysreg_def[] = {
+    [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M },
+    [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M },
+    [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M },
+    [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M },
+    [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN },
+    [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN },
+    [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 },
+    [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 },
+};
+
+static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec)
+{
+    uint32_t *ptr;
+
+    switch (reg) {
+    case M_SYSREG_MSP:
+        ptr = arm_v7m_get_sp_ptr(env, sec, false, true);
+        break;
+    case M_SYSREG_PSP:
+        ptr = arm_v7m_get_sp_ptr(env, sec, true, true);
+        break;
+    case M_SYSREG_MSPLIM:
+        ptr = &env->v7m.msplim[sec];
+        break;
+    case M_SYSREG_PSPLIM:
+        ptr = &env->v7m.psplim[sec];
+        break;
+    case M_SYSREG_PRIMASK:
+        ptr = &env->v7m.primask[sec];
+        break;
+    case M_SYSREG_BASEPRI:
+        ptr = &env->v7m.basepri[sec];
+        break;
+    case M_SYSREG_FAULTMASK:
+        ptr = &env->v7m.faultmask[sec];
+        break;
+    case M_SYSREG_CONTROL:
+        ptr = &env->v7m.control[sec];
+        break;
+    default:
+        return NULL;
+    }
+    return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL;
+}
+
+static int m_sysreg_get(CPUARMState *env, GByteArray *buf,
+                        MProfileSysreg reg, bool secure)
+{
+    uint32_t *ptr = m_sysreg_ptr(env, reg, secure);
+
+    if (ptr == NULL) {
+        return 0;
+    }
+    return gdb_get_reg32(buf, *ptr);
+}
+
+static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)
+{
+    /*
+     * Here, we emulate MRS instruction, where CONTROL has a mix of
+     * banked and non-banked bits.
+     */
+    if (reg == M_SYSREG_CONTROL) {
+        return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure));
+    }
+    return m_sysreg_get(env, buf, reg, env->v7m.secure);
+}
+
+static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)
+{
+    return 0; /* TODO */
+}
+
+static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+    GString *s = g_string_new(NULL);
+    int base_reg = orig_base_reg;
+    int i;
+
+    g_string_printf(s, "<?xml version=\"1.0\"?>");
+    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.m-system\">\n");
+
+    for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
+        if (arm_feature(env, m_sysreg_def[i].feature)) {
+            g_string_append_printf(s,
+                "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n",
+                m_sysreg_def[i].name, base_reg++);
+        }
+    }
+
+    g_string_append_printf(s, "</feature>");
+    cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false);
+    cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg;
+
+    return cpu->dyn_m_systemreg_xml.num;
+}
+
+#ifndef CONFIG_USER_ONLY
+/*
+ * For user-only, we see the non-secure registers via m_systemreg above.
+ * For secext, encode the non-secure view as even and secure view as odd.
+ */
+static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg)
+{
+    return m_sysreg_get(env, buf, reg >> 1, reg & 1);
+}
+
+static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)
+{
+    return 0; /* TODO */
+}
+
+static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    GString *s = g_string_new(NULL);
+    int base_reg = orig_base_reg;
+    int i;
+
+    g_string_printf(s, "<?xml version=\"1.0\"?>");
+    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+    g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.secext\">\n");
+
+    for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
+        g_string_append_printf(s,
+            "<reg name=\"%s_ns\" bitsize=\"32\" regnum=\"%d\"/>\n",
+            m_sysreg_def[i].name, base_reg++);
+        g_string_append_printf(s,
+            "<reg name=\"%s_s\" bitsize=\"32\" regnum=\"%d\"/>\n",
+            m_sysreg_def[i].name, base_reg++);
+    }
+
+    g_string_append_printf(s, "</feature>");
+    cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false);
+    cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg;
+
+    return cpu->dyn_m_secextreg_xml.num;
+}
+#endif
+
 const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 {
     ARMCPU *cpu = ARM_CPU(cs);
@@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
         return cpu->dyn_sysreg_xml.desc;
     } else if (strcmp(xmlname, "sve-registers.xml") == 0) {
         return cpu->dyn_svereg_xml.desc;
+    } else if (strcmp(xmlname, "arm-m-system.xml") == 0) {
+        return cpu->dyn_m_systemreg_xml.desc;
+#ifndef CONFIG_USER_ONLY
+    } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) {
+        return cpu->dyn_m_secextreg_xml.desc;
+#endif
     }
     return NULL;
 }
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
                              arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
                              "system-registers.xml", 0);
 
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        gdb_register_coprocessor(cs,
+            arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
+            arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
+            "arm-m-system.xml", 0);
+#ifndef CONFIG_USER_ONLY
+        if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
+            gdb_register_coprocessor(cs,
+                arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,
+                arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs),
+                "arm-m-secext.xml", 0);
+        }
+#endif
+    }
 }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

M-profile doesn't have HCR_EL2.  While we could test features
before each call, zero is a generally safe return value to
disable the code in the caller.  This test is required to
avoid an assert in arm_is_secure_below_el3.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227225832.816605-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure)
 
 uint64_t arm_hcr_el2_eff(CPUARMState *env)
 {
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        return 0;
+    }
     return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env));
 }
 
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

In several places we use arm_is_secure_below_el3 and
arm_is_el3_or_mon separately from arm_is_secure.
These functions make no sense for m-profile, and
would indicate prior incorrect feature testing.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227225832.816605-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
 
 #if !defined(CONFIG_USER_ONLY)
-/* Return true if exception levels below EL3 are in secure state,
+/*
+ * Return true if exception levels below EL3 are in secure state,
  * or would be following an exception return to that level.
  * Unlike arm_is_secure() (which is always a question about the
  * _current_ state of the CPU) this doesn't care about the current
@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
  */
 static inline bool arm_is_secure_below_el3(CPUARMState *env)
 {
+    assert(!arm_feature(env, ARM_FEATURE_M));
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         return !(env->cp15.scr_el3 & SCR_NS);
     } else {
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
 static inline bool arm_is_el3_or_mon(CPUARMState *env)
 {
+    assert(!arm_feature(env, ARM_FEATURE_M));
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
             /* CPU currently in AArch64 state and EL3 */
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Integrate neighboring code from get_phys_addr_lpae which computed
starting level, as it is easier to validate when doing both at the
same time.  Mirror the checks at the start of AArch{64,32}.S2Walk,
especially S2InvalidSL and S2InconsistentSL.

This reverts 49ba115bb74, which was incorrect -- there is nothing
in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the
pseudocode is consistent in referencing PAMax.

Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227225832.816605-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 173 ++++++++++++++++++++++++++---------------------
 1 file changed, 97 insertions(+), 76 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
  * check_s2_mmu_setup
  * @cpu:        ARMCPU
  * @is_aa64:    True if the translation regime is in AArch64 state
- * @startlevel: Suggested starting level
- * @inputsize:  Bitsize of IPAs
+ * @tcr:        VTCR_EL2 or VSTCR_EL2
+ * @ds:         Effective value of TCR.DS.
+ * @iasize:     Bitsize of IPAs
  * @stride:     Page-table stride (See the ARM ARM)
  *
- * Returns true if the suggested S2 translation parameters are OK and
- * false otherwise.
+ * Decode the starting level of the S2 lookup, returning INT_MIN if
+ * the configuration is invalid.
  */
-static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
-                               int inputsize, int stride, int outputsize)
+static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr,
+                              bool ds, int iasize, int stride)
 {
-    const int grainsize = stride + 3;
-    int startsizecheck;
-
-    /*
-     * Negative levels are usually not allowed...
-     * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
-     * begins with level -1.  Note that previous feature tests will have
-     * eliminated this combination if it is not enabled.
-     */
-    if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) {
-        return false;
-    }
-
-    startsizecheck = inputsize - ((3 - level) * stride + grainsize);
-    if (startsizecheck < 1 || startsizecheck > stride + 4) {
-        return false;
-    }
+    int sl0, sl2, startlevel, granulebits, levels;
+    int s1_min_iasize, s1_max_iasize;
 
+    sl0 = extract32(tcr, 6, 2);
     if (is_aa64) {
+        /*
+         * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of
+         * get_phys_addr_lpae, that used aa64_va_parameters which apply
+         * to aarch64.  If Stage1 is aarch32, the min_txsz is larger.
+         * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to
+         * inputsize is 64 - 24 = 40.
+         */
+        if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) {
+            goto fail;
+        }
+
+        /*
+         * AArch64.S2InvalidSL: Interpretation of SL depends on the page size,
+         * so interleave AArch64.S2StartLevel.
+         */
         switch (stride) {
-        case 13: /* 64KB Pages.  */
-            if (level == 0 || (level == 1 && outputsize <= 42)) {
-                return false;
+        case 9: /* 4KB */
+            /* SL2 is RES0 unless DS=1 & 4KB granule. */
+            sl2 = extract64(tcr, 33, 1);
+            if (ds && sl2) {
+                if (sl0 != 0) {
+                    goto fail;
+                }
+                startlevel = -1;
+            } else {
+                startlevel = 2 - sl0;
+                switch (sl0) {
+                case 2:
+                    if (arm_pamax(cpu) < 44) {
+                        goto fail;
+                    }
+                    break;
+                case 3:
+                    if (!cpu_isar_feature(aa64_st, cpu)) {
+                        goto fail;
+                    }
+                    startlevel = 3;
+                    break;
+                }
             }
             break;
-        case 11: /* 16KB Pages.  */
-            if (level == 0 || (level == 1 && outputsize <= 40)) {
-                return false;
+        case 11: /* 16KB */
+            switch (sl0) {
+            case 2:
+                if (arm_pamax(cpu) < 42) {
+                    goto fail;
+                }
+                break;
+            case 3:
+                if (!ds) {
+                    goto fail;
+                }
+                break;
             }
+            startlevel = 3 - sl0;
             break;
-        case 9: /* 4KB Pages.  */
-            if (level == 0 && outputsize <= 42) {
-                return false;
+        case 13: /* 64KB */
+            switch (sl0) {
+            case 2:
+                if (arm_pamax(cpu) < 44) {
+                    goto fail;
+                }
+                break;
+            case 3:
+                goto fail;
             }
+            startlevel = 3 - sl0;
             break;
         default:
             g_assert_not_reached();
         }
-
-        /* Inputsize checks.  */
-        if (inputsize > outputsize &&
-            (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) {
-            /* This is CONSTRAINED UNPREDICTABLE and we choose to fault.  */
-            return false;
-        }
     } else {
-        /* AArch32 only supports 4KB pages. Assert on that.  */
+        /*
+         * Things are simpler for AArch32 EL2, with only 4k pages.
+         * There is no separate S2InvalidSL function, but AArch32.S2Walk
+         * begins with walkparms.sl0 in {'1x'}.
+         */
         assert(stride == 9);
-
-        if (level == 0) {
-            return false;
+        if (sl0 >= 2) {
+            goto fail;
         }
+        startlevel = 2 - sl0;
     }
-    return true;
+
+    /* AArch{64,32}.S2InconsistentSL are functionally equivalent.  */
+    levels = 3 - startlevel;
+    granulebits = stride + 3;
+
+    s1_min_iasize = levels * stride + granulebits + 1;
+    s1_max_iasize = s1_min_iasize + (stride - 1) + 4;
+
+    if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) {
+        return startlevel;
+    }
+
+ fail:
+    return INT_MIN;
 }
 
 /**
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
          */
         level = 4 - (inputsize - 4) / stride;
     } else {
-        /*
-         * For stage 2 translations the starting level is specified by the
-         * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
-         */
-        uint32_t sl0 = extract32(tcr, 6, 2);
-        uint32_t sl2 = extract64(tcr, 33, 1);
-        int32_t startlevel;
-        bool ok;
-
-        /* SL2 is RES0 unless DS=1 & 4kb granule. */
-        if (param.ds && stride == 9 && sl2) {
-            if (sl0 != 0) {
-                level = 0;
-                goto do_translation_fault;
-            }
-            startlevel = -1;
-        } else if (!aarch64 || stride == 9) {
-            /* AArch32 or 4KB pages */
-            startlevel = 2 - sl0;
-
-            if (cpu_isar_feature(aa64_st, cpu)) {
-                startlevel &= 3;
-            }
-        } else {
-            /* 16KB or 64KB pages */
-            startlevel = 3 - sl0;
-        }
-
-        /* Check that the starting level is valid. */
-        ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
-                                inputsize, stride, outputsize);
-        if (!ok) {
+        int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds,
+                                            inputsize, stride);
+        if (startlevel == INT_MIN) {
+            level = 0;
             goto do_translation_fault;
         }
         level = startlevel;
-- 
2.34.1

From: Ard Biesheuvel <ardb@kernel.org>

Fedora 39 will ship its arm64 kernels in the new generic EFI zboot
format, using gzip compression for the payload.

For doing EFI boot in QEMU, this is completely transparent, as the
firmware or bootloader will take care of this. However, for direct
kernel boot without firmware, we will lose the ability to boot such
distro kernels unless we deal with the new format directly.

EFI zboot images contain metadata in the header regarding the placement
of the compressed payload inside the image, and the type of compression
used. This means we can wire up the existing gzip support without too
much hassle, by parsing the header and grabbing the payload from inside
the loaded zboot image.

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Message-id: 20230303160109.3626966-1-ardb@kernel.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked comment formatting, fixed checkpatch nits]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/loader.h | 19 ++++++++++
 hw/arm/boot.c       |  6 +++
 hw/core/loader.c    | 91 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 116 insertions(+)

diff --git a/include/hw/loader.h b/include/hw/loader.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
                                   uint8_t **buffer);
 ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz);
 
+/**
+ * unpack_efi_zboot_image:
+ * @buffer: pointer to a variable holding the address of a buffer containing the
+ *          image
+ * @size: pointer to a variable holding the size of the buffer
+ *
+ * Check whether the buffer contains a EFI zboot image, and if it does, extract
+ * the compressed payload and decompress it into a new buffer. If successful,
+ * the old buffer is freed, and the *buffer and size variables pointed to by the
+ * function arguments are updated to refer to the newly populated buffer.
+ *
+ * Returns 0 if the image could not be identified as a EFI zboot image.
+ * Returns -1 if the buffer contents were identified as a EFI zboot image, but
+ * unpacking failed for any reason.
+ * Returns the size of the decompressed payload if decompression was performed
+ * successfully.
+ */
+ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size);
+
 #define ELF_LOAD_FAILED       -1
 #define ELF_LOAD_NOT_ELF      -2
 #define ELF_LOAD_WRONG_ARCH   -3
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
             return -1;
         }
         size = len;
+
+        /* Unpack the image if it is a EFI zboot image */
+        if (unpack_efi_zboot_image(&buffer, &size) < 0) {
+            g_free(buffer);
+            return -1;
+        }
     }
 
     /* check the arm64 magic header value -- very old kernels may not have it */
diff --git a/hw/core/loader.c b/hw/core/loader.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz)
     return bytes;
 }
 
+/* The PE/COFF MS-DOS stub magic number */
+#define EFI_PE_MSDOS_MAGIC        "MZ"
+
+/*
+ * The Linux header magic number for a EFI PE/COFF
+ * image targetting an unspecified architecture.
+ */
+#define EFI_PE_LINUX_MAGIC        "\xcd\x23\x82\x81"
+
+/*
+ * Bootable Linux kernel images may be packaged as EFI zboot images, which are
+ * self-decompressing executables when loaded via EFI. The compressed payload
+ * can also be extracted from the image and decompressed by a non-EFI loader.
+ *
+ * The de facto specification for this format is at the following URL:
+ *
+ * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/efi/libstub/zboot-header.S
+ *
+ * This definition is based on Linux upstream commit 29636a5ce87beba.
+ */
+struct linux_efi_zboot_header {
+    uint8_t     msdos_magic[2];         /* PE/COFF 'MZ' magic number */
+    uint8_t     reserved0[2];
+    uint8_t     zimg[4];                /* "zimg" for Linux EFI zboot images */
+    uint32_t    payload_offset;         /* LE offset to compressed payload */
+    uint32_t    payload_size;           /* LE size of the compressed payload */
+    uint8_t     reserved1[8];
+    char        compression_type[32];   /* Compression type, NUL terminated */
+    uint8_t     linux_magic[4];         /* Linux header magic */
+    uint32_t    pe_header_offset;       /* LE offset to the PE header */
+};
+
+/*
+ * Check whether *buffer points to a Linux EFI zboot image in memory.
+ *
+ * If it does, attempt to decompress it to a new buffer, and free the old one.
+ * If any of this fails, return an error to the caller.
+ *
+ * If the image is not a Linux EFI zboot image, do nothing and return success.
+ */
+ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size)
+{
+    const struct linux_efi_zboot_header *header;
+    uint8_t *data = NULL;
+    int ploff, plsize;
+    ssize_t bytes;
+
+    /* ignore if this is too small to be a EFI zboot image */
+    if (*size < sizeof(*header)) {
+        return 0;
+    }
+
+    header = (struct linux_efi_zboot_header *)*buffer;
+
+    /* ignore if this is not a Linux EFI zboot image */
+    if (memcmp(&header->msdos_magic, EFI_PE_MSDOS_MAGIC, 2) != 0 ||
+        memcmp(&header->zimg, "zimg", 4) != 0 ||
+        memcmp(&header->linux_magic, EFI_PE_LINUX_MAGIC, 4) != 0) {
+        return 0;
+    }
+
+    if (strcmp(header->compression_type, "gzip") != 0) {
+        fprintf(stderr,
+                "unable to handle EFI zboot image with \"%.*s\" compression\n",
+                (int)sizeof(header->compression_type) - 1,
+                header->compression_type);
+        return -1;
+    }
+
+    ploff = ldl_le_p(&header->payload_offset);
+    plsize = ldl_le_p(&header->payload_size);
+
+    if (ploff < 0 || plsize < 0 || ploff + plsize > *size) {
+        fprintf(stderr, "unable to handle corrupt EFI zboot image\n");
+        return -1;
+    }
+
+    data = g_malloc(LOAD_IMAGE_MAX_GUNZIP_BYTES);
+    bytes = gunzip(data, LOAD_IMAGE_MAX_GUNZIP_BYTES, *buffer + ploff, plsize);
+    if (bytes < 0) {
+        fprintf(stderr, "failed to decompress EFI zboot image\n");
+        g_free(data);
+        return -1;
+    }
+
+    g_free(*buffer);
+    *buffer = g_realloc(data, bytes);
+    *size = bytes;
+    return bytes;
+}
+
 /*
  * Functions for reboot-persistent memory regions.
  *  - used for vga bios and option roms.
-- 
2.34.1

From: qianfan Zhao <qianfanguijin@163.com>

TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect)
register on SUN6i based SoCs, we should lower interrupt when the guest
set this bit.

The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no
device connected on the i2c bus, next is the trace log:

allwinner_i2c_write write   CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN
allwinner_i2c_write write   CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
allwinner_i2c_read  read    CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
allwinner_i2c_read  read    STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK
allwinner_i2c_write write   CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
allwinner_i2c_write write   CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    STAT(0x10): 0xf8 STAT_IDLE
allwinner_i2c_write write   CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
allwinner_i2c_write write   CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
allwinner_i2c_read  read    STAT(0x10): 0xf8 STAT_IDLE
...

Fix it.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Tested-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/i2c/allwinner-i2c.h |  6 ++++++
 hw/i2c/allwinner-i2c.c         | 26 ++++++++++++++++++++++++--
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/i2c/allwinner-i2c.h
+++ b/include/hw/i2c/allwinner-i2c.h
@@ -XXX,XX +XXX,XX @@
 #include "qom/object.h"
 
 #define TYPE_AW_I2C "allwinner.i2c"
+
+/** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */
+#define TYPE_AW_I2C_SUN6I    TYPE_AW_I2C "-sun6i"
+
 OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
 
 #define AW_I2C_MEM_SIZE         0x24
@@ -XXX,XX +XXX,XX @@ struct AWI2CState {
     uint8_t srst;
     uint8_t efr;
     uint8_t lcr;
+
+    bool irq_clear_inverted;
 };
 
 #endif /* ALLWINNER_I2C_H */
diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/allwinner-i2c.c
+++ b/hw/i2c/allwinner-i2c.c
@@ -XXX,XX +XXX,XX @@ static void allwinner_i2c_write(void *opaque, hwaddr offset,
                 s->stat = STAT_FROM_STA(STAT_IDLE);
                 s->cntr &= ~TWI_CNTR_M_STP;
             }
-            if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
-                /* Interrupt flag cleared */
+
+            if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) {
+                /* Write 0 to clear this flag */
+                qemu_irq_lower(s->irq);
+            } else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) {
+                /* Write 1 to clear this flag */
+                s->cntr &= ~TWI_CNTR_INT_FLAG;
                 qemu_irq_lower(s->irq);
             }
+
             if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
                 if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
                     s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo allwinner_i2c_type_info = {
     .class_init = allwinner_i2c_class_init,
 };
 
+static void allwinner_i2c_sun6i_init(Object *obj)
+{
+    AWI2CState *s = AW_I2C(obj);
+
+    s->irq_clear_inverted = true;
+}
+
+static const TypeInfo allwinner_i2c_sun6i_type_info = {
+    .name = TYPE_AW_I2C_SUN6I,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(AWI2CState),
+    .instance_init = allwinner_i2c_sun6i_init,
+    .class_init = allwinner_i2c_class_init,
+};
+
 static void allwinner_i2c_register_types(void)
 {
     type_register_static(&allwinner_i2c_type_info);
+    type_register_static(&allwinner_i2c_sun6i_type_info);
 }
 
 type_init(allwinner_i2c_register_types)
-- 
2.34.1

From: qianfan Zhao <qianfanguijin@163.com>

Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi.
The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear
control register's INT_FLAG bit.

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/allwinner-h3.h |  6 ++++++
 hw/arm/allwinner-h3.c         | 29 +++++++++++++++++++++++++----
 2 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -XXX,XX +XXX,XX @@ enum {
     AW_H3_DEV_UART3,
     AW_H3_DEV_EMAC,
     AW_H3_DEV_TWI0,
+    AW_H3_DEV_TWI1,
+    AW_H3_DEV_TWI2,
     AW_H3_DEV_DRAMCOM,
     AW_H3_DEV_DRAMCTL,
     AW_H3_DEV_DRAMPHY,
@@ -XXX,XX +XXX,XX @@ enum {
     AW_H3_DEV_GIC_VCPU,
     AW_H3_DEV_RTC,
     AW_H3_DEV_CPUCFG,
+    AW_H3_DEV_R_TWI,
     AW_H3_DEV_SDRAM
 };
 
@@ -XXX,XX +XXX,XX @@ struct AwH3State {
     AwSidState sid;
     AwSdHostState mmc0;
     AWI2CState i2c0;
+    AWI2CState i2c1;
+    AWI2CState i2c2;
+    AWI2CState r_twi;
     AwSun8iEmacState emac;
     AwRtcState rtc;
     GICState gic;
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
     [AW_H3_DEV_UART2]      = 0x01c28800,
     [AW_H3_DEV_UART3]      = 0x01c28c00,
     [AW_H3_DEV_TWI0]       = 0x01c2ac00,
+    [AW_H3_DEV_TWI1]       = 0x01c2b000,
+    [AW_H3_DEV_TWI2]       = 0x01c2b400,
     [AW_H3_DEV_EMAC]       = 0x01c30000,
     [AW_H3_DEV_DRAMCOM]    = 0x01c62000,
     [AW_H3_DEV_DRAMCTL]    = 0x01c63000,
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
     [AW_H3_DEV_GIC_VCPU]   = 0x01c86000,
     [AW_H3_DEV_RTC]        = 0x01f00000,
     [AW_H3_DEV_CPUCFG]     = 0x01f01c00,
+    [AW_H3_DEV_R_TWI]      = 0x01f02400,
     [AW_H3_DEV_SDRAM]      = 0x40000000
 };
 
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
     { "uart1",     0x01c28400, 1 * KiB },
     { "uart2",     0x01c28800, 1 * KiB },
     { "uart3",     0x01c28c00, 1 * KiB },
-    { "twi1",      0x01c2b000, 1 * KiB },
-    { "twi2",      0x01c2b400, 1 * KiB },
     { "scr",       0x01c2c400, 1 * KiB },
     { "gpu",       0x01c40000, 64 * KiB },
     { "hstmr",     0x01c60000, 4 * KiB },
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
     { "r_prcm",    0x01f01400, 1 * KiB },
     { "r_twd",     0x01f01800, 1 * KiB },
     { "r_cir-rx",  0x01f02000, 1 * KiB },
-    { "r_twi",     0x01f02400, 1 * KiB },
     { "r_uart",    0x01f02800, 1 * KiB },
     { "r_pio",     0x01f02c00, 1 * KiB },
     { "r_pwm",     0x01f03800, 1 * KiB },
@@ -XXX,XX +XXX,XX @@ enum {
     AW_H3_GIC_SPI_UART2     =  2,
     AW_H3_GIC_SPI_UART3     =  3,
     AW_H3_GIC_SPI_TWI0      =  6,
+    AW_H3_GIC_SPI_TWI1      =  7,
+    AW_H3_GIC_SPI_TWI2      =  8,
     AW_H3_GIC_SPI_TIMER0    = 18,
     AW_H3_GIC_SPI_TIMER1    = 19,
+    AW_H3_GIC_SPI_R_TWI     = 44,
     AW_H3_GIC_SPI_MMC0      = 60,
     AW_H3_GIC_SPI_EHCI0     = 72,
     AW_H3_GIC_SPI_OHCI0     = 73,
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
 
     object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
 
-    object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
+    object_initialize_child(obj, "twi0",  &s->i2c0,  TYPE_AW_I2C_SUN6I);
+    object_initialize_child(obj, "twi1",  &s->i2c1,  TYPE_AW_I2C_SUN6I);
+    object_initialize_child(obj, "twi2",  &s->i2c2,  TYPE_AW_I2C_SUN6I);
+    object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I);
 }
 
 static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
                        qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
 
+    sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0,
+                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1));
+
+    sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0,
+                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2));
+
+    sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0,
+                       qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI));
+
     /* Unimplemented devices */
     for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
         create_unimplemented_device(unimplemented[i].device_name,
-- 
2.34.1