[PULL 00/14] target-arm queue
[PULL 00/22] target-arm queue
1
arm pullreq for rc1. All minor bugfixes, except for the sve-default-vector-length
1
Nothing too exciting in this lot :-)
2
patches, which are somewhere between a bugfix and a new feature.
3
2
4
thanks
3
The following changes since commit ba0fa56bc06e563de68d2a2bf3ddb0cfea1be4f9:
5
-- PMM
6
4
7
The following changes since commit c08ccd1b53f488ac86c1f65cf7623dc91acc249a:
5
Merge remote-tracking branch 'remotes/vivier/tags/q800-for-6.2-pull-request' into staging (2021-09-29 21:20:49 +0100)
8
9
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210726' into staging (2021-07-27 08:35:01 +0100)
10
6
11
are available in the Git repository at:
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are available in the Git repository at:
12
8
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210727
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210930
14
10
15
for you to fetch changes up to e229a179a503f2aee43a76888cf12fbdfe8a3749:
11
for you to fetch changes up to 1f4b2ec701b9d73d3fa7bb90c8b4376bc7d3c42b:
16
12
17
hw: aspeed_gpio: Fix memory size (2021-07-27 11:00:00 +0100)
13
hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19 (2021-09-30 13:44:13 +0100)
18
14
19
----------------------------------------------------------------
15
----------------------------------------------------------------
20
target-arm queue:
16
target-arm queue:
21
* hw/arm/smmuv3: Check 31st bit to see if CD is valid
17
* allwinner-h3: Switch to SMC as PSCI conduit
22
* qemu-options.hx: Fix formatting of -machine memory-backend option
18
* arm: tcg: Adhere to SMCCC 1.3 section 5.2
23
* hw: aspeed_gpio: Fix memory size
19
* xlnx-zcu102, xlnx-versal-virt: Support BBRAM and eFUSE devices
24
* hw/arm/nseries: Display hexadecimal value with '0x' prefix
20
* gdbstub related code cleanups
25
* Add sve-default-vector-length cpu property
21
* Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML
26
* docs: Update path that mentions deprecated.rst
22
* Use _init vs _new convention in bus creation function names
27
* hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
23
* sabrelite: Connect SPI flash CS line to GPIO3_19
28
* hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
29
* hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
30
* target/arm: Report M-profile alignment faults correctly to the guest
31
* target/arm: Add missing 'return's after calling v7m_exception_taken()
32
* target/arm: Enforce that M-profile SP low 2 bits are always zero
33
24
34
----------------------------------------------------------------
25
----------------------------------------------------------------
35
Joe Komlodi (1):
26
Alexander Graf (2):
36
hw/arm/smmuv3: Check 31st bit to see if CD is valid
27
allwinner-h3: Switch to SMC as PSCI conduit
28
arm: tcg: Adhere to SMCCC 1.3 section 5.2
37
29
38
Joel Stanley (1):
30
Peter Maydell (10):
39
hw: aspeed_gpio: Fix memory size
31
configs: Don't include 32-bit-only GDB XML in aarch64 linux configs
32
target/arm: Fix coding style issues in gdbstub code in helper.c
33
target/arm: Move gdbstub related code out of helper.c
34
target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML
35
scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named()
36
ipack: Rename ipack_bus_new_inplace() to ipack_bus_init()
37
pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init()
38
qbus: Rename qbus_create_inplace() to qbus_init()
39
qbus: Rename qbus_create() to qbus_new()
40
ide: Rename ide_bus_new() to ide_bus_init()
40
41
41
Mao Zhongyi (1):
42
Tong Ho (9):
42
docs: Update path that mentions deprecated.rst
43
hw/nvram: Introduce Xilinx eFuse QOM
44
hw/nvram: Introduce Xilinx Versal eFuse device
45
hw/nvram: Introduce Xilinx ZynqMP eFuse device
46
hw/nvram: Introduce Xilinx battery-backed ram
47
hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device
48
hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device
49
hw/arm: xlnx-zcu102: Add Xilinx BBRAM device
50
hw/arm: xlnx-zcu102: Add Xilinx eFUSE device
51
docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage
43
52
44
Peter Maydell (7):
53
Xuzhou Cheng (1):
45
qemu-options.hx: Fix formatting of -machine memory-backend option
54
hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19
46
target/arm: Enforce that M-profile SP low 2 bits are always zero
47
target/arm: Add missing 'return's after calling v7m_exception_taken()
48
target/arm: Report M-profile alignment faults correctly to the guest
49
hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
50
hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
51
hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
52
55
53
Philippe Mathieu-Daudé (1):
56
docs/system/arm/xlnx-versal-virt.rst | 49 ++
54
hw/arm/nseries: Display hexadecimal value with '0x' prefix
57
configs/targets/aarch64-linux-user.mak | 2 +-
58
configs/targets/aarch64-softmmu.mak | 2 +-
59
configs/targets/aarch64_be-linux-user.mak | 2 +-
60
configs/targets/arm-linux-user.mak | 2 +-
61
configs/targets/arm-softmmu.mak | 2 +-
62
configs/targets/armeb-linux-user.mak | 2 +-
63
include/hw/arm/xlnx-versal.h | 15 +
64
include/hw/arm/xlnx-zynqmp.h | 5 +
65
include/hw/ide/internal.h | 4 +-
66
include/hw/ipack/ipack.h | 8 +-
67
include/hw/nvram/xlnx-bbram.h | 54 ++
68
include/hw/nvram/xlnx-efuse.h | 132 +++++
69
include/hw/nvram/xlnx-versal-efuse.h | 68 +++
70
include/hw/nvram/xlnx-zynqmp-efuse.h | 44 ++
71
include/hw/pci/pci.h | 10 +-
72
include/hw/qdev-core.h | 6 +-
73
include/hw/scsi/scsi.h | 30 +-
74
target/arm/internals.h | 7 +
75
hw/arm/allwinner-h3.c | 2 +-
76
hw/arm/sabrelite.c | 2 +-
77
hw/arm/xlnx-versal-virt.c | 88 +++
78
hw/arm/xlnx-versal.c | 57 ++
79
hw/arm/xlnx-zcu102.c | 30 ++
80
hw/arm/xlnx-zynqmp.c | 49 ++
81
hw/audio/intel-hda.c | 2 +-
82
hw/block/fdc.c | 2 +-
83
hw/block/swim.c | 3 +-
84
hw/char/virtio-serial-bus.c | 4 +-
85
hw/core/bus.c | 13 +-
86
hw/core/sysbus.c | 10 +-
87
hw/gpio/bcm2835_gpio.c | 3 +-
88
hw/hyperv/vmbus.c | 2 +-
89
hw/i2c/core.c | 2 +-
90
hw/ide/ahci.c | 2 +-
91
hw/ide/cmd646.c | 2 +-
92
hw/ide/isa.c | 2 +-
93
hw/ide/macio.c | 2 +-
94
hw/ide/microdrive.c | 2 +-
95
hw/ide/mmio.c | 2 +-
96
hw/ide/piix.c | 2 +-
97
hw/ide/qdev.c | 4 +-
98
hw/ide/sii3112.c | 2 +-
99
hw/ide/via.c | 2 +-
100
hw/ipack/ipack.c | 10 +-
101
hw/ipack/tpci200.c | 4 +-
102
hw/isa/isa-bus.c | 2 +-
103
hw/misc/auxbus.c | 2 +-
104
hw/misc/mac_via.c | 4 +-
105
hw/misc/macio/cuda.c | 4 +-
106
hw/misc/macio/macio.c | 4 +-
107
hw/misc/macio/pmu.c | 4 +-
108
hw/nubus/nubus-bridge.c | 2 +-
109
hw/nvme/ctrl.c | 4 +-
110
hw/nvme/subsys.c | 3 +-
111
hw/nvram/xlnx-bbram.c | 545 +++++++++++++++++++
112
hw/nvram/xlnx-efuse-crc.c | 119 +++++
113
hw/nvram/xlnx-efuse.c | 280 ++++++++++
114
hw/nvram/xlnx-versal-efuse-cache.c | 114 ++++
115
hw/nvram/xlnx-versal-efuse-ctrl.c | 783 +++++++++++++++++++++++++++
116
hw/nvram/xlnx-zynqmp-efuse.c | 855 ++++++++++++++++++++++++++++++
117
hw/pci-host/raven.c | 4 +-
118
hw/pci-host/versatile.c | 6 +-
119
hw/pci/pci.c | 30 +-
120
hw/pci/pci_bridge.c | 4 +-
121
hw/ppc/spapr_vio.c | 2 +-
122
hw/s390x/ap-bridge.c | 2 +-
123
hw/s390x/css-bridge.c | 2 +-
124
hw/s390x/event-facility.c | 4 +-
125
hw/s390x/s390-pci-bus.c | 2 +-
126
hw/s390x/virtio-ccw.c | 3 +-
127
hw/scsi/esp-pci.c | 2 +-
128
hw/scsi/esp.c | 2 +-
129
hw/scsi/lsi53c895a.c | 2 +-
130
hw/scsi/megasas.c | 3 +-
131
hw/scsi/mptsas.c | 2 +-
132
hw/scsi/scsi-bus.c | 6 +-
133
hw/scsi/spapr_vscsi.c | 3 +-
134
hw/scsi/virtio-scsi.c | 4 +-
135
hw/scsi/vmw_pvscsi.c | 3 +-
136
hw/sd/allwinner-sdhost.c | 4 +-
137
hw/sd/bcm2835_sdhost.c | 4 +-
138
hw/sd/pl181.c | 3 +-
139
hw/sd/pxa2xx_mmci.c | 4 +-
140
hw/sd/sdhci.c | 3 +-
141
hw/sd/ssi-sd.c | 3 +-
142
hw/ssi/ssi.c | 2 +-
143
hw/usb/bus.c | 2 +-
144
hw/usb/dev-smartcard-reader.c | 3 +-
145
hw/usb/dev-storage-bot.c | 3 +-
146
hw/usb/dev-storage-classic.c | 4 +-
147
hw/usb/dev-uas.c | 3 +-
148
hw/virtio/virtio-mmio.c | 3 +-
149
hw/virtio/virtio-pci.c | 3 +-
150
hw/xen/xen-bus.c | 2 +-
151
hw/xen/xen-legacy-backend.c | 2 +-
152
target/arm/gdbstub.c | 154 ++++++
153
target/arm/gdbstub64.c | 140 +++++
154
target/arm/helper.c | 262 ---------
155
target/arm/psci.c | 35 +-
156
gdb-xml/arm-neon.xml | 2 -
157
gdb-xml/arm-vfp-sysregs.xml | 17 +
158
gdb-xml/arm-vfp.xml | 2 -
159
gdb-xml/arm-vfp3.xml | 2 -
160
hw/Kconfig | 2 +
161
hw/arm/Kconfig | 2 +
162
hw/nvram/Kconfig | 19 +
163
hw/nvram/meson.build | 8 +
164
108 files changed, 3806 insertions(+), 447 deletions(-)
165
create mode 100644 include/hw/nvram/xlnx-bbram.h
166
create mode 100644 include/hw/nvram/xlnx-efuse.h
167
create mode 100644 include/hw/nvram/xlnx-versal-efuse.h
168
create mode 100644 include/hw/nvram/xlnx-zynqmp-efuse.h
169
create mode 100644 hw/nvram/xlnx-bbram.c
170
create mode 100644 hw/nvram/xlnx-efuse-crc.c
171
create mode 100644 hw/nvram/xlnx-efuse.c
172
create mode 100644 hw/nvram/xlnx-versal-efuse-cache.c
173
create mode 100644 hw/nvram/xlnx-versal-efuse-ctrl.c
174
create mode 100644 hw/nvram/xlnx-zynqmp-efuse.c
175
create mode 100644 gdb-xml/arm-vfp-sysregs.xml
55
176
56
Richard Henderson (3):
57
target/arm: Correctly bound length in sve_zcr_get_valid_len
58
target/arm: Export aarch64_sve_zcr_get_valid_len
59
target/arm: Add sve-default-vector-length cpu property
60
61
docs/system/arm/cpu-features.rst | 15 ++++++++++
62
configure | 2 +-
63
hw/arm/smmuv3-internal.h | 2 +-
64
target/arm/cpu.h | 5 ++++
65
target/arm/internals.h | 10 +++++++
66
hw/arm/nseries.c | 2 +-
67
hw/gpio/aspeed_gpio.c | 3 +-
68
hw/intc/armv7m_nvic.c | 40 +++++++++++++++++++--------
69
target/arm/cpu.c | 14 ++++++++--
70
target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++++++++++
71
target/arm/gdbstub.c | 4 +++
72
target/arm/helper.c | 8 ++++--
73
target/arm/m_helper.c | 24 ++++++++++++----
74
target/arm/translate.c | 3 ++
75
target/i386/cpu.c | 2 +-
76
MAINTAINERS | 2 +-
77
qemu-options.hx | 30 +++++++++++---------
78
17 files changed, 183 insertions(+), 43 deletions(-)
79
diff view generated by jsdifflib
New patch
[PULL 01/22] allwinner-h3: Switch to SMC as PSCI conduit
1
From: Alexander Graf <agraf@csgraf.de>
1
2
3
The Allwinner H3 SoC uses Cortex-A7 cores which support virtualization.
4
However, today we are configuring QEMU to use HVC as PSCI conduit.
5
6
That means HVC calls get trapped into QEMU instead of the guest's own
7
emulated CPU and thus break the guest's ability to execute virtualization.
8
9
Fix this by moving to SMC as conduit, freeing up HYP completely to the VM.
10
11
Signed-off-by: Alexander Graf <agraf@csgraf.de>
12
Message-id: 20210920203931.66527-1-agraf@csgraf.de
13
Fixes: 740dafc0ba0 ("hw/arm: add Allwinner H3 System-on-Chip")
14
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
15
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
hw/arm/allwinner-h3.c | 2 +-
21
1 file changed, 1 insertion(+), 1 deletion(-)
22
23
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/allwinner-h3.c
26
+++ b/hw/arm/allwinner-h3.c
27
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
28
29
/* Provide Power State Coordination Interface */
30
qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
31
- QEMU_PSCI_CONDUIT_HVC);
32
+ QEMU_PSCI_CONDUIT_SMC);
33
34
/* Disable secondary CPUs */
35
qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
[PULL 14/14] hw: aspeed_gpio: Fix memory size
[PULL 02/22] arm: tcg: Adhere to SMCCC 1.3 section 5.2
1
From: Joel Stanley <joel@jms.id.au>
1
From: Alexander Graf <agraf@csgraf.de>
2
2
3
The macro used to calculate the maximum memory size of the MMIO region
3
The SMCCC 1.3 spec section 5.2 says
4
had a mistake, causing all GPIO models to create a mapping of 0x9D8.
5
The intent was to have it be 0x9D8 - 0x800.
6
4
7
This extra size doesn't matter on ast2400 and ast2500, which have a 4KB
5
The Unknown SMC Function Identifier is a sign-extended value of (-1)
8
region set aside for the GPIO controller.
6
that is returned in the R0, W0 or X0 registers. An implementation must
7
return this error code when it receives:
9
8
10
On the ast2600 the 3.3V and 1.8V GPIO controllers are 2KB apart, so the
9
* An SMC or HVC call with an unknown Function Identifier
11
regions would overlap. Worse was the 1.8V controller would map over the
10
* An SMC or HVC call for a removed Function Identifier
12
top of the following peripheral, which happens to be the RTC.
11
* An SMC64/HVC64 call from AArch32 state
13
12
14
The mmio region used by each device is a maximum of 2KB, so avoid the
13
To comply with these statements, let's always return -1 when we encounter
15
calculations and hard code this as the maximum.
14
an unknown HVC or SMC call.
16
15
17
Fixes: 36d737ee82b2 ("hw/gpio: Add in AST2600 specific implementation")
16
Signed-off-by: Alexander Graf <agraf@csgraf.de>
18
Signed-off-by: Joel Stanley <joel@jms.id.au>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
20
Reviewed-by: Cédric Le Goater <clg@kaod.org>
21
Message-id: 20210713065854.134634-2-joel@jms.id.au
22
[PMM: fix autocorrect error in commit message]
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
19
---
25
hw/gpio/aspeed_gpio.c | 3 +--
20
target/arm/psci.c | 35 ++++++-----------------------------
26
1 file changed, 1 insertion(+), 2 deletions(-)
21
1 file changed, 6 insertions(+), 29 deletions(-)
27
22
28
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
23
diff --git a/target/arm/psci.c b/target/arm/psci.c
29
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/gpio/aspeed_gpio.c
25
--- a/target/arm/psci.c
31
+++ b/hw/gpio/aspeed_gpio.c
26
+++ b/target/arm/psci.c
32
@@ -XXX,XX +XXX,XX @@
27
@@ -XXX,XX +XXX,XX @@
33
#define GPIO_1_8V_MEM_SIZE 0x9D8
28
34
#define GPIO_1_8V_REG_ARRAY_SIZE ((GPIO_1_8V_MEM_SIZE - \
29
bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
35
GPIO_1_8V_REG_OFFSET) >> 2)
36
-#define GPIO_MAX_MEM_SIZE MAX(GPIO_3_6V_MEM_SIZE, GPIO_1_8V_MEM_SIZE)
37
38
static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio)
39
{
30
{
40
@@ -XXX,XX +XXX,XX @@ static void aspeed_gpio_realize(DeviceState *dev, Error **errp)
31
- /* Return true if the r0/x0 value indicates a PSCI call and
32
- * the exception type matches the configured PSCI conduit. This is
33
- * called before the SMC/HVC instruction is executed, to decide whether
34
- * we should treat it as a PSCI call or with the architecturally
35
+ /*
36
+ * Return true if the exception type matches the configured PSCI conduit.
37
+ * This is called before the SMC/HVC instruction is executed, to decide
38
+ * whether we should treat it as a PSCI call or with the architecturally
39
* defined behaviour for an SMC or HVC (which might be UNDEF or trap
40
* to EL2 or to EL3).
41
*/
42
- CPUARMState *env = &cpu->env;
43
- uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0];
44
45
switch (excp_type) {
46
case EXCP_HVC:
47
@@ -XXX,XX +XXX,XX @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
48
return false;
41
}
49
}
42
50
43
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s,
51
- switch (param) {
44
- TYPE_ASPEED_GPIO, GPIO_MAX_MEM_SIZE);
52
- case QEMU_PSCI_0_2_FN_PSCI_VERSION:
45
+ TYPE_ASPEED_GPIO, 0x800);
53
- case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
46
54
- case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
47
sysbus_init_mmio(sbd, &s->iomem);
55
- case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
56
- case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
57
- case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
58
- case QEMU_PSCI_0_1_FN_CPU_ON:
59
- case QEMU_PSCI_0_2_FN_CPU_ON:
60
- case QEMU_PSCI_0_2_FN64_CPU_ON:
61
- case QEMU_PSCI_0_1_FN_CPU_OFF:
62
- case QEMU_PSCI_0_2_FN_CPU_OFF:
63
- case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
64
- case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
65
- case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
66
- case QEMU_PSCI_0_1_FN_MIGRATE:
67
- case QEMU_PSCI_0_2_FN_MIGRATE:
68
- return true;
69
- default:
70
- return false;
71
- }
72
+ return true;
48
}
73
}
74
75
void arm_handle_psci_call(ARMCPU *cpu)
76
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
77
break;
78
case QEMU_PSCI_0_1_FN_MIGRATE:
79
case QEMU_PSCI_0_2_FN_MIGRATE:
80
+ default:
81
ret = QEMU_PSCI_RET_NOT_SUPPORTED;
82
break;
83
- default:
84
- g_assert_not_reached();
85
}
86
87
err:
49
--
88
--
50
2.20.1
89
2.20.1
51
90
52
91
diff view generated by jsdifflib
New patch
[PULL 03/22] hw/nvram: Introduce Xilinx eFuse QOM
1
From: Tong Ho <tong.ho@xilinx.com>
1
2
3
This introduces the QOM for Xilinx eFuse, an one-time
4
field-programmable storage bit array.
5
6
The actual mmio interface to the array varies by device
7
families and will be provided in different change-sets.
8
9
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
11
12
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
13
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
14
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
15
Message-id: 20210917052400.1249094-2-tong.ho@xilinx.com
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
include/hw/nvram/xlnx-efuse.h | 132 ++++++++++++++++
20
hw/nvram/xlnx-efuse-crc.c | 119 +++++++++++++++
21
hw/nvram/xlnx-efuse.c | 280 ++++++++++++++++++++++++++++++++++
22
hw/nvram/Kconfig | 7 +
23
hw/nvram/meson.build | 2 +
24
5 files changed, 540 insertions(+)
25
create mode 100644 include/hw/nvram/xlnx-efuse.h
26
create mode 100644 hw/nvram/xlnx-efuse-crc.c
27
create mode 100644 hw/nvram/xlnx-efuse.c
28
29
diff --git a/include/hw/nvram/xlnx-efuse.h b/include/hw/nvram/xlnx-efuse.h
30
new file mode 100644
31
index XXXXXXX..XXXXXXX
32
--- /dev/null
33
+++ b/include/hw/nvram/xlnx-efuse.h
34
@@ -XXX,XX +XXX,XX @@
35
+/*
36
+ * QEMU model of the Xilinx eFuse core
37
+ *
38
+ * Copyright (c) 2015 Xilinx Inc.
39
+ *
40
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
41
+ *
42
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
43
+ * of this software and associated documentation files (the "Software"), to deal
44
+ * in the Software without restriction, including without limitation the rights
45
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
46
+ * copies of the Software, and to permit persons to whom the Software is
47
+ * furnished to do so, subject to the following conditions:
48
+ *
49
+ * The above copyright notice and this permission notice shall be included in
50
+ * all copies or substantial portions of the Software.
51
+ *
52
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
53
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
54
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
55
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
56
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
57
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
58
+ * THE SOFTWARE.
59
+ */
60
+
61
+#ifndef XLNX_EFUSE_H
62
+#define XLNX_EFUSE_H
63
+
64
+#include "sysemu/block-backend.h"
65
+#include "hw/qdev-core.h"
66
+
67
+#define TYPE_XLNX_EFUSE "xlnx,efuse"
68
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxEFuse, XLNX_EFUSE);
69
+
70
+struct XlnxEFuse {
71
+ DeviceState parent_obj;
72
+ BlockBackend *blk;
73
+ bool blk_ro;
74
+ uint32_t *fuse32;
75
+
76
+ DeviceState *dev;
77
+
78
+ bool init_tbits;
79
+
80
+ uint8_t efuse_nr;
81
+ uint32_t efuse_size;
82
+
83
+ uint32_t *ro_bits;
84
+ uint32_t ro_bits_cnt;
85
+};
86
+
87
+/**
88
+ * xlnx_efuse_calc_crc:
89
+ * @data: an array of 32-bit words for which the CRC should be computed
90
+ * @u32_cnt: the array size in number of 32-bit words
91
+ * @zpads: the number of 32-bit zeros prepended to @data before computation
92
+ *
93
+ * This function is used to compute the CRC for an array of 32-bit words,
94
+ * using a Xilinx-specific data padding.
95
+ *
96
+ * Returns: the computed 32-bit CRC
97
+ */
98
+uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt,
99
+ unsigned zpads);
100
+
101
+/**
102
+ * xlnx_efuse_get_bit:
103
+ * @s: the efuse object
104
+ * @bit: the efuse bit-address to read the data
105
+ *
106
+ * Returns: the bit, 0 or 1, at @bit of object @s
107
+ */
108
+bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit);
109
+
110
+/**
111
+ * xlnx_efuse_set_bit:
112
+ * @s: the efuse object
113
+ * @bit: the efuse bit-address to be written a value of 1
114
+ *
115
+ * Returns: true on success, false on failure
116
+ */
117
+bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit);
118
+
119
+/**
120
+ * xlnx_efuse_k256_check:
121
+ * @s: the efuse object
122
+ * @crc: the 32-bit CRC to be compared with
123
+ * @start: the efuse bit-address (which must be multiple of 32) of the
124
+ * start of a 256-bit array
125
+ *
126
+ * This function computes the CRC of a 256-bit array starting at @start
127
+ * then compares to the given @crc
128
+ *
129
+ * Returns: true of @crc == computed, false otherwise
130
+ */
131
+bool xlnx_efuse_k256_check(XlnxEFuse *s, uint32_t crc, unsigned start);
132
+
133
+/**
134
+ * xlnx_efuse_tbits_check:
135
+ * @s: the efuse object
136
+ *
137
+ * This function inspects a number of efuse bits at specific addresses
138
+ * to see if they match a validation pattern. Each pattern is a group
139
+ * of 4 bits, and there are 3 groups.
140
+ *
141
+ * Returns: a 3-bit mask, where a bit of '1' means the corresponding
142
+ * group has a valid pattern.
143
+ */
144
+uint32_t xlnx_efuse_tbits_check(XlnxEFuse *s);
145
+
146
+/**
147
+ * xlnx_efuse_get_row:
148
+ * @s: the efuse object
149
+ * @bit: the efuse bit address for which a 32-bit value is read
150
+ *
151
+ * Returns: the entire 32 bits of the efuse, starting at a bit
152
+ * address that is multiple of 32 and contains the bit at @bit
153
+ */
154
+static inline uint32_t xlnx_efuse_get_row(XlnxEFuse *s, unsigned int bit)
155
+{
156
+ if (!(s->fuse32)) {
157
+ return 0;
158
+ } else {
159
+ unsigned int row_idx = bit / 32;
160
+
161
+ assert(row_idx < (s->efuse_size * s->efuse_nr / 32));
162
+ return s->fuse32[row_idx];
163
+ }
164
+}
165
+
166
+#endif
167
diff --git a/hw/nvram/xlnx-efuse-crc.c b/hw/nvram/xlnx-efuse-crc.c
168
new file mode 100644
169
index XXXXXXX..XXXXXXX
170
--- /dev/null
171
+++ b/hw/nvram/xlnx-efuse-crc.c
172
@@ -XXX,XX +XXX,XX @@
173
+/*
174
+ * Xilinx eFuse/bbram CRC calculator
175
+ *
176
+ * Copyright (c) 2021 Xilinx Inc.
177
+ *
178
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
179
+ * of this software and associated documentation files (the "Software"), to deal
180
+ * in the Software without restriction, including without limitation the rights
181
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
182
+ * copies of the Software, and to permit persons to whom the Software is
183
+ * furnished to do so, subject to the following conditions:
184
+ *
185
+ * The above copyright notice and this permission notice shall be included in
186
+ * all copies or substantial portions of the Software.
187
+ *
188
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
189
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
190
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
191
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
192
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
193
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
194
+ * THE SOFTWARE.
195
+ */
196
+#include "qemu/osdep.h"
197
+#include "hw/nvram/xlnx-efuse.h"
198
+
199
+static uint32_t xlnx_efuse_u37_crc(uint32_t prev_crc, uint32_t data,
200
+ uint32_t addr)
201
+{
202
+ /* A table for 7-bit slicing */
203
+ static const uint32_t crc_tab[128] = {
204
+ 0x00000000, 0xe13b70f7, 0xc79a971f, 0x26a1e7e8,
205
+ 0x8ad958cf, 0x6be22838, 0x4d43cfd0, 0xac78bf27,
206
+ 0x105ec76f, 0xf165b798, 0xd7c45070, 0x36ff2087,
207
+ 0x9a879fa0, 0x7bbcef57, 0x5d1d08bf, 0xbc267848,
208
+ 0x20bd8ede, 0xc186fe29, 0xe72719c1, 0x061c6936,
209
+ 0xaa64d611, 0x4b5fa6e6, 0x6dfe410e, 0x8cc531f9,
210
+ 0x30e349b1, 0xd1d83946, 0xf779deae, 0x1642ae59,
211
+ 0xba3a117e, 0x5b016189, 0x7da08661, 0x9c9bf696,
212
+ 0x417b1dbc, 0xa0406d4b, 0x86e18aa3, 0x67dafa54,
213
+ 0xcba24573, 0x2a993584, 0x0c38d26c, 0xed03a29b,
214
+ 0x5125dad3, 0xb01eaa24, 0x96bf4dcc, 0x77843d3b,
215
+ 0xdbfc821c, 0x3ac7f2eb, 0x1c661503, 0xfd5d65f4,
216
+ 0x61c69362, 0x80fde395, 0xa65c047d, 0x4767748a,
217
+ 0xeb1fcbad, 0x0a24bb5a, 0x2c855cb2, 0xcdbe2c45,
218
+ 0x7198540d, 0x90a324fa, 0xb602c312, 0x5739b3e5,
219
+ 0xfb410cc2, 0x1a7a7c35, 0x3cdb9bdd, 0xdde0eb2a,
220
+ 0x82f63b78, 0x63cd4b8f, 0x456cac67, 0xa457dc90,
221
+ 0x082f63b7, 0xe9141340, 0xcfb5f4a8, 0x2e8e845f,
222
+ 0x92a8fc17, 0x73938ce0, 0x55326b08, 0xb4091bff,
223
+ 0x1871a4d8, 0xf94ad42f, 0xdfeb33c7, 0x3ed04330,
224
+ 0xa24bb5a6, 0x4370c551, 0x65d122b9, 0x84ea524e,
225
+ 0x2892ed69, 0xc9a99d9e, 0xef087a76, 0x0e330a81,
226
+ 0xb21572c9, 0x532e023e, 0x758fe5d6, 0x94b49521,
227
+ 0x38cc2a06, 0xd9f75af1, 0xff56bd19, 0x1e6dcdee,
228
+ 0xc38d26c4, 0x22b65633, 0x0417b1db, 0xe52cc12c,
229
+ 0x49547e0b, 0xa86f0efc, 0x8ecee914, 0x6ff599e3,
230
+ 0xd3d3e1ab, 0x32e8915c, 0x144976b4, 0xf5720643,
231
+ 0x590ab964, 0xb831c993, 0x9e902e7b, 0x7fab5e8c,
232
+ 0xe330a81a, 0x020bd8ed, 0x24aa3f05, 0xc5914ff2,
233
+ 0x69e9f0d5, 0x88d28022, 0xae7367ca, 0x4f48173d,
234
+ 0xf36e6f75, 0x12551f82, 0x34f4f86a, 0xd5cf889d,
235
+ 0x79b737ba, 0x988c474d, 0xbe2da0a5, 0x5f16d052
236
+ };
237
+
238
+ /*
239
+ * eFuse calculation is shown here:
240
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1496
241
+ *
242
+ * Each u32 word is appended a 5-bit value, for a total of 37 bits; see:
243
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1356
244
+ */
245
+ uint32_t crc = prev_crc;
246
+ const unsigned rshf = 7;
247
+ const uint32_t im = (1 << rshf) - 1;
248
+ const uint32_t rm = (1 << (32 - rshf)) - 1;
249
+ const uint32_t i2 = (1 << 2) - 1;
250
+ const uint32_t r2 = (1 << 30) - 1;
251
+
252
+ unsigned j;
253
+ uint32_t i, r;
254
+ uint64_t w;
255
+
256
+ w = (uint64_t)(addr) << 32;
257
+ w |= data;
258
+
259
+ /* Feed 35 bits, in 5 rounds, each a slice of 7 bits */
260
+ for (j = 0; j < 5; j++) {
261
+ r = rm & (crc >> rshf);
262
+ i = im & (crc ^ w);
263
+ crc = crc_tab[i] ^ r;
264
+
265
+ w >>= rshf;
266
+ }
267
+
268
+ /* Feed the remaining 2 bits */
269
+ r = r2 & (crc >> 2);
270
+ i = i2 & (crc ^ w);
271
+ crc = crc_tab[i << (rshf - 2)] ^ r;
272
+
273
+ return crc;
274
+}
275
+
276
+uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt,
277
+ unsigned zpads)
278
+{
279
+ uint32_t crc = 0;
280
+ unsigned index;
281
+
282
+ for (index = zpads; index; index--) {
283
+ crc = xlnx_efuse_u37_crc(crc, 0, (index + u32_cnt));
284
+ }
285
+
286
+ for (index = u32_cnt; index; index--) {
287
+ crc = xlnx_efuse_u37_crc(crc, data[index - 1], index);
288
+ }
289
+
290
+ return crc;
291
+}
292
diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
293
new file mode 100644
294
index XXXXXXX..XXXXXXX
295
--- /dev/null
296
+++ b/hw/nvram/xlnx-efuse.c
297
@@ -XXX,XX +XXX,XX @@
298
+/*
299
+ * QEMU model of the EFUSE eFuse
300
+ *
301
+ * Copyright (c) 2015 Xilinx Inc.
302
+ *
303
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
304
+ *
305
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
306
+ * of this software and associated documentation files (the "Software"), to deal
307
+ * in the Software without restriction, including without limitation the rights
308
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
309
+ * copies of the Software, and to permit persons to whom the Software is
310
+ * furnished to do so, subject to the following conditions:
311
+ *
312
+ * The above copyright notice and this permission notice shall be included in
313
+ * all copies or substantial portions of the Software.
314
+ *
315
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
316
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
317
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
318
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
319
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
320
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
321
+ * THE SOFTWARE.
322
+ */
323
+
324
+#include "qemu/osdep.h"
325
+#include "hw/nvram/xlnx-efuse.h"
326
+
327
+#include "qemu/error-report.h"
328
+#include "qemu/log.h"
329
+#include "qapi/error.h"
330
+#include "sysemu/blockdev.h"
331
+#include "hw/qdev-properties.h"
332
+#include "hw/qdev-properties-system.h"
333
+
334
+#define TBIT0_OFFSET 28
335
+#define TBIT1_OFFSET 29
336
+#define TBIT2_OFFSET 30
337
+#define TBIT3_OFFSET 31
338
+#define TBITS_PATTERN (0x0AU << TBIT0_OFFSET)
339
+#define TBITS_MASK (0x0FU << TBIT0_OFFSET)
340
+
341
+bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit)
342
+{
343
+ bool b = s->fuse32[bit / 32] & (1 << (bit % 32));
344
+ return b;
345
+}
346
+
347
+static int efuse_bytes(XlnxEFuse *s)
348
+{
349
+ return ROUND_UP((s->efuse_nr * s->efuse_size) / 8, 4);
350
+}
351
+
352
+static int efuse_bdrv_read(XlnxEFuse *s, Error **errp)
353
+{
354
+ uint32_t *ram = s->fuse32;
355
+ int nr = efuse_bytes(s);
356
+
357
+ if (!s->blk) {
358
+ return 0;
359
+ }
360
+
361
+ s->blk_ro = !blk_supports_write_perm(s->blk);
362
+ if (!s->blk_ro) {
363
+ int rc;
364
+
365
+ rc = blk_set_perm(s->blk,
366
+ (BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE),
367
+ BLK_PERM_ALL, NULL);
368
+ if (rc) {
369
+ s->blk_ro = true;
370
+ }
371
+ }
372
+ if (s->blk_ro) {
373
+ warn_report("%s: Skip saving updates to read-only eFUSE backstore.",
374
+ blk_name(s->blk));
375
+ }
376
+
377
+ if (blk_pread(s->blk, 0, ram, nr) < 0) {
378
+ error_setg(errp, "%s: Failed to read %u bytes from eFUSE backstore.",
379
+ blk_name(s->blk), nr);
380
+ return -1;
381
+ }
382
+
383
+ /* Convert from little-endian backstore for each 32-bit row */
384
+ nr /= 4;
385
+ while (nr--) {
386
+ ram[nr] = le32_to_cpu(ram[nr]);
387
+ }
388
+
389
+ return 0;
390
+}
391
+
392
+static void efuse_bdrv_sync(XlnxEFuse *s, unsigned int bit)
393
+{
394
+ unsigned int row_offset;
395
+ uint32_t le32;
396
+
397
+ if (!s->blk || s->blk_ro) {
398
+ return; /* Silent on read-only backend to avoid message flood */
399
+ }
400
+
401
+ /* Backstore is always in little-endian */
402
+ le32 = cpu_to_le32(xlnx_efuse_get_row(s, bit));
403
+
404
+ row_offset = (bit / 32) * 4;
405
+ if (blk_pwrite(s->blk, row_offset, &le32, 4, 0) < 0) {
406
+ error_report("%s: Failed to write offset %u of eFUSE backstore.",
407
+ blk_name(s->blk), row_offset);
408
+ }
409
+}
410
+
411
+static int efuse_ro_bits_cmp(const void *a, const void *b)
412
+{
413
+ uint32_t i = *(const uint32_t *)a;
414
+ uint32_t j = *(const uint32_t *)b;
415
+
416
+ return (i > j) - (i < j);
417
+}
418
+
419
+static void efuse_ro_bits_sort(XlnxEFuse *s)
420
+{
421
+ uint32_t *ary = s->ro_bits;
422
+ const uint32_t cnt = s->ro_bits_cnt;
423
+
424
+ if (ary && cnt > 1) {
425
+ qsort(ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp);
426
+ }
427
+}
428
+
429
+static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k)
430
+{
431
+ const uint32_t *ary = s->ro_bits;
432
+ const uint32_t cnt = s->ro_bits_cnt;
433
+
434
+ if (!ary || !cnt) {
435
+ return false;
436
+ }
437
+
438
+ return bsearch(&k, ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp) != NULL;
439
+}
440
+
441
+bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
442
+{
443
+ if (efuse_ro_bits_find(s, bit)) {
444
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: WARN: "
445
+ "Ignored setting of readonly efuse bit<%u,%u>!\n",
446
+ object_get_canonical_path(OBJECT(s)),
447
+ (bit / 32), (bit % 32));
448
+ return false;
449
+ }
450
+
451
+ s->fuse32[bit / 32] |= 1 << (bit % 32);
452
+ efuse_bdrv_sync(s, bit);
453
+ return true;
454
+}
455
+
456
+bool xlnx_efuse_k256_check(XlnxEFuse *s, uint32_t crc, unsigned start)
457
+{
458
+ uint32_t calc;
459
+
460
+ /* A key always occupies multiple of whole rows */
461
+ assert((start % 32) == 0);
462
+
463
+ calc = xlnx_efuse_calc_crc(&s->fuse32[start / 32], (256 / 32), 0);
464
+ return calc == crc;
465
+}
466
+
467
+uint32_t xlnx_efuse_tbits_check(XlnxEFuse *s)
468
+{
469
+ int nr;
470
+ uint32_t check = 0;
471
+
472
+ for (nr = s->efuse_nr; nr-- > 0; ) {
473
+ int efuse_start_row_num = (s->efuse_size * nr) / 32;
474
+ uint32_t data = s->fuse32[efuse_start_row_num];
475
+
476
+ /*
477
+ * If the option is on, auto-init blank T-bits.
478
+ * (non-blank will still be reported as '0' in the check, e.g.,
479
+ * for error-injection tests)
480
+ */
481
+ if ((data & TBITS_MASK) == 0 && s->init_tbits) {
482
+ data |= TBITS_PATTERN;
483
+
484
+ s->fuse32[efuse_start_row_num] = data;
485
+ efuse_bdrv_sync(s, (efuse_start_row_num * 32 + TBIT0_OFFSET));
486
+ }
487
+
488
+ check = (check << 1) | ((data & TBITS_MASK) == TBITS_PATTERN);
489
+ }
490
+
491
+ return check;
492
+}
493
+
494
+static void efuse_realize(DeviceState *dev, Error **errp)
495
+{
496
+ XlnxEFuse *s = XLNX_EFUSE(dev);
497
+
498
+ /* Sort readonly-list for bsearch lookup */
499
+ efuse_ro_bits_sort(s);
500
+
501
+ if ((s->efuse_size % 32) != 0) {
502
+ error_setg(errp,
503
+ "%s.efuse-size: %u: property value not multiple of 32.",
504
+ object_get_canonical_path(OBJECT(dev)), s->efuse_size);
505
+ return;
506
+ }
507
+
508
+ s->fuse32 = g_malloc0(efuse_bytes(s));
509
+ if (efuse_bdrv_read(s, errp)) {
510
+ g_free(s->fuse32);
511
+ }
512
+}
513
+
514
+static void efuse_prop_set_drive(Object *obj, Visitor *v, const char *name,
515
+ void *opaque, Error **errp)
516
+{
517
+ DeviceState *dev = DEVICE(obj);
518
+
519
+ qdev_prop_drive.set(obj, v, name, opaque, errp);
520
+
521
+ /* Fill initial data if backend is attached after realized */
522
+ if (dev->realized) {
523
+ efuse_bdrv_read(XLNX_EFUSE(obj), errp);
524
+ }
525
+}
526
+
527
+static void efuse_prop_get_drive(Object *obj, Visitor *v, const char *name,
528
+ void *opaque, Error **errp)
529
+{
530
+ qdev_prop_drive.get(obj, v, name, opaque, errp);
531
+}
532
+
533
+static void efuse_prop_release_drive(Object *obj, const char *name,
534
+ void *opaque)
535
+{
536
+ qdev_prop_drive.release(obj, name, opaque);
537
+}
538
+
539
+static const PropertyInfo efuse_prop_drive = {
540
+ .name = "str",
541
+ .description = "Node name or ID of a block device to use as eFUSE backend",
542
+ .realized_set_allowed = true,
543
+ .get = efuse_prop_get_drive,
544
+ .set = efuse_prop_set_drive,
545
+ .release = efuse_prop_release_drive,
546
+};
547
+
548
+static Property efuse_properties[] = {
549
+ DEFINE_PROP("drive", XlnxEFuse, blk, efuse_prop_drive, BlockBackend *),
550
+ DEFINE_PROP_UINT8("efuse-nr", XlnxEFuse, efuse_nr, 3),
551
+ DEFINE_PROP_UINT32("efuse-size", XlnxEFuse, efuse_size, 64 * 32),
552
+ DEFINE_PROP_BOOL("init-factory-tbits", XlnxEFuse, init_tbits, true),
553
+ DEFINE_PROP_ARRAY("read-only", XlnxEFuse, ro_bits_cnt, ro_bits,
554
+ qdev_prop_uint32, uint32_t),
555
+ DEFINE_PROP_END_OF_LIST(),
556
+};
557
+
558
+static void efuse_class_init(ObjectClass *klass, void *data)
559
+{
560
+ DeviceClass *dc = DEVICE_CLASS(klass);
561
+
562
+ dc->realize = efuse_realize;
563
+ device_class_set_props(dc, efuse_properties);
564
+}
565
+
566
+static const TypeInfo efuse_info = {
567
+ .name = TYPE_XLNX_EFUSE,
568
+ .parent = TYPE_DEVICE,
569
+ .instance_size = sizeof(XlnxEFuse),
570
+ .class_init = efuse_class_init,
571
+};
572
+
573
+static void efuse_register_types(void)
574
+{
575
+ type_register_static(&efuse_info);
576
+}
577
+type_init(efuse_register_types)
578
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
579
index XXXXXXX..XXXXXXX 100644
580
--- a/hw/nvram/Kconfig
581
+++ b/hw/nvram/Kconfig
582
@@ -XXX,XX +XXX,XX @@ config NMC93XX_EEPROM
583
584
config CHRP_NVRAM
585
bool
586
+
587
+config XLNX_EFUSE_CRC
588
+ bool
589
+
590
+config XLNX_EFUSE
591
+ bool
592
+ select XLNX_EFUSE_CRC
593
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
594
index XXXXXXX..XXXXXXX 100644
595
--- a/hw/nvram/meson.build
596
+++ b/hw/nvram/meson.build
597
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_AT24C', if_true: files('eeprom_at24c.c'))
598
softmmu_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c'))
599
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
600
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
601
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c'))
602
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
603
604
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
605
--
606
2.20.1
607
608
diff view generated by jsdifflib
New patch
[PULL 04/22] hw/nvram: Introduce Xilinx Versal eFuse device
1
From: Tong Ho <tong.ho@xilinx.com>
1
2
3
This implements the Xilinx Versal eFuse, an one-time
4
field-programmable non-volatile storage device. There is
5
only one such device in the Xilinx Versal product family.
6
7
This device has two separate mmio interfaces, a controller
8
and a flatten readback.
9
10
The controller provides interfaces for field-programming,
11
configuration, control, and status.
12
13
The flatten readback is a cache to provide a byte-accessible
14
read-only interface to efficiently read efuse array.
15
16
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
17
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
18
19
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
20
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
21
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
22
Message-id: 20210917052400.1249094-3-tong.ho@xilinx.com
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
26
include/hw/nvram/xlnx-versal-efuse.h | 68 +++
27
hw/nvram/xlnx-versal-efuse-cache.c | 114 ++++
28
hw/nvram/xlnx-versal-efuse-ctrl.c | 783 +++++++++++++++++++++++++++
29
hw/nvram/Kconfig | 4 +
30
hw/nvram/meson.build | 3 +
31
5 files changed, 972 insertions(+)
32
create mode 100644 include/hw/nvram/xlnx-versal-efuse.h
33
create mode 100644 hw/nvram/xlnx-versal-efuse-cache.c
34
create mode 100644 hw/nvram/xlnx-versal-efuse-ctrl.c
35
36
diff --git a/include/hw/nvram/xlnx-versal-efuse.h b/include/hw/nvram/xlnx-versal-efuse.h
37
new file mode 100644
38
index XXXXXXX..XXXXXXX
39
--- /dev/null
40
+++ b/include/hw/nvram/xlnx-versal-efuse.h
41
@@ -XXX,XX +XXX,XX @@
42
+/*
43
+ * Copyright (c) 2020 Xilinx Inc.
44
+ *
45
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
46
+ * of this software and associated documentation files (the "Software"), to deal
47
+ * in the Software without restriction, including without limitation the rights
48
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
49
+ * copies of the Software, and to permit persons to whom the Software is
50
+ * furnished to do so, subject to the following conditions:
51
+ *
52
+ * The above copyright notice and this permission notice shall be included in
53
+ * all copies or substantial portions of the Software.
54
+ *
55
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
56
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
57
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
58
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
59
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
60
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
61
+ * THE SOFTWARE.
62
+ */
63
+#ifndef XLNX_VERSAL_EFUSE_H
64
+#define XLNX_VERSAL_EFUSE_H
65
+
66
+#include "hw/irq.h"
67
+#include "hw/sysbus.h"
68
+#include "hw/register.h"
69
+#include "hw/nvram/xlnx-efuse.h"
70
+
71
+#define XLNX_VERSAL_EFUSE_CTRL_R_MAX ((0x100 / 4) + 1)
72
+
73
+#define TYPE_XLNX_VERSAL_EFUSE_CTRL "xlnx,versal-efuse"
74
+#define TYPE_XLNX_VERSAL_EFUSE_CACHE "xlnx,pmc-efuse-cache"
75
+
76
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCtrl, XLNX_VERSAL_EFUSE_CTRL);
77
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCache, XLNX_VERSAL_EFUSE_CACHE);
78
+
79
+struct XlnxVersalEFuseCtrl {
80
+ SysBusDevice parent_obj;
81
+ qemu_irq irq_efuse_imr;
82
+
83
+ XlnxEFuse *efuse;
84
+
85
+ void *extra_pg0_lock_spec; /* Opaque property */
86
+ uint32_t extra_pg0_lock_n16;
87
+
88
+ uint32_t regs[XLNX_VERSAL_EFUSE_CTRL_R_MAX];
89
+ RegisterInfo regs_info[XLNX_VERSAL_EFUSE_CTRL_R_MAX];
90
+};
91
+
92
+struct XlnxVersalEFuseCache {
93
+ SysBusDevice parent_obj;
94
+ MemoryRegion iomem;
95
+
96
+ XlnxEFuse *efuse;
97
+};
98
+
99
+/**
100
+ * xlnx_versal_efuse_read_row:
101
+ * @s: the efuse object
102
+ * @bit: the bit-address within the 32-bit row to be read
103
+ * @denied: if non-NULL, to receive true if the row is write-only
104
+ *
105
+ * Returns: the 32-bit word containing address @bit; 0 if @denies is true
106
+ */
107
+uint32_t xlnx_versal_efuse_read_row(XlnxEFuse *s, uint32_t bit, bool *denied);
108
+
109
+#endif
110
diff --git a/hw/nvram/xlnx-versal-efuse-cache.c b/hw/nvram/xlnx-versal-efuse-cache.c
111
new file mode 100644
112
index XXXXXXX..XXXXXXX
113
--- /dev/null
114
+++ b/hw/nvram/xlnx-versal-efuse-cache.c
115
@@ -XXX,XX +XXX,XX @@
116
+/*
117
+ * QEMU model of the EFuse_Cache
118
+ *
119
+ * Copyright (c) 2017 Xilinx Inc.
120
+ *
121
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
122
+ * of this software and associated documentation files (the "Software"), to deal
123
+ * in the Software without restriction, including without limitation the rights
124
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
125
+ * copies of the Software, and to permit persons to whom the Software is
126
+ * furnished to do so, subject to the following conditions:
127
+ *
128
+ * The above copyright notice and this permission notice shall be included in
129
+ * all copies or substantial portions of the Software.
130
+ *
131
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
132
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
133
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
134
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
135
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
136
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
137
+ * THE SOFTWARE.
138
+ */
139
+
140
+#include "qemu/osdep.h"
141
+#include "hw/nvram/xlnx-versal-efuse.h"
142
+
143
+#include "qemu/log.h"
144
+#include "hw/qdev-properties.h"
145
+
146
+#define MR_SIZE 0xC00
147
+
148
+static uint64_t efuse_cache_read(void *opaque, hwaddr addr, unsigned size)
149
+{
150
+ XlnxVersalEFuseCache *s = XLNX_VERSAL_EFUSE_CACHE(opaque);
151
+ unsigned int w0 = QEMU_ALIGN_DOWN(addr * 8, 32);
152
+ unsigned int w1 = QEMU_ALIGN_DOWN((addr + size - 1) * 8, 32);
153
+
154
+ uint64_t ret;
155
+
156
+ assert(w0 == w1 || (w0 + 32) == w1);
157
+
158
+ ret = xlnx_versal_efuse_read_row(s->efuse, w1, NULL);
159
+ if (w0 < w1) {
160
+ ret <<= 32;
161
+ ret |= xlnx_versal_efuse_read_row(s->efuse, w0, NULL);
162
+ }
163
+
164
+ /* If 'addr' unaligned, the guest is always assumed to be little-endian. */
165
+ addr &= 3;
166
+ if (addr) {
167
+ ret >>= 8 * addr;
168
+ }
169
+
170
+ return ret;
171
+}
172
+
173
+static void efuse_cache_write(void *opaque, hwaddr addr, uint64_t value,
174
+ unsigned size)
175
+{
176
+ /* No Register Writes allowed */
177
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: efuse cache registers are read-only",
178
+ __func__);
179
+}
180
+
181
+static const MemoryRegionOps efuse_cache_ops = {
182
+ .read = efuse_cache_read,
183
+ .write = efuse_cache_write,
184
+ .endianness = DEVICE_LITTLE_ENDIAN,
185
+ .valid = {
186
+ .min_access_size = 1,
187
+ .max_access_size = 4,
188
+ },
189
+};
190
+
191
+static void efuse_cache_init(Object *obj)
192
+{
193
+ XlnxVersalEFuseCache *s = XLNX_VERSAL_EFUSE_CACHE(obj);
194
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
195
+
196
+ memory_region_init_io(&s->iomem, obj, &efuse_cache_ops, s,
197
+ TYPE_XLNX_VERSAL_EFUSE_CACHE, MR_SIZE);
198
+ sysbus_init_mmio(sbd, &s->iomem);
199
+}
200
+
201
+static Property efuse_cache_props[] = {
202
+ DEFINE_PROP_LINK("efuse",
203
+ XlnxVersalEFuseCache, efuse,
204
+ TYPE_XLNX_EFUSE, XlnxEFuse *),
205
+
206
+ DEFINE_PROP_END_OF_LIST(),
207
+};
208
+
209
+static void efuse_cache_class_init(ObjectClass *klass, void *data)
210
+{
211
+ DeviceClass *dc = DEVICE_CLASS(klass);
212
+
213
+ device_class_set_props(dc, efuse_cache_props);
214
+}
215
+
216
+static const TypeInfo efuse_cache_info = {
217
+ .name = TYPE_XLNX_VERSAL_EFUSE_CACHE,
218
+ .parent = TYPE_SYS_BUS_DEVICE,
219
+ .instance_size = sizeof(XlnxVersalEFuseCache),
220
+ .class_init = efuse_cache_class_init,
221
+ .instance_init = efuse_cache_init,
222
+};
223
+
224
+static void efuse_cache_register_types(void)
225
+{
226
+ type_register_static(&efuse_cache_info);
227
+}
228
+
229
+type_init(efuse_cache_register_types)
230
diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c
231
new file mode 100644
232
index XXXXXXX..XXXXXXX
233
--- /dev/null
234
+++ b/hw/nvram/xlnx-versal-efuse-ctrl.c
235
@@ -XXX,XX +XXX,XX @@
236
+/*
237
+ * QEMU model of the Versal eFuse controller
238
+ *
239
+ * Copyright (c) 2020 Xilinx Inc.
240
+ *
241
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
242
+ * of this software and associated documentation files (the "Software"), to deal
243
+ * in the Software without restriction, including without limitation the rights
244
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
245
+ * copies of the Software, and to permit persons to whom the Software is
246
+ * furnished to do so, subject to the following conditions:
247
+ *
248
+ * The above copyright notice and this permission notice shall be included in
249
+ * all copies or substantial portions of the Software.
250
+ *
251
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
252
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
253
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
254
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
255
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
256
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
257
+ * THE SOFTWARE.
258
+ */
259
+
260
+#include "qemu/osdep.h"
261
+#include "hw/nvram/xlnx-versal-efuse.h"
262
+
263
+#include "qemu/log.h"
264
+#include "qapi/error.h"
265
+#include "migration/vmstate.h"
266
+#include "hw/qdev-properties.h"
267
+
268
+#ifndef XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG
269
+#define XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG 0
270
+#endif
271
+
272
+REG32(WR_LOCK, 0x0)
273
+ FIELD(WR_LOCK, LOCK, 0, 16)
274
+REG32(CFG, 0x4)
275
+ FIELD(CFG, SLVERR_ENABLE, 5, 1)
276
+ FIELD(CFG, MARGIN_RD, 2, 1)
277
+ FIELD(CFG, PGM_EN, 1, 1)
278
+REG32(STATUS, 0x8)
279
+ FIELD(STATUS, AES_USER_KEY_1_CRC_PASS, 11, 1)
280
+ FIELD(STATUS, AES_USER_KEY_1_CRC_DONE, 10, 1)
281
+ FIELD(STATUS, AES_USER_KEY_0_CRC_PASS, 9, 1)
282
+ FIELD(STATUS, AES_USER_KEY_0_CRC_DONE, 8, 1)
283
+ FIELD(STATUS, AES_CRC_PASS, 7, 1)
284
+ FIELD(STATUS, AES_CRC_DONE, 6, 1)
285
+ FIELD(STATUS, CACHE_DONE, 5, 1)
286
+ FIELD(STATUS, CACHE_LOAD, 4, 1)
287
+ FIELD(STATUS, EFUSE_2_TBIT, 2, 1)
288
+ FIELD(STATUS, EFUSE_1_TBIT, 1, 1)
289
+ FIELD(STATUS, EFUSE_0_TBIT, 0, 1)
290
+REG32(EFUSE_PGM_ADDR, 0xc)
291
+ FIELD(EFUSE_PGM_ADDR, PAGE, 13, 4)
292
+ FIELD(EFUSE_PGM_ADDR, ROW, 5, 8)
293
+ FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5)
294
+REG32(EFUSE_RD_ADDR, 0x10)
295
+ FIELD(EFUSE_RD_ADDR, PAGE, 13, 4)
296
+ FIELD(EFUSE_RD_ADDR, ROW, 5, 8)
297
+REG32(EFUSE_RD_DATA, 0x14)
298
+REG32(TPGM, 0x18)
299
+ FIELD(TPGM, VALUE, 0, 16)
300
+REG32(TRD, 0x1c)
301
+ FIELD(TRD, VALUE, 0, 8)
302
+REG32(TSU_H_PS, 0x20)
303
+ FIELD(TSU_H_PS, VALUE, 0, 8)
304
+REG32(TSU_H_PS_CS, 0x24)
305
+ FIELD(TSU_H_PS_CS, VALUE, 0, 8)
306
+REG32(TRDM, 0x28)
307
+ FIELD(TRDM, VALUE, 0, 8)
308
+REG32(TSU_H_CS, 0x2c)
309
+ FIELD(TSU_H_CS, VALUE, 0, 8)
310
+REG32(EFUSE_ISR, 0x30)
311
+ FIELD(EFUSE_ISR, APB_SLVERR, 31, 1)
312
+ FIELD(EFUSE_ISR, CACHE_PARITY_E2, 14, 1)
313
+ FIELD(EFUSE_ISR, CACHE_PARITY_E1, 13, 1)
314
+ FIELD(EFUSE_ISR, CACHE_PARITY_E0S, 12, 1)
315
+ FIELD(EFUSE_ISR, CACHE_PARITY_E0R, 11, 1)
316
+ FIELD(EFUSE_ISR, CACHE_APB_SLVERR, 10, 1)
317
+ FIELD(EFUSE_ISR, CACHE_REQ_ERROR, 9, 1)
318
+ FIELD(EFUSE_ISR, MAIN_REQ_ERROR, 8, 1)
319
+ FIELD(EFUSE_ISR, READ_ON_CACHE_LD, 7, 1)
320
+ FIELD(EFUSE_ISR, CACHE_FSM_ERROR, 6, 1)
321
+ FIELD(EFUSE_ISR, MAIN_FSM_ERROR, 5, 1)
322
+ FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1)
323
+ FIELD(EFUSE_ISR, RD_ERROR, 3, 1)
324
+ FIELD(EFUSE_ISR, RD_DONE, 2, 1)
325
+ FIELD(EFUSE_ISR, PGM_ERROR, 1, 1)
326
+ FIELD(EFUSE_ISR, PGM_DONE, 0, 1)
327
+REG32(EFUSE_IMR, 0x34)
328
+ FIELD(EFUSE_IMR, APB_SLVERR, 31, 1)
329
+ FIELD(EFUSE_IMR, CACHE_PARITY_E2, 14, 1)
330
+ FIELD(EFUSE_IMR, CACHE_PARITY_E1, 13, 1)
331
+ FIELD(EFUSE_IMR, CACHE_PARITY_E0S, 12, 1)
332
+ FIELD(EFUSE_IMR, CACHE_PARITY_E0R, 11, 1)
333
+ FIELD(EFUSE_IMR, CACHE_APB_SLVERR, 10, 1)
334
+ FIELD(EFUSE_IMR, CACHE_REQ_ERROR, 9, 1)
335
+ FIELD(EFUSE_IMR, MAIN_REQ_ERROR, 8, 1)
336
+ FIELD(EFUSE_IMR, READ_ON_CACHE_LD, 7, 1)
337
+ FIELD(EFUSE_IMR, CACHE_FSM_ERROR, 6, 1)
338
+ FIELD(EFUSE_IMR, MAIN_FSM_ERROR, 5, 1)
339
+ FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1)
340
+ FIELD(EFUSE_IMR, RD_ERROR, 3, 1)
341
+ FIELD(EFUSE_IMR, RD_DONE, 2, 1)
342
+ FIELD(EFUSE_IMR, PGM_ERROR, 1, 1)
343
+ FIELD(EFUSE_IMR, PGM_DONE, 0, 1)
344
+REG32(EFUSE_IER, 0x38)
345
+ FIELD(EFUSE_IER, APB_SLVERR, 31, 1)
346
+ FIELD(EFUSE_IER, CACHE_PARITY_E2, 14, 1)
347
+ FIELD(EFUSE_IER, CACHE_PARITY_E1, 13, 1)
348
+ FIELD(EFUSE_IER, CACHE_PARITY_E0S, 12, 1)
349
+ FIELD(EFUSE_IER, CACHE_PARITY_E0R, 11, 1)
350
+ FIELD(EFUSE_IER, CACHE_APB_SLVERR, 10, 1)
351
+ FIELD(EFUSE_IER, CACHE_REQ_ERROR, 9, 1)
352
+ FIELD(EFUSE_IER, MAIN_REQ_ERROR, 8, 1)
353
+ FIELD(EFUSE_IER, READ_ON_CACHE_LD, 7, 1)
354
+ FIELD(EFUSE_IER, CACHE_FSM_ERROR, 6, 1)
355
+ FIELD(EFUSE_IER, MAIN_FSM_ERROR, 5, 1)
356
+ FIELD(EFUSE_IER, CACHE_ERROR, 4, 1)
357
+ FIELD(EFUSE_IER, RD_ERROR, 3, 1)
358
+ FIELD(EFUSE_IER, RD_DONE, 2, 1)
359
+ FIELD(EFUSE_IER, PGM_ERROR, 1, 1)
360
+ FIELD(EFUSE_IER, PGM_DONE, 0, 1)
361
+REG32(EFUSE_IDR, 0x3c)
362
+ FIELD(EFUSE_IDR, APB_SLVERR, 31, 1)
363
+ FIELD(EFUSE_IDR, CACHE_PARITY_E2, 14, 1)
364
+ FIELD(EFUSE_IDR, CACHE_PARITY_E1, 13, 1)
365
+ FIELD(EFUSE_IDR, CACHE_PARITY_E0S, 12, 1)
366
+ FIELD(EFUSE_IDR, CACHE_PARITY_E0R, 11, 1)
367
+ FIELD(EFUSE_IDR, CACHE_APB_SLVERR, 10, 1)
368
+ FIELD(EFUSE_IDR, CACHE_REQ_ERROR, 9, 1)
369
+ FIELD(EFUSE_IDR, MAIN_REQ_ERROR, 8, 1)
370
+ FIELD(EFUSE_IDR, READ_ON_CACHE_LD, 7, 1)
371
+ FIELD(EFUSE_IDR, CACHE_FSM_ERROR, 6, 1)
372
+ FIELD(EFUSE_IDR, MAIN_FSM_ERROR, 5, 1)
373
+ FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1)
374
+ FIELD(EFUSE_IDR, RD_ERROR, 3, 1)
375
+ FIELD(EFUSE_IDR, RD_DONE, 2, 1)
376
+ FIELD(EFUSE_IDR, PGM_ERROR, 1, 1)
377
+ FIELD(EFUSE_IDR, PGM_DONE, 0, 1)
378
+REG32(EFUSE_CACHE_LOAD, 0x40)
379
+ FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1)
380
+REG32(EFUSE_PGM_LOCK, 0x44)
381
+ FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1)
382
+REG32(EFUSE_AES_CRC, 0x48)
383
+REG32(EFUSE_AES_USR_KEY0_CRC, 0x4c)
384
+REG32(EFUSE_AES_USR_KEY1_CRC, 0x50)
385
+REG32(EFUSE_PD, 0x54)
386
+REG32(EFUSE_ANLG_OSC_SW_1LP, 0x60)
387
+REG32(EFUSE_TEST_CTRL, 0x100)
388
+
389
+#define R_MAX (R_EFUSE_TEST_CTRL + 1)
390
+
391
+#define R_WR_LOCK_UNLOCK_PASSCODE (0xDF0D)
392
+
393
+/*
394
+ * eFuse layout references:
395
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilnvm/src/xnvm_efuse_hw.h
396
+ */
397
+#define BIT_POS_OF(A_) \
398
+ ((uint32_t)((A_) & (R_EFUSE_PGM_ADDR_ROW_MASK | \
399
+ R_EFUSE_PGM_ADDR_COLUMN_MASK)))
400
+
401
+#define BIT_POS(R_, C_) \
402
+ ((uint32_t)((R_EFUSE_PGM_ADDR_ROW_MASK \
403
+ & ((R_) << R_EFUSE_PGM_ADDR_ROW_SHIFT)) \
404
+ | \
405
+ (R_EFUSE_PGM_ADDR_COLUMN_MASK \
406
+ & ((C_) << R_EFUSE_PGM_ADDR_COLUMN_SHIFT))))
407
+
408
+#define EFUSE_TBIT_POS(A_) (BIT_POS_OF(A_) >= BIT_POS(0, 28))
409
+
410
+#define EFUSE_ANCHOR_ROW (0)
411
+#define EFUSE_ANCHOR_3_COL (27)
412
+#define EFUSE_ANCHOR_1_COL (1)
413
+
414
+#define EFUSE_AES_KEY_START BIT_POS(12, 0)
415
+#define EFUSE_AES_KEY_END BIT_POS(19, 31)
416
+#define EFUSE_USER_KEY_0_START BIT_POS(20, 0)
417
+#define EFUSE_USER_KEY_0_END BIT_POS(27, 31)
418
+#define EFUSE_USER_KEY_1_START BIT_POS(28, 0)
419
+#define EFUSE_USER_KEY_1_END BIT_POS(35, 31)
420
+
421
+#define EFUSE_RD_BLOCKED_START EFUSE_AES_KEY_START
422
+#define EFUSE_RD_BLOCKED_END EFUSE_USER_KEY_1_END
423
+
424
+#define EFUSE_GLITCH_DET_WR_LK BIT_POS(4, 31)
425
+#define EFUSE_PPK0_WR_LK BIT_POS(43, 6)
426
+#define EFUSE_PPK1_WR_LK BIT_POS(43, 7)
427
+#define EFUSE_PPK2_WR_LK BIT_POS(43, 8)
428
+#define EFUSE_AES_WR_LK BIT_POS(43, 11)
429
+#define EFUSE_USER_KEY_0_WR_LK BIT_POS(43, 13)
430
+#define EFUSE_USER_KEY_1_WR_LK BIT_POS(43, 15)
431
+#define EFUSE_PUF_SYN_LK BIT_POS(43, 16)
432
+#define EFUSE_DNA_WR_LK BIT_POS(43, 27)
433
+#define EFUSE_BOOT_ENV_WR_LK BIT_POS(43, 28)
434
+
435
+#define EFUSE_PGM_LOCKED_START BIT_POS(44, 0)
436
+#define EFUSE_PGM_LOCKED_END BIT_POS(51, 31)
437
+
438
+#define EFUSE_PUF_PAGE (2)
439
+#define EFUSE_PUF_SYN_START BIT_POS(129, 0)
440
+#define EFUSE_PUF_SYN_END BIT_POS(255, 27)
441
+
442
+#define EFUSE_KEY_CRC_LK_ROW (43)
443
+#define EFUSE_AES_KEY_CRC_LK_MASK ((1U << 9) | (1U << 10))
444
+#define EFUSE_USER_KEY_0_CRC_LK_MASK (1U << 12)
445
+#define EFUSE_USER_KEY_1_CRC_LK_MASK (1U << 14)
446
+
447
+/*
448
+ * A handy macro to return value of an array element,
449
+ * or a specific default if given index is out of bound.
450
+ */
451
+#define ARRAY_GET(A_, I_, D_) \
452
+ ((unsigned int)(I_) < ARRAY_SIZE(A_) ? (A_)[I_] : (D_))
453
+
454
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxVersalEFuseCtrl *)0)->regs));
455
+
456
+typedef struct XlnxEFuseLkSpec {
457
+ uint16_t row;
458
+ uint16_t lk_bit;
459
+} XlnxEFuseLkSpec;
460
+
461
+static void efuse_imr_update_irq(XlnxVersalEFuseCtrl *s)
462
+{
463
+ bool pending = s->regs[R_EFUSE_ISR] & ~s->regs[R_EFUSE_IMR];
464
+ qemu_set_irq(s->irq_efuse_imr, pending);
465
+}
466
+
467
+static void efuse_isr_postw(RegisterInfo *reg, uint64_t val64)
468
+{
469
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
470
+ efuse_imr_update_irq(s);
471
+}
472
+
473
+static uint64_t efuse_ier_prew(RegisterInfo *reg, uint64_t val64)
474
+{
475
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
476
+ uint32_t val = val64;
477
+
478
+ s->regs[R_EFUSE_IMR] &= ~val;
479
+ efuse_imr_update_irq(s);
480
+ return 0;
481
+}
482
+
483
+static uint64_t efuse_idr_prew(RegisterInfo *reg, uint64_t val64)
484
+{
485
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
486
+ uint32_t val = val64;
487
+
488
+ s->regs[R_EFUSE_IMR] |= val;
489
+ efuse_imr_update_irq(s);
490
+ return 0;
491
+}
492
+
493
+static void efuse_status_tbits_sync(XlnxVersalEFuseCtrl *s)
494
+{
495
+ uint32_t check = xlnx_efuse_tbits_check(s->efuse);
496
+ uint32_t val = s->regs[R_STATUS];
497
+
498
+ val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0)));
499
+ val = FIELD_DP32(val, STATUS, EFUSE_1_TBIT, !!(check & (1 << 1)));
500
+ val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 2)));
501
+
502
+ s->regs[R_STATUS] = val;
503
+}
504
+
505
+static void efuse_anchor_bits_check(XlnxVersalEFuseCtrl *s)
506
+{
507
+ unsigned page;
508
+
509
+ if (!s->efuse || !s->efuse->init_tbits) {
510
+ return;
511
+ }
512
+
513
+ for (page = 0; page < s->efuse->efuse_nr; page++) {
514
+ uint32_t row = 0, bit;
515
+
516
+ row = FIELD_DP32(row, EFUSE_PGM_ADDR, PAGE, page);
517
+ row = FIELD_DP32(row, EFUSE_PGM_ADDR, ROW, EFUSE_ANCHOR_ROW);
518
+
519
+ bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_3_COL);
520
+ if (!xlnx_efuse_get_bit(s->efuse, bit)) {
521
+ xlnx_efuse_set_bit(s->efuse, bit);
522
+ }
523
+
524
+ bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_1_COL);
525
+ if (!xlnx_efuse_get_bit(s->efuse, bit)) {
526
+ xlnx_efuse_set_bit(s->efuse, bit);
527
+ }
528
+ }
529
+}
530
+
531
+static void efuse_key_crc_check(RegisterInfo *reg, uint32_t crc,
532
+ uint32_t pass_mask, uint32_t done_mask,
533
+ unsigned first, uint32_t lk_mask)
534
+{
535
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
536
+ uint32_t r, lk_bits;
537
+
538
+ /*
539
+ * To start, assume both DONE and PASS, and clear PASS by xor
540
+ * if CRC-check fails or CRC-check disabled by lock fuse.
541
+ */
542
+ r = s->regs[R_STATUS] | done_mask | pass_mask;
543
+
544
+ lk_bits = xlnx_efuse_get_row(s->efuse, EFUSE_KEY_CRC_LK_ROW) & lk_mask;
545
+ if (lk_bits == 0 && xlnx_efuse_k256_check(s->efuse, crc, first)) {
546
+ pass_mask = 0;
547
+ }
548
+
549
+ s->regs[R_STATUS] = r ^ pass_mask;
550
+}
551
+
552
+static void efuse_data_sync(XlnxVersalEFuseCtrl *s)
553
+{
554
+ efuse_status_tbits_sync(s);
555
+}
556
+
557
+static int efuse_lk_spec_cmp(const void *a, const void *b)
558
+{
559
+ uint16_t r1 = ((const XlnxEFuseLkSpec *)a)->row;
560
+ uint16_t r2 = ((const XlnxEFuseLkSpec *)b)->row;
561
+
562
+ return (r1 > r2) - (r1 < r2);
563
+}
564
+
565
+static void efuse_lk_spec_sort(XlnxVersalEFuseCtrl *s)
566
+{
567
+ XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec;
568
+ const uint32_t n8 = s->extra_pg0_lock_n16 * 2;
569
+ const uint32_t sz = sizeof(ary[0]);
570
+ const uint32_t cnt = n8 / sz;
571
+
572
+ if (ary && cnt) {
573
+ qsort(ary, cnt, sz, efuse_lk_spec_cmp);
574
+ }
575
+}
576
+
577
+static uint32_t efuse_lk_spec_find(XlnxVersalEFuseCtrl *s, uint32_t row)
578
+{
579
+ const XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec;
580
+ const uint32_t n8 = s->extra_pg0_lock_n16 * 2;
581
+ const uint32_t sz = sizeof(ary[0]);
582
+ const uint32_t cnt = n8 / sz;
583
+ const XlnxEFuseLkSpec *item = NULL;
584
+
585
+ if (ary && cnt) {
586
+ XlnxEFuseLkSpec k = { .row = row, };
587
+
588
+ item = bsearch(&k, ary, cnt, sz, efuse_lk_spec_cmp);
589
+ }
590
+
591
+ return item ? item->lk_bit : 0;
592
+}
593
+
594
+static uint32_t efuse_bit_locked(XlnxVersalEFuseCtrl *s, uint32_t bit)
595
+{
596
+ /* Hard-coded locks */
597
+ static const uint16_t pg0_hard_lock[] = {
598
+ [4] = EFUSE_GLITCH_DET_WR_LK,
599
+ [37] = EFUSE_BOOT_ENV_WR_LK,
600
+
601
+ [8 ... 11] = EFUSE_DNA_WR_LK,
602
+ [12 ... 19] = EFUSE_AES_WR_LK,
603
+ [20 ... 27] = EFUSE_USER_KEY_0_WR_LK,
604
+ [28 ... 35] = EFUSE_USER_KEY_1_WR_LK,
605
+ [64 ... 71] = EFUSE_PPK0_WR_LK,
606
+ [72 ... 79] = EFUSE_PPK1_WR_LK,
607
+ [80 ... 87] = EFUSE_PPK2_WR_LK,
608
+ };
609
+
610
+ uint32_t row = FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW);
611
+ uint32_t lk_bit = ARRAY_GET(pg0_hard_lock, row, 0);
612
+
613
+ return lk_bit ? lk_bit : efuse_lk_spec_find(s, row);
614
+}
615
+
616
+static bool efuse_pgm_locked(XlnxVersalEFuseCtrl *s, unsigned int bit)
617
+{
618
+
619
+ unsigned int lock = 1;
620
+
621
+ /* Global lock */
622
+ if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) {
623
+ goto ret_lock;
624
+ }
625
+
626
+ /* Row lock */
627
+ switch (FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE)) {
628
+ case 0:
629
+ if (ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK) &&
630
+ bit >= EFUSE_PGM_LOCKED_START && bit <= EFUSE_PGM_LOCKED_END) {
631
+ goto ret_lock;
632
+ }
633
+
634
+ lock = efuse_bit_locked(s, bit);
635
+ break;
636
+ case EFUSE_PUF_PAGE:
637
+ if (bit < EFUSE_PUF_SYN_START || bit > EFUSE_PUF_SYN_END) {
638
+ lock = 0;
639
+ goto ret_lock;
640
+ }
641
+
642
+ lock = EFUSE_PUF_SYN_LK;
643
+ break;
644
+ default:
645
+ lock = 0;
646
+ goto ret_lock;
647
+ }
648
+
649
+ /* Row lock by an efuse bit */
650
+ if (lock) {
651
+ lock = xlnx_efuse_get_bit(s->efuse, lock);
652
+ }
653
+
654
+ ret_lock:
655
+ return lock != 0;
656
+}
657
+
658
+static void efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64)
659
+{
660
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
661
+ unsigned bit = val64;
662
+ bool ok = false;
663
+
664
+ /* Always zero out PGM_ADDR because it is write-only */
665
+ s->regs[R_EFUSE_PGM_ADDR] = 0;
666
+
667
+ /*
668
+ * Indicate error if bit is write-protected (or read-only
669
+ * as guarded by efuse_set_bit()).
670
+ *
671
+ * Keep it simple by not modeling program timing.
672
+ *
673
+ * Note: model must NEVER clear the PGM_ERROR bit; it is
674
+ * up to guest to do so (or by reset).
675
+ */
676
+ if (efuse_pgm_locked(s, bit)) {
677
+ qemu_log_mask(LOG_GUEST_ERROR,
678
+ "%s: Denied setting of efuse<%u, %u, %u>\n",
679
+ object_get_canonical_path(OBJECT(s)),
680
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE),
681
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW),
682
+ FIELD_EX32(bit, EFUSE_PGM_ADDR, COLUMN));
683
+ } else if (xlnx_efuse_set_bit(s->efuse, bit)) {
684
+ ok = true;
685
+ if (EFUSE_TBIT_POS(bit)) {
686
+ efuse_status_tbits_sync(s);
687
+ }
688
+ }
689
+
690
+ if (!ok) {
691
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1);
692
+ }
693
+
694
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1);
695
+ efuse_imr_update_irq(s);
696
+}
697
+
698
+static void efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64)
699
+{
700
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
701
+ unsigned bit = val64;
702
+ bool denied;
703
+
704
+ /* Always zero out RD_ADDR because it is write-only */
705
+ s->regs[R_EFUSE_RD_ADDR] = 0;
706
+
707
+ /*
708
+ * Indicate error if row is read-blocked.
709
+ *
710
+ * Note: model must NEVER clear the RD_ERROR bit; it is
711
+ * up to guest to do so (or by reset).
712
+ */
713
+ s->regs[R_EFUSE_RD_DATA] = xlnx_versal_efuse_read_row(s->efuse,
714
+ bit, &denied);
715
+ if (denied) {
716
+ qemu_log_mask(LOG_GUEST_ERROR,
717
+ "%s: Denied reading of efuse<%u, %u>\n",
718
+ object_get_canonical_path(OBJECT(s)),
719
+ FIELD_EX32(bit, EFUSE_RD_ADDR, PAGE),
720
+ FIELD_EX32(bit, EFUSE_RD_ADDR, ROW));
721
+
722
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1);
723
+ }
724
+
725
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1);
726
+ efuse_imr_update_irq(s);
727
+ return;
728
+}
729
+
730
+static uint64_t efuse_cache_load_prew(RegisterInfo *reg, uint64_t val64)
731
+{
732
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
733
+
734
+ if (val64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) {
735
+ efuse_data_sync(s);
736
+
737
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
738
+ efuse_imr_update_irq(s);
739
+ }
740
+
741
+ return 0;
742
+}
743
+
744
+static uint64_t efuse_pgm_lock_prew(RegisterInfo *reg, uint64_t val64)
745
+{
746
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque);
747
+
748
+ /* Ignore all other bits */
749
+ val64 = FIELD_EX32(val64, EFUSE_PGM_LOCK, SPK_ID_LOCK);
750
+
751
+ /* Once the bit is written 1, only reset will clear it to 0 */
752
+ val64 |= ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK);
753
+
754
+ return val64;
755
+}
756
+
757
+static void efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
758
+{
759
+ efuse_key_crc_check(reg, val64,
760
+ R_STATUS_AES_CRC_PASS_MASK,
761
+ R_STATUS_AES_CRC_DONE_MASK,
762
+ EFUSE_AES_KEY_START,
763
+ EFUSE_AES_KEY_CRC_LK_MASK);
764
+}
765
+
766
+static void efuse_aes_u0_crc_postw(RegisterInfo *reg, uint64_t val64)
767
+{
768
+ efuse_key_crc_check(reg, val64,
769
+ R_STATUS_AES_USER_KEY_0_CRC_PASS_MASK,
770
+ R_STATUS_AES_USER_KEY_0_CRC_DONE_MASK,
771
+ EFUSE_USER_KEY_0_START,
772
+ EFUSE_USER_KEY_0_CRC_LK_MASK);
773
+}
774
+
775
+static void efuse_aes_u1_crc_postw(RegisterInfo *reg, uint64_t val64)
776
+{
777
+ efuse_key_crc_check(reg, val64,
778
+ R_STATUS_AES_USER_KEY_1_CRC_PASS_MASK,
779
+ R_STATUS_AES_USER_KEY_1_CRC_DONE_MASK,
780
+ EFUSE_USER_KEY_1_START,
781
+ EFUSE_USER_KEY_1_CRC_LK_MASK);
782
+}
783
+
784
+static uint64_t efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val)
785
+{
786
+ return val != R_WR_LOCK_UNLOCK_PASSCODE;
787
+}
788
+
789
+static const RegisterAccessInfo efuse_ctrl_regs_info[] = {
790
+ { .name = "WR_LOCK", .addr = A_WR_LOCK,
791
+ .reset = 0x1,
792
+ .pre_write = efuse_wr_lock_prew,
793
+ },{ .name = "CFG", .addr = A_CFG,
794
+ .rsvd = 0x9,
795
+ },{ .name = "STATUS", .addr = A_STATUS,
796
+ .rsvd = 0x8,
797
+ .ro = 0xfff,
798
+ },{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR,
799
+ .post_write = efuse_pgm_addr_postw,
800
+ },{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR,
801
+ .rsvd = 0x1f,
802
+ .post_write = efuse_rd_addr_postw,
803
+ },{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA,
804
+ .ro = 0xffffffff,
805
+ },{ .name = "TPGM", .addr = A_TPGM,
806
+ },{ .name = "TRD", .addr = A_TRD,
807
+ .reset = 0x19,
808
+ },{ .name = "TSU_H_PS", .addr = A_TSU_H_PS,
809
+ .reset = 0xff,
810
+ },{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS,
811
+ .reset = 0x11,
812
+ },{ .name = "TRDM", .addr = A_TRDM,
813
+ .reset = 0x3a,
814
+ },{ .name = "TSU_H_CS", .addr = A_TSU_H_CS,
815
+ .reset = 0x16,
816
+ },{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR,
817
+ .rsvd = 0x7fff8000,
818
+ .w1c = 0x80007fff,
819
+ .post_write = efuse_isr_postw,
820
+ },{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR,
821
+ .reset = 0x80007fff,
822
+ .rsvd = 0x7fff8000,
823
+ .ro = 0xffffffff,
824
+ },{ .name = "EFUSE_IER", .addr = A_EFUSE_IER,
825
+ .rsvd = 0x7fff8000,
826
+ .pre_write = efuse_ier_prew,
827
+ },{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR,
828
+ .rsvd = 0x7fff8000,
829
+ .pre_write = efuse_idr_prew,
830
+ },{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD,
831
+ .pre_write = efuse_cache_load_prew,
832
+ },{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK,
833
+ .pre_write = efuse_pgm_lock_prew,
834
+ },{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC,
835
+ .post_write = efuse_aes_crc_postw,
836
+ },{ .name = "EFUSE_AES_USR_KEY0_CRC", .addr = A_EFUSE_AES_USR_KEY0_CRC,
837
+ .post_write = efuse_aes_u0_crc_postw,
838
+ },{ .name = "EFUSE_AES_USR_KEY1_CRC", .addr = A_EFUSE_AES_USR_KEY1_CRC,
839
+ .post_write = efuse_aes_u1_crc_postw,
840
+ },{ .name = "EFUSE_PD", .addr = A_EFUSE_PD,
841
+ .ro = 0xfffffffe,
842
+ },{ .name = "EFUSE_ANLG_OSC_SW_1LP", .addr = A_EFUSE_ANLG_OSC_SW_1LP,
843
+ },{ .name = "EFUSE_TEST_CTRL", .addr = A_EFUSE_TEST_CTRL,
844
+ .reset = 0x8,
845
+ }
846
+};
847
+
848
+static void efuse_ctrl_reg_write(void *opaque, hwaddr addr,
849
+ uint64_t data, unsigned size)
850
+{
851
+ RegisterInfoArray *reg_array = opaque;
852
+ XlnxVersalEFuseCtrl *s;
853
+ Object *dev;
854
+
855
+ assert(reg_array != NULL);
856
+
857
+ dev = reg_array->mem.owner;
858
+ assert(dev);
859
+
860
+ s = XLNX_VERSAL_EFUSE_CTRL(dev);
861
+
862
+ if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {
863
+ qemu_log_mask(LOG_GUEST_ERROR,
864
+ "%s[reg_0x%02lx]: Attempt to write locked register.\n",
865
+ object_get_canonical_path(OBJECT(s)), (long)addr);
866
+ } else {
867
+ register_write_memory(opaque, addr, data, size);
868
+ }
869
+}
870
+
871
+static void efuse_ctrl_register_reset(RegisterInfo *reg)
872
+{
873
+ if (!reg->data || !reg->access) {
874
+ return;
875
+ }
876
+
877
+ /* Reset must not trigger some registers' writers */
878
+ switch (reg->access->addr) {
879
+ case A_EFUSE_AES_CRC:
880
+ case A_EFUSE_AES_USR_KEY0_CRC:
881
+ case A_EFUSE_AES_USR_KEY1_CRC:
882
+ *(uint32_t *)reg->data = reg->access->reset;
883
+ return;
884
+ }
885
+
886
+ register_reset(reg);
887
+}
888
+
889
+static void efuse_ctrl_reset(DeviceState *dev)
890
+{
891
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev);
892
+ unsigned int i;
893
+
894
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
895
+ efuse_ctrl_register_reset(&s->regs_info[i]);
896
+ }
897
+
898
+ efuse_anchor_bits_check(s);
899
+ efuse_data_sync(s);
900
+ efuse_imr_update_irq(s);
901
+}
902
+
903
+static const MemoryRegionOps efuse_ctrl_ops = {
904
+ .read = register_read_memory,
905
+ .write = efuse_ctrl_reg_write,
906
+ .endianness = DEVICE_LITTLE_ENDIAN,
907
+ .valid = {
908
+ .min_access_size = 4,
909
+ .max_access_size = 4,
910
+ },
911
+};
912
+
913
+static void efuse_ctrl_realize(DeviceState *dev, Error **errp)
914
+{
915
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev);
916
+ const uint32_t lks_sz = sizeof(XlnxEFuseLkSpec) / 2;
917
+
918
+ if (!s->efuse) {
919
+ error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE",
920
+ object_get_canonical_path(OBJECT(dev)));
921
+ return;
922
+ }
923
+
924
+ /* Sort property-defined pgm-locks for bsearch lookup */
925
+ if ((s->extra_pg0_lock_n16 % lks_sz) != 0) {
926
+ error_setg(errp,
927
+ "%s.pg0-lock: array property item-count not multiple of %u",
928
+ object_get_canonical_path(OBJECT(dev)), lks_sz);
929
+ return;
930
+ }
931
+
932
+ efuse_lk_spec_sort(s);
933
+}
934
+
935
+static void efuse_ctrl_init(Object *obj)
936
+{
937
+ XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj);
938
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
939
+ RegisterInfoArray *reg_array;
940
+
941
+ reg_array =
942
+ register_init_block32(DEVICE(obj), efuse_ctrl_regs_info,
943
+ ARRAY_SIZE(efuse_ctrl_regs_info),
944
+ s->regs_info, s->regs,
945
+ &efuse_ctrl_ops,
946
+ XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG,
947
+ R_MAX * 4);
948
+
949
+ sysbus_init_mmio(sbd, &reg_array->mem);
950
+ sysbus_init_irq(sbd, &s->irq_efuse_imr);
951
+}
952
+
953
+static const VMStateDescription vmstate_efuse_ctrl = {
954
+ .name = TYPE_XLNX_VERSAL_EFUSE_CTRL,
955
+ .version_id = 1,
956
+ .minimum_version_id = 1,
957
+ .fields = (VMStateField[]) {
958
+ VMSTATE_UINT32_ARRAY(regs, XlnxVersalEFuseCtrl, R_MAX),
959
+ VMSTATE_END_OF_LIST(),
960
+ }
961
+};
962
+
963
+static Property efuse_ctrl_props[] = {
964
+ DEFINE_PROP_LINK("efuse",
965
+ XlnxVersalEFuseCtrl, efuse,
966
+ TYPE_XLNX_EFUSE, XlnxEFuse *),
967
+ DEFINE_PROP_ARRAY("pg0-lock",
968
+ XlnxVersalEFuseCtrl, extra_pg0_lock_n16,
969
+ extra_pg0_lock_spec, qdev_prop_uint16, uint16_t),
970
+
971
+ DEFINE_PROP_END_OF_LIST(),
972
+};
973
+
974
+static void efuse_ctrl_class_init(ObjectClass *klass, void *data)
975
+{
976
+ DeviceClass *dc = DEVICE_CLASS(klass);
977
+
978
+ dc->reset = efuse_ctrl_reset;
979
+ dc->realize = efuse_ctrl_realize;
980
+ dc->vmsd = &vmstate_efuse_ctrl;
981
+ device_class_set_props(dc, efuse_ctrl_props);
982
+}
983
+
984
+static const TypeInfo efuse_ctrl_info = {
985
+ .name = TYPE_XLNX_VERSAL_EFUSE_CTRL,
986
+ .parent = TYPE_SYS_BUS_DEVICE,
987
+ .instance_size = sizeof(XlnxVersalEFuseCtrl),
988
+ .class_init = efuse_ctrl_class_init,
989
+ .instance_init = efuse_ctrl_init,
990
+};
991
+
992
+static void efuse_ctrl_register_types(void)
993
+{
994
+ type_register_static(&efuse_ctrl_info);
995
+}
996
+
997
+type_init(efuse_ctrl_register_types)
998
+
999
+/*
1000
+ * Retrieve a row, with unreadable bits returned as 0.
1001
+ */
1002
+uint32_t xlnx_versal_efuse_read_row(XlnxEFuse *efuse,
1003
+ uint32_t bit, bool *denied)
1004
+{
1005
+ bool dummy;
1006
+
1007
+ if (!denied) {
1008
+ denied = &dummy;
1009
+ }
1010
+
1011
+ if (bit >= EFUSE_RD_BLOCKED_START && bit <= EFUSE_RD_BLOCKED_END) {
1012
+ *denied = true;
1013
+ return 0;
1014
+ }
1015
+
1016
+ *denied = false;
1017
+ return xlnx_efuse_get_row(efuse, bit);
1018
+}
1019
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
1020
index XXXXXXX..XXXXXXX 100644
1021
--- a/hw/nvram/Kconfig
1022
+++ b/hw/nvram/Kconfig
1023
@@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE_CRC
1024
config XLNX_EFUSE
1025
bool
1026
select XLNX_EFUSE_CRC
1027
+
1028
+config XLNX_EFUSE_VERSAL
1029
+ bool
1030
+ select XLNX_EFUSE
1031
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
1032
index XXXXXXX..XXXXXXX 100644
1033
--- a/hw/nvram/meson.build
1034
+++ b/hw/nvram/meson.build
1035
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
1036
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
1037
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c'))
1038
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
1039
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
1040
+ 'xlnx-versal-efuse-cache.c',
1041
+ 'xlnx-versal-efuse-ctrl.c'))
1042
1043
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
1044
--
1045
2.20.1
1046
1047
diff view generated by jsdifflib
New patch
[PULL 05/22] hw/nvram: Introduce Xilinx ZynqMP eFuse device
1
From: Tong Ho <tong.ho@xilinx.com>
1
2
3
This implements the Xilinx ZynqMP eFuse, an one-time
4
field-programmable non-volatile storage device. There is
5
only one such device in the Xilinx ZynqMP product family.
6
7
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
9
10
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
12
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
13
Message-id: 20210917052400.1249094-4-tong.ho@xilinx.com
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
include/hw/nvram/xlnx-zynqmp-efuse.h | 44 ++
18
hw/nvram/xlnx-zynqmp-efuse.c | 855 +++++++++++++++++++++++++++
19
hw/nvram/Kconfig | 4 +
20
hw/nvram/meson.build | 2 +
21
4 files changed, 905 insertions(+)
22
create mode 100644 include/hw/nvram/xlnx-zynqmp-efuse.h
23
create mode 100644 hw/nvram/xlnx-zynqmp-efuse.c
24
25
diff --git a/include/hw/nvram/xlnx-zynqmp-efuse.h b/include/hw/nvram/xlnx-zynqmp-efuse.h
26
new file mode 100644
27
index XXXXXXX..XXXXXXX
28
--- /dev/null
29
+++ b/include/hw/nvram/xlnx-zynqmp-efuse.h
30
@@ -XXX,XX +XXX,XX @@
31
+/*
32
+ * Copyright (c) 2021 Xilinx Inc.
33
+ *
34
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
35
+ * of this software and associated documentation files (the "Software"), to deal
36
+ * in the Software without restriction, including without limitation the rights
37
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
38
+ * copies of the Software, and to permit persons to whom the Software is
39
+ * furnished to do so, subject to the following conditions:
40
+ *
41
+ * The above copyright notice and this permission notice shall be included in
42
+ * all copies or substantial portions of the Software.
43
+ *
44
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
45
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
46
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
47
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
48
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
49
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
50
+ * THE SOFTWARE.
51
+ */
52
+#ifndef XLNX_ZYNQMP_EFUSE_H
53
+#define XLNX_ZYNQMP_EFUSE_H
54
+
55
+#include "hw/irq.h"
56
+#include "hw/sysbus.h"
57
+#include "hw/register.h"
58
+#include "hw/nvram/xlnx-efuse.h"
59
+
60
+#define XLNX_ZYNQMP_EFUSE_R_MAX ((0x10fc / 4) + 1)
61
+
62
+#define TYPE_XLNX_ZYNQMP_EFUSE "xlnx,zynqmp-efuse"
63
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPEFuse, XLNX_ZYNQMP_EFUSE);
64
+
65
+struct XlnxZynqMPEFuse {
66
+ SysBusDevice parent_obj;
67
+ qemu_irq irq;
68
+
69
+ XlnxEFuse *efuse;
70
+ uint32_t regs[XLNX_ZYNQMP_EFUSE_R_MAX];
71
+ RegisterInfo regs_info[XLNX_ZYNQMP_EFUSE_R_MAX];
72
+};
73
+
74
+#endif
75
diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c
76
new file mode 100644
77
index XXXXXXX..XXXXXXX
78
--- /dev/null
79
+++ b/hw/nvram/xlnx-zynqmp-efuse.c
80
@@ -XXX,XX +XXX,XX @@
81
+/*
82
+ * QEMU model of the ZynqMP eFuse
83
+ *
84
+ * Copyright (c) 2015 Xilinx Inc.
85
+ *
86
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
87
+ *
88
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
89
+ * of this software and associated documentation files (the "Software"), to deal
90
+ * in the Software without restriction, including without limitation the rights
91
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
92
+ * copies of the Software, and to permit persons to whom the Software is
93
+ * furnished to do so, subject to the following conditions:
94
+ *
95
+ * The above copyright notice and this permission notice shall be included in
96
+ * all copies or substantial portions of the Software.
97
+ *
98
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
99
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
100
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
101
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
102
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
103
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
104
+ * THE SOFTWARE.
105
+ */
106
+
107
+#include "qemu/osdep.h"
108
+#include "hw/nvram/xlnx-zynqmp-efuse.h"
109
+
110
+#include "qemu/log.h"
111
+#include "qapi/error.h"
112
+#include "migration/vmstate.h"
113
+#include "hw/qdev-properties.h"
114
+
115
+#ifndef ZYNQMP_EFUSE_ERR_DEBUG
116
+#define ZYNQMP_EFUSE_ERR_DEBUG 0
117
+#endif
118
+
119
+REG32(WR_LOCK, 0x0)
120
+ FIELD(WR_LOCK, LOCK, 0, 16)
121
+REG32(CFG, 0x4)
122
+ FIELD(CFG, SLVERR_ENABLE, 5, 1)
123
+ FIELD(CFG, MARGIN_RD, 2, 2)
124
+ FIELD(CFG, PGM_EN, 1, 1)
125
+ FIELD(CFG, EFUSE_CLK_SEL, 0, 1)
126
+REG32(STATUS, 0x8)
127
+ FIELD(STATUS, AES_CRC_PASS, 7, 1)
128
+ FIELD(STATUS, AES_CRC_DONE, 6, 1)
129
+ FIELD(STATUS, CACHE_DONE, 5, 1)
130
+ FIELD(STATUS, CACHE_LOAD, 4, 1)
131
+ FIELD(STATUS, EFUSE_3_TBIT, 2, 1)
132
+ FIELD(STATUS, EFUSE_2_TBIT, 1, 1)
133
+ FIELD(STATUS, EFUSE_0_TBIT, 0, 1)
134
+REG32(EFUSE_PGM_ADDR, 0xc)
135
+ FIELD(EFUSE_PGM_ADDR, EFUSE, 11, 2)
136
+ FIELD(EFUSE_PGM_ADDR, ROW, 5, 6)
137
+ FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5)
138
+REG32(EFUSE_RD_ADDR, 0x10)
139
+ FIELD(EFUSE_RD_ADDR, EFUSE, 11, 2)
140
+ FIELD(EFUSE_RD_ADDR, ROW, 5, 6)
141
+REG32(EFUSE_RD_DATA, 0x14)
142
+REG32(TPGM, 0x18)
143
+ FIELD(TPGM, VALUE, 0, 16)
144
+REG32(TRD, 0x1c)
145
+ FIELD(TRD, VALUE, 0, 8)
146
+REG32(TSU_H_PS, 0x20)
147
+ FIELD(TSU_H_PS, VALUE, 0, 8)
148
+REG32(TSU_H_PS_CS, 0x24)
149
+ FIELD(TSU_H_PS_CS, VALUE, 0, 8)
150
+REG32(TSU_H_CS, 0x2c)
151
+ FIELD(TSU_H_CS, VALUE, 0, 4)
152
+REG32(EFUSE_ISR, 0x30)
153
+ FIELD(EFUSE_ISR, APB_SLVERR, 31, 1)
154
+ FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1)
155
+ FIELD(EFUSE_ISR, RD_ERROR, 3, 1)
156
+ FIELD(EFUSE_ISR, RD_DONE, 2, 1)
157
+ FIELD(EFUSE_ISR, PGM_ERROR, 1, 1)
158
+ FIELD(EFUSE_ISR, PGM_DONE, 0, 1)
159
+REG32(EFUSE_IMR, 0x34)
160
+ FIELD(EFUSE_IMR, APB_SLVERR, 31, 1)
161
+ FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1)
162
+ FIELD(EFUSE_IMR, RD_ERROR, 3, 1)
163
+ FIELD(EFUSE_IMR, RD_DONE, 2, 1)
164
+ FIELD(EFUSE_IMR, PGM_ERROR, 1, 1)
165
+ FIELD(EFUSE_IMR, PGM_DONE, 0, 1)
166
+REG32(EFUSE_IER, 0x38)
167
+ FIELD(EFUSE_IER, APB_SLVERR, 31, 1)
168
+ FIELD(EFUSE_IER, CACHE_ERROR, 4, 1)
169
+ FIELD(EFUSE_IER, RD_ERROR, 3, 1)
170
+ FIELD(EFUSE_IER, RD_DONE, 2, 1)
171
+ FIELD(EFUSE_IER, PGM_ERROR, 1, 1)
172
+ FIELD(EFUSE_IER, PGM_DONE, 0, 1)
173
+REG32(EFUSE_IDR, 0x3c)
174
+ FIELD(EFUSE_IDR, APB_SLVERR, 31, 1)
175
+ FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1)
176
+ FIELD(EFUSE_IDR, RD_ERROR, 3, 1)
177
+ FIELD(EFUSE_IDR, RD_DONE, 2, 1)
178
+ FIELD(EFUSE_IDR, PGM_ERROR, 1, 1)
179
+ FIELD(EFUSE_IDR, PGM_DONE, 0, 1)
180
+REG32(EFUSE_CACHE_LOAD, 0x40)
181
+ FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1)
182
+REG32(EFUSE_PGM_LOCK, 0x44)
183
+ FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1)
184
+REG32(EFUSE_AES_CRC, 0x48)
185
+REG32(EFUSE_TBITS_PRGRMG_EN, 0x100)
186
+ FIELD(EFUSE_TBITS_PRGRMG_EN, TBITS_PRGRMG_EN, 3, 1)
187
+REG32(DNA_0, 0x100c)
188
+REG32(DNA_1, 0x1010)
189
+REG32(DNA_2, 0x1014)
190
+REG32(IPDISABLE, 0x1018)
191
+ FIELD(IPDISABLE, VCU_DIS, 8, 1)
192
+ FIELD(IPDISABLE, GPU_DIS, 5, 1)
193
+ FIELD(IPDISABLE, APU3_DIS, 3, 1)
194
+ FIELD(IPDISABLE, APU2_DIS, 2, 1)
195
+ FIELD(IPDISABLE, APU1_DIS, 1, 1)
196
+ FIELD(IPDISABLE, APU0_DIS, 0, 1)
197
+REG32(SYSOSC_CTRL, 0x101c)
198
+ FIELD(SYSOSC_CTRL, SYSOSC_EN, 0, 1)
199
+REG32(USER_0, 0x1020)
200
+REG32(USER_1, 0x1024)
201
+REG32(USER_2, 0x1028)
202
+REG32(USER_3, 0x102c)
203
+REG32(USER_4, 0x1030)
204
+REG32(USER_5, 0x1034)
205
+REG32(USER_6, 0x1038)
206
+REG32(USER_7, 0x103c)
207
+REG32(MISC_USER_CTRL, 0x1040)
208
+ FIELD(MISC_USER_CTRL, FPD_SC_EN_0, 14, 1)
209
+ FIELD(MISC_USER_CTRL, LPD_SC_EN_0, 11, 1)
210
+ FIELD(MISC_USER_CTRL, LBIST_EN, 10, 1)
211
+ FIELD(MISC_USER_CTRL, USR_WRLK_7, 7, 1)
212
+ FIELD(MISC_USER_CTRL, USR_WRLK_6, 6, 1)
213
+ FIELD(MISC_USER_CTRL, USR_WRLK_5, 5, 1)
214
+ FIELD(MISC_USER_CTRL, USR_WRLK_4, 4, 1)
215
+ FIELD(MISC_USER_CTRL, USR_WRLK_3, 3, 1)
216
+ FIELD(MISC_USER_CTRL, USR_WRLK_2, 2, 1)
217
+ FIELD(MISC_USER_CTRL, USR_WRLK_1, 1, 1)
218
+ FIELD(MISC_USER_CTRL, USR_WRLK_0, 0, 1)
219
+REG32(ROM_RSVD, 0x1044)
220
+ FIELD(ROM_RSVD, PBR_BOOT_ERROR, 0, 3)
221
+REG32(PUF_CHASH, 0x1050)
222
+REG32(PUF_MISC, 0x1054)
223
+ FIELD(PUF_MISC, REGISTER_DIS, 31, 1)
224
+ FIELD(PUF_MISC, SYN_WRLK, 30, 1)
225
+ FIELD(PUF_MISC, SYN_INVLD, 29, 1)
226
+ FIELD(PUF_MISC, TEST2_DIS, 28, 1)
227
+ FIELD(PUF_MISC, UNUSED27, 27, 1)
228
+ FIELD(PUF_MISC, UNUSED26, 26, 1)
229
+ FIELD(PUF_MISC, UNUSED25, 25, 1)
230
+ FIELD(PUF_MISC, UNUSED24, 24, 1)
231
+ FIELD(PUF_MISC, AUX, 0, 24)
232
+REG32(SEC_CTRL, 0x1058)
233
+ FIELD(SEC_CTRL, PPK1_INVLD, 30, 2)
234
+ FIELD(SEC_CTRL, PPK1_WRLK, 29, 1)
235
+ FIELD(SEC_CTRL, PPK0_INVLD, 27, 2)
236
+ FIELD(SEC_CTRL, PPK0_WRLK, 26, 1)
237
+ FIELD(SEC_CTRL, RSA_EN, 11, 15)
238
+ FIELD(SEC_CTRL, SEC_LOCK, 10, 1)
239
+ FIELD(SEC_CTRL, PROG_GATE_2, 9, 1)
240
+ FIELD(SEC_CTRL, PROG_GATE_1, 8, 1)
241
+ FIELD(SEC_CTRL, PROG_GATE_0, 7, 1)
242
+ FIELD(SEC_CTRL, DFT_DIS, 6, 1)
243
+ FIELD(SEC_CTRL, JTAG_DIS, 5, 1)
244
+ FIELD(SEC_CTRL, ERROR_DIS, 4, 1)
245
+ FIELD(SEC_CTRL, BBRAM_DIS, 3, 1)
246
+ FIELD(SEC_CTRL, ENC_ONLY, 2, 1)
247
+ FIELD(SEC_CTRL, AES_WRLK, 1, 1)
248
+ FIELD(SEC_CTRL, AES_RDLK, 0, 1)
249
+REG32(SPK_ID, 0x105c)
250
+REG32(PPK0_0, 0x10a0)
251
+REG32(PPK0_1, 0x10a4)
252
+REG32(PPK0_2, 0x10a8)
253
+REG32(PPK0_3, 0x10ac)
254
+REG32(PPK0_4, 0x10b0)
255
+REG32(PPK0_5, 0x10b4)
256
+REG32(PPK0_6, 0x10b8)
257
+REG32(PPK0_7, 0x10bc)
258
+REG32(PPK0_8, 0x10c0)
259
+REG32(PPK0_9, 0x10c4)
260
+REG32(PPK0_10, 0x10c8)
261
+REG32(PPK0_11, 0x10cc)
262
+REG32(PPK1_0, 0x10d0)
263
+REG32(PPK1_1, 0x10d4)
264
+REG32(PPK1_2, 0x10d8)
265
+REG32(PPK1_3, 0x10dc)
266
+REG32(PPK1_4, 0x10e0)
267
+REG32(PPK1_5, 0x10e4)
268
+REG32(PPK1_6, 0x10e8)
269
+REG32(PPK1_7, 0x10ec)
270
+REG32(PPK1_8, 0x10f0)
271
+REG32(PPK1_9, 0x10f4)
272
+REG32(PPK1_10, 0x10f8)
273
+REG32(PPK1_11, 0x10fc)
274
+
275
+#define BIT_POS(ROW, COLUMN) (ROW * 32 + COLUMN)
276
+#define R_MAX (R_PPK1_11 + 1)
277
+
278
+/* #define EFUSE_XOSC 26 */
279
+
280
+/*
281
+ * eFUSE layout references:
282
+ * ZynqMP: UG1085 (v2.1) August 21, 2019, p.277, Table 12-13
283
+ */
284
+#define EFUSE_AES_RDLK BIT_POS(22, 0)
285
+#define EFUSE_AES_WRLK BIT_POS(22, 1)
286
+#define EFUSE_ENC_ONLY BIT_POS(22, 2)
287
+#define EFUSE_BBRAM_DIS BIT_POS(22, 3)
288
+#define EFUSE_ERROR_DIS BIT_POS(22, 4)
289
+#define EFUSE_JTAG_DIS BIT_POS(22, 5)
290
+#define EFUSE_DFT_DIS BIT_POS(22, 6)
291
+#define EFUSE_PROG_GATE_0 BIT_POS(22, 7)
292
+#define EFUSE_PROG_GATE_1 BIT_POS(22, 7)
293
+#define EFUSE_PROG_GATE_2 BIT_POS(22, 9)
294
+#define EFUSE_SEC_LOCK BIT_POS(22, 10)
295
+#define EFUSE_RSA_EN BIT_POS(22, 11)
296
+#define EFUSE_RSA_EN14 BIT_POS(22, 25)
297
+#define EFUSE_PPK0_WRLK BIT_POS(22, 26)
298
+#define EFUSE_PPK0_INVLD BIT_POS(22, 27)
299
+#define EFUSE_PPK0_INVLD_1 BIT_POS(22, 28)
300
+#define EFUSE_PPK1_WRLK BIT_POS(22, 29)
301
+#define EFUSE_PPK1_INVLD BIT_POS(22, 30)
302
+#define EFUSE_PPK1_INVLD_1 BIT_POS(22, 31)
303
+
304
+/* Areas. */
305
+#define EFUSE_TRIM_START BIT_POS(1, 0)
306
+#define EFUSE_TRIM_END BIT_POS(1, 30)
307
+#define EFUSE_DNA_START BIT_POS(3, 0)
308
+#define EFUSE_DNA_END BIT_POS(5, 31)
309
+#define EFUSE_AES_START BIT_POS(24, 0)
310
+#define EFUSE_AES_END BIT_POS(31, 31)
311
+#define EFUSE_ROM_START BIT_POS(17, 0)
312
+#define EFUSE_ROM_END BIT_POS(17, 31)
313
+#define EFUSE_IPDIS_START BIT_POS(6, 0)
314
+#define EFUSE_IPDIS_END BIT_POS(6, 31)
315
+#define EFUSE_USER_START BIT_POS(8, 0)
316
+#define EFUSE_USER_END BIT_POS(15, 31)
317
+#define EFUSE_BISR_START BIT_POS(32, 0)
318
+#define EFUSE_BISR_END BIT_POS(39, 31)
319
+
320
+#define EFUSE_USER_CTRL_START BIT_POS(16, 0)
321
+#define EFUSE_USER_CTRL_END BIT_POS(16, 16)
322
+#define EFUSE_USER_CTRL_MASK ((uint32_t)MAKE_64BIT_MASK(0, 17))
323
+
324
+#define EFUSE_PUF_CHASH_START BIT_POS(20, 0)
325
+#define EFUSE_PUF_CHASH_END BIT_POS(20, 31)
326
+#define EFUSE_PUF_MISC_START BIT_POS(21, 0)
327
+#define EFUSE_PUF_MISC_END BIT_POS(21, 31)
328
+#define EFUSE_PUF_SYN_WRLK BIT_POS(21, 30)
329
+
330
+#define EFUSE_SPK_START BIT_POS(23, 0)
331
+#define EFUSE_SPK_END BIT_POS(23, 31)
332
+
333
+#define EFUSE_PPK0_START BIT_POS(40, 0)
334
+#define EFUSE_PPK0_END BIT_POS(51, 31)
335
+#define EFUSE_PPK1_START BIT_POS(52, 0)
336
+#define EFUSE_PPK1_END BIT_POS(63, 31)
337
+
338
+#define EFUSE_CACHE_FLD(s, reg, field) \
339
+ ARRAY_FIELD_DP32((s)->regs, reg, field, \
340
+ (xlnx_efuse_get_row((s->efuse), EFUSE_ ## field) \
341
+ >> (EFUSE_ ## field % 32)))
342
+
343
+#define EFUSE_CACHE_BIT(s, reg, field) \
344
+ ARRAY_FIELD_DP32((s)->regs, reg, field, xlnx_efuse_get_bit((s->efuse), \
345
+ EFUSE_ ## field))
346
+
347
+#define FBIT_UNKNOWN (~0)
348
+
349
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxZynqMPEFuse *)0)->regs));
350
+
351
+static void update_tbit_status(XlnxZynqMPEFuse *s)
352
+{
353
+ unsigned int check = xlnx_efuse_tbits_check(s->efuse);
354
+ uint32_t val = s->regs[R_STATUS];
355
+
356
+ val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0)));
357
+ val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 1)));
358
+ val = FIELD_DP32(val, STATUS, EFUSE_3_TBIT, !!(check & (1 << 2)));
359
+
360
+ s->regs[R_STATUS] = val;
361
+}
362
+
363
+/* Update the u32 array from efuse bits. Slow but simple approach. */
364
+static void cache_sync_u32(XlnxZynqMPEFuse *s, unsigned int r_start,
365
+ unsigned int f_start, unsigned int f_end,
366
+ unsigned int f_written)
367
+{
368
+ uint32_t *u32 = &s->regs[r_start];
369
+ unsigned int fbit, wbits = 0, u32_off = 0;
370
+
371
+ /* Avoid working on bits that are not relevant. */
372
+ if (f_written != FBIT_UNKNOWN
373
+ && (f_written < f_start || f_written > f_end)) {
374
+ return;
375
+ }
376
+
377
+ for (fbit = f_start; fbit <= f_end; fbit++, wbits++) {
378
+ if (wbits == 32) {
379
+ /* Update the key offset. */
380
+ u32_off += 1;
381
+ wbits = 0;
382
+ }
383
+ u32[u32_off] |= xlnx_efuse_get_bit(s->efuse, fbit) << wbits;
384
+ }
385
+}
386
+
387
+/*
388
+ * Keep the syncs in bit order so we can bail out for the
389
+ * slower ones.
390
+ */
391
+static void zynqmp_efuse_sync_cache(XlnxZynqMPEFuse *s, unsigned int bit)
392
+{
393
+ EFUSE_CACHE_BIT(s, SEC_CTRL, AES_RDLK);
394
+ EFUSE_CACHE_BIT(s, SEC_CTRL, AES_WRLK);
395
+ EFUSE_CACHE_BIT(s, SEC_CTRL, ENC_ONLY);
396
+ EFUSE_CACHE_BIT(s, SEC_CTRL, BBRAM_DIS);
397
+ EFUSE_CACHE_BIT(s, SEC_CTRL, ERROR_DIS);
398
+ EFUSE_CACHE_BIT(s, SEC_CTRL, JTAG_DIS);
399
+ EFUSE_CACHE_BIT(s, SEC_CTRL, DFT_DIS);
400
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_0);
401
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_1);
402
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_2);
403
+ EFUSE_CACHE_BIT(s, SEC_CTRL, SEC_LOCK);
404
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PPK0_WRLK);
405
+ EFUSE_CACHE_BIT(s, SEC_CTRL, PPK1_WRLK);
406
+
407
+ EFUSE_CACHE_FLD(s, SEC_CTRL, RSA_EN);
408
+ EFUSE_CACHE_FLD(s, SEC_CTRL, PPK0_INVLD);
409
+ EFUSE_CACHE_FLD(s, SEC_CTRL, PPK1_INVLD);
410
+
411
+ /* Update the tbits. */
412
+ update_tbit_status(s);
413
+
414
+ /* Sync the various areas. */
415
+ s->regs[R_MISC_USER_CTRL] = xlnx_efuse_get_row(s->efuse,
416
+ EFUSE_USER_CTRL_START)
417
+ & EFUSE_USER_CTRL_MASK;
418
+ s->regs[R_PUF_CHASH] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_CHASH_START);
419
+ s->regs[R_PUF_MISC] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_MISC_START);
420
+
421
+ cache_sync_u32(s, R_DNA_0, EFUSE_DNA_START, EFUSE_DNA_END, bit);
422
+
423
+ if (bit < EFUSE_AES_START) {
424
+ return;
425
+ }
426
+
427
+ cache_sync_u32(s, R_ROM_RSVD, EFUSE_ROM_START, EFUSE_ROM_END, bit);
428
+ cache_sync_u32(s, R_IPDISABLE, EFUSE_IPDIS_START, EFUSE_IPDIS_END, bit);
429
+ cache_sync_u32(s, R_USER_0, EFUSE_USER_START, EFUSE_USER_END, bit);
430
+ cache_sync_u32(s, R_SPK_ID, EFUSE_SPK_START, EFUSE_SPK_END, bit);
431
+ cache_sync_u32(s, R_PPK0_0, EFUSE_PPK0_START, EFUSE_PPK0_END, bit);
432
+ cache_sync_u32(s, R_PPK1_0, EFUSE_PPK1_START, EFUSE_PPK1_END, bit);
433
+}
434
+
435
+static void zynqmp_efuse_update_irq(XlnxZynqMPEFuse *s)
436
+{
437
+ bool pending = s->regs[R_EFUSE_ISR] & s->regs[R_EFUSE_IMR];
438
+ qemu_set_irq(s->irq, pending);
439
+}
440
+
441
+static void zynqmp_efuse_isr_postw(RegisterInfo *reg, uint64_t val64)
442
+{
443
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
444
+ zynqmp_efuse_update_irq(s);
445
+}
446
+
447
+static uint64_t zynqmp_efuse_ier_prew(RegisterInfo *reg, uint64_t val64)
448
+{
449
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
450
+ uint32_t val = val64;
451
+
452
+ s->regs[R_EFUSE_IMR] |= val;
453
+ zynqmp_efuse_update_irq(s);
454
+ return 0;
455
+}
456
+
457
+static uint64_t zynqmp_efuse_idr_prew(RegisterInfo *reg, uint64_t val64)
458
+{
459
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
460
+ uint32_t val = val64;
461
+
462
+ s->regs[R_EFUSE_IMR] &= ~val;
463
+ zynqmp_efuse_update_irq(s);
464
+ return 0;
465
+}
466
+
467
+static void zynqmp_efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64)
468
+{
469
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
470
+ unsigned bit = val64;
471
+ unsigned page = FIELD_EX32(bit, EFUSE_PGM_ADDR, EFUSE);
472
+ bool puf_prot = false;
473
+ const char *errmsg = NULL;
474
+
475
+ /* Allow only valid array, and adjust for skipped array 1 */
476
+ switch (page) {
477
+ case 0:
478
+ break;
479
+ case 2 ... 3:
480
+ bit = FIELD_DP32(bit, EFUSE_PGM_ADDR, EFUSE, page - 1);
481
+ puf_prot = xlnx_efuse_get_bit(s->efuse, EFUSE_PUF_SYN_WRLK);
482
+ break;
483
+ default:
484
+ errmsg = "Invalid address";
485
+ goto pgm_done;
486
+ }
487
+
488
+ if (ARRAY_FIELD_EX32(s->regs, WR_LOCK, LOCK)) {
489
+ errmsg = "Array write-locked";
490
+ goto pgm_done;
491
+ }
492
+
493
+ if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) {
494
+ errmsg = "Array pgm-disabled";
495
+ goto pgm_done;
496
+ }
497
+
498
+ if (puf_prot) {
499
+ errmsg = "PUF_HD-store write-locked";
500
+ goto pgm_done;
501
+ }
502
+
503
+ if (ARRAY_FIELD_EX32(s->regs, SEC_CTRL, AES_WRLK)
504
+ && bit >= EFUSE_AES_START && bit <= EFUSE_AES_END) {
505
+ errmsg = "AES key-store Write-locked";
506
+ goto pgm_done;
507
+ }
508
+
509
+ if (!xlnx_efuse_set_bit(s->efuse, bit)) {
510
+ errmsg = "Write failed";
511
+ }
512
+
513
+ pgm_done:
514
+ if (!errmsg) {
515
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 0);
516
+ } else {
517
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1);
518
+ qemu_log_mask(LOG_GUEST_ERROR,
519
+ "%s - eFuse write error: %s; addr=0x%x\n",
520
+ object_get_canonical_path(OBJECT(s)),
521
+ errmsg, (unsigned)val64);
522
+ }
523
+
524
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1);
525
+ zynqmp_efuse_update_irq(s);
526
+}
527
+
528
+static void zynqmp_efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64)
529
+{
530
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
531
+
532
+ /*
533
+ * Grant reads only to allowed bits; reference sources:
534
+ * 1/ XilSKey - XilSKey_ZynqMp_EfusePs_ReadRow()
535
+ * 2/ UG1085, v2.0, table 12-13
536
+ * (note: enumerates the masks as <first, last> per described in
537
+ * references to avoid mental translation).
538
+ */
539
+#define COL_MASK(L_, H_) \
540
+ ((uint32_t)MAKE_64BIT_MASK((L_), (1 + (H_) - (L_))))
541
+
542
+ static const uint32_t ary0_col_mask[] = {
543
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_TBITS_ROW */
544
+ [0] = COL_MASK(28, 31),
545
+
546
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_USR{0:7}_FUSE_ROW */
547
+ [8] = COL_MASK(0, 31), [9] = COL_MASK(0, 31),
548
+ [10] = COL_MASK(0, 31), [11] = COL_MASK(0, 31),
549
+ [12] = COL_MASK(0, 31), [13] = COL_MASK(0, 31),
550
+ [14] = COL_MASK(0, 31), [15] = COL_MASK(0, 31),
551
+
552
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_MISC_USR_CTRL_ROW */
553
+ [16] = COL_MASK(0, 7) | COL_MASK(10, 16),
554
+
555
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_ROW */
556
+ [17] = COL_MASK(0, 2),
557
+
558
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_CHASH_ROW */
559
+ [20] = COL_MASK(0, 31),
560
+
561
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_AUX_ROW */
562
+ [21] = COL_MASK(0, 23) | COL_MASK(29, 31),
563
+
564
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW */
565
+ [22] = COL_MASK(0, 31),
566
+
567
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW */
568
+ [23] = COL_MASK(0, 31),
569
+
570
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW */
571
+ [40] = COL_MASK(0, 31), [41] = COL_MASK(0, 31),
572
+ [42] = COL_MASK(0, 31), [43] = COL_MASK(0, 31),
573
+ [44] = COL_MASK(0, 31), [45] = COL_MASK(0, 31),
574
+ [46] = COL_MASK(0, 31), [47] = COL_MASK(0, 31),
575
+ [48] = COL_MASK(0, 31), [49] = COL_MASK(0, 31),
576
+ [50] = COL_MASK(0, 31), [51] = COL_MASK(0, 31),
577
+
578
+ /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW */
579
+ [52] = COL_MASK(0, 31), [53] = COL_MASK(0, 31),
580
+ [54] = COL_MASK(0, 31), [55] = COL_MASK(0, 31),
581
+ [56] = COL_MASK(0, 31), [57] = COL_MASK(0, 31),
582
+ [58] = COL_MASK(0, 31), [59] = COL_MASK(0, 31),
583
+ [60] = COL_MASK(0, 31), [61] = COL_MASK(0, 31),
584
+ [62] = COL_MASK(0, 31), [63] = COL_MASK(0, 31),
585
+ };
586
+
587
+ uint32_t col_mask = COL_MASK(0, 31);
588
+#undef COL_MASK
589
+
590
+ uint32_t efuse_idx = s->regs[R_EFUSE_RD_ADDR];
591
+ uint32_t efuse_ary = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, EFUSE);
592
+ uint32_t efuse_row = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, ROW);
593
+
594
+ switch (efuse_ary) {
595
+ case 0: /* Various */
596
+ if (efuse_row >= ARRAY_SIZE(ary0_col_mask)) {
597
+ goto denied;
598
+ }
599
+
600
+ col_mask = ary0_col_mask[efuse_row];
601
+ if (!col_mask) {
602
+ goto denied;
603
+ }
604
+ break;
605
+ case 2: /* PUF helper data, adjust for skipped array 1 */
606
+ case 3:
607
+ val64 = FIELD_DP32(efuse_idx, EFUSE_RD_ADDR, EFUSE, efuse_ary - 1);
608
+ break;
609
+ default:
610
+ goto denied;
611
+ }
612
+
613
+ s->regs[R_EFUSE_RD_DATA] = xlnx_efuse_get_row(s->efuse, val64) & col_mask;
614
+
615
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 0);
616
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1);
617
+ zynqmp_efuse_update_irq(s);
618
+ return;
619
+
620
+ denied:
621
+ qemu_log_mask(LOG_GUEST_ERROR,
622
+ "%s: Denied efuse read from array %u, row %u\n",
623
+ object_get_canonical_path(OBJECT(s)),
624
+ efuse_ary, efuse_row);
625
+
626
+ s->regs[R_EFUSE_RD_DATA] = 0;
627
+
628
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1);
629
+ ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 0);
630
+ zynqmp_efuse_update_irq(s);
631
+}
632
+
633
+static void zynqmp_efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
634
+{
635
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
636
+ bool ok;
637
+
638
+ ok = xlnx_efuse_k256_check(s->efuse, (uint32_t)val64, EFUSE_AES_START);
639
+
640
+ ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_PASS, (ok ? 1 : 0));
641
+ ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_DONE, 1);
642
+
643
+ s->regs[R_EFUSE_AES_CRC] = 0; /* crc value is write-only */
644
+}
645
+
646
+static uint64_t zynqmp_efuse_cache_load_prew(RegisterInfo *reg,
647
+ uint64_t valu64)
648
+{
649
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque);
650
+
651
+ if (valu64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) {
652
+ zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN);
653
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
654
+ zynqmp_efuse_update_irq(s);
655
+ }
656
+
657
+ return 0;
658
+}
659
+
660
+static uint64_t zynqmp_efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val)
661
+{
662
+ return val == 0xDF0D ? 0 : 1;
663
+}
664
+
665
+static RegisterAccessInfo zynqmp_efuse_regs_info[] = {
666
+ { .name = "WR_LOCK", .addr = A_WR_LOCK,
667
+ .reset = 0x1,
668
+ .pre_write = zynqmp_efuse_wr_lock_prew,
669
+ },{ .name = "CFG", .addr = A_CFG,
670
+ },{ .name = "STATUS", .addr = A_STATUS,
671
+ .rsvd = 0x8,
672
+ .ro = 0xff,
673
+ },{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR,
674
+ .post_write = zynqmp_efuse_pgm_addr_postw
675
+ },{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR,
676
+ .rsvd = 0x1f,
677
+ .post_write = zynqmp_efuse_rd_addr_postw,
678
+ },{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA,
679
+ .ro = 0xffffffff,
680
+ },{ .name = "TPGM", .addr = A_TPGM,
681
+ },{ .name = "TRD", .addr = A_TRD,
682
+ .reset = 0x1b,
683
+ },{ .name = "TSU_H_PS", .addr = A_TSU_H_PS,
684
+ .reset = 0xff,
685
+ },{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS,
686
+ .reset = 0xb,
687
+ },{ .name = "TSU_H_CS", .addr = A_TSU_H_CS,
688
+ .reset = 0x7,
689
+ },{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR,
690
+ .rsvd = 0x7fffffe0,
691
+ .w1c = 0x8000001f,
692
+ .post_write = zynqmp_efuse_isr_postw,
693
+ },{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR,
694
+ .reset = 0x8000001f,
695
+ .rsvd = 0x7fffffe0,
696
+ .ro = 0xffffffff,
697
+ },{ .name = "EFUSE_IER", .addr = A_EFUSE_IER,
698
+ .rsvd = 0x7fffffe0,
699
+ .pre_write = zynqmp_efuse_ier_prew,
700
+ },{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR,
701
+ .rsvd = 0x7fffffe0,
702
+ .pre_write = zynqmp_efuse_idr_prew,
703
+ },{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD,
704
+ .pre_write = zynqmp_efuse_cache_load_prew,
705
+ },{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK,
706
+ },{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC,
707
+ .post_write = zynqmp_efuse_aes_crc_postw,
708
+ },{ .name = "EFUSE_TBITS_PRGRMG_EN", .addr = A_EFUSE_TBITS_PRGRMG_EN,
709
+ .reset = R_EFUSE_TBITS_PRGRMG_EN_TBITS_PRGRMG_EN_MASK,
710
+ },{ .name = "DNA_0", .addr = A_DNA_0,
711
+ .ro = 0xffffffff,
712
+ },{ .name = "DNA_1", .addr = A_DNA_1,
713
+ .ro = 0xffffffff,
714
+ },{ .name = "DNA_2", .addr = A_DNA_2,
715
+ .ro = 0xffffffff,
716
+ },{ .name = "IPDISABLE", .addr = A_IPDISABLE,
717
+ .ro = 0xffffffff,
718
+ },{ .name = "SYSOSC_CTRL", .addr = A_SYSOSC_CTRL,
719
+ .ro = 0xffffffff,
720
+ },{ .name = "USER_0", .addr = A_USER_0,
721
+ .ro = 0xffffffff,
722
+ },{ .name = "USER_1", .addr = A_USER_1,
723
+ .ro = 0xffffffff,
724
+ },{ .name = "USER_2", .addr = A_USER_2,
725
+ .ro = 0xffffffff,
726
+ },{ .name = "USER_3", .addr = A_USER_3,
727
+ .ro = 0xffffffff,
728
+ },{ .name = "USER_4", .addr = A_USER_4,
729
+ .ro = 0xffffffff,
730
+ },{ .name = "USER_5", .addr = A_USER_5,
731
+ .ro = 0xffffffff,
732
+ },{ .name = "USER_6", .addr = A_USER_6,
733
+ .ro = 0xffffffff,
734
+ },{ .name = "USER_7", .addr = A_USER_7,
735
+ .ro = 0xffffffff,
736
+ },{ .name = "MISC_USER_CTRL", .addr = A_MISC_USER_CTRL,
737
+ .ro = 0xffffffff,
738
+ },{ .name = "ROM_RSVD", .addr = A_ROM_RSVD,
739
+ .ro = 0xffffffff,
740
+ },{ .name = "PUF_CHASH", .addr = A_PUF_CHASH,
741
+ .ro = 0xffffffff,
742
+ },{ .name = "PUF_MISC", .addr = A_PUF_MISC,
743
+ .ro = 0xffffffff,
744
+ },{ .name = "SEC_CTRL", .addr = A_SEC_CTRL,
745
+ .ro = 0xffffffff,
746
+ },{ .name = "SPK_ID", .addr = A_SPK_ID,
747
+ .ro = 0xffffffff,
748
+ },{ .name = "PPK0_0", .addr = A_PPK0_0,
749
+ .ro = 0xffffffff,
750
+ },{ .name = "PPK0_1", .addr = A_PPK0_1,
751
+ .ro = 0xffffffff,
752
+ },{ .name = "PPK0_2", .addr = A_PPK0_2,
753
+ .ro = 0xffffffff,
754
+ },{ .name = "PPK0_3", .addr = A_PPK0_3,
755
+ .ro = 0xffffffff,
756
+ },{ .name = "PPK0_4", .addr = A_PPK0_4,
757
+ .ro = 0xffffffff,
758
+ },{ .name = "PPK0_5", .addr = A_PPK0_5,
759
+ .ro = 0xffffffff,
760
+ },{ .name = "PPK0_6", .addr = A_PPK0_6,
761
+ .ro = 0xffffffff,
762
+ },{ .name = "PPK0_7", .addr = A_PPK0_7,
763
+ .ro = 0xffffffff,
764
+ },{ .name = "PPK0_8", .addr = A_PPK0_8,
765
+ .ro = 0xffffffff,
766
+ },{ .name = "PPK0_9", .addr = A_PPK0_9,
767
+ .ro = 0xffffffff,
768
+ },{ .name = "PPK0_10", .addr = A_PPK0_10,
769
+ .ro = 0xffffffff,
770
+ },{ .name = "PPK0_11", .addr = A_PPK0_11,
771
+ .ro = 0xffffffff,
772
+ },{ .name = "PPK1_0", .addr = A_PPK1_0,
773
+ .ro = 0xffffffff,
774
+ },{ .name = "PPK1_1", .addr = A_PPK1_1,
775
+ .ro = 0xffffffff,
776
+ },{ .name = "PPK1_2", .addr = A_PPK1_2,
777
+ .ro = 0xffffffff,
778
+ },{ .name = "PPK1_3", .addr = A_PPK1_3,
779
+ .ro = 0xffffffff,
780
+ },{ .name = "PPK1_4", .addr = A_PPK1_4,
781
+ .ro = 0xffffffff,
782
+ },{ .name = "PPK1_5", .addr = A_PPK1_5,
783
+ .ro = 0xffffffff,
784
+ },{ .name = "PPK1_6", .addr = A_PPK1_6,
785
+ .ro = 0xffffffff,
786
+ },{ .name = "PPK1_7", .addr = A_PPK1_7,
787
+ .ro = 0xffffffff,
788
+ },{ .name = "PPK1_8", .addr = A_PPK1_8,
789
+ .ro = 0xffffffff,
790
+ },{ .name = "PPK1_9", .addr = A_PPK1_9,
791
+ .ro = 0xffffffff,
792
+ },{ .name = "PPK1_10", .addr = A_PPK1_10,
793
+ .ro = 0xffffffff,
794
+ },{ .name = "PPK1_11", .addr = A_PPK1_11,
795
+ .ro = 0xffffffff,
796
+ }
797
+};
798
+
799
+static void zynqmp_efuse_reg_write(void *opaque, hwaddr addr,
800
+ uint64_t data, unsigned size)
801
+{
802
+ RegisterInfoArray *reg_array = opaque;
803
+ XlnxZynqMPEFuse *s;
804
+ Object *dev;
805
+
806
+ assert(reg_array != NULL);
807
+
808
+ dev = reg_array->mem.owner;
809
+ assert(dev);
810
+
811
+ s = XLNX_ZYNQMP_EFUSE(dev);
812
+
813
+ if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) {
814
+ qemu_log_mask(LOG_GUEST_ERROR,
815
+ "%s[reg_0x%02lx]: Attempt to write locked register.\n",
816
+ object_get_canonical_path(OBJECT(s)), (long)addr);
817
+ } else {
818
+ register_write_memory(opaque, addr, data, size);
819
+ }
820
+}
821
+
822
+static const MemoryRegionOps zynqmp_efuse_ops = {
823
+ .read = register_read_memory,
824
+ .write = zynqmp_efuse_reg_write,
825
+ .endianness = DEVICE_LITTLE_ENDIAN,
826
+ .valid = {
827
+ .min_access_size = 4,
828
+ .max_access_size = 4,
829
+ },
830
+};
831
+
832
+static void zynqmp_efuse_register_reset(RegisterInfo *reg)
833
+{
834
+ if (!reg->data || !reg->access) {
835
+ return;
836
+ }
837
+
838
+ /* Reset must not trigger some registers' writers */
839
+ switch (reg->access->addr) {
840
+ case A_EFUSE_AES_CRC:
841
+ *(uint32_t *)reg->data = reg->access->reset;
842
+ return;
843
+ }
844
+
845
+ register_reset(reg);
846
+}
847
+
848
+static void zynqmp_efuse_reset(DeviceState *dev)
849
+{
850
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
851
+ unsigned int i;
852
+
853
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
854
+ zynqmp_efuse_register_reset(&s->regs_info[i]);
855
+ }
856
+
857
+ zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN);
858
+ ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1);
859
+ zynqmp_efuse_update_irq(s);
860
+}
861
+
862
+static void zynqmp_efuse_realize(DeviceState *dev, Error **errp)
863
+{
864
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev);
865
+
866
+ if (!s->efuse) {
867
+ error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE",
868
+ object_get_canonical_path(OBJECT(dev)));
869
+ return;
870
+ }
871
+
872
+ s->efuse->dev = dev;
873
+}
874
+
875
+static void zynqmp_efuse_init(Object *obj)
876
+{
877
+ XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj);
878
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
879
+ RegisterInfoArray *reg_array;
880
+
881
+ reg_array =
882
+ register_init_block32(DEVICE(obj), zynqmp_efuse_regs_info,
883
+ ARRAY_SIZE(zynqmp_efuse_regs_info),
884
+ s->regs_info, s->regs,
885
+ &zynqmp_efuse_ops,
886
+ ZYNQMP_EFUSE_ERR_DEBUG,
887
+ R_MAX * 4);
888
+
889
+ sysbus_init_mmio(sbd, &reg_array->mem);
890
+ sysbus_init_irq(sbd, &s->irq);
891
+}
892
+
893
+static const VMStateDescription vmstate_efuse = {
894
+ .name = TYPE_XLNX_ZYNQMP_EFUSE,
895
+ .version_id = 1,
896
+ .minimum_version_id = 1,
897
+ .fields = (VMStateField[]) {
898
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPEFuse, R_MAX),
899
+ VMSTATE_END_OF_LIST(),
900
+ }
901
+};
902
+
903
+static Property zynqmp_efuse_props[] = {
904
+ DEFINE_PROP_LINK("efuse",
905
+ XlnxZynqMPEFuse, efuse,
906
+ TYPE_XLNX_EFUSE, XlnxEFuse *),
907
+
908
+ DEFINE_PROP_END_OF_LIST(),
909
+};
910
+
911
+static void zynqmp_efuse_class_init(ObjectClass *klass, void *data)
912
+{
913
+ DeviceClass *dc = DEVICE_CLASS(klass);
914
+
915
+ dc->reset = zynqmp_efuse_reset;
916
+ dc->realize = zynqmp_efuse_realize;
917
+ dc->vmsd = &vmstate_efuse;
918
+ device_class_set_props(dc, zynqmp_efuse_props);
919
+}
920
+
921
+
922
+static const TypeInfo efuse_info = {
923
+ .name = TYPE_XLNX_ZYNQMP_EFUSE,
924
+ .parent = TYPE_SYS_BUS_DEVICE,
925
+ .instance_size = sizeof(XlnxZynqMPEFuse),
926
+ .class_init = zynqmp_efuse_class_init,
927
+ .instance_init = zynqmp_efuse_init,
928
+};
929
+
930
+static void efuse_register_types(void)
931
+{
932
+ type_register_static(&efuse_info);
933
+}
934
+
935
+type_init(efuse_register_types)
936
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
937
index XXXXXXX..XXXXXXX 100644
938
--- a/hw/nvram/Kconfig
939
+++ b/hw/nvram/Kconfig
940
@@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE
941
config XLNX_EFUSE_VERSAL
942
bool
943
select XLNX_EFUSE
944
+
945
+config XLNX_EFUSE_ZYNQMP
946
+ bool
947
+ select XLNX_EFUSE
948
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
949
index XXXXXXX..XXXXXXX 100644
950
--- a/hw/nvram/meson.build
951
+++ b/hw/nvram/meson.build
952
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c'))
953
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
954
'xlnx-versal-efuse-cache.c',
955
'xlnx-versal-efuse-ctrl.c'))
956
+softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files(
957
+ 'xlnx-zynqmp-efuse.c'))
958
959
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
960
--
961
2.20.1
962
963
diff view generated by jsdifflib
New patch
[PULL 06/22] hw/nvram: Introduce Xilinx battery-backed ram
1
From: Tong Ho <tong.ho@xilinx.com>
1
2
3
This device is present in Versal and ZynqMP product
4
families to store a 256-bit encryption key.
5
6
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
8
9
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
10
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
11
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
12
Message-id: 20210917052400.1249094-5-tong.ho@xilinx.com
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/nvram/xlnx-bbram.h | 54 ++++
17
hw/nvram/xlnx-bbram.c | 545 ++++++++++++++++++++++++++++++++++
18
hw/nvram/Kconfig | 4 +
19
hw/nvram/meson.build | 1 +
20
4 files changed, 604 insertions(+)
21
create mode 100644 include/hw/nvram/xlnx-bbram.h
22
create mode 100644 hw/nvram/xlnx-bbram.c
23
24
diff --git a/include/hw/nvram/xlnx-bbram.h b/include/hw/nvram/xlnx-bbram.h
25
new file mode 100644
26
index XXXXXXX..XXXXXXX
27
--- /dev/null
28
+++ b/include/hw/nvram/xlnx-bbram.h
29
@@ -XXX,XX +XXX,XX @@
30
+/*
31
+ * QEMU model of the Xilinx BBRAM Battery Backed RAM
32
+ *
33
+ * Copyright (c) 2015-2021 Xilinx Inc.
34
+ *
35
+ * Written by Edgar E. Iglesias <edgari@xilinx.com>
36
+ *
37
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
38
+ * of this software and associated documentation files (the "Software"), to deal
39
+ * in the Software without restriction, including without limitation the rights
40
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
41
+ * copies of the Software, and to permit persons to whom the Software is
42
+ * furnished to do so, subject to the following conditions:
43
+ *
44
+ * The above copyright notice and this permission notice shall be included in
45
+ * all copies or substantial portions of the Software.
46
+ *
47
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
48
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
49
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
50
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
51
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
52
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
53
+ * THE SOFTWARE.
54
+ */
55
+#ifndef XLNX_BBRAM_H
56
+#define XLNX_BBRAM_H
57
+
58
+#include "sysemu/block-backend.h"
59
+#include "hw/qdev-core.h"
60
+#include "hw/irq.h"
61
+#include "hw/sysbus.h"
62
+#include "hw/register.h"
63
+
64
+#define RMAX_XLNX_BBRAM ((0x4c / 4) + 1)
65
+
66
+#define TYPE_XLNX_BBRAM "xlnx,bbram-ctrl"
67
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxBBRam, XLNX_BBRAM);
68
+
69
+struct XlnxBBRam {
70
+ SysBusDevice parent_obj;
71
+ qemu_irq irq_bbram;
72
+
73
+ BlockBackend *blk;
74
+
75
+ uint32_t crc_zpads;
76
+ bool bbram8_wo;
77
+ bool blk_ro;
78
+
79
+ uint32_t regs[RMAX_XLNX_BBRAM];
80
+ RegisterInfo regs_info[RMAX_XLNX_BBRAM];
81
+};
82
+
83
+#endif
84
diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c
85
new file mode 100644
86
index XXXXXXX..XXXXXXX
87
--- /dev/null
88
+++ b/hw/nvram/xlnx-bbram.c
89
@@ -XXX,XX +XXX,XX @@
90
+/*
91
+ * QEMU model of the Xilinx BBRAM Battery Backed RAM
92
+ *
93
+ * Copyright (c) 2014-2021 Xilinx Inc.
94
+ *
95
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
96
+ * of this software and associated documentation files (the "Software"), to deal
97
+ * in the Software without restriction, including without limitation the rights
98
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
99
+ * copies of the Software, and to permit persons to whom the Software is
100
+ * furnished to do so, subject to the following conditions:
101
+ *
102
+ * The above copyright notice and this permission notice shall be included in
103
+ * all copies or substantial portions of the Software.
104
+ *
105
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
106
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
107
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
108
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
109
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
110
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
111
+ * THE SOFTWARE.
112
+ */
113
+
114
+#include "qemu/osdep.h"
115
+#include "hw/nvram/xlnx-bbram.h"
116
+
117
+#include "qemu/error-report.h"
118
+#include "qemu/log.h"
119
+#include "qapi/error.h"
120
+#include "sysemu/blockdev.h"
121
+#include "migration/vmstate.h"
122
+#include "hw/qdev-properties.h"
123
+#include "hw/qdev-properties-system.h"
124
+#include "hw/nvram/xlnx-efuse.h"
125
+
126
+#ifndef XLNX_BBRAM_ERR_DEBUG
127
+#define XLNX_BBRAM_ERR_DEBUG 0
128
+#endif
129
+
130
+REG32(BBRAM_STATUS, 0x0)
131
+ FIELD(BBRAM_STATUS, AES_CRC_PASS, 9, 1)
132
+ FIELD(BBRAM_STATUS, AES_CRC_DONE, 8, 1)
133
+ FIELD(BBRAM_STATUS, BBRAM_ZEROIZED, 4, 1)
134
+ FIELD(BBRAM_STATUS, PGM_MODE, 0, 1)
135
+REG32(BBRAM_CTRL, 0x4)
136
+ FIELD(BBRAM_CTRL, ZEROIZE, 0, 1)
137
+REG32(PGM_MODE, 0x8)
138
+REG32(BBRAM_AES_CRC, 0xc)
139
+REG32(BBRAM_0, 0x10)
140
+REG32(BBRAM_1, 0x14)
141
+REG32(BBRAM_2, 0x18)
142
+REG32(BBRAM_3, 0x1c)
143
+REG32(BBRAM_4, 0x20)
144
+REG32(BBRAM_5, 0x24)
145
+REG32(BBRAM_6, 0x28)
146
+REG32(BBRAM_7, 0x2c)
147
+REG32(BBRAM_8, 0x30)
148
+REG32(BBRAM_SLVERR, 0x34)
149
+ FIELD(BBRAM_SLVERR, ENABLE, 0, 1)
150
+REG32(BBRAM_ISR, 0x38)
151
+ FIELD(BBRAM_ISR, APB_SLVERR, 0, 1)
152
+REG32(BBRAM_IMR, 0x3c)
153
+ FIELD(BBRAM_IMR, APB_SLVERR, 0, 1)
154
+REG32(BBRAM_IER, 0x40)
155
+ FIELD(BBRAM_IER, APB_SLVERR, 0, 1)
156
+REG32(BBRAM_IDR, 0x44)
157
+ FIELD(BBRAM_IDR, APB_SLVERR, 0, 1)
158
+REG32(BBRAM_MSW_LOCK, 0x4c)
159
+ FIELD(BBRAM_MSW_LOCK, VAL, 0, 1)
160
+
161
+#define R_MAX (R_BBRAM_MSW_LOCK + 1)
162
+
163
+#define RAM_MAX (A_BBRAM_8 + 4 - A_BBRAM_0)
164
+
165
+#define BBRAM_PGM_MAGIC 0x757bdf0d
166
+
167
+QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxBBRam *)0)->regs));
168
+
169
+static bool bbram_msw_locked(XlnxBBRam *s)
170
+{
171
+ return ARRAY_FIELD_EX32(s->regs, BBRAM_MSW_LOCK, VAL) != 0;
172
+}
173
+
174
+static bool bbram_pgm_enabled(XlnxBBRam *s)
175
+{
176
+ return ARRAY_FIELD_EX32(s->regs, BBRAM_STATUS, PGM_MODE) != 0;
177
+}
178
+
179
+static void bbram_bdrv_error(XlnxBBRam *s, int rc, gchar *detail)
180
+{
181
+ Error *errp;
182
+
183
+ error_setg_errno(&errp, -rc, "%s: BBRAM backstore %s failed.",
184
+ blk_name(s->blk), detail);
185
+ error_report("%s", error_get_pretty(errp));
186
+ error_free(errp);
187
+
188
+ g_free(detail);
189
+}
190
+
191
+static void bbram_bdrv_read(XlnxBBRam *s, Error **errp)
192
+{
193
+ uint32_t *ram = &s->regs[R_BBRAM_0];
194
+ int nr = RAM_MAX;
195
+
196
+ if (!s->blk) {
197
+ return;
198
+ }
199
+
200
+ s->blk_ro = !blk_supports_write_perm(s->blk);
201
+ if (!s->blk_ro) {
202
+ int rc;
203
+
204
+ rc = blk_set_perm(s->blk,
205
+ (BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE),
206
+ BLK_PERM_ALL, NULL);
207
+ if (rc) {
208
+ s->blk_ro = true;
209
+ }
210
+ }
211
+ if (s->blk_ro) {
212
+ warn_report("%s: Skip saving updates to read-only BBRAM backstore.",
213
+ blk_name(s->blk));
214
+ }
215
+
216
+ if (blk_pread(s->blk, 0, ram, nr) < 0) {
217
+ error_setg(errp,
218
+ "%s: Failed to read %u bytes from BBRAM backstore.",
219
+ blk_name(s->blk), nr);
220
+ return;
221
+ }
222
+
223
+ /* Convert from little-endian backstore for each 32-bit word */
224
+ nr /= 4;
225
+ while (nr--) {
226
+ ram[nr] = le32_to_cpu(ram[nr]);
227
+ }
228
+}
229
+
230
+static void bbram_bdrv_sync(XlnxBBRam *s, uint64_t hwaddr)
231
+{
232
+ uint32_t le32;
233
+ unsigned offset;
234
+ int rc;
235
+
236
+ assert(A_BBRAM_0 <= hwaddr && hwaddr <= A_BBRAM_8);
237
+
238
+ /* Backstore is always in little-endian */
239
+ le32 = cpu_to_le32(s->regs[hwaddr / 4]);
240
+
241
+ /* Update zeroized flag */
242
+ if (le32 && (hwaddr != A_BBRAM_8 || s->bbram8_wo)) {
243
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 0);
244
+ }
245
+
246
+ if (!s->blk || s->blk_ro) {
247
+ return;
248
+ }
249
+
250
+ offset = hwaddr - A_BBRAM_0;
251
+ rc = blk_pwrite(s->blk, offset, &le32, 4, 0);
252
+ if (rc < 0) {
253
+ bbram_bdrv_error(s, rc, g_strdup_printf("write to offset %u", offset));
254
+ }
255
+}
256
+
257
+static void bbram_bdrv_zero(XlnxBBRam *s)
258
+{
259
+ int rc;
260
+
261
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 1);
262
+
263
+ if (!s->blk || s->blk_ro) {
264
+ return;
265
+ }
266
+
267
+ rc = blk_make_zero(s->blk, 0);
268
+ if (rc < 0) {
269
+ bbram_bdrv_error(s, rc, g_strdup("zeroizing"));
270
+ }
271
+
272
+ /* Restore bbram8 if it is non-zero */
273
+ if (s->regs[R_BBRAM_8]) {
274
+ bbram_bdrv_sync(s, A_BBRAM_8);
275
+ }
276
+}
277
+
278
+static void bbram_zeroize(XlnxBBRam *s)
279
+{
280
+ int nr = RAM_MAX - (s->bbram8_wo ? 0 : 4); /* only wo bbram8 is cleared */
281
+
282
+ memset(&s->regs[R_BBRAM_0], 0, nr);
283
+ bbram_bdrv_zero(s);
284
+}
285
+
286
+static void bbram_update_irq(XlnxBBRam *s)
287
+{
288
+ bool pending = s->regs[R_BBRAM_ISR] & ~s->regs[R_BBRAM_IMR];
289
+
290
+ qemu_set_irq(s->irq_bbram, pending);
291
+}
292
+
293
+static void bbram_ctrl_postw(RegisterInfo *reg, uint64_t val64)
294
+{
295
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
296
+ uint32_t val = val64;
297
+
298
+ if (val & R_BBRAM_CTRL_ZEROIZE_MASK) {
299
+ bbram_zeroize(s);
300
+ /* The bit is self clearing */
301
+ s->regs[R_BBRAM_CTRL] &= ~R_BBRAM_CTRL_ZEROIZE_MASK;
302
+ }
303
+}
304
+
305
+static void bbram_pgm_mode_postw(RegisterInfo *reg, uint64_t val64)
306
+{
307
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
308
+ uint32_t val = val64;
309
+
310
+ if (val == BBRAM_PGM_MAGIC) {
311
+ bbram_zeroize(s);
312
+
313
+ /* The status bit is cleared only by POR */
314
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, PGM_MODE, 1);
315
+ }
316
+}
317
+
318
+static void bbram_aes_crc_postw(RegisterInfo *reg, uint64_t val64)
319
+{
320
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
321
+ uint32_t calc_crc;
322
+
323
+ if (!bbram_pgm_enabled(s)) {
324
+ /* We are not in programming mode, don't do anything */
325
+ return;
326
+ }
327
+
328
+ /* Perform the AES integrity check */
329
+ s->regs[R_BBRAM_STATUS] |= R_BBRAM_STATUS_AES_CRC_DONE_MASK;
330
+
331
+ /*
332
+ * Set check status.
333
+ *
334
+ * ZynqMP BBRAM check has a zero-u32 prepended; see:
335
+ * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_bbramps_zynqmp.c#L311
336
+ */
337
+ calc_crc = xlnx_efuse_calc_crc(&s->regs[R_BBRAM_0],
338
+ (R_BBRAM_8 - R_BBRAM_0), s->crc_zpads);
339
+
340
+ ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, AES_CRC_PASS,
341
+ (s->regs[R_BBRAM_AES_CRC] == calc_crc));
342
+}
343
+
344
+static uint64_t bbram_key_prew(RegisterInfo *reg, uint64_t val64)
345
+{
346
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
347
+ uint32_t original_data = *(uint32_t *) reg->data;
348
+
349
+ if (bbram_pgm_enabled(s)) {
350
+ return val64;
351
+ } else {
352
+ /* We are not in programming mode, don't do anything */
353
+ qemu_log_mask(LOG_GUEST_ERROR,
354
+ "Not in programming mode, dropping the write\n");
355
+ return original_data;
356
+ }
357
+}
358
+
359
+static void bbram_key_postw(RegisterInfo *reg, uint64_t val64)
360
+{
361
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
362
+
363
+ bbram_bdrv_sync(s, reg->access->addr);
364
+}
365
+
366
+static uint64_t bbram_wo_postr(RegisterInfo *reg, uint64_t val)
367
+{
368
+ return 0;
369
+}
370
+
371
+static uint64_t bbram_r8_postr(RegisterInfo *reg, uint64_t val)
372
+{
373
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
374
+
375
+ return s->bbram8_wo ? bbram_wo_postr(reg, val) : val;
376
+}
377
+
378
+static bool bbram_r8_readonly(XlnxBBRam *s)
379
+{
380
+ return !bbram_pgm_enabled(s) || bbram_msw_locked(s);
381
+}
382
+
383
+static uint64_t bbram_r8_prew(RegisterInfo *reg, uint64_t val64)
384
+{
385
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
386
+
387
+ if (bbram_r8_readonly(s)) {
388
+ val64 = *(uint32_t *)reg->data;
389
+ }
390
+
391
+ return val64;
392
+}
393
+
394
+static void bbram_r8_postw(RegisterInfo *reg, uint64_t val64)
395
+{
396
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
397
+
398
+ if (!bbram_r8_readonly(s)) {
399
+ bbram_bdrv_sync(s, A_BBRAM_8);
400
+ }
401
+}
402
+
403
+static uint64_t bbram_msw_lock_prew(RegisterInfo *reg, uint64_t val64)
404
+{
405
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
406
+
407
+ /* Never lock if bbram8 is wo; and, only POR can clear the lock */
408
+ if (s->bbram8_wo) {
409
+ val64 = 0;
410
+ } else {
411
+ val64 |= s->regs[R_BBRAM_MSW_LOCK];
412
+ }
413
+
414
+ return val64;
415
+}
416
+
417
+static void bbram_isr_postw(RegisterInfo *reg, uint64_t val64)
418
+{
419
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
420
+
421
+ bbram_update_irq(s);
422
+}
423
+
424
+static uint64_t bbram_ier_prew(RegisterInfo *reg, uint64_t val64)
425
+{
426
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
427
+ uint32_t val = val64;
428
+
429
+ s->regs[R_BBRAM_IMR] &= ~val;
430
+ bbram_update_irq(s);
431
+ return 0;
432
+}
433
+
434
+static uint64_t bbram_idr_prew(RegisterInfo *reg, uint64_t val64)
435
+{
436
+ XlnxBBRam *s = XLNX_BBRAM(reg->opaque);
437
+ uint32_t val = val64;
438
+
439
+ s->regs[R_BBRAM_IMR] |= val;
440
+ bbram_update_irq(s);
441
+ return 0;
442
+}
443
+
444
+static RegisterAccessInfo bbram_ctrl_regs_info[] = {
445
+ { .name = "BBRAM_STATUS", .addr = A_BBRAM_STATUS,
446
+ .rsvd = 0xee,
447
+ .ro = 0x3ff,
448
+ },{ .name = "BBRAM_CTRL", .addr = A_BBRAM_CTRL,
449
+ .post_write = bbram_ctrl_postw,
450
+ },{ .name = "PGM_MODE", .addr = A_PGM_MODE,
451
+ .post_write = bbram_pgm_mode_postw,
452
+ },{ .name = "BBRAM_AES_CRC", .addr = A_BBRAM_AES_CRC,
453
+ .post_write = bbram_aes_crc_postw,
454
+ .post_read = bbram_wo_postr,
455
+ },{ .name = "BBRAM_0", .addr = A_BBRAM_0,
456
+ .pre_write = bbram_key_prew,
457
+ .post_write = bbram_key_postw,
458
+ .post_read = bbram_wo_postr,
459
+ },{ .name = "BBRAM_1", .addr = A_BBRAM_1,
460
+ .pre_write = bbram_key_prew,
461
+ .post_write = bbram_key_postw,
462
+ .post_read = bbram_wo_postr,
463
+ },{ .name = "BBRAM_2", .addr = A_BBRAM_2,
464
+ .pre_write = bbram_key_prew,
465
+ .post_write = bbram_key_postw,
466
+ .post_read = bbram_wo_postr,
467
+ },{ .name = "BBRAM_3", .addr = A_BBRAM_3,
468
+ .pre_write = bbram_key_prew,
469
+ .post_write = bbram_key_postw,
470
+ .post_read = bbram_wo_postr,
471
+ },{ .name = "BBRAM_4", .addr = A_BBRAM_4,
472
+ .pre_write = bbram_key_prew,
473
+ .post_write = bbram_key_postw,
474
+ .post_read = bbram_wo_postr,
475
+ },{ .name = "BBRAM_5", .addr = A_BBRAM_5,
476
+ .pre_write = bbram_key_prew,
477
+ .post_write = bbram_key_postw,
478
+ .post_read = bbram_wo_postr,
479
+ },{ .name = "BBRAM_6", .addr = A_BBRAM_6,
480
+ .pre_write = bbram_key_prew,
481
+ .post_write = bbram_key_postw,
482
+ .post_read = bbram_wo_postr,
483
+ },{ .name = "BBRAM_7", .addr = A_BBRAM_7,
484
+ .pre_write = bbram_key_prew,
485
+ .post_write = bbram_key_postw,
486
+ .post_read = bbram_wo_postr,
487
+ },{ .name = "BBRAM_8", .addr = A_BBRAM_8,
488
+ .pre_write = bbram_r8_prew,
489
+ .post_write = bbram_r8_postw,
490
+ .post_read = bbram_r8_postr,
491
+ },{ .name = "BBRAM_SLVERR", .addr = A_BBRAM_SLVERR,
492
+ .rsvd = ~1,
493
+ },{ .name = "BBRAM_ISR", .addr = A_BBRAM_ISR,
494
+ .w1c = 0x1,
495
+ .post_write = bbram_isr_postw,
496
+ },{ .name = "BBRAM_IMR", .addr = A_BBRAM_IMR,
497
+ .ro = 0x1,
498
+ },{ .name = "BBRAM_IER", .addr = A_BBRAM_IER,
499
+ .pre_write = bbram_ier_prew,
500
+ },{ .name = "BBRAM_IDR", .addr = A_BBRAM_IDR,
501
+ .pre_write = bbram_idr_prew,
502
+ },{ .name = "BBRAM_MSW_LOCK", .addr = A_BBRAM_MSW_LOCK,
503
+ .pre_write = bbram_msw_lock_prew,
504
+ .ro = ~R_BBRAM_MSW_LOCK_VAL_MASK,
505
+ }
506
+};
507
+
508
+static void bbram_ctrl_reset(DeviceState *dev)
509
+{
510
+ XlnxBBRam *s = XLNX_BBRAM(dev);
511
+ unsigned int i;
512
+
513
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
514
+ if (i < R_BBRAM_0 || i > R_BBRAM_8) {
515
+ register_reset(&s->regs_info[i]);
516
+ }
517
+ }
518
+
519
+ bbram_update_irq(s);
520
+}
521
+
522
+static const MemoryRegionOps bbram_ctrl_ops = {
523
+ .read = register_read_memory,
524
+ .write = register_write_memory,
525
+ .endianness = DEVICE_LITTLE_ENDIAN,
526
+ .valid = {
527
+ .min_access_size = 4,
528
+ .max_access_size = 4,
529
+ },
530
+};
531
+
532
+static void bbram_ctrl_realize(DeviceState *dev, Error **errp)
533
+{
534
+ XlnxBBRam *s = XLNX_BBRAM(dev);
535
+
536
+ if (s->crc_zpads) {
537
+ s->bbram8_wo = true;
538
+ }
539
+
540
+ bbram_bdrv_read(s, errp);
541
+}
542
+
543
+static void bbram_ctrl_init(Object *obj)
544
+{
545
+ XlnxBBRam *s = XLNX_BBRAM(obj);
546
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
547
+ RegisterInfoArray *reg_array;
548
+
549
+ reg_array =
550
+ register_init_block32(DEVICE(obj), bbram_ctrl_regs_info,
551
+ ARRAY_SIZE(bbram_ctrl_regs_info),
552
+ s->regs_info, s->regs,
553
+ &bbram_ctrl_ops,
554
+ XLNX_BBRAM_ERR_DEBUG,
555
+ R_MAX * 4);
556
+
557
+ sysbus_init_mmio(sbd, &reg_array->mem);
558
+ sysbus_init_irq(sbd, &s->irq_bbram);
559
+}
560
+
561
+static void bbram_prop_set_drive(Object *obj, Visitor *v, const char *name,
562
+ void *opaque, Error **errp)
563
+{
564
+ DeviceState *dev = DEVICE(obj);
565
+
566
+ qdev_prop_drive.set(obj, v, name, opaque, errp);
567
+
568
+ /* Fill initial data if backend is attached after realized */
569
+ if (dev->realized) {
570
+ bbram_bdrv_read(XLNX_BBRAM(obj), errp);
571
+ }
572
+}
573
+
574
+static void bbram_prop_get_drive(Object *obj, Visitor *v, const char *name,
575
+ void *opaque, Error **errp)
576
+{
577
+ qdev_prop_drive.get(obj, v, name, opaque, errp);
578
+}
579
+
580
+static void bbram_prop_release_drive(Object *obj, const char *name,
581
+ void *opaque)
582
+{
583
+ qdev_prop_drive.release(obj, name, opaque);
584
+}
585
+
586
+static const PropertyInfo bbram_prop_drive = {
587
+ .name = "str",
588
+ .description = "Node name or ID of a block device to use as BBRAM backend",
589
+ .realized_set_allowed = true,
590
+ .get = bbram_prop_get_drive,
591
+ .set = bbram_prop_set_drive,
592
+ .release = bbram_prop_release_drive,
593
+};
594
+
595
+static const VMStateDescription vmstate_bbram_ctrl = {
596
+ .name = TYPE_XLNX_BBRAM,
597
+ .version_id = 1,
598
+ .minimum_version_id = 1,
599
+ .fields = (VMStateField[]) {
600
+ VMSTATE_UINT32_ARRAY(regs, XlnxBBRam, R_MAX),
601
+ VMSTATE_END_OF_LIST(),
602
+ }
603
+};
604
+
605
+static Property bbram_ctrl_props[] = {
606
+ DEFINE_PROP("drive", XlnxBBRam, blk, bbram_prop_drive, BlockBackend *),
607
+ DEFINE_PROP_UINT32("crc-zpads", XlnxBBRam, crc_zpads, 1),
608
+ DEFINE_PROP_END_OF_LIST(),
609
+};
610
+
611
+static void bbram_ctrl_class_init(ObjectClass *klass, void *data)
612
+{
613
+ DeviceClass *dc = DEVICE_CLASS(klass);
614
+
615
+ dc->reset = bbram_ctrl_reset;
616
+ dc->realize = bbram_ctrl_realize;
617
+ dc->vmsd = &vmstate_bbram_ctrl;
618
+ device_class_set_props(dc, bbram_ctrl_props);
619
+}
620
+
621
+static const TypeInfo bbram_ctrl_info = {
622
+ .name = TYPE_XLNX_BBRAM,
623
+ .parent = TYPE_SYS_BUS_DEVICE,
624
+ .instance_size = sizeof(XlnxBBRam),
625
+ .class_init = bbram_ctrl_class_init,
626
+ .instance_init = bbram_ctrl_init,
627
+};
628
+
629
+static void bbram_ctrl_register_types(void)
630
+{
631
+ type_register_static(&bbram_ctrl_info);
632
+}
633
+
634
+type_init(bbram_ctrl_register_types)
635
diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig
636
index XXXXXXX..XXXXXXX 100644
637
--- a/hw/nvram/Kconfig
638
+++ b/hw/nvram/Kconfig
639
@@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE_VERSAL
640
config XLNX_EFUSE_ZYNQMP
641
bool
642
select XLNX_EFUSE
643
+
644
+config XLNX_BBRAM
645
+ bool
646
+ select XLNX_EFUSE_CRC
647
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
648
index XXXXXXX..XXXXXXX 100644
649
--- a/hw/nvram/meson.build
650
+++ b/hw/nvram/meson.build
651
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files(
652
'xlnx-versal-efuse-ctrl.c'))
653
softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files(
654
'xlnx-zynqmp-efuse.c'))
655
+softmmu_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c'))
656
657
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
658
--
659
2.20.1
660
661
diff view generated by jsdifflib
New patch
[PULL 07/22] hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device
1
From: Tong Ho <tong.ho@xilinx.com>
1
2
3
Connect the support for Versal Battery-Backed RAM (BBRAM)
4
5
The command argument:
6
-drive if=pflash,index=0,...
7
Can be used to optionally connect the bbram to a backend
8
storage, such that field-programmed values in one
9
invocation can be made available to next invocation.
10
11
The backend storage must be a seekable binary file, and
12
its size must be 36 bytes or larger. A file with all
13
binary 0's is a 'blank'.
14
15
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
16
Message-id: 20210917052400.1249094-6-tong.ho@xilinx.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
include/hw/arm/xlnx-versal.h | 5 +++++
21
hw/arm/xlnx-versal-virt.c | 36 ++++++++++++++++++++++++++++++++++++
22
hw/arm/xlnx-versal.c | 18 ++++++++++++++++++
23
hw/arm/Kconfig | 1 +
24
4 files changed, 60 insertions(+)
25
26
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/xlnx-versal.h
29
+++ b/include/hw/arm/xlnx-versal.h
30
@@ -XXX,XX +XXX,XX @@
31
#include "qom/object.h"
32
#include "hw/usb/xlnx-usb-subsystem.h"
33
#include "hw/misc/xlnx-versal-xramc.h"
34
+#include "hw/nvram/xlnx-bbram.h"
35
36
#define TYPE_XLNX_VERSAL "xlnx-versal"
37
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
38
@@ -XXX,XX +XXX,XX @@ struct Versal {
39
} iou;
40
41
XlnxZynqMPRTC rtc;
42
+ XlnxBBRam bbram;
43
} pmc;
44
45
struct {
46
@@ -XXX,XX +XXX,XX @@ struct Versal {
47
#define VERSAL_GEM1_WAKE_IRQ_0 59
48
#define VERSAL_ADMA_IRQ_0 60
49
#define VERSAL_XRAM_IRQ_0 79
50
+#define VERSAL_BBRAM_APB_IRQ_0 121
51
#define VERSAL_RTC_APB_ERR_IRQ 121
52
#define VERSAL_SD0_IRQ_0 126
53
#define VERSAL_RTC_ALARM_IRQ 142
54
@@ -XXX,XX +XXX,XX @@ struct Versal {
55
56
#define MM_PMC_SD0 0xf1040000U
57
#define MM_PMC_SD0_SIZE 0x10000
58
+#define MM_PMC_BBRAM_CTRL 0xf11f0000
59
+#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
60
#define MM_PMC_CRP 0xf1260000U
61
#define MM_PMC_CRP_SIZE 0x10000
62
#define MM_PMC_RTC 0xf12a0000
63
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/arm/xlnx-versal-virt.c
66
+++ b/hw/arm/xlnx-versal-virt.c
67
@@ -XXX,XX +XXX,XX @@ static void fdt_add_rtc_node(VersalVirt *s)
68
g_free(name);
69
}
70
71
+static void fdt_add_bbram_node(VersalVirt *s)
72
+{
73
+ const char compat[] = TYPE_XLNX_BBRAM;
74
+ const char interrupt_names[] = "bbram-error";
75
+ char *name = g_strdup_printf("/bbram@%x", MM_PMC_BBRAM_CTRL);
76
+
77
+ qemu_fdt_add_subnode(s->fdt, name);
78
+
79
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
80
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_BBRAM_APB_IRQ_0,
81
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
82
+ qemu_fdt_setprop(s->fdt, name, "interrupt-names",
83
+ interrupt_names, sizeof(interrupt_names));
84
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
85
+ 2, MM_PMC_BBRAM_CTRL,
86
+ 2, MM_PMC_BBRAM_CTRL_SIZE);
87
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
88
+ g_free(name);
89
+}
90
+
91
static void fdt_nop_memory_nodes(void *fdt, Error **errp)
92
{
93
Error *err = NULL;
94
@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
95
}
96
}
97
98
+static void bbram_attach_drive(XlnxBBRam *dev)
99
+{
100
+ DriveInfo *dinfo;
101
+ BlockBackend *blk;
102
+
103
+ dinfo = drive_get_by_index(IF_PFLASH, 0);
104
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
105
+ if (blk) {
106
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
107
+ }
108
+}
109
+
110
static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
111
{
112
BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
113
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
114
fdt_add_usb_xhci_nodes(s);
115
fdt_add_sd_nodes(s);
116
fdt_add_rtc_node(s);
117
+ fdt_add_bbram_node(s);
118
fdt_add_cpu_nodes(s, psci_conduit);
119
fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
120
fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
121
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
122
memory_region_add_subregion_overlap(get_system_memory(),
123
0, &s->soc.fpd.apu.mr, 0);
124
125
+ /* Attach bbram backend, if given */
126
+ bbram_attach_drive(&s->soc.pmc.bbram);
127
+
128
/* Plugin SD cards. */
129
for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
130
sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
131
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/hw/arm/xlnx-versal.c
134
+++ b/hw/arm/xlnx-versal.c
135
@@ -XXX,XX +XXX,XX @@ static void versal_create_xrams(Versal *s, qemu_irq *pic)
136
}
137
}
138
139
+static void versal_create_bbram(Versal *s, qemu_irq *pic)
140
+{
141
+ SysBusDevice *sbd;
142
+
143
+ object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram,
144
+ sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM,
145
+ &error_fatal,
146
+ "crc-zpads", "0",
147
+ NULL);
148
+ sbd = SYS_BUS_DEVICE(&s->pmc.bbram);
149
+
150
+ sysbus_realize(sbd, &error_fatal);
151
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL,
152
+ sysbus_mmio_get_region(sbd, 0));
153
+ sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]);
154
+}
155
+
156
/* This takes the board allocated linear DDR memory and creates aliases
157
* for each split DDR range/aperture on the Versal address map.
158
*/
159
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
160
versal_create_sds(s, pic);
161
versal_create_rtc(s, pic);
162
versal_create_xrams(s, pic);
163
+ versal_create_bbram(s, pic);
164
versal_map_ddr(s);
165
versal_unimp(s);
166
167
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
168
index XXXXXXX..XXXXXXX 100644
169
--- a/hw/arm/Kconfig
170
+++ b/hw/arm/Kconfig
171
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
172
select XLNX_ZDMA
173
select XLNX_ZYNQMP
174
select OR_IRQ
175
+ select XLNX_BBRAM
176
177
config NPCM7XX
178
bool
179
--
180
2.20.1
181
182
diff view generated by jsdifflib
[PULL 12/14] target/arm: Add sve-default-vector-length cpu property
[PULL 08/22] hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Tong Ho <tong.ho@xilinx.com>
2
2
3
Mirror the behavour of /proc/sys/abi/sve_default_vector_length
3
Connect the support for Versal eFUSE one-time field-programmable
4
under the real linux kernel. We have no way of passing along
4
bit array.
5
a real default across exec like the kernel can, but this is a
5
6
decent way of adjusting the startup vector length of a process.
6
The command argument:
7
7
-drive if=pflash,index=1,...
8
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/482
8
Can be used to optionally connect the bit array to a
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
backend storage, such that field-programmed values
10
in one invocation can be made available to next
11
invocation.
12
13
The backend storage must be a seekable binary file, and
14
its size must be 3072 bytes or larger. A file with all
15
binary 0's is a 'blank'.
16
17
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
18
Message-id: 20210917052400.1249094-7-tong.ho@xilinx.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20210723203344.968563-4-richard.henderson@linaro.org
12
[PMM: tweaked docs formatting, document -1 special-case,
13
added fixup patch from RTH mentioning QEMU's maximum veclen.]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
21
---
16
docs/system/arm/cpu-features.rst | 15 ++++++++
22
include/hw/arm/xlnx-versal.h | 10 +++++++
17
target/arm/cpu.h | 5 +++
23
hw/arm/xlnx-versal-virt.c | 52 ++++++++++++++++++++++++++++++++++++
18
target/arm/cpu.c | 14 ++++++--
24
hw/arm/xlnx-versal.c | 39 +++++++++++++++++++++++++++
19
target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++
25
hw/arm/Kconfig | 1 +
20
4 files changed, 92 insertions(+), 2 deletions(-)
26
4 files changed, 102 insertions(+)
21
27
22
diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
28
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
23
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
24
--- a/docs/system/arm/cpu-features.rst
30
--- a/include/hw/arm/xlnx-versal.h
25
+++ b/docs/system/arm/cpu-features.rst
31
+++ b/include/hw/arm/xlnx-versal.h
26
@@ -XXX,XX +XXX,XX @@ verbose command lines. However, the recommended way to select vector
32
@@ -XXX,XX +XXX,XX @@
27
lengths is to explicitly enable each desired length. Therefore only
33
#include "hw/usb/xlnx-usb-subsystem.h"
28
example's (1), (4), and (6) exhibit recommended uses of the properties.
34
#include "hw/misc/xlnx-versal-xramc.h"
29
35
#include "hw/nvram/xlnx-bbram.h"
30
+SVE User-mode Default Vector Length Property
36
+#include "hw/nvram/xlnx-versal-efuse.h"
31
+--------------------------------------------
37
32
+
38
#define TYPE_XLNX_VERSAL "xlnx-versal"
33
+For qemu-aarch64, the cpu property ``sve-default-vector-length=N`` is
39
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
34
+defined to mirror the Linux kernel parameter file
40
@@ -XXX,XX +XXX,XX @@ struct Versal {
35
+``/proc/sys/abi/sve_default_vector_length``. The default length, ``N``,
41
36
+is in units of bytes and must be between 16 and 8192.
42
XlnxZynqMPRTC rtc;
37
+If not specified, the default vector length is 64.
43
XlnxBBRam bbram;
38
+
44
+ XlnxEFuse efuse;
39
+If the default length is larger than the maximum vector length enabled,
45
+ XlnxVersalEFuseCtrl efuse_ctrl;
40
+the actual vector length will be reduced. Note that the maximum vector
46
+ XlnxVersalEFuseCache efuse_cache;
41
+length supported by QEMU is 256.
47
} pmc;
42
+
48
43
+If this property is set to ``-1`` then the default vector length
49
struct {
44
+is set to the maximum possible length.
50
@@ -XXX,XX +XXX,XX @@ struct Versal {
45
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
51
#define VERSAL_BBRAM_APB_IRQ_0 121
46
index XXXXXXX..XXXXXXX 100644
52
#define VERSAL_RTC_APB_ERR_IRQ 121
47
--- a/target/arm/cpu.h
53
#define VERSAL_SD0_IRQ_0 126
48
+++ b/target/arm/cpu.h
54
+#define VERSAL_EFUSE_IRQ 139
49
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
55
#define VERSAL_RTC_ALARM_IRQ 142
50
/* Used to set the maximum vector length the cpu will support. */
56
#define VERSAL_RTC_SECONDS_IRQ 143
51
uint32_t sve_max_vq;
57
52
58
@@ -XXX,XX +XXX,XX @@ struct Versal {
53
+#ifdef CONFIG_USER_ONLY
59
#define MM_PMC_SD0_SIZE 0x10000
54
+ /* Used to set the default vector length at process start. */
60
#define MM_PMC_BBRAM_CTRL 0xf11f0000
55
+ uint32_t sve_default_vq;
61
#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
56
+#endif
62
+#define MM_PMC_EFUSE_CTRL 0xf1240000
57
+
63
+#define MM_PMC_EFUSE_CTRL_SIZE 0x00104
58
/*
64
+#define MM_PMC_EFUSE_CACHE 0xf1250000
59
* In sve_vq_map each set bit is a supported vector length of
65
+#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00
60
* (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
66
+
61
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
67
#define MM_PMC_CRP 0xf1260000U
62
index XXXXXXX..XXXXXXX 100644
68
#define MM_PMC_CRP_SIZE 0x10000
63
--- a/target/arm/cpu.c
69
#define MM_PMC_RTC 0xf12a0000
64
+++ b/target/arm/cpu.c
70
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
65
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
71
index XXXXXXX..XXXXXXX 100644
66
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
72
--- a/hw/arm/xlnx-versal-virt.c
67
/* with reasonable vector length */
73
+++ b/hw/arm/xlnx-versal-virt.c
68
if (cpu_isar_feature(aa64_sve, cpu)) {
74
@@ -XXX,XX +XXX,XX @@ static void fdt_add_bbram_node(VersalVirt *s)
69
- env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3);
75
g_free(name);
70
+ env->vfp.zcr_el[1] =
71
+ aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1);
72
}
73
/*
74
* Enable TBI0 but not TBI1.
75
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
76
QLIST_INIT(&cpu->pre_el_change_hooks);
77
QLIST_INIT(&cpu->el_change_hooks);
78
79
-#ifndef CONFIG_USER_ONLY
80
+#ifdef CONFIG_USER_ONLY
81
+# ifdef TARGET_AARCH64
82
+ /*
83
+ * The linux kernel defaults to 512-bit vectors, when sve is supported.
84
+ * See documentation for /proc/sys/abi/sve_default_vector_length, and
85
+ * our corresponding sve-default-vector-length cpu property.
86
+ */
87
+ cpu->sve_default_vq = 4;
88
+# endif
89
+#else
90
/* Our inbound IRQ and FIQ lines */
91
if (kvm_enabled()) {
92
/* VIRQ and VFIQ are unused with KVM but we add them to maintain
93
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
94
index XXXXXXX..XXXXXXX 100644
95
--- a/target/arm/cpu64.c
96
+++ b/target/arm/cpu64.c
97
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)
98
cpu->isar.id_aa64pfr0 = t;
99
}
76
}
100
77
101
+#ifdef CONFIG_USER_ONLY
78
+static void fdt_add_efuse_ctrl_node(VersalVirt *s)
102
+/* Mirror linux /proc/sys/abi/sve_default_vector_length. */
79
+{
103
+static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v,
80
+ const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CTRL;
104
+ const char *name, void *opaque,
81
+ const char interrupt_names[] = "pmc_efuse";
105
+ Error **errp)
82
+ char *name = g_strdup_printf("/pmc_efuse@%x", MM_PMC_EFUSE_CTRL);
106
+{
83
+
107
+ ARMCPU *cpu = ARM_CPU(obj);
84
+ qemu_fdt_add_subnode(s->fdt, name);
108
+ int32_t default_len, default_vq, remainder;
85
+
109
+
86
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
110
+ if (!visit_type_int32(v, name, &default_len, errp)) {
87
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_EFUSE_IRQ,
111
+ return;
88
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
89
+ qemu_fdt_setprop(s->fdt, name, "interrupt-names",
90
+ interrupt_names, sizeof(interrupt_names));
91
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
92
+ 2, MM_PMC_EFUSE_CTRL,
93
+ 2, MM_PMC_EFUSE_CTRL_SIZE);
94
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
95
+ g_free(name);
96
+}
97
+
98
+static void fdt_add_efuse_cache_node(VersalVirt *s)
99
+{
100
+ const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CACHE;
101
+ char *name = g_strdup_printf("/xlnx_pmc_efuse_cache@%x",
102
+ MM_PMC_EFUSE_CACHE);
103
+
104
+ qemu_fdt_add_subnode(s->fdt, name);
105
+
106
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
107
+ 2, MM_PMC_EFUSE_CACHE,
108
+ 2, MM_PMC_EFUSE_CACHE_SIZE);
109
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
110
+ g_free(name);
111
+}
112
+
113
static void fdt_nop_memory_nodes(void *fdt, Error **errp)
114
{
115
Error *err = NULL;
116
@@ -XXX,XX +XXX,XX @@ static void bbram_attach_drive(XlnxBBRam *dev)
117
}
118
}
119
120
+static void efuse_attach_drive(XlnxEFuse *dev)
121
+{
122
+ DriveInfo *dinfo;
123
+ BlockBackend *blk;
124
+
125
+ dinfo = drive_get_by_index(IF_PFLASH, 1);
126
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
127
+ if (blk) {
128
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
112
+ }
129
+ }
113
+
130
+}
114
+ /* Undocumented, but the kernel allows -1 to indicate "maximum". */
131
+
115
+ if (default_len == -1) {
132
static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
116
+ cpu->sve_default_vq = ARM_MAX_VQ;
117
+ return;
118
+ }
119
+
120
+ default_vq = default_len / 16;
121
+ remainder = default_len % 16;
122
+
123
+ /*
124
+ * Note that the 512 max comes from include/uapi/asm/sve_context.h
125
+ * and is the maximum architectural width of ZCR_ELx.LEN.
126
+ */
127
+ if (remainder || default_vq < 1 || default_vq > 512) {
128
+ error_setg(errp, "cannot set sve-default-vector-length");
129
+ if (remainder) {
130
+ error_append_hint(errp, "Vector length not a multiple of 16\n");
131
+ } else if (default_vq < 1) {
132
+ error_append_hint(errp, "Vector length smaller than 16\n");
133
+ } else {
134
+ error_append_hint(errp, "Vector length larger than %d\n",
135
+ 512 * 16);
136
+ }
137
+ return;
138
+ }
139
+
140
+ cpu->sve_default_vq = default_vq;
141
+}
142
+
143
+static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v,
144
+ const char *name, void *opaque,
145
+ Error **errp)
146
+{
147
+ ARMCPU *cpu = ARM_CPU(obj);
148
+ int32_t value = cpu->sve_default_vq * 16;
149
+
150
+ visit_type_int32(v, name, &value, errp);
151
+}
152
+#endif
153
+
154
void aarch64_add_sve_properties(Object *obj)
155
{
133
{
156
uint32_t vq;
134
BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
157
@@ -XXX,XX +XXX,XX @@ void aarch64_add_sve_properties(Object *obj)
135
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
158
object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
136
fdt_add_sd_nodes(s);
159
cpu_arm_set_sve_vq, NULL, NULL);
137
fdt_add_rtc_node(s);
160
}
138
fdt_add_bbram_node(s);
161
+
139
+ fdt_add_efuse_ctrl_node(s);
162
+#ifdef CONFIG_USER_ONLY
140
+ fdt_add_efuse_cache_node(s);
163
+ /* Mirror linux /proc/sys/abi/sve_default_vector_length. */
141
fdt_add_cpu_nodes(s, psci_conduit);
164
+ object_property_add(obj, "sve-default-vector-length", "int32",
142
fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
165
+ cpu_arm_get_sve_default_vec_len,
143
fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
166
+ cpu_arm_set_sve_default_vec_len, NULL, NULL);
144
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
167
+#endif
145
/* Attach bbram backend, if given */
146
bbram_attach_drive(&s->soc.pmc.bbram);
147
148
+ /* Attach efuse backend, if given */
149
+ efuse_attach_drive(&s->soc.pmc.efuse);
150
+
151
/* Plugin SD cards. */
152
for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
153
sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
154
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
155
index XXXXXXX..XXXXXXX 100644
156
--- a/hw/arm/xlnx-versal.c
157
+++ b/hw/arm/xlnx-versal.c
158
@@ -XXX,XX +XXX,XX @@ static void versal_create_bbram(Versal *s, qemu_irq *pic)
159
sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]);
168
}
160
}
169
161
170
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
162
+static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base)
163
+{
164
+ SysBusDevice *part = SYS_BUS_DEVICE(dev);
165
+
166
+ object_property_set_link(OBJECT(part), "efuse",
167
+ OBJECT(&s->pmc.efuse), &error_abort);
168
+
169
+ sysbus_realize(part, &error_abort);
170
+ memory_region_add_subregion(&s->mr_ps, base,
171
+ sysbus_mmio_get_region(part, 0));
172
+}
173
+
174
+static void versal_create_efuse(Versal *s, qemu_irq *pic)
175
+{
176
+ Object *bits = OBJECT(&s->pmc.efuse);
177
+ Object *ctrl = OBJECT(&s->pmc.efuse_ctrl);
178
+ Object *cache = OBJECT(&s->pmc.efuse_cache);
179
+
180
+ object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl,
181
+ TYPE_XLNX_VERSAL_EFUSE_CTRL);
182
+
183
+ object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache,
184
+ TYPE_XLNX_VERSAL_EFUSE_CACHE);
185
+
186
+ object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits,
187
+ sizeof(s->pmc.efuse),
188
+ TYPE_XLNX_EFUSE, &error_abort,
189
+ "efuse-nr", "3",
190
+ "efuse-size", "8192",
191
+ NULL);
192
+
193
+ qdev_realize(DEVICE(bits), NULL, &error_abort);
194
+ versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL);
195
+ versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE);
196
+
197
+ sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]);
198
+}
199
+
200
/* This takes the board allocated linear DDR memory and creates aliases
201
* for each split DDR range/aperture on the Versal address map.
202
*/
203
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
204
versal_create_rtc(s, pic);
205
versal_create_xrams(s, pic);
206
versal_create_bbram(s, pic);
207
+ versal_create_efuse(s, pic);
208
versal_map_ddr(s);
209
versal_unimp(s);
210
211
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
212
index XXXXXXX..XXXXXXX 100644
213
--- a/hw/arm/Kconfig
214
+++ b/hw/arm/Kconfig
215
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
216
select XLNX_ZYNQMP
217
select OR_IRQ
218
select XLNX_BBRAM
219
+ select XLNX_EFUSE_VERSAL
220
221
config NPCM7XX
222
bool
171
--
223
--
172
2.20.1
224
2.20.1
173
225
174
226
diff view generated by jsdifflib
New patch
[PULL 09/22] hw/arm: xlnx-zcu102: Add Xilinx BBRAM device
1
From: Tong Ho <tong.ho@xilinx.com>
1
2
3
Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM)
4
5
The command argument:
6
-drive if=pflash,index=2,...
7
Can be used to optionally connect the bbram to a backend
8
storage, such that field-programmed values in one
9
invocation can be made available to next invocation.
10
11
The backend storage must be a seekable binary file, and
12
its size must be 36 bytes or larger. A file with all
13
binary 0's is a 'blank'.
14
15
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
16
Message-id: 20210917052400.1249094-8-tong.ho@xilinx.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
include/hw/arm/xlnx-zynqmp.h | 2 ++
21
hw/arm/xlnx-zcu102.c | 15 +++++++++++++++
22
hw/arm/xlnx-zynqmp.c | 20 ++++++++++++++++++++
23
hw/Kconfig | 1 +
24
4 files changed, 38 insertions(+)
25
26
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/xlnx-zynqmp.h
29
+++ b/include/hw/arm/xlnx-zynqmp.h
30
@@ -XXX,XX +XXX,XX @@
31
#include "qom/object.h"
32
#include "net/can_emu.h"
33
#include "hw/dma/xlnx_csu_dma.h"
34
+#include "hw/nvram/xlnx-bbram.h"
35
36
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
37
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
38
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
39
40
MemoryRegion *ddr_ram;
41
MemoryRegion ddr_ram_low, ddr_ram_high;
42
+ XlnxBBRam bbram;
43
44
MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
45
46
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/xlnx-zcu102.c
49
+++ b/hw/arm/xlnx-zcu102.c
50
@@ -XXX,XX +XXX,XX @@ static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt)
51
}
52
}
53
54
+static void bbram_attach_drive(XlnxBBRam *dev)
55
+{
56
+ DriveInfo *dinfo;
57
+ BlockBackend *blk;
58
+
59
+ dinfo = drive_get_by_index(IF_PFLASH, 2);
60
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
61
+ if (blk) {
62
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
63
+ }
64
+}
65
+
66
static void xlnx_zcu102_init(MachineState *machine)
67
{
68
XlnxZCU102 *s = ZCU102_MACHINE(machine);
69
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
70
71
qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
72
73
+ /* Attach bbram backend, if given */
74
+ bbram_attach_drive(&s->soc.bbram);
75
+
76
/* Create and plug in the SD cards */
77
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
78
BusState *bus;
79
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/arm/xlnx-zynqmp.c
82
+++ b/hw/arm/xlnx-zynqmp.c
83
@@ -XXX,XX +XXX,XX @@
84
#define RTC_ADDR 0xffa60000
85
#define RTC_IRQ 26
86
87
+#define BBRAM_ADDR 0xffcd0000
88
+#define BBRAM_IRQ 11
89
+
90
#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
91
92
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
93
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
94
qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
95
}
96
97
+static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
98
+{
99
+ SysBusDevice *sbd;
100
+
101
+ object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram,
102
+ sizeof(s->bbram), TYPE_XLNX_BBRAM,
103
+ &error_fatal,
104
+ "crc-zpads", "1",
105
+ NULL);
106
+ sbd = SYS_BUS_DEVICE(&s->bbram);
107
+
108
+ sysbus_realize(sbd, &error_fatal);
109
+ sysbus_mmio_map(sbd, 0, BBRAM_ADDR);
110
+ sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
111
+}
112
+
113
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
114
{
115
static const struct UnimpInfo {
116
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
117
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
118
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
119
120
+ xlnx_zynqmp_create_bbram(s, gic_spi);
121
xlnx_zynqmp_create_unimp_mmio(s);
122
123
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
124
diff --git a/hw/Kconfig b/hw/Kconfig
125
index XXXXXXX..XXXXXXX 100644
126
--- a/hw/Kconfig
127
+++ b/hw/Kconfig
128
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP
129
select REGISTER
130
select CAN_BUS
131
select PTIMER
132
+ select XLNX_BBRAM
133
--
134
2.20.1
135
136
diff view generated by jsdifflib
[PULL 09/14] docs: Update path that mentions deprecated.rst
[PULL 10/22] hw/arm: xlnx-zcu102: Add Xilinx eFUSE device
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
From: Tong Ho <tong.ho@xilinx.com>
2
2
3
Missed in commit f3478392 "docs: Move deprecation, build
3
Connect the support for ZynqMP eFUSE one-time field-programmable
4
and license info out of system/"
4
bit array.
5
5
6
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
6
The command argument:
7
-drive if=pflash,index=3,...
8
Can be used to optionally connect the bit array to a
9
backend storage, such that field-programmed values
10
in one invocation can be made available to next
11
invocation.
12
13
The backend storage must be a seekable binary file, and
14
its size must be 768 bytes or larger. A file with all
15
binary 0's is a 'blank'.
16
17
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
18
Message-id: 20210917052400.1249094-9-tong.ho@xilinx.com
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20210723065828.1336760-1-maozhongyi@cmss.chinamobile.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
21
---
11
configure | 2 +-
22
include/hw/arm/xlnx-zynqmp.h | 3 +++
12
target/i386/cpu.c | 2 +-
23
hw/arm/xlnx-zcu102.c | 15 +++++++++++++++
13
MAINTAINERS | 2 +-
24
hw/arm/xlnx-zynqmp.c | 29 +++++++++++++++++++++++++++++
14
3 files changed, 3 insertions(+), 3 deletions(-)
25
hw/Kconfig | 1 +
26
4 files changed, 48 insertions(+)
15
27
16
diff --git a/configure b/configure
28
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
17
index XXXXXXX..XXXXXXX 100755
18
--- a/configure
19
+++ b/configure
20
@@ -XXX,XX +XXX,XX @@ fi
21
22
if test -n "${deprecated_features}"; then
23
echo "Warning, deprecated features enabled."
24
- echo "Please see docs/system/deprecated.rst"
25
+ echo "Please see docs/about/deprecated.rst"
26
echo " features: ${deprecated_features}"
27
fi
28
29
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
30
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
31
--- a/target/i386/cpu.c
30
--- a/include/hw/arm/xlnx-zynqmp.h
32
+++ b/target/i386/cpu.c
31
+++ b/include/hw/arm/xlnx-zynqmp.h
33
@@ -XXX,XX +XXX,XX @@ static const X86CPUDefinition builtin_x86_defs[] = {
32
@@ -XXX,XX +XXX,XX @@
34
* none", but this is just for compatibility while libvirt isn't
33
#include "net/can_emu.h"
35
* adapted to resolve CPU model versions before creating VMs.
34
#include "hw/dma/xlnx_csu_dma.h"
36
* See "Runnability guarantee of CPU models" at
35
#include "hw/nvram/xlnx-bbram.h"
37
- * docs/system/deprecated.rst.
36
+#include "hw/nvram/xlnx-zynqmp-efuse.h"
38
+ * docs/about/deprecated.rst.
37
39
*/
38
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
40
X86CPUVersion default_cpu_version = 1;
39
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
41
40
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
42
diff --git a/MAINTAINERS b/MAINTAINERS
41
MemoryRegion *ddr_ram;
42
MemoryRegion ddr_ram_low, ddr_ram_high;
43
XlnxBBRam bbram;
44
+ XlnxEFuse efuse;
45
+ XlnxZynqMPEFuse efuse_ctrl;
46
47
MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
48
49
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
43
index XXXXXXX..XXXXXXX 100644
50
index XXXXXXX..XXXXXXX 100644
44
--- a/MAINTAINERS
51
--- a/hw/arm/xlnx-zcu102.c
45
+++ b/MAINTAINERS
52
+++ b/hw/arm/xlnx-zcu102.c
46
@@ -XXX,XX +XXX,XX @@ F: contrib/gitdm/*
53
@@ -XXX,XX +XXX,XX @@ static void bbram_attach_drive(XlnxBBRam *dev)
47
54
}
48
Incompatible changes
55
}
49
R: libvir-list@redhat.com
56
50
-F: docs/system/deprecated.rst
57
+static void efuse_attach_drive(XlnxEFuse *dev)
51
+F: docs/about/deprecated.rst
58
+{
52
59
+ DriveInfo *dinfo;
53
Build System
60
+ BlockBackend *blk;
54
------------
61
+
62
+ dinfo = drive_get_by_index(IF_PFLASH, 3);
63
+ blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
64
+ if (blk) {
65
+ qdev_prop_set_drive(DEVICE(dev), "drive", blk);
66
+ }
67
+}
68
+
69
static void xlnx_zcu102_init(MachineState *machine)
70
{
71
XlnxZCU102 *s = ZCU102_MACHINE(machine);
72
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
73
/* Attach bbram backend, if given */
74
bbram_attach_drive(&s->soc.bbram);
75
76
+ /* Attach efuse backend, if given */
77
+ efuse_attach_drive(&s->soc.efuse);
78
+
79
/* Create and plug in the SD cards */
80
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
81
BusState *bus;
82
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/hw/arm/xlnx-zynqmp.c
85
+++ b/hw/arm/xlnx-zynqmp.c
86
@@ -XXX,XX +XXX,XX @@
87
#define BBRAM_ADDR 0xffcd0000
88
#define BBRAM_IRQ 11
89
90
+#define EFUSE_ADDR 0xffcc0000
91
+#define EFUSE_IRQ 87
92
+
93
#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
94
95
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
96
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
97
sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
98
}
99
100
+static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
101
+{
102
+ Object *bits = OBJECT(&s->efuse);
103
+ Object *ctrl = OBJECT(&s->efuse_ctrl);
104
+ SysBusDevice *sbd;
105
+
106
+ object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl,
107
+ TYPE_XLNX_ZYNQMP_EFUSE);
108
+
109
+ object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits,
110
+ sizeof(s->efuse),
111
+ TYPE_XLNX_EFUSE, &error_abort,
112
+ "efuse-nr", "3",
113
+ "efuse-size", "2048",
114
+ NULL);
115
+
116
+ qdev_realize(DEVICE(bits), NULL, &error_abort);
117
+ object_property_set_link(ctrl, "efuse", bits, &error_abort);
118
+
119
+ sbd = SYS_BUS_DEVICE(ctrl);
120
+ sysbus_realize(sbd, &error_abort);
121
+ sysbus_mmio_map(sbd, 0, EFUSE_ADDR);
122
+ sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
123
+}
124
+
125
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
126
{
127
static const struct UnimpInfo {
128
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
129
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
130
131
xlnx_zynqmp_create_bbram(s, gic_spi);
132
+ xlnx_zynqmp_create_efuse(s, gic_spi);
133
xlnx_zynqmp_create_unimp_mmio(s);
134
135
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
136
diff --git a/hw/Kconfig b/hw/Kconfig
137
index XXXXXXX..XXXXXXX 100644
138
--- a/hw/Kconfig
139
+++ b/hw/Kconfig
140
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP
141
select CAN_BUS
142
select PTIMER
143
select XLNX_BBRAM
144
+ select XLNX_EFUSE_ZYNQMP
55
--
145
--
56
2.20.1
146
2.20.1
57
147
58
148
diff view generated by jsdifflib
[PULL 01/14] hw/arm/smmuv3: Check 31st bit to see if CD is valid
[PULL 11/22] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
1
From: Tong Ho <tong.ho@xilinx.com>
2
2
3
The bit to see if a CD is valid is the last bit of the first word of the CD.
3
Add BBRAM and eFUSE usage to the Xilinx Versal Virt board
4
document.
4
5
5
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
6
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
6
Message-id: 1626728232-134665-2-git-send-email-joe.komlodi@xilinx.com
7
Message-id: 20210917052400.1249094-10-tong.ho@xilinx.com
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
hw/arm/smmuv3-internal.h | 2 +-
11
docs/system/arm/xlnx-versal-virt.rst | 49 ++++++++++++++++++++++++++++
11
1 file changed, 1 insertion(+), 1 deletion(-)
12
1 file changed, 49 insertions(+)
12
13
13
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
14
diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/smmuv3-internal.h
16
--- a/docs/system/arm/xlnx-versal-virt.rst
16
+++ b/hw/arm/smmuv3-internal.h
17
+++ b/docs/system/arm/xlnx-versal-virt.rst
17
@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)
18
@@ -XXX,XX +XXX,XX @@ Implemented devices:
18
19
- OCM (256KB of On Chip Memory)
19
/* CD fields */
20
- XRAM (4MB of on chip Accelerator RAM)
20
21
- DDR memory
21
-#define CD_VALID(x) extract32((x)->word[0], 30, 1)
22
+- BBRAM (36 bytes of Battery-backed RAM)
22
+#define CD_VALID(x) extract32((x)->word[0], 31, 1)
23
+- eFUSE (3072 bytes of one-time field-programmable bit array)
23
#define CD_ASID(x) extract32((x)->word[1], 16, 16)
24
24
#define CD_TTB(x, sel) \
25
QEMU does not yet model any other devices, including the PL and the AI Engine.
25
({ \
26
27
@@ -XXX,XX +XXX,XX @@ Run the following at the U-Boot prompt:
28
fdt set /chosen/dom0 reg <0x00000000 0x40000000 0x0 0x03100000>
29
booti 30000000 - 20000000
30
31
+BBRAM File Backend
32
+""""""""""""""""""
33
+BBRAM can have an optional file backend, which must be a seekable
34
+binary file with a size of 36 bytes or larger. A file with all
35
+binary 0s is a 'blank'.
36
+
37
+To add a file-backend for the BBRAM:
38
+
39
+.. code-block:: bash
40
+
41
+ -drive if=pflash,index=0,file=versal-bbram.bin,format=raw
42
+
43
+To use a different index value, N, from default of 0, add:
44
+
45
+.. code-block:: bash
46
+
47
+ -global xlnx,bbram-ctrl.drive-index=N
48
+
49
+eFUSE File Backend
50
+""""""""""""""""""
51
+eFUSE can have an optional file backend, which must be a seekable
52
+binary file with a size of 3072 bytes or larger. A file with all
53
+binary 0s is a 'blank'.
54
+
55
+To add a file-backend for the eFUSE:
56
+
57
+.. code-block:: bash
58
+
59
+ -drive if=pflash,index=1,file=versal-efuse.bin,format=raw
60
+
61
+To use a different index value, N, from default of 1, add:
62
+
63
+.. code-block:: bash
64
+
65
+ -global xlnx,efuse.drive-index=N
66
+
67
+.. warning::
68
+ In actual physical Versal, BBRAM and eFUSE contain sensitive data.
69
+ The QEMU device models do **not** encrypt nor obfuscate any data
70
+ when holding them in models' memory or when writing them to their
71
+ file backends.
72
+
73
+ Thus, a file backend should be used with caution, and 'format=luks'
74
+ is highly recommended (albeit with usage complexity).
75
+
76
+ Better yet, do not use actual product data when running guest image
77
+ on this Xilinx Versal Virt board.
26
--
78
--
27
2.20.1
79
2.20.1
28
80
29
81
diff view generated by jsdifflib
[PULL 07/14] hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
[PULL 12/22] configs: Don't include 32-bit-only GDB XML in aarch64 linux configs
1
The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of
1
The aarch64-linux QEMU usermode binaries can never run 32-bit
2
the register. We were incorrectly masking it to 8 bits, so it would
2
code, so they do not need to include the GDB XML for it.
3
report the wrong value if the pending exception was greater than 256.
3
(arm_cpu_register_gdb_regs_for_features() will not use these
4
Fix the bug.
4
XML files if the CPU has ARM_FEATURE_AARCH64, so we will not
5
advertise to gdb that we have them.)
5
6
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210723162146.5167-6-peter.maydell@linaro.org
9
Message-id: 20210921162901.17508-2-peter.maydell@linaro.org
9
---
10
---
10
hw/intc/armv7m_nvic.c | 2 +-
11
configs/targets/aarch64-linux-user.mak | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
12
configs/targets/aarch64_be-linux-user.mak | 2 +-
13
2 files changed, 2 insertions(+), 2 deletions(-)
12
14
13
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/armv7m_nvic.c
17
--- a/configs/targets/aarch64-linux-user.mak
16
+++ b/hw/intc/armv7m_nvic.c
18
+++ b/configs/targets/aarch64-linux-user.mak
17
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
19
@@ -XXX,XX +XXX,XX @@
18
/* VECTACTIVE */
20
TARGET_ARCH=aarch64
19
val = cpu->env.v7m.exception;
21
TARGET_BASE_ARCH=arm
20
/* VECTPENDING */
22
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
21
- val |= (s->vectpending & 0xff) << 12;
23
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
22
+ val |= (s->vectpending & 0x1ff) << 12;
24
TARGET_HAS_BFLT=y
23
/* ISRPENDING - set if any external IRQ is pending */
25
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
24
if (nvic_isrpending(s)) {
26
diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak
25
val |= (1 << 22);
27
index XXXXXXX..XXXXXXX 100644
28
--- a/configs/targets/aarch64_be-linux-user.mak
29
+++ b/configs/targets/aarch64_be-linux-user.mak
30
@@ -XXX,XX +XXX,XX @@
31
TARGET_ARCH=aarch64
32
TARGET_BASE_ARCH=arm
33
TARGET_WORDS_BIGENDIAN=y
34
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
35
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
36
TARGET_HAS_BFLT=y
37
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
26
--
38
--
27
2.20.1
39
2.20.1
28
40
29
41
diff view generated by jsdifflib
[PULL 10/14] target/arm: Correctly bound length in sve_zcr_get_valid_len
[PULL 13/22] target/arm: Fix coding style issues in gdbstub code in helper.c
1
From: Richard Henderson <richard.henderson@linaro.org>
1
We're going to move this code to a different file; fix the coding
2
style first so checkpatch doesn't complain. This includes deleting
3
the spurious 'break' statements after returns in the
4
vfp_gdb_get_reg() function.
2
5
3
Currently, our only caller is sve_zcr_len_for_el, which has
4
already masked the length extracted from ZCR_ELx, so the
5
masking done here is a nop. But we will shortly have uses
6
from other locations, where the length will be unmasked.
7
8
Saturate the length to ARM_MAX_VQ instead of truncating to
9
the low 4 bits.
10
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Message-id: 20210723203344.968563-2-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210921162901.17508-3-peter.maydell@linaro.org
15
---
10
---
16
target/arm/helper.c | 4 +++-
11
target/arm/helper.c | 23 ++++++++++++++++-------
17
1 file changed, 3 insertions(+), 1 deletion(-)
12
1 file changed, 16 insertions(+), 7 deletions(-)
18
13
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
16
--- a/target/arm/helper.c
22
+++ b/target/arm/helper.c
17
+++ b/target/arm/helper.c
23
@@ -XXX,XX +XXX,XX @@ static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
18
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
24
{
19
}
25
uint32_t end_len;
20
}
26
21
switch (reg - nregs) {
27
- end_len = start_len &= 0xf;
22
- case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); break;
28
+ start_len = MIN(start_len, ARM_MAX_VQ - 1);
23
- case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break;
29
+ end_len = start_len;
24
- case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); break;
30
+
25
+ case 0:
31
if (!test_bit(start_len, cpu->sve_vq_map)) {
26
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
32
end_len = find_last_bit(cpu->sve_vq_map, start_len);
27
+ case 1:
33
assert(end_len < start_len);
28
+ return gdb_get_reg32(buf, vfp_get_fpscr(env));
29
+ case 2:
30
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
31
}
32
return 0;
33
}
34
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
35
}
36
}
37
switch (reg - nregs) {
38
- case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
39
- case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4;
40
- case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
41
+ case 0:
42
+ env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
43
+ return 4;
44
+ case 1:
45
+ vfp_set_fpscr(env, ldl_p(buf));
46
+ return 4;
47
+ case 2:
48
+ env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
49
+ return 4;
50
}
51
return 0;
52
}
53
@@ -XXX,XX +XXX,XX @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
54
return gdb_get_reg32(buf, vfp_get_fpsr(env));
55
case 33:
56
/* FPCR */
57
- return gdb_get_reg32(buf,vfp_get_fpcr(env));
58
+ return gdb_get_reg32(buf, vfp_get_fpcr(env));
59
default:
60
return 0;
61
}
34
--
62
--
35
2.20.1
63
2.20.1
36
64
37
65
diff view generated by jsdifflib
[PULL 11/14] target/arm: Export aarch64_sve_zcr_get_valid_len
[PULL 14/22] target/arm: Move gdbstub related code out of helper.c
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Currently helper.c includes some code which is part of the arm
2
target's gdbstub support. This code has a better home: in gdbstub.c
3
and gdbstub64.c. Move it there.
2
4
3
Rename from sve_zcr_get_valid_len and make accessible
5
Because aarch64_fpu_gdb_get_reg() and aarch64_fpu_gdb_set_reg() move
4
from outside of helper.c.
6
into gdbstub64.c, this means that they're now compiled only for
7
TARGET_AARCH64 rather than always. That is the only case when they
8
would ever be used, but it does mean that the ifdef in
9
arm_cpu_register_gdb_regs_for_features() needs to be adjusted to
10
match.
5
11
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20210723203344.968563-3-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20210921162901.17508-4-peter.maydell@linaro.org
10
---
16
---
11
target/arm/internals.h | 10 ++++++++++
17
target/arm/internals.h | 7 ++
12
target/arm/helper.c | 4 ++--
18
target/arm/gdbstub.c | 130 ++++++++++++++++++++
13
2 files changed, 12 insertions(+), 2 deletions(-)
19
target/arm/gdbstub64.c | 140 +++++++++++++++++++++
20
target/arm/helper.c | 271 -----------------------------------------
21
4 files changed, 277 insertions(+), 271 deletions(-)
14
22
15
diff --git a/target/arm/internals.h b/target/arm/internals.h
23
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/internals.h
25
--- a/target/arm/internals.h
18
+++ b/target/arm/internals.h
26
+++ b/target/arm/internals.h
19
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void);
27
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
20
void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
28
return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
21
#endif /* CONFIG_TCG */
29
}
22
30
31
+#ifdef TARGET_AARCH64
32
+int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);
33
+int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);
34
+int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
35
+int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
36
+#endif
37
+
38
#endif
39
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/gdbstub.c
42
+++ b/target/arm/gdbstub.c
43
@@ -XXX,XX +XXX,XX @@
44
*/
45
#include "qemu/osdep.h"
46
#include "cpu.h"
47
+#include "internals.h"
48
#include "exec/gdbstub.h"
49
50
typedef struct RegisterSysregXmlParam {
51
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
52
return 0;
53
}
54
55
+static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
56
+{
57
+ ARMCPU *cpu = env_archcpu(env);
58
+ int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
59
+
60
+ /* VFP data registers are always little-endian. */
61
+ if (reg < nregs) {
62
+ return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));
63
+ }
64
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
65
+ /* Aliases for Q regs. */
66
+ nregs += 16;
67
+ if (reg < nregs) {
68
+ uint64_t *q = aa32_vfp_qreg(env, reg - 32);
69
+ return gdb_get_reg128(buf, q[0], q[1]);
70
+ }
71
+ }
72
+ switch (reg - nregs) {
73
+ case 0:
74
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
75
+ case 1:
76
+ return gdb_get_reg32(buf, vfp_get_fpscr(env));
77
+ case 2:
78
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
79
+ }
80
+ return 0;
81
+}
82
+
83
+static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
84
+{
85
+ ARMCPU *cpu = env_archcpu(env);
86
+ int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
87
+
88
+ if (reg < nregs) {
89
+ *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
90
+ return 8;
91
+ }
92
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
93
+ nregs += 16;
94
+ if (reg < nregs) {
95
+ uint64_t *q = aa32_vfp_qreg(env, reg - 32);
96
+ q[0] = ldq_le_p(buf);
97
+ q[1] = ldq_le_p(buf + 8);
98
+ return 16;
99
+ }
100
+ }
101
+ switch (reg - nregs) {
102
+ case 0:
103
+ env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
104
+ return 4;
105
+ case 1:
106
+ vfp_set_fpscr(env, ldl_p(buf));
107
+ return 4;
108
+ case 2:
109
+ env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
110
+ return 4;
111
+ }
112
+ return 0;
113
+}
114
+
23
+/**
115
+/**
24
+ * aarch64_sve_zcr_get_valid_len:
116
+ * arm_get/set_gdb_*: get/set a gdb register
25
+ * @cpu: cpu context
117
+ * @env: the CPU state
26
+ * @start_len: maximum len to consider
118
+ * @buf: a buffer to copy to/from
119
+ * @reg: register number (offset from start of group)
27
+ *
120
+ *
28
+ * Return the maximum supported sve vector length <= @start_len.
121
+ * We return the number of bytes copied
29
+ * Note that both @start_len and the return value are in units
30
+ * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128.
31
+ */
122
+ */
32
+uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len);
123
+
33
124
+static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
34
enum arm_fprounding {
125
+{
35
FPROUNDING_TIEEVEN,
126
+ ARMCPU *cpu = env_archcpu(env);
127
+ const ARMCPRegInfo *ri;
128
+ uint32_t key;
129
+
130
+ key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];
131
+ ri = get_arm_cp_reginfo(cpu->cp_regs, key);
132
+ if (ri) {
133
+ if (cpreg_field_is_64bit(ri)) {
134
+ return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
135
+ } else {
136
+ return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
137
+ }
138
+ }
139
+ return 0;
140
+}
141
+
142
+static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
143
+{
144
+ return 0;
145
+}
146
+
147
static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
148
ARMCPRegInfo *ri, uint32_t ri_key,
149
int bitsize, int regnum)
150
@@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
151
}
152
return NULL;
153
}
154
+
155
+void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
156
+{
157
+ CPUState *cs = CPU(cpu);
158
+ CPUARMState *env = &cpu->env;
159
+
160
+ if (arm_feature(env, ARM_FEATURE_AARCH64)) {
161
+ /*
162
+ * The lower part of each SVE register aliases to the FPU
163
+ * registers so we don't need to include both.
164
+ */
165
+#ifdef TARGET_AARCH64
166
+ if (isar_feature_aa64_sve(&cpu->isar)) {
167
+ gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
168
+ arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
169
+ "sve-registers.xml", 0);
170
+ } else {
171
+ gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
172
+ aarch64_fpu_gdb_set_reg,
173
+ 34, "aarch64-fpu.xml", 0);
174
+ }
175
+#endif
176
+ } else if (arm_feature(env, ARM_FEATURE_NEON)) {
177
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
178
+ 51, "arm-neon.xml", 0);
179
+ } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
180
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
181
+ 35, "arm-vfp3.xml", 0);
182
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
183
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
184
+ 19, "arm-vfp.xml", 0);
185
+ }
186
+ gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
187
+ arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
188
+ "system-registers.xml", 0);
189
+
190
+}
191
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
192
index XXXXXXX..XXXXXXX 100644
193
--- a/target/arm/gdbstub64.c
194
+++ b/target/arm/gdbstub64.c
195
@@ -XXX,XX +XXX,XX @@
196
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
197
*/
198
#include "qemu/osdep.h"
199
+#include "qemu/log.h"
200
#include "cpu.h"
201
+#include "internals.h"
202
#include "exec/gdbstub.h"
203
204
int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
205
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
206
/* Unknown register. */
207
return 0;
208
}
209
+
210
+int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
211
+{
212
+ switch (reg) {
213
+ case 0 ... 31:
214
+ {
215
+ /* 128 bit FP register - quads are in LE order */
216
+ uint64_t *q = aa64_vfp_qreg(env, reg);
217
+ return gdb_get_reg128(buf, q[1], q[0]);
218
+ }
219
+ case 32:
220
+ /* FPSR */
221
+ return gdb_get_reg32(buf, vfp_get_fpsr(env));
222
+ case 33:
223
+ /* FPCR */
224
+ return gdb_get_reg32(buf, vfp_get_fpcr(env));
225
+ default:
226
+ return 0;
227
+ }
228
+}
229
+
230
+int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
231
+{
232
+ switch (reg) {
233
+ case 0 ... 31:
234
+ /* 128 bit FP register */
235
+ {
236
+ uint64_t *q = aa64_vfp_qreg(env, reg);
237
+ q[0] = ldq_le_p(buf);
238
+ q[1] = ldq_le_p(buf + 8);
239
+ return 16;
240
+ }
241
+ case 32:
242
+ /* FPSR */
243
+ vfp_set_fpsr(env, ldl_p(buf));
244
+ return 4;
245
+ case 33:
246
+ /* FPCR */
247
+ vfp_set_fpcr(env, ldl_p(buf));
248
+ return 4;
249
+ default:
250
+ return 0;
251
+ }
252
+}
253
+
254
+int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
255
+{
256
+ ARMCPU *cpu = env_archcpu(env);
257
+
258
+ switch (reg) {
259
+ /* The first 32 registers are the zregs */
260
+ case 0 ... 31:
261
+ {
262
+ int vq, len = 0;
263
+ for (vq = 0; vq < cpu->sve_max_vq; vq++) {
264
+ len += gdb_get_reg128(buf,
265
+ env->vfp.zregs[reg].d[vq * 2 + 1],
266
+ env->vfp.zregs[reg].d[vq * 2]);
267
+ }
268
+ return len;
269
+ }
270
+ case 32:
271
+ return gdb_get_reg32(buf, vfp_get_fpsr(env));
272
+ case 33:
273
+ return gdb_get_reg32(buf, vfp_get_fpcr(env));
274
+ /* then 16 predicates and the ffr */
275
+ case 34 ... 50:
276
+ {
277
+ int preg = reg - 34;
278
+ int vq, len = 0;
279
+ for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
280
+ len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
281
+ }
282
+ return len;
283
+ }
284
+ case 51:
285
+ {
286
+ /*
287
+ * We report in Vector Granules (VG) which is 64bit in a Z reg
288
+ * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
289
+ */
290
+ int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
291
+ return gdb_get_reg64(buf, vq * 2);
292
+ }
293
+ default:
294
+ /* gdbstub asked for something out our range */
295
+ qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
296
+ break;
297
+ }
298
+
299
+ return 0;
300
+}
301
+
302
+int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
303
+{
304
+ ARMCPU *cpu = env_archcpu(env);
305
+
306
+ /* The first 32 registers are the zregs */
307
+ switch (reg) {
308
+ /* The first 32 registers are the zregs */
309
+ case 0 ... 31:
310
+ {
311
+ int vq, len = 0;
312
+ uint64_t *p = (uint64_t *) buf;
313
+ for (vq = 0; vq < cpu->sve_max_vq; vq++) {
314
+ env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
315
+ env->vfp.zregs[reg].d[vq * 2] = *p++;
316
+ len += 16;
317
+ }
318
+ return len;
319
+ }
320
+ case 32:
321
+ vfp_set_fpsr(env, *(uint32_t *)buf);
322
+ return 4;
323
+ case 33:
324
+ vfp_set_fpcr(env, *(uint32_t *)buf);
325
+ return 4;
326
+ case 34 ... 50:
327
+ {
328
+ int preg = reg - 34;
329
+ int vq, len = 0;
330
+ uint64_t *p = (uint64_t *) buf;
331
+ for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
332
+ env->vfp.pregs[preg].p[vq / 4] = *p++;
333
+ len += 8;
334
+ }
335
+ return len;
336
+ }
337
+ case 51:
338
+ /* cannot set vg via gdbstub */
339
+ return 0;
340
+ default:
341
+ /* gdbstub asked for something out our range */
342
+ break;
343
+ }
344
+
345
+ return 0;
346
+}
36
diff --git a/target/arm/helper.c b/target/arm/helper.c
347
diff --git a/target/arm/helper.c b/target/arm/helper.c
37
index XXXXXXX..XXXXXXX 100644
348
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/helper.c
349
--- a/target/arm/helper.c
39
+++ b/target/arm/helper.c
350
+++ b/target/arm/helper.c
40
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
351
@@ -XXX,XX +XXX,XX @@
41
return 0;
352
#include "trace.h"
353
#include "cpu.h"
354
#include "internals.h"
355
-#include "exec/gdbstub.h"
356
#include "exec/helper-proto.h"
357
#include "qemu/host-utils.h"
358
#include "qemu/main-loop.h"
359
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
360
static void switch_mode(CPUARMState *env, int mode);
361
static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
362
363
-static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
364
-{
365
- ARMCPU *cpu = env_archcpu(env);
366
- int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
367
-
368
- /* VFP data registers are always little-endian. */
369
- if (reg < nregs) {
370
- return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg));
371
- }
372
- if (arm_feature(env, ARM_FEATURE_NEON)) {
373
- /* Aliases for Q regs. */
374
- nregs += 16;
375
- if (reg < nregs) {
376
- uint64_t *q = aa32_vfp_qreg(env, reg - 32);
377
- return gdb_get_reg128(buf, q[0], q[1]);
378
- }
379
- }
380
- switch (reg - nregs) {
381
- case 0:
382
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
383
- case 1:
384
- return gdb_get_reg32(buf, vfp_get_fpscr(env));
385
- case 2:
386
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
387
- }
388
- return 0;
389
-}
390
-
391
-static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
392
-{
393
- ARMCPU *cpu = env_archcpu(env);
394
- int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;
395
-
396
- if (reg < nregs) {
397
- *aa32_vfp_dreg(env, reg) = ldq_le_p(buf);
398
- return 8;
399
- }
400
- if (arm_feature(env, ARM_FEATURE_NEON)) {
401
- nregs += 16;
402
- if (reg < nregs) {
403
- uint64_t *q = aa32_vfp_qreg(env, reg - 32);
404
- q[0] = ldq_le_p(buf);
405
- q[1] = ldq_le_p(buf + 8);
406
- return 16;
407
- }
408
- }
409
- switch (reg - nregs) {
410
- case 0:
411
- env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
412
- return 4;
413
- case 1:
414
- vfp_set_fpscr(env, ldl_p(buf));
415
- return 4;
416
- case 2:
417
- env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
418
- return 4;
419
- }
420
- return 0;
421
-}
422
-
423
-static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
424
-{
425
- switch (reg) {
426
- case 0 ... 31:
427
- {
428
- /* 128 bit FP register - quads are in LE order */
429
- uint64_t *q = aa64_vfp_qreg(env, reg);
430
- return gdb_get_reg128(buf, q[1], q[0]);
431
- }
432
- case 32:
433
- /* FPSR */
434
- return gdb_get_reg32(buf, vfp_get_fpsr(env));
435
- case 33:
436
- /* FPCR */
437
- return gdb_get_reg32(buf, vfp_get_fpcr(env));
438
- default:
439
- return 0;
440
- }
441
-}
442
-
443
-static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
444
-{
445
- switch (reg) {
446
- case 0 ... 31:
447
- /* 128 bit FP register */
448
- {
449
- uint64_t *q = aa64_vfp_qreg(env, reg);
450
- q[0] = ldq_le_p(buf);
451
- q[1] = ldq_le_p(buf + 8);
452
- return 16;
453
- }
454
- case 32:
455
- /* FPSR */
456
- vfp_set_fpsr(env, ldl_p(buf));
457
- return 4;
458
- case 33:
459
- /* FPCR */
460
- vfp_set_fpcr(env, ldl_p(buf));
461
- return 4;
462
- default:
463
- return 0;
464
- }
465
-}
466
-
467
static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
468
{
469
assert(ri->fieldoffset);
470
@@ -XXX,XX +XXX,XX @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
471
}
42
}
472
}
43
473
44
-static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
474
-/**
45
+uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
475
- * arm_get/set_gdb_*: get/set a gdb register
476
- * @env: the CPU state
477
- * @buf: a buffer to copy to/from
478
- * @reg: register number (offset from start of group)
479
- *
480
- * We return the number of bytes copied
481
- */
482
-
483
-static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
484
-{
485
- ARMCPU *cpu = env_archcpu(env);
486
- const ARMCPRegInfo *ri;
487
- uint32_t key;
488
-
489
- key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];
490
- ri = get_arm_cp_reginfo(cpu->cp_regs, key);
491
- if (ri) {
492
- if (cpreg_field_is_64bit(ri)) {
493
- return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri));
494
- } else {
495
- return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri));
496
- }
497
- }
498
- return 0;
499
-}
500
-
501
-static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
502
-{
503
- return 0;
504
-}
505
-
506
-#ifdef TARGET_AARCH64
507
-static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
508
-{
509
- ARMCPU *cpu = env_archcpu(env);
510
-
511
- switch (reg) {
512
- /* The first 32 registers are the zregs */
513
- case 0 ... 31:
514
- {
515
- int vq, len = 0;
516
- for (vq = 0; vq < cpu->sve_max_vq; vq++) {
517
- len += gdb_get_reg128(buf,
518
- env->vfp.zregs[reg].d[vq * 2 + 1],
519
- env->vfp.zregs[reg].d[vq * 2]);
520
- }
521
- return len;
522
- }
523
- case 32:
524
- return gdb_get_reg32(buf, vfp_get_fpsr(env));
525
- case 33:
526
- return gdb_get_reg32(buf, vfp_get_fpcr(env));
527
- /* then 16 predicates and the ffr */
528
- case 34 ... 50:
529
- {
530
- int preg = reg - 34;
531
- int vq, len = 0;
532
- for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
533
- len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
534
- }
535
- return len;
536
- }
537
- case 51:
538
- {
539
- /*
540
- * We report in Vector Granules (VG) which is 64bit in a Z reg
541
- * while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
542
- */
543
- int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
544
- return gdb_get_reg64(buf, vq * 2);
545
- }
546
- default:
547
- /* gdbstub asked for something out our range */
548
- qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
549
- break;
550
- }
551
-
552
- return 0;
553
-}
554
-
555
-static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
556
-{
557
- ARMCPU *cpu = env_archcpu(env);
558
-
559
- /* The first 32 registers are the zregs */
560
- switch (reg) {
561
- /* The first 32 registers are the zregs */
562
- case 0 ... 31:
563
- {
564
- int vq, len = 0;
565
- uint64_t *p = (uint64_t *) buf;
566
- for (vq = 0; vq < cpu->sve_max_vq; vq++) {
567
- env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
568
- env->vfp.zregs[reg].d[vq * 2] = *p++;
569
- len += 16;
570
- }
571
- return len;
572
- }
573
- case 32:
574
- vfp_set_fpsr(env, *(uint32_t *)buf);
575
- return 4;
576
- case 33:
577
- vfp_set_fpcr(env, *(uint32_t *)buf);
578
- return 4;
579
- case 34 ... 50:
580
- {
581
- int preg = reg - 34;
582
- int vq, len = 0;
583
- uint64_t *p = (uint64_t *) buf;
584
- for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
585
- env->vfp.pregs[preg].p[vq / 4] = *p++;
586
- len += 8;
587
- }
588
- return len;
589
- }
590
- case 51:
591
- /* cannot set vg via gdbstub */
592
- return 0;
593
- default:
594
- /* gdbstub asked for something out our range */
595
- break;
596
- }
597
-
598
- return 0;
599
-}
600
-#endif /* TARGET_AARCH64 */
601
-
602
static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
46
{
603
{
47
uint32_t end_len;
604
/* Return true if the regdef would cause an assertion if you called
48
605
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
49
@@ -XXX,XX +XXX,XX @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
606
#endif
50
zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
51
}
52
53
- return sve_zcr_get_valid_len(cpu, zcr_len);
54
+ return aarch64_sve_zcr_get_valid_len(cpu, zcr_len);
55
}
607
}
56
608
57
static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
609
-void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
610
-{
611
- CPUState *cs = CPU(cpu);
612
- CPUARMState *env = &cpu->env;
613
-
614
- if (arm_feature(env, ARM_FEATURE_AARCH64)) {
615
- /*
616
- * The lower part of each SVE register aliases to the FPU
617
- * registers so we don't need to include both.
618
- */
619
-#ifdef TARGET_AARCH64
620
- if (isar_feature_aa64_sve(&cpu->isar)) {
621
- gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
622
- arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
623
- "sve-registers.xml", 0);
624
- } else
625
-#endif
626
- {
627
- gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
628
- aarch64_fpu_gdb_set_reg,
629
- 34, "aarch64-fpu.xml", 0);
630
- }
631
- } else if (arm_feature(env, ARM_FEATURE_NEON)) {
632
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
633
- 51, "arm-neon.xml", 0);
634
- } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
635
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
636
- 35, "arm-vfp3.xml", 0);
637
- } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
638
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
639
- 19, "arm-vfp.xml", 0);
640
- }
641
- gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
642
- arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
643
- "system-registers.xml", 0);
644
-
645
-}
646
-
647
/* Sort alphabetically by type name, except for "any". */
648
static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
649
{
58
--
650
--
59
2.20.1
651
2.20.1
60
652
61
653
diff view generated by jsdifflib
[PULL 03/14] target/arm: Enforce that M-profile SP low 2 bits are always zero
[PULL 15/22] target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML
1
For M-profile, unlike A-profile, the low 2 bits of SP are defined to be
1
Currently we send VFP XML which includes D0..D15 or D0..D31, plus
2
RES0H, which is to say that they must be hardwired to zero so that
2
FPSID, FPSCR and FPEXC. The upstream GDB tolerates this, but its
3
guest attempts to write non-zero values to them are ignored.
3
definition of this XML feature does not include FPSID or FPEXC. In
4
4
particular, for M-profile cores there are no FPSID or FPEXC
5
Implement this behaviour by masking out the low bits:
5
registers, so advertising those is wrong.
6
* for writes to r13 by the gdbstub
6
7
* for writes to any of the various flavours of SP via MSR
7
Move FPSID and FPEXC into their own bit of XML which we only send for
8
* for writes to r13 via store_reg() in generated code
8
A and R profile cores. This brings our definition of the XML
9
9
org.gnu.gdb.arm.vfp feature into line with GDB's own (at least for
10
Note that all the direct uses of cpu_R[] in translate.c are in places
10
non-Neon cores...) and means we don't claim to have FPSID and FPEXC
11
where the register is definitely not r13 (usually because that has
11
on M-profile.
12
been checked for as an UNDEFINED or UNPREDICTABLE case and handled as
12
13
UNDEF).
13
(It seems unlikely to me that any gdbstub users really care about
14
14
being able to look at FPEXC and FPSID; but we've supplied them to gdb
15
All the other writes to regs[13] in C code are either:
15
for a decade and it's not hard to keep doing so.)
16
* A-profile only code
17
* writes of values we can guarantee to be aligned, such as
18
- writes of previous-SP-value plus or minus a 4-aligned constant
19
- writes of the value in an SP limit register (which we already
20
enforce to be aligned)
21
16
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
24
Message-id: 20210723162146.5167-2-peter.maydell@linaro.org
19
Message-id: 20210921162901.17508-5-peter.maydell@linaro.org
25
---
20
---
26
target/arm/gdbstub.c | 4 ++++
21
configs/targets/aarch64-softmmu.mak | 2 +-
27
target/arm/m_helper.c | 14 ++++++++------
22
configs/targets/arm-linux-user.mak | 2 +-
28
target/arm/translate.c | 3 +++
23
configs/targets/arm-softmmu.mak | 2 +-
29
3 files changed, 15 insertions(+), 6 deletions(-)
24
configs/targets/armeb-linux-user.mak | 2 +-
30
25
target/arm/gdbstub.c | 56 ++++++++++++++++++++--------
26
gdb-xml/arm-neon.xml | 2 -
27
gdb-xml/arm-vfp-sysregs.xml | 17 +++++++++
28
gdb-xml/arm-vfp.xml | 2 -
29
gdb-xml/arm-vfp3.xml | 2 -
30
9 files changed, 61 insertions(+), 26 deletions(-)
31
create mode 100644 gdb-xml/arm-vfp-sysregs.xml
32
33
diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
34
index XXXXXXX..XXXXXXX 100644
35
--- a/configs/targets/aarch64-softmmu.mak
36
+++ b/configs/targets/aarch64-softmmu.mak
37
@@ -XXX,XX +XXX,XX @@
38
TARGET_ARCH=aarch64
39
TARGET_BASE_ARCH=arm
40
TARGET_SUPPORTS_MTTCG=y
41
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
42
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
43
TARGET_NEED_FDT=y
44
diff --git a/configs/targets/arm-linux-user.mak b/configs/targets/arm-linux-user.mak
45
index XXXXXXX..XXXXXXX 100644
46
--- a/configs/targets/arm-linux-user.mak
47
+++ b/configs/targets/arm-linux-user.mak
48
@@ -XXX,XX +XXX,XX @@
49
TARGET_ARCH=arm
50
TARGET_SYSTBL_ABI=common,oabi
51
TARGET_SYSTBL=syscall.tbl
52
-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
53
+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
54
TARGET_HAS_BFLT=y
55
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
56
diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.mak
57
index XXXXXXX..XXXXXXX 100644
58
--- a/configs/targets/arm-softmmu.mak
59
+++ b/configs/targets/arm-softmmu.mak
60
@@ -XXX,XX +XXX,XX @@
61
TARGET_ARCH=arm
62
TARGET_SUPPORTS_MTTCG=y
63
-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
64
+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
65
TARGET_NEED_FDT=y
66
diff --git a/configs/targets/armeb-linux-user.mak b/configs/targets/armeb-linux-user.mak
67
index XXXXXXX..XXXXXXX 100644
68
--- a/configs/targets/armeb-linux-user.mak
69
+++ b/configs/targets/armeb-linux-user.mak
70
@@ -XXX,XX +XXX,XX @@ TARGET_ARCH=arm
71
TARGET_SYSTBL_ABI=common,oabi
72
TARGET_SYSTBL=syscall.tbl
73
TARGET_WORDS_BIGENDIAN=y
74
-TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
75
+TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
76
TARGET_HAS_BFLT=y
77
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
31
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
78
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
32
index XXXXXXX..XXXXXXX 100644
79
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/gdbstub.c
80
--- a/target/arm/gdbstub.c
34
+++ b/target/arm/gdbstub.c
81
+++ b/target/arm/gdbstub.c
35
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
82
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
36
83
}
37
if (n < 16) {
84
switch (reg - nregs) {
38
/* Core integer register. */
85
case 0:
39
+ if (n == 13 && arm_feature(env, ARM_FEATURE_M)) {
86
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
40
+ /* M profile SP low bits are always 0 */
87
- case 1:
41
+ tmp &= ~3;
88
return gdb_get_reg32(buf, vfp_get_fpscr(env));
89
- case 2:
90
- return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
91
}
92
return 0;
93
}
94
@@ -XXX,XX +XXX,XX @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
95
}
96
}
97
switch (reg - nregs) {
98
+ case 0:
99
+ vfp_set_fpscr(env, ldl_p(buf));
100
+ return 4;
101
+ }
102
+ return 0;
103
+}
104
+
105
+static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)
106
+{
107
+ switch (reg) {
108
+ case 0:
109
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);
110
+ case 1:
111
+ return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]);
112
+ }
113
+ return 0;
114
+}
115
+
116
+static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
117
+{
118
+ switch (reg) {
119
case 0:
120
env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);
121
return 4;
122
case 1:
123
- vfp_set_fpscr(env, ldl_p(buf));
124
- return 4;
125
- case 2:
126
env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30);
127
return 4;
128
}
129
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
130
34, "aarch64-fpu.xml", 0);
131
}
132
#endif
133
- } else if (arm_feature(env, ARM_FEATURE_NEON)) {
134
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
135
- 51, "arm-neon.xml", 0);
136
- } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
137
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
138
- 35, "arm-vfp3.xml", 0);
139
- } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
140
- gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
141
- 19, "arm-vfp.xml", 0);
142
+ } else {
143
+ if (arm_feature(env, ARM_FEATURE_NEON)) {
144
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
145
+ 49, "arm-neon.xml", 0);
146
+ } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
147
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
148
+ 33, "arm-vfp3.xml", 0);
149
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
150
+ gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
151
+ 17, "arm-vfp.xml", 0);
42
+ }
152
+ }
43
env->regs[n] = tmp;
153
+ if (!arm_feature(env, ARM_FEATURE_M)) {
44
return 4;
154
+ /*
45
}
155
+ * A and R profile have FP sysregs FPEXC and FPSID that we
46
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
156
+ * expose to gdb.
47
index XXXXXXX..XXXXXXX 100644
157
+ */
48
--- a/target/arm/m_helper.c
158
+ gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_sysreg,
49
+++ b/target/arm/m_helper.c
159
+ 2, "arm-vfp-sysregs.xml", 0);
50
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
160
+ }
51
if (!env->v7m.secure) {
161
}
52
return;
162
gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
53
}
163
arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
54
- env->v7m.other_ss_msp = val;
164
diff --git a/gdb-xml/arm-neon.xml b/gdb-xml/arm-neon.xml
55
+ env->v7m.other_ss_msp = val & ~3;
165
index XXXXXXX..XXXXXXX 100644
56
return;
166
--- a/gdb-xml/arm-neon.xml
57
case 0x89: /* PSP_NS */
167
+++ b/gdb-xml/arm-neon.xml
58
if (!env->v7m.secure) {
168
@@ -XXX,XX +XXX,XX @@
59
return;
169
<reg name="q14" bitsize="128" type="neon_q"/>
60
}
170
<reg name="q15" bitsize="128" type="neon_q"/>
61
- env->v7m.other_ss_psp = val;
171
62
+ env->v7m.other_ss_psp = val & ~3;
172
- <reg name="fpsid" bitsize="32" type="int" group="float"/>
63
return;
173
<reg name="fpscr" bitsize="32" type="int" group="float"/>
64
case 0x8a: /* MSPLIM_NS */
174
- <reg name="fpexc" bitsize="32" type="int" group="float"/>
65
if (!env->v7m.secure) {
175
</feature>
66
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
176
diff --git a/gdb-xml/arm-vfp-sysregs.xml b/gdb-xml/arm-vfp-sysregs.xml
67
177
new file mode 100644
68
limit = is_psp ? env->v7m.psplim[false] : env->v7m.msplim[false];
178
index XXXXXXX..XXXXXXX
69
179
--- /dev/null
70
+ val &= ~0x3;
180
+++ b/gdb-xml/arm-vfp-sysregs.xml
71
+
181
@@ -XXX,XX +XXX,XX @@
72
if (val < limit) {
182
+<?xml version="1.0"?>
73
raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC());
183
+<!-- Copyright (C) 2021 Linaro Ltd.
74
}
184
+
75
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
185
+ Copying and distribution of this file, with or without modification,
76
break;
186
+ are permitted in any medium without royalty provided the copyright
77
case 8: /* MSP */
187
+ notice and this notice are preserved.
78
if (v7m_using_psp(env)) {
188
+
79
- env->v7m.other_sp = val;
189
+ These are A/R profile VFP system registers. Debugger users probably
80
+ env->v7m.other_sp = val & ~3;
190
+ don't really care about these, but because we used to (incorrectly)
81
} else {
191
+ provide them to gdb in the org.gnu.gdb.arm.vfp XML we continue
82
- env->regs[13] = val;
192
+ to do so via this separate XML.
83
+ env->regs[13] = val & ~3;
193
+ -->
84
}
194
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
85
break;
195
+<feature name="org.qemu.gdb.arm.vfp-sysregs">
86
case 9: /* PSP */
196
+ <reg name="fpsid" bitsize="32" type="int" group="float"/>
87
if (v7m_using_psp(env)) {
197
+ <reg name="fpexc" bitsize="32" type="int" group="float"/>
88
- env->regs[13] = val;
198
+</feature>
89
+ env->regs[13] = val & ~3;
199
diff --git a/gdb-xml/arm-vfp.xml b/gdb-xml/arm-vfp.xml
90
} else {
200
index XXXXXXX..XXXXXXX 100644
91
- env->v7m.other_sp = val;
201
--- a/gdb-xml/arm-vfp.xml
92
+ env->v7m.other_sp = val & ~3;
202
+++ b/gdb-xml/arm-vfp.xml
93
}
203
@@ -XXX,XX +XXX,XX @@
94
break;
204
<reg name="d14" bitsize="64" type="float"/>
95
case 10: /* MSPLIM */
205
<reg name="d15" bitsize="64" type="float"/>
96
diff --git a/target/arm/translate.c b/target/arm/translate.c
206
97
index XXXXXXX..XXXXXXX 100644
207
- <reg name="fpsid" bitsize="32" type="int" group="float"/>
98
--- a/target/arm/translate.c
208
<reg name="fpscr" bitsize="32" type="int" group="float"/>
99
+++ b/target/arm/translate.c
209
- <reg name="fpexc" bitsize="32" type="int" group="float"/>
100
@@ -XXX,XX +XXX,XX @@ void store_reg(DisasContext *s, int reg, TCGv_i32 var)
210
</feature>
101
*/
211
diff --git a/gdb-xml/arm-vfp3.xml b/gdb-xml/arm-vfp3.xml
102
tcg_gen_andi_i32(var, var, s->thumb ? ~1 : ~3);
212
index XXXXXXX..XXXXXXX 100644
103
s->base.is_jmp = DISAS_JUMP;
213
--- a/gdb-xml/arm-vfp3.xml
104
+ } else if (reg == 13 && arm_dc_feature(s, ARM_FEATURE_M)) {
214
+++ b/gdb-xml/arm-vfp3.xml
105
+ /* For M-profile SP bits [1:0] are always zero */
215
@@ -XXX,XX +XXX,XX @@
106
+ tcg_gen_andi_i32(var, var, ~3);
216
<reg name="d30" bitsize="64" type="float"/>
107
}
217
<reg name="d31" bitsize="64" type="float"/>
108
tcg_gen_mov_i32(cpu_R[reg], var);
218
109
tcg_temp_free_i32(var);
219
- <reg name="fpsid" bitsize="32" type="int" group="float"/>
220
<reg name="fpscr" bitsize="32" type="int" group="float"/>
221
- <reg name="fpexc" bitsize="32" type="int" group="float"/>
222
</feature>
110
--
223
--
111
2.20.1
224
2.20.1
112
225
113
226
diff view generated by jsdifflib
New patch
[PULL 16/22] scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named()
1
1
The function scsi_bus_new() creates a new SCSI bus; callers can
2
either pass in a name argument to specify the name of the new bus, or
3
they can pass in NULL to allow the bus to be given an automatically
4
generated unique name. Almost all callers want to use the
5
autogenerated name; the only exception is the virtio-scsi device.
6
7
Taking a name argument that should almost always be NULL is an
8
easy-to-misuse API design -- it encourages callers to think perhaps
9
they should pass in some standard name like "scsi" or "scsi-bus". We
10
don't do this anywhere for SCSI, but we do (incorrectly) do it for
11
other bus types such as i2c.
12
13
The function name also implies that it will return a newly allocated
14
object, when it in fact does in-place allocation. We more commonly
15
name such functions foo_init(), with foo_new() being the
16
allocate-and-return variant.
17
18
Replace all the scsi_bus_new() callsites with either:
19
* scsi_bus_init() for the usual case where the caller wants
20
an autogenerated bus name
21
* scsi_bus_init_named() for the rare case where the caller
22
needs to specify the bus name
23
24
and document that for the _named() version it's then the caller's
25
responsibility to think about uniqueness of bus names.
26
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
29
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
30
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
31
Message-id: 20210923121153.23754-2-peter.maydell@linaro.org
32
---
33
include/hw/scsi/scsi.h | 30 ++++++++++++++++++++++++++++--
34
hw/scsi/esp-pci.c | 2 +-
35
hw/scsi/esp.c | 2 +-
36
hw/scsi/lsi53c895a.c | 2 +-
37
hw/scsi/megasas.c | 3 +--
38
hw/scsi/mptsas.c | 2 +-
39
hw/scsi/scsi-bus.c | 4 ++--
40
hw/scsi/spapr_vscsi.c | 3 +--
41
hw/scsi/virtio-scsi.c | 4 ++--
42
hw/scsi/vmw_pvscsi.c | 3 +--
43
hw/usb/dev-storage-bot.c | 3 +--
44
hw/usb/dev-storage-classic.c | 4 ++--
45
hw/usb/dev-uas.c | 3 +--
46
13 files changed, 43 insertions(+), 22 deletions(-)
47
48
diff --git a/include/hw/scsi/scsi.h b/include/hw/scsi/scsi.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/scsi/scsi.h
51
+++ b/include/hw/scsi/scsi.h
52
@@ -XXX,XX +XXX,XX @@ struct SCSIBus {
53
const SCSIBusInfo *info;
54
};
55
56
-void scsi_bus_new(SCSIBus *bus, size_t bus_size, DeviceState *host,
57
- const SCSIBusInfo *info, const char *bus_name);
58
+/**
59
+ * scsi_bus_init_named: Initialize a SCSI bus with the specified name
60
+ * @bus: SCSIBus object to initialize
61
+ * @bus_size: size of @bus object
62
+ * @host: Device which owns the bus (generally the SCSI controller)
63
+ * @info: structure defining callbacks etc for the controller
64
+ * @bus_name: Name to use for this bus
65
+ *
66
+ * This in-place initializes @bus as a new SCSI bus with a name
67
+ * provided by the caller. It is the caller's responsibility to make
68
+ * sure that name does not clash with the name of any other bus in the
69
+ * system. Unless you need the new bus to have a specific name, you
70
+ * should use scsi_bus_new() instead.
71
+ */
72
+void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host,
73
+ const SCSIBusInfo *info, const char *bus_name);
74
+
75
+/**
76
+ * scsi_bus_init: Initialize a SCSI bus
77
+ *
78
+ * This in-place-initializes @bus as a new SCSI bus and gives it
79
+ * an automatically generated unique name.
80
+ */
81
+static inline void scsi_bus_init(SCSIBus *bus, size_t bus_size,
82
+ DeviceState *host, const SCSIBusInfo *info)
83
+{
84
+ scsi_bus_init_named(bus, bus_size, host, info, NULL);
85
+}
86
87
static inline SCSIBus *scsi_bus_from_device(SCSIDevice *d)
88
{
89
diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/hw/scsi/esp-pci.c
92
+++ b/hw/scsi/esp-pci.c
93
@@ -XXX,XX +XXX,XX @@ static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp)
94
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
95
s->irq = pci_allocate_irq(dev);
96
97
- scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL);
98
+ scsi_bus_init(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info);
99
}
100
101
static void esp_pci_scsi_exit(PCIDevice *d)
102
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/hw/scsi/esp.c
105
+++ b/hw/scsi/esp.c
106
@@ -XXX,XX +XXX,XX @@ static void sysbus_esp_realize(DeviceState *dev, Error **errp)
107
108
qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
109
110
- scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
111
+ scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info);
112
}
113
114
static void sysbus_esp_hard_reset(DeviceState *dev)
115
diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
116
index XXXXXXX..XXXXXXX 100644
117
--- a/hw/scsi/lsi53c895a.c
118
+++ b/hw/scsi/lsi53c895a.c
119
@@ -XXX,XX +XXX,XX @@ static void lsi_scsi_realize(PCIDevice *dev, Error **errp)
120
pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_io);
121
QTAILQ_INIT(&s->queue);
122
123
- scsi_bus_new(&s->bus, sizeof(s->bus), d, &lsi_scsi_info, NULL);
124
+ scsi_bus_init(&s->bus, sizeof(s->bus), d, &lsi_scsi_info);
125
}
126
127
static void lsi_scsi_exit(PCIDevice *dev)
128
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/hw/scsi/megasas.c
131
+++ b/hw/scsi/megasas.c
132
@@ -XXX,XX +XXX,XX @@ static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
133
s->frames[i].state = s;
134
}
135
136
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
137
- &megasas_scsi_info, NULL);
138
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &megasas_scsi_info);
139
}
140
141
static Property megasas_properties_gen1[] = {
142
diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c
143
index XXXXXXX..XXXXXXX 100644
144
--- a/hw/scsi/mptsas.c
145
+++ b/hw/scsi/mptsas.c
146
@@ -XXX,XX +XXX,XX @@ static void mptsas_scsi_realize(PCIDevice *dev, Error **errp)
147
148
s->request_bh = qemu_bh_new(mptsas_fetch_requests, s);
149
150
- scsi_bus_new(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info, NULL);
151
+ scsi_bus_init(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info);
152
}
153
154
static void mptsas_scsi_uninit(PCIDevice *dev)
155
diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c
156
index XXXXXXX..XXXXXXX 100644
157
--- a/hw/scsi/scsi-bus.c
158
+++ b/hw/scsi/scsi-bus.c
159
@@ -XXX,XX +XXX,XX @@ void scsi_device_unit_attention_reported(SCSIDevice *s)
160
}
161
162
/* Create a scsi bus, and attach devices to it. */
163
-void scsi_bus_new(SCSIBus *bus, size_t bus_size, DeviceState *host,
164
- const SCSIBusInfo *info, const char *bus_name)
165
+void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host,
166
+ const SCSIBusInfo *info, const char *bus_name)
167
{
168
qbus_create_inplace(bus, bus_size, TYPE_SCSI_BUS, host, bus_name);
169
bus->busnr = next_scsi_bus++;
170
diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c
171
index XXXXXXX..XXXXXXX 100644
172
--- a/hw/scsi/spapr_vscsi.c
173
+++ b/hw/scsi/spapr_vscsi.c
174
@@ -XXX,XX +XXX,XX @@ static void spapr_vscsi_realize(SpaprVioDevice *dev, Error **errp)
175
176
dev->crq.SendFunc = vscsi_do_crq;
177
178
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
179
- &vscsi_scsi_info, NULL);
180
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &vscsi_scsi_info);
181
182
/* ibmvscsi SCSI bus does not allow hotplug. */
183
qbus_set_hotplug_handler(BUS(&s->bus), NULL);
184
diff --git a/hw/scsi/virtio-scsi.c b/hw/scsi/virtio-scsi.c
185
index XXXXXXX..XXXXXXX 100644
186
--- a/hw/scsi/virtio-scsi.c
187
+++ b/hw/scsi/virtio-scsi.c
188
@@ -XXX,XX +XXX,XX @@ static void virtio_scsi_device_realize(DeviceState *dev, Error **errp)
189
return;
190
}
191
192
- scsi_bus_new(&s->bus, sizeof(s->bus), dev,
193
- &virtio_scsi_scsi_info, vdev->bus_name);
194
+ scsi_bus_init_named(&s->bus, sizeof(s->bus), dev,
195
+ &virtio_scsi_scsi_info, vdev->bus_name);
196
/* override default SCSI bus hotplug-handler, with virtio-scsi's one */
197
qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(dev));
198
199
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/hw/scsi/vmw_pvscsi.c
202
+++ b/hw/scsi/vmw_pvscsi.c
203
@@ -XXX,XX +XXX,XX @@ pvscsi_realizefn(PCIDevice *pci_dev, Error **errp)
204
205
s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s);
206
207
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
208
- &pvscsi_scsi_info, NULL);
209
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev), &pvscsi_scsi_info);
210
/* override default SCSI bus hotplug-handler, with pvscsi's one */
211
qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(s));
212
pvscsi_reset_state(s);
213
diff --git a/hw/usb/dev-storage-bot.c b/hw/usb/dev-storage-bot.c
214
index XXXXXXX..XXXXXXX 100644
215
--- a/hw/usb/dev-storage-bot.c
216
+++ b/hw/usb/dev-storage-bot.c
217
@@ -XXX,XX +XXX,XX @@ static void usb_msd_bot_realize(USBDevice *dev, Error **errp)
218
s->dev.auto_attach = 0;
219
}
220
221
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
222
- &usb_msd_scsi_info_bot, NULL);
223
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &usb_msd_scsi_info_bot);
224
usb_msd_handle_reset(dev);
225
}
226
227
diff --git a/hw/usb/dev-storage-classic.c b/hw/usb/dev-storage-classic.c
228
index XXXXXXX..XXXXXXX 100644
229
--- a/hw/usb/dev-storage-classic.c
230
+++ b/hw/usb/dev-storage-classic.c
231
@@ -XXX,XX +XXX,XX @@ static void usb_msd_storage_realize(USBDevice *dev, Error **errp)
232
usb_desc_create_serial(dev);
233
usb_desc_init(dev);
234
dev->flags |= (1 << USB_DEV_FLAG_IS_SCSI_STORAGE);
235
- scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
236
- &usb_msd_scsi_info_storage, NULL);
237
+ scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev),
238
+ &usb_msd_scsi_info_storage);
239
scsi_dev = scsi_bus_legacy_add_drive(&s->bus, blk, 0, !!s->removable,
240
s->conf.bootindex, s->conf.share_rw,
241
s->conf.rerror, s->conf.werror,
242
diff --git a/hw/usb/dev-uas.c b/hw/usb/dev-uas.c
243
index XXXXXXX..XXXXXXX 100644
244
--- a/hw/usb/dev-uas.c
245
+++ b/hw/usb/dev-uas.c
246
@@ -XXX,XX +XXX,XX @@ static void usb_uas_realize(USBDevice *dev, Error **errp)
247
uas->status_bh = qemu_bh_new(usb_uas_send_status_bh, uas);
248
249
dev->flags |= (1 << USB_DEV_FLAG_IS_SCSI_STORAGE);
250
- scsi_bus_new(&uas->bus, sizeof(uas->bus), DEVICE(dev),
251
- &usb_uas_scsi_info, NULL);
252
+ scsi_bus_init(&uas->bus, sizeof(uas->bus), DEVICE(dev), &usb_uas_scsi_info);
253
}
254
255
static const VMStateDescription vmstate_usb_uas = {
256
--
257
2.20.1
258
259
diff view generated by jsdifflib
[PULL 08/14] hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
[PULL 17/22] ipack: Rename ipack_bus_new_inplace() to ipack_bus_init()
1
In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if
1
Rename ipack_bus_new_inplace() to ipack_bus_init(), to bring it in to
2
the register is accessed NonSecure and the highest priority pending
2
line with a "_init for in-place init, _new for allocate-and-return"
3
enabled exception (that would be returned in the VECTPENDING field)
3
convention. Drop the 'name' argument, because the only caller does
4
targets Secure, then the VECTPENDING field must read 1 rather than
4
not pass in a name. If a future caller does need to specify the bus
5
the exception number of the pending exception. Implement this.
5
name, we should create an ipack_bus_init_named() function at that
6
point.
6
7
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20210723162146.5167-7-peter.maydell@linaro.org
10
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
11
Message-id: 20210923121153.23754-3-peter.maydell@linaro.org
10
---
12
---
11
hw/intc/armv7m_nvic.c | 31 ++++++++++++++++++++++++-------
13
include/hw/ipack/ipack.h | 8 ++++----
12
1 file changed, 24 insertions(+), 7 deletions(-)
14
hw/ipack/ipack.c | 10 +++++-----
15
hw/ipack/tpci200.c | 4 ++--
16
3 files changed, 11 insertions(+), 11 deletions(-)
13
17
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
18
diff --git a/include/hw/ipack/ipack.h b/include/hw/ipack/ipack.h
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
20
--- a/include/hw/ipack/ipack.h
17
+++ b/hw/intc/armv7m_nvic.c
21
+++ b/include/hw/ipack/ipack.h
18
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque)
22
@@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ipack_device;
19
nvic_irq_update(s);
23
VMSTATE_STRUCT(_field, _state, 1, vmstate_ipack_device, IPackDevice)
24
25
IPackDevice *ipack_device_find(IPackBus *bus, int32_t slot);
26
-void ipack_bus_new_inplace(IPackBus *bus, size_t bus_size,
27
- DeviceState *parent,
28
- const char *name, uint8_t n_slots,
29
- qemu_irq_handler handler);
30
+void ipack_bus_init(IPackBus *bus, size_t bus_size,
31
+ DeviceState *parent,
32
+ uint8_t n_slots,
33
+ qemu_irq_handler handler);
34
35
#endif
36
diff --git a/hw/ipack/ipack.c b/hw/ipack/ipack.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/ipack/ipack.c
39
+++ b/hw/ipack/ipack.c
40
@@ -XXX,XX +XXX,XX @@ IPackDevice *ipack_device_find(IPackBus *bus, int32_t slot)
41
return NULL;
20
}
42
}
21
43
22
+static bool vectpending_targets_secure(NVICState *s)
44
-void ipack_bus_new_inplace(IPackBus *bus, size_t bus_size,
23
+{
45
- DeviceState *parent,
24
+ /* Return true if s->vectpending targets Secure state */
46
- const char *name, uint8_t n_slots,
25
+ if (s->vectpending_is_s_banked) {
47
- qemu_irq_handler handler)
26
+ return true;
48
+void ipack_bus_init(IPackBus *bus, size_t bus_size,
27
+ }
49
+ DeviceState *parent,
28
+ return !exc_is_banked(s->vectpending) &&
50
+ uint8_t n_slots,
29
+ exc_targets_secure(s, s->vectpending);
51
+ qemu_irq_handler handler)
30
+}
31
+
32
void armv7m_nvic_get_pending_irq_info(void *opaque,
33
int *pirq, bool *ptargets_secure)
34
{
52
{
35
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,
53
- qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, name);
36
54
+ qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, NULL);
37
assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
55
bus->n_slots = n_slots;
38
56
bus->set_irq = handler;
39
- if (s->vectpending_is_s_banked) {
57
}
40
- targets_secure = true;
58
diff --git a/hw/ipack/tpci200.c b/hw/ipack/tpci200.c
41
- } else {
59
index XXXXXXX..XXXXXXX 100644
42
- targets_secure = !exc_is_banked(pending) &&
60
--- a/hw/ipack/tpci200.c
43
- exc_targets_secure(s, pending);
61
+++ b/hw/ipack/tpci200.c
44
- }
62
@@ -XXX,XX +XXX,XX @@ static void tpci200_realize(PCIDevice *pci_dev, Error **errp)
45
+ targets_secure = vectpending_targets_secure(s);
63
pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las2);
46
64
pci_register_bar(&s->dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las3);
47
trace_nvic_get_pending_irq_info(pending, targets_secure);
65
48
66
- ipack_bus_new_inplace(&s->bus, sizeof(s->bus), DEVICE(pci_dev), NULL,
49
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
67
- N_MODULES, tpci200_set_irq);
50
/* VECTACTIVE */
68
+ ipack_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
51
val = cpu->env.v7m.exception;
69
+ N_MODULES, tpci200_set_irq);
52
/* VECTPENDING */
70
}
53
- val |= (s->vectpending & 0x1ff) << 12;
71
54
+ if (s->vectpending) {
72
static const VMStateDescription vmstate_tpci200 = {
55
+ /*
56
+ * From v8.1M VECTPENDING must read as 1 if accessed as
57
+ * NonSecure and the highest priority pending and enabled
58
+ * exception targets Secure.
59
+ */
60
+ int vp = s->vectpending;
61
+ if (!attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_V8_1M) &&
62
+ vectpending_targets_secure(s)) {
63
+ vp = 1;
64
+ }
65
+ val |= (vp & 0x1ff) << 12;
66
+ }
67
/* ISRPENDING - set if any external IRQ is pending */
68
if (nvic_isrpending(s)) {
69
val |= (1 << 22);
70
--
73
--
71
2.20.1
74
2.20.1
72
75
73
76
diff view generated by jsdifflib
[PULL 06/14] hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
[PULL 18/22] pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init()
1
The ISCR.ISRPENDING bit is set when an external interrupt is pending.
1
Rename the pci_root_bus_new_inplace() function to
2
This is true whether that external interrupt is enabled or not.
2
pci_root_bus_init(); this brings the bus type in to line with a
3
This means that we can't use 's->vectpending == 0' as a shortcut to
3
"_init for in-place init, _new for allocate-and-return" convention.
4
"ISRPENDING is zero", because s->vectpending indicates only the
4
To do this we need to rename the implementation-internal function
5
highest priority pending enabled interrupt.
5
that was using the pci_root_bus_init() name to
6
6
pci_root_bus_internal_init().
7
Remove the incorrect optimization so that if there is no pending
8
enabled interrupt we fall through to scanning through the whole
9
interrupt array.
10
7
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20210723162146.5167-5-peter.maydell@linaro.org
10
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
11
Message-id: 20210923121153.23754-4-peter.maydell@linaro.org
14
---
12
---
15
hw/intc/armv7m_nvic.c | 9 ++++-----
13
include/hw/pci/pci.h | 10 +++++-----
16
1 file changed, 4 insertions(+), 5 deletions(-)
14
hw/pci-host/raven.c | 4 ++--
15
hw/pci-host/versatile.c | 6 +++---
16
hw/pci/pci.c | 26 +++++++++++++-------------
17
4 files changed, 23 insertions(+), 23 deletions(-)
17
18
18
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
19
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
19
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/intc/armv7m_nvic.c
21
--- a/include/hw/pci/pci.h
21
+++ b/hw/intc/armv7m_nvic.c
22
+++ b/include/hw/pci/pci.h
22
@@ -XXX,XX +XXX,XX @@ static bool nvic_isrpending(NVICState *s)
23
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
24
25
bool pci_bus_is_express(PCIBus *bus);
26
27
-void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
28
- const char *name,
29
- MemoryRegion *address_space_mem,
30
- MemoryRegion *address_space_io,
31
- uint8_t devfn_min, const char *typename);
32
+void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
33
+ const char *name,
34
+ MemoryRegion *address_space_mem,
35
+ MemoryRegion *address_space_io,
36
+ uint8_t devfn_min, const char *typename);
37
PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
38
MemoryRegion *address_space_mem,
39
MemoryRegion *address_space_io,
40
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/pci-host/raven.c
43
+++ b/hw/pci-host/raven.c
44
@@ -XXX,XX +XXX,XX @@ static void raven_pcihost_initfn(Object *obj)
45
memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR,
46
&s->pci_io_non_contiguous, 1);
47
memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
48
- pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
49
- &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
50
+ pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
51
+ &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
52
53
/* Bus master address space */
54
memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB);
55
diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/pci-host/versatile.c
58
+++ b/hw/pci-host/versatile.c
59
@@ -XXX,XX +XXX,XX @@ static void pci_vpb_realize(DeviceState *dev, Error **errp)
60
memory_region_init(&s->pci_io_space, OBJECT(s), "pci_io", 4 * GiB);
61
memory_region_init(&s->pci_mem_space, OBJECT(s), "pci_mem", 4 * GiB);
62
63
- pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), dev, "pci",
64
- &s->pci_mem_space, &s->pci_io_space,
65
- PCI_DEVFN(11, 0), TYPE_PCI_BUS);
66
+ pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), dev, "pci",
67
+ &s->pci_mem_space, &s->pci_io_space,
68
+ PCI_DEVFN(11, 0), TYPE_PCI_BUS);
69
h->bus = &s->pci_bus;
70
71
object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_VERSATILE_PCI_HOST);
72
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/pci/pci.c
75
+++ b/hw/pci/pci.c
76
@@ -XXX,XX +XXX,XX @@ bool pci_bus_bypass_iommu(PCIBus *bus)
77
return host_bridge->bypass_iommu;
78
}
79
80
-static void pci_root_bus_init(PCIBus *bus, DeviceState *parent,
81
- MemoryRegion *address_space_mem,
82
- MemoryRegion *address_space_io,
83
- uint8_t devfn_min)
84
+static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent,
85
+ MemoryRegion *address_space_mem,
86
+ MemoryRegion *address_space_io,
87
+ uint8_t devfn_min)
23
{
88
{
24
int irq;
89
assert(PCI_FUNC(devfn_min) == 0);
25
90
bus->devfn_min = devfn_min;
26
- /* We can shortcut if the highest priority pending interrupt
91
@@ -XXX,XX +XXX,XX @@ bool pci_bus_is_express(PCIBus *bus)
27
- * happens to be external or if there is nothing pending.
92
return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
28
+ /*
93
}
29
+ * We can shortcut if the highest priority pending interrupt
94
30
+ * happens to be external; if not we need to check the whole
95
-void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
31
+ * vectors[] array.
96
- const char *name,
32
*/
97
- MemoryRegion *address_space_mem,
33
if (s->vectpending > NVIC_FIRST_IRQ) {
98
- MemoryRegion *address_space_io,
34
return true;
99
- uint8_t devfn_min, const char *typename)
35
}
100
+void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
36
- if (s->vectpending == 0) {
101
+ const char *name,
37
- return false;
102
+ MemoryRegion *address_space_mem,
38
- }
103
+ MemoryRegion *address_space_io,
39
104
+ uint8_t devfn_min, const char *typename)
40
for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) {
105
{
41
if (s->vectors[irq].pending) {
106
qbus_create_inplace(bus, bus_size, typename, parent, name);
107
- pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
108
- devfn_min);
109
+ pci_root_bus_internal_init(bus, parent, address_space_mem,
110
+ address_space_io, devfn_min);
111
}
112
113
PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
114
@@ -XXX,XX +XXX,XX @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
115
PCIBus *bus;
116
117
bus = PCI_BUS(qbus_create(typename, parent, name));
118
- pci_root_bus_init(bus, parent, address_space_mem, address_space_io,
119
- devfn_min);
120
+ pci_root_bus_internal_init(bus, parent, address_space_mem,
121
+ address_space_io, devfn_min);
122
return bus;
123
}
124
42
--
125
--
43
2.20.1
126
2.20.1
44
127
45
128
diff view generated by jsdifflib
[PULL 05/14] target/arm: Report M-profile alignment faults correctly to the guest
[PULL 19/22] qbus: Rename qbus_create_inplace() to qbus_init()
1
For M-profile, we weren't reporting alignment faults triggered by the
1
Rename qbus_create_inplace() to qbus_init(); this is more in line
2
generic TCG code correctly to the guest. These get passed into
2
with our usual naming convention for functions that in-place
3
arm_v7m_cpu_do_interrupt() as an EXCP_DATA_ABORT with an A-profile
3
initialize objects.
4
style exception.fsr value of 1. We didn't check for this, and so
5
they fell through into the default of "assume this is an MPU fault"
6
and were reported to the guest as a data access violation MPU fault.
7
8
Report these alignment faults as UsageFaults which set the UNALIGNED
9
bit in the UFSR.
10
4
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20210723162146.5167-4-peter.maydell@linaro.org
7
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
8
Message-id: 20210923121153.23754-5-peter.maydell@linaro.org
14
---
9
---
15
target/arm/m_helper.c | 8 ++++++++
10
include/hw/qdev-core.h | 4 ++--
16
1 file changed, 8 insertions(+)
11
hw/audio/intel-hda.c | 2 +-
12
hw/block/fdc.c | 2 +-
13
hw/block/swim.c | 3 +--
14
hw/char/virtio-serial-bus.c | 4 ++--
15
hw/core/bus.c | 11 ++++++-----
16
hw/core/sysbus.c | 10 ++++++----
17
hw/gpio/bcm2835_gpio.c | 3 +--
18
hw/ide/qdev.c | 2 +-
19
hw/ipack/ipack.c | 2 +-
20
hw/misc/mac_via.c | 4 ++--
21
hw/misc/macio/cuda.c | 4 ++--
22
hw/misc/macio/macio.c | 4 ++--
23
hw/misc/macio/pmu.c | 4 ++--
24
hw/nubus/nubus-bridge.c | 2 +-
25
hw/nvme/ctrl.c | 4 ++--
26
hw/nvme/subsys.c | 3 +--
27
hw/pci/pci.c | 2 +-
28
hw/pci/pci_bridge.c | 4 ++--
29
hw/s390x/event-facility.c | 4 ++--
30
hw/s390x/virtio-ccw.c | 3 +--
31
hw/scsi/scsi-bus.c | 2 +-
32
hw/sd/allwinner-sdhost.c | 4 ++--
33
hw/sd/bcm2835_sdhost.c | 4 ++--
34
hw/sd/pl181.c | 3 +--
35
hw/sd/pxa2xx_mmci.c | 4 ++--
36
hw/sd/sdhci.c | 3 +--
37
hw/sd/ssi-sd.c | 3 +--
38
hw/usb/bus.c | 2 +-
39
hw/usb/dev-smartcard-reader.c | 3 +--
40
hw/virtio/virtio-mmio.c | 3 +--
41
hw/virtio/virtio-pci.c | 3 +--
42
32 files changed, 54 insertions(+), 61 deletions(-)
17
43
18
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
44
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
19
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/m_helper.c
46
--- a/include/hw/qdev-core.h
21
+++ b/target/arm/m_helper.c
47
+++ b/include/hw/qdev-core.h
22
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
48
@@ -XXX,XX +XXX,XX @@ DeviceState *qdev_find_recursive(BusState *bus, const char *id);
23
env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK;
49
typedef int (qbus_walkerfn)(BusState *bus, void *opaque);
24
break;
50
typedef int (qdev_walkerfn)(DeviceState *dev, void *opaque);
25
case EXCP_UNALIGNED:
51
26
+ /* Unaligned faults reported by M-profile aware code */
52
-void qbus_create_inplace(void *bus, size_t size, const char *typename,
27
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
53
- DeviceState *parent, const char *name);
28
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;
54
+void qbus_init(void *bus, size_t size, const char *typename,
29
break;
55
+ DeviceState *parent, const char *name);
30
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
56
BusState *qbus_create(const char *typename, DeviceState *parent, const char *name);
31
}
57
bool qbus_realize(BusState *bus, Error **errp);
32
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
58
void qbus_unrealize(BusState *bus);
33
break;
59
diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
34
+ case 0x1: /* Alignment fault reported by generic code */
60
index XXXXXXX..XXXXXXX 100644
35
+ qemu_log_mask(CPU_LOG_INT,
61
--- a/hw/audio/intel-hda.c
36
+ "...really UsageFault with UFSR.UNALIGNED\n");
62
+++ b/hw/audio/intel-hda.c
37
+ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;
63
@@ -XXX,XX +XXX,XX @@ void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
38
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
64
hda_codec_response_func response,
39
+ env->v7m.secure);
65
hda_codec_xfer_func xfer)
40
+ break;
66
{
41
default:
67
- qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
42
/*
68
+ qbus_init(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
43
* All other FSR values are either MPU faults or "can't happen
69
bus->response = response;
70
bus->xfer = xfer;
71
}
72
diff --git a/hw/block/fdc.c b/hw/block/fdc.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/block/fdc.c
75
+++ b/hw/block/fdc.c
76
@@ -XXX,XX +XXX,XX @@ static const TypeInfo floppy_bus_info = {
77
78
static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev)
79
{
80
- qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
81
+ qbus_init(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
82
bus->fdc = fdc;
83
}
84
85
diff --git a/hw/block/swim.c b/hw/block/swim.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/hw/block/swim.c
88
+++ b/hw/block/swim.c
89
@@ -XXX,XX +XXX,XX @@ static void sysbus_swim_realize(DeviceState *dev, Error **errp)
90
Swim *sys = SWIM(dev);
91
SWIMCtrl *swimctrl = &sys->ctrl;
92
93
- qbus_create_inplace(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev,
94
- NULL);
95
+ qbus_init(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev, NULL);
96
swimctrl->bus.ctrl = swimctrl;
97
}
98
99
diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/hw/char/virtio-serial-bus.c
102
+++ b/hw/char/virtio-serial-bus.c
103
@@ -XXX,XX +XXX,XX @@ static void virtio_serial_device_realize(DeviceState *dev, Error **errp)
104
config_size);
105
106
/* Spawn a new virtio-serial bus on which the ports will ride as devices */
107
- qbus_create_inplace(&vser->bus, sizeof(vser->bus), TYPE_VIRTIO_SERIAL_BUS,
108
- dev, vdev->bus_name);
109
+ qbus_init(&vser->bus, sizeof(vser->bus), TYPE_VIRTIO_SERIAL_BUS,
110
+ dev, vdev->bus_name);
111
qbus_set_hotplug_handler(BUS(&vser->bus), OBJECT(vser));
112
vser->bus.vser = vser;
113
QTAILQ_INIT(&vser->ports);
114
diff --git a/hw/core/bus.c b/hw/core/bus.c
115
index XXXXXXX..XXXXXXX 100644
116
--- a/hw/core/bus.c
117
+++ b/hw/core/bus.c
118
@@ -XXX,XX +XXX,XX @@ static void bus_reset_child_foreach(Object *obj, ResettableChildCallback cb,
119
}
120
}
121
122
-static void qbus_init(BusState *bus, DeviceState *parent, const char *name)
123
+static void qbus_init_internal(BusState *bus, DeviceState *parent,
124
+ const char *name)
125
{
126
const char *typename = object_get_typename(OBJECT(bus));
127
BusClass *bc;
128
@@ -XXX,XX +XXX,XX @@ static void bus_unparent(Object *obj)
129
bus->parent = NULL;
130
}
131
132
-void qbus_create_inplace(void *bus, size_t size, const char *typename,
133
- DeviceState *parent, const char *name)
134
+void qbus_init(void *bus, size_t size, const char *typename,
135
+ DeviceState *parent, const char *name)
136
{
137
object_initialize(bus, size, typename);
138
- qbus_init(bus, parent, name);
139
+ qbus_init_internal(bus, parent, name);
140
}
141
142
BusState *qbus_create(const char *typename, DeviceState *parent, const char *name)
143
@@ -XXX,XX +XXX,XX @@ BusState *qbus_create(const char *typename, DeviceState *parent, const char *nam
144
BusState *bus;
145
146
bus = BUS(object_new(typename));
147
- qbus_init(bus, parent, name);
148
+ qbus_init_internal(bus, parent, name);
149
150
return bus;
151
}
152
diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c
153
index XXXXXXX..XXXXXXX 100644
154
--- a/hw/core/sysbus.c
155
+++ b/hw/core/sysbus.c
156
@@ -XXX,XX +XXX,XX @@ static BusState *main_system_bus;
157
158
static void main_system_bus_create(void)
159
{
160
- /* assign main_system_bus before qbus_create_inplace()
161
- * in order to make "if (bus != sysbus_get_default())" work */
162
+ /*
163
+ * assign main_system_bus before qbus_init()
164
+ * in order to make "if (bus != sysbus_get_default())" work
165
+ */
166
main_system_bus = g_malloc0(system_bus_info.instance_size);
167
- qbus_create_inplace(main_system_bus, system_bus_info.instance_size,
168
- TYPE_SYSTEM_BUS, NULL, "main-system-bus");
169
+ qbus_init(main_system_bus, system_bus_info.instance_size,
170
+ TYPE_SYSTEM_BUS, NULL, "main-system-bus");
171
OBJECT(main_system_bus)->free = g_free;
172
}
173
174
diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c
175
index XXXXXXX..XXXXXXX 100644
176
--- a/hw/gpio/bcm2835_gpio.c
177
+++ b/hw/gpio/bcm2835_gpio.c
178
@@ -XXX,XX +XXX,XX @@ static void bcm2835_gpio_init(Object *obj)
179
DeviceState *dev = DEVICE(obj);
180
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
181
182
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
183
- TYPE_SD_BUS, DEVICE(s), "sd-bus");
184
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(s), "sd-bus");
185
186
memory_region_init_io(&s->iomem, obj,
187
&bcm2835_gpio_ops, s, "bcm2835_gpio", 0x1000);
188
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
189
index XXXXXXX..XXXXXXX 100644
190
--- a/hw/ide/qdev.c
191
+++ b/hw/ide/qdev.c
192
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ide_bus_info = {
193
void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
194
int bus_id, int max_units)
195
{
196
- qbus_create_inplace(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL);
197
+ qbus_init(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL);
198
idebus->bus_id = bus_id;
199
idebus->max_units = max_units;
200
}
201
diff --git a/hw/ipack/ipack.c b/hw/ipack/ipack.c
202
index XXXXXXX..XXXXXXX 100644
203
--- a/hw/ipack/ipack.c
204
+++ b/hw/ipack/ipack.c
205
@@ -XXX,XX +XXX,XX @@ void ipack_bus_init(IPackBus *bus, size_t bus_size,
206
uint8_t n_slots,
207
qemu_irq_handler handler)
208
{
209
- qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, NULL);
210
+ qbus_init(bus, bus_size, TYPE_IPACK_BUS, parent, NULL);
211
bus->n_slots = n_slots;
212
bus->set_irq = handler;
213
}
214
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
215
index XXXXXXX..XXXXXXX 100644
216
--- a/hw/misc/mac_via.c
217
+++ b/hw/misc/mac_via.c
218
@@ -XXX,XX +XXX,XX @@ static void mos6522_q800_via1_init(Object *obj)
219
sysbus_init_mmio(sbd, &v1s->via_mem);
220
221
/* ADB */
222
- qbus_create_inplace((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus),
223
- TYPE_ADB_BUS, DEVICE(v1s), "adb.0");
224
+ qbus_init((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus),
225
+ TYPE_ADB_BUS, DEVICE(v1s), "adb.0");
226
227
qdev_init_gpio_in(DEVICE(obj), via1_irq_request, VIA1_IRQ_NB);
228
}
229
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c
230
index XXXXXXX..XXXXXXX 100644
231
--- a/hw/misc/macio/cuda.c
232
+++ b/hw/misc/macio/cuda.c
233
@@ -XXX,XX +XXX,XX @@ static void cuda_init(Object *obj)
234
memory_region_init_io(&s->mem, obj, &mos6522_cuda_ops, s, "cuda", 0x2000);
235
sysbus_init_mmio(sbd, &s->mem);
236
237
- qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
238
- DEVICE(obj), "adb.0");
239
+ qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
240
+ DEVICE(obj), "adb.0");
241
}
242
243
static Property cuda_properties[] = {
244
diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
245
index XXXXXXX..XXXXXXX 100644
246
--- a/hw/misc/macio/macio.c
247
+++ b/hw/misc/macio/macio.c
248
@@ -XXX,XX +XXX,XX @@ static void macio_instance_init(Object *obj)
249
250
memory_region_init(&s->bar, obj, "macio", 0x80000);
251
252
- qbus_create_inplace(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS,
253
- DEVICE(obj), "macio.0");
254
+ qbus_init(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS,
255
+ DEVICE(obj), "macio.0");
256
257
object_initialize_child(OBJECT(s), "dbdma", &s->dbdma, TYPE_MAC_DBDMA);
258
259
diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c
260
index XXXXXXX..XXXXXXX 100644
261
--- a/hw/misc/macio/pmu.c
262
+++ b/hw/misc/macio/pmu.c
263
@@ -XXX,XX +XXX,XX @@ static void pmu_realize(DeviceState *dev, Error **errp)
264
timer_mod(s->one_sec_timer, s->one_sec_target);
265
266
if (s->has_adb) {
267
- qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
268
- dev, "adb.0");
269
+ qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
270
+ dev, "adb.0");
271
adb_register_autopoll_callback(adb_bus, pmu_adb_poll, s);
272
}
273
}
274
diff --git a/hw/nubus/nubus-bridge.c b/hw/nubus/nubus-bridge.c
275
index XXXXXXX..XXXXXXX 100644
276
--- a/hw/nubus/nubus-bridge.c
277
+++ b/hw/nubus/nubus-bridge.c
278
@@ -XXX,XX +XXX,XX @@ static void nubus_bridge_init(Object *obj)
279
NubusBridge *s = NUBUS_BRIDGE(obj);
280
NubusBus *bus = &s->bus;
281
282
- qbus_create_inplace(bus, sizeof(s->bus), TYPE_NUBUS_BUS, DEVICE(s), NULL);
283
+ qbus_init(bus, sizeof(s->bus), TYPE_NUBUS_BUS, DEVICE(s), NULL);
284
285
qdev_init_gpio_out(DEVICE(s), bus->irqs, NUBUS_IRQS);
286
}
287
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
288
index XXXXXXX..XXXXXXX 100644
289
--- a/hw/nvme/ctrl.c
290
+++ b/hw/nvme/ctrl.c
291
@@ -XXX,XX +XXX,XX @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
292
return;
293
}
294
295
- qbus_create_inplace(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS,
296
- &pci_dev->qdev, n->parent_obj.qdev.id);
297
+ qbus_init(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS,
298
+ &pci_dev->qdev, n->parent_obj.qdev.id);
299
300
nvme_init_state(n);
301
if (nvme_init_pci(n, pci_dev, errp)) {
302
diff --git a/hw/nvme/subsys.c b/hw/nvme/subsys.c
303
index XXXXXXX..XXXXXXX 100644
304
--- a/hw/nvme/subsys.c
305
+++ b/hw/nvme/subsys.c
306
@@ -XXX,XX +XXX,XX @@ static void nvme_subsys_realize(DeviceState *dev, Error **errp)
307
{
308
NvmeSubsystem *subsys = NVME_SUBSYS(dev);
309
310
- qbus_create_inplace(&subsys->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev,
311
- dev->id);
312
+ qbus_init(&subsys->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev, dev->id);
313
314
nvme_subsys_setup(subsys);
315
}
316
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
317
index XXXXXXX..XXXXXXX 100644
318
--- a/hw/pci/pci.c
319
+++ b/hw/pci/pci.c
320
@@ -XXX,XX +XXX,XX @@ void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
321
MemoryRegion *address_space_io,
322
uint8_t devfn_min, const char *typename)
323
{
324
- qbus_create_inplace(bus, bus_size, typename, parent, name);
325
+ qbus_init(bus, bus_size, typename, parent, name);
326
pci_root_bus_internal_init(bus, parent, address_space_mem,
327
address_space_io, devfn_min);
328
}
329
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
330
index XXXXXXX..XXXXXXX 100644
331
--- a/hw/pci/pci_bridge.c
332
+++ b/hw/pci/pci_bridge.c
333
@@ -XXX,XX +XXX,XX @@ void pci_bridge_initfn(PCIDevice *dev, const char *typename)
334
br->bus_name = dev->qdev.id;
335
}
336
337
- qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
338
- br->bus_name);
339
+ qbus_init(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
340
+ br->bus_name);
341
sec_bus->parent_dev = dev;
342
sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
343
sec_bus->address_space_mem = &br->address_space_mem;
344
diff --git a/hw/s390x/event-facility.c b/hw/s390x/event-facility.c
345
index XXXXXXX..XXXXXXX 100644
346
--- a/hw/s390x/event-facility.c
347
+++ b/hw/s390x/event-facility.c
348
@@ -XXX,XX +XXX,XX @@ static void init_event_facility(Object *obj)
349
sclp_event_set_allow_all_mask_sizes);
350
351
/* Spawn a new bus for SCLP events */
352
- qbus_create_inplace(&event_facility->sbus, sizeof(event_facility->sbus),
353
- TYPE_SCLP_EVENTS_BUS, sdev, NULL);
354
+ qbus_init(&event_facility->sbus, sizeof(event_facility->sbus),
355
+ TYPE_SCLP_EVENTS_BUS, sdev, NULL);
356
357
object_initialize_child(obj, TYPE_SCLP_QUIESCE,
358
&event_facility->quiesce,
359
diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c
360
index XXXXXXX..XXXXXXX 100644
361
--- a/hw/s390x/virtio-ccw.c
362
+++ b/hw/s390x/virtio-ccw.c
363
@@ -XXX,XX +XXX,XX @@ static void virtio_ccw_bus_new(VirtioBusState *bus, size_t bus_size,
364
DeviceState *qdev = DEVICE(dev);
365
char virtio_bus_name[] = "virtio-bus";
366
367
- qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_CCW_BUS,
368
- qdev, virtio_bus_name);
369
+ qbus_init(bus, bus_size, TYPE_VIRTIO_CCW_BUS, qdev, virtio_bus_name);
370
}
371
372
static void virtio_ccw_bus_class_init(ObjectClass *klass, void *data)
373
diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c
374
index XXXXXXX..XXXXXXX 100644
375
--- a/hw/scsi/scsi-bus.c
376
+++ b/hw/scsi/scsi-bus.c
377
@@ -XXX,XX +XXX,XX @@ void scsi_device_unit_attention_reported(SCSIDevice *s)
378
void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host,
379
const SCSIBusInfo *info, const char *bus_name)
380
{
381
- qbus_create_inplace(bus, bus_size, TYPE_SCSI_BUS, host, bus_name);
382
+ qbus_init(bus, bus_size, TYPE_SCSI_BUS, host, bus_name);
383
bus->busnr = next_scsi_bus++;
384
bus->info = info;
385
qbus_set_bus_hotplug_handler(BUS(bus));
386
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
387
index XXXXXXX..XXXXXXX 100644
388
--- a/hw/sd/allwinner-sdhost.c
389
+++ b/hw/sd/allwinner-sdhost.c
390
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_init(Object *obj)
391
{
392
AwSdHostState *s = AW_SDHOST(obj);
393
394
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
395
- TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
396
+ qbus_init(&s->sdbus, sizeof(s->sdbus),
397
+ TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
398
399
memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
400
TYPE_AW_SDHOST, 4 * KiB);
401
diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c
402
index XXXXXXX..XXXXXXX 100644
403
--- a/hw/sd/bcm2835_sdhost.c
404
+++ b/hw/sd/bcm2835_sdhost.c
405
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_init(Object *obj)
406
{
407
BCM2835SDHostState *s = BCM2835_SDHOST(obj);
408
409
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
410
- TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus");
411
+ qbus_init(&s->sdbus, sizeof(s->sdbus),
412
+ TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus");
413
414
memory_region_init_io(&s->iomem, obj, &bcm2835_sdhost_ops, s,
415
TYPE_BCM2835_SDHOST, 0x1000);
416
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
417
index XXXXXXX..XXXXXXX 100644
418
--- a/hw/sd/pl181.c
419
+++ b/hw/sd/pl181.c
420
@@ -XXX,XX +XXX,XX @@ static void pl181_init(Object *obj)
421
qdev_init_gpio_out_named(dev, &s->card_readonly, "card-read-only", 1);
422
qdev_init_gpio_out_named(dev, &s->card_inserted, "card-inserted", 1);
423
424
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
425
- TYPE_PL181_BUS, dev, "sd-bus");
426
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_PL181_BUS, dev, "sd-bus");
427
}
428
429
static void pl181_class_init(ObjectClass *klass, void *data)
430
diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c
431
index XXXXXXX..XXXXXXX 100644
432
--- a/hw/sd/pxa2xx_mmci.c
433
+++ b/hw/sd/pxa2xx_mmci.c
434
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_mmci_instance_init(Object *obj)
435
qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
436
qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);
437
438
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
439
- TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
440
+ qbus_init(&s->sdbus, sizeof(s->sdbus),
441
+ TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
442
}
443
444
static void pxa2xx_mmci_class_init(ObjectClass *klass, void *data)
445
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
446
index XXXXXXX..XXXXXXX 100644
447
--- a/hw/sd/sdhci.c
448
+++ b/hw/sd/sdhci.c
449
@@ -XXX,XX +XXX,XX @@ static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
450
451
void sdhci_initfn(SDHCIState *s)
452
{
453
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
454
- TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
455
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus");
456
457
s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s);
458
s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s);
459
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
460
index XXXXXXX..XXXXXXX 100644
461
--- a/hw/sd/ssi-sd.c
462
+++ b/hw/sd/ssi-sd.c
463
@@ -XXX,XX +XXX,XX @@ static void ssi_sd_realize(SSIPeripheral *d, Error **errp)
464
DeviceState *carddev;
465
DriveInfo *dinfo;
466
467
- qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
468
- DEVICE(d), "sd-bus");
469
+ qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(d), "sd-bus");
470
471
/* Create and plug in the sd card */
472
/* FIXME use a qdev drive property instead of drive_get_next() */
473
diff --git a/hw/usb/bus.c b/hw/usb/bus.c
474
index XXXXXXX..XXXXXXX 100644
475
--- a/hw/usb/bus.c
476
+++ b/hw/usb/bus.c
477
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_usb_device = {
478
void usb_bus_new(USBBus *bus, size_t bus_size,
479
USBBusOps *ops, DeviceState *host)
480
{
481
- qbus_create_inplace(bus, bus_size, TYPE_USB_BUS, host, NULL);
482
+ qbus_init(bus, bus_size, TYPE_USB_BUS, host, NULL);
483
qbus_set_bus_hotplug_handler(BUS(bus));
484
bus->ops = ops;
485
bus->busnr = next_usb_bus++;
486
diff --git a/hw/usb/dev-smartcard-reader.c b/hw/usb/dev-smartcard-reader.c
487
index XXXXXXX..XXXXXXX 100644
488
--- a/hw/usb/dev-smartcard-reader.c
489
+++ b/hw/usb/dev-smartcard-reader.c
490
@@ -XXX,XX +XXX,XX @@ static void ccid_realize(USBDevice *dev, Error **errp)
491
492
usb_desc_create_serial(dev);
493
usb_desc_init(dev);
494
- qbus_create_inplace(&s->bus, sizeof(s->bus), TYPE_CCID_BUS, DEVICE(dev),
495
- NULL);
496
+ qbus_init(&s->bus, sizeof(s->bus), TYPE_CCID_BUS, DEVICE(dev), NULL);
497
qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(dev));
498
s->intr = usb_ep_get(dev, USB_TOKEN_IN, CCID_INT_IN_EP);
499
s->bulk = usb_ep_get(dev, USB_TOKEN_IN, CCID_BULK_IN_EP);
500
diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c
501
index XXXXXXX..XXXXXXX 100644
502
--- a/hw/virtio/virtio-mmio.c
503
+++ b/hw/virtio/virtio-mmio.c
504
@@ -XXX,XX +XXX,XX @@ static void virtio_mmio_realizefn(DeviceState *d, Error **errp)
505
VirtIOMMIOProxy *proxy = VIRTIO_MMIO(d);
506
SysBusDevice *sbd = SYS_BUS_DEVICE(d);
507
508
- qbus_create_inplace(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS,
509
- d, NULL);
510
+ qbus_init(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS, d, NULL);
511
sysbus_init_irq(sbd, &proxy->irq);
512
513
if (!kvm_eventfds_enabled()) {
514
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
515
index XXXXXXX..XXXXXXX 100644
516
--- a/hw/virtio/virtio-pci.c
517
+++ b/hw/virtio/virtio-pci.c
518
@@ -XXX,XX +XXX,XX @@ static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size,
519
DeviceState *qdev = DEVICE(dev);
520
char virtio_bus_name[] = "virtio-bus";
521
522
- qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev,
523
- virtio_bus_name);
524
+ qbus_init(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev, virtio_bus_name);
525
}
526
527
static void virtio_pci_bus_class_init(ObjectClass *klass, void *data)
44
--
528
--
45
2.20.1
529
2.20.1
46
530
47
531
diff view generated by jsdifflib
[PULL 04/14] target/arm: Add missing 'return's after calling v7m_exception_taken()
[PULL 20/22] qbus: Rename qbus_create() to qbus_new()
1
In do_v7m_exception_exit(), we perform various checks as part of
1
Rename the "allocate and return" qbus creation function to
2
performing the exception return. If one of these checks fails, the
2
qbus_new(), to bring it into line with our _init vs _new convention.
3
architecture requires that we take an appropriate exception on the
4
existing stackframe. We implement this by calling
5
v7m_exception_taken() to set up to take the new exception, and then
6
immediately returning from do_v7m_exception_exit() without proceeding
7
any further with the unstack-and-exception-return process.
8
9
In a couple of checks that are new in v8.1M, we forgot the "return"
10
statement, with the effect that if bad code in the guest tripped over
11
these checks we would set up to take a UsageFault exception but then
12
blunder on trying to also unstack and return from the original
13
exception, with the probable result that the guest would crash.
14
15
Add the missing return statements.
16
3
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
19
Message-id: 20210723162146.5167-3-peter.maydell@linaro.org
6
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
7
Reviewed-by: Corey Minyard <cminyard@mvista.com>
8
Message-id: 20210923121153.23754-6-peter.maydell@linaro.org
20
---
9
---
21
target/arm/m_helper.c | 2 ++
10
include/hw/qdev-core.h | 2 +-
22
1 file changed, 2 insertions(+)
11
hw/core/bus.c | 2 +-
23
12
hw/hyperv/vmbus.c | 2 +-
24
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
13
hw/i2c/core.c | 2 +-
25
index XXXXXXX..XXXXXXX 100644
14
hw/isa/isa-bus.c | 2 +-
26
--- a/target/arm/m_helper.c
15
hw/misc/auxbus.c | 2 +-
27
+++ b/target/arm/m_helper.c
16
hw/pci/pci.c | 2 +-
28
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
17
hw/ppc/spapr_vio.c | 2 +-
29
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
18
hw/s390x/ap-bridge.c | 2 +-
30
"stackframe: NSACR prevents clearing FPU registers\n");
19
hw/s390x/css-bridge.c | 2 +-
31
v7m_exception_taken(cpu, excret, true, false);
20
hw/s390x/s390-pci-bus.c | 2 +-
32
+ return;
21
hw/ssi/ssi.c | 2 +-
33
} else if (!cpacr_pass) {
22
hw/xen/xen-bus.c | 2 +-
34
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
23
hw/xen/xen-legacy-backend.c | 2 +-
35
exc_secure);
24
14 files changed, 14 insertions(+), 14 deletions(-)
36
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
25
37
qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
26
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
38
"stackframe: CPACR prevents clearing FPU registers\n");
27
index XXXXXXX..XXXXXXX 100644
39
v7m_exception_taken(cpu, excret, true, false);
28
--- a/include/hw/qdev-core.h
40
+ return;
29
+++ b/include/hw/qdev-core.h
41
}
30
@@ -XXX,XX +XXX,XX @@ typedef int (qdev_walkerfn)(DeviceState *dev, void *opaque);
42
}
31
43
/* Clear s0..s15, FPSCR and VPR */
32
void qbus_init(void *bus, size_t size, const char *typename,
33
DeviceState *parent, const char *name);
34
-BusState *qbus_create(const char *typename, DeviceState *parent, const char *name);
35
+BusState *qbus_new(const char *typename, DeviceState *parent, const char *name);
36
bool qbus_realize(BusState *bus, Error **errp);
37
void qbus_unrealize(BusState *bus);
38
39
diff --git a/hw/core/bus.c b/hw/core/bus.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/core/bus.c
42
+++ b/hw/core/bus.c
43
@@ -XXX,XX +XXX,XX @@ void qbus_init(void *bus, size_t size, const char *typename,
44
qbus_init_internal(bus, parent, name);
45
}
46
47
-BusState *qbus_create(const char *typename, DeviceState *parent, const char *name)
48
+BusState *qbus_new(const char *typename, DeviceState *parent, const char *name)
49
{
50
BusState *bus;
51
52
diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/hyperv/vmbus.c
55
+++ b/hw/hyperv/vmbus.c
56
@@ -XXX,XX +XXX,XX @@ static void vmbus_bridge_realize(DeviceState *dev, Error **errp)
57
return;
58
}
59
60
- bridge->bus = VMBUS(qbus_create(TYPE_VMBUS, dev, "vmbus"));
61
+ bridge->bus = VMBUS(qbus_new(TYPE_VMBUS, dev, "vmbus"));
62
}
63
64
static char *vmbus_bridge_ofw_unit_address(const SysBusDevice *dev)
65
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/hw/i2c/core.c
68
+++ b/hw/i2c/core.c
69
@@ -XXX,XX +XXX,XX @@ I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
70
{
71
I2CBus *bus;
72
73
- bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name));
74
+ bus = I2C_BUS(qbus_new(TYPE_I2C_BUS, parent, name));
75
QLIST_INIT(&bus->current_devs);
76
vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_i2c_bus, bus);
77
return bus;
78
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/hw/isa/isa-bus.c
81
+++ b/hw/isa/isa-bus.c
82
@@ -XXX,XX +XXX,XX @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion* address_space,
83
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
84
}
85
86
- isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL));
87
+ isabus = ISA_BUS(qbus_new(TYPE_ISA_BUS, dev, NULL));
88
isabus->address_space = address_space;
89
isabus->address_space_io = address_space_io;
90
return isabus;
91
diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/hw/misc/auxbus.c
94
+++ b/hw/misc/auxbus.c
95
@@ -XXX,XX +XXX,XX @@ AUXBus *aux_bus_init(DeviceState *parent, const char *name)
96
AUXBus *bus;
97
Object *auxtoi2c;
98
99
- bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
100
+ bus = AUX_BUS(qbus_new(TYPE_AUX_BUS, parent, name));
101
auxtoi2c = object_new_with_props(TYPE_AUXTOI2C, OBJECT(bus), "i2c",
102
&error_abort, NULL);
103
104
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/hw/pci/pci.c
107
+++ b/hw/pci/pci.c
108
@@ -XXX,XX +XXX,XX @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
109
{
110
PCIBus *bus;
111
112
- bus = PCI_BUS(qbus_create(typename, parent, name));
113
+ bus = PCI_BUS(qbus_new(typename, parent, name));
114
pci_root_bus_internal_init(bus, parent, address_space_mem,
115
address_space_io, devfn_min);
116
return bus;
117
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/hw/ppc/spapr_vio.c
120
+++ b/hw/ppc/spapr_vio.c
121
@@ -XXX,XX +XXX,XX @@ SpaprVioBus *spapr_vio_bus_init(void)
122
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
123
124
/* Create bus on bridge device */
125
- qbus = qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");
126
+ qbus = qbus_new(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio");
127
bus = SPAPR_VIO_BUS(qbus);
128
bus->next_reg = SPAPR_VIO_REG_BASE;
129
130
diff --git a/hw/s390x/ap-bridge.c b/hw/s390x/ap-bridge.c
131
index XXXXXXX..XXXXXXX 100644
132
--- a/hw/s390x/ap-bridge.c
133
+++ b/hw/s390x/ap-bridge.c
134
@@ -XXX,XX +XXX,XX @@ void s390_init_ap(void)
135
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
136
137
/* Create bus on bridge device */
138
- bus = qbus_create(TYPE_AP_BUS, dev, TYPE_AP_BUS);
139
+ bus = qbus_new(TYPE_AP_BUS, dev, TYPE_AP_BUS);
140
141
/* Enable hotplugging */
142
qbus_set_hotplug_handler(bus, OBJECT(dev));
143
diff --git a/hw/s390x/css-bridge.c b/hw/s390x/css-bridge.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/hw/s390x/css-bridge.c
146
+++ b/hw/s390x/css-bridge.c
147
@@ -XXX,XX +XXX,XX @@ VirtualCssBus *virtual_css_bus_init(void)
148
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
149
150
/* Create bus on bridge device */
151
- bus = qbus_create(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css");
152
+ bus = qbus_new(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css");
153
cbus = VIRTUAL_CSS_BUS(bus);
154
155
/* Enable hotplugging */
156
diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c
157
index XXXXXXX..XXXXXXX 100644
158
--- a/hw/s390x/s390-pci-bus.c
159
+++ b/hw/s390x/s390-pci-bus.c
160
@@ -XXX,XX +XXX,XX @@ static void s390_pcihost_realize(DeviceState *dev, Error **errp)
161
qbus_set_hotplug_handler(bus, OBJECT(dev));
162
phb->bus = b;
163
164
- s->bus = S390_PCI_BUS(qbus_create(TYPE_S390_PCI_BUS, dev, NULL));
165
+ s->bus = S390_PCI_BUS(qbus_new(TYPE_S390_PCI_BUS, dev, NULL));
166
qbus_set_hotplug_handler(BUS(s->bus), OBJECT(dev));
167
168
s->iommu_table = g_hash_table_new_full(g_int64_hash, g_int64_equal,
169
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
170
index XXXXXXX..XXXXXXX 100644
171
--- a/hw/ssi/ssi.c
172
+++ b/hw/ssi/ssi.c
173
@@ -XXX,XX +XXX,XX @@ DeviceState *ssi_create_peripheral(SSIBus *bus, const char *name)
174
SSIBus *ssi_create_bus(DeviceState *parent, const char *name)
175
{
176
BusState *bus;
177
- bus = qbus_create(TYPE_SSI_BUS, parent, name);
178
+ bus = qbus_new(TYPE_SSI_BUS, parent, name);
179
return SSI_BUS(bus);
180
}
181
182
diff --git a/hw/xen/xen-bus.c b/hw/xen/xen-bus.c
183
index XXXXXXX..XXXXXXX 100644
184
--- a/hw/xen/xen-bus.c
185
+++ b/hw/xen/xen-bus.c
186
@@ -XXX,XX +XXX,XX @@ type_init(xen_register_types)
187
void xen_bus_init(void)
188
{
189
DeviceState *dev = qdev_new(TYPE_XEN_BRIDGE);
190
- BusState *bus = qbus_create(TYPE_XEN_BUS, dev, NULL);
191
+ BusState *bus = qbus_new(TYPE_XEN_BUS, dev, NULL);
192
193
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
194
qbus_set_bus_hotplug_handler(bus);
195
diff --git a/hw/xen/xen-legacy-backend.c b/hw/xen/xen-legacy-backend.c
196
index XXXXXXX..XXXXXXX 100644
197
--- a/hw/xen/xen-legacy-backend.c
198
+++ b/hw/xen/xen-legacy-backend.c
199
@@ -XXX,XX +XXX,XX @@ int xen_be_init(void)
200
201
xen_sysdev = qdev_new(TYPE_XENSYSDEV);
202
sysbus_realize_and_unref(SYS_BUS_DEVICE(xen_sysdev), &error_fatal);
203
- xen_sysbus = qbus_create(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus");
204
+ xen_sysbus = qbus_new(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus");
205
qbus_set_bus_hotplug_handler(xen_sysbus);
206
207
return 0;
44
--
208
--
45
2.20.1
209
2.20.1
46
210
47
211
diff view generated by jsdifflib
[PULL 02/14] qemu-options.hx: Fix formatting of -machine memory-backend option
[PULL 21/22] ide: Rename ide_bus_new() to ide_bus_init()
1
The documentation of the -machine memory-backend has some minor
1
The function ide_bus_new() does an in-place initialization. Rename
2
formatting errors:
2
it to ide_bus_init() to follow our _init vs _new convention.
3
* Misindentation of the initial line meant that the whole option
4
section is incorrectly indented in the HTML output compared to
5
the other -machine options
6
* The examples weren't indented, which meant that they were formatted
7
as plain run-on text including outputting the "::" as text.
8
* The a) b) list has no rst-format markup so it is rendered as
9
a single run-on paragraph
10
11
Fix the formatting.
12
3
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Message-id: 20210719105257.3599-1-peter.maydell@linaro.org
6
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
7
Reviewed-by: Corey Minyard <cminyard@mvista.com>
8
Reviewed-by: John Snow <jsnow@redhat.com>
9
Acked-by: John Snow <jsnow@redhat.com> (Feel free to merge.)
10
Message-id: 20210923121153.23754-7-peter.maydell@linaro.org
16
---
11
---
17
qemu-options.hx | 30 +++++++++++++++++-------------
12
include/hw/ide/internal.h | 4 ++--
18
1 file changed, 17 insertions(+), 13 deletions(-)
13
hw/ide/ahci.c | 2 +-
14
hw/ide/cmd646.c | 2 +-
15
hw/ide/isa.c | 2 +-
16
hw/ide/macio.c | 2 +-
17
hw/ide/microdrive.c | 2 +-
18
hw/ide/mmio.c | 2 +-
19
hw/ide/piix.c | 2 +-
20
hw/ide/qdev.c | 2 +-
21
hw/ide/sii3112.c | 2 +-
22
hw/ide/via.c | 2 +-
23
11 files changed, 12 insertions(+), 12 deletions(-)
19
24
20
diff --git a/qemu-options.hx b/qemu-options.hx
25
diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h
21
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
22
--- a/qemu-options.hx
27
--- a/include/hw/ide/internal.h
23
+++ b/qemu-options.hx
28
+++ b/include/hw/ide/internal.h
24
@@ -XXX,XX +XXX,XX @@ SRST
29
@@ -XXX,XX +XXX,XX @@ void ide_atapi_cmd(IDEState *s);
25
Enables or disables ACPI Heterogeneous Memory Attribute Table
30
void ide_atapi_cmd_reply_end(IDEState *s);
26
(HMAT) support. The default is off.
31
27
32
/* hw/ide/qdev.c */
28
- ``memory-backend='id'``
33
-void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
29
+ ``memory-backend='id'``
34
- int bus_id, int max_units);
30
An alternative to legacy ``-mem-path`` and ``mem-prealloc`` options.
35
+void ide_bus_init(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
31
Allows to use a memory backend as main RAM.
36
+ int bus_id, int max_units);
32
37
IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive);
33
For example:
38
34
::
39
int ide_handle_rw_error(IDEState *s, int error, int op);
35
- -object memory-backend-file,id=pc.ram,size=512M,mem-path=/hugetlbfs,prealloc=on,share=on
40
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
36
- -machine memory-backend=pc.ram
41
index XXXXXXX..XXXXXXX 100644
37
- -m 512M
42
--- a/hw/ide/ahci.c
38
+
43
+++ b/hw/ide/ahci.c
39
+ -object memory-backend-file,id=pc.ram,size=512M,mem-path=/hugetlbfs,prealloc=on,share=on
44
@@ -XXX,XX +XXX,XX @@ void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
40
+ -machine memory-backend=pc.ram
45
for (i = 0; i < s->ports; i++) {
41
+ -m 512M
46
AHCIDevice *ad = &s->dev[i];
42
47
43
Migration compatibility note:
48
- ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1);
44
- a) as backend id one shall use value of 'default-ram-id', advertised by
49
+ ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1);
45
- machine type (available via ``query-machines`` QMP command), if migration
50
ide_init2(&ad->port, irqs[i]);
46
- to/from old QEMU (<5.0) is expected.
51
47
- b) for machine types 4.0 and older, user shall
52
ad->hba = s;
48
- use ``x-use-canonical-path-for-ramblock-id=off`` backend option
53
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
49
- if migration to/from old QEMU (<5.0) is expected.
54
index XXXXXXX..XXXXXXX 100644
50
+
55
--- a/hw/ide/cmd646.c
51
+ * as backend id one shall use value of 'default-ram-id', advertised by
56
+++ b/hw/ide/cmd646.c
52
+ machine type (available via ``query-machines`` QMP command), if migration
57
@@ -XXX,XX +XXX,XX @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
53
+ to/from old QEMU (<5.0) is expected.
58
54
+ * for machine types 4.0 and older, user shall
59
qdev_init_gpio_in(ds, cmd646_set_irq, 2);
55
+ use ``x-use-canonical-path-for-ramblock-id=off`` backend option
60
for (i = 0; i < 2; i++) {
56
+ if migration to/from old QEMU (<5.0) is expected.
61
- ide_bus_new(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
57
+
62
+ ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
58
For example:
63
ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i));
59
::
64
60
- -object memory-backend-ram,id=pc.ram,size=512M,x-use-canonical-path-for-ramblock-id=off
65
bmdma_init(&d->bus[i], &d->bmdma[i], d);
61
- -machine memory-backend=pc.ram
66
diff --git a/hw/ide/isa.c b/hw/ide/isa.c
62
- -m 512M
67
index XXXXXXX..XXXXXXX 100644
63
+
68
--- a/hw/ide/isa.c
64
+ -object memory-backend-ram,id=pc.ram,size=512M,x-use-canonical-path-for-ramblock-id=off
69
+++ b/hw/ide/isa.c
65
+ -machine memory-backend=pc.ram
70
@@ -XXX,XX +XXX,XX @@ static void isa_ide_realizefn(DeviceState *dev, Error **errp)
66
+ -m 512M
71
ISADevice *isadev = ISA_DEVICE(dev);
67
ERST
72
ISAIDEState *s = ISA_IDE(dev);
68
73
69
HXCOMM Deprecated by -machine
74
- ide_bus_new(&s->bus, sizeof(s->bus), dev, 0, 2);
75
+ ide_bus_init(&s->bus, sizeof(s->bus), dev, 0, 2);
76
ide_init_ioport(&s->bus, isadev, s->iobase, s->iobase2);
77
isa_init_irq(isadev, &s->irq, s->isairq);
78
ide_init2(&s->bus, s->irq);
79
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/ide/macio.c
82
+++ b/hw/ide/macio.c
83
@@ -XXX,XX +XXX,XX @@ static void macio_ide_initfn(Object *obj)
84
SysBusDevice *d = SYS_BUS_DEVICE(obj);
85
MACIOIDEState *s = MACIO_IDE(obj);
86
87
- ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
88
+ ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
89
memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
90
sysbus_init_mmio(d, &s->mem);
91
sysbus_init_irq(d, &s->real_ide_irq);
92
diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/hw/ide/microdrive.c
95
+++ b/hw/ide/microdrive.c
96
@@ -XXX,XX +XXX,XX @@ static void microdrive_init(Object *obj)
97
{
98
MicroDriveState *md = MICRODRIVE(obj);
99
100
- ide_bus_new(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
101
+ ide_bus_init(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1);
102
}
103
104
static void microdrive_class_init(ObjectClass *oc, void *data)
105
diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/hw/ide/mmio.c
108
+++ b/hw/ide/mmio.c
109
@@ -XXX,XX +XXX,XX @@ static void mmio_ide_initfn(Object *obj)
110
SysBusDevice *d = SYS_BUS_DEVICE(obj);
111
MMIOState *s = MMIO_IDE(obj);
112
113
- ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
114
+ ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
115
sysbus_init_irq(d, &s->irq);
116
}
117
118
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
119
index XXXXXXX..XXXXXXX 100644
120
--- a/hw/ide/piix.c
121
+++ b/hw/ide/piix.c
122
@@ -XXX,XX +XXX,XX @@ static int pci_piix_init_ports(PCIIDEState *d)
123
int i, ret;
124
125
for (i = 0; i < 2; i++) {
126
- ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
127
+ ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
128
ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
129
port_info[i].iobase2);
130
if (ret) {
131
diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/hw/ide/qdev.c
134
+++ b/hw/ide/qdev.c
135
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ide_bus_info = {
136
.class_init = ide_bus_class_init,
137
};
138
139
-void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
140
+void ide_bus_init(IDEBus *idebus, size_t idebus_size, DeviceState *dev,
141
int bus_id, int max_units)
142
{
143
qbus_init(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL);
144
diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c
145
index XXXXXXX..XXXXXXX 100644
146
--- a/hw/ide/sii3112.c
147
+++ b/hw/ide/sii3112.c
148
@@ -XXX,XX +XXX,XX @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp)
149
150
qdev_init_gpio_in(ds, sii3112_set_irq, 2);
151
for (i = 0; i < 2; i++) {
152
- ide_bus_new(&s->bus[i], sizeof(s->bus[i]), ds, i, 1);
153
+ ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1);
154
ide_init2(&s->bus[i], qdev_get_gpio_in(ds, i));
155
156
bmdma_init(&s->bus[i], &s->bmdma[i], s);
157
diff --git a/hw/ide/via.c b/hw/ide/via.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/hw/ide/via.c
160
+++ b/hw/ide/via.c
161
@@ -XXX,XX +XXX,XX @@ static void via_ide_realize(PCIDevice *dev, Error **errp)
162
163
qdev_init_gpio_in(ds, via_ide_set_irq, 2);
164
for (i = 0; i < 2; i++) {
165
- ide_bus_new(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
166
+ ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2);
167
ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i));
168
169
bmdma_init(&d->bus[i], &d->bmdma[i], d);
70
--
170
--
71
2.20.1
171
2.20.1
72
172
73
173
diff view generated by jsdifflib
[PULL 13/14] hw/arm/nseries: Display hexadecimal value with '0x' prefix
[PULL 22/22] hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
The Linux spi-imx driver does not work on QEMU. The reason is that the
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
state of m25p80 loops in STATE_READING_DATA state after receiving
5
Message-id: 20210726150953.1218690-1-f4bug@amsat.org
5
RDSR command, the new command is ignored. Before sending a new command,
6
CS line should be pulled high to make the state of m25p80 back to IDLE.
7
8
Currently the SPI flash CS line is connected to the SPI controller, but
9
on the real board, it's connected to GPIO3_19. This matches the ecspi1
10
device node in the board dts.
11
12
ecspi1 node in imx6qdl-sabrelite.dtsi:
13
&ecspi1 {
14
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
15
pinctrl-names = "default";
16
pinctrl-0 = <&pinctrl_ecspi1>;
17
status = "okay";
18
19
flash: m25p80@0 {
20
compatible = "sst,sst25vf016b", "jedec,spi-nor";
21
spi-max-frequency = <20000000>;
22
reg = <0>;
23
};
24
};
25
26
Should connect the SSI_GPIO_CS to GPIO3_19 when adding a spi-nor to
27
spi1 on sabrelite machine.
28
29
Verified this patch on Linux v5.14.
30
31
Logs:
32
# echo "01234567899876543210" > test
33
# mtd_debug erase /dev/mtd0 0x0 0x1000
34
Erased 4096 bytes from address 0x00000000 in flash
35
# mtd_debug write /dev/mtdblock0 0x0 20 test
36
Copied 20 bytes from test to address 0x00000000 in flash
37
# mtd_debug read /dev/mtdblock0 0x0 20 test_out
38
Copied 20 bytes from address 0x00000000 in flash to test_out
39
# cat test_out
40
01234567899876543210#
41
42
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
43
Reported-by: Guenter Roeck <linux@roeck-us.net>
44
Reviewed-by: Bin Meng <bin.meng@windriver.com>
45
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
46
Message-id: 20210927142825.491-1-xchengl.cn@gmail.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
47
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
48
---
8
hw/arm/nseries.c | 2 +-
49
hw/arm/sabrelite.c | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
50
1 file changed, 1 insertion(+), 1 deletion(-)
10
51
11
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
52
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
12
index XXXXXXX..XXXXXXX 100644
53
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/nseries.c
54
--- a/hw/arm/sabrelite.c
14
+++ b/hw/arm/nseries.c
55
+++ b/hw/arm/sabrelite.c
15
@@ -XXX,XX +XXX,XX @@ static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
56
@@ -XXX,XX +XXX,XX @@ static void sabrelite_init(MachineState *machine)
16
default:
57
qdev_realize_and_unref(flash_dev, BUS(spi_bus), &error_fatal);
17
bad_cmd:
58
18
qemu_log_mask(LOG_GUEST_ERROR,
59
cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
19
- "%s: unknown command %02x\n", __func__, s->cmd);
60
- sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line);
20
+ "%s: unknown command 0x%02x\n", __func__, s->cmd);
61
+ qdev_connect_gpio_out(DEVICE(&s->gpio[2]), 19, cs_line);
21
break;
62
}
63
}
22
}
64
}
23
24
--
65
--
25
2.20.1
66
2.20.1
26
67
27
68
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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