1 | The following changes since commit 57e28d34c0cb04abf7683ac6a12c87ede447c320: | 1 | From: Alistair Francis <alistair.francis@wdc.com> |
---|---|---|---|
2 | 2 | ||
3 | Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210708' into staging (2021-07-12 19:15:11 +0100) | 3 | The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1: |
4 | |||
5 | Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100) | ||
4 | 6 | ||
5 | are available in the Git repository at: | 7 | are available in the Git repository at: |
6 | 8 | ||
7 | git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210712 | 9 | git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122 |
8 | 10 | ||
9 | for you to fetch changes up to d6b87906f09f72a837dc68c33bfc3d913ef74b7d: | 11 | for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3: |
10 | 12 | ||
11 | hw/riscv: opentitan: Add the flash alias (2021-07-13 08:47:52 +1000) | 13 | hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000) |
12 | 14 | ||
13 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
14 | Fourth RISC-V PR for 6.1 release | 16 | Seventh RISC-V PR for QEMU 6.2 |
15 | 17 | ||
16 | - Code cleanups | 18 | - Deprecate IF_NONE for SiFive OTP |
17 | - Documentation improvements | 19 | - Don't reset SiFive OTP content |
18 | - Hypervisor extension improvements with hideleg and hedeleg | ||
19 | - sifive_u fixes | ||
20 | - OpenTitan register layout updates | ||
21 | 20 | ||
22 | ---------------------------------------------------------------- | 21 | ---------------------------------------------------------------- |
23 | Alistair Francis (3): | 22 | Philippe Mathieu-Daudé (1): |
24 | char: ibex_uart: Update the register layout | 23 | hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset |
25 | hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri | ||
26 | hw/riscv: opentitan: Add the flash alias | ||
27 | 24 | ||
28 | Bin Meng (7): | 25 | Thomas Huth (1): |
29 | target/riscv: pmp: Fix some typos | 26 | hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE |
30 | target/riscv: csr: Remove redundant check in fp csr read/write routines | ||
31 | docs/system: riscv: Fix CLINT name in the sifive_u doc | ||
32 | docs/system: riscv: Add documentation for virt machine | ||
33 | docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot | ||
34 | hw/riscv: sifive_u: Correct the CLINT timebase frequency | ||
35 | hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned | ||
36 | 27 | ||
37 | Jose Martins (1): | 28 | docs/about/deprecated.rst | 6 ++++++ |
38 | target/riscv: hardwire bits in hideleg and hedeleg | 29 | hw/misc/sifive_u_otp.c | 22 +++++++++++++--------- |
30 | 2 files changed, 19 insertions(+), 9 deletions(-) | ||
39 | 31 | ||
40 | docs/system/riscv/microchip-icicle-kit.rst | 54 +++++++++-- | ||
41 | docs/system/riscv/sifive_u.rst | 2 +- | ||
42 | docs/system/riscv/virt.rst | 138 +++++++++++++++++++++++++++++ | ||
43 | docs/system/target-riscv.rst | 1 + | ||
44 | include/hw/riscv/opentitan.h | 3 + | ||
45 | hw/char/ibex_uart.c | 19 ++-- | ||
46 | hw/riscv/opentitan.c | 9 ++ | ||
47 | hw/riscv/sifive_u.c | 12 ++- | ||
48 | target/riscv/csr.c | 37 +++----- | ||
49 | target/riscv/pmp.c | 10 +-- | ||
50 | 10 files changed, 233 insertions(+), 52 deletions(-) | ||
51 | create mode 100644 docs/system/riscv/virt.rst | ||
52 | diff view generated by jsdifflib |
1 | From: Bin Meng <bmeng.cn@gmail.com> | 1 | From: Thomas Huth <thuth@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | The following check: | 3 | Configuring a drive with "if=none" is meant for creation of a backend |
4 | only, it should not get automatically assigned to a device frontend. | ||
5 | Use "if=pflash" for the One-Time-Programmable device instead (like | ||
6 | it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c). | ||
4 | 7 | ||
5 | if (!env->debugger && !riscv_cpu_fp_enabled(env)) { | 8 | Since the old way of configuring the device has already been published |
6 | return -RISCV_EXCP_ILLEGAL_INST; | 9 | with the previous QEMU versions, we cannot remove this immediately, but |
7 | } | 10 | have to deprecate it and support it for at least two more releases. |
8 | 11 | ||
9 | is redundant in fflags/frm/fcsr read/write routines, as the check was | 12 | Signed-off-by: Thomas Huth <thuth@redhat.com> |
10 | already done in fs(). | 13 | Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
11 | 14 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | |
12 | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> | ||
13 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
14 | Message-id: 20210627120604.11116-1-bmeng.cn@gmail.com | 16 | Message-id: 20211119102549.217755-1-thuth@redhat.com |
15 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
16 | --- | 18 | --- |
17 | target/riscv/csr.c | 24 ------------------------ | 19 | docs/about/deprecated.rst | 6 ++++++ |
18 | 1 file changed, 24 deletions(-) | 20 | hw/misc/sifive_u_otp.c | 9 ++++++++- |
21 | 2 files changed, 14 insertions(+), 1 deletion(-) | ||
19 | 22 | ||
20 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | 23 | diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst |
21 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/target/riscv/csr.c | 25 | --- a/docs/about/deprecated.rst |
23 | +++ b/target/riscv/csr.c | 26 | +++ b/docs/about/deprecated.rst |
24 | @@ -XXX,XX +XXX,XX @@ static RISCVException epmp(CPURISCVState *env, int csrno) | 27 | @@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``. |
25 | static RISCVException read_fflags(CPURISCVState *env, int csrno, | 28 | However, short-form booleans are deprecated and full explicit ``arg_name=on`` |
26 | target_ulong *val) | 29 | form is preferred. |
27 | { | 30 | |
28 | -#if !defined(CONFIG_USER_ONLY) | 31 | +``-drive if=none`` for the sifive_u OTP device (since 6.2) |
29 | - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { | 32 | +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''' |
30 | - return RISCV_EXCP_ILLEGAL_INST; | 33 | + |
31 | - } | 34 | +Using ``-drive if=none`` to configure the OTP device of the sifive_u |
32 | -#endif | 35 | +RISC-V machine is deprecated. Use ``-drive if=pflash`` instead. |
33 | *val = riscv_cpu_get_fflags(env); | 36 | + |
34 | return RISCV_EXCP_NONE; | 37 | |
35 | } | 38 | QEMU Machine Protocol (QMP) commands |
36 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_fflags(CPURISCVState *env, int csrno, | 39 | ------------------------------------ |
37 | target_ulong val) | 40 | diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c |
38 | { | 41 | index XXXXXXX..XXXXXXX 100644 |
39 | #if !defined(CONFIG_USER_ONLY) | 42 | --- a/hw/misc/sifive_u_otp.c |
40 | - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { | 43 | +++ b/hw/misc/sifive_u_otp.c |
41 | - return RISCV_EXCP_ILLEGAL_INST; | 44 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) |
42 | - } | 45 | TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); |
43 | env->mstatus |= MSTATUS_FS; | 46 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); |
44 | #endif | 47 | |
45 | riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); | 48 | - dinfo = drive_get_next(IF_NONE); |
46 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_fflags(CPURISCVState *env, int csrno, | 49 | + dinfo = drive_get_next(IF_PFLASH); |
47 | static RISCVException read_frm(CPURISCVState *env, int csrno, | 50 | + if (!dinfo) { |
48 | target_ulong *val) | 51 | + dinfo = drive_get_next(IF_NONE); |
49 | { | 52 | + if (dinfo) { |
50 | -#if !defined(CONFIG_USER_ONLY) | 53 | + warn_report("using \"-drive if=none\" for the OTP is deprecated, " |
51 | - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { | 54 | + "use \"-drive if=pflash\" instead."); |
52 | - return RISCV_EXCP_ILLEGAL_INST; | 55 | + } |
53 | - } | 56 | + } |
54 | -#endif | 57 | if (dinfo) { |
55 | *val = env->frm; | 58 | int ret; |
56 | return RISCV_EXCP_NONE; | 59 | uint64_t perm; |
57 | } | ||
58 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_frm(CPURISCVState *env, int csrno, | ||
59 | target_ulong val) | ||
60 | { | ||
61 | #if !defined(CONFIG_USER_ONLY) | ||
62 | - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { | ||
63 | - return RISCV_EXCP_ILLEGAL_INST; | ||
64 | - } | ||
65 | env->mstatus |= MSTATUS_FS; | ||
66 | #endif | ||
67 | env->frm = val & (FSR_RD >> FSR_RD_SHIFT); | ||
68 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_frm(CPURISCVState *env, int csrno, | ||
69 | static RISCVException read_fcsr(CPURISCVState *env, int csrno, | ||
70 | target_ulong *val) | ||
71 | { | ||
72 | -#if !defined(CONFIG_USER_ONLY) | ||
73 | - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { | ||
74 | - return RISCV_EXCP_ILLEGAL_INST; | ||
75 | - } | ||
76 | -#endif | ||
77 | *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) | ||
78 | | (env->frm << FSR_RD_SHIFT); | ||
79 | if (vs(env, csrno) >= 0) { | ||
80 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno, | ||
81 | target_ulong val) | ||
82 | { | ||
83 | #if !defined(CONFIG_USER_ONLY) | ||
84 | - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { | ||
85 | - return RISCV_EXCP_ILLEGAL_INST; | ||
86 | - } | ||
87 | env->mstatus |= MSTATUS_FS; | ||
88 | #endif | ||
89 | env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; | ||
90 | -- | 60 | -- |
91 | 2.31.1 | 61 | 2.31.1 |
92 | 62 | ||
93 | 63 | diff view generated by jsdifflib |
1 | From: Bin Meng <bmeng.cn@gmail.com> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | %s/CSP/CSR | 3 | Once a "One Time Programmable" is programmed, it shouldn't be reset. |
4 | %s/thie/the | ||
5 | 4 | ||
6 | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> | 5 | Do not re-initialize the OTP content in the DeviceReset handler, |
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | initialize it once in the DeviceRealize one. |
7 | |||
8 | Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP") | ||
9 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
9 | Message-id: 20210627115716.3552-1-bmeng.cn@gmail.com | 11 | Message-Id: <20211119104757.331579-1-f4bug@amsat.org> |
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
11 | --- | 13 | --- |
12 | target/riscv/pmp.c | 10 +++++----- | 14 | hw/misc/sifive_u_otp.c | 13 +++++-------- |
13 | 1 file changed, 5 insertions(+), 5 deletions(-) | 15 | 1 file changed, 5 insertions(+), 8 deletions(-) |
14 | 16 | ||
15 | diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c | 17 | diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c |
16 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/riscv/pmp.c | 19 | --- a/hw/misc/sifive_u_otp.c |
18 | +++ b/target/riscv/pmp.c | 20 | +++ b/hw/misc/sifive_u_otp.c |
19 | @@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, | 21 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) |
22 | |||
23 | if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) { | ||
24 | error_setg(errp, "failed to read the initial flash content"); | ||
25 | + return; | ||
26 | } | ||
27 | } | ||
28 | } | ||
29 | -} | ||
30 | - | ||
31 | -static void sifive_u_otp_reset(DeviceState *dev) | ||
32 | -{ | ||
33 | - SiFiveUOTPState *s = SIFIVE_U_OTP(dev); | ||
34 | |||
35 | /* Initialize all fuses' initial value to 0xFFs */ | ||
36 | memset(s->fuse, 0xff, sizeof(s->fuse)); | ||
37 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev) | ||
38 | serial_data = s->serial; | ||
39 | if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD, | ||
40 | &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { | ||
41 | - error_report("write error index<%d>", index); | ||
42 | + error_setg(errp, "failed to write index<%d>", index); | ||
43 | + return; | ||
44 | } | ||
45 | |||
46 | serial_data = ~(s->serial); | ||
47 | if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD, | ||
48 | &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { | ||
49 | - error_report("write error index<%d>", index + 1); | ||
50 | + error_setg(errp, "failed to write index<%d>", index + 1); | ||
51 | + return; | ||
52 | } | ||
53 | } | ||
54 | |||
55 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data) | ||
56 | |||
57 | device_class_set_props(dc, sifive_u_otp_properties); | ||
58 | dc->realize = sifive_u_otp_realize; | ||
59 | - dc->reset = sifive_u_otp_reset; | ||
20 | } | 60 | } |
21 | 61 | ||
22 | /* | 62 | static const TypeInfo sifive_u_otp_info = { |
23 | - * Handle a write to a pmpcfg CSP | ||
24 | + * Handle a write to a pmpcfg CSR | ||
25 | */ | ||
26 | void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, | ||
27 | target_ulong val) | ||
28 | @@ -XXX,XX +XXX,XX @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, | ||
29 | |||
30 | |||
31 | /* | ||
32 | - * Handle a read from a pmpcfg CSP | ||
33 | + * Handle a read from a pmpcfg CSR | ||
34 | */ | ||
35 | target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) | ||
36 | { | ||
37 | @@ -XXX,XX +XXX,XX @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) | ||
38 | |||
39 | |||
40 | /* | ||
41 | - * Handle a write to a pmpaddr CSP | ||
42 | + * Handle a write to a pmpaddr CSR | ||
43 | */ | ||
44 | void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, | ||
45 | target_ulong val) | ||
46 | @@ -XXX,XX +XXX,XX @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, | ||
47 | |||
48 | |||
49 | /* | ||
50 | - * Handle a read from a pmpaddr CSP | ||
51 | + * Handle a read from a pmpaddr CSR | ||
52 | */ | ||
53 | target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) | ||
54 | { | ||
55 | @@ -XXX,XX +XXX,XX @@ target_ulong mseccfg_csr_read(CPURISCVState *env) | ||
56 | |||
57 | /* | ||
58 | * Calculate the TLB size if the start address or the end address of | ||
59 | - * PMP entry is presented in thie TLB page. | ||
60 | + * PMP entry is presented in the TLB page. | ||
61 | */ | ||
62 | static target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index, | ||
63 | target_ulong tlb_sa, target_ulong tlb_ea) | ||
64 | -- | 63 | -- |
65 | 2.31.1 | 64 | 2.31.1 |
66 | 65 | ||
67 | 66 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Bin Meng <bmeng.cn@gmail.com> | ||
2 | 1 | ||
3 | It's Core *Local* Interruptor, not 'Level'. | ||
4 | |||
5 | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> | ||
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
7 | Message-id: 20210627142816.19789-1-bmeng.cn@gmail.com | ||
8 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | --- | ||
10 | docs/system/riscv/sifive_u.rst | 2 +- | ||
11 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
12 | |||
13 | diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/docs/system/riscv/sifive_u.rst | ||
16 | +++ b/docs/system/riscv/sifive_u.rst | ||
17 | @@ -XXX,XX +XXX,XX @@ The ``sifive_u`` machine supports the following devices: | ||
18 | |||
19 | * 1 E51 / E31 core | ||
20 | * Up to 4 U54 / U34 cores | ||
21 | -* Core Level Interruptor (CLINT) | ||
22 | +* Core Local Interruptor (CLINT) | ||
23 | * Platform-Level Interrupt Controller (PLIC) | ||
24 | * Power, Reset, Clock, Interrupt (PRCI) | ||
25 | * L2 Loosely Integrated Memory (L2-LIM) | ||
26 | -- | ||
27 | 2.31.1 | ||
28 | |||
29 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Bin Meng <bmeng.cn@gmail.com> | ||
2 | 1 | ||
3 | This adds detailed documentation for RISC-V `virt` machine, | ||
4 | including the following information: | ||
5 | |||
6 | - Supported devices | ||
7 | - Hardware configuration information | ||
8 | - Boot options | ||
9 | - Running Linux kernel | ||
10 | - Running U-Boot | ||
11 | |||
12 | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> | ||
13 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
14 | Message-id: 20210627142816.19789-2-bmeng.cn@gmail.com | ||
15 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
16 | --- | ||
17 | docs/system/riscv/virt.rst | 138 +++++++++++++++++++++++++++++++++++ | ||
18 | docs/system/target-riscv.rst | 1 + | ||
19 | 2 files changed, 139 insertions(+) | ||
20 | create mode 100644 docs/system/riscv/virt.rst | ||
21 | |||
22 | diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst | ||
23 | new file mode 100644 | ||
24 | index XXXXXXX..XXXXXXX | ||
25 | --- /dev/null | ||
26 | +++ b/docs/system/riscv/virt.rst | ||
27 | @@ -XXX,XX +XXX,XX @@ | ||
28 | +'virt' Generic Virtual Platform (``virt``) | ||
29 | +========================================== | ||
30 | + | ||
31 | +The `virt` board is a platform which does not correspond to any real hardware; | ||
32 | +it is designed for use in virtual machines. It is the recommended board type | ||
33 | +if you simply want to run a guest such as Linux and do not care about | ||
34 | +reproducing the idiosyncrasies and limitations of a particular bit of | ||
35 | +real-world hardware. | ||
36 | + | ||
37 | +Supported devices | ||
38 | +----------------- | ||
39 | + | ||
40 | +The ``virt`` machine supports the following devices: | ||
41 | + | ||
42 | +* Up to 8 generic RV32GC/RV64GC cores, with optional extensions | ||
43 | +* Core Local Interruptor (CLINT) | ||
44 | +* Platform-Level Interrupt Controller (PLIC) | ||
45 | +* CFI parallel NOR flash memory | ||
46 | +* 1 NS16550 compatible UART | ||
47 | +* 1 Google Goldfish RTC | ||
48 | +* 1 SiFive Test device | ||
49 | +* 8 virtio-mmio transport devices | ||
50 | +* 1 generic PCIe host bridge | ||
51 | +* The fw_cfg device that allows a guest to obtain data from QEMU | ||
52 | + | ||
53 | +Note that the default CPU is a generic RV32GC/RV64GC. Optional extensions | ||
54 | +can be enabled via command line parameters, e.g.: ``-cpu rv64,x-h=true`` | ||
55 | +enables the hypervisor extension for RV64. | ||
56 | + | ||
57 | +Hardware configuration information | ||
58 | +---------------------------------- | ||
59 | + | ||
60 | +The ``virt`` machine automatically generates a device tree blob ("dtb") | ||
61 | +which it passes to the guest, if there is no ``-dtb`` option. This provides | ||
62 | +information about the addresses, interrupt lines and other configuration of | ||
63 | +the various devices in the system. Guest software should discover the devices | ||
64 | +that are present in the generated DTB. | ||
65 | + | ||
66 | +If users want to provide their own DTB, they can use the ``-dtb`` option. | ||
67 | +These DTBs should have the following requirements: | ||
68 | + | ||
69 | +* The number of subnodes of the /cpus node should match QEMU's ``-smp`` option | ||
70 | +* The /memory reg size should match QEMU’s selected ram_size via ``-m`` | ||
71 | +* Should contain a node for the CLINT device with a compatible string | ||
72 | + "riscv,clint0" if using with OpenSBI BIOS images | ||
73 | + | ||
74 | +Boot options | ||
75 | +------------ | ||
76 | + | ||
77 | +The ``virt`` machine can start using the standard -kernel functionality | ||
78 | +for loading a Linux kernel, a VxWorks kernel, an S-mode U-Boot bootloader | ||
79 | +with the default OpenSBI firmware image as the -bios. It also supports | ||
80 | +the recommended RISC-V bootflow: U-Boot SPL (M-mode) loads OpenSBI fw_dynamic | ||
81 | +firmware and U-Boot proper (S-mode), using the standard -bios functionality. | ||
82 | + | ||
83 | +Running Linux kernel | ||
84 | +-------------------- | ||
85 | + | ||
86 | +Linux mainline v5.12 release is tested at the time of writing. To build a | ||
87 | +Linux mainline kernel that can be booted by the ``virt`` machine in | ||
88 | +64-bit mode, simply configure the kernel using the defconfig configuration: | ||
89 | + | ||
90 | +.. code-block:: bash | ||
91 | + | ||
92 | + $ export ARCH=riscv | ||
93 | + $ export CROSS_COMPILE=riscv64-linux- | ||
94 | + $ make defconfig | ||
95 | + $ make | ||
96 | + | ||
97 | +To boot the newly built Linux kernel in QEMU with the ``virt`` machine: | ||
98 | + | ||
99 | +.. code-block:: bash | ||
100 | + | ||
101 | + $ qemu-system-riscv64 -M virt -smp 4 -m 2G \ | ||
102 | + -display none -serial stdio \ | ||
103 | + -kernel arch/riscv/boot/Image \ | ||
104 | + -initrd /path/to/rootfs.cpio \ | ||
105 | + -append "root=/dev/ram" | ||
106 | + | ||
107 | +To build a Linux mainline kernel that can be booted by the ``virt`` machine | ||
108 | +in 32-bit mode, use the rv32_defconfig configuration. A patch is required to | ||
109 | +fix the 32-bit boot issue for Linux kernel v5.12. | ||
110 | + | ||
111 | +.. code-block:: bash | ||
112 | + | ||
113 | + $ export ARCH=riscv | ||
114 | + $ export CROSS_COMPILE=riscv64-linux- | ||
115 | + $ curl https://patchwork.kernel.org/project/linux-riscv/patch/20210627135117.28641-1-bmeng.cn@gmail.com/mbox/ > riscv.patch | ||
116 | + $ git am riscv.patch | ||
117 | + $ make rv32_defconfig | ||
118 | + $ make | ||
119 | + | ||
120 | +Replace ``qemu-system-riscv64`` with ``qemu-system-riscv32`` in the command | ||
121 | +line above to boot the 32-bit Linux kernel. A rootfs image containing 32-bit | ||
122 | +applications shall be used in order for kernel to boot to user space. | ||
123 | + | ||
124 | +Running U-Boot | ||
125 | +-------------- | ||
126 | + | ||
127 | +U-Boot mainline v2021.04 release is tested at the time of writing. To build an | ||
128 | +S-mode U-Boot bootloader that can be booted by the ``virt`` machine, use | ||
129 | +the qemu-riscv64_smode_defconfig with similar commands as described above for Linux: | ||
130 | + | ||
131 | +.. code-block:: bash | ||
132 | + | ||
133 | + $ export CROSS_COMPILE=riscv64-linux- | ||
134 | + $ make qemu-riscv64_smode_defconfig | ||
135 | + | ||
136 | +Boot the 64-bit U-Boot S-mode image directly: | ||
137 | + | ||
138 | +.. code-block:: bash | ||
139 | + | ||
140 | + $ qemu-system-riscv64 -M virt -smp 4 -m 2G \ | ||
141 | + -display none -serial stdio \ | ||
142 | + -kernel /path/to/u-boot.bin | ||
143 | + | ||
144 | +To test booting U-Boot SPL which in M-mode, which in turn loads a FIT image | ||
145 | +that bundles OpenSBI fw_dynamic firmware and U-Boot proper (S-mode) together, | ||
146 | +build the U-Boot images using riscv64_spl_defconfig: | ||
147 | + | ||
148 | +.. code-block:: bash | ||
149 | + | ||
150 | + $ export CROSS_COMPILE=riscv64-linux- | ||
151 | + $ export OPENSBI=/path/to/opensbi-riscv64-generic-fw_dynamic.bin | ||
152 | + $ make qemu-riscv64_spl_defconfig | ||
153 | + | ||
154 | +The minimal QEMU commands to run U-Boot SPL are: | ||
155 | + | ||
156 | +.. code-block:: bash | ||
157 | + | ||
158 | + $ qemu-system-riscv64 -M virt -smp 4 -m 2G \ | ||
159 | + -display none -serial stdio \ | ||
160 | + -bios /path/to/u-boot-spl \ | ||
161 | + -device loader,file=/path/to/u-boot.itb,addr=0x80200000 | ||
162 | + | ||
163 | +To test 32-bit U-Boot images, switch to use qemu-riscv32_smode_defconfig and | ||
164 | +riscv32_spl_defconfig builds, and replace ``qemu-system-riscv64`` with | ||
165 | +``qemu-system-riscv32`` in the command lines above to boot the 32-bit U-Boot. | ||
166 | diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst | ||
167 | index XXXXXXX..XXXXXXX 100644 | ||
168 | --- a/docs/system/target-riscv.rst | ||
169 | +++ b/docs/system/target-riscv.rst | ||
170 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | ||
171 | riscv/microchip-icicle-kit | ||
172 | riscv/shakti-c | ||
173 | riscv/sifive_u | ||
174 | + riscv/virt | ||
175 | |||
176 | RISC-V CPU firmware | ||
177 | ------------------- | ||
178 | -- | ||
179 | 2.31.1 | ||
180 | |||
181 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Jose Martins <josemartins90@gmail.com> | ||
2 | 1 | ||
3 | The specification mandates for certain bits to be hardwired in the | ||
4 | hypervisor delegation registers. This was not being enforced. | ||
5 | |||
6 | Signed-off-by: Jose Martins <josemartins90@gmail.com> | ||
7 | Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-id: 20210522155902.374439-1-josemartins90@gmail.com | ||
10 | [ Changes by AF: | ||
11 | - Improve indentation | ||
12 | ] | ||
13 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
14 | --- | ||
15 | target/riscv/csr.c | 13 +++++++++++-- | ||
16 | 1 file changed, 11 insertions(+), 2 deletions(-) | ||
17 | |||
18 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/riscv/csr.c | ||
21 | +++ b/target/riscv/csr.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static RISCVException read_timeh(CPURISCVState *env, int csrno, | ||
23 | |||
24 | static const target_ulong delegable_ints = S_MODE_INTERRUPTS | | ||
25 | VS_MODE_INTERRUPTS; | ||
26 | +static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; | ||
27 | static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | | ||
28 | VS_MODE_INTERRUPTS; | ||
29 | static const target_ulong delegable_excps = | ||
30 | @@ -XXX,XX +XXX,XX @@ static const target_ulong delegable_excps = | ||
31 | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | | ||
32 | (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | | ||
33 | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); | ||
34 | +static const target_ulong vs_delegable_excps = delegable_excps & | ||
35 | + ~((1ULL << (RISCV_EXCP_S_ECALL)) | | ||
36 | + (1ULL << (RISCV_EXCP_VS_ECALL)) | | ||
37 | + (1ULL << (RISCV_EXCP_M_ECALL)) | | ||
38 | + (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | | ||
39 | + (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | | ||
40 | + (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | | ||
41 | + (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); | ||
42 | static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | | ||
43 | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | | ||
44 | SSTATUS_SUM | SSTATUS_MXR; | ||
45 | @@ -XXX,XX +XXX,XX @@ static RISCVException read_hedeleg(CPURISCVState *env, int csrno, | ||
46 | static RISCVException write_hedeleg(CPURISCVState *env, int csrno, | ||
47 | target_ulong val) | ||
48 | { | ||
49 | - env->hedeleg = val; | ||
50 | + env->hedeleg = val & vs_delegable_excps; | ||
51 | return RISCV_EXCP_NONE; | ||
52 | } | ||
53 | |||
54 | @@ -XXX,XX +XXX,XX @@ static RISCVException read_hideleg(CPURISCVState *env, int csrno, | ||
55 | static RISCVException write_hideleg(CPURISCVState *env, int csrno, | ||
56 | target_ulong val) | ||
57 | { | ||
58 | - env->hideleg = val; | ||
59 | + env->hideleg = val & vs_delegable_ints; | ||
60 | return RISCV_EXCP_NONE; | ||
61 | } | ||
62 | |||
63 | -- | ||
64 | 2.31.1 | ||
65 | |||
66 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Bin Meng <bin.meng@windriver.com> | ||
2 | 1 | ||
3 | This adds a new section in the documentation to demonstrate how to | ||
4 | use the new direct kernel boot feature for Microchip Icicle Kit, | ||
5 | other than the HSS bootflow, using an upstream U-Boot v2021.07 image | ||
6 | as an example. | ||
7 | |||
8 | It also updates the truth table to have a new '-dtb' column which is | ||
9 | required by direct kernel boot. | ||
10 | |||
11 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
13 | Message-id: 20210706095045.1917913-1-bmeng.cn@gmail.com | ||
14 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
15 | --- | ||
16 | docs/system/riscv/microchip-icicle-kit.rst | 54 +++++++++++++++++++--- | ||
17 | 1 file changed, 47 insertions(+), 7 deletions(-) | ||
18 | |||
19 | diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/docs/system/riscv/microchip-icicle-kit.rst | ||
22 | +++ b/docs/system/riscv/microchip-icicle-kit.rst | ||
23 | @@ -XXX,XX +XXX,XX @@ The user provided DTB should have the following requirements: | ||
24 | |||
25 | QEMU follows below truth table to select which payload to execute: | ||
26 | |||
27 | -===== ========== ======= | ||
28 | --bios -kernel payload | ||
29 | -===== ========== ======= | ||
30 | - N N HSS | ||
31 | - Y don't care HSS | ||
32 | - N Y kernel | ||
33 | -===== ========== ======= | ||
34 | +===== ========== ========== ======= | ||
35 | +-bios -kernel -dtb payload | ||
36 | +===== ========== ========== ======= | ||
37 | + N N don't care HSS | ||
38 | + Y don't care don't care HSS | ||
39 | + N Y Y kernel | ||
40 | +===== ========== ========== ======= | ||
41 | |||
42 | The memory is set to 1537 MiB by default which is the minimum required high | ||
43 | memory size by HSS. A sanity check on ram size is performed in the machine | ||
44 | @@ -XXX,XX +XXX,XX @@ HSS output is on the first serial port (stdio) and U-Boot outputs on the | ||
45 | second serial port. U-Boot will automatically load the Linux kernel from | ||
46 | the SD card image. | ||
47 | |||
48 | +Direct Kernel Boot | ||
49 | +------------------ | ||
50 | + | ||
51 | +Sometimes we just want to test booting a new kernel, and transforming the | ||
52 | +kernel image to the format required by the HSS bootflow is tedious. We can | ||
53 | +use '-kernel' for direct kernel booting just like other RISC-V machines do. | ||
54 | + | ||
55 | +In this mode, the OpenSBI fw_dynamic BIOS image for 'generic' platform is | ||
56 | +used to boot an S-mode payload like U-Boot or OS kernel directly. | ||
57 | + | ||
58 | +For example, the following commands show building a U-Boot image from U-Boot | ||
59 | +mainline v2021.07 for the Microchip Icicle Kit board: | ||
60 | + | ||
61 | +.. code-block:: bash | ||
62 | + | ||
63 | + $ export CROSS_COMPILE=riscv64-linux- | ||
64 | + $ make microchip_mpfs_icicle_defconfig | ||
65 | + | ||
66 | +Then we can boot the machine by: | ||
67 | + | ||
68 | +.. code-block:: bash | ||
69 | + | ||
70 | + $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 -m 2G \ | ||
71 | + -sd path/to/sdcard.img \ | ||
72 | + -nic user,model=cadence_gem \ | ||
73 | + -nic tap,ifname=tap,model=cadence_gem,script=no \ | ||
74 | + -display none -serial stdio \ | ||
75 | + -kernel path/to/u-boot/build/dir/u-boot.bin \ | ||
76 | + -dtb path/to/u-boot/build/dir/u-boot.dtb | ||
77 | + | ||
78 | +CAVEATS: | ||
79 | + | ||
80 | +* Check the "stdout-path" property in the /chosen node in the DTB to determine | ||
81 | + which serial port is used for the serial console, e.g.: if the console is set | ||
82 | + to the second serial port, change to use "-serial null -serial stdio". | ||
83 | +* The default U-Boot configuration uses CONFIG_OF_SEPARATE hence the ELF image | ||
84 | + ``u-boot`` cannot be passed to "-kernel" as it does not contain the DTB hence | ||
85 | + ``u-boot.bin`` has to be used which does contain one. To use the ELF image, | ||
86 | + we need to change to CONFIG_OF_EMBED or CONFIG_OF_PRIOR_STAGE. | ||
87 | + | ||
88 | .. _HSS: https://github.com/polarfire-soc/hart-software-services | ||
89 | -- | ||
90 | 2.31.1 | ||
91 | |||
92 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Bin Meng <bin.meng@windriver.com> | ||
2 | 1 | ||
3 | At present the CLINT timebase frequency is set to 10MHz on sifive_u, | ||
4 | but on the real hardware the timebase frequency is 1Mhz. | ||
5 | |||
6 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
8 | Message-id: 20210706102616.1922469-1-bmeng.cn@gmail.com | ||
9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | --- | ||
11 | hw/riscv/sifive_u.c | 7 +++++-- | ||
12 | 1 file changed, 5 insertions(+), 2 deletions(-) | ||
13 | |||
14 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/riscv/sifive_u.c | ||
17 | +++ b/hw/riscv/sifive_u.c | ||
18 | @@ -XXX,XX +XXX,XX @@ | ||
19 | |||
20 | #include <libfdt.h> | ||
21 | |||
22 | +/* CLINT timebase frequency */ | ||
23 | +#define CLINT_TIMEBASE_FREQ 1000000 | ||
24 | + | ||
25 | static const MemMapEntry sifive_u_memmap[] = { | ||
26 | [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, | ||
27 | [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, | ||
28 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, | ||
29 | |||
30 | qemu_fdt_add_subnode(fdt, "/cpus"); | ||
31 | qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", | ||
32 | - SIFIVE_CLINT_TIMEBASE_FREQ); | ||
33 | + CLINT_TIMEBASE_FREQ); | ||
34 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); | ||
35 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); | ||
36 | |||
37 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) | ||
38 | sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, | ||
39 | memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, | ||
40 | SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, | ||
41 | - SIFIVE_CLINT_TIMEBASE_FREQ, false); | ||
42 | + CLINT_TIMEBASE_FREQ, false); | ||
43 | |||
44 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { | ||
45 | return; | ||
46 | -- | ||
47 | 2.31.1 | ||
48 | |||
49 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Bin Meng <bmeng.cn@gmail.com> | ||
2 | 1 | ||
3 | Currently the firmware dynamic info (fw_dyn) is put right after | ||
4 | the reset vector, which is not 8-byte aligned on RV64. OpenSBI | ||
5 | fw_dynamic uses ld to read contents from 'struct fw_dynamic_info', | ||
6 | which expects fw_dyn to be on the 8-byte boundary, otherwise the | ||
7 | misaligned load exception may happen. Fortunately this does not | ||
8 | cause any issue on QEMU, as QEMU does support misaligned load. | ||
9 | |||
10 | RV32 does not have any issue as it is 4-byte aligned already. | ||
11 | Change to make sure it is 8-byte aligned which works for both | ||
12 | RV32 and RV64. | ||
13 | |||
14 | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> | ||
15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
16 | Message-id: 20210708143319.10441-1-bmeng.cn@gmail.com | ||
17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
18 | --- | ||
19 | hw/riscv/sifive_u.c | 5 +++-- | ||
20 | 1 file changed, 3 insertions(+), 2 deletions(-) | ||
21 | |||
22 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/hw/riscv/sifive_u.c | ||
25 | +++ b/hw/riscv/sifive_u.c | ||
26 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
27 | } | ||
28 | |||
29 | /* reset vector */ | ||
30 | - uint32_t reset_vec[11] = { | ||
31 | + uint32_t reset_vec[12] = { | ||
32 | s->msel, /* MSEL pin state */ | ||
33 | 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ | ||
34 | - 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ | ||
35 | + 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */ | ||
36 | 0xf1402573, /* csrr a0, mhartid */ | ||
37 | 0, | ||
38 | 0, | ||
39 | @@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine) | ||
40 | start_addr, /* start: .dword */ | ||
41 | start_addr_hi32, | ||
42 | fdt_load_addr, /* fdt_laddr: .dword */ | ||
43 | + 0x00000000, | ||
44 | 0x00000000, | ||
45 | /* fw_dyn: */ | ||
46 | }; | ||
47 | -- | ||
48 | 2.31.1 | ||
49 | |||
50 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Update the register layout to match the latest OpenTitan bitstream. | ||
2 | 1 | ||
3 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
4 | Reviewed-by: Bin Meng <bmeng.cn@gmail.com> | ||
5 | Message-id: 25c8377d32f3e0f0a1a862c8a5092f8a9e3f9928.1625801868.git.alistair.francis@wdc.com | ||
6 | --- | ||
7 | hw/char/ibex_uart.c | 19 ++++++++++--------- | ||
8 | 1 file changed, 10 insertions(+), 9 deletions(-) | ||
9 | |||
10 | diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c | ||
11 | index XXXXXXX..XXXXXXX 100644 | ||
12 | --- a/hw/char/ibex_uart.c | ||
13 | +++ b/hw/char/ibex_uart.c | ||
14 | @@ -XXX,XX +XXX,XX @@ REG32(INTR_STATE, 0x00) | ||
15 | FIELD(INTR_STATE, RX_OVERFLOW, 3, 1) | ||
16 | REG32(INTR_ENABLE, 0x04) | ||
17 | REG32(INTR_TEST, 0x08) | ||
18 | -REG32(CTRL, 0x0C) | ||
19 | +REG32(ALERT_TEST, 0x0C) | ||
20 | +REG32(CTRL, 0x10) | ||
21 | FIELD(CTRL, TX_ENABLE, 0, 1) | ||
22 | FIELD(CTRL, RX_ENABLE, 1, 1) | ||
23 | FIELD(CTRL, NF, 2, 1) | ||
24 | @@ -XXX,XX +XXX,XX @@ REG32(CTRL, 0x0C) | ||
25 | FIELD(CTRL, PARITY_ODD, 7, 1) | ||
26 | FIELD(CTRL, RXBLVL, 8, 2) | ||
27 | FIELD(CTRL, NCO, 16, 16) | ||
28 | -REG32(STATUS, 0x10) | ||
29 | +REG32(STATUS, 0x14) | ||
30 | FIELD(STATUS, TXFULL, 0, 1) | ||
31 | FIELD(STATUS, RXFULL, 1, 1) | ||
32 | FIELD(STATUS, TXEMPTY, 2, 1) | ||
33 | FIELD(STATUS, RXIDLE, 4, 1) | ||
34 | FIELD(STATUS, RXEMPTY, 5, 1) | ||
35 | -REG32(RDATA, 0x14) | ||
36 | -REG32(WDATA, 0x18) | ||
37 | -REG32(FIFO_CTRL, 0x1c) | ||
38 | +REG32(RDATA, 0x18) | ||
39 | +REG32(WDATA, 0x1C) | ||
40 | +REG32(FIFO_CTRL, 0x20) | ||
41 | FIELD(FIFO_CTRL, RXRST, 0, 1) | ||
42 | FIELD(FIFO_CTRL, TXRST, 1, 1) | ||
43 | FIELD(FIFO_CTRL, RXILVL, 2, 3) | ||
44 | FIELD(FIFO_CTRL, TXILVL, 5, 2) | ||
45 | -REG32(FIFO_STATUS, 0x20) | ||
46 | +REG32(FIFO_STATUS, 0x24) | ||
47 | FIELD(FIFO_STATUS, TXLVL, 0, 5) | ||
48 | FIELD(FIFO_STATUS, RXLVL, 16, 5) | ||
49 | -REG32(OVRD, 0x24) | ||
50 | -REG32(VAL, 0x28) | ||
51 | -REG32(TIMEOUT_CTRL, 0x2c) | ||
52 | +REG32(OVRD, 0x28) | ||
53 | +REG32(VAL, 0x2C) | ||
54 | +REG32(TIMEOUT_CTRL, 0x30) | ||
55 | |||
56 | static void ibex_uart_update_irqs(IbexUartState *s) | ||
57 | { | ||
58 | -- | ||
59 | 2.31.1 | ||
60 | |||
61 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
2 | Reviewed-by: Bin Meng <bmeng.cn@gmail.com> | ||
3 | Message-id: ed707782e84118e1b06a32fd79b70fecfb54ff82.1625801868.git.alistair.francis@wdc.com | ||
4 | --- | ||
5 | include/hw/riscv/opentitan.h | 1 + | ||
6 | hw/riscv/opentitan.c | 3 +++ | ||
7 | 2 files changed, 4 insertions(+) | ||
8 | 1 | ||
9 | diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h | ||
10 | index XXXXXXX..XXXXXXX 100644 | ||
11 | --- a/include/hw/riscv/opentitan.h | ||
12 | +++ b/include/hw/riscv/opentitan.h | ||
13 | @@ -XXX,XX +XXX,XX @@ enum { | ||
14 | IBEX_DEV_ALERT_HANDLER, | ||
15 | IBEX_DEV_NMI_GEN, | ||
16 | IBEX_DEV_OTBN, | ||
17 | + IBEX_DEV_PERI, | ||
18 | }; | ||
19 | |||
20 | enum { | ||
21 | diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/hw/riscv/opentitan.c | ||
24 | +++ b/hw/riscv/opentitan.c | ||
25 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = { | ||
26 | [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 }, | ||
27 | [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 }, | ||
28 | [IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 }, | ||
29 | + [IBEX_DEV_PERI] = { 0x411f0000, 0x10000 }, | ||
30 | }; | ||
31 | |||
32 | static void opentitan_board_init(MachineState *machine) | ||
33 | @@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) | ||
34 | memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size); | ||
35 | create_unimplemented_device("riscv.lowrisc.ibex.otbn", | ||
36 | memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size); | ||
37 | + create_unimplemented_device("riscv.lowrisc.ibex.peri", | ||
38 | + memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size); | ||
39 | } | ||
40 | |||
41 | static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) | ||
42 | -- | ||
43 | 2.31.1 | ||
44 | |||
45 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | OpenTitan has an alias of flash avaliable which is called virtual flash. | ||
2 | Add support for that in the QEMU model. | ||
3 | 1 | ||
4 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
5 | Reviewed-by: Bin Meng <bmeng.cn@gmail.com> | ||
6 | Message-id: c9cfbd2dd840fd0076877b8ea4d6dcfce60db5e9.1625801868.git.alistair.francis@wdc.com | ||
7 | --- | ||
8 | include/hw/riscv/opentitan.h | 2 ++ | ||
9 | hw/riscv/opentitan.c | 6 ++++++ | ||
10 | 2 files changed, 8 insertions(+) | ||
11 | |||
12 | diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/include/hw/riscv/opentitan.h | ||
15 | +++ b/include/hw/riscv/opentitan.h | ||
16 | @@ -XXX,XX +XXX,XX @@ struct LowRISCIbexSoCState { | ||
17 | |||
18 | MemoryRegion flash_mem; | ||
19 | MemoryRegion rom; | ||
20 | + MemoryRegion flash_alias; | ||
21 | }; | ||
22 | |||
23 | typedef struct OpenTitanState { | ||
24 | @@ -XXX,XX +XXX,XX @@ enum { | ||
25 | IBEX_DEV_ROM, | ||
26 | IBEX_DEV_RAM, | ||
27 | IBEX_DEV_FLASH, | ||
28 | + IBEX_DEV_FLASH_VIRTUAL, | ||
29 | IBEX_DEV_UART, | ||
30 | IBEX_DEV_GPIO, | ||
31 | IBEX_DEV_SPI, | ||
32 | diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/riscv/opentitan.c | ||
35 | +++ b/hw/riscv/opentitan.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = { | ||
37 | [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 }, | ||
38 | [IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 }, | ||
39 | [IBEX_DEV_PERI] = { 0x411f0000, 0x10000 }, | ||
40 | + [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 }, | ||
41 | }; | ||
42 | |||
43 | static void opentitan_board_init(MachineState *machine) | ||
44 | @@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) | ||
45 | /* Flash memory */ | ||
46 | memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash", | ||
47 | memmap[IBEX_DEV_FLASH].size, &error_fatal); | ||
48 | + memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), | ||
49 | + "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0, | ||
50 | + memmap[IBEX_DEV_FLASH_VIRTUAL].size); | ||
51 | memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base, | ||
52 | &s->flash_mem); | ||
53 | + memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base, | ||
54 | + &s->flash_alias); | ||
55 | |||
56 | /* PLIC */ | ||
57 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) { | ||
58 | -- | ||
59 | 2.31.1 | ||
60 | |||
61 | diff view generated by jsdifflib |