Arm changes for before softfreeze: mostly my PL061/GPIO patches,

but also a new M-profile board and various other things.

The following changes since commit 05de778b5b8ab0b402996769117b88c7ea5c7c61:

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-07-09 14:30:01 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210709

for you to fetch changes up to 05449abb1d4c5f0c69ceb3d8d03cbc75de39b646:

hw/intc: Improve formatting of MEMTX_ERROR guest error message (2021-07-09 16:09:12 +0100)

* New machine type: stm32vldiscovery

* hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write

* hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers

* virt: Fix implementation of GPIO-based powerdown/shutdown mechanism

* Correct the encoding of MDCCSR_EL0 and DBGDSCRint

* hw/intc: Improve formatting of MEMTX_ERROR guest error message

Alexandre Iooss (4):

stm32f100: Add the stm32f100 SoC

stm32vldiscovery: Add the STM32VLDISCOVERY Machine

docs/system: arm: Add stm32 boards description

tests/boot-serial-test: Add STM32VLDISCOVERY board testcase

Peter Maydell (10):

hw/gpio/pl061: Convert DPRINTF to tracepoints

hw/gpio/pl061: Clean up read/write offset handling logic

hw/gpio/pl061: Add tracepoints for register read and write

hw/gpio/pl061: Document the interface of this device

hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers

hw/gpio/pl061: Make pullup/pulldown of outputs configurable

hw/arm/virt: Make PL061 GPIO lines pulled low, not high

hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset

hw/gpio/pl061: Document a shortcoming in our implementation

hw/arm/stellaris: Expand comment about handling of OLED chipselect

Rebecca Cran (1):

hw/intc: Improve formatting of MEMTX_ERROR guest error message

Ricardo Koller (1):

hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write

hnick@vmware.com (1):

target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint

docs/system/arm/stm32.rst | 66 +++++++

docs/system/target-arm.rst | 1 +

default-configs/devices/arm-softmmu.mak | 1 +

include/hw/arm/stm32f100_soc.h | 57 ++++++

hw/arm/stellaris.c | 56 +++++-

hw/arm/stm32f100_soc.c | 182 +++++++++++++++++

hw/arm/stm32vldiscovery.c | 66 +++++++

hw/arm/virt.c | 3 +

hw/gpio/pl061.c | 341 +++++++++++++++++++++++++-------

hw/intc/arm_gicv3_cpuif.c | 4 +-

hw/intc/arm_gicv3_redist.c | 4 +-

target/arm/helper.c | 16 +-

tests/qtest/boot-serial-test.c | 37 ++++

MAINTAINERS | 13 ++

hw/arm/Kconfig | 10 +

hw/arm/meson.build | 2 +

hw/gpio/trace-events | 9 +

17 files changed, 790 insertions(+), 78 deletions(-)

create mode 100644 docs/system/arm/stm32.rst

create mode 100644 include/hw/arm/stm32f100_soc.h

create mode 100644 hw/arm/stm32f100_soc.c

create mode 100644 hw/arm/stm32vldiscovery.c

From: Rebecca Cran <rebecca@nuviainc.com>

Add a space in the message printed when gicr_read*/gicr_write* returns

MEMTX_ERROR in arm_gicv3_redist.c.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20210706211432.31902-1-rebecca@nuviainc.com

hw/intc/arm_gicv3_redist.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c

--- a/hw/intc/arm_gicv3_redist.c

+++ b/hw/intc/arm_gicv3_redist.c

@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,

if (r == MEMTX_ERROR) {

qemu_log_mask(LOG_GUEST_ERROR,

"%s: invalid guest read at offset " TARGET_FMT_plx

- "size %u\n", __func__, offset, size);

+ " size %u\n", __func__, offset, size);

trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset,

size, attrs.secure);

/* The spec requires that reserved registers are RAZ/WI;

@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,

if (r == MEMTX_ERROR) {

qemu_log_mask(LOG_GUEST_ERROR,

"%s: invalid guest write at offset " TARGET_FMT_plx

- "size %u\n", __func__, offset, size);

+ " size %u\n", __func__, offset, size);

trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data,

size, attrs.secure);

/* The spec requires that reserved registers are RAZ/WI;

2.20.1

Convert the use of the DPRINTF debug macro in the PL061 model to

use tracepoints.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

hw/gpio/pl061.c | 27 +++++++++------------------

hw/gpio/trace-events | 6 ++++++

2 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c

--- a/hw/gpio/pl061.c

+++ b/hw/gpio/pl061.c

@@ -XXX,XX +XXX,XX @@

#include "qemu/log.h"

#include "qemu/module.h"

#include "qom/object.h"

-

-//#define DEBUG_PL061 1

-

-#ifdef DEBUG_PL061

-#define DPRINTF(fmt, ...) \

-do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)

-#define BADF(fmt, ...) \

-do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)

-#else

-#define DPRINTF(fmt, ...) do {} while(0)

-#define BADF(fmt, ...) \

-do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)

-#endif

+#include "trace.h"

static const uint8_t pl061_id[12] =

{ 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };

@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)

uint8_t out;

int i;

- DPRINTF("dir = %d, data = %d\n", s->dir, s->data);

+ trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);

/* Outputs float high. */

/* FIXME: This is board dependent. */

@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)

for (i = 0; i < N_GPIOS; i++) {

mask = 1 << i;

if (changed & mask) {

- DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);

- qemu_set_irq(s->out[i], (out & mask) != 0);

+ int level = (out & mask) != 0;

+ trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);

+ qemu_set_irq(s->out[i], level);

}

@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)

for (i = 0; i < N_GPIOS; i++) {

mask = 1 << i;

if (changed & mask) {

- DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);

+ trace_pl061_input_change(DEVICE(s)->canonical_path, i,

+ (s->data & mask) != 0);

if (!(s->isense & mask)) {

/* Edge interrupt */

@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)

/* Level interrupt */

s->istate |= ~(s->data ^ s->iev) & s->isense;

- DPRINTF("istate = %02X\n", s->istate);

+ trace_pl061_update_istate(DEVICE(s)->canonical_path,

+ s->istate, s->im, (s->istate & s->im) != 0);

qemu_set_irq(s->irq, (s->istate & s->im) != 0);

}

diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/gpio/trace-events

+++ b/hw/gpio/trace-events

@@ -XXX,XX +XXX,XX @@ nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x

nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64

nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64

+# pl061.c

+pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"

+pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"

+pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"

+pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"

+

# sifive_gpio.c

sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64

sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64

2.20.1

Currently the pl061_read() and pl061_write() functions handle offsets

using a combination of three if() statements and a switch(). Clean

this up to use just a switch, using case ranges.

This requires that instead of catching accesses to the luminary-only

registers on a stock PL061 via a check on s->rsvd_start we use

an "is this luminary?" check in the cases for each luminary-only

register.

hw/gpio/pl061.c | 104 ++++++++++++++++++++++++++++++++++++------------

1 file changed, 79 insertions(+), 25 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c

--- a/hw/gpio/pl061.c

+++ b/hw/gpio/pl061.c

@@ -XXX,XX +XXX,XX @@ struct PL061State {

qemu_irq irq;

qemu_irq out[N_GPIOS];

const unsigned char *id;

- uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */

};

static const VMStateDescription vmstate_pl061 = {

@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,

{

PL061State *s = (PL061State *)opaque;

- if (offset < 0x400) {

- return s->data & (offset >> 2);

- }

- if (offset >= s->rsvd_start && offset <= 0xfcc) {

- goto err_out;

- }

- if (offset >= 0xfd0 && offset < 0x1000) {

- return s->id[(offset - 0xfd0) >> 2];

- }

switch (offset) {

+ case 0x0 ... 0x3ff: /* Data */

+ return s->data & (offset >> 2);

case 0x400: /* Direction */

return s->dir;

case 0x404: /* Interrupt sense */

@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,

case 0x420: /* Alternate function select */

return s->afsel;

case 0x500: /* 2mA drive */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

return s->dr2r;

case 0x504: /* 4mA drive */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

return s->dr4r;

case 0x508: /* 8mA drive */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

return s->dr8r;

case 0x50c: /* Open drain */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

return s->odr;

case 0x510: /* Pull-up */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

return s->pur;

case 0x514: /* Pull-down */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

return s->pdr;

case 0x518: /* Slew rate control */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

return s->slr;

case 0x51c: /* Digital enable */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

return s->den;

case 0x520: /* Lock */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

return s->locked;

case 0x524: /* Commit */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

return s->cr;

case 0x528: /* Analog mode select */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

return s->amsel;

+ case 0xfd0 ... 0xfff: /* ID registers */

+ return s->id[(offset - 0xfd0) >> 2];

default:

+ bad_offset:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "pl061_read: Bad offset %x\n", (int)offset);

break;

}

-err_out:

- qemu_log_mask(LOG_GUEST_ERROR,

- "pl061_read: Bad offset %x\n", (int)offset);

return 0;

}

@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,

PL061State *s = (PL061State *)opaque;

uint8_t mask;

- if (offset < 0x400) {

+ switch (offset) {

+ case 0 ... 0x3ff:

mask = (offset >> 2) & s->dir;

s->data = (s->data & ~mask) | (value & mask);

pl061_update(s);

return;

- }

- if (offset >= s->rsvd_start) {

- goto err_out;

- }

- switch (offset) {

case 0x400: /* Direction */

s->dir = value & 0xff;

break;

@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,

s->afsel = (s->afsel & ~mask) | (value & mask);

break;

case 0x500: /* 2mA drive */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

s->dr2r = value & 0xff;

break;

case 0x504: /* 4mA drive */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

s->dr4r = value & 0xff;

break;

case 0x508: /* 8mA drive */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

s->dr8r = value & 0xff;

break;

case 0x50c: /* Open drain */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

s->odr = value & 0xff;

break;

case 0x510: /* Pull-up */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

s->pur = value & 0xff;

break;

case 0x514: /* Pull-down */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

s->pdr = value & 0xff;

break;

case 0x518: /* Slew rate control */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

s->slr = value & 0xff;

break;

case 0x51c: /* Digital enable */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

s->den = value & 0xff;

break;

case 0x520: /* Lock */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

s->locked = (value != 0xacce551);

break;

case 0x524: /* Commit */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

if (!s->locked)

s->cr = value & 0xff;

break;

case 0x528:

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

s->amsel = value & 0xff;

break;

default:

- goto err_out;

+ bad_offset:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "pl061_write: Bad offset %x\n", (int)offset);

+ return;

}

pl061_update(s);

return;

-err_out:

- qemu_log_mask(LOG_GUEST_ERROR,

- "pl061_write: Bad offset %x\n", (int)offset);

}

static void pl061_reset(DeviceState *dev)

@@ -XXX,XX +XXX,XX @@ static void pl061_luminary_init(Object *obj)

PL061State *s = PL061(obj);

s->id = pl061_id_luminary;

- s->rsvd_start = 0x52c;

}

static void pl061_init(Object *obj)

@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)

SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

s->id = pl061_id;

- s->rsvd_start = 0x424;

memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);

sysbus_init_mmio(sbd, &s->iomem);

2.20.1

From: Alexandre Iooss <erdnaxe@crans.org>

This SoC is similar to stm32f205 SoC.

This will be used by the STM32VLDISCOVERY to create a machine.

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20210617165647.2575955-2-erdnaxe@crans.org

include/hw/arm/stm32f100_soc.h | 57 +++++++++++

hw/arm/stm32f100_soc.c | 182 +++++++++++++++++++++++++++++++++

MAINTAINERS | 6 ++

hw/arm/Kconfig | 6 ++

hw/arm/meson.build | 1 +

5 files changed, 252 insertions(+)

create mode 100644 include/hw/arm/stm32f100_soc.h

create mode 100644 hw/arm/stm32f100_soc.c

diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/arm/stm32f100_soc.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * STM32F100 SoC

+ *

+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

+

+#ifndef HW_ARM_STM32F100_SOC_H

+#define HW_ARM_STM32F100_SOC_H

+

+#include "hw/char/stm32f2xx_usart.h"

+#include "hw/ssi/stm32f2xx_spi.h"

+#include "hw/arm/armv7m.h"

+#include "qom/object.h"

+

+#define TYPE_STM32F100_SOC "stm32f100-soc"

+OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)

+

+#define STM_NUM_USARTS 3

+#define STM_NUM_SPIS 2

+

+#define FLASH_BASE_ADDRESS 0x08000000

+#define FLASH_SIZE (128 * 1024)

+#define SRAM_BASE_ADDRESS 0x20000000

+#define SRAM_SIZE (8 * 1024)

+

+struct STM32F100State {

+ /*< private >*/

+ SysBusDevice parent_obj;

+

+ /*< public >*/

+ char *cpu_type;

+

+ ARMv7MState armv7m;

+

+ STM32F2XXUsartState usart[STM_NUM_USARTS];

+ STM32F2XXSPIState spi[STM_NUM_SPIS];

+};

+

+#endif

diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/arm/stm32f100_soc.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * STM32F100 SoC

+ *

+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>

+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>

+ *

+ * Permission is hereby granted, free of charge, to any person obtaining a copy

+ * of this software and associated documentation files (the "Software"), to deal

+ * in the Software without restriction, including without limitation the rights

+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

+ * copies of the Software, and to permit persons to whom the Software is

+ * furnished to do so, subject to the following conditions:

+ *

+ * The above copyright notice and this permission notice shall be included in

+ * all copies or substantial portions of the Software.

+ *

+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

+ * THE SOFTWARE.

+ */

+

+#include "qemu/osdep.h"

+#include "qapi/error.h"

+#include "qemu/module.h"

+#include "hw/arm/boot.h"

+#include "exec/address-spaces.h"

+#include "hw/arm/stm32f100_soc.h"

+#include "hw/qdev-properties.h"

+#include "hw/misc/unimp.h"

+#include "sysemu/sysemu.h"

+

+/* stm32f100_soc implementation is derived from stm32f205_soc */

+

+static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,

+ 0x40004800 };

+static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };

+

+static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39};

+static const int spi_irq[STM_NUM_SPIS] = {35, 36};

+

+static void stm32f100_soc_initfn(Object *obj)

+ STM32F100State *s = STM32F100_SOC(obj);

+ int i;

+

+ object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);

+

+ for (i = 0; i < STM_NUM_USARTS; i++) {

+ object_initialize_child(obj, "usart[*]", &s->usart[i],

+ TYPE_STM32F2XX_USART);

+ }

+

+ for (i = 0; i < STM_NUM_SPIS; i++) {

+ object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);

+static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)

+{

+ STM32F100State *s = STM32F100_SOC(dev_soc);

+ DeviceState *dev, *armv7m;

+ SysBusDevice *busdev;

+ int i;

+

+ MemoryRegion *system_memory = get_system_memory();

+ MemoryRegion *sram = g_new(MemoryRegion, 1);

+ MemoryRegion *flash = g_new(MemoryRegion, 1);

+ MemoryRegion *flash_alias = g_new(MemoryRegion, 1);

+

+ /*

+ * Init flash region

+ * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0

+ */

+ memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",

+ FLASH_SIZE, &error_fatal);

+ memory_region_init_alias(flash_alias, OBJECT(dev_soc),

+ "STM32F100.flash.alias", flash, 0, FLASH_SIZE);

+ memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);

+ memory_region_add_subregion(system_memory, 0, flash_alias);

+

+ /* Init SRAM region */

+ memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,

+ &error_fatal);

+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);

+

+ /* Init ARMv7m */

+ armv7m = DEVICE(&s->armv7m);

+ qdev_prop_set_uint32(armv7m, "num-irq", 61);

+ qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);

+ qdev_prop_set_bit(armv7m, "enable-bitband", true);

+ object_property_set_link(OBJECT(&s->armv7m), "memory",

+ OBJECT(get_system_memory()), &error_abort);

+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {

+ return;

+ }

+

+ /* Attach UART (uses USART registers) and USART controllers */

+ for (i = 0; i < STM_NUM_USARTS; i++) {

+ dev = DEVICE(&(s->usart[i]));

+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));

+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {

+ return;

+ }

+ busdev = SYS_BUS_DEVICE(dev);

+ sysbus_mmio_map(busdev, 0, usart_addr[i]);

+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));

+ }

+

+ /* SPI 1 and 2 */

+ for (i = 0; i < STM_NUM_SPIS; i++) {

+ dev = DEVICE(&(s->spi[i]));

+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {

+ return;

+ }

+ busdev = SYS_BUS_DEVICE(dev);

+ sysbus_mmio_map(busdev, 0, spi_addr[i]);

+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));

+ }

+

+ create_unimplemented_device("timer[2]", 0x40000000, 0x400);

+ create_unimplemented_device("timer[3]", 0x40000400, 0x400);

+ create_unimplemented_device("timer[4]", 0x40000800, 0x400);

+ create_unimplemented_device("timer[6]", 0x40001000, 0x400);

+ create_unimplemented_device("timer[7]", 0x40001400, 0x400);

+ create_unimplemented_device("RTC", 0x40002800, 0x400);

+ create_unimplemented_device("WWDG", 0x40002C00, 0x400);

+ create_unimplemented_device("IWDG", 0x40003000, 0x400);

+ create_unimplemented_device("I2C1", 0x40005400, 0x400);

+ create_unimplemented_device("I2C2", 0x40005800, 0x400);

+ create_unimplemented_device("BKP", 0x40006C00, 0x400);

+ create_unimplemented_device("PWR", 0x40007000, 0x400);

+ create_unimplemented_device("DAC", 0x40007400, 0x400);

+ create_unimplemented_device("CEC", 0x40007800, 0x400);

+ create_unimplemented_device("AFIO", 0x40010000, 0x400);

+ create_unimplemented_device("EXTI", 0x40010400, 0x400);

+ create_unimplemented_device("GPIOA", 0x40010800, 0x400);

+ create_unimplemented_device("GPIOB", 0x40010C00, 0x400);

+ create_unimplemented_device("GPIOC", 0x40011000, 0x400);

+ create_unimplemented_device("GPIOD", 0x40011400, 0x400);

+ create_unimplemented_device("GPIOE", 0x40011800, 0x400);

+ create_unimplemented_device("ADC1", 0x40012400, 0x400);

+ create_unimplemented_device("timer[1]", 0x40012C00, 0x400);

+ create_unimplemented_device("timer[15]", 0x40014000, 0x400);

+ create_unimplemented_device("timer[16]", 0x40014400, 0x400);

+ create_unimplemented_device("timer[17]", 0x40014800, 0x400);

+ create_unimplemented_device("DMA", 0x40020000, 0x400);

+ create_unimplemented_device("RCC", 0x40021000, 0x400);

+ create_unimplemented_device("Flash Int", 0x40022000, 0x400);

+ create_unimplemented_device("CRC", 0x40023000, 0x400);

+}

+

+static Property stm32f100_soc_properties[] = {

+ DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),

+ DEFINE_PROP_END_OF_LIST(),

+};

+

+static void stm32f100_soc_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+

+ dc->realize = stm32f100_soc_realize;

+ device_class_set_props(dc, stm32f100_soc_properties);

+}

+

+static const TypeInfo stm32f100_soc_info = {

+ .name = TYPE_STM32F100_SOC,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(STM32F100State),

+ .instance_init = stm32f100_soc_initfn,

+ .class_init = stm32f100_soc_class_init,

+};

+

+static void stm32f100_soc_types(void)

+{

+ type_register_static(&stm32f100_soc_info);

+}

+

+type_init(stm32f100_soc_types)

diff --git a/MAINTAINERS b/MAINTAINERS

index XXXXXXX..XXXXXXX 100644

--- a/MAINTAINERS

+++ b/MAINTAINERS

@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org

S: Maintained

F: hw/arm/virt-acpi-build.c

+STM32F100

+M: Alexandre Iooss <erdnaxe@crans.org>

+L: qemu-arm@nongnu.org

+S: Maintained

+F: hw/arm/stm32f100_soc.c

+

STM32F205

M: Alistair Francis <alistair@alistair23.me>

M: Peter Maydell <peter.maydell@linaro.org>

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/Kconfig

+++ b/hw/arm/Kconfig

@@ -XXX,XX +XXX,XX @@ config RASPI

select SDHCI

select USB_DWC2

+config STM32F100_SOC

+ bool

+ select ARM_V7M

+ select STM32F2XX_USART

+ select STM32F2XX_SPI

+

config STM32F205_SOC

bool

select ARM_V7M

diff --git a/hw/arm/meson.build b/hw/arm/meson.build

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/meson.build

+++ b/hw/arm/meson.build

@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))

arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))

arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))

arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c'))

+arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))

arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))

arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))

arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))

2.20.1

The PL061 GPIO does not itself include pullup or pulldown resistors

to set the value of a GPIO line treated as an output when it is

configured as an input (ie when the PL061 itself is not driving it).

In real hardware it is up to the board to add suitable pullups or

pulldowns. Currently our implementation hardwires this to "outputs

pulled high", which is correct for some boards (eg the realview ones:

see figure 3-29 in the "RealView Platform Baseboard for ARM926EJ-S

User Guide" DUI0224I), but wrong for others.

In particular, the wiring in the 'virt' board and the gpio-pwr device

assumes that wires should be pulled low, because otherwise the

pull-to-high will trigger a shutdown or reset action. (The only

reason this doesn't happen immediately on startup is due to another

bug in the PL061, where we don't assert the GPIOs to the correct

value on reset, but will do so as soon as the guest touches a

register and pl061_update() gets called.)

Add properties to the pl061 so the board can configure whether it

wants GPIO lines to have pullup, pulldown, or neither.

hw/gpio/pl061.c | 51 +++++++++++++++++++++++++++++++++++++++++++++----

1 file changed, 47 insertions(+), 4 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c

--- a/hw/gpio/pl061.c

+++ b/hw/gpio/pl061.c

@@ -XXX,XX +XXX,XX @@

* + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lines

* + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as

* outputs

+ * + QOM property "pullups": an integer defining whether non-floating lines

+ * configured as inputs should be pulled up to logical 1 (ie whether in

+ * real hardware they have a pullup resistor on the line out of the PL061).

+ * This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should

+ * be pulled high, bit 1 configures line 1, and so on. The default is 0xff,

+ * indicating that all GPIO lines are pulled up to logical 1.

+ * + QOM property "pulldowns": an integer defining whether non-floating lines

+ * configured as inputs should be pulled down to logical 0 (ie whether in

+ * real hardware they have a pulldown resistor on the line out of the PL061).

+ * This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should

+ * be pulled low, bit 1 configures line 1, and so on. The default is 0x0.

+ * It is an error to set a bit in both "pullups" and "pulldowns". If a bit

+ * is 0 in both, then the line is considered to be floating, and it will

+ * not have qemu_set_irq() called on it when it is configured as an input.

*/

#include "qemu/osdep.h"

#include "hw/irq.h"

#include "hw/sysbus.h"

+#include "hw/qdev-properties.h"

#include "migration/vmstate.h"

+#include "qapi/error.h"

#include "qemu/log.h"

#include "qemu/module.h"

#include "qom/object.h"

@@ -XXX,XX +XXX,XX @@ struct PL061State {

qemu_irq irq;

qemu_irq out[N_GPIOS];

const unsigned char *id;

+ /* Properties, for non-Luminary PL061 */

+ uint32_t pullups;

+ uint32_t pulldowns;

};

static const VMStateDescription vmstate_pl061 = {

@@ -XXX,XX +XXX,XX @@ static uint8_t pl061_floating(PL061State *s)

*/

floating = ~(s->pur | s->pdr);

} else {

- /* Assume outputs are pulled high. FIXME: this is board dependent. */

- floating = 0;

+ floating = ~(s->pullups | s->pulldowns);

}

return floating & ~s->dir;