Arm changes for before softfreeze: mostly my PL061/GPIO patches,

but also a new M-profile board and various other things.

thanks

-- PMM

The following changes since commit 05de778b5b8ab0b402996769117b88c7ea5c7c61:

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-07-09 14:30:01 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210709

for you to fetch changes up to 05449abb1d4c5f0c69ceb3d8d03cbc75de39b646:

hw/intc: Improve formatting of MEMTX_ERROR guest error message (2021-07-09 16:09:12 +0100)

* New machine type: stm32vldiscovery

* hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write

* hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers

* virt: Fix implementation of GPIO-based powerdown/shutdown mechanism

* Correct the encoding of MDCCSR_EL0 and DBGDSCRint

* hw/intc: Improve formatting of MEMTX_ERROR guest error message

Alexandre Iooss (4):

stm32f100: Add the stm32f100 SoC

stm32vldiscovery: Add the STM32VLDISCOVERY Machine

docs/system: arm: Add stm32 boards description

tests/boot-serial-test: Add STM32VLDISCOVERY board testcase

Peter Maydell (10):

hw/gpio/pl061: Convert DPRINTF to tracepoints

hw/gpio/pl061: Clean up read/write offset handling logic

hw/gpio/pl061: Add tracepoints for register read and write

hw/gpio/pl061: Document the interface of this device

hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers

hw/gpio/pl061: Make pullup/pulldown of outputs configurable

hw/arm/virt: Make PL061 GPIO lines pulled low, not high

hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset

hw/gpio/pl061: Document a shortcoming in our implementation

hw/arm/stellaris: Expand comment about handling of OLED chipselect

Rebecca Cran (1):

hw/intc: Improve formatting of MEMTX_ERROR guest error message

Ricardo Koller (1):

hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write

hnick@vmware.com (1):

target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint

docs/system/arm/stm32.rst | 66 +++++++

docs/system/target-arm.rst | 1 +

default-configs/devices/arm-softmmu.mak | 1 +

include/hw/arm/stm32f100_soc.h | 57 ++++++

hw/arm/stellaris.c | 56 +++++-

hw/arm/stm32f100_soc.c | 182 +++++++++++++++++

hw/arm/stm32vldiscovery.c | 66 +++++++

hw/arm/virt.c | 3 +

hw/gpio/pl061.c | 341 +++++++++++++++++++++++++-------

hw/intc/arm_gicv3_cpuif.c | 4 +-

hw/intc/arm_gicv3_redist.c | 4 +-

target/arm/helper.c | 16 +-

tests/qtest/boot-serial-test.c | 37 ++++

MAINTAINERS | 13 ++

hw/arm/Kconfig | 10 +

hw/arm/meson.build | 2 +

hw/gpio/trace-events | 9 +

17 files changed, 790 insertions(+), 78 deletions(-)

create mode 100644 docs/system/arm/stm32.rst

create mode 100644 include/hw/arm/stm32f100_soc.h

create mode 100644 hw/arm/stm32f100_soc.c

create mode 100644 hw/arm/stm32vldiscovery.c

From: "hnick@vmware.com" <hnick@vmware.com>

Signed-off-by: Nick Hudson <hnick@vmware.com>

target/arm/helper.c | 16 +++++++++++++---

1 file changed, 13 insertions(+), 3 deletions(-)

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {

.access = PL1_RW, .accessfn = access_tda,

.fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),

.resetvalue = 0 },

- /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.

+ /*

+ * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external

+ * Debug Communication Channel is not implemented.

+ */

+ { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,

+ .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,

+ .access = PL0_R, .accessfn = access_tda,

+ .type = ARM_CP_CONST, .resetvalue = 0 },

+ /*

+ * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as

+ * it is unlikely a guest will care.

* We don't implement the configurable EL0 access.

*/

- { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,

- .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,

+ { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32,

+ .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,

.type = ARM_CP_ALIAS,

.access = PL1_R, .accessfn = access_tda,

.fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },

2.20.1

The Luminary variant of the PL061 has registers GPIOPUR and GPIOPDR

which lets the guest configure whether the GPIO lines are pull-up,

pull-down, or truly floating. Instead of assuming all lines are pulled

high, honour the PUR and PDR registers.

For the plain PL061, continue to assume that lines have an external

pull-up resistor, as we did before.

The stellaris board actually relies on this behaviour -- the CD line

of the ssd0323 display device is connected to GPIO output C7, and it

is only because of a different bug which we're about to fix that we

weren't incorrectly driving this line high on reset and putting the

ssd0323 into data mode.

hw/gpio/pl061.c | 58 +++++++++++++++++++++++++++++++++++++++++---

hw/gpio/trace-events | 2 +-

2 files changed, 55 insertions(+), 5 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c

--- a/hw/gpio/pl061.c

+++ b/hw/gpio/pl061.c

@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl061 = {

}

+static uint8_t pl061_floating(PL061State *s)

+ /*

+ * Return mask of bits which correspond to pins configured as inputs

+ * and which are floating (neither pulled up to 1 nor down to 0).

+ */

+ uint8_t floating;

+

+ if (s->id == pl061_id_luminary) {

+ /*

+ * If both PUR and PDR bits are clear, there is neither a pullup

+ * nor a pulldown in place, and the output truly floats.

+ */

+ floating = ~(s->pur | s->pdr);

+ } else {

+ /* Assume outputs are pulled high. FIXME: this is board dependent. */

+ floating = 0;

+ }

+ return floating & ~s->dir;

+static uint8_t pl061_pullups(PL061State *s)

+ /*

+ * Return mask of bits which correspond to pins configured as inputs

+ * and which are pulled up to 1.

+ */

+ uint8_t pullups;

+

+ if (s->id == pl061_id_luminary) {

+ /*

+ * The Luminary variant of the PL061 has an extra registers which

+ * the guest can use to configure whether lines should be pullup

+ * or pulldown.

+ */

+ pullups = s->pur;

+ } else {

+ /* Assume outputs are pulled high. FIXME: this is board dependent. */

+ pullups = 0xff;

+ }

+ return pullups & ~s->dir;

static void pl061_update(PL061State *s)

uint8_t changed;

uint8_t mask;

uint8_t out;

int i;

+ uint8_t pullups = pl061_pullups(s);

+ uint8_t floating = pl061_floating(s);

- trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);

+ trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data,

+ pullups, floating);

- /* Outputs float high. */

- /* FIXME: This is board dependent. */

- out = (s->data & s->dir) | ~s->dir;

+ * Pins configured as output are driven from the data register;

+ * otherwise if they're pulled up they're 1, and if they're floating

+ * then we give them the same value they had previously, so we don't

+ * report any change to the other end.

+ out = (s->data & s->dir) | pullups | (s->old_out_data & floating);

changed = s->old_out_data ^ out;

if (changed) {

s->old_out_data = out;

diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/gpio/trace-events

+++ b/hw/gpio/trace-events

@@ -XXX,XX +XXX,XX @@ nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64

nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64

# pl061.c

-pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"

+pl061_update(const char *id, uint32_t dir, uint32_t data, uint32_t pullups, uint32_t floating) "%s GPIODIR 0x%x GPIODATA 0x%x pullups 0x%x floating 0x%x"

pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"

pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"

pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"

2.20.1

The Luminary PL061s in the Stellaris LM3S9695 don't all have the same

reset value for GPIOPUR. We can get away with not letting the board

configure the PUR reset value because we don't actually wire anything

up to the lines which should reset to pull-up. Add a comment noting

this omission.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

hw/gpio/pl061.c | 9 +++++++++

1 file changed, 9 insertions(+)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c

--- a/hw/gpio/pl061.c

+++ b/hw/gpio/pl061.c

@@ -XXX,XX +XXX,XX @@ static void pl061_enter_reset(Object *obj, ResetType type)

trace_pl061_reset(DEVICE(s)->canonical_path);

/* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */

+ * FIXME: For the LM3S6965, not all of the PL061 instances have the

+ * same reset values for GPIOPUR, GPIOAFSEL and GPIODEN, so in theory

+ * we should allow the board to configure these via properties.

+ * In practice, we don't wire anything up to the affected GPIO lines

+ * (PB7, PC0, PC1, PC2, PC3 -- they're used for JTAG), so we can

+ * get away with this inaccuracy.

s->data = 0;

s->old_in_data = 0;

s->dir = 0;

2.20.1

Add tracepoints for reads and writes to the PL061 registers. This requires

restructuring pl061_read() to only return after the tracepoint, rather

than having lots of early-returns.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

hw/gpio/pl061.c | 70 ++++++++++++++++++++++++++++++--------------

hw/gpio/trace-events | 2 ++

2 files changed, 50 insertions(+), 22 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c

--- a/hw/gpio/pl061.c

+++ b/hw/gpio/pl061.c

@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,

unsigned size)

{

PL061State *s = (PL061State *)opaque;

+ uint64_t r = 0;

switch (offset) {

case 0x0 ... 0x3ff: /* Data */

- return s->data & (offset >> 2);

+ r = s->data & (offset >> 2);

+ break;

case 0x400: /* Direction */

- return s->dir;

+ r = s->dir;

+ break;

case 0x404: /* Interrupt sense */

- return s->isense;

+ r = s->isense;

+ break;

case 0x408: /* Interrupt both edges */

- return s->ibe;

+ r = s->ibe;

+ break;

case 0x40c: /* Interrupt event */

- return s->iev;

+ r = s->iev;

+ break;

case 0x410: /* Interrupt mask */

- return s->im;

+ r = s->im;

+ break;

case 0x414: /* Raw interrupt status */

- return s->istate;

+ r = s->istate;

+ break;

case 0x418: /* Masked interrupt status */

- return s->istate & s->im;

+ r = s->istate & s->im;

+ break;

case 0x420: /* Alternate function select */

- return s->afsel;

+ r = s->afsel;

+ break;

case 0x500: /* 2mA drive */

if (s->id != pl061_id_luminary) {

goto bad_offset;

}

- return s->dr2r;

+ r = s->dr2r;

+ break;

case 0x504: /* 4mA drive */

if (s->id != pl061_id_luminary) {

goto bad_offset;

}

- return s->dr4r;

+ r = s->dr4r;

+ break;

case 0x508: /* 8mA drive */

if (s->id != pl061_id_luminary) {

goto bad_offset;

}

- return s->dr8r;

+ r = s->dr8r;

+ break;

case 0x50c: /* Open drain */

if (s->id != pl061_id_luminary) {

goto bad_offset;

}

- return s->odr;

+ r = s->odr;

+ break;

case 0x510: /* Pull-up */

if (s->id != pl061_id_luminary) {

goto bad_offset;

}

- return s->pur;

+ r = s->pur;

+ break;

case 0x514: /* Pull-down */

if (s->id != pl061_id_luminary) {

goto bad_offset;

}

- return s->pdr;

+ r = s->pdr;

+ break;

case 0x518: /* Slew rate control */

if (s->id != pl061_id_luminary) {

goto bad_offset;

}

- return s->slr;

+ r = s->slr;

+ break;

case 0x51c: /* Digital enable */

if (s->id != pl061_id_luminary) {

goto bad_offset;

}

- return s->den;

+ r = s->den;

+ break;

case 0x520: /* Lock */

if (s->id != pl061_id_luminary) {

goto bad_offset;

}

- return s->locked;

+ r = s->locked;

+ break;

case 0x524: /* Commit */

if (s->id != pl061_id_luminary) {

goto bad_offset;

}

- return s->cr;

+ r = s->cr;

+ break;

case 0x528: /* Analog mode select */

if (s->id != pl061_id_luminary) {

goto bad_offset;

}

- return s->amsel;

+ r = s->amsel;

+ break;

case 0xfd0 ... 0xfff: /* ID registers */

- return s->id[(offset - 0xfd0) >> 2];

+ r = s->id[(offset - 0xfd0) >> 2];

+ break;

default:

bad_offset:

qemu_log_mask(LOG_GUEST_ERROR,

"pl061_read: Bad offset %x\n", (int)offset);

break;

}

- return 0;

+

+ trace_pl061_read(DEVICE(s)->canonical_path, offset, r);

+ return r;

static void pl061_write(void *opaque, hwaddr offset,

@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,

PL061State *s = (PL061State *)opaque;

uint8_t mask;

+ trace_pl061_write(DEVICE(s)->canonical_path, offset, value);

+

switch (offset) {

case 0 ... 0x3ff:

mask = (offset >> 2) & s->dir;

diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events

--- a/hw/gpio/trace-events

+++ b/hw/gpio/trace-events

@@ -XXX,XX +XXX,XX @@ pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIOD

pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"

pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"

pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"

+pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64

+pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64

# sifive_gpio.c

sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64

2.20.1