hw/riscv/sifive_u.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
From: Bin Meng <bin.meng@windriver.com>
At present the CLINT timebase frequency is set to 10MHz on sifive_u,
but on the real hardware the timebase frequency is 1Mhz.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 273c86418c..e75ca38783 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -62,6 +62,9 @@
#include <libfdt.h>
+/* CLINT timebase frequency */
+#define CLINT_TIMEBASE_FREQ 1000000
+
static const MemMapEntry sifive_u_memmap[] = {
[SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
[SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
@@ -165,7 +168,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/cpus");
qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
- SIFIVE_CLINT_TIMEBASE_FREQ);
+ CLINT_TIMEBASE_FREQ);
qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
@@ -847,7 +850,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
- SIFIVE_CLINT_TIMEBASE_FREQ, false);
+ CLINT_TIMEBASE_FREQ, false);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
return;
--
2.25.1
On Tue, Jul 6, 2021 at 8:48 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > At present the CLINT timebase frequency is set to 10MHz on sifive_u, > but on the real hardware the timebase frequency is 1Mhz. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > > hw/riscv/sifive_u.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 273c86418c..e75ca38783 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -62,6 +62,9 @@ > > #include <libfdt.h> > > +/* CLINT timebase frequency */ > +#define CLINT_TIMEBASE_FREQ 1000000 > + > static const MemMapEntry sifive_u_memmap[] = { > [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, > [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, > @@ -165,7 +168,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, > > qemu_fdt_add_subnode(fdt, "/cpus"); > qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", > - SIFIVE_CLINT_TIMEBASE_FREQ); > + CLINT_TIMEBASE_FREQ); > qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); > qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); > > @@ -847,7 +850,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) > sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, > memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, > SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, > - SIFIVE_CLINT_TIMEBASE_FREQ, false); > + CLINT_TIMEBASE_FREQ, false); > > if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { > return; > -- > 2.25.1 > >
On Tue, Jul 6, 2021 at 8:48 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > At present the CLINT timebase frequency is set to 10MHz on sifive_u, > but on the real hardware the timebase frequency is 1Mhz. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > hw/riscv/sifive_u.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 273c86418c..e75ca38783 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -62,6 +62,9 @@ > > #include <libfdt.h> > > +/* CLINT timebase frequency */ > +#define CLINT_TIMEBASE_FREQ 1000000 > + > static const MemMapEntry sifive_u_memmap[] = { > [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, > [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, > @@ -165,7 +168,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, > > qemu_fdt_add_subnode(fdt, "/cpus"); > qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", > - SIFIVE_CLINT_TIMEBASE_FREQ); > + CLINT_TIMEBASE_FREQ); > qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); > qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); > > @@ -847,7 +850,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) > sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, > memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, > SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, > - SIFIVE_CLINT_TIMEBASE_FREQ, false); > + CLINT_TIMEBASE_FREQ, false); > > if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { > return; > -- > 2.25.1 > >
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