The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:

Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702

for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:

target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)

* more MVE instructions

* hw/gpio/gpio_pwr: use shutdown function for reboot

* target/arm: Check NaN mode before silencing NaN

* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine

* hw/arm: Add basic power management to raspi.

* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc

Joe Komlodi (1):

target/arm: Check NaN mode before silencing NaN

Maxim Uvarov (1):

hw/gpio/gpio_pwr: use shutdown function for reboot

Nolan Leake (1):

hw/arm: Add basic power management to raspi.

Patrick Venture (2):

docs/system/arm: Add quanta-q7l1-bmc reference

docs/system/arm: Add quanta-gbs-bmc reference

Peter Maydell (18):

target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation

target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH

target/arm: Make asimd_imm_const() public

target/arm: Use asimd_imm_const for A64 decode

target/arm: Use dup_const() instead of bitfield_replicate()

target/arm: Implement MVE logical immediate insns

target/arm: Implement MVE vector shift left by immediate insns

target/arm: Implement MVE vector shift right by immediate insns

target/arm: Implement MVE VSHLL

target/arm: Implement MVE VSRI, VSLI

target/arm: Implement MVE VSHRN, VRSHRN

target/arm: Implement MVE saturating narrowing shifts

target/arm: Implement MVE VSHLC

target/arm: Implement MVE VADDLV

target/arm: Implement MVE long shifts by immediate

target/arm: Implement MVE long shifts by register

target/arm: Implement MVE shifts by immediate

target/arm: Implement MVE shifts by register

Philippe Mathieu-Daudé (1):

tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine

docs/system/arm/aspeed.rst | 1 +

docs/system/arm/nuvoton.rst | 5 +-

include/hw/arm/bcm2835_peripherals.h | 3 +-

include/hw/misc/bcm2835_powermgt.h | 29 ++

target/arm/helper-mve.h | 108 +++++++

target/arm/translate.h | 41 +++

target/arm/mve.decode | 177 ++++++++++-

target/arm/t32.decode | 71 ++++-

hw/arm/bcm2835_peripherals.c | 13 +-

hw/gpio/gpio_pwr.c | 2 +-

hw/misc/bcm2835_powermgt.c | 160 ++++++++++

target/arm/helper-a64.c | 12 +-

target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--

target/arm/translate-a64.c | 86 +-----

target/arm/translate-mve.c | 261 +++++++++++++++-

target/arm/translate-neon.c | 81 -----

target/arm/translate.c | 327 +++++++++++++++++++-

target/arm/vfp_helper.c | 24 +-

hw/misc/meson.build | 1 +

tests/acceptance/boot_linux_console.py | 43 +++

20 files changed, 1760 insertions(+), 209 deletions(-)

create mode 100644 include/hw/misc/bcm2835_powermgt.h

create mode 100644 hw/misc/bcm2835_powermgt.c

Implement the MVE shifts by register, which perform

shifts on a single general-purpose register.

target/arm/helper-mve.h | 2 ++

target/arm/translate.h | 1 +

target/arm/t32.decode | 18 ++++++++++++++----

target/arm/mve_helper.c | 10 ++++++++++

target/arm/translate.c | 30 ++++++++++++++++++++++++++++++

5 files changed, 57 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h

--- a/target/arm/helper-mve.h

+++ b/target/arm/helper-mve.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)

DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)

DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)

+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)

+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)

diff --git a/target/arm/translate.h b/target/arm/translate.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);

typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);

typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);

typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);

+typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);

/**

* arm_tbflags_from_tb:

diff --git a/target/arm/t32.decode b/target/arm/t32.decode

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/t32.decode

+++ b/target/arm/t32.decode

@@ -XXX,XX +XXX,XX @@

&mve_shl_ri rdalo rdahi shim

&mve_shl_rr rdalo rdahi rm

&mve_sh_ri rda shim

+&mve_sh_rr rda rm

# rdahi: bits [3:1] from insn, bit 0 is 1

# rdalo: bits [3:1] from insn, bit 0 is 0

@@ -XXX,XX +XXX,XX @@

&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9

@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \

&mve_sh_ri shim=%imm5_12_6

+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr

{

TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi

@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi

SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri

}

- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr

- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr

- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr

- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr

+ {

+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr

+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr

+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr

+ }

+

+ {

+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr

+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr

+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr

+ }

+

UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr

SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr

]

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/mve_helper.c

+++ b/target/arm/mve_helper.c

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)

{

return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);

}

+

+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)

+{

+ return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);

+}

+

+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)

+{

+ return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);

+}

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)

return do_mve_sh_ri(s, a, gen_mve_uqshl);

}

+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)

+{

+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {

+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */

+ return false;

+ }

+ if (!dc_isar_feature(aa32_mve, s) ||

+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||

+ a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||

+ a->rm == a->rda) {

+ /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */

+ unallocated_encoding(s);

+ return true;

+ }

+

+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */

+ fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);

+ return true;

+}

+

+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)

+{

+ return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);

+}

+

+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)

+{

+ return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);

+}

+

/*

* Multiply and multiply accumulate

*/

2.20.1

The A64 AdvSIMD modified-immediate grouping uses almost the same

constant encoding that A32 Neon does; reuse asimd_imm_const() (to

which we add the AArch64-specific case for cmode 15 op 1) instead of

reimplementing it all.

target/arm/translate.h | 3 +-

target/arm/translate-a64.c | 86 ++++----------------------------------

target/arm/translate.c | 17 +++++++-

3 files changed, 24 insertions(+), 82 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)

* VMVN and VBIC (when cmode < 14 && op == 1).

*

* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;

- * callers must catch this.

+ * callers must catch this; we return the 64-bit constant value defined

+ * for AArch64.

*

* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but

* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)

{

int rd = extract32(insn, 0, 5);

int cmode = extract32(insn, 12, 4);

- int cmode_3_1 = extract32(cmode, 1, 3);

- int cmode_0 = extract32(cmode, 0, 1);

int o2 = extract32(insn, 11, 1);

uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);

bool is_neg = extract32(insn, 29, 1);

@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)

- /* See AdvSIMDExpandImm() in ARM ARM */

- switch (cmode_3_1) {

- case 0: /* Replicate(Zeros(24):imm8, 2) */

- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */

- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */

- case 3: /* Replicate(imm8:Zeros(24), 2) */

- {

- int shift = cmode_3_1 * 8;

- imm = bitfield_replicate(abcdefgh << shift, 32);

- break;

- }

- case 4: /* Replicate(Zeros(8):imm8, 4) */

- case 5: /* Replicate(imm8:Zeros(8), 4) */

- {

- int shift = (cmode_3_1 & 0x1) * 8;

- imm = bitfield_replicate(abcdefgh << shift, 16);

- break;

- }

- case 6:

- if (cmode_0) {

- /* Replicate(Zeros(8):imm8:Ones(16), 2) */

- imm = (abcdefgh << 16) | 0xffff;

- } else {

- /* Replicate(Zeros(16):imm8:Ones(8), 2) */

- imm = (abcdefgh << 8) | 0xff;

- }

- imm = bitfield_replicate(imm, 32);

- break;

- case 7:

- if (!cmode_0 && !is_neg) {

- imm = bitfield_replicate(abcdefgh, 8);

- } else if (!cmode_0 && is_neg) {

- int i;

- imm = 0;

- for (i = 0; i < 8; i++) {

- if ((abcdefgh) & (1 << i)) {

- imm |= 0xffULL << (i * 8);

- }

- }

- } else if (cmode_0) {

- if (is_neg) {

- imm = (abcdefgh & 0x3f) << 48;

- if (abcdefgh & 0x80) {

- imm |= 0x8000000000000000ULL;

- }

- if (abcdefgh & 0x40) {

- imm |= 0x3fc0000000000000ULL;

- } else {

- imm |= 0x4000000000000000ULL;

- }

- } else {

- if (o2) {

- /* FMOV (vector, immediate) - half-precision */

- imm = vfp_expand_imm(MO_16, abcdefgh);

- /* now duplicate across the lanes */

- imm = bitfield_replicate(imm, 16);

- } else {

- imm = (abcdefgh & 0x3f) << 19;

- if (abcdefgh & 0x80) {

- imm |= 0x80000000;

- }

- if (abcdefgh & 0x40) {

- imm |= 0x3e000000;

- } else {

- imm |= 0x40000000;

- }

- imm |= (imm << 32);

- }

- }

- }

- break;

- default:

- g_assert_not_reached();

- }

- if (cmode_3_1 != 7 && is_neg) {

- imm = ~imm;

+ if (cmode == 15 && o2 && !is_neg) {

+ /* FMOV (vector, immediate) - half-precision */

+ imm = vfp_expand_imm(MO_16, abcdefgh);

+ /* now duplicate across the lanes */

+ imm = bitfield_replicate(imm, 16);

+ } else {

+ imm = asimd_imm_const(abcdefgh, cmode, is_neg);

}

if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)

case 14:

if (op) {

/*

- * This is the only case where the top and bottom 32 bits

- * of the encoded constant differ.

+ * This and cmode == 15 op == 1 are the only cases where

+ * the top and bottom 32 bits of the encoded constant differ.

*/

uint64_t imm64 = 0;

int n;

@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)

imm |= (imm << 8) | (imm << 16) | (imm << 24);

break;

case 15:

+ if (op) {

+ /* Reserved encoding for AArch32; valid for AArch64 */

+ uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;

+ if (imm & 0x80) {

+ imm64 |= 0x8000000000000000ULL;

+ }

+ if (imm & 0x40) {

+ imm64 |= 0x3fc0000000000000ULL;

+ } else {

+ imm64 |= 0x4000000000000000ULL;

+ }

+ return imm64;

+ }

imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)

| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));

2.20.1

Implement the MVE shifts by immediate, which perform shifts

on a single general-purpose register.

These patterns overlap with the long-shift-by-immediates,

so we have to rearrange the grouping a little here.

target/arm/helper-mve.h | 3 ++

target/arm/translate.h | 1 +

target/arm/t32.decode | 31 ++++++++++++++-----

target/arm/mve_helper.c | 10 ++++++

target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++--

5 files changed, 104 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h

--- a/target/arm/helper-mve.h

+++ b/target/arm/helper-mve.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)

DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)

DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)

DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)

+

+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)

+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)

diff --git a/target/arm/translate.h b/target/arm/translate.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);

typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);

typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);

typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);

+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);

/**

* arm_tbflags_from_tb:

diff --git a/target/arm/t32.decode b/target/arm/t32.decode

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/t32.decode

+++ b/target/arm/t32.decode

@@ -XXX,XX +XXX,XX @@

&mve_shl_ri rdalo rdahi shim

&mve_shl_rr rdalo rdahi rm

+&mve_sh_ri rda shim

# rdahi: bits [3:1] from insn, bit 0 is 1

# rdalo: bits [3:1] from insn, bit 0 is 0

@@ -XXX,XX +XXX,XX @@

&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9

@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \

&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9

+@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \

+ &mve_sh_ri shim=%imm5_12_6

{

TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi

@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi

# the rest fall through (where ORR_rrri and MOV_rxri will end up

# handling them as r13 and r15 accesses with the same semantics as A32).

[

- LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri

- LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri

- ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri

+ {

+ UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri

+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri

+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri

+ }

- UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri

- URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri

- SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri

- SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri

+ {

+ URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri

+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri

+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri

+ }

+

+ {

+ SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri

+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri

+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri

+ }

+

+ {

+ SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri

+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri

+ }

LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr

ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/mve_helper.c

+++ b/target/arm/mve_helper.c

@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)

{

return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);

}

+

+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)

+{

+ return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);

+}

+

+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)

+{

+ return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);

+}

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)

static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)

{

- TCGv_i32 t = tcg_temp_new_i32();

+ TCGv_i32 t;

+ /* Handle shift by the input size for the benefit of trans_SRSHR_ri */

+ if (sh == 32) {

+ tcg_gen_movi_i32(d, 0);

+ return;

+ }

+ t = tcg_temp_new_i32();

tcg_gen_extract_i32(t, a, sh - 1, 1);

tcg_gen_sari_i32(d, a, sh);

tcg_gen_add_i32(d, d, t);

@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)

static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)

{

- TCGv_i32 t = tcg_temp_new_i32();

+ TCGv_i32 t;

+ /* Handle shift by the input size for the benefit of trans_URSHR_ri */

+ if (sh == 32) {

+ tcg_gen_extract_i32(d, a, sh - 1, 1);

+ return;

+ }

+ t = tcg_temp_new_i32();

tcg_gen_extract_i32(t, a, sh - 1, 1);

tcg_gen_shri_i32(d, a, sh);

tcg_gen_add_i32(d, d, t);

@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)

return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);

}

+static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)

+{

+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {

+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */

+ return false;

+ }

+ if (!dc_isar_feature(aa32_mve, s) ||

+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||

+ a->rda == 13 || a->rda == 15) {

+ /* These rda cases are UNPREDICTABLE; we choose to UNDEF */

+ unallocated_encoding(s);

+ return true;

+ }

+

+ if (a->shim == 0) {

+ a->shim = 32;

+ }

+ fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);

+

+ return true;

+}

+

+static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)

+{

+ return do_mve_sh_ri(s, a, gen_urshr32_i32);

+}

+

+static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)

+{

+ return do_mve_sh_ri(s, a, gen_srshr32_i32);

+}

+

+static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)

+{

+ gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));

+}

+

+static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)

+{

+ return do_mve_sh_ri(s, a, gen_mve_sqshl);

+}

+

+static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)

+{

+ gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));

+}

+

+static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)

+{

+ return do_mve_sh_ri(s, a, gen_mve_uqshl);

+}

+

/*

* Multiply and multiply accumulate

*/

2.20.1

From: Nolan Leake <nolan@sigbus.net>

This is just enough to make reboot and poweroff work. Works for

linux, u-boot, and the arm trusted firmware. Not tested, but should

work for plan9, and bare-metal/hobby OSes, since they seem to generally

do what linux does for reset.

The watchdog timer functionality is not yet implemented.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64

Signed-off-by: Nolan Leake <nolan@sigbus.net>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20210625210209.1870217-1-nolan@sigbus.net

[PMM: tweaked commit title; fixed region size to 0x200;

moved header file to include/]

include/hw/arm/bcm2835_peripherals.h | 3 +-

include/hw/misc/bcm2835_powermgt.h | 29 +++++

hw/arm/bcm2835_peripherals.c | 13 ++-

hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++

hw/misc/meson.build | 1 +

5 files changed, 204 insertions(+), 2 deletions(-)

create mode 100644 include/hw/misc/bcm2835_powermgt.h

create mode 100644 hw/misc/bcm2835_powermgt.c

diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h

--- a/include/hw/arm/bcm2835_peripherals.h

+++ b/include/hw/arm/bcm2835_peripherals.h

@@ -XXX,XX +XXX,XX @@

#include "hw/misc/bcm2835_mphi.h"

#include "hw/misc/bcm2835_thermal.h"

#include "hw/misc/bcm2835_cprman.h"

+#include "hw/misc/bcm2835_powermgt.h"

#include "hw/sd/sdhci.h"

#include "hw/sd/bcm2835_sdhost.h"

#include "hw/gpio/bcm2835_gpio.h"

@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {

BCM2835MphiState mphi;

UnimplementedDeviceState txp;

UnimplementedDeviceState armtmr;

- UnimplementedDeviceState powermgt;

+ BCM2835PowerMgtState powermgt;

BCM2835CprmanState cprman;

PL011State uart0;

BCM2835AuxState aux;

diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/include/hw/misc/bcm2835_powermgt.h

@@ -XXX,XX +XXX,XX @@

+/*

+ * BCM2835 Power Management emulation

+ *

+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>

+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ */

+

+#ifndef BCM2835_POWERMGT_H

+#define BCM2835_POWERMGT_H

+

+#include "hw/sysbus.h"

+#include "qom/object.h"

+

+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"

+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)

+

+struct BCM2835PowerMgtState {

+ SysBusDevice busdev;

+ MemoryRegion iomem;

+

+ uint32_t rstc;

+ uint32_t rsts;

+ uint32_t wdog;

+};

+

+#endif

diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/bcm2835_peripherals.c

+++ b/hw/arm/bcm2835_peripherals.c

@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)

object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",

OBJECT(&s->gpu_bus_mr));

+

+ /* Power Management */

+ object_initialize_child(obj, "powermgt", &s->powermgt,

+ TYPE_BCM2835_POWERMGT);

static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)

@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)

qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,

INTERRUPT_USB));

+ /* Power Management */

+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {

+ return;

+ }

+

+ memory_region_add_subregion(&s->peri_mr, PM_OFFSET,

+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));

+

create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);

create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);

- create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);

create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);

create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);

create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);

diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/misc/bcm2835_powermgt.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * BCM2835 Power Management emulation

+ *

+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>

+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ */

+

+#include "qemu/osdep.h"

+#include "qemu/log.h"

+#include "qemu/module.h"

+#include "hw/misc/bcm2835_powermgt.h"

+#include "migration/vmstate.h"

+#include "sysemu/runstate.h"

+

+#define PASSWORD 0x5a000000

+#define PASSWORD_MASK 0xff000000

+

+#define R_RSTC 0x1c

+#define V_RSTC_RESET 0x20

+#define R_RSTS 0x20

+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */

+#define R_WDOG 0x24

+

+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,

+ unsigned size)

+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;

+ uint32_t res = 0;

+

+ switch (offset) {

+ case R_RSTC:

+ res = s->rstc;

+ break;

+ case R_RSTS:

+ res = s->rsts;

+ break;

+ case R_WDOG:

+ res = s->wdog;

+ break;

+

+ qemu_log_mask(LOG_UNIMP,

+ "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx

+ "\n", offset);

+ res = 0;

+ break;

+ }

+

+ return res;

+}

+

+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,

+ uint64_t value, unsigned size)

+{

+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;

+

+ if ((value & PASSWORD_MASK) != PASSWORD) {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "bcm2835_powermgt_write: Bad password 0x%"PRIx64

+ " at offset 0x%08"HWADDR_PRIx"\n",

+ value, offset);

+ return;

+ }

+

+ value = value & ~PASSWORD_MASK;

+

+ switch (offset) {

+ case R_RSTC:

+ s->rstc = value;

+ if (value & V_RSTC_RESET) {

+ if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {

+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);

+ } else {

+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);

+ }

+ }

+ break;

+ case R_RSTS:

+ qemu_log_mask(LOG_UNIMP,

+ "bcm2835_powermgt_write: RSTS\n");

+ s->rsts = value;

+ break;

+ case R_WDOG:

+ qemu_log_mask(LOG_UNIMP,

+ "bcm2835_powermgt_write: WDOG\n");

+ s->wdog = value;

+ break;

+

+ default:

+ qemu_log_mask(LOG_UNIMP,

+ "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx

+ "\n", offset);

+ break;

+static const MemoryRegionOps bcm2835_powermgt_ops = {

+ .read = bcm2835_powermgt_read,

+ .write = bcm2835_powermgt_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+ .impl.min_access_size = 4,

+ .impl.max_access_size = 4,

+};

+

+static const VMStateDescription vmstate_bcm2835_powermgt = {

+ .name = TYPE_BCM2835_POWERMGT,

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .fields = (VMStateField[]) {

+ VMSTATE_UINT32(rstc, BCM2835PowerMgtState),

+ VMSTATE_UINT32(rsts, BCM2835PowerMgtState),

+ VMSTATE_UINT32(wdog, BCM2835PowerMgtState),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

+static void bcm2835_powermgt_init(Object *obj)

+{

+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);

+

+ memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,

+ TYPE_BCM2835_POWERMGT, 0x200);

+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);

+}

+

+static void bcm2835_powermgt_reset(DeviceState *dev)

+{

+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);

+

+ /* https://elinux.org/BCM2835_registers#PM */

+ s->rstc = 0x00000102;

+ s->rsts = 0x00001000;

+ s->wdog = 0x00000000;

+}

+

+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+

+ dc->reset = bcm2835_powermgt_reset;

+ dc->vmsd = &vmstate_bcm2835_powermgt;

+}

+

+static TypeInfo bcm2835_powermgt_info = {

+ .name = TYPE_BCM2835_POWERMGT,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(BCM2835PowerMgtState),

+ .class_init = bcm2835_powermgt_class_init,

+ .instance_init = bcm2835_powermgt_init,

+};

+

+static void bcm2835_powermgt_register_types(void)

+{

+ type_register_static(&bcm2835_powermgt_info);

+}

+

+type_init(bcm2835_powermgt_register_types)

diff --git a/hw/misc/meson.build b/hw/misc/meson.build

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/meson.build

+++ b/hw/misc/meson.build

@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(

'bcm2835_rng.c',

'bcm2835_thermal.c',

'bcm2835_cprman.c',

+ 'bcm2835_powermgt.c',

))

softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))

softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))

2.20.1

Implement the MVE VSHLC insn, which performs a shift left of the

entire vector with carry in bits provided from a general purpose

register and carry out bits written back to that register.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210628135835.6690-14-peter.maydell@linaro.org

target/arm/helper-mve.h | 2 ++

target/arm/mve.decode | 2 ++

target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++

target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++

4 files changed, 72 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h

--- a/target/arm/helper-mve.h

+++ b/target/arm/helper-mve.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

+

+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)

diff --git a/target/arm/mve.decode b/target/arm/mve.decode

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/mve.decode

+++ b/target/arm/mve.decode

@@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b

VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h

VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b

VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h

+

+VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/mve_helper.c

+++ b/target/arm/mve_helper.c

@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)

DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)

DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)

DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)

+

+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,

+ uint32_t shift)

+{

+ uint32_t *d = vd;

+ uint16_t mask = mve_element_mask(env);

+ unsigned e;

+ uint32_t r;

+

+ /*

+ * For each 32-bit element, we shift it left, bringing in the

+ * low 'shift' bits of rdm at the bottom. Bits shifted out at

+ * the top become the new rdm, if the predicate mask permits.

+ * The final rdm value is returned to update the register.

+ * shift == 0 here means "shift by 32 bits".

+ */

+ if (shift == 0) {

+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {

+ r = rdm;

+ if (mask & 1) {

+ rdm = d[H4(e)];

+ }

+ mergemask(&d[H4(e)], r, mask);

+ }

+ } else {

+ uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);

+

+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {

+ r = (d[H4(e)] << shift) | (rdm & shiftmask);

+ if (mask & 1) {

+ rdm = d[H4(e)] >> (32 - shift);

+ }

+ mergemask(&d[H4(e)], r, mask);

+ }

+ }

+ mve_advance_vpt(env);

+ return rdm;

+}

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-mve.c

+++ b/target/arm/translate-mve.c

@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)

DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)

DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)

DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)

+

+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)

+{

+ /*

+ * Whole Vector Left Shift with Carry. The carry is taken

+ * from a general purpose register and written back there.

+ * An imm of 0 means "shift by 32".

+ */

+ TCGv_ptr qd;

+ TCGv_i32 rdm;

+

+ if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {

+ return false;

+ }

+ if (a->rdm == 13 || a->rdm == 15) {

+ /* CONSTRAINED UNPREDICTABLE: we UNDEF */

+ return false;

+ }

+ if (!mve_eci_check(s) || !vfp_access_check(s)) {

+ return true;

+ }

+

+ qd = mve_qreg_ptr(a->qd);

+ rdm = load_reg(s, a->rdm);

+ gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));

+ store_reg(s, a->rdm, rdm);

+ tcg_temp_free_ptr(qd);

+ mve_update_eci(s);

+ return true;

+}

2.20.1

Implement the MVE VSRI and VSLI insns, which perform a

shift-and-insert operation.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210628135835.6690-11-peter.maydell@linaro.org

target/arm/helper-mve.h | 8 ++++++++

target/arm/mve.decode | 9 ++++++++

target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++

target/arm/translate-mve.c | 3 +++

4 files changed, 62 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h

--- a/target/arm/helper-mve.h

+++ b/target/arm/helper-mve.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

+

+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

+

+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

diff --git a/target/arm/mve.decode b/target/arm/mve.decode

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/mve.decode

+++ b/target/arm/mve.decode

@@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h

VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b

VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h

+

+# Shift-and-insert

+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b

+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h

+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w

+

+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b

+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h

+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/mve_helper.c

+++ b/target/arm/mve_helper.c

@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)

DO_2SHIFT_U(vrshli_u, DO_VRSHLU)

DO_2SHIFT_S(vrshli_s, DO_VRSHLS)

+/* Shift-and-insert; we always work with 64 bits at a time */

+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \

+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \

+ void *vm, uint32_t shift) \

+ { \

+ uint64_t *d = vd, *m = vm; \

+ uint16_t mask; \

+ uint64_t shiftmask; \

+ unsigned e; \

+ if (shift == 0 || shift == ESIZE * 8) { \

+ /* \

+ * Only VSLI can shift by 0; only VSRI can shift by <dt>. \

+ * The generic logic would give the right answer for 0 but \

+ * fails for <dt>. \

+ */ \

+ goto done; \

+ } \

+ assert(shift < ESIZE * 8); \

+ mask = mve_element_mask(env); \

+ /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \

+ shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \

+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \

+ uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \

+ (d[H8(e)] & ~shiftmask); \

+ mergemask(&d[H8(e)], r, mask); \

+ } \

+done: \

+ mve_advance_vpt(env); \

+ }

+

+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))

+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))

+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))

+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))

+

+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)

+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)

+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)

+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)

+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)

+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)

+

/*

* Long shifts taking half-sized inputs from top or bottom of the input

* vector and producing a double-width result. ESIZE, TYPE are for

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-mve.c

+++ b/target/arm/translate-mve.c

@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)

DO_2SHIFT(VRSHRI_S, vrshli_s, true)

DO_2SHIFT(VRSHRI_U, vrshli_u, true)

+DO_2SHIFT(VSRI, vsri, false)

+DO_2SHIFT(VSLI, vsli, false)

+

#define DO_VSHLL(INSN, FN) \

static bool trans_##INSN(DisasContext *s, arg_2shift *a) \

{ \

2.20.1

Implement the MVE vector shift right by immediate insns VSHRI and

VRSHRI. As with Neon, we implement these by using helper functions

which perform left shifts but allow negative shift counts to indicate

right shifts.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210628135835.6690-9-peter.maydell@linaro.org

target/arm/helper-mve.h | 12 ++++++++++++

target/arm/translate.h | 20 ++++++++++++++++++++

target/arm/mve.decode | 28 ++++++++++++++++++++++++++++

target/arm/mve_helper.c | 7 +++++++

target/arm/translate-mve.c | 5 +++++

target/arm/translate-neon.c | 18 ------------------

6 files changed, 72 insertions(+), 18 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h

--- a/target/arm/helper-mve.h

+++ b/target/arm/helper-mve.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)

DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)

DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)

+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

+

DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

+