Series comparison

-[PULL 00/24] target-arm queue
+[PULL 00/21] target-arm queue
-The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
+Here's another arm pullreq; nothing too exciting in here I think.
-  Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
+thanks
 -- PMM
 The following changes since commit 5fee33d97a7f2e95716417bd164f2f5264acd976:
   Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu into staging (2024-04-29 14:34:25 -0700)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240430
-for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
+for you to fetch changes up to a0c325c4b05cf7815739d6a84e567b95c8c5be7e:
-  target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
+  tests/qtest : Add testcase for DM163 (2024-04-30 16:05:08 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * more MVE instructions
+ * hw/core/clock: allow clock_propagate on child clocks
- * hw/gpio/gpio_pwr: use shutdown function for reboot
+ * hvf: arm: Remove unused PL1_WRITE_MASK define
- * target/arm: Check NaN mode before silencing NaN
+ * target/arm: Restrict translation disabled alignment check to VMSA
- * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
+ * docs/system/arm/emulation.rst: Add missing implemented features
- * hw/arm: Add basic power management to raspi.
+ * target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max'
- * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
+ * tests/avocado: update sunxi kernel from armbian to 6.6.16
  * target/arm: Make new CPUs default to 1GHz generic timer
  * hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
  * hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
  * hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
  * hw/arm: Add DM163 display to B-L475E-IOT01A board
 ----------------------------------------------------------------
-Joe Komlodi (1):
+Alexandra Diupina (1):
-      target/arm: Check NaN mode before silencing NaN
+      hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
-Maxim Uvarov (1):
+Inès Varhol (5):
-      hw/gpio/gpio_pwr: use shutdown function for reboot
+      hw/display : Add device DM163
       hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC
       hw/arm : Create Bl475eMachineState
       hw/arm : Connect DM163 to B-L475E-IOT01A
       tests/qtest : Add testcase for DM163
-Nolan Leake (1):
+Peter Maydell (10):
-      hw/arm: Add basic power management to raspi.
+      docs/system/arm/emulation.rst: Add missing implemented features
+      target/arm: Enable FEAT_CSV2_3 for -cpu max
-Patrick Venture (2):
+      target/arm: Enable FEAT_ETS2 for -cpu max
-      docs/system/arm: Add quanta-q7l1-bmc reference
+      target/arm: Implement ID_AA64MMFR3_EL1
-      docs/system/arm: Add quanta-gbs-bmc reference
+      target/arm: Enable FEAT_Spec_FPACC for -cpu max
+      tests/avocado: update sunxi kernel from armbian to 6.6.16
-Peter Maydell (18):
+      target/arm: Refactor default generic timer frequency handling
-      target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
+      hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz
-      target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
+      hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property
-      target/arm: Make asimd_imm_const() public
+      target/arm: Default to 1GHz cntfrq for 'max' and new CPUs
       target/arm: Use asimd_imm_const for A64 decode
       target/arm: Use dup_const() instead of bitfield_replicate()
       target/arm: Implement MVE logical immediate insns
       target/arm: Implement MVE vector shift left by immediate insns
       target/arm: Implement MVE vector shift right by immediate insns
       target/arm: Implement MVE VSHLL
       target/arm: Implement MVE VSRI, VSLI
       target/arm: Implement MVE VSHRN, VRSHRN
       target/arm: Implement MVE saturating narrowing shifts
       target/arm: Implement MVE VSHLC
       target/arm: Implement MVE VADDLV
       target/arm: Implement MVE long shifts by immediate
       target/arm: Implement MVE long shifts by register
       target/arm: Implement MVE shifts by immediate
       target/arm: Implement MVE shifts by register
 Philippe Mathieu-Daudé (1):
-      tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
+      hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
- docs/system/arm/aspeed.rst             |   1 +
+Raphael Poggi (1):
- docs/system/arm/nuvoton.rst            |   5 +-
+      hw/core/clock: allow clock_propagate on child clocks
  include/hw/arm/bcm2835_peripherals.h   |   3 +-
  include/hw/misc/bcm2835_powermgt.h     |  29 ++
  target/arm/helper-mve.h                | 108 +++++++
  target/arm/translate.h                 |  41 +++
  target/arm/mve.decode                  | 177 ++++++++++-
  target/arm/t32.decode                  |  71 ++++-
  hw/arm/bcm2835_peripherals.c           |  13 +-
  hw/gpio/gpio_pwr.c                     |   2 +-
  hw/misc/bcm2835_powermgt.c             | 160 ++++++++++
  target/arm/helper-a64.c                |  12 +-
  target/arm/mve_helper.c                | 524 +++++++++++++++++++++++++++++++--
  target/arm/translate-a64.c             |  86 +-----
  target/arm/translate-mve.c             | 261 +++++++++++++++-
  target/arm/translate-neon.c            |  81 -----
  target/arm/translate.c                 | 327 +++++++++++++++++++-
  target/arm/vfp_helper.c                |  24 +-
  hw/misc/meson.build                    |   1 +
  tests/acceptance/boot_linux_console.py |  43 +++
 files changed, 1760 insertions(+), 209 deletions(-)
  create mode 100644 include/hw/misc/bcm2835_powermgt.h
  create mode 100644 hw/misc/bcm2835_powermgt.c
+Richard Henderson (1):
+      target/arm: Restrict translation disabled alignment check to VMSA
+Thomas Huth (1):
+      hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
+Zenghui Yu (1):
+      hvf: arm: Remove PL1_WRITE_MASK
+ docs/system/arm/b-l475e-iot01a.rst  |   3 +-
+ docs/system/arm/emulation.rst       |  42 ++++-
+ include/hw/display/dm163.h          |  59 ++++++
+ include/hw/watchdog/sbsa_gwdt.h     |   3 +-
+ target/arm/cpu.h                    |  28 +++
+ target/arm/internals.h              |  15 +-
+ hw/arm/b-l475e-iot01a.c             | 105 +++++++++--
+ hw/arm/npcm7xx.c                    |   3 +-
+ hw/arm/sbsa-ref.c                   |  16 ++
+ hw/arm/stm32l4x5_soc.c              |   6 +-
+ hw/char/stm32l4x5_usart.c           |   1 +
+ hw/core/clock.c                     |   1 -
+ hw/core/machine.c                   |   4 +-
+ hw/display/dm163.c                  | 349 ++++++++++++++++++++++++++++++++++++
+ hw/dma/xlnx_dpdma.c                 |  20 +--
+ hw/watchdog/sbsa_gwdt.c             |  15 +-
+ target/arm/cpu.c                    |  42 +++--
+ target/arm/cpu64.c                  |   2 +
+ target/arm/helper.c                 |  22 +--
+ target/arm/hvf/hvf.c                |   3 +-
+ target/arm/kvm.c                    |   2 +
+ target/arm/tcg/cpu32.c              |   6 +-
+ target/arm/tcg/cpu64.c              |  28 ++-
+ target/arm/tcg/hflags.c             |  12 +-
+ tests/qtest/dm163-test.c            | 194 ++++++++++++++++++++
+ tests/qtest/stm32l4x5_gpio-test.c   |  13 +-
+ tests/qtest/stm32l4x5_syscfg-test.c |  17 +-
+ hw/arm/Kconfig                      |   1 +
+ hw/display/Kconfig                  |   3 +
+ hw/display/meson.build              |   1 +
+ hw/display/trace-events             |  14 ++
+ tests/avocado/boot_linux_console.py |  70 ++++----
+ tests/avocado/replay_kernel.py      |   8 +-
+ tests/qtest/meson.build             |   2 +
+files changed, 987 insertions(+), 123 deletions(-)
+ create mode 100644 include/hw/display/dm163.h
+ create mode 100644 hw/display/dm163.c
+ create mode 100644 tests/qtest/dm163-test.c

-[PULL 24/24] target/arm: Implement MVE shifts by register
+[PULL 01/21] hw/core/clock: allow clock_propagate on child clocks
-Implement the MVE shifts by register, which perform
+From: Raphael Poggi <raphael.poggi@lynxleap.co.uk>
 shifts on a single general-purpose register.
+clock_propagate() has an assert that clk->source is NULL, i.e. that
+you are calling it on a clock which has no source clock.  This made
+sense in the original design where the only way for a clock's
+frequency to change if it had a source clock was when that source
+clock changed.  However, we subsequently added multiplier/divider
+support, but didn't look at what that meant for propagation.
+If a clock-management device changes the multiplier or divider value
+on a clock, it needs to propagate that change down to child clocks,
+even if the clock has a source clock set.  So the assertion is now
+incorrect.
+Remove the assertion.
+Signed-off-by: Raphael Poggi <raphael.poggi@lynxleap.co.uk>
+Message-id: 20240419162951.23558-1-raphael.poggi@lynxleap.co.uk
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+[PMM: Rewrote the commit message]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h |  2 ++
+ hw/core/clock.c | 1 -
- target/arm/translate.h  |  1 +
+file changed, 1 deletion(-)
  target/arm/t32.decode   | 18 ++++++++++++++----
  target/arm/mve_helper.c | 10 ++++++++++
  target/arm/translate.c  | 30 ++++++++++++++++++++++++++++++
 files changed, 57 insertions(+), 4 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/hw/core/clock.c b/hw/core/clock.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/hw/core/clock.c
-+++ b/target/arm/helper-mve.h
++++ b/hw/core/clock.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
+@@ -XXX,XX +XXX,XX @@ static void clock_propagate_period(Clock *clk, bool call_callbacks)
- DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
+ void clock_propagate(Clock *clk)
  DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
 +DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
 +DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
  typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
  typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
  typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
 +typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
  /**
   * arm_tbflags_from_tb:
 diff --git a/target/arm/t32.decode b/target/arm/t32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/t32.decode
 +++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@
  &mve_shl_ri      rdalo rdahi shim
  &mve_shl_rr      rdalo rdahi rm
  &mve_sh_ri       rda shim
 +&mve_sh_rr       rda rm
  # rdahi: bits [3:1] from insn, bit 0 is 1
  # rdalo: bits [3:1] from insn, bit 0 is 0
@@ -XXX,XX +XXX,XX @@
                   &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
  @mve_sh_ri       ....... .... . rda:4 . ... ... . .. .. .... \
                   &mve_sh_ri shim=%imm5_12_6
 +@mve_sh_rr       ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
  {
-   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
+-    assert(clk->source == NULL);
-@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
+     trace_clock_propagate(CLOCK_PATH(clk));
-       SQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
+     clock_propagate_period(clk, true);
      }
 -    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
 -    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
 -    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
 -    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
 +    {
 +      UQRSHL_rr    1110101 0010 1 ....  ....  1111 0000 1101  @mve_sh_rr
 +      LSLL_rr      1110101 0010 1 ... 0 .... ... 1 0000 1101  @mve_shl_rr
 +      UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101  @mve_shl_rr
 +    }
 +
 +    {
 +      SQRSHR_rr    1110101 0010 1 ....  ....  1111 0010 1101  @mve_sh_rr
 +      ASRL_rr      1110101 0010 1 ... 0 .... ... 1 0010 1101  @mve_shl_rr
 +      SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101  @mve_shl_rr
 +    }
 +
      UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
      SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
    ]
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
  {
      return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
  }
-+
-+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
-+{
-+    return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
-+}
-+
-+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
-+{
-+    return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
-     return do_mve_sh_ri(s, a, gen_mve_uqshl);
- }
-+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
-+{
-+    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
-+        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
-+        return false;
-+    }
-+    if (!dc_isar_feature(aa32_mve, s) ||
-+        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
-+        a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
-+        a->rm == a->rda) {
-+        /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
-+        unallocated_encoding(s);
-+        return true;
-+    }
-+
-+    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
-+    fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
-+    return true;
-+}
-+
-+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
-+{
-+    return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
-+}
-+
-+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
-+{
-+    return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
-+}
-+
- /*
-  * Multiply and multiply accumulate
-  */
 --
-.20.1
+.34.1

-[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
+[PULL 02/21] hvf: arm: Remove PL1_WRITE_MASK
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Zenghui Yu <zenghui.yu@linux.dev>
-Add a test booting and quickly shutdown a raspi2 machine,
+As it had never been used since the first commit a1477da3ddeb ("hvf: Add
-to test the power management model:
+Apple Silicon support").
-   (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
+Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev>
-  console: [    0.000000] Booting Linux on physical CPU 0xf00
+Message-id: 20240422092715.71973-1-zenghui.yu@linux.dev
-  console: [    0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
   console: [    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
   console: [    0.000000] CPU: div instructions available: patching division code
   console: [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
   console: [    0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
   ...
   console: Boot successful.
   console: cat /proc/cpuinfo
   console: / # cat /proc/cpuinfo
   ...
   console: processor      : 3
   console: model name     : ARMv7 Processor rev 5 (v7l)
   console: BogoMIPS       : 125.00
   console: Features       : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
   console: CPU implementer        : 0x41
   console: CPU architecture: 7
   console: CPU variant    : 0x0
   console: CPU part       : 0xc07
   console: CPU revision   : 5
   console: Hardware       : BCM2835
   console: Revision       : 0000
   console: Serial         : 0000000000000000
   console: cat /proc/iomem
   console: / # cat /proc/iomem
   console: 00000000-3bffffff : System RAM
   console: 00008000-00afffff : Kernel code
   console: 00c00000-00d468ef : Kernel data
   console: 3f006000-3f006fff : dwc_otg
   console: 3f007000-3f007eff : /soc/dma@7e007000
   console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
   console: 3f100000-3f100027 : /soc/watchdog@7e100000
   console: 3f101000-3f102fff : /soc/cprman@7e101000
   console: 3f200000-3f2000b3 : /soc/gpio@7e200000
   PASS (24.59 s)
   RESULTS    : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
   JOB TIME   : 25.02 s
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
 Message-id: 20210531113837.1689775-1-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
+ target/arm/hvf/hvf.c | 1 -
-file changed, 43 insertions(+)
+file changed, 1 deletion(-)
-diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
+diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
 index XXXXXXX..XXXXXXX 100644
---- a/tests/acceptance/boot_linux_console.py
+--- a/target/arm/hvf/hvf.c
-+++ b/tests/acceptance/boot_linux_console.py
++++ b/target/arm/hvf/hvf.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void hvf_arm_init_debug(void)
- from avocado import skip
- from avocado import skipUnless
+ #define HVF_SYSREG(crn, crm, op0, op1, op2) \
- from avocado_qemu import Test
+         ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
-+from avocado_qemu import exec_command
+-#define PL1_WRITE_MASK 0x4
- from avocado_qemu import exec_command_and_wait_for_pattern
- from avocado_qemu import interrupt_interactive_console_until_pattern
+ #define SYSREG_OP0_SHIFT      20
- from avocado_qemu import wait_for_console_pattern
+ #define SYSREG_OP0_MASK       0x3
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
          """
          self.do_test_arm_raspi2(0)
 +    def test_arm_raspi2_initrd(self):
 +        """
 +        :avocado: tags=arch:arm
 +        :avocado: tags=machine:raspi2
 +        """
 +        deb_url = ('http://archive.raspberrypi.org/debian/'
 +                   'pool/main/r/raspberrypi-firmware/'
 +                   'raspberrypi-kernel_1.20190215-1_armhf.deb')
 +        deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
 +        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
 +        kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
 +        dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
 +
 +        initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
 +                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
 +                      'arm/rootfs-armv7a.cpio.gz')
 +        initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
 +        initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
 +        initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
 +        archive.gzip_uncompress(initrd_path_gz, initrd_path)
 +
 +        self.vm.set_console()
 +        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
 +                               'earlycon=pl011,0x3f201000 console=ttyAMA0 '
 +                               'panic=-1 noreboot ' +
 +                               'dwc_otg.fiq_fsm_enable=0')
 +        self.vm.add_args('-kernel', kernel_path,
 +                         '-dtb', dtb_path,
 +                         '-initrd', initrd_path,
 +                         '-append', kernel_command_line,
 +                         '-no-reboot')
 +        self.vm.launch()
 +        self.wait_for_console_pattern('Boot successful.')
 +
 +        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
 +                                                'BCM2835')
 +        exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
 +                                                '/soc/cprman@7e101000')
 +        exec_command(self, 'halt')
 +        # Wait for VM to shut down gracefully
 +        self.vm.wait()
 +
      def test_arm_exynos4210_initrd(self):
          """
          :avocado: tags=arch:arm
 --
-.20.1
+.34.1

-[PULL 20/24] target/arm: Implement MVE VADDLV
+[PULL 03/21] target/arm: Restrict translation disabled alignment check to VMSA
-Implement the MVE VADDLV insn; this is similar to VADDV, except
+From: Richard Henderson <richard.henderson@linaro.org>
 that it accumulates 32-bit elements into a 64-bit accumulator
 stored in a pair of general-purpose registers.
+For cpus using PMSA, when the MPU is disabled, the default memory
+type is Normal, Non-cachable. This means that it should not
+have alignment restrictions enforced.
+Cc: qemu-stable@nongnu.org
+Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled")
+Reported-by: Clément Chigot <chigot@adacore.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Tested-by: Clément Chigot <chigot@adacore.com>
+Message-id: 20240422170722.117409-1-richard.henderson@linaro.org
+[PMM: trivial comment, commit message tweaks]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    |  3 ++
+ target/arm/tcg/hflags.c | 12 ++++++++++--
- target/arm/mve.decode      |  6 +++-
+file changed, 10 insertions(+), 2 deletions(-)
  target/arm/mve_helper.c    | 19 ++++++++++++
  target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
 files changed, 90 insertions(+), 1 deletion(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/tcg/hflags.c
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/tcg/hflags.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr)
- DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
+     }
- DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
+     /*
-+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
+-     * If translation is disabled, then the default memory type is
-+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
+-     * Device(-nGnRnE) instead of Normal, which requires that alignment
-+
++     * With PMSA, when the MPU is disabled, all memory types in the
- DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
++     * default map are Normal, so don't need aligment enforcing.
  DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
  DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar   1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
  VQRDMULH_scalar  1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
  # Vector add across vector
 -VADDV            111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
 +{
 +  VADDV          111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
 +  VADDLV         111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
 +                 rdahi=%rdahi rdalo=%rdalo
 +}
  # Predicate operations
  %mask_22_13      22:1 13:3
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
  DO_VADDV(vaddvuh, 2, uint16_t)
  DO_VADDV(vaddvuw, 4, uint32_t)
 +#define DO_VADDLV(OP, TYPE, LTYPE)                              \
 +    uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
 +                                    uint64_t ra)                \
 +    {                                                           \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned e;                                             \
 +        TYPE *m = vm;                                           \
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {              \
 +            if (mask & 1) {                                     \
 +                ra += (LTYPE)m[H4(e)];                          \
 +            }                                                   \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +        return ra;                                              \
 +    }                                                           \
 +
 +DO_VADDLV(vaddlv_s, int32_t, int64_t)
 +DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
 +
  /* Shifts by immediate */
  #define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
      void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
      return true;
  }
 +static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
 +{
 +    /*
 +     * Vector Add Long Across Vector: accumulate the 32-bit
 +     * elements of the vector into a 64-bit result stored in
 +     * a pair of general-purpose registers.
 +     * No need to check Qm's bank: it is only 3 bits in decode.
 +     */
-+    TCGv_ptr qm;
++    if (arm_feature(env, ARM_FEATURE_PMSA)) {
 +    TCGv_i64 rda;
 +    TCGv_i32 rdalo, rdahi;
 +
 +    if (!dc_isar_feature(aa32_mve, s)) {
 +        return false;
-+    }
-+    /*
-+     * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
-+     * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
-+     */
-+    if (a->rdahi == 13 || a->rdahi == 15) {
-+        return false;
-+    }
-+    if (!mve_eci_check(s) || !vfp_access_check(s)) {
-+        return true;
 +    }
 +
 +    /*
-+     * This insn is subject to beat-wise execution. Partial execution
++     * With VMSA, if translation is disabled, then the default memory type
-+     * of an A=0 (no-accumulate) insn which does not execute the first
++     * is Device(-nGnRnE) instead of Normal, which requires that alignment
-+     * beat must start with the current value of RdaHi:RdaLo, not zero.
+      * be enforced.  Since this affects all ram, it is most efficient
-+     */
+      * to handle this during translation.
-+    if (a->a || mve_skip_first_beat(s)) {
+      */
 +        /* Accumulate input from RdaHi:RdaLo */
 +        rda = tcg_temp_new_i64();
 +        rdalo = load_reg(s, a->rdalo);
 +        rdahi = load_reg(s, a->rdahi);
 +        tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
 +        tcg_temp_free_i32(rdalo);
 +        tcg_temp_free_i32(rdahi);
 +    } else {
 +        /* Accumulate starting at zero */
 +        rda = tcg_const_i64(0);
 +    }
 +
 +    qm = mve_qreg_ptr(a->qm);
 +    if (a->u) {
 +        gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
 +    } else {
 +        gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
 +    }
 +    tcg_temp_free_ptr(qm);
 +
 +    rdalo = tcg_temp_new_i32();
 +    rdahi = tcg_temp_new_i32();
 +    tcg_gen_extrl_i64_i32(rdalo, rda);
 +    tcg_gen_extrh_i64_i32(rdahi, rda);
 +    store_reg(s, a->rdalo, rdalo);
 +    store_reg(s, a->rdahi, rdahi);
 +    tcg_temp_free_i64(rda);
 +    mve_update_eci(s);
 +    return true;
 +}
 +
  static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
  {
      TCGv_ptr qd;
 --
-.20.1
+.34.1

-[PULL 23/24] target/arm: Implement MVE shifts by immediate
+[PULL 04/21] docs/system/arm/emulation.rst: Add missing implemented features
-Implement the MVE shifts by immediate, which perform shifts
+As of version DDI0487K.a of the Arm ARM, some architectural features
-on a single general-purpose register.
+which previously didn't have official names have been named.  Add
+these to the list of features which QEMU's TCG emulation supports.
-These patterns overlap with the long-shift-by-immediates,
+Mostly these are features which we thought of as part of baseline 8.0
-so we have to rearrange the grouping a little here.
+support.  For SVE and SVE2, the names have been brought into line
 with the FEAT_* naming convention of other extensions, and some
 sub-components split into separate FEAT_ items.  In a few cases (eg
 FEAT_CCIDX, FEAT_DPB2) the omission from our list was just an oversight.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
+Message-id: 20240418152004.2106516-2-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h |  3 ++
+ docs/system/arm/emulation.rst | 38 +++++++++++++++++++++++++++++++++--
- target/arm/translate.h  |  1 +
+file changed, 36 insertions(+), 2 deletions(-)
  target/arm/t32.decode   | 31 ++++++++++++++-----
  target/arm/mve_helper.c | 10 ++++++
  target/arm/translate.c  | 68 +++++++++++++++++++++++++++++++++++++++--
 files changed, 104 insertions(+), 9 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/docs/system/arm/emulation.rst
-+++ b/target/arm/helper-mve.h
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+@@ -XXX,XX +XXX,XX @@ Armv8 versions of the A-profile architecture. It also has support for
- DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+ the following architecture extensions:
- DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
- DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
+ - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
-+
++- FEAT_AA32EL0 (Support for AArch32 at EL0)
-+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
++- FEAT_AA32EL1 (Support for AArch32 at EL1)
-+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
++- FEAT_AA32EL2 (Support for AArch32 at EL2)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
++- FEAT_AA32EL3 (Support for AArch32 at EL3)
-index XXXXXXX..XXXXXXX 100644
+ - FEAT_AA32HPD (AArch32 hierarchical permission disables)
---- a/target/arm/translate.h
+ - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
-+++ b/target/arm/translate.h
++- FEAT_AA64EL0 (Support for AArch64 at EL0)
-@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
++- FEAT_AA64EL1 (Support for AArch64 at EL1)
- typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
++- FEAT_AA64EL2 (Support for AArch64 at EL2)
- typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
++- FEAT_AA64EL3 (Support for AArch64 at EL3)
- typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
++- FEAT_AdvSIMD (Advanced SIMD Extension)
-+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
+ - FEAT_AES (AESD and AESE instructions)
++- FEAT_Armv9_Crypto (Armv9 Cryptographic Extension)
- /**
++- FEAT_ASID16 (16 bit ASID)
-  * arm_tbflags_from_tb:
+ - FEAT_BBM at level 2 (Translation table break-before-make levels)
-diff --git a/target/arm/t32.decode b/target/arm/t32.decode
+ - FEAT_BF16 (AArch64 BFloat16 instructions)
-index XXXXXXX..XXXXXXX 100644
+ - FEAT_BTI (Branch Target Identification)
---- a/target/arm/t32.decode
++- FEAT_CCIDX (Extended cache index)
-+++ b/target/arm/t32.decode
+ - FEAT_CRC32 (CRC32 instructions)
-@@ -XXX,XX +XXX,XX @@
++- FEAT_Crypto (Cryptographic Extension)
+ - FEAT_CSV2 (Cache speculation variant 2)
- &mve_shl_ri      rdalo rdahi shim
+ - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
- &mve_shl_rr      rdalo rdahi rm
+ - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
-+&mve_sh_ri       rda shim
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+ - FEAT_DGH (Data gathering hint)
- # rdahi: bits [3:1] from insn, bit 0 is 1
+ - FEAT_DIT (Data Independent Timing instructions)
- # rdalo: bits [3:1] from insn, bit 0 is 0
+ - FEAT_DPB (DC CVAP instruction)
-@@ -XXX,XX +XXX,XX @@
++- FEAT_DPB2 (DC CVADP instruction)
-                  &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
++- FEAT_Debugv8p1 (Debug with VHE)
- @mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
+ - FEAT_Debugv8p2 (Debug changes for v8.2)
-                  &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
+ - FEAT_Debugv8p4 (Debug changes for v8.4)
-+@mve_sh_ri       ....... .... . rda:4 . ... ... . .. .. .... \
+ - FEAT_DotProd (Advanced SIMD dot product instructions)
-+                 &mve_sh_ri shim=%imm5_12_6
+ - FEAT_DoubleFault (Double Fault Extension)
+ - FEAT_E0PD (Preventing EL0 access to halves of address maps)
- {
+ - FEAT_ECV (Enhanced Counter Virtualization)
-   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
++- FEAT_EL0 (Support for execution at EL0)
-@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
++- FEAT_EL1 (Support for execution at EL1)
-   # the rest fall through (where ORR_rrri and MOV_rxri will end up
++- FEAT_EL2 (Support for execution at EL2)
-   # handling them as r13 and r15 accesses with the same semantics as A32).
++- FEAT_EL3 (Support for execution at EL3)
-   [
+ - FEAT_EPAC (Enhanced pointer authentication)
--    LSLL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
+ - FEAT_ETS (Enhanced Translation Synchronization)
--    LSRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
+ - FEAT_EVT (Enhanced Virtualization Traps)
--    ASRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
++- FEAT_F32MM (Single-precision Matrix Multiplication)
-+    {
++- FEAT_F64MM (Double-precision Matrix Multiplication)
-+      UQSHL_ri   1110101 0010 1 ....  0 ...  1111 .. 00 1111  @mve_sh_ri
+ - FEAT_FCMA (Floating-point complex number instructions)
-+      LSLL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
+ - FEAT_FGT (Fine-Grained Traps)
-+      UQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
+ - FEAT_FHM (Floating-point half-precision multiplication instructions)
-+    }
++- FEAT_FP (Floating Point extensions)
+ - FEAT_FP16 (Half-precision floating-point data processing)
--    UQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
+ - FEAT_FPAC (Faulting on AUT* instructions)
--    URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
+ - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
--    SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
--    SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
+ - FEAT_LSE (Large System Extensions)
-+    {
+ - FEAT_LSE2 (Large System Extensions v2)
-+      URSHR_ri   1110101 0010 1 ....  0 ...  1111 .. 01 1111  @mve_sh_ri
+ - FEAT_LVA (Large Virtual Address space)
-+      LSRL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
++- FEAT_MixedEnd (Mixed-endian support)
-+      URSHRL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
++- FEAT_MixdEndEL0 (Mixed-endian support at EL0)
-+    }
+ - FEAT_MOPS (Standardization of memory operations)
-+
+ - FEAT_MTE (Memory Tagging Extension)
-+    {
+ - FEAT_MTE2 (Memory Tagging Extension)
-+      SRSHR_ri   1110101 0010 1 ....  0 ...  1111 .. 10 1111  @mve_sh_ri
+ - FEAT_MTE3 (MTE Asymmetric Fault Handling)
-+      ASRL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
++- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
-+      SRSHRL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
+ - FEAT_NMI (Non-maskable Interrupt)
-+    }
+ - FEAT_NV (Nested Virtualization)
-+
+ - FEAT_NV2 (Enhanced nested virtualization support)
-+    {
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
-+      SQSHL_ri   1110101 0010 1 ....  0 ...  1111 .. 11 1111  @mve_sh_ri
+ - FEAT_PAuth (Pointer authentication)
-+      SQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
+ - FEAT_PAuth2 (Enhancements to pointer authentication)
-+    }
+ - FEAT_PMULL (PMULL, PMULL2 instructions)
++- FEAT_PMUv3 (PMU extension version 3)
-     LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
+ - FEAT_PMUv3p1 (PMU Extensions v3.1)
-     ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
+ - FEAT_PMUv3p4 (PMU Extensions v3.4)
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
+ - FEAT_PMUv3p5 (PMU Extensions v3.5)
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
---- a/target/arm/mve_helper.c
+ - FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
-+++ b/target/arm/mve_helper.c
+ - FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
-@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
+ - FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
- {
++- FEAT_SVE (Scalable Vector Extension)
-     return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
++- FEAT_SVE_AES (Scalable Vector AES instructions)
- }
++- FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions)
-+
++- FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions)
-+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
++- FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions)
-+{
++- FEAT_SVE_SM4 (Scalable Vector SM4 instructions)
-+    return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
++- FEAT_SVE2 (Scalable Vector Extension version 2)
-+}
+ - FEAT_SPECRES (Speculation restriction instructions)
-+
+ - FEAT_SSBS (Speculative Store Bypass Safe)
-+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
++- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1)
-+{
++- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1)
-+    return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
++- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1)
-+}
+ - FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+ - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
-index XXXXXXX..XXXXXXX 100644
+ - FEAT_TLBIRANGE (TLB invalidate range instructions)
---- a/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
-+++ b/target/arm/translate.c
+ - FEAT_VHE (Virtualization Host Extensions)
-@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
+ - FEAT_VMID16 (16-bit VMID)
+ - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
- static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
+-- SVE (The Scalable Vector Extension)
- {
+-- SVE2 (The Scalable Vector Extension v2)
--    TCGv_i32 t = tcg_temp_new_i32();
-+    TCGv_i32 t;
+ For information on the specifics of these extensions, please refer
+ to the `Armv8-A Arm Architecture Reference Manual
 +    /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
 +    if (sh == 32) {
 +        tcg_gen_movi_i32(d, 0);
 +        return;
 +    }
 +    t = tcg_temp_new_i32();
      tcg_gen_extract_i32(t, a, sh - 1, 1);
      tcg_gen_sari_i32(d, a, sh);
      tcg_gen_add_i32(d, d, t);
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
  static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
  {
 -    TCGv_i32 t = tcg_temp_new_i32();
 +    TCGv_i32 t;
 +    /* Handle shift by the input size for the benefit of trans_URSHR_ri */
 +    if (sh == 32) {
 +        tcg_gen_extract_i32(d, a, sh - 1, 1);
 +        return;
 +    }
 +    t = tcg_temp_new_i32();
      tcg_gen_extract_i32(t, a, sh - 1, 1);
      tcg_gen_shri_i32(d, a, sh);
      tcg_gen_add_i32(d, d, t);
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
      return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
  }
 +static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
 +{
 +    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 +        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
 +        return false;
 +    }
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
 +        a->rda == 13 || a->rda == 15) {
 +        /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
 +    if (a->shim == 0) {
 +        a->shim = 32;
 +    }
 +    fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
 +
 +    return true;
 +}
 +
 +static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_urshr32_i32);
 +}
 +
 +static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_srshr32_i32);
 +}
 +
 +static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
 +{
 +    gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_mve_sqshl);
 +}
 +
 +static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
 +{
 +    gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_mve_uqshl);
 +}
 +
  /*
   * Multiply and multiply accumulate
   */
 --
-.20.1
+.34.1

-[PULL 22/24] target/arm: Implement MVE long shifts by register
+[PULL 05/21] target/arm: Enable FEAT_CSV2_3 for -cpu max
-Implement the MVE long shifts by register, which perform shifts on a
+FEAT_CSV2_3 adds a mechanism to identify if hardware cannot disclose
-pair of general-purpose registers treated as a 64-bit quantity, with
+information about whether branch targets and branch history trained
-the shift count in another general-purpose register, which might be
+in one hardware described context can control speculative execution
-either positive or negative.
+in a different hardware context.
-Like the long-shifts-by-immediate, these encodings sit in the space
+There is no branch prediction in TCG, so we don't need to do anything
-that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
+to be compliant with this.  Upadte the '-cpu max' ID registers to
-Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
+advertise the feature.
 also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
 we have to move the CSEL pattern into the same decodetree group.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20240418152004.2106516-3-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h |  6 +++
+ docs/system/arm/emulation.rst | 1 +
- target/arm/translate.h  |  1 +
+ target/arm/tcg/cpu64.c        | 4 ++--
- target/arm/t32.decode   | 16 +++++--
+files changed, 3 insertions(+), 2 deletions(-)
  target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
  target/arm/translate.c  | 69 ++++++++++++++++++++++++++++++
 files changed, 182 insertions(+), 3 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/docs/system/arm/emulation.rst
-+++ b/target/arm/helper-mve.h
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+ - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
- DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
+ - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
+ - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
-+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
++- FEAT_CSV2_3 (Cache speculation variant 2, version 3)
-+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+ - FEAT_CSV3 (Cache speculation variant 3)
- DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+ - FEAT_DGH (Data gathering hint)
- DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+ - FEAT_DIT (Data Independent Timing instructions)
-+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 +DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 +DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
 +DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
+--- a/target/arm/tcg/cpu64.c
-+++ b/target/arm/translate.h
++++ b/target/arm/tcg/cpu64.c
-@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
- typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
+     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
- typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
+     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
- typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
+     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
+-    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
++    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 3);      /* FEAT_CSV2_3 */
- /**
+     t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1);      /* FEAT_CSV3 */
-  * arm_tbflags_from_tb:
+     cpu->isar.id_aa64pfr0 = t;
-diff --git a/target/arm/t32.decode b/target/arm/t32.decode
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
---- a/target/arm/t32.decode
+     t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
-+++ b/target/arm/t32.decode
+     t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0);  /* FEAT_RASv1p1 + FEAT_DoubleFault */
-@@ -XXX,XX +XXX,XX @@
+     t = FIELD_DP64(t, ID_AA64PFR1, SME, 1);       /* FEAT_SME */
- &mcrr            !extern cp opc1 crm rt rt2
+-    t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
++    t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */
- &mve_shl_ri      rdalo rdahi shim
+     t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1);       /* FEAT_NMI */
-+&mve_shl_rr      rdalo rdahi rm
+     cpu->isar.id_aa64pfr1 = t;
  # rdahi: bits [3:1] from insn, bit 0 is 1
  # rdalo: bits [3:1] from insn, bit 0 is 0
@@ -XXX,XX +XXX,XX @@
  @mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
                   &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
 +@mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
 +                 &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
  {
    TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
      URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
      SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
      SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +
 +    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
 +    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
 +    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
 +    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
 +    UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
 +    SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
    ]
    MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
    ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
 +
 +  # v8.1M CSEL and friends
 +  CSEL           1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
  }
  {
    MVN_rxri       1110101 0011 . 1111 0 ... .... .... ....     @s_rxr_shi
@@ -XXX,XX +XXX,XX @@ SBC_rrri         1110101 1011 . .... 0 ... .... .... ....     @s_rrr_shi
  }
  RSB_rrri         1110101 1110 . .... 0 ... .... .... ....     @s_rrr_shi
 -# v8.1M CSEL and friends
 -CSEL             1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
 -
  # Data-processing (register-shifted register)
  MOV_rxrr         1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
      return rdm;
  }
 +uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
 +}
 +
 +uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_uqrshl_d(n, (int8_t)shift, false, NULL);
 +}
 +
  uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
  {
      return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
  {
      return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
  }
 +
 +uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
 +}
 +
 +uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
 +}
 +
 +/* Operate on 64-bit values, but saturate at 48 bits */
 +static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
 +                                    bool round, uint32_t *sat)
 +{
 +    if (shift <= -48) {
 +        /* Rounding the sign bit always produces 0. */
 +        if (round) {
 +            return 0;
 +        }
 +        return src >> 63;
 +    } else if (shift < 0) {
 +        if (round) {
 +            src >>= -shift - 1;
 +            return (src >> 1) + (src & 1);
 +        }
 +        return src >> -shift;
 +    } else if (shift < 48) {
 +        int64_t val = src << shift;
 +        int64_t extval = sextract64(val, 0, 48);
 +        if (!sat || val == extval) {
 +            return extval;
 +        }
 +    } else if (!sat || src == 0) {
 +        return 0;
 +    }
 +
 +    *sat = 1;
 +    return (1ULL << 47) - (src >= 0);
 +}
 +
 +/* Operate on 64-bit values, but saturate at 48 bits */
 +static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
 +                                     bool round, uint32_t *sat)
 +{
 +    uint64_t val, extval;
 +
 +    if (shift <= -(48 + round)) {
 +        return 0;
 +    } else if (shift < 0) {
 +        if (round) {
 +            val = src >> (-shift - 1);
 +            val = (val >> 1) + (val & 1);
 +        } else {
 +            val = src >> -shift;
 +        }
 +        extval = extract64(val, 0, 48);
 +        if (!sat || val == extval) {
 +            return extval;
 +        }
 +    } else if (shift < 48) {
 +        uint64_t val = src << shift;
 +        uint64_t extval = extract64(val, 0, 48);
 +        if (!sat || val == extval) {
 +            return extval;
 +        }
 +    } else if (!sat || src == 0) {
 +        return 0;
 +    }
 +
 +    *sat = 1;
 +    return MAKE_64BIT_MASK(0, 48);
 +}
 +
 +uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
 +}
 +
 +uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
      return do_mve_shl_ri(s, a, gen_urshr64_i64);
  }
 +static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
 +{
 +    TCGv_i64 rda;
 +    TCGv_i32 rdalo, rdahi;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 +        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
 +        return false;
 +    }
 +    if (a->rdahi == 15) {
 +        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
 +        return false;
 +    }
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
 +        a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
 +        a->rm == a->rdahi || a->rm == a->rdalo) {
 +        /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
 +    rda = tcg_temp_new_i64();
 +    rdalo = load_reg(s, a->rdalo);
 +    rdahi = load_reg(s, a->rdahi);
 +    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
 +
 +    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
 +    fn(rda, cpu_env, rda, cpu_R[a->rm]);
 +
 +    tcg_gen_extrl_i64_i32(rdalo, rda);
 +    tcg_gen_extrh_i64_i32(rdahi, rda);
 +    store_reg(s, a->rdalo, rdalo);
 +    store_reg(s, a->rdahi, rdahi);
 +    tcg_temp_free_i64(rda);
 +
 +    return true;
 +}
 +
 +static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
 +}
 +
 +static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
 +}
 +
 +static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
 +}
 +
 +static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
 +}
 +
 +static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
 +}
 +
 +static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
 +{
 +    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
 +}
 +
  /*
   * Multiply and multiply accumulate
   */
 --
-.20.1
+.34.1

-[PULL 21/24] target/arm: Implement MVE long shifts by immediate
+[PULL 06/21] target/arm: Enable FEAT_ETS2 for -cpu max
-The MVE extension to v8.1M includes some new shift instructions which
+FEAT_ETS2 is a tighter set of guarantees about memory ordering
-sit entirely within the non-coprocessor part of the encoding space
+involving translation table walks than the old FEAT_ETS; FEAT_ETS has
-and which operate only on general-purpose registers.  They take up
+been retired from the Arm ARM and the old ID_AA64MMFR1.ETS == 1
-the space which was previously UNPREDICTABLE MOVS and ORRS encodings
+now gives no greater guarantees than ETS == 0.
 with Rm == 13 or 15.
-Implement the long shifts by immediate, which perform shifts on a
+FEAT_ETS2 requires:
-pair of general-purpose registers treated as a 64-bit quantity, with
+ * the virtual address of a load or store that appears in program
-an immediate shift count between 1 and 32.
+   order after a DSB cannot be translated until after the DSB
    completes (section B2.10.9)
  * TLB maintenance operations that only affect translations without
    execute permission are guaranteed complete after a DSB
    (R_BLDZX)
  * if a memory access RW2 is ordered-before memory access RW2,
    then RW1 is also ordered-before any translation table walk
    generated by RW2 that generates a Translation, Address size
    or Access flag fault (R_NNFPF, I_CLGHP)
-Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
+As with FEAT_ETS, QEMU is already compliant, because we do not
-the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
+reorder translation table walk memory accesses relative to other
-cases where v8.1M now requires that.  (Trying to change MOVS and ORRS
+memory accesses, and we always guarantee to have finished TLB
-is too difficult, because the functions that generate the code are
+maintenance as soon as the TLB op is done.
 shared between a dozen different kinds of arithmetic or logical
 instruction for all A32, T16 and T32 encodings, and for some insns
 and some encodings Rm==13,15 are valid.)
-We make the helper functions we need for UQSHLL and SQSHLL take
+Update the documentation to list FEAT_ETS2 instead of the
-a 32-bit value which the helper casts to int8_t because we'll need
+no-longer-existent FEAT_ETS, and update the 'max' CPU ID registers.
 these helpers also for the shift-by-register insns, where the shift
 count might be < 0 or > 32.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20240418152004.2106516-4-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h |  3 ++
+ docs/system/arm/emulation.rst | 2 +-
- target/arm/translate.h  |  1 +
+ target/arm/tcg/cpu32.c        | 2 +-
- target/arm/t32.decode   | 28 +++++++++++++
+ target/arm/tcg/cpu64.c        | 2 +-
- target/arm/mve_helper.c | 10 +++++
+files changed, 3 insertions(+), 3 deletions(-)
  target/arm/translate.c  | 90 +++++++++++++++++++++++++++++++++++++++++
 files changed, 132 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/docs/system/arm/emulation.rst
-+++ b/target/arm/helper-mve.h
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ - FEAT_EL2 (Support for execution at EL2)
+ - FEAT_EL3 (Support for execution at EL3)
- DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
+ - FEAT_EPAC (Enhanced pointer authentication)
-+
+-- FEAT_ETS (Enhanced Translation Synchronization)
-+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
++- FEAT_ETS2 (Enhanced Translation Synchronization)
-+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+ - FEAT_EVT (Enhanced Virtualization Traps)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
+ - FEAT_F32MM (Single-precision Matrix Multiplication)
  - FEAT_F64MM (Double-precision Matrix Multiplication)
 diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
+--- a/target/arm/tcg/cpu32.c
-+++ b/target/arm/translate.h
++++ b/target/arm/tcg/cpu32.c
-@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
+@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
- typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
+     cpu->isar.id_mmfr4 = t;
- typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
- typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
+     t = cpu->isar.id_mmfr5;
-+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
+-    t = FIELD_DP32(t, ID_MMFR5, ETS, 1);          /* FEAT_ETS */
++    t = FIELD_DP32(t, ID_MMFR5, ETS, 2);          /* FEAT_ETS2 */
- /**
+     cpu->isar.id_mmfr5 = t;
-  * arm_tbflags_from_tb:
-diff --git a/target/arm/t32.decode b/target/arm/t32.decode
+     t = cpu->isar.id_pfr0;
 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/t32.decode
+--- a/target/arm/tcg/cpu64.c
-+++ b/target/arm/t32.decode
++++ b/target/arm/tcg/cpu64.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
- &mcr             !extern cp opc1 crn crm opc2 rt
+     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
- &mcrr            !extern cp opc1 crm rt rt2
+     t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
+     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
-+&mve_shl_ri      rdalo rdahi shim
+-    t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1);      /* FEAT_ETS */
-+
++    t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 2);      /* FEAT_ETS2 */
-+# rdahi: bits [3:1] from insn, bit 0 is 1
+     t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1);      /* FEAT_HCX */
-+# rdalo: bits [3:1] from insn, bit 0 is 0
+     t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1);   /* FEAT_TIDCP1 */
-+%rdahi_9 9:3 !function=times_2_plus_1
+     cpu->isar.id_aa64mmfr1 = t;
 +%rdalo_17 17:3 !function=times_2
 +
  # Data-processing (register)
  %imm5_12_6       12:3 6:2
@@ -XXX,XX +XXX,XX @@
  @S_xrr_shi       ....... .... .   rn:4 .... .... .. shty:2 rm:4 \
                   &s_rrr_shi shim=%imm5_12_6 s=1 rd=0
 +@mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
 +                 &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
 +
  {
    TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
    AND_rrri       1110101 0000 . .... 0 ... .... .... ....     @s_rrr_shi
  }
  BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
  {
 +  # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
 +  # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
 +  # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
 +  # they explicitly call unallocated_encoding() for cases that must UNDEF
 +  # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
 +  # the rest fall through (where ORR_rrri and MOV_rxri will end up
 +  # handling them as r13 and r15 accesses with the same semantics as A32).
 +  [
 +    LSLL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +    LSRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +    ASRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +
 +    UQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +    URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +    SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +    SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +  ]
 +
    MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
    ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
  }
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
      mve_advance_vpt(env);
      return rdm;
  }
 +
 +uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
 +}
 +
 +uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
      return true;
  }
 +/*
 + * v8.1M MVE wide-shifts
 + */
 +static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
 +                          WideShiftImmFn *fn)
 +{
 +    TCGv_i64 rda;
 +    TCGv_i32 rdalo, rdahi;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 +        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
 +        return false;
 +    }
 +    if (a->rdahi == 15) {
 +        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
 +        return false;
 +    }
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
 +        a->rdahi == 13) {
 +        /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
 +    if (a->shim == 0) {
 +        a->shim = 32;
 +    }
 +
 +    rda = tcg_temp_new_i64();
 +    rdalo = load_reg(s, a->rdalo);
 +    rdahi = load_reg(s, a->rdahi);
 +    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
 +
 +    fn(rda, rda, a->shim);
 +
 +    tcg_gen_extrl_i64_i32(rdalo, rda);
 +    tcg_gen_extrh_i64_i32(rdahi, rda);
 +    store_reg(s, a->rdalo, rdalo);
 +    store_reg(s, a->rdahi, rdahi);
 +    tcg_temp_free_i64(rda);
 +
 +    return true;
 +}
 +
 +static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
 +}
 +
 +static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
 +}
 +
 +static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
 +}
 +
 +static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
 +{
 +    gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_mve_sqshll);
 +}
 +
 +static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
 +{
 +    gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_mve_uqshll);
 +}
 +
 +static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_srshr64_i64);
 +}
 +
 +static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_urshr64_i64);
 +}
 +
  /*
   * Multiply and multiply accumulate
   */
 --
-.20.1
+.34.1

-[PULL 19/24] target/arm: Implement MVE VSHLC
+[PULL 07/21] target/arm: Implement ID_AA64MMFR3_EL1
-Implement the MVE VSHLC insn, which performs a shift left of the
+Newer versions of the Arm ARM (e.g.  rev K.a) now define fields for
-entire vector with carry in bits provided from a general purpose
+ID_AA64MMFR3_EL1.  Implement this register, so that we can set the
-register and carry out bits written back to that register.
+fields if we need to.  There's no behaviour change here since we
 don't currently set the register value to non-zero.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20240418152004.2106516-5-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    |  2 ++
+ target/arm/cpu.h     | 17 +++++++++++++++++
- target/arm/mve.decode      |  2 ++
+ target/arm/helper.c  |  6 ++++--
- target/arm/mve_helper.c    | 38 ++++++++++++++++++++++++++++++++++++++
+ target/arm/hvf/hvf.c |  2 ++
- target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
+ target/arm/kvm.c     |  2 ++
-files changed, 72 insertions(+)
+files changed, 25 insertions(+), 2 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/cpu.h
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
- DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+         uint64_t id_aa64mmfr0;
- DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+         uint64_t id_aa64mmfr1;
- DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+         uint64_t id_aa64mmfr2;
 +        uint64_t id_aa64mmfr3;
          uint64_t id_aa64dfr0;
          uint64_t id_aa64dfr1;
          uint64_t id_aa64zfr0;
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR2, BBM, 52, 4)
  FIELD(ID_AA64MMFR2, EVT, 56, 4)
  FIELD(ID_AA64MMFR2, E0PD, 60, 4)
 +FIELD(ID_AA64MMFR3, TCRX, 0, 4)
 +FIELD(ID_AA64MMFR3, SCTLRX, 4, 4)
 +FIELD(ID_AA64MMFR3, S1PIE, 8, 4)
 +FIELD(ID_AA64MMFR3, S2PIE, 12, 4)
 +FIELD(ID_AA64MMFR3, S1POE, 16, 4)
 +FIELD(ID_AA64MMFR3, S2POE, 20, 4)
 +FIELD(ID_AA64MMFR3, AIE, 24, 4)
 +FIELD(ID_AA64MMFR3, MEC, 28, 4)
 +FIELD(ID_AA64MMFR3, D128, 32, 4)
 +FIELD(ID_AA64MMFR3, D128_2, 36, 4)
 +FIELD(ID_AA64MMFR3, SNERR, 40, 4)
 +FIELD(ID_AA64MMFR3, ANERR, 44, 4)
 +FIELD(ID_AA64MMFR3, SDERR, 52, 4)
 +FIELD(ID_AA64MMFR3, ADERR, 56, 4)
 +FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4)
 +
-+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
+ FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
+ FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
  FIELD(ID_AA64DFR0, PMUVER, 8, 4)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
+--- a/target/arm/helper.c
-+++ b/target/arm/mve.decode
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
- VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+               .access = PL1_R, .type = ARM_CP_CONST,
- VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+               .accessfn = access_aa64_tid3,
- VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
+               .resetvalue = cpu->isar.id_aa64mmfr2 },
-+
+-            { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
-+VSHLC             111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
++            { .name = "ID_AA64MMFR3_EL1", .state = ARM_CP_STATE_AA64,
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
+               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
                .access = PL1_R, .type = ARM_CP_CONST,
                .accessfn = access_aa64_tid3,
 -              .resetvalue = 0 },
 +              .resetvalue = cpu->isar.id_aa64mmfr3 },
              { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
                .access = PL1_R, .type = ARM_CP_CONST,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .exported_bits = R_ID_AA64MMFR1_AFP_MASK },
              { .name = "ID_AA64MMFR2_EL1",
                .exported_bits = R_ID_AA64MMFR2_AT_MASK },
 +            { .name = "ID_AA64MMFR3_EL1",
 +              .exported_bits = 0 },
              { .name = "ID_AA64MMFR*_EL1_RESERVED",
                .is_glob = true },
              { .name = "ID_AA64DFR0_EL1",
 diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve_helper.c
+--- a/target/arm/hvf/hvf.c
-+++ b/target/arm/mve_helper.c
++++ b/target/arm/hvf/hvf.c
-@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
+@@ -XXX,XX +XXX,XX @@ static struct hvf_sreg_match hvf_sreg_match[] = {
- DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
+ #endif
- DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
+     { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) },
- DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
+     { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) },
-+
++    /* Add ID_AA64MMFR3_EL1 here when HVF supports it */
-+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
-+                           uint32_t shift)
+     { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) },
-+{
+     { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) },
-+    uint32_t *d = vd;
+@@ -XXX,XX +XXX,XX @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
-+    uint16_t mask = mve_element_mask(env);
+         { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
-+    unsigned e;
+         { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
-+    uint32_t r;
+         { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },
-+
++        /* Add ID_AA64MMFR3_EL1 here when HVF supports it */
-+    /*
+     };
-+     * For each 32-bit element, we shift it left, bringing in the
+     hv_vcpu_t fd;
-+     * low 'shift' bits of rdm at the bottom. Bits shifted out at
+     hv_return_t r = HV_SUCCESS;
-+     * the top become the new rdm, if the predicate mask permits.
+diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 +     * The final rdm value is returned to update the register.
 +     * shift == 0 here means "shift by 32 bits".
 +     */
 +    if (shift == 0) {
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {
 +            r = rdm;
 +            if (mask & 1) {
 +                rdm = d[H4(e)];
 +            }
 +            mergemask(&d[H4(e)], r, mask);
 +        }
 +    } else {
 +        uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
 +
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {
 +            r = (d[H4(e)] << shift) | (rdm & shiftmask);
 +            if (mask & 1) {
 +                rdm = d[H4(e)] >> (32 - shift);
 +            }
 +            mergemask(&d[H4(e)], r, mask);
 +        }
 +    }
 +    mve_advance_vpt(env);
 +    return rdm;
 +}
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
+--- a/target/arm/kvm.c
-+++ b/target/arm/translate-mve.c
++++ b/target/arm/kvm.c
-@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
+@@ -XXX,XX +XXX,XX @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
- DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
+                               ARM64_SYS_REG(3, 0, 0, 7, 1));
- DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
+         err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
- DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
+                               ARM64_SYS_REG(3, 0, 0, 7, 2));
-+
++        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3,
-+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
++                              ARM64_SYS_REG(3, 0, 0, 7, 3));
-+{
-+    /*
+         /*
-+     * Whole Vector Left Shift with Carry. The carry is taken
+          * Note that if AArch32 support is not present in the host,
 +     * from a general purpose register and written back there.
 +     * An imm of 0 means "shift by 32".
 +     */
 +    TCGv_ptr qd;
 +    TCGv_i32 rdm;
 +
 +    if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
 +        return false;
 +    }
 +    if (a->rdm == 13 || a->rdm == 15) {
 +        /* CONSTRAINED UNPREDICTABLE: we UNDEF */
 +        return false;
 +    }
 +    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    qd = mve_qreg_ptr(a->qd);
 +    rdm = load_reg(s, a->rdm);
 +    gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
 +    store_reg(s, a->rdm, rdm);
 +    tcg_temp_free_ptr(qd);
 +    mve_update_eci(s);
 +    return true;
 +}
 --
-.20.1
+.34.1

-[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
+[PULL 08/21] target/arm: Enable FEAT_Spec_FPACC for -cpu max
-Implement the MVE saturating shift-right-and-narrow insns
+FEAT_Spec_FPACC is a feature describing speculative behaviour in the
-VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
+event of a PAC authontication failure when FEAT_FPACCOMBINE is
 implemented.  FEAT_Spec_FPACC means that the speculative use of
 pointers processed by a PAC Authentication is not materially
 different in terms of the impact on cached microarchitectural state
 (caches, TLBs, etc) between passing and failing of the PAC
 Authentication.
-do_srshr() is borrowed from sve_helper.c.
+QEMU doesn't do speculative execution, so we can advertise
 this feature.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20240418152004.2106516-6-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    |  30 +++++++++++
+ docs/system/arm/emulation.rst | 1 +
- target/arm/mve.decode      |  28 ++++++++++
+ target/arm/tcg/cpu64.c        | 4 ++++
- target/arm/mve_helper.c    | 104 +++++++++++++++++++++++++++++++++++++
+files changed, 5 insertions(+)
  target/arm/translate-mve.c |  12 +++++
 files changed, 174 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/docs/system/arm/emulation.rst
-+++ b/target/arm/helper-mve.h
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ - FEAT_FP16 (Half-precision floating-point data processing)
- DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ - FEAT_FPAC (Faulting on AUT* instructions)
- DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
 +- FEAT_FPACC_SPEC (Speculative behavior of combined pointer authentication instructions)
  - FEAT_FRINTTS (Floating-point to integer instructions)
  - FEAT_FlagM (Flag manipulation instructions v2)
  - FEAT_FlagM2 (Enhancements to flag manipulation instructions)
 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/cpu64.c
 +++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
      t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1);     /* FEAT_E0PD */
      cpu->isar.id_aa64mmfr2 = t;
 +    t = cpu->isar.id_aa64mmfr3;
 +    t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
 +    cpu->isar.id_aa64mmfr3 = t;
 +
-+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     t = cpu->isar.id_aa64zfr0;
-+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
-+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */
 +DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
  VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
  VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
  VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
 +
 +VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
 +VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
 +VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
 +VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
 +VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
 +VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
 +VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
 +VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
 +
 +VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
 +VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
 +VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
 +VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
 +
 +VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
 +VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
 +VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
 +VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
 +
 +VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
 +VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
 +VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
 +VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
      }
  }
 +static inline int64_t do_srshr(int64_t x, unsigned sh)
 +{
 +    if (likely(sh < 64)) {
 +        return (x >> sh) + ((x >> (sh - 1)) & 1);
 +    } else {
 +        /* Rounding the sign bit always produces 0. */
 +        return 0;
 +    }
 +}
 +
  DO_VSHRN_ALL(vshrn, DO_SHR)
  DO_VSHRN_ALL(vrshrn, do_urshr)
 +
 +static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
 +                                 bool *satp)
 +{
 +    if (val > max) {
 +        *satp = true;
 +        return max;
 +    } else if (val < min) {
 +        *satp = true;
 +        return min;
 +    } else {
 +        return val;
 +    }
 +}
 +
 +/* Saturating narrowing right shifts */
 +#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)   \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 +                                void *vm, uint32_t shift)       \
 +    {                                                           \
 +        LTYPE *m = vm;                                          \
 +        TYPE *d = vd;                                           \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        bool qc = false;                                        \
 +        unsigned le;                                            \
 +        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
 +            bool sat = false;                                   \
 +            TYPE r = FN(m[H##LESIZE(le)], shift, &sat);         \
 +            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
 +            qc |= sat && (mask & 1 << (TOP * ESIZE));           \
 +        }                                                       \
 +        if (qc) {                                               \
 +            env->vfp.qc[0] = qc;                                \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +    }
 +
 +#define DO_VSHRN_SAT_UB(BOP, TOP, FN)                           \
 +    DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN)       \
 +    DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
 +
 +#define DO_VSHRN_SAT_UH(BOP, TOP, FN)                           \
 +    DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN)      \
 +    DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
 +
 +#define DO_VSHRN_SAT_SB(BOP, TOP, FN)                           \
 +    DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN)         \
 +    DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
 +
 +#define DO_VSHRN_SAT_SH(BOP, TOP, FN)                           \
 +    DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN)        \
 +    DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
 +
 +#define DO_SHRN_SB(N, M, SATP)                                  \
 +    do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
 +#define DO_SHRN_UB(N, M, SATP)                                  \
 +    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
 +#define DO_SHRUN_B(N, M, SATP)                                  \
 +    do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
 +
 +#define DO_SHRN_SH(N, M, SATP)                                  \
 +    do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
 +#define DO_SHRN_UH(N, M, SATP)                                  \
 +    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
 +#define DO_SHRUN_H(N, M, SATP)                                  \
 +    do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
 +
 +#define DO_RSHRN_SB(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
 +#define DO_RSHRN_UB(N, M, SATP)                                 \
 +    do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
 +#define DO_RSHRUN_B(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
 +
 +#define DO_RSHRN_SH(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
 +#define DO_RSHRN_UH(N, M, SATP)                                 \
 +    do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
 +#define DO_RSHRUN_H(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
 +
 +DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
 +DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
 +DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
 +DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
 +DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
 +DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
 +
 +DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
 +DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
 +DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
 +DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
 +DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
 +DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
  DO_2SHIFT_N(VSHRNT, vshrnt)
  DO_2SHIFT_N(VRSHRNB, vrshrnb)
  DO_2SHIFT_N(VRSHRNT, vrshrnt)
 +DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
 +DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
 +DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
 +DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
 +DO_2SHIFT_N(VQSHRUNB, vqshrunb)
 +DO_2SHIFT_N(VQSHRUNT, vqshrunt)
 +DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
 +DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
 +DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
 +DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
 +DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
 +DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
 --
-.20.1
+.34.1

-[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
+[PULL 09/21] tests/avocado: update sunxi kernel from armbian to 6.6.16
-Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
+The Linux kernel 5.10.16 binary for sunxi has been removed from
 apt.armbian.com. This means that the avocado tests for these machines
 will be skipped (status CANCEL) if the old binary isn't present in
 the avocado cache.
-do_urshr() is borrowed from sve_helper.c.
+Update to 6.6.16, in the same way we did in commit e384db41d8661
 when we moved to 5.10.16 in 2021.
+Cc: qemu-stable@nongnu.org
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2284
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
-Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
+Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
 Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
 Message-id: 20240415151845.1564201-1-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    | 10 ++++++++++
+ tests/avocado/boot_linux_console.py | 70 ++++++++++++++---------------
- target/arm/mve.decode      | 11 +++++++++++
+ tests/avocado/replay_kernel.py      |  8 ++--
- target/arm/mve_helper.c    | 40 ++++++++++++++++++++++++++++++++++++++
+files changed, 39 insertions(+), 39 deletions(-)
  target/arm/translate-mve.c | 15 ++++++++++++++
 files changed, 76 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/tests/avocado/boot_linux_console.py
-+++ b/target/arm/helper-mve.h
++++ b/tests/avocado/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
- DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+         :avocado: tags=accel:tcg
- DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+         """
- DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+         deb_url = ('https://apt.armbian.com/pool/main/l/'
-+
+-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
-+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
-+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
-+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
-+
+         kernel_path = self.extract_from_deb(deb_path,
-+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+-                                            '/boot/vmlinuz-5.10.16-sunxi')
-+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
-+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++                                            '/boot/vmlinuz-6.6.16-current-sunxi')
-+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
+         dtb_path = self.extract_from_deb(deb_path, dtb_path)
          initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
                        '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self):
          :avocado: tags=accel:tcg
          """
          deb_url = ('https://apt.armbian.com/pool/main/l/'
 -                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
 -        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
 +                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
 +        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
          deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
          kernel_path = self.extract_from_deb(deb_path,
 -                                            '/boot/vmlinuz-5.10.16-sunxi')
 -        dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
 +                                            '/boot/vmlinuz-6.6.16-current-sunxi')
 +        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
          dtb_path = self.extract_from_deb(deb_path, dtb_path)
          rootfs_url = ('https://github.com/groeck/linux-build-test/raw/'
                        '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u(self):
          :avocado: tags=machine:bpim2u
          :avocado: tags=accel:tcg
          """
 -        deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
 -                   'linux-image-current-sunxi_21.02.2_armhf.deb')
 -        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
 +        deb_url = ('https://apt.armbian.com/pool/main/l/'
 +                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
 +        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
          deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
          kernel_path = self.extract_from_deb(deb_path,
 -                                            '/boot/vmlinuz-5.10.16-sunxi')
 -        dtb_path = ('/usr/lib/linux-image-current-sunxi/'
 +                                            '/boot/vmlinuz-6.6.16-current-sunxi')
 +        dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
                      'sun8i-r40-bananapi-m2-ultra.dtb')
          dtb_path = self.extract_from_deb(deb_path, dtb_path)
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u_initrd(self):
          :avocado: tags=accel:tcg
          :avocado: tags=machine:bpim2u
          """
 -        deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
 -                   'linux-image-current-sunxi_21.02.2_armhf.deb')
 -        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
 +        deb_url = ('https://apt.armbian.com/pool/main/l/'
 +                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
 +        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
          deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
          kernel_path = self.extract_from_deb(deb_path,
 -                                            '/boot/vmlinuz-5.10.16-sunxi')
 -        dtb_path = ('/usr/lib/linux-image-current-sunxi/'
 +                                            '/boot/vmlinuz-6.6.16-current-sunxi')
 +        dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
                      'sun8i-r40-bananapi-m2-ultra.dtb')
          dtb_path = self.extract_from_deb(deb_path, dtb_path)
          initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u_gmac(self):
          """
          self.require_netdev('user')
 -        deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
 -                   'linux-image-current-sunxi_21.02.2_armhf.deb')
 -        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
 +        deb_url = ('https://apt.armbian.com/pool/main/l/'
 +                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
 +        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
          deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
          kernel_path = self.extract_from_deb(deb_path,
 -                                            '/boot/vmlinuz-5.10.16-sunxi')
 -        dtb_path = ('/usr/lib/linux-image-current-sunxi/'
 +                                            '/boot/vmlinuz-6.6.16-current-sunxi')
 +        dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
                      'sun8i-r40-bananapi-m2-ultra.dtb')
          dtb_path = self.extract_from_deb(deb_path, dtb_path)
          rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi(self):
          :avocado: tags=accel:tcg
          """
          deb_url = ('https://apt.armbian.com/pool/main/l/'
 -                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
 -        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
 +                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
 +        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
          deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
          kernel_path = self.extract_from_deb(deb_path,
 -                                            '/boot/vmlinuz-5.10.16-sunxi')
 -        dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
 +                                            '/boot/vmlinuz-6.6.16-current-sunxi')
 +        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
          dtb_path = self.extract_from_deb(deb_path, dtb_path)
          self.vm.set_console()
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_initrd(self):
          :avocado: tags=machine:orangepi-pc
          """
          deb_url = ('https://apt.armbian.com/pool/main/l/'
 -                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
 -        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
 +                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
 +        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
          deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
          kernel_path = self.extract_from_deb(deb_path,
 -                                            '/boot/vmlinuz-5.10.16-sunxi')
 -        dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
 +                                            '/boot/vmlinuz-6.6.16-current-sunxi')
 +        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
          dtb_path = self.extract_from_deb(deb_path, dtb_path)
          initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
                        '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_sd(self):
          self.require_netdev('user')
          deb_url = ('https://apt.armbian.com/pool/main/l/'
 -                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
 -        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
 +                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
 +        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
          deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
          kernel_path = self.extract_from_deb(deb_path,
 -                                            '/boot/vmlinuz-5.10.16-sunxi')
 -        dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
 +                                            '/boot/vmlinuz-6.6.16-current-sunxi')
 +        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
          dtb_path = self.extract_from_deb(deb_path, dtb_path)
          rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
                        'buildroot-baseline/20221116.0/armel/rootfs.ext2.xz')
 diff --git a/tests/avocado/replay_kernel.py b/tests/avocado/replay_kernel.py
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
+--- a/tests/avocado/replay_kernel.py
-+++ b/target/arm/mve.decode
++++ b/tests/avocado/replay_kernel.py
-@@ -XXX,XX +XXX,XX @@ VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
+@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
- VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
+         :avocado: tags=machine:cubieboard
- VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
+         """
- VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
+         deb_url = ('https://apt.armbian.com/pool/main/l/'
-+
+-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-+# Narrowing shifts (which only support b and h sizes)
+-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
-+VSHRNB            111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
++                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
-+VSHRNB            111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
++        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
-+VSHRNT            111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
+         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
-+VSHRNT            111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
+         kernel_path = self.extract_from_deb(deb_path,
-+
+-                                            '/boot/vmlinuz-5.10.16-sunxi')
-+VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
+-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
-+VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
++                                            '/boot/vmlinuz-6.6.16-current-sunxi')
-+VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
++        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
-+VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
+         dtb_path = self.extract_from_deb(deb_path, dtb_path)
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
+         initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
-index XXXXXXX..XXXXXXX 100644
+                       '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
  DO_VSHLL_ALL(vshllb, false)
  DO_VSHLL_ALL(vshllt, true)
 +
 +/*
 + * Narrowing right shifts, taking a double sized input, shifting it
 + * and putting the result in either the top or bottom half of the output.
 + * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
 + */
 +#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)       \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 +                                void *vm, uint32_t shift)       \
 +    {                                                           \
 +        LTYPE *m = vm;                                          \
 +        TYPE *d = vd;                                           \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned le;                                            \
 +        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
 +            TYPE r = FN(m[H##LESIZE(le)], shift);               \
 +            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +    }
 +
 +#define DO_VSHRN_ALL(OP, FN)                                    \
 +    DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN)        \
 +    DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN)       \
 +    DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN)         \
 +    DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
 +
 +static inline uint64_t do_urshr(uint64_t x, unsigned sh)
 +{
 +    if (likely(sh < 64)) {
 +        return (x >> sh) + ((x >> (sh - 1)) & 1);
 +    } else if (sh == 64) {
 +        return x >> 63;
 +    } else {
 +        return 0;
 +    }
 +}
 +
 +DO_VSHRN_ALL(vshrn, DO_SHR)
 +DO_VSHRN_ALL(vrshrn, do_urshr)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
  DO_VSHLL(VSHLL_BU, vshllbu)
  DO_VSHLL(VSHLL_TS, vshllts)
  DO_VSHLL(VSHLL_TU, vshlltu)
 +
 +#define DO_2SHIFT_N(INSN, FN)                                   \
 +    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
 +    {                                                           \
 +        static MVEGenTwoOpShiftFn * const fns[] = {             \
 +            gen_helper_mve_##FN##b,                             \
 +            gen_helper_mve_##FN##h,                             \
 +        };                                                      \
 +        return do_2shift(s, a, fns[a->size], false);            \
 +    }
 +
 +DO_2SHIFT_N(VSHRNB, vshrnb)
 +DO_2SHIFT_N(VSHRNT, vshrnt)
 +DO_2SHIFT_N(VRSHRNB, vrshrnb)
 +DO_2SHIFT_N(VRSHRNT, vrshrnt)
 --
-.20.1
+.34.1

-[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
+[PULL 10/21] target/arm: Refactor default generic timer frequency handling
-Implement the MVE vector shift right by immediate insns VSHRI and
+The generic timer frequency is settable by board code via a QOM
-VRSHRI.  As with Neon, we implement these by using helper functions
+property "cntfrq", but otherwise defaults to 62.5MHz.  The way this
-which perform left shifts but allow negative shift counts to indicate
+is done includes some complication resulting from how this was
-right shifts.
+originally a fixed value with no QOM property.  Clean it up:
  * always set cpu->gt_cntfrq_hz to some sensible value, whether
    the CPU has the generic timer or not, and whether it's system
    or user-only emulation
  * this means we can always use gt_cntfrq_hz, and never need
    the old GTIMER_SCALE define
  * set the default value in exactly one place, in the realize fn
 The aim here is to pave the way for handling the ARMv8.6 requirement
 that the generic timer frequency is always 1GHz.  We're going to do
 that by having old CPU types keep their legacy-in-QEMU behaviour and
 having the default for any new CPU types be a 1GHz rather han 62.5MHz
 cntfrq, so we want the point where the default is decided to be in
 one place, and in code, not in a DEFINE_PROP_UINT64() initializer.
 This commit should have no behavioural changes.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
+Message-id: 20240426122913.3427983-2-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h     | 12 ++++++++++++
+ target/arm/internals.h |  7 ++++---
- target/arm/translate.h      | 20 ++++++++++++++++++++
+ target/arm/cpu.c       | 31 +++++++++++++++++--------------
- target/arm/mve.decode       | 28 ++++++++++++++++++++++++++++
+ target/arm/helper.c    | 16 ++++++++--------
- target/arm/mve_helper.c     |  7 +++++++
+files changed, 29 insertions(+), 25 deletions(-)
  target/arm/translate-mve.c  |  5 +++++
  target/arm/translate-neon.c | 18 ------------------
 files changed, 72 insertions(+), 18 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/internals.h
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
+@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
- DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
+         || excp == EXCP_SEMIHOST;
- DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
+ }
-+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+-/* Scale factor for generic timers, ie number of ns per tick.
-+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+- * This gives a 62.5MHz timer.
-+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++/*
 + * Default frequency for the generic timer, in Hz.
 + * This is 62.5MHz, which gives a 16 ns tick period.
   */
 -#define GTIMER_SCALE 16
 +#define GTIMER_DEFAULT_HZ 62500000
  /* Bit definitions for the v7M CONTROL register */
  FIELD(V7M_CONTROL, NPRIV, 0, 1)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
      }
  }
 +/*
 + * 0 means "unset, use the default value". That default might vary depending
 + * on the CPU type, and is set in the realize fn.
 + */
  static Property arm_cpu_gt_cntfrq_property =
 -            DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz,
 -                               NANOSECONDS_PER_SECOND / GTIMER_SCALE);
 +            DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0);
  static Property arm_cpu_reset_cbar_property =
              DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
          return;
      }
 +    if (!cpu->gt_cntfrq_hz) {
 +        /*
 +         * 0 means "the board didn't set a value, use the default".
 +         * The default value of the generic timer frequency (as seen in
 +         * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns.
 +         * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the
 +         * board doesn't set it.
 +         */
 +        cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
 +    }
 +
- DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ #ifndef CONFIG_USER_ONLY
- DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     /* The NVIC and M-profile CPU are two halves of a single piece of
- DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+      * hardware; trying to use one without the other is a command line
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
- DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     }
- DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     {
 -        uint64_t scale;
 -
 -        if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
 -            if (!cpu->gt_cntfrq_hz) {
 -                error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
 -                           cpu->gt_cntfrq_hz);
 -                return;
 -            }
 -            scale = gt_cntfrq_period_ns(cpu);
 -        } else {
 -            scale = GTIMER_SCALE;
 -        }
 +        uint64_t scale = gt_cntfrq_period_ns(cpu);
          cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
                                                 arm_gt_ptimer_cb, cpu);
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
        .resetvalue = 0 },
  };
 +static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
 +{
 +    ARMCPU *cpu = env_archcpu(env);
 +
-+DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
 +DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
      return x * 2 + 1;
  }
 +static inline int rsub_64(DisasContext *s, int x)
 +{
 +    return 64 - x;
 +}
 +
-+static inline int rsub_32(DisasContext *s, int x)
+ #ifndef CONFIG_USER_ONLY
-+{
-+    return 32 - x;
+ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
-+}
+@@ -XXX,XX +XXX,XX @@ void arm_gt_hvtimer_cb(void *opaque)
-+
+     gt_recalc_timer(cpu, GTIMER_HYPVIRT);
 +static inline int rsub_16(DisasContext *s, int x)
 +{
 +    return 16 - x;
 +}
 +
 +static inline int rsub_8(DisasContext *s, int x)
 +{
 +    return 8 - x;
 +}
 +
  static inline int arm_dc_feature(DisasContext *dc, int feature)
  {
      return (dc->features & (1ULL << feature)) != 0;
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
  @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
  @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
 +# Right shifts are encoded as N - shift, where N is the element size in bits.
 +%rshift_i5  16:5 !function=rsub_32
 +%rshift_i4  16:4 !function=rsub_16
 +%rshift_i3  16:3 !function=rsub_8
 +
 +@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
 +         size=0 shift=%rshift_i3
 +@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
 +         size=1 shift=%rshift_i4
 +@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
 +         size=2 shift=%rshift_i5
 +
  # Vector loads and stores
  # Widening loads and narrowing stores:
@@ -XXX,XX +XXX,XX @@ VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
  VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
  VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
  VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
 +
 +VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
 +VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
 +VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
 +
 +VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
 +VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
 +VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
 +
 +VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 +VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 +VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 +
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
      DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
      DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
      DO_2SHIFT(OP##w, 4, uint32_t, FN)
 +#define DO_2SHIFT_S(OP, FN)                     \
 +    DO_2SHIFT(OP##b, 1, int8_t, FN)             \
 +    DO_2SHIFT(OP##h, 2, int16_t, FN)            \
 +    DO_2SHIFT(OP##w, 4, int32_t, FN)
  #define DO_2SHIFT_SAT_U(OP, FN)                 \
      DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
      DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
  DO_2SHIFT_U(vshli_u, DO_VSHLU)
 +DO_2SHIFT_S(vshli_s, DO_VSHLS)
  DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
  DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
  DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
 +DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
 +DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
  DO_2SHIFT(VQSHLI_S, vqshli_s, false)
  DO_2SHIFT(VQSHLI_U, vqshli_u, false)
  DO_2SHIFT(VQSHLUI, vqshlui_s, false)
 +/* These right shifts use a left-shift helper with negated shift count */
 +DO_2SHIFT(VSHRI_S, vshli_s, true)
 +DO_2SHIFT(VSHRI_U, vshli_u, true)
 +DO_2SHIFT(VRSHRI_S, vrshli_s, true)
 +DO_2SHIFT(VRSHRI_U, vrshli_u, true)
 diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.c
 +++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
      return x + 1;
  }
--static inline int rsub_64(DisasContext *s, int x)
+-static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
 -{
--    return 64 - x;
+-    ARMCPU *cpu = env_archcpu(env);
 -
 -    cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
 -}
 -
--static inline int rsub_32(DisasContext *s, int x)
+ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
--{
+     /*
--    return 32 - x;
+      * Note that CNTFRQ is purely reads-as-written for the benefit
--}
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
--static inline int rsub_16(DisasContext *s, int x)
+       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
--{
+       .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */,
--    return 16 - x;
+       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
--}
+-      .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE,
--static inline int rsub_8(DisasContext *s, int x)
++      .resetfn = arm_gt_cntfrq_reset,
--{
+     },
--    return 8 - x;
+     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
--}
+       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
 -
  static inline int neon_3same_fp_size(DisasContext *s, int x)
  {
      /* Convert 0==fp32, 1==fp16 into a MO_* value */
 --
-.20.1
+.34.1

-[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
+[PULL 11/21] hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz
-Implement the MVE VSRI and VSLI insns, which perform a
+Currently QEMU CPUs always run with a generic timer counter frequency
-shift-and-insert operation.
+of 62.5MHz, but ARMv8.6 CPUs will run at 1GHz.  For older versions of
 the TF-A firmware that sbsa-ref runs, the frequency of the generic
 timer is hardcoded into the firmware, and so if the CPU actually has
 a different frequency then timers in the guest will be set
 incorrectly.
 The default frequency used by the 'max' CPU is about to change, so
 make the sbsa-ref board force the CPU frequency to the value which
 the firmware expects.
 Newer versions of TF-A will read the frequency from the CPU's
 CNTFRQ_EL0 register:
  https://github.com/ARM-software/arm-trusted-firmware/commit/4c77fac98dac0bebc63798aae9101ac865b87148
 so in the longer term we could make this board use the 1GHz
 frequency. We will need to make sure we update the binaries used
 by our avocado test
  Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef
 before we can do that.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
+Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
 Message-id: 20240426122913.3427983-3-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    |  8 ++++++++
+ hw/arm/sbsa-ref.c | 15 +++++++++++++++
- target/arm/mve.decode      |  9 ++++++++
+file changed, 15 insertions(+)
  target/arm/mve_helper.c    | 42 ++++++++++++++++++++++++++++++++++++++
  target/arm/translate-mve.c |  3 +++
 files changed, 62 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/hw/arm/sbsa-ref.c
-+++ b/target/arm/helper-mve.h
++++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@
- DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ #define NUM_SMMU_IRQS   4
- DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ #define NUM_SATA_PORTS  6
- DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +/*
 + * Generic timer frequency in Hz (which drives both the CPU generic timers
 + * and the SBSA watchdog-timer). Older versions of the TF-A firmware
 + * typically used with sbsa-ref (including the binaries in our Avocado test
 + * Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef
 + * assume it is this value.
 + *
 + * TODO: this value is not architecturally correct for an Armv8.6 or
 + * better CPU, so we should move to 1GHz once the TF-A fix above has
 + * made it into a release and into our Avocado test.
 + */
 +#define SBSA_GTIMER_HZ 62500000
 +
-+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ enum {
-+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     SBSA_FLASH,
-+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     SBSA_MEM,
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
                                      &error_abort);
          }
 +        object_property_set_int(cpuobj, "cntfrq", SBSA_GTIMER_HZ, &error_abort);
 +
-+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+         object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
-+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+                                  &error_abort);
-+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
  VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
  VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
 +
 +# Shift-and-insert
 +VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
 +VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
 +VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
 +
 +VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
 +VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
 +VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
  DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
  DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
 +/* Shift-and-insert; we always work with 64 bits at a time */
 +#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN)                    \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
 +                                void *vm, uint32_t shift)               \
 +    {                                                                   \
 +        uint64_t *d = vd, *m = vm;                                      \
 +        uint16_t mask;                                                  \
 +        uint64_t shiftmask;                                             \
 +        unsigned e;                                                     \
 +        if (shift == 0 || shift == ESIZE * 8) {                         \
 +            /*                                                          \
 +             * Only VSLI can shift by 0; only VSRI can shift by <dt>.   \
 +             * The generic logic would give the right answer for 0 but  \
 +             * fails for <dt>.                                          \
 +             */                                                         \
 +            goto done;                                                  \
 +        }                                                               \
 +        assert(shift < ESIZE * 8);                                      \
 +        mask = mve_element_mask(env);                                   \
 +        /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */     \
 +        shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift));     \
 +        for (e = 0; e < 16 / 8; e++, mask >>= 8) {                      \
 +            uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) |       \
 +                (d[H8(e)] & ~shiftmask);                                \
 +            mergemask(&d[H8(e)], r, mask);                              \
 +        }                                                               \
 +done:                                                                   \
 +        mve_advance_vpt(env);                                           \
 +    }
 +
 +#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
 +#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
 +#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
 +#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
 +
 +DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
 +DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
 +DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
 +DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
 +DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
 +DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
 +
  /*
   * Long shifts taking half-sized inputs from top or bottom of the input
   * vector and producing a double-width result. ESIZE, TYPE are for
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
  DO_2SHIFT(VRSHRI_S, vrshli_s, true)
  DO_2SHIFT(VRSHRI_U, vrshli_u, true)
 +DO_2SHIFT(VSRI, vsri, false)
 +DO_2SHIFT(VSLI, vsli, false)
 +
  #define DO_VSHLL(INSN, FN)                                      \
      static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
      {                                                           \
 --
-.20.1
+.34.1

-[PULL 09/24] target/arm: Make asimd_imm_const() public
+[PULL 12/21] hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property
-The function asimd_imm_const() in translate-neon.c is an
+Currently the sbsa_gdwt watchdog device hardcodes its frequency at
-implementation of the pseudocode AdvSIMDExpandImm(), which we will
+.5MHz. In real hardware, this watchdog is supposed to be driven
-also want for MVE.  Move the implementation to translate.c, with a
+from the system counter, which also drives the CPU generic timers.
-prototype in translate.h.
+Newer CPU types (in particular from Armv8.6) should have a CPU
 generic timer frequency of 1GHz, so we can't leave the watchdog
 on the old QEMU default of 62.5GHz.
 Make the frequency a QOM property so it can be set by the board,
 and have our only board that uses this device set that frequency
 to the same value it sets the CPU frequency.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
+Message-id: 20240426122913.3427983-4-peter.maydell@linaro.org
 ---
- target/arm/translate.h      | 16 ++++++++++
+ include/hw/watchdog/sbsa_gwdt.h |  3 +--
- target/arm/translate-neon.c | 63 -------------------------------------
+ hw/arm/sbsa-ref.c               |  1 +
- target/arm/translate.c      | 57 +++++++++++++++++++++++++++++++++
+ hw/watchdog/sbsa_gwdt.c         | 15 ++++++++++++++-
-files changed, 73 insertions(+), 63 deletions(-)
+files changed, 16 insertions(+), 3 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
+diff --git a/include/hw/watchdog/sbsa_gwdt.h b/include/hw/watchdog/sbsa_gwdt.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
+--- a/include/hw/watchdog/sbsa_gwdt.h
-+++ b/target/arm/translate.h
++++ b/include/hw/watchdog/sbsa_gwdt.h
-@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
+@@ -XXX,XX +XXX,XX @@
-     return opc | s->be_data;
+ #define SBSA_GWDT_RMMIO_SIZE 0x1000
  #define SBSA_GWDT_CMMIO_SIZE 0x1000
 -#define SBSA_TIMER_FREQ      62500000 /* Hz */
 -
  typedef struct SBSA_GWDTState {
      /* <private> */
      SysBusDevice parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct SBSA_GWDTState {
      qemu_irq irq;
      QEMUTimer *timer;
 +    uint64_t freq;
      uint32_t id;
      uint32_t wcs;
 diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/sbsa-ref.c
 +++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static void create_wdt(const SBSAMachineState *sms)
      SysBusDevice *s = SYS_BUS_DEVICE(dev);
      int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0];
 +    qdev_prop_set_uint64(dev, "clock-frequency", SBSA_GTIMER_HZ);
      sysbus_realize_and_unref(s, &error_fatal);
      sysbus_mmio_map(s, 0, rbase);
      sysbus_mmio_map(s, 1, cbase);
 diff --git a/hw/watchdog/sbsa_gwdt.c b/hw/watchdog/sbsa_gwdt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/watchdog/sbsa_gwdt.c
 +++ b/hw/watchdog/sbsa_gwdt.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "sysemu/reset.h"
  #include "sysemu/watchdog.h"
 +#include "hw/qdev-properties.h"
  #include "hw/watchdog/sbsa_gwdt.h"
  #include "qemu/timer.h"
  #include "migration/vmstate.h"
@@ -XXX,XX +XXX,XX @@ static void sbsa_gwdt_update_timer(SBSA_GWDTState *s, WdtRefreshType rtype)
          timeout = s->woru;
          timeout <<= 32;
          timeout |= s->worl;
 -        timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, SBSA_TIMER_FREQ);
 +        timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, s->freq);
          timeout += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
          if ((rtype == EXPLICIT_REFRESH) || ((rtype == TIMEOUT_REFRESH) &&
@@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_realize(DeviceState *dev, Error **errp)
                  dev);
  }
-+/**
++static Property wdt_sbsa_gwdt_props[] = {
-+ * asimd_imm_const: Expand an encoded SIMD constant value
++    /*
-+ *
++     * Timer frequency in Hz. This must match the frequency used by
-+ * Expand a SIMD constant value. This is essentially the pseudocode
++     * the CPU's generic timer. Default 62.5Hz matches QEMU's legacy
-+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
++     * CPU timer frequency default.
-+ * VMVN and VBIC (when cmode < 14 && op == 1).
++     */
-+ *
++    DEFINE_PROP_UINT64("clock-frequency", struct SBSA_GWDTState, freq,
-+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
++                       62500000),
-+ * callers must catch this.
++    DEFINE_PROP_END_OF_LIST(),
-+ *
++};
 + * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
 + * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
 + * we produce an immediate constant value of 0 in these cases.
 + */
 +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
 +
- #endif /* TARGET_ARM_TRANSLATE_H */
+ static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
 diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.c
 +++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
  DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
  DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
 -static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
 -{
 -    /*
 -     * Expand the encoded constant.
 -     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
 -     * We choose to not special-case this and will behave as if a
 -     * valid constant encoding of 0 had been given.
 -     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
 -     */
 -    switch (cmode) {
 -    case 0: case 1:
 -        /* no-op */
 -        break;
 -    case 2: case 3:
 -        imm <<= 8;
 -        break;
 -    case 4: case 5:
 -        imm <<= 16;
 -        break;
 -    case 6: case 7:
 -        imm <<= 24;
 -        break;
 -    case 8: case 9:
 -        imm |= imm << 16;
 -        break;
 -    case 10: case 11:
 -        imm = (imm << 8) | (imm << 24);
 -        break;
 -    case 12:
 -        imm = (imm << 8) | 0xff;
 -        break;
 -    case 13:
 -        imm = (imm << 16) | 0xffff;
 -        break;
 -    case 14:
 -        if (op) {
 -            /*
 -             * This is the only case where the top and bottom 32 bits
 -             * of the encoded constant differ.
 -             */
 -            uint64_t imm64 = 0;
 -            int n;
 -
 -            for (n = 0; n < 8; n++) {
 -                if (imm & (1 << n)) {
 -                    imm64 |= (0xffULL << (n * 8));
 -                }
 -            }
 -            return imm64;
 -        }
 -        imm |= (imm << 8) | (imm << 16) | (imm << 24);
 -        break;
 -    case 15:
 -        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
 -            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
 -        break;
 -    }
 -    if (op) {
 -        imm = ~imm;
 -    }
 -    return dup_const(MO_32, imm);
 -}
 -
  static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
                          GVecGen2iFn *fn)
  {
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+     DeviceClass *dc = DEVICE_CLASS(klass);
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
---- a/target/arm/translate.c
+     set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
-+++ b/target/arm/translate.c
+     dc->vmsd = &vmstate_sbsa_gwdt;
-@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
+     dc->desc = "SBSA-compliant generic watchdog device";
-     a64_translate_init();
++    device_class_set_props(dc, wdt_sbsa_gwdt_props);
  }
-+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
+ static const TypeInfo wdt_sbsa_gwdt_info = {
 +{
 +    /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
 +    switch (cmode) {
 +    case 0: case 1:
 +        /* no-op */
 +        break;
 +    case 2: case 3:
 +        imm <<= 8;
 +        break;
 +    case 4: case 5:
 +        imm <<= 16;
 +        break;
 +    case 6: case 7:
 +        imm <<= 24;
 +        break;
 +    case 8: case 9:
 +        imm |= imm << 16;
 +        break;
 +    case 10: case 11:
 +        imm = (imm << 8) | (imm << 24);
 +        break;
 +    case 12:
 +        imm = (imm << 8) | 0xff;
 +        break;
 +    case 13:
 +        imm = (imm << 16) | 0xffff;
 +        break;
 +    case 14:
 +        if (op) {
 +            /*
 +             * This is the only case where the top and bottom 32 bits
 +             * of the encoded constant differ.
 +             */
 +            uint64_t imm64 = 0;
 +            int n;
 +
 +            for (n = 0; n < 8; n++) {
 +                if (imm & (1 << n)) {
 +                    imm64 |= (0xffULL << (n * 8));
 +                }
 +            }
 +            return imm64;
 +        }
 +        imm |= (imm << 8) | (imm << 16) | (imm << 24);
 +        break;
 +    case 15:
 +        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
 +            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
 +        break;
 +    }
 +    if (op) {
 +        imm = ~imm;
 +    }
 +    return dup_const(MO_32, imm);
 +}
 +
  /* Generate a label used for skipping this instruction */
  void arm_gen_condlabel(DisasContext *s)
  {
 --
-.20.1
+.34.1

-[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
+[PULL 13/21] target/arm: Default to 1GHz cntfrq for 'max' and new CPUs
-The A64 AdvSIMD modified-immediate grouping uses almost the same
+In previous versions of the Arm architecture, the frequency of the
-constant encoding that A32 Neon does; reuse asimd_imm_const() (to
+generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
-which we add the AArch64-specific case for cmode 15 op 1) instead of
+and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
-reimplementing it all.
+In Armv8.6, the architecture standardized this frequency to 1GHz.
 Because there is no ID register feature field that indicates whether
 a CPU is v8.6 or that it ought to have this counter frequency, we
 implement this by changing our default CNTFRQ value for all CPUs,
 with exceptions for backwards compatibility:
  * CPU types which we already implement will retain the old
    default value. None of these are v8.6 CPUs, so this is
    architecturally OK.
  * CPUs used in versioned machine types with a version of 9.0
    or earlier will retain the old default value.
 The upshot is that the only CPU type that changes is 'max'; but any
 new type we add in future (whether v8.6 or not) will also get the new
 GHz default.
 It remains the case that the machine model can override the default
 value via the 'cntfrq' QOM property (regardless of the CPU type).
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20240426122913.3427983-5-peter.maydell@linaro.org
 ---
- target/arm/translate.h     |  3 +-
+ target/arm/cpu.h       | 11 +++++++++++
- target/arm/translate-a64.c | 86 ++++----------------------------------
+ target/arm/internals.h | 12 ++++++++++--
- target/arm/translate.c     | 17 +++++++-
+ hw/core/machine.c      |  4 +++-
-files changed, 24 insertions(+), 82 deletions(-)
+ target/arm/cpu.c       | 23 +++++++++++++++++------
+ target/arm/cpu64.c     |  2 ++
-diff --git a/target/arm/translate.h b/target/arm/translate.h
+ target/arm/tcg/cpu32.c |  4 ++++
-index XXXXXXX..XXXXXXX 100644
+ target/arm/tcg/cpu64.c | 18 ++++++++++++++++++
---- a/target/arm/translate.h
+files changed, 65 insertions(+), 9 deletions(-)
-+++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-  * VMVN and VBIC (when cmode < 14 && op == 1).
+index XXXXXXX..XXXXXXX 100644
-  *
+--- a/target/arm/cpu.h
-  * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
++++ b/target/arm/cpu.h
-- * callers must catch this.
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
-+ * callers must catch this; we return the 64-bit constant value defined
+      */
-+ * for AArch64.
+     bool host_cpu_probe_failed;
-  *
-  * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
++    /* QOM property to indicate we should use the back-compat CNTFRQ default */
-  * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
++    bool backcompat_cntfrq;
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
++
-index XXXXXXX..XXXXXXX 100644
+     /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
---- a/target/arm/translate-a64.c
+      * register.
-+++ b/target/arm/translate-a64.c
+      */
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ enum arm_features {
- {
+     ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
-     int rd = extract32(insn, 0, 5);
+     ARM_FEATURE_M_MAIN, /* M profile Main Extension */
-     int cmode = extract32(insn, 12, 4);
+     ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
--    int cmode_3_1 = extract32(cmode, 1, 3);
++    /*
--    int cmode_0 = extract32(cmode, 0, 1);
++     * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz
-     int o2 = extract32(insn, 11, 1);
++     * if the board doesn't set a value, instead of 1GHz. It is for backwards
-     uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
++     * compatibility and used only with CPU definitions that were already
-     bool is_neg = extract32(insn, 29, 1);
++     * in QEMU before we changed the default. It should not be set on any
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
++     * CPU types added in future.
-         return;
++     */
 +    ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
  };
  static inline int arm_feature(CPUARMState *env, int feature)
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
  /*
   * Default frequency for the generic timer, in Hz.
 - * This is 62.5MHz, which gives a 16 ns tick period.
 + * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
 + * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
 + * which gives a 16ns tick period.
 + *
 + * We will use the back-compat value:
 + *  - for QEMU CPU types added before we standardized on 1GHz
 + *  - for versioned machine types with a version of 9.0 or earlier
 + * In any case, the machine model may override via the cntfrq property.
   */
 -#define GTIMER_DEFAULT_HZ 62500000
 +#define GTIMER_DEFAULT_HZ 1000000000
 +#define GTIMER_BACKCOMPAT_HZ 62500000
  /* Bit definitions for the v7M CONTROL register */
  FIELD(V7M_CONTROL, NPRIV, 0, 1)
 diff --git a/hw/core/machine.c b/hw/core/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/machine.c
 +++ b/hw/core/machine.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/virtio/virtio-iommu.h"
  #include "audio/audio.h"
 -GlobalProperty hw_compat_9_0[] = {};
 +GlobalProperty hw_compat_9_0[] = {
 +    {"arm-cpu", "backcompat-cntfrq", "true" },
 +};
  const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0);
  GlobalProperty hw_compat_8_2[] = {
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
      if (!cpu->gt_cntfrq_hz) {
          /*
 -         * 0 means "the board didn't set a value, use the default".
 -         * The default value of the generic timer frequency (as seen in
 -         * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns.
 -         * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the
 -         * board doesn't set it.
 +         * 0 means "the board didn't set a value, use the default". (We also
 +         * get here for the CONFIG_USER_ONLY case.)
 +         * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
 +         * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
 +         * which gives a 16ns tick period.
 +         *
 +         * We will use the back-compat value:
 +         *  - for QEMU CPU types added before we standardized on 1GHz
 +         *  - for versioned machine types with a version of 9.0 or earlier
           */
 -        cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
 +        if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) ||
 +            cpu->backcompat_cntfrq) {
 +            cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
 +        } else {
 +            cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
 +        }
      }
--    /* See AdvSIMDExpandImm() in ARM ARM */
+ #ifndef CONFIG_USER_ONLY
--    switch (cmode_3_1) {
+@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_properties[] = {
--    case 0: /* Replicate(Zeros(24):imm8, 2) */
+                         mp_affinity, ARM64_AFFINITY_INVALID),
--    case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
+     DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
--    case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
+     DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
--    case 3: /* Replicate(imm8:Zeros(24), 2) */
++    /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */
--    {
++    DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false),
--        int shift = cmode_3_1 * 8;
+     DEFINE_PROP_END_OF_LIST()
--        imm = bitfield_replicate(abcdefgh << shift, 32);
+ };
--        break;
--    }
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
--    case 4: /* Replicate(Zeros(8):imm8, 4) */
+index XXXXXXX..XXXXXXX 100644
--    case 5: /* Replicate(imm8:Zeros(8), 4) */
+--- a/target/arm/cpu64.c
--    {
++++ b/target/arm/cpu64.c
--        int shift = (cmode_3_1 & 0x1) * 8;
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
--        imm = bitfield_replicate(abcdefgh << shift, 16);
+     set_feature(&cpu->env, ARM_FEATURE_V8);
--        break;
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
--    }
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
--    case 6:
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
--        if (cmode_0) {
+     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
--            /* Replicate(Zeros(8):imm8:Ones(16), 2) */
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
--            imm = (abcdefgh << 16) | 0xffff;
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
--        } else {
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
--            /* Replicate(Zeros(16):imm8:Ones(8), 2) */
+     set_feature(&cpu->env, ARM_FEATURE_V8);
--            imm = (abcdefgh << 8) | 0xff;
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
--        }
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
--        imm = bitfield_replicate(imm, 32);
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
--        break;
+     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
--    case 7:
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
--        if (!cmode_0 && !is_neg) {
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
--            imm = bitfield_replicate(abcdefgh, 8);
+diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
--        } else if (!cmode_0 && is_neg) {
+index XXXXXXX..XXXXXXX 100644
--            int i;
+--- a/target/arm/tcg/cpu32.c
--            imm = 0;
++++ b/target/arm/tcg/cpu32.c
--            for (i = 0; i < 8; i++) {
+@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
--                if ((abcdefgh) & (1 << i)) {
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
--                    imm |= 0xffULL << (i * 8);
+     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
--                }
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
--            }
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
--        } else if (cmode_0) {
+     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
--            if (is_neg) {
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
--                imm = (abcdefgh & 0x3f) << 48;
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
--                if (abcdefgh & 0x80) {
+@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
--                    imm |= 0x8000000000000000ULL;
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
--                }
+     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
--                if (abcdefgh & 0x40) {
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
--                    imm |= 0x3fc0000000000000ULL;
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
--                } else {
+     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
--                    imm |= 0x4000000000000000ULL;
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
--                }
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
--            } else {
+@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
--                if (o2) {
+     set_feature(&cpu->env, ARM_FEATURE_PMSA);
--                    /* FMOV (vector, immediate) - half-precision */
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
--                    imm = vfp_expand_imm(MO_16, abcdefgh);
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
--                    /* now duplicate across the lanes */
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
--                    imm = bitfield_replicate(imm, 16);
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
--                } else {
+     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
--                    imm = (abcdefgh & 0x3f) << 19;
+     cpu->midr = 0x411fd133; /* r1p3 */
--                    if (abcdefgh & 0x80) {
+@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
--                        imm |= 0x80000000;
+     set_feature(&cpu->env, ARM_FEATURE_V8);
--                    }
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
--                    if (abcdefgh & 0x40) {
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
--                        imm |= 0x3e000000;
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
--                    } else {
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
--                        imm |= 0x40000000;
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
--                    }
+     set_feature(&cpu->env, ARM_FEATURE_EL3);
--                    imm |= (imm << 32);
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
--                }
+index XXXXXXX..XXXXXXX 100644
--            }
+--- a/target/arm/tcg/cpu64.c
--        }
++++ b/target/arm/tcg/cpu64.c
--        break;
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
--    default:
+     set_feature(&cpu->env, ARM_FEATURE_V8);
--        g_assert_not_reached();
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
--    }
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
--
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
--    if (cmode_3_1 != 7 && is_neg) {
+     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
--        imm = ~imm;
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-+    if (cmode == 15 && o2 && !is_neg) {
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
-+        /* FMOV (vector, immediate) - half-precision */
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a55_initfn(Object *obj)
-+        imm = vfp_expand_imm(MO_16, abcdefgh);
+     set_feature(&cpu->env, ARM_FEATURE_V8);
-+        /* now duplicate across the lanes */
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
-+        imm = bitfield_replicate(imm, 16);
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-+    } else {
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
-+        imm = asimd_imm_const(abcdefgh, cmode, is_neg);
+     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-     }
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
-     if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+     set_feature(&cpu->env, ARM_FEATURE_V8);
-index XXXXXXX..XXXXXXX 100644
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
---- a/target/arm/translate.c
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-+++ b/target/arm/translate.c
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
-@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
+     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-     case 14:
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-         if (op) {
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
-             /*
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
--             * This is the only case where the top and bottom 32 bits
+     set_feature(&cpu->env, ARM_FEATURE_V8);
--             * of the encoded constant differ.
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
-+             * This and cmode == 15 op == 1 are the only cases where
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-+             * the top and bottom 32 bits of the encoded constant differ.
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
-              */
+     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-             uint64_t imm64 = 0;
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-             int n;
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
-@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
-         imm |= (imm << 8) | (imm << 16) | (imm << 24);
+     set_feature(&cpu->env, ARM_FEATURE_V8);
-         break;
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
-     case 15:
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-+        if (op) {
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
-+            /* Reserved encoding for AArch32; valid for AArch64 */
+     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-+            uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
-+            if (imm & 0x80) {
+     set_feature(&cpu->env, ARM_FEATURE_EL3);
-+                imm64 |= 0x8000000000000000ULL;
+@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n1_initfn(Object *obj)
-+            }
+     set_feature(&cpu->env, ARM_FEATURE_V8);
-+            if (imm & 0x40) {
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
-+                imm64 |= 0x3fc0000000000000ULL;
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-+            } else {
++    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
-+                imm64 |= 0x4000000000000000ULL;
+     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-+            }
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
-+            return imm64;
+     set_feature(&cpu->env, ARM_FEATURE_EL2);
-+        }
+@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
-         imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
+     set_feature(&cpu->env, ARM_FEATURE_V8);
-             | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
-         break;
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
      set_feature(&cpu->env, ARM_FEATURE_AARCH64);
      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
      set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a710_initfn(Object *obj)
      set_feature(&cpu->env, ARM_FEATURE_V8);
      set_feature(&cpu->env, ARM_FEATURE_NEON);
      set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
      set_feature(&cpu->env, ARM_FEATURE_AARCH64);
      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
      set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n2_initfn(Object *obj)
      set_feature(&cpu->env, ARM_FEATURE_V8);
      set_feature(&cpu->env, ARM_FEATURE_NEON);
      set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 +    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
      set_feature(&cpu->env, ARM_FEATURE_AARCH64);
      set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
      set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
      uint64_t t;
      uint32_t u;
 +    /*
 +     * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default
 +     * to because we started with aarch64_a57_initfn(). A 'max' CPU might
 +     * be a v8.6-or-later one, in which case the cntfrq must be 1GHz; and
 +     * because it is our "may change" CPU type we are OK with it not being
 +     * backwards-compatible with how it worked in old QEMU.
 +     */
 +    unset_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
 +
      /*
       * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
       * one and try to apply errata workarounds or use impdef features we
 --
-.20.1
+.34.1

-[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
+[PULL 14/21] hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
-From: Patrick Venture <venture@google.com>
+From: Alexandra Diupina <adiupina@astralinux.ru>
-Add line item reference to quanta-gbs-bmc machine.
+The DMA descriptor structures for this device have
 a set of "address extension" fields which extend the 32
 bit source addresses with an extra 16 bits to give a
 bit address:
  https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field
-Signed-off-by: Patrick Venture <venture@google.com>
+However, we misimplemented this address extension in several ways:
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
+ * we only extracted 12 bits of the extension fields, not 16
-Message-id: 20210615192848.1065297-3-venture@google.com
+ * we didn't shift the extension field up far enough
-[PMM: fixed underline Sphinx warning]
+ * we accidentally did the shift as 32-bit arithmetic, which
    meant that we would have an overflow instead of setting
    bits [47:32] of the resulting 64-bit address
 Add a type cast and use extract64() instead of extract32()
 to avoid integer overflow on addition. Fix bit fields
 extraction according to documentation.
 Found by Linux Verification Center (linuxtesting.org) with SVACE.
 Cc: qemu-stable@nongnu.org
 Fixes: d3c6369a96 ("introduce xlnx-dpdma")
 Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
 Message-id: 20240428181131.23801-1-adiupina@astralinux.ru
 [PMM: adjusted commit message]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/nuvoton.rst | 5 +++--
+ hw/dma/xlnx_dpdma.c | 20 ++++++++++----------
-file changed, 3 insertions(+), 2 deletions(-)
+file changed, 10 insertions(+), 10 deletions(-)
-diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
+diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/nuvoton.rst
+--- a/hw/dma/xlnx_dpdma.c
-+++ b/docs/system/arm/nuvoton.rst
++++ b/hw/dma/xlnx_dpdma.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static uint64_t xlnx_dpdma_desc_get_source_address(DPDMADescriptor *desc,
--Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
--=====================================================
+     switch (frag) {
-+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
+     case 0:
-+================================================================
+-        addr = desc->source_address
+-            + (extract32(desc->address_extension, 16, 12) << 20);
- The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
++        addr = (uint64_t)desc->source_address
- designed to be used as Baseboard Management Controllers (BMCs) in various
++            + (extract64(desc->address_extension, 16, 16) << 32);
-@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
+         break;
- The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
+     case 1:
- Hyperscale applications. The following machines are based on this chip :
+-        addr = desc->source_address2
+-            + (extract32(desc->address_extension_23, 0, 12) << 8);
-+- ``quanta-gbs-bmc``    Quanta GBS server BMC
++        addr = (uint64_t)desc->source_address2
- - ``quanta-gsj``        Quanta GSJ server BMC
++            + (extract64(desc->address_extension_23, 0, 16) << 32);
+         break;
- There are also two more SoCs, NPCM710 and NPCM705, which are single-core
+     case 2:
 -        addr = desc->source_address3
 -            + (extract32(desc->address_extension_23, 16, 12) << 20);
 +        addr = (uint64_t)desc->source_address3
 +            + (extract64(desc->address_extension_23, 16, 16) << 32);
          break;
      case 3:
 -        addr = desc->source_address4
 -            + (extract32(desc->address_extension_45, 0, 12) << 8);
 +        addr = (uint64_t)desc->source_address4
 +            + (extract64(desc->address_extension_45, 0, 16) << 32);
          break;
      case 4:
 -        addr = desc->source_address5
 -            + (extract32(desc->address_extension_45, 16, 12) << 20);
 +        addr = (uint64_t)desc->source_address5
 +            + (extract64(desc->address_extension_45, 16, 16) << 32);
          break;
      default:
          addr = 0;
 --
-.20.1
+.34.1

-[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
+[PULL 15/21] hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
-From: Patrick Venture <venture@google.com>
+From: Thomas Huth <thuth@redhat.com>
-Adds a line-item reference to the supported quanta-q71l-bmc aspeed
+"make check-qtest-aarch64" recently started failing on FreeBSD builds,
-entry.
+and valgrind on Linux also detected that there is something fishy with
 the new stm32l4x5-usart: The code forgot to set the correct class_size
 here, so the various class_init functions in this file wrote beyond
 the allocated buffer when setting the subc->type field.
-Signed-off-by: Patrick Venture <venture@google.com>
+Fixes: 4fb37aea7e ("hw/char: Implement STM32L4x5 USART skeleton")
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
+Signed-off-by: Thomas Huth <thuth@redhat.com>
-Message-id: 20210615192848.1065297-2-venture@google.com
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20240429075908.36302-1-thuth@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/aspeed.rst | 1 +
+ hw/char/stm32l4x5_usart.c | 1 +
 file changed, 1 insertion(+)
-diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
+diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/aspeed.rst
+--- a/hw/char/stm32l4x5_usart.c
-+++ b/docs/system/arm/aspeed.rst
++++ b/hw/char/stm32l4x5_usart.c
-@@ -XXX,XX +XXX,XX @@ etc.
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo stm32l4x5_usart_types[] = {
- AST2400 SoC based machines :
+         .parent         = TYPE_SYS_BUS_DEVICE,
+         .instance_size  = sizeof(Stm32l4x5UsartBaseState),
- - ``palmetto-bmc``         OpenPOWER Palmetto POWER8 BMC
+         .instance_init  = stm32l4x5_usart_base_init,
-+- ``quanta-q71l-bmc``      OpenBMC Quanta BMC
++        .class_size     = sizeof(Stm32l4x5UsartBaseClass),
+         .class_init     = stm32l4x5_usart_base_class_init,
- AST2500 SoC based machines :
+         .abstract       = true,
+     }, {
 --
-.20.1
+.34.1

-[PULL 05/24] target/arm: Check NaN mode before silencing NaN
+[PULL 16/21] hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
-From: Joe Komlodi <joe.komlodi@xilinx.com>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
+Use little endian for derivative OTP fuse key.
 FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
 assert due to fpst->default_nan_mode being set.
-To avoid this, we check to see what NaN mode we're running in before we call
+Cc: qemu-stable@nongnu.org
-floatxx_silence_nan().
+Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model")
+Suggested-by: Avi Fishman <Avi.Fishman@nuvoton.com>
-Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20240422125813.1403-1-philmd@linaro.org
 Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper-a64.c | 12 +++++++++---
+ hw/arm/npcm7xx.c | 3 ++-
- target/arm/vfp_helper.c | 24 ++++++++++++++++++------
+file changed, 2 insertions(+), 1 deletion(-)
 files changed, 27 insertions(+), 9 deletions(-)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
+diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
+--- a/hw/arm/npcm7xx.c
-+++ b/target/arm/helper-a64.c
++++ b/hw/arm/npcm7xx.c
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
+@@ -XXX,XX +XXX,XX @@
-         float16 nan = a;
+ #include "hw/qdev-clock.h"
-         if (float16_is_signaling_nan(a, fpst)) {
+ #include "hw/qdev-properties.h"
-             float_raise(float_flag_invalid, fpst);
+ #include "qapi/error.h"
--            nan = float16_silence_nan(a, fpst);
++#include "qemu/bswap.h"
-+            if (!fpst->default_nan_mode) {
+ #include "qemu/units.h"
-+                nan = float16_silence_nan(a, fpst);
+ #include "sysemu/sysemu.h"
-+            }
+ #include "target/arm/cpu-qom.h"
-         }
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
-         if (fpst->default_nan_mode) {
+      * The initial mask of disabled modules indicates the chip derivative (e.g.
-             nan = float16_default_nan(fpst);
+      * NPCM750 or NPCM730).
-@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
+      */
-         float32 nan = a;
+-    value = tswap32(nc->disabled_modules);
-         if (float32_is_signaling_nan(a, fpst)) {
++    value = cpu_to_le32(nc->disabled_modules);
-             float_raise(float_flag_invalid, fpst);
+     npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
--            nan = float32_silence_nan(a, fpst);
+                             sizeof(value));
-+            if (!fpst->default_nan_mode) {
+ }
 +                nan = float32_silence_nan(a, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan = float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
          float64 nan = a;
          if (float64_is_signaling_nan(a, fpst)) {
              float_raise(float_flag_invalid, fpst);
 -            nan = float64_silence_nan(a, fpst);
 +            if (!fpst->default_nan_mode) {
 +                nan = float64_silence_nan(a, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan = float64_default_nan(fpst);
 diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/vfp_helper.c
 +++ b/target/arm/vfp_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
          float16 nan = f16;
          if (float16_is_signaling_nan(f16, fpst)) {
              float_raise(float_flag_invalid, fpst);
 -            nan = float16_silence_nan(f16, fpst);
 +            if (!fpst->default_nan_mode) {
 +                nan = float16_silence_nan(f16, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan =  float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
          float32 nan = f32;
          if (float32_is_signaling_nan(f32, fpst)) {
              float_raise(float_flag_invalid, fpst);
 -            nan = float32_silence_nan(f32, fpst);
 +            if (!fpst->default_nan_mode) {
 +                nan = float32_silence_nan(f32, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan =  float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
          float64 nan = f64;
          if (float64_is_signaling_nan(f64, fpst)) {
              float_raise(float_flag_invalid, fpst);
 -            nan = float64_silence_nan(f64, fpst);
 +            if (!fpst->default_nan_mode) {
 +                nan = float64_silence_nan(f64, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan =  float64_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
          float16 nan = f16;
          if (float16_is_signaling_nan(f16, s)) {
              float_raise(float_flag_invalid, s);
 -            nan = float16_silence_nan(f16, s);
 +            if (!s->default_nan_mode) {
 +                nan = float16_silence_nan(f16, fpstp);
 +            }
          }
          if (s->default_nan_mode) {
              nan =  float16_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
          float32 nan = f32;
          if (float32_is_signaling_nan(f32, s)) {
              float_raise(float_flag_invalid, s);
 -            nan = float32_silence_nan(f32, s);
 +            if (!s->default_nan_mode) {
 +                nan = float32_silence_nan(f32, fpstp);
 +            }
          }
          if (s->default_nan_mode) {
              nan =  float32_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
          float64 nan = f64;
          if (float64_is_signaling_nan(f64, s)) {
              float_raise(float_flag_invalid, s);
 -            nan = float64_silence_nan(f64, s);
 +            if (!s->default_nan_mode) {
 +                nan = float64_silence_nan(f64, fpstp);
 +            }
          }
          if (s->default_nan_mode) {
              nan =  float64_default_nan(s);
 --
-.20.1
+.34.1

-[PULL 03/24] hw/arm: Add basic power management to raspi.
+[PULL 17/21] hw/display : Add device DM163
-From: Nolan Leake <nolan@sigbus.net>
+From: Inès Varhol <ines.varhol@telecom-paris.fr>
-This is just enough to make reboot and poweroff work. Works for
+This device implements the IM120417002 colors shield v1.1 for Arduino
-linux, u-boot, and the arm trusted firmware. Not tested, but should
+(which relies on the DM163 8x3-channel led driving logic) and features
-work for plan9, and bare-metal/hobby OSes, since they seem to generally
+a simple display of an 8x8 RGB matrix. The columns of the matrix are
-do what linux does for reset.
+driven by the DM163 and the rows are driven externally.
-The watchdog timer functionality is not yet implemented.
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
+Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
-Signed-off-by: Nolan Leake <nolan@sigbus.net>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20240424200929.240921-2-ines.varhol@telecom-paris.fr
-Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+[PMM: updated to new reset hold method prototype]
 Message-id: 20210625210209.1870217-1-nolan@sigbus.net
 [PMM: tweaked commit title; fixed region size to 0x200;
  moved header file to include/]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/bcm2835_peripherals.h |   3 +-
+ docs/system/arm/b-l475e-iot01a.rst |   3 +-
- include/hw/misc/bcm2835_powermgt.h   |  29 +++++
+ include/hw/display/dm163.h         |  59 +++++
- hw/arm/bcm2835_peripherals.c         |  13 ++-
+ hw/display/dm163.c                 | 349 +++++++++++++++++++++++++++++
- hw/misc/bcm2835_powermgt.c           | 160 +++++++++++++++++++++++++++
+ hw/display/Kconfig                 |   3 +
- hw/misc/meson.build                  |   1 +
+ hw/display/meson.build             |   1 +
-files changed, 204 insertions(+), 2 deletions(-)
+ hw/display/trace-events            |  14 ++
- create mode 100644 include/hw/misc/bcm2835_powermgt.h
+files changed, 428 insertions(+), 1 deletion(-)
- create mode 100644 hw/misc/bcm2835_powermgt.c
+ create mode 100644 include/hw/display/dm163.h
  create mode 100644 hw/display/dm163.c
-diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
+diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/bcm2835_peripherals.h
+--- a/docs/system/arm/b-l475e-iot01a.rst
-+++ b/include/hw/arm/bcm2835_peripherals.h
++++ b/docs/system/arm/b-l475e-iot01a.rst
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ USART, I2C, SPI, CAN and USB OTG, as well as a variety of sensors.
- #include "hw/misc/bcm2835_mphi.h"
+ Supported devices
- #include "hw/misc/bcm2835_thermal.h"
+ """""""""""""""""
- #include "hw/misc/bcm2835_cprman.h"
-+#include "hw/misc/bcm2835_powermgt.h"
+-Currently B-L475E-IOT01A machine's only supports the following devices:
- #include "hw/sd/sdhci.h"
++Currently B-L475E-IOT01A machines support the following devices:
- #include "hw/sd/bcm2835_sdhost.h"
- #include "hw/gpio/bcm2835_gpio.h"
+ - Cortex-M4F based STM32L4x5 SoC
-@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
+ - STM32L4x5 EXTI (Extended interrupts and events controller)
-     BCM2835MphiState mphi;
+@@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices:
-     UnimplementedDeviceState txp;
+ - STM32L4x5 RCC (Reset and clock control)
-     UnimplementedDeviceState armtmr;
+ - STM32L4x5 GPIOs (General-purpose I/Os)
--    UnimplementedDeviceState powermgt;
+ - STM32L4x5 USARTs, UARTs and LPUART (Serial ports)
-+    BCM2835PowerMgtState powermgt;
++- optional 8x8 led display (based on DM163 driver)
-     BCM2835CprmanState cprman;
-     PL011State uart0;
+ Missing devices
-     BCM2835AuxState aux;
+ """""""""""""""
-diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
+diff --git a/include/hw/display/dm163.h b/include/hw/display/dm163.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/misc/bcm2835_powermgt.h
++++ b/include/hw/display/dm163.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * BCM2835 Power Management emulation
++ * QEMU DM163 8x3-channel constant current led driver
 + * driving columns of associated 8x8 RGB matrix.
 + *
-+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
++ * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
-+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
++ * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
 + * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
 + *
-+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
++ * SPDX-License-Identifier: GPL-2.0-or-later
 + * See the COPYING file in the top-level directory.
 + */
 +
-+#ifndef BCM2835_POWERMGT_H
++#ifndef HW_DISPLAY_DM163_H
-+#define BCM2835_POWERMGT_H
++#define HW_DISPLAY_DM163_H
 +
 +#include "hw/sysbus.h"
 +#include "qom/object.h"
-+
++#include "hw/qdev-core.h"
-+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
++
-+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
++#define TYPE_DM163 "dm163"
-+
++OBJECT_DECLARE_SIMPLE_TYPE(DM163State, DM163);
-+struct BCM2835PowerMgtState {
++
-+    SysBusDevice busdev;
++#define RGB_MATRIX_NUM_ROWS 8
-+    MemoryRegion iomem;
++#define RGB_MATRIX_NUM_COLS 8
-+
++#define DM163_NUM_LEDS (RGB_MATRIX_NUM_COLS * 3)
-+    uint32_t rstc;
++/* The last row is filled with 0 (turned off row) */
-+    uint32_t rsts;
++#define COLOR_BUFFER_SIZE (RGB_MATRIX_NUM_ROWS + 1)
-+    uint32_t wdog;
++
-+};
++typedef struct DM163State {
-+
++    DeviceState parent_obj;
-+#endif
++
-diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
++    /* DM163 driver */
-index XXXXXXX..XXXXXXX 100644
++    uint64_t bank0_shift_register[3];
---- a/hw/arm/bcm2835_peripherals.c
++    uint64_t bank1_shift_register[3];
-+++ b/hw/arm/bcm2835_peripherals.c
++    uint16_t latched_outputs[DM163_NUM_LEDS];
-@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
++    uint16_t outputs[DM163_NUM_LEDS];
++    qemu_irq sout;
-     object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
++
-                                    OBJECT(&s->gpu_bus_mr));
++    uint8_t sin;
-+
++    uint8_t dck;
-+    /* Power Management */
++    uint8_t rst_b;
-+    object_initialize_child(obj, "powermgt", &s->powermgt,
++    uint8_t lat_b;
-+                            TYPE_BCM2835_POWERMGT);
++    uint8_t selbk;
- }
++    uint8_t en_b;
++
- static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
++    /* IM120417002 colors shield */
-@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
++    uint8_t activated_rows;
-         qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
++
-                                INTERRUPT_USB));
++    /* 8x8 RGB matrix */
++    QemuConsole *console;
-+    /* Power Management */
++    uint8_t redraw;
-+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
++    /* Rows currently being displayed on the matrix. */
-+        return;
++    /* The last row is filled with 0 (turned off row) */
-+    }
++    uint32_t buffer[COLOR_BUFFER_SIZE][RGB_MATRIX_NUM_COLS];
-+
++    uint8_t last_buffer_idx;
-+    memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
++    uint8_t buffer_idx_of_row[RGB_MATRIX_NUM_ROWS];
-+                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
++    /* Used to simulate retinal persistence of rows */
-+
++    uint8_t row_persistence_delay[RGB_MATRIX_NUM_ROWS];
-     create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
++} DM163State;
-     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
++
--    create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
++#endif /* HW_DISPLAY_DM163_H */
-     create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
+diff --git a/hw/display/dm163.c b/hw/display/dm163.c
      create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
      create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
 diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/misc/bcm2835_powermgt.c
++++ b/hw/display/dm163.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * BCM2835 Power Management emulation
++ * QEMU DM163 8x3-channel constant current led driver
 + * driving columns of associated 8x8 RGB matrix.
 + *
-+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
++ * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
-+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
++ * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
 + * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
 + *
-+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
++ * SPDX-License-Identifier: GPL-2.0-or-later
 + * See the COPYING file in the top-level directory.
 + */
 +
++/*
++ * The reference used for the DM163 is the following :
++ * http://www.siti.com.tw/product/spec/LED/DM163.pdf
++ */
++
 +#include "qemu/osdep.h"
-+#include "qemu/log.h"
++#include "qapi/error.h"
 +#include "qemu/module.h"
 +#include "hw/misc/bcm2835_powermgt.h"
 +#include "migration/vmstate.h"
-+#include "sysemu/runstate.h"
++#include "hw/irq.h"
-+
++#include "hw/qdev-properties.h"
-+#define PASSWORD 0x5a000000
++#include "hw/display/dm163.h"
-+#define PASSWORD_MASK 0xff000000
++#include "ui/console.h"
-+
++#include "trace.h"
-+#define R_RSTC 0x1c
++
-+#define V_RSTC_RESET 0x20
++#define LED_SQUARE_SIZE 100
-+#define R_RSTS 0x20
++/* Number of frames a row stays visible after being turned off. */
-+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
++#define ROW_PERSISTENCE 3
-+#define R_WDOG 0x24
++#define TURNED_OFF_ROW (COLOR_BUFFER_SIZE - 1)
 +
-+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
++static const VMStateDescription vmstate_dm163 = {
-+                                      unsigned size)
++    .name = TYPE_DM163,
 +{
 +    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
 +    uint32_t res = 0;
 +
 +    switch (offset) {
 +    case R_RSTC:
 +        res = s->rstc;
 +        break;
 +    case R_RSTS:
 +        res = s->rsts;
 +        break;
 +    case R_WDOG:
 +        res = s->wdog;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
 +                      "\n", offset);
 +        res = 0;
 +        break;
 +    }
 +
 +    return res;
 +}
 +
 +static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
 +                                   uint64_t value, unsigned size)
 +{
 +    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
 +
 +    if ((value & PASSWORD_MASK) != PASSWORD) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "bcm2835_powermgt_write: Bad password 0x%"PRIx64
 +                      " at offset 0x%08"HWADDR_PRIx"\n",
 +                      value, offset);
 +        return;
 +    }
 +
 +    value = value & ~PASSWORD_MASK;
 +
 +    switch (offset) {
 +    case R_RSTC:
 +        s->rstc = value;
 +        if (value & V_RSTC_RESET) {
 +            if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
 +                qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 +            } else {
 +                qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 +            }
 +        }
 +        break;
 +    case R_RSTS:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "bcm2835_powermgt_write: RSTS\n");
 +        s->rsts = value;
 +        break;
 +    case R_WDOG:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "bcm2835_powermgt_write: WDOG\n");
 +        s->wdog = value;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
 +                      "\n", offset);
 +        break;
 +    }
 +}
 +
 +static const MemoryRegionOps bcm2835_powermgt_ops = {
 +    .read = bcm2835_powermgt_read,
 +    .write = bcm2835_powermgt_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .impl.min_access_size = 4,
 +    .impl.max_access_size = 4,
 +};
 +
 +static const VMStateDescription vmstate_bcm2835_powermgt = {
 +    .name = TYPE_BCM2835_POWERMGT,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
-+    .fields = (VMStateField[]) {
++    .fields = (const VMStateField[]) {
-+        VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
++        VMSTATE_UINT64_ARRAY(bank0_shift_register, DM163State, 3),
-+        VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
++        VMSTATE_UINT64_ARRAY(bank1_shift_register, DM163State, 3),
-+        VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
++        VMSTATE_UINT16_ARRAY(latched_outputs, DM163State, DM163_NUM_LEDS),
 +        VMSTATE_UINT16_ARRAY(outputs, DM163State, DM163_NUM_LEDS),
 +        VMSTATE_UINT8(dck, DM163State),
 +        VMSTATE_UINT8(en_b, DM163State),
 +        VMSTATE_UINT8(lat_b, DM163State),
 +        VMSTATE_UINT8(rst_b, DM163State),
 +        VMSTATE_UINT8(selbk, DM163State),
 +        VMSTATE_UINT8(sin, DM163State),
 +        VMSTATE_UINT8(activated_rows, DM163State),
 +        VMSTATE_UINT32_2DARRAY(buffer, DM163State, COLOR_BUFFER_SIZE,
 +                               RGB_MATRIX_NUM_COLS),
 +        VMSTATE_UINT8(last_buffer_idx, DM163State),
 +        VMSTATE_UINT8_ARRAY(buffer_idx_of_row, DM163State, RGB_MATRIX_NUM_ROWS),
 +        VMSTATE_UINT8_ARRAY(row_persistence_delay, DM163State,
 +                            RGB_MATRIX_NUM_ROWS),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
-+static void bcm2835_powermgt_init(Object *obj)
++static void dm163_reset_hold(Object *obj, ResetType type)
 +{
-+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
++    DM163State *s = DM163(obj);
 +
-+    memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
++    s->sin = 0;
-+                          TYPE_BCM2835_POWERMGT, 0x200);
++    s->dck = 0;
-+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
++    s->rst_b = 0;
-+}
++    /* Ensuring the first falling edge of lat_b isn't missed */
-+
++    s->lat_b = 1;
-+static void bcm2835_powermgt_reset(DeviceState *dev)
++    s->selbk = 0;
-+{
++    s->en_b = 0;
-+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
++    /* Reset stops the PWM, not the shift and latched registers. */
-+
++    memset(s->outputs, 0, sizeof(s->outputs));
-+    /* https://elinux.org/BCM2835_registers#PM */
++
-+    s->rstc = 0x00000102;
++    s->activated_rows = 0;
-+    s->rsts = 0x00001000;
++    s->redraw = 0;
-+    s->wdog = 0x00000000;
++    trace_dm163_redraw(s->redraw);
-+}
++    for (unsigned i = 0; i < COLOR_BUFFER_SIZE; i++) {
-+
++        memset(s->buffer[i], 0, sizeof(s->buffer[0]));
-+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
++    }
 +    s->last_buffer_idx = 0;
 +    memset(s->buffer_idx_of_row, TURNED_OFF_ROW, sizeof(s->buffer_idx_of_row));
 +    memset(s->row_persistence_delay, 0, sizeof(s->row_persistence_delay));
 +}
 +
 +static void dm163_dck_gpio_handler(void *opaque, int line, int new_state)
 +{
 +    DM163State *s = opaque;
 +
 +    if (new_state && !s->dck) {
 +        /*
 +         * On raising dck, sample selbk to get the bank to use, and
 +         * sample sin for the bit to enter into the bank shift buffer.
 +         */
 +        uint64_t *sb =
 +            s->selbk ? s->bank1_shift_register : s->bank0_shift_register;
 +        /* Output the outgoing bit on sout */
 +        const bool sout = (s->selbk ? sb[2] & MAKE_64BIT_MASK(63, 1) :
 +                           sb[2] & MAKE_64BIT_MASK(15, 1)) != 0;
 +        qemu_set_irq(s->sout, sout);
 +        /* Enter sin into the shift buffer */
 +        sb[2] = (sb[2] << 1) | ((sb[1] >> 63) & 1);
 +        sb[1] = (sb[1] << 1) | ((sb[0] >> 63) & 1);
 +        sb[0] = (sb[0] << 1) | s->sin;
 +    }
 +
 +    s->dck = new_state;
 +    trace_dm163_dck(new_state);
 +}
 +
 +static void dm163_propagate_outputs(DM163State *s)
 +{
 +    s->last_buffer_idx = (s->last_buffer_idx + 1) % RGB_MATRIX_NUM_ROWS;
 +    /* Values are output when reset is high and enable is low. */
 +    if (s->rst_b && !s->en_b) {
 +        memcpy(s->outputs, s->latched_outputs, sizeof(s->outputs));
 +    } else {
 +        memset(s->outputs, 0, sizeof(s->outputs));
 +    }
 +    for (unsigned x = 0; x < RGB_MATRIX_NUM_COLS; x++) {
 +        /* Grouping the 3 RGB channels in a pixel value */
 +        const uint16_t b = extract16(s->outputs[3 * x + 0], 6, 8);
 +        const uint16_t g = extract16(s->outputs[3 * x + 1], 6, 8);
 +        const uint16_t r = extract16(s->outputs[3 * x + 2], 6, 8);
 +        uint32_t rgba = 0;
 +
 +        trace_dm163_channels(3 * x + 2, r);
 +        trace_dm163_channels(3 * x + 1, g);
 +        trace_dm163_channels(3 * x + 0, b);
 +
 +        rgba = deposit32(rgba,  0, 8, r);
 +        rgba = deposit32(rgba,  8, 8, g);
 +        rgba = deposit32(rgba, 16, 8, b);
 +
 +        /* Led values are sent from the last one to the first one */
 +        s->buffer[s->last_buffer_idx][RGB_MATRIX_NUM_COLS - x - 1] = rgba;
 +    }
 +    for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) {
 +        if (s->activated_rows & (1 << row)) {
 +            s->buffer_idx_of_row[row] = s->last_buffer_idx;
 +            s->redraw |= (1 << row);
 +            trace_dm163_redraw(s->redraw);
 +        }
 +    }
 +}
 +
 +static void dm163_en_b_gpio_handler(void *opaque, int line, int new_state)
 +{
 +    DM163State *s = opaque;
 +
 +    s->en_b = new_state;
 +    dm163_propagate_outputs(s);
 +    trace_dm163_en_b(new_state);
 +}
 +
 +static uint8_t dm163_bank0(const DM163State *s, uint8_t led)
 +{
 +    /*
 +     * Bank 0 uses 6 bits per led, so a value may be stored accross
 +     * two uint64_t entries.
 +     */
 +    const uint8_t low_bit = 6 * led;
 +    const uint8_t low_word = low_bit / 64;
 +    const uint8_t high_word = (low_bit + 5) / 64;
 +    const uint8_t low_shift = low_bit % 64;
 +
 +    if (low_word == high_word) {
 +        /* Simple case: the value belongs to one entry. */
 +        return extract64(s->bank0_shift_register[low_word], low_shift, 6);
 +    }
 +
 +    const uint8_t nb_bits_in_low_word = 64 - low_shift;
 +    const uint8_t nb_bits_in_high_word = 6 - nb_bits_in_low_word;
 +
 +    const uint64_t bits_in_low_word = \
 +        extract64(s->bank0_shift_register[low_word], low_shift,
 +                  nb_bits_in_low_word);
 +    const uint64_t bits_in_high_word = \
 +        extract64(s->bank0_shift_register[high_word], 0,
 +                  nb_bits_in_high_word);
 +    uint8_t val = 0;
 +
 +    val = deposit32(val, 0, nb_bits_in_low_word, bits_in_low_word);
 +    val = deposit32(val, nb_bits_in_low_word, nb_bits_in_high_word,
 +                    bits_in_high_word);
 +
 +    return val;
 +}
 +
 +static uint8_t dm163_bank1(const DM163State *s, uint8_t led)
 +{
 +    const uint64_t entry = s->bank1_shift_register[led / RGB_MATRIX_NUM_COLS];
 +    return extract64(entry, 8 * (led % RGB_MATRIX_NUM_COLS), 8);
 +}
 +
 +static void dm163_lat_b_gpio_handler(void *opaque, int line, int new_state)
 +{
 +    DM163State *s = opaque;
 +
 +    if (s->lat_b && !new_state) {
 +        for (int led = 0; led < DM163_NUM_LEDS; led++) {
 +            s->latched_outputs[led] = dm163_bank0(s, led) * dm163_bank1(s, led);
 +        }
 +        dm163_propagate_outputs(s);
 +    }
 +
 +    s->lat_b = new_state;
 +    trace_dm163_lat_b(new_state);
 +}
 +
 +static void dm163_rst_b_gpio_handler(void *opaque, int line, int new_state)
 +{
 +    DM163State *s = opaque;
 +
 +    s->rst_b = new_state;
 +    dm163_propagate_outputs(s);
 +    trace_dm163_rst_b(new_state);
 +}
 +
 +static void dm163_selbk_gpio_handler(void *opaque, int line, int new_state)
 +{
 +    DM163State *s = opaque;
 +
 +    s->selbk = new_state;
 +    trace_dm163_selbk(new_state);
 +}
 +
 +static void dm163_sin_gpio_handler(void *opaque, int line, int new_state)
 +{
 +    DM163State *s = opaque;
 +
 +    s->sin = new_state;
 +    trace_dm163_sin(new_state);
 +}
 +
 +static void dm163_rows_gpio_handler(void *opaque, int line, int new_state)
 +{
 +    DM163State *s = opaque;
 +
 +    if (new_state) {
 +        s->activated_rows |= (1 << line);
 +        s->buffer_idx_of_row[line] = s->last_buffer_idx;
 +        s->redraw |= (1 << line);
 +        trace_dm163_redraw(s->redraw);
 +    } else {
 +        s->activated_rows &= ~(1 << line);
 +        s->row_persistence_delay[line] = ROW_PERSISTENCE;
 +    }
 +    trace_dm163_activated_rows(s->activated_rows);
 +}
 +
 +static void dm163_invalidate_display(void *opaque)
 +{
 +    DM163State *s = (DM163State *)opaque;
 +    s->redraw = 0xFF;
 +    trace_dm163_redraw(s->redraw);
 +}
 +
 +static void update_row_persistence_delay(DM163State *s, unsigned row)
 +{
 +    if (s->row_persistence_delay[row]) {
 +        s->row_persistence_delay[row]--;
 +    } else {
 +        /*
 +         * If the ROW_PERSISTENCE delay is up,
 +         * the row is turned off.
 +         */
 +        s->buffer_idx_of_row[row] = TURNED_OFF_ROW;
 +        s->redraw |= (1 << row);
 +        trace_dm163_redraw(s->redraw);
 +    }
 +}
 +
 +static uint32_t *update_display_of_row(DM163State *s, uint32_t *dest,
 +                                       unsigned row)
 +{
 +    for (unsigned _ = 0; _ < LED_SQUARE_SIZE; _++) {
 +        for (int x = 0; x < RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE; x++) {
 +            /* UI layer guarantees that there's 32 bits per pixel (Mar 2024) */
 +            *dest++ = s->buffer[s->buffer_idx_of_row[row]][x / LED_SQUARE_SIZE];
 +        }
 +    }
 +
 +    dpy_gfx_update(s->console, 0, LED_SQUARE_SIZE * row,
 +                    RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE, LED_SQUARE_SIZE);
 +    s->redraw &= ~(1 << row);
 +    trace_dm163_redraw(s->redraw);
 +
 +    return dest;
 +}
 +
 +static void dm163_update_display(void *opaque)
 +{
 +    DM163State *s = (DM163State *)opaque;
 +    DisplaySurface *surface = qemu_console_surface(s->console);
 +    uint32_t *dest;
 +
 +    dest = surface_data(surface);
 +    for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) {
 +        update_row_persistence_delay(s, row);
 +        if (!extract8(s->redraw, row, 1)) {
 +            dest += LED_SQUARE_SIZE * LED_SQUARE_SIZE * RGB_MATRIX_NUM_COLS;
 +            continue;
 +        }
 +        dest = update_display_of_row(s, dest, row);
 +    }
 +}
 +
 +static const GraphicHwOps dm163_ops = {
 +    .invalidate  = dm163_invalidate_display,
 +    .gfx_update  = dm163_update_display,
 +};
 +
 +static void dm163_realize(DeviceState *dev, Error **errp)
 +{
 +    DM163State *s = DM163(dev);
 +
 +    qdev_init_gpio_in(dev, dm163_rows_gpio_handler, RGB_MATRIX_NUM_ROWS);
 +    qdev_init_gpio_in(dev, dm163_sin_gpio_handler, 1);
 +    qdev_init_gpio_in(dev, dm163_dck_gpio_handler, 1);
 +    qdev_init_gpio_in(dev, dm163_rst_b_gpio_handler, 1);
 +    qdev_init_gpio_in(dev, dm163_lat_b_gpio_handler, 1);
 +    qdev_init_gpio_in(dev, dm163_selbk_gpio_handler, 1);
 +    qdev_init_gpio_in(dev, dm163_en_b_gpio_handler, 1);
 +    qdev_init_gpio_out_named(dev, &s->sout, "sout", 1);
 +
 +    s->console = graphic_console_init(dev, 0, &dm163_ops, s);
 +    qemu_console_resize(s->console, RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE,
 +                        RGB_MATRIX_NUM_ROWS * LED_SQUARE_SIZE);
 +}
 +
 +static void dm163_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
-+
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
-+    dc->reset = bcm2835_powermgt_reset;
++
-+    dc->vmsd = &vmstate_bcm2835_powermgt;
++    dc->desc = "DM163";
-+}
++    dc->vmsd = &vmstate_dm163;
-+
++    dc->realize = dm163_realize;
-+static TypeInfo bcm2835_powermgt_info = {
++    rc->phases.hold = dm163_reset_hold;
-+    .name          = TYPE_BCM2835_POWERMGT,
++    set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
-+    .parent        = TYPE_SYS_BUS_DEVICE,
++}
-+    .instance_size = sizeof(BCM2835PowerMgtState),
++
-+    .class_init    = bcm2835_powermgt_class_init,
++static const TypeInfo dm163_types[] = {
-+    .instance_init = bcm2835_powermgt_init,
++    {
 +        .name = TYPE_DM163,
 +        .parent = TYPE_DEVICE,
 +        .instance_size = sizeof(DM163State),
 +        .class_init = dm163_class_init
 +    }
 +};
 +
-+static void bcm2835_powermgt_register_types(void)
++DEFINE_TYPES(dm163_types)
-+{
+diff --git a/hw/display/Kconfig b/hw/display/Kconfig
 +    type_register_static(&bcm2835_powermgt_info);
 +}
 +
 +type_init(bcm2835_powermgt_register_types)
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/meson.build
+--- a/hw/display/Kconfig
-+++ b/hw/misc/meson.build
++++ b/hw/display/Kconfig
-@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
+@@ -XXX,XX +XXX,XX @@ config XLNX_DISPLAYPORT
-   'bcm2835_rng.c',
+     bool
-   'bcm2835_thermal.c',
+     # defaults to "N", enabled by specific boards
-   'bcm2835_cprman.c',
+     depends on PIXMAN
-+  'bcm2835_powermgt.c',
++
- ))
++config DM163
- softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
++    bool
- softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
+diff --git a/hw/display/meson.build b/hw/display/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/display/meson.build
 +++ b/hw/display/meson.build
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-fb.c'))
  system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c'))
  system_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-dmabuf.c'))
 +system_ss.add(when: 'CONFIG_DM163', if_true: files('dm163.c'))
  if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or
      config_all_devices.has_key('CONFIG_VGA_PCI') or
 diff --git a/hw/display/trace-events b/hw/display/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/display/trace-events
 +++ b/hw/display/trace-events
@@ -XXX,XX +XXX,XX @@ macfb_ctrl_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%"PRI
  macfb_sense_read(uint32_t value) "video sense: 0x%"PRIx32
  macfb_sense_write(uint32_t value) "video sense: 0x%"PRIx32
  macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) "setting mode to width %"PRId32 " height %"PRId32 " size %d"
 +
 +# dm163.c
 +dm163_redraw(uint8_t redraw) "0x%02x"
 +dm163_dck(unsigned new_state) "dck : %u"
 +dm163_en_b(unsigned new_state) "en_b : %u"
 +dm163_rst_b(unsigned new_state) "rst_b : %u"
 +dm163_lat_b(unsigned new_state) "lat_b : %u"
 +dm163_sin(unsigned new_state) "sin : %u"
 +dm163_selbk(unsigned new_state) "selbk : %u"
 +dm163_activated_rows(int new_state) "Activated rows : 0x%" PRIx32 ""
 +dm163_bits_ppi(unsigned dest_width) "dest_width : %u"
 +dm163_leds(int led, uint32_t value) "led %d: 0x%x"
 +dm163_channels(int channel, uint8_t value) "channel %d: 0x%x"
 +dm163_refresh_rate(uint32_t rr) "refresh rate %d"
 --
-.20.1
+.34.1

-[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
+[PULL 18/21] hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC
-The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
+From: Inès Varhol <ines.varhol@telecom-paris.fr>
 insns had some bugs:
  * the 32x32 multiply of elements was being done as 32x32->32,
    not 32x32->64
  * we were incorrectly maintaining the accumulator in its full
 -bit form across all 4 beats of the insn; in the pseudocode
    it is squashed back into the 64 bits of the RdaHi:RdaLo
    registers after each beat
-In particular, fixing the second of these allows us to recast
+Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC
-the implementation to avoid 128-bit arithmetic entirely.
+to the optional DM163 display from the board code (GPIOs outputs need
 to be connected to both SYSCFG inputs and DM163 inputs).
-Since the element size here is always 4, we can also drop the
+STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly.
 parameterization of ESIZE to make the code a little more readable.
-Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
 Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20240424200929.240921-3-ines.varhol@telecom-paris.fr
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
 ---
- target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
+ hw/arm/stm32l4x5_soc.c              |  6 ++++--
-file changed, 21 insertions(+), 17 deletions(-)
+ tests/qtest/stm32l4x5_gpio-test.c   | 13 ++++++++-----
  tests/qtest/stm32l4x5_syscfg-test.c | 17 ++++++++++-------
 files changed, 22 insertions(+), 14 deletions(-)
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
+diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve_helper.c
+--- a/hw/arm/stm32l4x5_soc.c
-+++ b/target/arm/mve_helper.c
++++ b/hw/arm/stm32l4x5_soc.c
 @@ -XXX,XX +XXX,XX @@
-  */
- #include "qemu/osdep.h"
--#include "qemu/int128.h"
- #include "cpu.h"
- #include "internals.h"
- #include "vec_internal.h"
-@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
- DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
  /*
-- * Rounding multiply add long dual accumulate high: we must keep
+  * STM32L4x5 SoC family
-- * a 72-bit internal accumulator value and return the top 64 bits.
+  *
-+ * Rounding multiply add long dual accumulate high. In the pseudocode
+- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
-+ * this is implemented with a 72-bit internal accumulator value of which
+- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
-+ * the top 64 bits are returned. We optimize this to avoid having to
++ * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
-+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
++ * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
-+ * is squashed back into 64-bits after each beat.
+  *
-  */
+  * SPDX-License-Identifier: GPL-2.0-or-later
--#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128)         \
+  *
-+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB)                            \
+@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
-     uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn,         \
+         }
                                      void *vm, uint64_t a)               \
      {                                                                   \
          uint16_t mask = mve_element_mask(env);                          \
          unsigned e;                                                     \
          TYPE *n = vn, *m = vm;                                          \
 -        Int128 acc = int128_lshift(TO128(a), 8);                        \
 -        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {              \
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {                      \
              if (mask & 1) {                                             \
 +                LTYPE mul;                                              \
                  if (e & 1) {                                            \
 -                    acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
 -                                            m[H##ESIZE(e)]));           \
 +                    mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)];        \
 +                    if (SUB) {                                          \
 +                        mul = -mul;                                     \
 +                    }                                                   \
                  } else {                                                \
 -                    acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
 -                                             m[H##ESIZE(e)]));          \
 +                    mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)];        \
                  }                                                       \
 -                acc = int128_add(acc, int128_make64(1 << 7));           \
 +                mul = (mul >> 8) + ((mul >> 7) & 1);                    \
 +                a += mul;                                               \
              }                                                           \
          }                                                               \
          mve_advance_vpt(env);                                           \
 -        return int128_getlo(int128_rshift(acc, 8));                     \
 +        return a;                                                       \
      }
--DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
++    qdev_pass_gpios(DEVICE(&s->syscfg), dev_soc, NULL);
--DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
++
-+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
+     /* EXTI device */
-+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
+     busdev = SYS_BUS_DEVICE(&s->exti);
+     if (!sysbus_realize(busdev, errp)) {
--DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
+diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c
-+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/qtest/stm32l4x5_gpio-test.c
--DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
++++ b/tests/qtest/stm32l4x5_gpio-test.c
--DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
+@@ -XXX,XX +XXX,XX @@
-+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
+ #define OTYPER_PUSH_PULL 0
-+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
+ #define OTYPER_OPEN_DRAIN 1
- /* Vector add across vector */
++/* SoC forwards GPIOs to SysCfg */
- #define DO_VADDV(OP, ESIZE, TYPE)                               \
++#define SYSCFG "/machine/soc"
 +
  const uint32_t moder_reset[NUM_GPIOS] = {
 xABFFFFFF,
 xFFFFFEBF,
@@ -XXX,XX +XXX,XX @@ static void test_gpio_output_mode(const void *data)
      uint32_t gpio = test_gpio_addr(data);
      unsigned int gpio_id = get_gpio_id(gpio);
 -    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
 +    qtest_irq_intercept_in(global_qtest, SYSCFG);
      /* Set a bit in ODR and check nothing happens */
      gpio_set_bit(gpio, ODR, pin, 1);
@@ -XXX,XX +XXX,XX @@ static void test_gpio_input_mode(const void *data)
      uint32_t gpio = test_gpio_addr(data);
      unsigned int gpio_id = get_gpio_id(gpio);
 -    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
 +    qtest_irq_intercept_in(global_qtest, SYSCFG);
      /* Configure a line as input, raise it, and check that the pin is high */
      gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
@@ -XXX,XX +XXX,XX @@ static void test_pull_up_pull_down(const void *data)
      uint32_t gpio = test_gpio_addr(data);
      unsigned int gpio_id = get_gpio_id(gpio);
 -    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
 +    qtest_irq_intercept_in(global_qtest, SYSCFG);
      /* Configure a line as input with pull-up, check the line is set high */
      gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
@@ -XXX,XX +XXX,XX @@ static void test_push_pull(const void *data)
      uint32_t gpio = test_gpio_addr(data);
      uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
 -    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
 +    qtest_irq_intercept_in(global_qtest, SYSCFG);
      /* Setting a line high externally, configuring it in push-pull output */
      /* And checking the pin was disconnected */
@@ -XXX,XX +XXX,XX @@ static void test_open_drain(const void *data)
      uint32_t gpio = test_gpio_addr(data);
      uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
 -    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
 +    qtest_irq_intercept_in(global_qtest, SYSCFG);
      /* Setting a line high externally, configuring it in open-drain output */
      /* And checking the pin was disconnected */
 diff --git a/tests/qtest/stm32l4x5_syscfg-test.c b/tests/qtest/stm32l4x5_syscfg-test.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/stm32l4x5_syscfg-test.c
 +++ b/tests/qtest/stm32l4x5_syscfg-test.c
@@ -XXX,XX +XXX,XX @@
  /*
   * QTest testcase for STM32L4x5_SYSCFG
   *
 - * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
 - * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
 + * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
 + * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
   *
   * This work is licensed under the terms of the GNU GPL, version 2 or later.
   * See the COPYING file in the top-level directory.
@@ -XXX,XX +XXX,XX @@
  #define SYSCFG_SWPR2 0x28
  #define INVALID_ADDR 0x2C
 +/* SoC forwards GPIOs to SysCfg */
 +#define SYSCFG "/machine/soc"
 +#define EXTI "/machine/soc/exti"
 +
  static void syscfg_writel(unsigned int offset, uint32_t value)
  {
      writel(SYSCFG_BASE_ADDR + offset, value);
@@ -XXX,XX +XXX,XX @@ static uint32_t syscfg_readl(unsigned int offset)
  static void syscfg_set_irq(int num, int level)
  {
 -   qtest_set_irq_in(global_qtest, "/machine/soc/syscfg",
 -                    NULL, num, level);
 +   qtest_set_irq_in(global_qtest, SYSCFG, NULL, num, level);
  }
  static void system_reset(void)
@@ -XXX,XX +XXX,XX @@ static void test_interrupt(void)
       * Test that GPIO rising lines result in an irq
       * with the right configuration
       */
 -    qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
 +    qtest_irq_intercept_in(global_qtest, EXTI);
      /* GPIOA is the default source for EXTI lines 0 to 15 */
@@ -XXX,XX +XXX,XX @@ static void test_irq_pin_multiplexer(void)
       * Test that syscfg irq sets the right exti irq
       */
 -    qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
 +    qtest_irq_intercept_in(global_qtest, EXTI);
      syscfg_set_irq(0, 1);
@@ -XXX,XX +XXX,XX @@ static void test_irq_gpio_multiplexer(void)
       * Test that an irq is generated only by the right GPIO
       */
 -    qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
 +    qtest_irq_intercept_in(global_qtest, EXTI);
      /* GPIOA is the default source for EXTI lines 0 to 15 */
 --
-.20.1
+.34.1

-[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
+[PULL 19/21] hw/arm : Create Bl475eMachineState
-In do_ldst(), the calculation of the offset needs to be based on the
+From: Inès Varhol <ines.varhol@telecom-paris.fr>
 size of the memory access, not the size of the elements in the
 vector.  This meant we were getting it wrong for the widening and
 narrowing variants of the various VLDR and VSTR insns.
+Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
+Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20240424200929.240921-4-ines.varhol@telecom-paris.fr
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
 ---
- target/arm/translate-mve.c | 17 +++++++++--------
+ hw/arm/b-l475e-iot01a.c | 46 ++++++++++++++++++++++++++++-------------
-file changed, 9 insertions(+), 8 deletions(-)
+file changed, 32 insertions(+), 14 deletions(-)
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
+diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
+--- a/hw/arm/b-l475e-iot01a.c
-+++ b/target/arm/translate-mve.c
++++ b/hw/arm/b-l475e-iot01a.c
-@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@
-     }
+  * B-L475E-IOT01A Discovery Kit machine
   * (B-L475E-IOT01A IoT Node)
   *
 - * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
 - * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
 + * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
 + * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
   *
   * SPDX-License-Identifier: GPL-2.0-or-later
   *
@@ -XXX,XX +XXX,XX @@
  /* B-L475E-IOT01A implementation is derived from netduinoplus2 */
 -static void b_l475e_iot01a_init(MachineState *machine)
 +#define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a")
 +OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A)
 +
 +typedef struct Bl475eMachineState {
 +    MachineState parent_obj;
 +
 +    Stm32l4x5SocState soc;
 +} Bl475eMachineState;
 +
 +static void bl475e_init(MachineState *machine)
  {
 +    Bl475eMachineState *s = B_L475E_IOT01A(machine);
      const Stm32l4x5SocClass *sc;
 -    DeviceState *dev;
 -    dev = qdev_new(TYPE_STM32L4X5XG_SOC);
 -    object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
 -    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 +    object_initialize_child(OBJECT(machine), "soc", &s->soc,
 +                            TYPE_STM32L4X5XG_SOC);
 +    sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
 -    sc = STM32L4X5_SOC_GET_CLASS(dev);
 -    armv7m_load_kernel(ARM_CPU(first_cpu),
 -                       machine->kernel_filename,
 -                       0, sc->flash_size);
 +    sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
 +    armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
 +                       sc->flash_size);
  }
--static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
+-static void b_l475e_iot01a_machine_init(MachineClass *mc)
-+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
++static void bl475e_machine_init(ObjectClass *oc, void *data)
 +                    unsigned msize)
  {
-     TCGv_i32 addr;
++    MachineClass *mc = MACHINE_CLASS(oc);
-     uint32_t offset;
+     static const char *machine_valid_cpu_types[] = {
-@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
+         ARM_CPU_TYPE_NAME("cortex-m4"),
-         return true;
+         NULL
      }
 -    offset = a->imm << a->size;
 +    offset = a->imm << msize;
      if (!a->a) {
          offset = -offset;
      }
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
          { gen_helper_mve_vstrw, gen_helper_mve_vldrw },
          { NULL, NULL }
      };
--    return do_ldst(s, a, ldstfns[a->size][a->l]);
+     mc->desc = "B-L475E-IOT01A Discovery Kit (Cortex-M4)";
-+    return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
+-    mc->init = b_l475e_iot01a_init;
 +    mc->init = bl475e_init;
      mc->valid_cpu_types = machine_valid_cpu_types;
      /* SRAM pre-allocated as part of the SoC instantiation */
      mc->default_ram_size = 0;
  }
--#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST)                  \
+-DEFINE_MACHINE("b-l475e-iot01a", b_l475e_iot01a_machine_init)
-+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE)           \
++static const TypeInfo bl475e_machine_type[] = {
-     static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
++    {
-     {                                                           \
++        .name           = TYPE_B_L475E_IOT01A,
-         static MVEGenLdStFn * const ldstfns[2][2] = {           \
++        .parent         = TYPE_MACHINE,
-             { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
++        .instance_size  = sizeof(Bl475eMachineState),
-             { NULL, gen_helper_mve_##ULD },                     \
++        .class_init     = bl475e_machine_init,
-         };                                                      \
++    }
--        return do_ldst(s, a, ldstfns[a->u][a->l]);              \
++};
-+        return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE);       \
++
-     }
++DEFINE_TYPES(bl475e_machine_type)
 -DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
 -DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
 -DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
 +DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
 +DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
 +DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
  static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
  {
 --
-.20.1
+.34.1

-[PULL 15/24] target/arm: Implement MVE VSHLL
+[PULL 20/21] hw/arm : Connect DM163 to B-L475E-IOT01A
-Implement the MVE VHLL (vector shift left long) insn.  This has two
+From: Inès Varhol <ines.varhol@telecom-paris.fr>
 encodings: the T1 encoding is the usual shift-by-immediate format,
 and the T2 encoding is a special case where the shift count is always
 equal to the element size.
+Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
+Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20240424200929.240921-5-ines.varhol@telecom-paris.fr
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    |  9 +++++++
+ hw/arm/b-l475e-iot01a.c | 59 +++++++++++++++++++++++++++++++++++++++--
- target/arm/mve.decode      | 53 +++++++++++++++++++++++++++++++++++---
+ hw/arm/Kconfig          |  1 +
- target/arm/mve_helper.c    | 32 +++++++++++++++++++++++
+files changed, 58 insertions(+), 2 deletions(-)
  target/arm/translate-mve.c | 15 +++++++++++
 files changed, 105 insertions(+), 4 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/hw/arm/b-l475e-iot01a.c
-+++ b/target/arm/helper-mve.h
++++ b/hw/arm/b-l475e-iot01a.c
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
 @@ -XXX,XX +XXX,XX @@
- @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+ #include "hw/boards.h"
- @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
+ #include "hw/qdev-properties.h"
+ #include "qemu/error-report.h"
-+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
+-#include "hw/arm/stm32l4x5_soc.h"
-+@2_shll_h .... .... ... 1  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+ #include "hw/arm/boot.h"
-+# VSHLL encoding T2 where shift == esize
++#include "hw/core/split-irq.h"
-+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
++#include "hw/arm/stm32l4x5_soc.h"
-+                qd=%qd qm=%qm size=0 shift=8
++#include "hw/gpio/stm32l4x5_gpio.h"
-+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
++#include "hw/display/dm163.h"
-+                qd=%qd qm=%qm size=1 shift=16
-+
+-/* B-L475E-IOT01A implementation is derived from netduinoplus2 */
- # Right shifts are encoded as N - shift, where N is the element size in bits.
++/* B-L475E-IOT01A implementation is inspired from netduinoplus2 and arduino */
  %rshift_i5  16:5 !function=rsub_32
  %rshift_i4  16:4 !function=rsub_16
@@ -XXX,XX +XXX,XX @@ VADD             1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
  VSUB             1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
  VMUL             1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
 -VMULH_S          111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
 -VMULH_U          111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
 +# The VSHLL T2 encoding is not a @2op pattern, but is here because it
 +# overlaps what would be size=0b11 VMULH/VRMULH
 +{
 +  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
 +  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
 -VRMULH_S         111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
 -VRMULH_U         111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
 +  VMULH_S        111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
 +}
 +
 +{
 +  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
 +  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
 +
 +  VMULH_U        111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
 +}
 +
 +{
 +  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
 +  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
 +
 +  VRMULH_S       111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
 +}
 +
 +{
 +  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
 +  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
 +
 +  VRMULH_U       111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
 +}
  VMAX_S           111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
  VMAX_U           111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
@@ -XXX,XX +XXX,XX @@ VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
  VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
  VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
  VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 +
 +# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
 +VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
 +VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
 +
 +VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
 +VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
 +
 +VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
 +VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
 +
 +VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
 +VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
  DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
  DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
  DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
 +
 +/*
-+ * Long shifts taking half-sized inputs from top or bottom of the input
++ * There are actually 14 input pins in the DM163 device.
-+ * vector and producing a double-width result. ESIZE, TYPE are for
++ * Here the DM163 input pin EN isn't connected to the STM32L4x5
-+ * the input, and LESIZE, LTYPE for the output.
++ * GPIOs as the IM120417002 colors shield doesn't actually use
-+ * Unlike the normal shift helpers, we do not handle negative shift counts,
++ * this pin to drive the RGB matrix.
 + * because the long shift is strictly left-only.
 + */
-+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE)                   \
++#define NUM_DM163_INPUTS 13
-+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
++
-+                                void *vm, uint32_t shift)               \
++static const unsigned dm163_input[NUM_DM163_INPUTS] = {
-+    {                                                                   \
++    1 * GPIO_NUM_PINS + 2,  /* ROW0  PB2       */
-+        LTYPE *d = vd;                                                  \
++    0 * GPIO_NUM_PINS + 15, /* ROW1  PA15      */
-+        TYPE *m = vm;                                                   \
++    0 * GPIO_NUM_PINS + 2,  /* ROW2  PA2       */
-+        uint16_t mask = mve_element_mask(env);                          \
++    0 * GPIO_NUM_PINS + 7,  /* ROW3  PA7       */
-+        unsigned le;                                                    \
++    0 * GPIO_NUM_PINS + 6,  /* ROW4  PA6       */
-+        assert(shift <= 16);                                            \
++    0 * GPIO_NUM_PINS + 5,  /* ROW5  PA5       */
-+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) {         \
++    1 * GPIO_NUM_PINS + 0,  /* ROW6  PB0       */
-+            LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift;        \
++    0 * GPIO_NUM_PINS + 3,  /* ROW7  PA3       */
-+            mergemask(&d[H##LESIZE(le)], r, mask);                      \
++    0 * GPIO_NUM_PINS + 4,  /* SIN (SDA) PA4   */
-+        }                                                               \
++    1 * GPIO_NUM_PINS + 1,  /* DCK (SCK) PB1   */
-+        mve_advance_vpt(env);                                           \
++    2 * GPIO_NUM_PINS + 3,  /* RST_B (RST) PC3 */
 +    2 * GPIO_NUM_PINS + 4,  /* LAT_B (LAT) PC4 */
 +    2 * GPIO_NUM_PINS + 5,  /* SELBK (SB)  PC5 */
 +};
  #define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a")
  OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A)
@@ -XXX,XX +XXX,XX @@ typedef struct Bl475eMachineState {
      MachineState parent_obj;
      Stm32l4x5SocState soc;
 +    SplitIRQ gpio_splitters[NUM_DM163_INPUTS];
 +    DM163State dm163;
  } Bl475eMachineState;
  static void bl475e_init(MachineState *machine)
  {
      Bl475eMachineState *s = B_L475E_IOT01A(machine);
      const Stm32l4x5SocClass *sc;
 +    DeviceState *dev, *gpio_out_splitter;
 +    unsigned gpio, pin;
      object_initialize_child(OBJECT(machine), "soc", &s->soc,
                              TYPE_STM32L4X5XG_SOC);
@@ -XXX,XX +XXX,XX @@ static void bl475e_init(MachineState *machine)
      sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
      armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
                         sc->flash_size);
 +
 +    if (object_class_by_name(TYPE_DM163)) {
 +        object_initialize_child(OBJECT(machine), "dm163",
 +                                &s->dm163, TYPE_DM163);
 +        dev = DEVICE(&s->dm163);
 +        qdev_realize(dev, NULL, &error_abort);
 +
 +        for (unsigned i = 0; i < NUM_DM163_INPUTS; i++) {
 +            object_initialize_child(OBJECT(machine), "gpio-out-splitters[*]",
 +                                    &s->gpio_splitters[i], TYPE_SPLIT_IRQ);
 +            gpio_out_splitter = DEVICE(&s->gpio_splitters[i]);
 +            qdev_prop_set_uint32(gpio_out_splitter, "num-lines", 2);
 +            qdev_realize(gpio_out_splitter, NULL, &error_fatal);
 +
 +            qdev_connect_gpio_out(gpio_out_splitter, 0,
 +                qdev_get_gpio_in(DEVICE(&s->soc), dm163_input[i]));
 +            qdev_connect_gpio_out(gpio_out_splitter, 1,
 +                qdev_get_gpio_in(dev, i));
 +            gpio = dm163_input[i] / GPIO_NUM_PINS;
 +            pin = dm163_input[i] % GPIO_NUM_PINS;
 +            qdev_connect_gpio_out(DEVICE(&s->soc.gpio[gpio]), pin,
 +                qdev_get_gpio_in(DEVICE(gpio_out_splitter), 0));
 +        }
 +    }
-+
+ }
-+#define DO_VSHLL_ALL(OP, TOP)                                \
-+    DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t)             \
+ static void bl475e_machine_init(ObjectClass *oc, void *data)
-+    DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t)           \
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 +    DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t)            \
 +    DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t)          \
 +
 +DO_VSHLL_ALL(vshllb, false)
 +DO_VSHLL_ALL(vshllt, true)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
+--- a/hw/arm/Kconfig
-+++ b/target/arm/translate-mve.c
++++ b/hw/arm/Kconfig
-@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
+@@ -XXX,XX +XXX,XX @@ config B_L475E_IOT01A
- DO_2SHIFT(VSHRI_U, vshli_u, true)
+     default y
- DO_2SHIFT(VRSHRI_S, vrshli_s, true)
+     depends on TCG && ARM
- DO_2SHIFT(VRSHRI_U, vrshli_u, true)
+     select STM32L4X5_SOC
-+
++    imply DM163
-+#define DO_VSHLL(INSN, FN)                                      \
-+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+ config STM32L4X5_SOC
-+    {                                                           \
+     bool
 +        static MVEGenTwoOpShiftFn * const fns[] = {             \
 +            gen_helper_mve_##FN##b,                             \
 +            gen_helper_mve_##FN##h,                             \
 +        };                                                      \
 +        return do_2shift(s, a, fns[a->size], false);            \
 +    }
 +
 +DO_VSHLL(VSHLL_BS, vshllbs)
 +DO_VSHLL(VSHLL_BU, vshllbu)
 +DO_VSHLL(VSHLL_TS, vshllts)
 +DO_VSHLL(VSHLL_TU, vshlltu)
 --
-.20.1
+.34.1

-[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
+[PULL 21/21] tests/qtest : Add testcase for DM163
-From: Maxim Uvarov <maxim.uvarov@linaro.org>
+From: Inès Varhol <ines.varhol@telecom-paris.fr>
-qemu has 2 type of functions: shutdown and reboot. Shutdown
+`test_dm163_bank()`
-function has to be used for machine shutdown. Otherwise we cause
+Checks that the pin "sout" of the DM163 led driver outputs the values
-a reset with a bogus "cause" value, when we intended a shutdown.
+received on pin "sin" with the expected latency (depending on the bank).
-Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
+`test_dm163_gpio_connection()`
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Check that changes to relevant STM32L4x5 GPIO pins are propagated to the
-Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
+DM163 device.
-[PMM: tweaked commit message]
 Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
 Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
 Acked-by: Thomas Huth <thuth@redhat.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20240424200929.240921-6-ines.varhol@telecom-paris.fr
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/gpio/gpio_pwr.c | 2 +-
+ tests/qtest/dm163-test.c | 194 +++++++++++++++++++++++++++++++++++++++
-file changed, 1 insertion(+), 1 deletion(-)
+ tests/qtest/meson.build  |   2 +
+files changed, 196 insertions(+)
-diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
+ create mode 100644 tests/qtest/dm163-test.c
 diff --git a/tests/qtest/dm163-test.c b/tests/qtest/dm163-test.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/qtest/dm163-test.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QTest testcase for DM163
 + *
 + * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
 + * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
 + * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
 + *
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + */
 +
 +#include "qemu/osdep.h"
 +#include "libqtest.h"
 +
 +enum DM163_INPUTS {
 +    SIN = 8,
 +    DCK = 9,
 +    RST_B = 10,
 +    LAT_B = 11,
 +    SELBK = 12,
 +    EN_B = 13
 +};
 +
 +#define DEVICE_NAME "/machine/dm163"
 +#define GPIO_OUT(name, value) qtest_set_irq_in(qts, DEVICE_NAME, NULL, name,   \
 +                                               value)
 +#define GPIO_PULSE(name)                                                       \
 +  do {                                                                         \
 +    GPIO_OUT(name, 1);                                                         \
 +    GPIO_OUT(name, 0);                                                         \
 +  } while (0)
 +
 +
 +static void rise_gpio_pin_dck(QTestState *qts)
 +{
 +    /* Configure output mode for pin PB1 */
 +    qtest_writel(qts, 0x48000400, 0xFFFFFEB7);
 +    /* Write 1 in ODR for PB1 */
 +    qtest_writel(qts, 0x48000414, 0x00000002);
 +}
 +
 +static void lower_gpio_pin_dck(QTestState *qts)
 +{
 +    /* Configure output mode for pin PB1 */
 +    qtest_writel(qts, 0x48000400, 0xFFFFFEB7);
 +    /* Write 0 in ODR for PB1 */
 +    qtest_writel(qts, 0x48000414, 0x00000000);
 +}
 +
 +static void rise_gpio_pin_selbk(QTestState *qts)
 +{
 +    /* Configure output mode for pin PC5 */
 +    qtest_writel(qts, 0x48000800, 0xFFFFF7FF);
 +    /* Write 1 in ODR for PC5 */
 +    qtest_writel(qts, 0x48000814, 0x00000020);
 +}
 +
 +static void lower_gpio_pin_selbk(QTestState *qts)
 +{
 +    /* Configure output mode for pin PC5 */
 +    qtest_writel(qts, 0x48000800, 0xFFFFF7FF);
 +    /* Write 0 in ODR for PC5 */
 +    qtest_writel(qts, 0x48000814, 0x00000000);
 +}
 +
 +static void rise_gpio_pin_lat_b(QTestState *qts)
 +{
 +    /* Configure output mode for pin PC4 */
 +    qtest_writel(qts, 0x48000800, 0xFFFFFDFF);
 +    /* Write 1 in ODR for PC4 */
 +    qtest_writel(qts, 0x48000814, 0x00000010);
 +}
 +
 +static void lower_gpio_pin_lat_b(QTestState *qts)
 +{
 +    /* Configure output mode for pin PC4 */
 +    qtest_writel(qts, 0x48000800, 0xFFFFFDFF);
 +    /* Write 0 in ODR for PC4 */
 +    qtest_writel(qts, 0x48000814, 0x00000000);
 +}
 +
 +static void rise_gpio_pin_rst_b(QTestState *qts)
 +{
 +    /* Configure output mode for pin PC3 */
 +    qtest_writel(qts, 0x48000800, 0xFFFFFF7F);
 +    /* Write 1 in ODR for PC3 */
 +    qtest_writel(qts, 0x48000814, 0x00000008);
 +}
 +
 +static void lower_gpio_pin_rst_b(QTestState *qts)
 +{
 +    /* Configure output mode for pin PC3 */
 +    qtest_writel(qts, 0x48000800, 0xFFFFFF7F);
 +    /* Write 0 in ODR for PC3 */
 +    qtest_writel(qts, 0x48000814, 0x00000000);
 +}
 +
 +static void rise_gpio_pin_sin(QTestState *qts)
 +{
 +    /* Configure output mode for pin PA4 */
 +    qtest_writel(qts, 0x48000000, 0xFFFFFDFF);
 +    /* Write 1 in ODR for PA4 */
 +    qtest_writel(qts, 0x48000014, 0x00000010);
 +}
 +
 +static void lower_gpio_pin_sin(QTestState *qts)
 +{
 +    /* Configure output mode for pin PA4 */
 +    qtest_writel(qts, 0x48000000, 0xFFFFFDFF);
 +    /* Write 0 in ODR for PA4 */
 +    qtest_writel(qts, 0x48000014, 0x00000000);
 +}
 +
 +static void test_dm163_bank(const void *opaque)
 +{
 +    const unsigned bank = (uintptr_t) opaque;
 +    const int width = bank ? 192 : 144;
 +
 +    QTestState *qts = qtest_initf("-M b-l475e-iot01a");
 +    qtest_irq_intercept_out_named(qts, DEVICE_NAME, "sout");
 +    GPIO_OUT(RST_B, 1);
 +    GPIO_OUT(EN_B, 0);
 +    GPIO_OUT(DCK, 0);
 +    GPIO_OUT(SELBK, bank);
 +    GPIO_OUT(LAT_B, 1);
 +
 +    /* Fill bank with zeroes */
 +    GPIO_OUT(SIN, 0);
 +    for (int i = 0; i < width; i++) {
 +        GPIO_PULSE(DCK);
 +    }
 +    /* Fill bank with ones, check that we get the previous zeroes */
 +    GPIO_OUT(SIN, 1);
 +    for (int i = 0; i < width; i++) {
 +        GPIO_PULSE(DCK);
 +        g_assert(!qtest_get_irq(qts, 0));
 +    }
 +
 +    /* Pulse one more bit in the bank, check that we get a one */
 +    GPIO_PULSE(DCK);
 +    g_assert(qtest_get_irq(qts, 0));
 +
 +    qtest_quit(qts);
 +}
 +
 +static void test_dm163_gpio_connection(void)
 +{
 +    QTestState *qts = qtest_init("-M b-l475e-iot01a");
 +    qtest_irq_intercept_in(qts, DEVICE_NAME);
 +
 +    g_assert_false(qtest_get_irq(qts, SIN));
 +    g_assert_false(qtest_get_irq(qts, DCK));
 +    g_assert_false(qtest_get_irq(qts, RST_B));
 +    g_assert_false(qtest_get_irq(qts, LAT_B));
 +    g_assert_false(qtest_get_irq(qts, SELBK));
 +
 +    rise_gpio_pin_dck(qts);
 +    g_assert_true(qtest_get_irq(qts, DCK));
 +    lower_gpio_pin_dck(qts);
 +    g_assert_false(qtest_get_irq(qts, DCK));
 +
 +    rise_gpio_pin_lat_b(qts);
 +    g_assert_true(qtest_get_irq(qts, LAT_B));
 +    lower_gpio_pin_lat_b(qts);
 +    g_assert_false(qtest_get_irq(qts, LAT_B));
 +
 +    rise_gpio_pin_selbk(qts);
 +    g_assert_true(qtest_get_irq(qts, SELBK));
 +    lower_gpio_pin_selbk(qts);
 +    g_assert_false(qtest_get_irq(qts, SELBK));
 +
 +    rise_gpio_pin_rst_b(qts);
 +    g_assert_true(qtest_get_irq(qts, RST_B));
 +    lower_gpio_pin_rst_b(qts);
 +    g_assert_false(qtest_get_irq(qts, RST_B));
 +
 +    rise_gpio_pin_sin(qts);
 +    g_assert_true(qtest_get_irq(qts, SIN));
 +    lower_gpio_pin_sin(qts);
 +    g_assert_false(qtest_get_irq(qts, SIN));
 +
 +    g_assert_false(qtest_get_irq(qts, DCK));
 +    g_assert_false(qtest_get_irq(qts, LAT_B));
 +    g_assert_false(qtest_get_irq(qts, SELBK));
 +    g_assert_false(qtest_get_irq(qts, RST_B));
 +}
 +
 +int main(int argc, char **argv)
 +{
 +    g_test_init(&argc, &argv, NULL);
 +    qtest_add_data_func("/dm163/bank0", (void *)0, test_dm163_bank);
 +    qtest_add_data_func("/dm163/bank1", (void *)1, test_dm163_bank);
 +    qtest_add_func("/dm163/gpio_connection", test_dm163_gpio_connection);
 +    return g_test_run();
 +}
 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/gpio/gpio_pwr.c
+--- a/tests/qtest/meson.build
-+++ b/hw/gpio/gpio_pwr.c
++++ b/tests/qtest/meson.build
-@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
+@@ -XXX,XX +XXX,XX @@ qtests_arm = \
- static void gpio_pwr_shutdown(void *opaque, int n, int level)
+   (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
- {
+   (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 : []) + \
-     if (level) {
+   (config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-test'] : []) + \
--        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
++  (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and
-+        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
++   config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \
-     }
+   ['arm-cpu-features',
- }
+    'boot-serial-test']
 --
-.20.1
+.34.1

-[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
+Deleted patch
-Use dup_const() instead of bitfield_replicate() in
-disas_simd_mod_imm().
-(We can't replace the other use of bitfield_replicate() in this file,
-in logic_imm_decode_wmask(), because that location needs to handle 2
-and 4 bit elements, which dup_const() cannot.)
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
----
- target/arm/translate-a64.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
-         /* FMOV (vector, immediate) - half-precision */
-         imm = vfp_expand_imm(MO_16, abcdefgh);
-         /* now duplicate across the lanes */
--        imm = bitfield_replicate(imm, 16);
-+        imm = dup_const(MO_16, imm);
-     } else {
-         imm = asimd_imm_const(abcdefgh, cmode, is_neg);
-     }
---
-.20.1

-[PULL 12/24] target/arm: Implement MVE logical immediate insns
+Deleted patch
-Implement the MVE logical-immediate insns (VMOV, VMVN,
-VORR and VBIC). These have essentially the same encoding
-as their Neon equivalents, and we implement the decode
-in the same way.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
----
- target/arm/helper-mve.h    |  4 +++
- target/arm/mve.decode      | 17 +++++++++++++
- target/arm/mve_helper.c    | 24 ++++++++++++++++++
- target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
-files changed, 95 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
-+++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
- DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
- DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
- DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
-+
-+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
-+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
-+DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
-+++ b/target/arm/mve.decode
-@@ -XXX,XX +XXX,XX @@
- # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
- %size_28 28:1 !function=plus_1
-+# 1imm format immediate
-+%imm_28_16_0 28:1 16:3 0:4
-+
- &vldr_vstr rn qd imm p a w size l u
- &1op qd qm size
- &2op qd qm qn size
- &2scalar qd qn rm size
-+&1imm qd imm cmode op
- @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
- # Note that both Rn and Qd are 3 bits only (no D bit)
-@@ -XXX,XX +XXX,XX @@
- @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
- @2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
-      size=%size_28
-+@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
- # The _rev suffix indicates that Vn and Vm are reversed. This is
- # the case for shifts. In the Arm ARM these insns are documented
-@@ -XXX,XX +XXX,XX @@ VADDV            111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
- # Predicate operations
- %mask_22_13      22:1 13:3
- VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
-+
-+# Logical immediate operations (1 reg and modified-immediate)
-+
-+# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
-+# not in a way we can conveniently represent in decodetree without
-+# a lot of repetition:
-+# VORR: op=0, (cmode & 1) && cmode < 12
-+# VBIC: op=1, (cmode & 1) && cmode < 12
-+# VMOV: everything else
-+# So we have a single decode line and check the cmode/op in the
-+# trans function.
-+Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve_helper.c
-+++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
- DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
- DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
-+/*
-+ * 1 operand immediates: Vda is destination and possibly also one source.
-+ * All these insns work at 64-bit widths.
-+ */
-+#define DO_1OP_IMM(OP, FN)                                              \
-+    void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm)    \
-+    {                                                                   \
-+        uint64_t *da = vda;                                             \
-+        uint16_t mask = mve_element_mask(env);                          \
-+        unsigned e;                                                     \
-+        for (e = 0; e < 16 / 8; e++, mask >>= 8) {                      \
-+            mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask);            \
-+        }                                                               \
-+        mve_advance_vpt(env);                                           \
-+    }
-+
-+#define DO_MOVI(N, I) (I)
-+#define DO_ANDI(N, I) ((N) & (I))
-+#define DO_ORRI(N, I) ((N) | (I))
-+
-+DO_1OP_IMM(vmovi, DO_MOVI)
-+DO_1OP_IMM(vandi, DO_ANDI)
-+DO_1OP_IMM(vorri, DO_ORRI)
-+
- #define DO_2OP(OP, ESIZE, TYPE, FN)                                     \
-     void HELPER(glue(mve_, OP))(CPUARMState *env,                       \
-                                 void *vd, void *vn, void *vm)           \
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
-+++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
- typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
- typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
- typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
-+typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
- /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
- static inline long mve_qreg_offset(unsigned reg)
-@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
-     mve_update_eci(s);
-     return true;
- }
-+
-+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
-+{
-+    TCGv_ptr qd;
-+    uint64_t imm;
-+
-+    if (!dc_isar_feature(aa32_mve, s) ||
-+        !mve_check_qreg_bank(s, a->qd) ||
-+        !fn) {
-+        return false;
-+    }
-+    if (!mve_eci_check(s) || !vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    imm = asimd_imm_const(a->imm, a->cmode, a->op);
-+
-+    qd = mve_qreg_ptr(a->qd);
-+    fn(cpu_env, qd, tcg_constant_i64(imm));
-+    tcg_temp_free_ptr(qd);
-+    mve_update_eci(s);
-+    return true;
-+}
-+
-+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
-+{
-+    /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
-+    MVEGenOneOpImmFn *fn;
-+
-+    if ((a->cmode & 1) && a->cmode < 12) {
-+        if (a->op) {
-+            /*
-+             * For op=1, the immediate will be inverted by asimd_imm_const(),
-+             * so the VBIC becomes a logical AND operation.
-+             */
-+            fn = gen_helper_mve_vandi;
-+        } else {
-+            fn = gen_helper_mve_vorri;
-+        }
-+    } else {
-+        /* There is one unallocated cmode/op combination in this space */
-+        if (a->cmode == 15 && a->op == 1) {
-+            return false;
-+        }
-+        /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
-+        fn = gen_helper_mve_vmovi;
-+    }
-+    return do_1imm(s, a, fn);
-+}
---
-.20.1

-[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
+Deleted patch
-Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
-and VQSHLU.
-The size-and-immediate encoding here is the same as Neon, and we
-handle it the same way neon-dp.decode does.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
----
- target/arm/helper-mve.h    | 16 +++++++++++
- target/arm/mve.decode      | 23 +++++++++++++++
- target/arm/mve_helper.c    | 57 ++++++++++++++++++++++++++++++++++++++
- target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
-files changed, 147 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
-+++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
- DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
- DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
- DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
-+
-+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+
-+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+
-+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+
-+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
-+++ b/target/arm/mve.decode
-@@ -XXX,XX +XXX,XX @@
- &2op qd qm qn size
- &2scalar qd qn rm size
- &1imm qd imm cmode op
-+&2shift qd qm shift size
- @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
- # Note that both Rn and Qd are 3 bits only (no D bit)
-@@ -XXX,XX +XXX,XX @@
- @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
- @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
-+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
-+@2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
-+@2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
-+
- # Vector loads and stores
- # Widening loads and narrowing stores:
-@@ -XXX,XX +XXX,XX @@ VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
- # So we have a single decode line and check the cmode/op in the
- # trans function.
- Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
-+
-+# Shifts by immediate
-+
-+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
-+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
-+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
-+
-+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
-+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
-+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
-+
-+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
-+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
-+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
-+
-+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
-+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
-+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve_helper.c
-+++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
-     WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
- #define DO_UQRSHL_OP(N, M, satp) \
-     WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
-+#define DO_SUQSHL_OP(N, M, satp) \
-+    WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
- DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
- DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
-@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
- DO_VADDV(vaddvub, 1, uint8_t)
- DO_VADDV(vaddvuh, 2, uint16_t)
- DO_VADDV(vaddvuw, 4, uint32_t)
-+
-+/* Shifts by immediate */
-+#define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
-+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
-+                                void *vm, uint32_t shift)       \
-+    {                                                           \
-+        TYPE *d = vd, *m = vm;                                  \
-+        uint16_t mask = mve_element_mask(env);                  \
-+        unsigned e;                                             \
-+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
-+            mergemask(&d[H##ESIZE(e)],                          \
-+                      FN(m[H##ESIZE(e)], shift), mask);         \
-+        }                                                       \
-+        mve_advance_vpt(env);                                   \
-+    }
-+
-+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN)                      \
-+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
-+                                void *vm, uint32_t shift)       \
-+    {                                                           \
-+        TYPE *d = vd, *m = vm;                                  \
-+        uint16_t mask = mve_element_mask(env);                  \
-+        unsigned e;                                             \
-+        bool qc = false;                                        \
-+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
-+            bool sat = false;                                   \
-+            mergemask(&d[H##ESIZE(e)],                          \
-+                      FN(m[H##ESIZE(e)], shift, &sat), mask);   \
-+            qc |= sat & mask & 1;                               \
-+        }                                                       \
-+        if (qc) {                                               \
-+            env->vfp.qc[0] = qc;                                \
-+        }                                                       \
-+        mve_advance_vpt(env);                                   \
-+    }
-+
-+/* provide unsigned 2-op shift helpers for all sizes */
-+#define DO_2SHIFT_U(OP, FN)                     \
-+    DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
-+    DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
-+    DO_2SHIFT(OP##w, 4, uint32_t, FN)
-+
-+#define DO_2SHIFT_SAT_U(OP, FN)                 \
-+    DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
-+    DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN)       \
-+    DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
-+#define DO_2SHIFT_SAT_S(OP, FN)                 \
-+    DO_2SHIFT_SAT(OP##b, 1, int8_t, FN)         \
-+    DO_2SHIFT_SAT(OP##h, 2, int16_t, FN)        \
-+    DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
-+
-+DO_2SHIFT_U(vshli_u, DO_VSHLU)
-+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
-+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
-+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
-+++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
- typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
- typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
- typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
-+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
- typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
- typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
- typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
-@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
-     }
-     return do_1imm(s, a, fn);
- }
-+
-+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
-+                      bool negateshift)
-+{
-+    TCGv_ptr qd, qm;
-+    int shift = a->shift;
-+
-+    if (!dc_isar_feature(aa32_mve, s) ||
-+        !mve_check_qreg_bank(s, a->qd | a->qm) ||
-+        !fn) {
-+        return false;
-+    }
-+    if (!mve_eci_check(s) || !vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    /*
-+     * When we handle a right shift insn using a left-shift helper
-+     * which permits a negative shift count to indicate a right-shift,
-+     * we must negate the shift count.
-+     */
-+    if (negateshift) {
-+        shift = -shift;
-+    }
-+
-+    qd = mve_qreg_ptr(a->qd);
-+    qm = mve_qreg_ptr(a->qm);
-+    fn(cpu_env, qd, qm, tcg_constant_i32(shift));
-+    tcg_temp_free_ptr(qd);
-+    tcg_temp_free_ptr(qm);
-+    mve_update_eci(s);
-+    return true;
-+}
-+
-+#define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
-+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
-+    {                                                           \
-+        static MVEGenTwoOpShiftFn * const fns[] = {             \
-+            gen_helper_mve_##FN##b,                             \
-+            gen_helper_mve_##FN##h,                             \
-+            gen_helper_mve_##FN##w,                             \
-+            NULL,                                               \
-+        };                                                      \
-+        return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
-+    }
-+
-+DO_2SHIFT(VSHLI, vshli_u, false)
-+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
-+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
-+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
---
-.20.1

The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:

Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702

for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:

target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)

----------------------------------------------------------------
target-arm queue:
 * more MVE instructions
 * hw/gpio/gpio_pwr: use shutdown function for reboot
 * target/arm: Check NaN mode before silencing NaN
 * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
 * hw/arm: Add basic power management to raspi.
 * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc

----------------------------------------------------------------
Joe Komlodi (1):
      target/arm: Check NaN mode before silencing NaN

Maxim Uvarov (1):
      hw/gpio/gpio_pwr: use shutdown function for reboot

Nolan Leake (1):
      hw/arm: Add basic power management to raspi.

Patrick Venture (2):
      docs/system/arm: Add quanta-q7l1-bmc reference
      docs/system/arm: Add quanta-gbs-bmc reference

Peter Maydell (18):
      target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
      target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
      target/arm: Make asimd_imm_const() public
      target/arm: Use asimd_imm_const for A64 decode
      target/arm: Use dup_const() instead of bitfield_replicate()
      target/arm: Implement MVE logical immediate insns
      target/arm: Implement MVE vector shift left by immediate insns
      target/arm: Implement MVE vector shift right by immediate insns
      target/arm: Implement MVE VSHLL
      target/arm: Implement MVE VSRI, VSLI
      target/arm: Implement MVE VSHRN, VRSHRN
      target/arm: Implement MVE saturating narrowing shifts
      target/arm: Implement MVE VSHLC
      target/arm: Implement MVE VADDLV
      target/arm: Implement MVE long shifts by immediate
      target/arm: Implement MVE long shifts by register
      target/arm: Implement MVE shifts by immediate
      target/arm: Implement MVE shifts by register

Philippe Mathieu-Daudé (1):
      tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine

docs/system/arm/aspeed.rst             |   1 +
 docs/system/arm/nuvoton.rst            |   5 +-
 include/hw/arm/bcm2835_peripherals.h   |   3 +-
 include/hw/misc/bcm2835_powermgt.h     |  29 ++
 target/arm/helper-mve.h                | 108 +++++++
 target/arm/translate.h                 |  41 +++
 target/arm/mve.decode                  | 177 ++++++++++-
 target/arm/t32.decode                  |  71 ++++-
 hw/arm/bcm2835_peripherals.c           |  13 +-
 hw/gpio/gpio_pwr.c                     |   2 +-
 hw/misc/bcm2835_powermgt.c             | 160 ++++++++++
 target/arm/helper-a64.c                |  12 +-
 target/arm/mve_helper.c                | 524 +++++++++++++++++++++++++++++++--
 target/arm/translate-a64.c             |  86 +-----
 target/arm/translate-mve.c             | 261 +++++++++++++++-
 target/arm/translate-neon.c            |  81 -----
 target/arm/translate.c                 | 327 +++++++++++++++++++-
 target/arm/vfp_helper.c                |  24 +-
 hw/misc/meson.build                    |   1 +
 tests/acceptance/boot_linux_console.py |  43 +++
 20 files changed, 1760 insertions(+), 209 deletions(-)
 create mode 100644 include/hw/misc/bcm2835_powermgt.h
 create mode 100644 hw/misc/bcm2835_powermgt.c

From: Patrick Venture <venture@google.com>

Add line item reference to quanta-gbs-bmc machine.

Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20210615192848.1065297-3-venture@google.com
[PMM: fixed underline Sphinx warning]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
-=====================================================
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
+================================================================
 
 The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
 designed to be used as Baseboard Management Controllers (BMCs) in various
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
 Hyperscale applications. The following machines are based on this chip :
 
+- ``quanta-gbs-bmc``    Quanta GBS server BMC
 - ``quanta-gsj``        Quanta GSJ server BMC
 
 There are also two more SoCs, NPCM710 and NPCM705, which are single-core
-- 
2.20.1

From: Nolan Leake <nolan@sigbus.net>

This is just enough to make reboot and poweroff work. Works for
linux, u-boot, and the arm trusted firmware. Not tested, but should
work for plan9, and bare-metal/hobby OSes, since they seem to generally
do what linux does for reset.

The watchdog timer functionality is not yet implemented.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
Signed-off-by: Nolan Leake <nolan@sigbus.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
[PMM: tweaked commit title; fixed region size to 0x200;
 moved header file to include/]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bcm2835_peripherals.h |   3 +-
 include/hw/misc/bcm2835_powermgt.h   |  29 +++++
 hw/arm/bcm2835_peripherals.c         |  13 ++-
 hw/misc/bcm2835_powermgt.c           | 160 +++++++++++++++++++++++++++
 hw/misc/meson.build                  |   1 +
 5 files changed, 204 insertions(+), 2 deletions(-)
 create mode 100644 include/hw/misc/bcm2835_powermgt.h
 create mode 100644 hw/misc/bcm2835_powermgt.c

diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2835_peripherals.h
+++ b/include/hw/arm/bcm2835_peripherals.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/bcm2835_mphi.h"
 #include "hw/misc/bcm2835_thermal.h"
 #include "hw/misc/bcm2835_cprman.h"
+#include "hw/misc/bcm2835_powermgt.h"
 #include "hw/sd/sdhci.h"
 #include "hw/sd/bcm2835_sdhost.h"
 #include "hw/gpio/bcm2835_gpio.h"
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
     BCM2835MphiState mphi;
     UnimplementedDeviceState txp;
     UnimplementedDeviceState armtmr;
-    UnimplementedDeviceState powermgt;
+    BCM2835PowerMgtState powermgt;
     BCM2835CprmanState cprman;
     PL011State uart0;
     BCM2835AuxState aux;
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/bcm2835_powermgt.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 Power Management emulation
+ *
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef BCM2835_POWERMGT_H
+#define BCM2835_POWERMGT_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
+
+struct BCM2835PowerMgtState {
+    SysBusDevice busdev;
+    MemoryRegion iomem;
+
+    uint32_t rstc;
+    uint32_t rsts;
+    uint32_t wdog;
+};
+
+#endif
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
 
     object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
                                    OBJECT(&s->gpu_bus_mr));
+
+    /* Power Management */
+    object_initialize_child(obj, "powermgt", &s->powermgt,
+                            TYPE_BCM2835_POWERMGT);
 }
 
 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
         qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
                                INTERRUPT_USB));
 
+    /* Power Management */
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
+        return;
+    }
+
+    memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
+                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
+
     create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
-    create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
     create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
     create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
     create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/bcm2835_powermgt.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 Power Management emulation
+ *
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/bcm2835_powermgt.h"
+#include "migration/vmstate.h"
+#include "sysemu/runstate.h"
+
+#define PASSWORD 0x5a000000
+#define PASSWORD_MASK 0xff000000
+
+#define R_RSTC 0x1c
+#define V_RSTC_RESET 0x20
+#define R_RSTS 0x20
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
+#define R_WDOG 0x24
+
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
+                                      unsigned size)
+{
+    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
+    uint32_t res = 0;
+
+    switch (offset) {
+    case R_RSTC:
+        res = s->rstc;
+        break;
+    case R_RSTS:
+        res = s->rsts;
+        break;
+    case R_WDOG:
+        res = s->wdog;
+        break;
+
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
+                      "\n", offset);
+        res = 0;
+        break;
+    }
+
+    return res;
+}
+
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
+                                   uint64_t value, unsigned size)
+{
+    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
+
+    if ((value & PASSWORD_MASK) != PASSWORD) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "bcm2835_powermgt_write: Bad password 0x%"PRIx64
+                      " at offset 0x%08"HWADDR_PRIx"\n",
+                      value, offset);
+        return;
+    }
+
+    value = value & ~PASSWORD_MASK;
+
+    switch (offset) {
+    case R_RSTC:
+        s->rstc = value;
+        if (value & V_RSTC_RESET) {
+            if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
+                qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+            } else {
+                qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+            }
+        }
+        break;
+    case R_RSTS:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: RSTS\n");
+        s->rsts = value;
+        break;
+    case R_WDOG:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: WDOG\n");
+        s->wdog = value;
+        break;
+
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
+                      "\n", offset);
+        break;
+    }
+}
+
+static const MemoryRegionOps bcm2835_powermgt_ops = {
+    .read = bcm2835_powermgt_read,
+    .write = bcm2835_powermgt_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const VMStateDescription vmstate_bcm2835_powermgt = {
+    .name = TYPE_BCM2835_POWERMGT,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
+        VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
+        VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void bcm2835_powermgt_init(Object *obj)
+{
+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
+
+    memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
+                          TYPE_BCM2835_POWERMGT, 0x200);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static void bcm2835_powermgt_reset(DeviceState *dev)
+{
+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
+
+    /* https://elinux.org/BCM2835_registers#PM */
+    s->rstc = 0x00000102;
+    s->rsts = 0x00001000;
+    s->wdog = 0x00000000;
+}
+
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = bcm2835_powermgt_reset;
+    dc->vmsd = &vmstate_bcm2835_powermgt;
+}
+
+static TypeInfo bcm2835_powermgt_info = {
+    .name          = TYPE_BCM2835_POWERMGT,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(BCM2835PowerMgtState),
+    .class_init    = bcm2835_powermgt_class_init,
+    .instance_init = bcm2835_powermgt_init,
+};
+
+static void bcm2835_powermgt_register_types(void)
+{
+    type_register_static(&bcm2835_powermgt_info);
+}
+
+type_init(bcm2835_powermgt_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
   'bcm2835_rng.c',
   'bcm2835_thermal.c',
   'bcm2835_cprman.c',
+  'bcm2835_powermgt.c',
 ))
 softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
 softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Add a test booting and quickly shutdown a raspi2 machine,
to test the power management model:

(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
  console: [    0.000000] Booting Linux on physical CPU 0xf00
  console: [    0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
  console: [    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
  console: [    0.000000] CPU: div instructions available: patching division code
  console: [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  console: [    0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
  ...
  console: Boot successful.
  console: cat /proc/cpuinfo
  console: / # cat /proc/cpuinfo
  ...
  console: processor      : 3
  console: model name     : ARMv7 Processor rev 5 (v7l)
  console: BogoMIPS       : 125.00
  console: Features       : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
  console: CPU implementer        : 0x41
  console: CPU architecture: 7
  console: CPU variant    : 0x0
  console: CPU part       : 0xc07
  console: CPU revision   : 5
  console: Hardware       : BCM2835
  console: Revision       : 0000
  console: Serial         : 0000000000000000
  console: cat /proc/iomem
  console: / # cat /proc/iomem
  console: 00000000-3bffffff : System RAM
  console: 00008000-00afffff : Kernel code
  console: 00c00000-00d468ef : Kernel data
  console: 3f006000-3f006fff : dwc_otg
  console: 3f007000-3f007eff : /soc/dma@7e007000
  console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
  console: 3f100000-3f100027 : /soc/watchdog@7e100000
  console: 3f101000-3f102fff : /soc/cprman@7e101000
  console: 3f200000-3f2000b3 : /soc/gpio@7e200000
  PASS (24.59 s)
  RESULTS    : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
  JOB TIME   : 25.02 s

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@
 from avocado import skip
 from avocado import skipUnless
 from avocado_qemu import Test
+from avocado_qemu import exec_command
 from avocado_qemu import exec_command_and_wait_for_pattern
 from avocado_qemu import interrupt_interactive_console_until_pattern
 from avocado_qemu import wait_for_console_pattern
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
         """
         self.do_test_arm_raspi2(0)
 
+    def test_arm_raspi2_initrd(self):
+        """
+        :avocado: tags=arch:arm
+        :avocado: tags=machine:raspi2
+        """
+        deb_url = ('http://archive.raspberrypi.org/debian/'
+                   'pool/main/r/raspberrypi-firmware/'
+                   'raspberrypi-kernel_1.20190215-1_armhf.deb')
+        deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
+        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+        kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
+        dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
+
+        initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
+                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
+                      'arm/rootfs-armv7a.cpio.gz')
+        initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
+        initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
+        initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
+        archive.gzip_uncompress(initrd_path_gz, initrd_path)
+
+        self.vm.set_console()
+        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+                               'earlycon=pl011,0x3f201000 console=ttyAMA0 '
+                               'panic=-1 noreboot ' +
+                               'dwc_otg.fiq_fsm_enable=0')
+        self.vm.add_args('-kernel', kernel_path,
+                         '-dtb', dtb_path,
+                         '-initrd', initrd_path,
+                         '-append', kernel_command_line,
+                         '-no-reboot')
+        self.vm.launch()
+        self.wait_for_console_pattern('Boot successful.')
+
+        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+                                                'BCM2835')
+        exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
+                                                '/soc/cprman@7e101000')
+        exec_command(self, 'halt')
+        # Wait for VM to shut down gracefully
+        self.vm.wait()
+
     def test_arm_exynos4210_initrd(self):
         """
         :avocado: tags=arch:arm
-- 
2.20.1

From: Joe Komlodi <joe.komlodi@xilinx.com>

If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
assert due to fpst->default_nan_mode being set.

To avoid this, we check to see what NaN mode we're running in before we call
floatxx_silence_nan().

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.c | 12 +++++++++---
 target/arm/vfp_helper.c | 24 ++++++++++++++++++------
 2 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
         float16 nan = a;
         if (float16_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float16_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float16_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
         float32 nan = a;
         if (float32_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float32_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float32_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
         float64 nan = a;
         if (float64_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float64_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float64_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float64_default_nan(fpst);
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
         float16 nan = f16;
         if (float16_is_signaling_nan(f16, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float16_silence_nan(f16, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float16_silence_nan(f16, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
         float32 nan = f32;
         if (float32_is_signaling_nan(f32, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float32_silence_nan(f32, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float32_silence_nan(f32, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
         float64 nan = f64;
         if (float64_is_signaling_nan(f64, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float64_silence_nan(f64, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float64_silence_nan(f64, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float64_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
         float16 nan = f16;
         if (float16_is_signaling_nan(f16, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float16_silence_nan(f16, s);
+            if (!s->default_nan_mode) {
+                nan = float16_silence_nan(f16, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float16_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
         float32 nan = f32;
         if (float32_is_signaling_nan(f32, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float32_silence_nan(f32, s);
+            if (!s->default_nan_mode) {
+                nan = float32_silence_nan(f32, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float32_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
         float64 nan = f64;
         if (float64_is_signaling_nan(f64, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float64_silence_nan(f64, s);
+            if (!s->default_nan_mode) {
+                nan = float64_silence_nan(f64, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float64_default_nan(s);
-- 
2.20.1

From: Maxim Uvarov <maxim.uvarov@linaro.org>

qemu has 2 type of functions: shutdown and reboot. Shutdown
function has to be used for machine shutdown. Otherwise we cause
a reset with a bogus "cause" value, when we intended a shutdown.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/gpio/gpio_pwr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/gpio_pwr.c
+++ b/hw/gpio/gpio_pwr.c
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
 static void gpio_pwr_shutdown(void *opaque, int n, int level)
 {
     if (level) {
-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
     }
 }
 
-- 
2.20.1

In do_ldst(), the calculation of the offset needs to be based on the
size of the memory access, not the size of the elements in the
vector.  This meant we were getting it wrong for the widening and
narrowing variants of the various VLDR and VSTR insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
---
 target/arm/translate-mve.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
     }
 }
 
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
+                    unsigned msize)
 {
     TCGv_i32 addr;
     uint32_t offset;
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
         return true;
     }
 
-    offset = a->imm << a->size;
+    offset = a->imm << msize;
     if (!a->a) {
         offset = -offset;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
         { gen_helper_mve_vstrw, gen_helper_mve_vldrw },
         { NULL, NULL }
     };
-    return do_ldst(s, a, ldstfns[a->size][a->l]);
+    return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
 }
 
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST)                  \
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE)           \
     static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
     {                                                           \
         static MVEGenLdStFn * const ldstfns[2][2] = {           \
             { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
             { NULL, gen_helper_mve_##ULD },                     \
         };                                                      \
-        return do_ldst(s, a, ldstfns[a->u][a->l]);              \
+        return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE);       \
     }
 
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
 
 static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
 {
-- 
2.20.1

The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
insns had some bugs:
 * the 32x32 multiply of elements was being done as 32x32->32,
   not 32x32->64
 * we were incorrectly maintaining the accumulator in its full
   72-bit form across all 4 beats of the insn; in the pseudocode
   it is squashed back into the 64 bits of the RdaHi:RdaLo
   registers after each beat

In particular, fixing the second of these allows us to recast
the implementation to avoid 128-bit arithmetic entirely.

Since the element size here is always 4, we can also drop the
parameterization of ESIZE to make the code a little more readable.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
---
 target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
 1 file changed, 21 insertions(+), 17 deletions(-)

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu/int128.h"
 #include "cpu.h"
 #include "internals.h"
 #include "vec_internal.h"
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
 
 /*
- * Rounding multiply add long dual accumulate high: we must keep
- * a 72-bit internal accumulator value and return the top 64 bits.
+ * Rounding multiply add long dual accumulate high. In the pseudocode
+ * this is implemented with a 72-bit internal accumulator value of which
+ * the top 64 bits are returned. We optimize this to avoid having to
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
+ * is squashed back into 64-bits after each beat.
  */
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128)         \
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB)                            \
     uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn,         \
                                     void *vm, uint64_t a)               \
     {                                                                   \
         uint16_t mask = mve_element_mask(env);                          \
         unsigned e;                                                     \
         TYPE *n = vn, *m = vm;                                          \
-        Int128 acc = int128_lshift(TO128(a), 8);                        \
-        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {              \
+        for (e = 0; e < 16 / 4; e++, mask >>= 4) {                      \
             if (mask & 1) {                                             \
+                LTYPE mul;                                              \
                 if (e & 1) {                                            \
-                    acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
-                                            m[H##ESIZE(e)]));           \
+                    mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)];        \
+                    if (SUB) {                                          \
+                        mul = -mul;                                     \
+                    }                                                   \
                 } else {                                                \
-                    acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
-                                             m[H##ESIZE(e)]));          \
+                    mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)];        \
                 }                                                       \
-                acc = int128_add(acc, int128_make64(1 << 7));           \
+                mul = (mul >> 8) + ((mul >> 7) & 1);                    \
+                a += mul;                                               \
             }                                                           \
         }                                                               \
         mve_advance_vpt(env);                                           \
-        return int128_getlo(int128_rshift(acc, 8));                     \
+        return a;                                                       \
     }
 
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
 
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
 
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
 
 /* Vector add across vector */
 #define DO_VADDV(OP, ESIZE, TYPE)                               \
-- 
2.20.1

The function asimd_imm_const() in translate-neon.c is an
implementation of the pseudocode AdvSIMDExpandImm(), which we will
also want for MVE.  Move the implementation to translate.c, with a
prototype in translate.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
---
 target/arm/translate.h      | 16 ++++++++++
 target/arm/translate-neon.c | 63 -------------------------------------
 target/arm/translate.c      | 57 +++++++++++++++++++++++++++++++++
 3 files changed, 73 insertions(+), 63 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
     return opc | s->be_data;
 }
 
+/**
+ * asimd_imm_const: Expand an encoded SIMD constant value
+ *
+ * Expand a SIMD constant value. This is essentially the pseudocode
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
+ * VMVN and VBIC (when cmode < 14 && op == 1).
+ *
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
+ * callers must catch this.
+ *
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
+ * we produce an immediate constant value of 0 in these cases.
+ */
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
+
 #endif /* TARGET_ARM_TRANSLATE_H */
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
 DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
 DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
 
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
-{
-    /*
-     * Expand the encoded constant.
-     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
-     * We choose to not special-case this and will behave as if a
-     * valid constant encoding of 0 had been given.
-     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
-     */
-    switch (cmode) {
-    case 0: case 1:
-        /* no-op */
-        break;
-    case 2: case 3:
-        imm <<= 8;
-        break;
-    case 4: case 5:
-        imm <<= 16;
-        break;
-    case 6: case 7:
-        imm <<= 24;
-        break;
-    case 8: case 9:
-        imm |= imm << 16;
-        break;
-    case 10: case 11:
-        imm = (imm << 8) | (imm << 24);
-        break;
-    case 12:
-        imm = (imm << 8) | 0xff;
-        break;
-    case 13:
-        imm = (imm << 16) | 0xffff;
-        break;
-    case 14:
-        if (op) {
-            /*
-             * This is the only case where the top and bottom 32 bits
-             * of the encoded constant differ.
-             */
-            uint64_t imm64 = 0;
-            int n;
-
-            for (n = 0; n < 8; n++) {
-                if (imm & (1 << n)) {
-                    imm64 |= (0xffULL << (n * 8));
-                }
-            }
-            return imm64;
-        }
-        imm |= (imm << 8) | (imm << 16) | (imm << 24);
-        break;
-    case 15:
-        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
-            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
-        break;
-    }
-    if (op) {
-        imm = ~imm;
-    }
-    return dup_const(MO_32, imm);
-}
-
 static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
                         GVecGen2iFn *fn)
 {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
     a64_translate_init();
 }
 
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
+{
+    /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
+    switch (cmode) {
+    case 0: case 1:
+        /* no-op */
+        break;
+    case 2: case 3:
+        imm <<= 8;
+        break;
+    case 4: case 5:
+        imm <<= 16;
+        break;
+    case 6: case 7:
+        imm <<= 24;
+        break;
+    case 8: case 9:
+        imm |= imm << 16;
+        break;
+    case 10: case 11:
+        imm = (imm << 8) | (imm << 24);
+        break;
+    case 12:
+        imm = (imm << 8) | 0xff;
+        break;
+    case 13:
+        imm = (imm << 16) | 0xffff;
+        break;
+    case 14:
+        if (op) {
+            /*
+             * This is the only case where the top and bottom 32 bits
+             * of the encoded constant differ.
+             */
+            uint64_t imm64 = 0;
+            int n;
+
+            for (n = 0; n < 8; n++) {
+                if (imm & (1 << n)) {
+                    imm64 |= (0xffULL << (n * 8));
+                }
+            }
+            return imm64;
+        }
+        imm |= (imm << 8) | (imm << 16) | (imm << 24);
+        break;
+    case 15:
+        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
+            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
+        break;
+    }
+    if (op) {
+        imm = ~imm;
+    }
+    return dup_const(MO_32, imm);
+}
+
 /* Generate a label used for skipping this instruction */
 void arm_gen_condlabel(DisasContext *s)
 {
-- 
2.20.1

The A64 AdvSIMD modified-immediate grouping uses almost the same
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
which we add the AArch64-specific case for cmode 15 op 1) instead of
reimplementing it all.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
---
 target/arm/translate.h     |  3 +-
 target/arm/translate-a64.c | 86 ++++----------------------------------
 target/arm/translate.c     | 17 +++++++-
 3 files changed, 24 insertions(+), 82 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
  * VMVN and VBIC (when cmode < 14 && op == 1).
  *
  * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
- * callers must catch this.
+ * callers must catch this; we return the 64-bit constant value defined
+ * for AArch64.
  *
  * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
  * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
 {
     int rd = extract32(insn, 0, 5);
     int cmode = extract32(insn, 12, 4);
-    int cmode_3_1 = extract32(cmode, 1, 3);
-    int cmode_0 = extract32(cmode, 0, 1);
     int o2 = extract32(insn, 11, 1);
     uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
     bool is_neg = extract32(insn, 29, 1);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
         return;
     }
 
-    /* See AdvSIMDExpandImm() in ARM ARM */
-    switch (cmode_3_1) {
-    case 0: /* Replicate(Zeros(24):imm8, 2) */
-    case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
-    case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
-    case 3: /* Replicate(imm8:Zeros(24), 2) */
-    {
-        int shift = cmode_3_1 * 8;
-        imm = bitfield_replicate(abcdefgh << shift, 32);
-        break;
-    }
-    case 4: /* Replicate(Zeros(8):imm8, 4) */
-    case 5: /* Replicate(imm8:Zeros(8), 4) */
-    {
-        int shift = (cmode_3_1 & 0x1) * 8;
-        imm = bitfield_replicate(abcdefgh << shift, 16);
-        break;
-    }
-    case 6:
-        if (cmode_0) {
-            /* Replicate(Zeros(8):imm8:Ones(16), 2) */
-            imm = (abcdefgh << 16) | 0xffff;
-        } else {
-            /* Replicate(Zeros(16):imm8:Ones(8), 2) */
-            imm = (abcdefgh << 8) | 0xff;
-        }
-        imm = bitfield_replicate(imm, 32);
-        break;
-    case 7:
-        if (!cmode_0 && !is_neg) {
-            imm = bitfield_replicate(abcdefgh, 8);
-        } else if (!cmode_0 && is_neg) {
-            int i;
-            imm = 0;
-            for (i = 0; i < 8; i++) {
-                if ((abcdefgh) & (1 << i)) {
-                    imm |= 0xffULL << (i * 8);
-                }
-            }
-        } else if (cmode_0) {
-            if (is_neg) {
-                imm = (abcdefgh & 0x3f) << 48;
-                if (abcdefgh & 0x80) {
-                    imm |= 0x8000000000000000ULL;
-                }
-                if (abcdefgh & 0x40) {
-                    imm |= 0x3fc0000000000000ULL;
-                } else {
-                    imm |= 0x4000000000000000ULL;
-                }
-            } else {
-                if (o2) {
-                    /* FMOV (vector, immediate) - half-precision */
-                    imm = vfp_expand_imm(MO_16, abcdefgh);
-                    /* now duplicate across the lanes */
-                    imm = bitfield_replicate(imm, 16);
-                } else {
-                    imm = (abcdefgh & 0x3f) << 19;
-                    if (abcdefgh & 0x80) {
-                        imm |= 0x80000000;
-                    }
-                    if (abcdefgh & 0x40) {
-                        imm |= 0x3e000000;
-                    } else {
-                        imm |= 0x40000000;
-                    }
-                    imm |= (imm << 32);
-                }
-            }
-        }
-        break;
-    default:
-        g_assert_not_reached();
-    }
-
-    if (cmode_3_1 != 7 && is_neg) {
-        imm = ~imm;
+    if (cmode == 15 && o2 && !is_neg) {
+        /* FMOV (vector, immediate) - half-precision */
+        imm = vfp_expand_imm(MO_16, abcdefgh);
+        /* now duplicate across the lanes */
+        imm = bitfield_replicate(imm, 16);
+    } else {
+        imm = asimd_imm_const(abcdefgh, cmode, is_neg);
     }
 
     if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
     case 14:
         if (op) {
             /*
-             * This is the only case where the top and bottom 32 bits
-             * of the encoded constant differ.
+             * This and cmode == 15 op == 1 are the only cases where
+             * the top and bottom 32 bits of the encoded constant differ.
              */
             uint64_t imm64 = 0;
             int n;
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
         imm |= (imm << 8) | (imm << 16) | (imm << 24);
         break;
     case 15:
+        if (op) {
+            /* Reserved encoding for AArch32; valid for AArch64 */
+            uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
+            if (imm & 0x80) {
+                imm64 |= 0x8000000000000000ULL;
+            }
+            if (imm & 0x40) {
+                imm64 |= 0x3fc0000000000000ULL;
+            } else {
+                imm64 |= 0x4000000000000000ULL;
+            }
+            return imm64;
+        }
         imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
             | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
         break;
-- 
2.20.1

Use dup_const() instead of bitfield_replicate() in
disas_simd_mod_imm().

(We can't replace the other use of bitfield_replicate() in this file,
in logic_imm_decode_wmask(), because that location needs to handle 2
and 4 bit elements, which dup_const() cannot.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
---
 target/arm/translate-a64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
         /* FMOV (vector, immediate) - half-precision */
         imm = vfp_expand_imm(MO_16, abcdefgh);
         /* now duplicate across the lanes */
-        imm = bitfield_replicate(imm, 16);
+        imm = dup_const(MO_16, imm);
     } else {
         imm = asimd_imm_const(abcdefgh, cmode, is_neg);
     }
-- 
2.20.1

Implement the MVE logical-immediate insns (VMOV, VMVN,
VORR and VBIC). These have essentially the same encoding
as their Neon equivalents, and we implement the decode
in the same way.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  4 +++
 target/arm/mve.decode      | 17 +++++++++++++
 target/arm/mve_helper.c    | 24 ++++++++++++++++++
 target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 95 insertions(+)

Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
and VQSHLU.

The size-and-immediate encoding here is the same as Neon, and we
handle it the same way neon-dp.decode does.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    | 16 +++++++++++
 target/arm/mve.decode      | 23 +++++++++++++++
 target/arm/mve_helper.c    | 57 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
 4 files changed, 147 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
 DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
 DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
 DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
+
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
 &2op qd qm qn size
 &2scalar qd qn rm size
 &1imm qd imm cmode op
+&2shift qd qm shift size
 
 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
 # Note that both Rn and Qd are 3 bits only (no D bit)
@@ -XXX,XX +XXX,XX @@
 @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
+@2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+@2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
+
 # Vector loads and stores
 
 # Widening loads and narrowing stores:
@@ -XXX,XX +XXX,XX @@ VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
 # So we have a single decode line and check the cmode/op in the
 # trans function.
 Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
+
+# Shifts by immediate
+
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
     WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
 #define DO_UQRSHL_OP(N, M, satp) \
     WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
+#define DO_SUQSHL_OP(N, M, satp) \
+    WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
 
 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
 DO_VADDV(vaddvub, 1, uint8_t)
 DO_VADDV(vaddvuh, 2, uint16_t)
 DO_VADDV(vaddvuw, 4, uint32_t)
+
+/* Shifts by immediate */
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        TYPE *d = vd, *m = vm;                                  \
+        uint16_t mask = mve_element_mask(env);                  \
+        unsigned e;                                             \
+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
+            mergemask(&d[H##ESIZE(e)],                          \
+                      FN(m[H##ESIZE(e)], shift), mask);         \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN)                      \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        TYPE *d = vd, *m = vm;                                  \
+        uint16_t mask = mve_element_mask(env);                  \
+        unsigned e;                                             \
+        bool qc = false;                                        \
+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
+            bool sat = false;                                   \
+            mergemask(&d[H##ESIZE(e)],                          \
+                      FN(m[H##ESIZE(e)], shift, &sat), mask);   \
+            qc |= sat & mask & 1;                               \
+        }                                                       \
+        if (qc) {                                               \
+            env->vfp.qc[0] = qc;                                \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+/* provide unsigned 2-op shift helpers for all sizes */
+#define DO_2SHIFT_U(OP, FN)                     \
+    DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
+    DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
+    DO_2SHIFT(OP##w, 4, uint32_t, FN)
+
+#define DO_2SHIFT_SAT_U(OP, FN)                 \
+    DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
+    DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN)       \
+    DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
+#define DO_2SHIFT_SAT_S(OP, FN)                 \
+    DO_2SHIFT_SAT(OP##b, 1, int8_t, FN)         \
+    DO_2SHIFT_SAT(OP##h, 2, int16_t, FN)        \
+    DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
+
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
 typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
     }
     return do_1imm(s, a, fn);
 }
+
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
+                      bool negateshift)
+{
+    TCGv_ptr qd, qm;
+    int shift = a->shift;
+
+    if (!dc_isar_feature(aa32_mve, s) ||
+        !mve_check_qreg_bank(s, a->qd | a->qm) ||
+        !fn) {
+        return false;
+    }
+    if (!mve_eci_check(s) || !vfp_access_check(s)) {
+        return true;
+    }
+
+    /*
+     * When we handle a right shift insn using a left-shift helper
+     * which permits a negative shift count to indicate a right-shift,
+     * we must negate the shift count.
+     */
+    if (negateshift) {
+        shift = -shift;
+    }
+
+    qd = mve_qreg_ptr(a->qd);
+    qm = mve_qreg_ptr(a->qm);
+    fn(cpu_env, qd, qm, tcg_constant_i32(shift));
+    tcg_temp_free_ptr(qd);
+    tcg_temp_free_ptr(qm);
+    mve_update_eci(s);
+    return true;
+}
+
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+    {                                                           \
+        static MVEGenTwoOpShiftFn * const fns[] = {             \
+            gen_helper_mve_##FN##b,                             \
+            gen_helper_mve_##FN##h,                             \
+            gen_helper_mve_##FN##w,                             \
+            NULL,                                               \
+        };                                                      \
+        return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
+    }
+
+DO_2SHIFT(VSHLI, vshli_u, false)
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
-- 
2.20.1

Implement the MVE vector shift right by immediate insns VSHRI and
VRSHRI.  As with Neon, we implement these by using helper functions
which perform left shifts but allow negative shift counts to indicate
right shifts.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
---
 target/arm/helper-mve.h     | 12 ++++++++++++
 target/arm/translate.h      | 20 ++++++++++++++++++++
 target/arm/mve.decode       | 28 ++++++++++++++++++++++++++++
 target/arm/mve_helper.c     |  7 +++++++
 target/arm/translate-mve.c  |  5 +++++
 target/arm/translate-neon.c | 18 ------------------
 6 files changed, 72 insertions(+), 18 deletions(-)

Implement the MVE VHLL (vector shift left long) insn.  This has two
encodings: the T1 encoding is the usual shift-by-immediate format,
and the T2 encoding is a special case where the shift count is always
equal to the element size.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  9 +++++++
 target/arm/mve.decode      | 53 +++++++++++++++++++++++++++++++++++---
 target/arm/mve_helper.c    | 32 +++++++++++++++++++++++
 target/arm/translate-mve.c | 15 +++++++++++
 4 files changed, 105 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
 @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
 @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
 
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
+@2_shll_h .... .... ... 1  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+# VSHLL encoding T2 where shift == esize
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
+                qd=%qd qm=%qm size=0 shift=8
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
+                qd=%qd qm=%qm size=1 shift=16
+
 # Right shifts are encoded as N - shift, where N is the element size in bits.
 %rshift_i5  16:5 !function=rsub_32
 %rshift_i4  16:4 !function=rsub_16
@@ -XXX,XX +XXX,XX @@ VADD             1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
 VSUB             1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
 VMUL             1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
 
-VMULH_S          111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
-VMULH_U          111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
+# overlaps what would be size=0b11 VMULH/VRMULH
+{
+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
 
-VRMULH_S         111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
-VRMULH_U         111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+  VMULH_S        111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VMULH_U        111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VRMULH_S       111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VRMULH_U       111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+}
 
 VMAX_S           111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
 VMAX_U           111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
@@ -XXX,XX +XXX,XX @@ VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
+
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
 DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
 DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
+
+/*
+ * Long shifts taking half-sized inputs from top or bottom of the input
+ * vector and producing a double-width result. ESIZE, TYPE are for
+ * the input, and LESIZE, LTYPE for the output.
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
+ * because the long shift is strictly left-only.
+ */
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE)                   \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
+                                void *vm, uint32_t shift)               \
+    {                                                                   \
+        LTYPE *d = vd;                                                  \
+        TYPE *m = vm;                                                   \
+        uint16_t mask = mve_element_mask(env);                          \
+        unsigned le;                                                    \
+        assert(shift <= 16);                                            \
+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) {         \
+            LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift;        \
+            mergemask(&d[H##LESIZE(le)], r, mask);                      \
+        }                                                               \
+        mve_advance_vpt(env);                                           \
+    }
+
+#define DO_VSHLL_ALL(OP, TOP)                                \
+    DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t)             \
+    DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t)           \
+    DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t)            \
+    DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t)          \
+
+DO_VSHLL_ALL(vshllb, false)
+DO_VSHLL_ALL(vshllt, true)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
 DO_2SHIFT(VSHRI_U, vshli_u, true)
 DO_2SHIFT(VRSHRI_S, vrshli_s, true)
 DO_2SHIFT(VRSHRI_U, vrshli_u, true)
+
+#define DO_VSHLL(INSN, FN)                                      \
+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+    {                                                           \
+        static MVEGenTwoOpShiftFn * const fns[] = {             \
+            gen_helper_mve_##FN##b,                             \
+            gen_helper_mve_##FN##h,                             \
+        };                                                      \
+        return do_2shift(s, a, fns[a->size], false);            \
+    }
+
+DO_VSHLL(VSHLL_BS, vshllbs)
+DO_VSHLL(VSHLL_BU, vshllbu)
+DO_VSHLL(VSHLL_TS, vshllts)
+DO_VSHLL(VSHLL_TU, vshlltu)
-- 
2.20.1

Implement the MVE VSRI and VSLI insns, which perform a
shift-and-insert operation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  8 ++++++++
 target/arm/mve.decode      |  9 ++++++++
 target/arm/mve_helper.c    | 42 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  3 +++
 4 files changed, 62 insertions(+)

Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.

do_urshr() is borrowed from sve_helper.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    | 10 ++++++++++
 target/arm/mve.decode      | 11 +++++++++++
 target/arm/mve_helper.c    | 40 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 15 ++++++++++++++
 4 files changed, 76 insertions(+)

Implement the MVE saturating shift-right-and-narrow insns
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.

do_srshr() is borrowed from sve_helper.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  30 +++++++++++
 target/arm/mve.decode      |  28 ++++++++++
 target/arm/mve_helper.c    | 104 +++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  12 +++++
 4 files changed, 174 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
 VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
 VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
 VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
+
+VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
+
+VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
+
+VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
+
+VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
     }
 }
 
+static inline int64_t do_srshr(int64_t x, unsigned sh)
+{
+    if (likely(sh < 64)) {
+        return (x >> sh) + ((x >> (sh - 1)) & 1);
+    } else {
+        /* Rounding the sign bit always produces 0. */
+        return 0;
+    }
+}
+
 DO_VSHRN_ALL(vshrn, DO_SHR)
 DO_VSHRN_ALL(vrshrn, do_urshr)
+
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
+                                 bool *satp)
+{
+    if (val > max) {
+        *satp = true;
+        return max;
+    } else if (val < min) {
+        *satp = true;
+        return min;
+    } else {
+        return val;
+    }
+}
+
+/* Saturating narrowing right shifts */
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)   \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        LTYPE *m = vm;                                          \
+        TYPE *d = vd;                                           \
+        uint16_t mask = mve_element_mask(env);                  \
+        bool qc = false;                                        \
+        unsigned le;                                            \
+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
+            bool sat = false;                                   \
+            TYPE r = FN(m[H##LESIZE(le)], shift, &sat);         \
+            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
+            qc |= sat && (mask & 1 << (TOP * ESIZE));           \
+        }                                                       \
+        if (qc) {                                               \
+            env->vfp.qc[0] = qc;                                \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN)       \
+    DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
+
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN)      \
+    DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
+
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN)         \
+    DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
+
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN)        \
+    DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
+
+#define DO_SHRN_SB(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
+#define DO_SHRN_UB(N, M, SATP)                                  \
+    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
+#define DO_SHRUN_B(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
+
+#define DO_SHRN_SH(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
+#define DO_SHRN_UH(N, M, SATP)                                  \
+    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
+#define DO_SHRUN_H(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
+
+#define DO_RSHRN_SB(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
+#define DO_RSHRN_UB(N, M, SATP)                                 \
+    do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
+#define DO_RSHRUN_B(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
+
+#define DO_RSHRN_SH(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
+#define DO_RSHRN_UH(N, M, SATP)                                 \
+    do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
+#define DO_RSHRUN_H(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
+
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
+
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
 DO_2SHIFT_N(VSHRNT, vshrnt)
 DO_2SHIFT_N(VRSHRNB, vrshrnb)
 DO_2SHIFT_N(VRSHRNT, vrshrnt)
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
-- 
2.20.1

Implement the MVE VSHLC insn, which performs a shift left of the
entire vector with carry in bits provided from a general purpose
register and carry out bits written back to that register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  2 ++
 target/arm/mve.decode      |  2 ++
 target/arm/mve_helper.c    | 38 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
 4 files changed, 72 insertions(+)

Implement the MVE VADDLV insn; this is similar to VADDV, except
that it accumulates 32-bit elements into a 64-bit accumulator
stored in a pair of general-purpose registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  3 ++
 target/arm/mve.decode      |  6 +++-
 target/arm/mve_helper.c    | 19 ++++++++++++
 target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 90 insertions(+), 1 deletion(-)

The MVE extension to v8.1M includes some new shift instructions which
sit entirely within the non-coprocessor part of the encoding space
and which operate only on general-purpose registers.  They take up
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
with Rm == 13 or 15.

Implement the long shifts by immediate, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
an immediate shift count between 1 and 32.

Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
cases where v8.1M now requires that.  (Trying to change MOVS and ORRS
is too difficult, because the functions that generate the code are
shared between a dozen different kinds of arithmetic or logical
instruction for all A32, T16 and T32 encodings, and for some insns
and some encodings Rm==13,15 are valid.)

We make the helper functions we need for UQSHLL and SQSHLL take
a 32-bit value which the helper casts to int8_t because we'll need
these helpers also for the shift-by-register insns, where the shift
count might be < 0 or > 32.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  3 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 28 +++++++++++++
 target/arm/mve_helper.c | 10 +++++
 target/arm/translate.c  | 90 +++++++++++++++++++++++++++++++++++++++++
 5 files changed, 132 insertions(+)

Implement the MVE long shifts by register, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
the shift count in another general-purpose register, which might be
either positive or negative.

Like the long-shifts-by-immediate, these encodings sit in the space
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
we have to move the CSEL pattern into the same decodetree group.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  6 +++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 16 +++++--
 target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
 target/arm/translate.c  | 69 ++++++++++++++++++++++++++++++
 5 files changed, 182 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
 
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
 typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
 
 /**
  * arm_tbflags_from_tb:
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@
 &mcrr            !extern cp opc1 crm rt rt2
 
 &mve_shl_ri      rdalo rdahi shim
+&mve_shl_rr      rdalo rdahi rm
 
 # rdahi: bits [3:1] from insn, bit 0 is 1
 # rdalo: bits [3:1] from insn, bit 0 is 0
@@ -XXX,XX +XXX,XX @@
 
 @mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
                  &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
+@mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
+                 &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
 
 {
   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
     URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
     SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
     SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
+
+    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
+    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
+    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
+    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
+    UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
+    SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
   ]
 
   MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
   ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
+
+  # v8.1M CSEL and friends
+  CSEL           1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
 }
 {
   MVN_rxri       1110101 0011 . 1111 0 ... .... .... ....     @s_rxr_shi
@@ -XXX,XX +XXX,XX @@ SBC_rrri         1110101 1011 . .... 0 ... .... .... ....     @s_rrr_shi
 }
 RSB_rrri         1110101 1110 . .... 0 ... .... .... ....     @s_rrr_shi
 
-# v8.1M CSEL and friends
-CSEL             1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
-
 # Data-processing (register-shifted register)
 
 MOV_rxrr         1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
     return rdm;
 }
 
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
+}
+
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl_d(n, (int8_t)shift, false, NULL);
+}
+
 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 {
     return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 {
     return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
 }
+
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
+}
+
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
+}
+
+/* Operate on 64-bit values, but saturate at 48 bits */
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
+                                    bool round, uint32_t *sat)
+{
+    if (shift <= -48) {
+        /* Rounding the sign bit always produces 0. */
+        if (round) {
+            return 0;
+        }
+        return src >> 63;
+    } else if (shift < 0) {
+        if (round) {
+            src >>= -shift - 1;
+            return (src >> 1) + (src & 1);
+        }
+        return src >> -shift;
+    } else if (shift < 48) {
+        int64_t val = src << shift;
+        int64_t extval = sextract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (!sat || src == 0) {
+        return 0;
+    }
+
+    *sat = 1;
+    return (1ULL << 47) - (src >= 0);
+}
+
+/* Operate on 64-bit values, but saturate at 48 bits */
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
+                                     bool round, uint32_t *sat)
+{
+    uint64_t val, extval;
+
+    if (shift <= -(48 + round)) {
+        return 0;
+    } else if (shift < 0) {
+        if (round) {
+            val = src >> (-shift - 1);
+            val = (val >> 1) + (val & 1);
+        } else {
+            val = src >> -shift;
+        }
+        extval = extract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (shift < 48) {
+        uint64_t val = src << shift;
+        uint64_t extval = extract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (!sat || src == 0) {
+        return 0;
+    }
+
+    *sat = 1;
+    return MAKE_64BIT_MASK(0, 48);
+}
+
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
+}
+
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
     return do_mve_shl_ri(s, a, gen_urshr64_i64);
 }
 
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
+{
+    TCGv_i64 rda;
+    TCGv_i32 rdalo, rdahi;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
+        return false;
+    }
+    if (a->rdahi == 15) {
+        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
+        return false;
+    }
+    if (!dc_isar_feature(aa32_mve, s) ||
+        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
+        a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
+        a->rm == a->rdahi || a->rm == a->rdalo) {
+        /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
+        unallocated_encoding(s);
+        return true;
+    }
+
+    rda = tcg_temp_new_i64();
+    rdalo = load_reg(s, a->rdalo);
+    rdahi = load_reg(s, a->rdahi);
+    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
+
+    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
+    fn(rda, cpu_env, rda, cpu_R[a->rm]);
+
+    tcg_gen_extrl_i64_i32(rdalo, rda);
+    tcg_gen_extrh_i64_i32(rdahi, rda);
+    store_reg(s, a->rdalo, rdalo);
+    store_reg(s, a->rdahi, rdahi);
+    tcg_temp_free_i64(rda);
+
+    return true;
+}
+
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
+}
+
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
+}
+
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
+}
+
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
+}
+
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
+}
+
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
+}
+
 /*
  * Multiply and multiply accumulate
  */
-- 
2.20.1

Implement the MVE shifts by immediate, which perform shifts
on a single general-purpose register.

These patterns overlap with the long-shift-by-immediates,
so we have to rearrange the grouping a little here.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  3 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 31 ++++++++++++++-----
 target/arm/mve_helper.c | 10 ++++++
 target/arm/translate.c  | 68 +++++++++++++++++++++++++++++++++++++++--
 5 files changed, 104 insertions(+), 9 deletions(-)

Implement the MVE shifts by register, which perform
shifts on a single general-purpose register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  2 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 18 ++++++++++++++----
 target/arm/mve_helper.c | 10 ++++++++++
 target/arm/translate.c  | 30 ++++++++++++++++++++++++++++++
 5 files changed, 57 insertions(+), 4 deletions(-)

Here's another arm pullreq; nothing too exciting in here I think.

thanks
-- PMM

The following changes since commit 5fee33d97a7f2e95716417bd164f2f5264acd976:

Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu into staging (2024-04-29 14:34:25 -0700)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240430

for you to fetch changes up to a0c325c4b05cf7815739d6a84e567b95c8c5be7e:

tests/qtest : Add testcase for DM163 (2024-04-30 16:05:08 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/core/clock: allow clock_propagate on child clocks
 * hvf: arm: Remove unused PL1_WRITE_MASK define
 * target/arm: Restrict translation disabled alignment check to VMSA
 * docs/system/arm/emulation.rst: Add missing implemented features
 * target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max'
 * tests/avocado: update sunxi kernel from armbian to 6.6.16
 * target/arm: Make new CPUs default to 1GHz generic timer
 * hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
 * hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
 * hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
 * hw/arm: Add DM163 display to B-L475E-IOT01A board

----------------------------------------------------------------
Alexandra Diupina (1):
      hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields

Inès Varhol (5):
      hw/display : Add device DM163
      hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC
      hw/arm : Create Bl475eMachineState
      hw/arm : Connect DM163 to B-L475E-IOT01A
      tests/qtest : Add testcase for DM163

Peter Maydell (10):
      docs/system/arm/emulation.rst: Add missing implemented features
      target/arm: Enable FEAT_CSV2_3 for -cpu max
      target/arm: Enable FEAT_ETS2 for -cpu max
      target/arm: Implement ID_AA64MMFR3_EL1
      target/arm: Enable FEAT_Spec_FPACC for -cpu max
      tests/avocado: update sunxi kernel from armbian to 6.6.16
      target/arm: Refactor default generic timer frequency handling
      hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz
      hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property
      target/arm: Default to 1GHz cntfrq for 'max' and new CPUs

Philippe Mathieu-Daudé (1):
      hw/arm/npcm7xx: Store derivative OTP fuse key in little endian

Raphael Poggi (1):
      hw/core/clock: allow clock_propagate on child clocks

Richard Henderson (1):
      target/arm: Restrict translation disabled alignment check to VMSA

Thomas Huth (1):
      hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size

Zenghui Yu (1):
      hvf: arm: Remove PL1_WRITE_MASK

From: Raphael Poggi <raphael.poggi@lynxleap.co.uk>

clock_propagate() has an assert that clk->source is NULL, i.e. that
you are calling it on a clock which has no source clock.  This made
sense in the original design where the only way for a clock's
frequency to change if it had a source clock was when that source
clock changed.  However, we subsequently added multiplier/divider
support, but didn't look at what that meant for propagation.

If a clock-management device changes the multiplier or divider value
on a clock, it needs to propagate that change down to child clocks,
even if the clock has a source clock set.  So the assertion is now
incorrect.

Remove the assertion.

Signed-off-by: Raphael Poggi <raphael.poggi@lynxleap.co.uk>
Message-id: 20240419162951.23558-1-raphael.poggi@lynxleap.co.uk
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: Rewrote the commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/core/clock.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/core/clock.c b/hw/core/clock.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/clock.c
+++ b/hw/core/clock.c
@@ -XXX,XX +XXX,XX @@ static void clock_propagate_period(Clock *clk, bool call_callbacks)
 
 void clock_propagate(Clock *clk)
 {
-    assert(clk->source == NULL);
     trace_clock_propagate(CLOCK_PATH(clk));
     clock_propagate_period(clk, true);
 }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

For cpus using PMSA, when the MPU is disabled, the default memory
type is Normal, Non-cachable. This means that it should not
have alignment restrictions enforced.

Cc: qemu-stable@nongnu.org
Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled")
Reported-by: Clément Chigot <chigot@adacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Clément Chigot <chigot@adacore.com>
Message-id: 20240422170722.117409-1-richard.henderson@linaro.org
[PMM: trivial comment, commit message tweaks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/hflags.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/hflags.c
+++ b/target/arm/tcg/hflags.c
@@ -XXX,XX +XXX,XX @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr)
     }
 
     /*
-     * If translation is disabled, then the default memory type is
-     * Device(-nGnRnE) instead of Normal, which requires that alignment
+     * With PMSA, when the MPU is disabled, all memory types in the
+     * default map are Normal, so don't need aligment enforcing.
+     */
+    if (arm_feature(env, ARM_FEATURE_PMSA)) {
+        return false;
+    }
+
+    /*
+     * With VMSA, if translation is disabled, then the default memory type
+     * is Device(-nGnRnE) instead of Normal, which requires that alignment
      * be enforced.  Since this affects all ram, it is most efficient
      * to handle this during translation.
      */
-- 
2.34.1

As of version DDI0487K.a of the Arm ARM, some architectural features
which previously didn't have official names have been named.  Add
these to the list of features which QEMU's TCG emulation supports.
Mostly these are features which we thought of as part of baseline 8.0
support.  For SVE and SVE2, the names have been brought into line
with the FEAT_* naming convention of other extensions, and some
sub-components split into separate FEAT_ items.  In a few cases (eg
FEAT_CCIDX, FEAT_DPB2) the omission from our list was just an oversight.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240418152004.2106516-2-peter.maydell@linaro.org
---
 docs/system/arm/emulation.rst | 38 +++++++++++++++++++++++++++++++++--
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ Armv8 versions of the A-profile architecture. It also has support for
 the following architecture extensions:
 
 - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
+- FEAT_AA32EL0 (Support for AArch32 at EL0)
+- FEAT_AA32EL1 (Support for AArch32 at EL1)
+- FEAT_AA32EL2 (Support for AArch32 at EL2)
+- FEAT_AA32EL3 (Support for AArch32 at EL3)
 - FEAT_AA32HPD (AArch32 hierarchical permission disables)
 - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
+- FEAT_AA64EL0 (Support for AArch64 at EL0)
+- FEAT_AA64EL1 (Support for AArch64 at EL1)
+- FEAT_AA64EL2 (Support for AArch64 at EL2)
+- FEAT_AA64EL3 (Support for AArch64 at EL3)
+- FEAT_AdvSIMD (Advanced SIMD Extension)
 - FEAT_AES (AESD and AESE instructions)
+- FEAT_Armv9_Crypto (Armv9 Cryptographic Extension)
+- FEAT_ASID16 (16 bit ASID)
 - FEAT_BBM at level 2 (Translation table break-before-make levels)
 - FEAT_BF16 (AArch64 BFloat16 instructions)
 - FEAT_BTI (Branch Target Identification)
+- FEAT_CCIDX (Extended cache index)
 - FEAT_CRC32 (CRC32 instructions)
+- FEAT_Crypto (Cryptographic Extension)
 - FEAT_CSV2 (Cache speculation variant 2)
 - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
 - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_DGH (Data gathering hint)
 - FEAT_DIT (Data Independent Timing instructions)
 - FEAT_DPB (DC CVAP instruction)
+- FEAT_DPB2 (DC CVADP instruction)
+- FEAT_Debugv8p1 (Debug with VHE)
 - FEAT_Debugv8p2 (Debug changes for v8.2)
 - FEAT_Debugv8p4 (Debug changes for v8.4)
 - FEAT_DotProd (Advanced SIMD dot product instructions)
 - FEAT_DoubleFault (Double Fault Extension)
 - FEAT_E0PD (Preventing EL0 access to halves of address maps)
 - FEAT_ECV (Enhanced Counter Virtualization)
+- FEAT_EL0 (Support for execution at EL0)
+- FEAT_EL1 (Support for execution at EL1)
+- FEAT_EL2 (Support for execution at EL2)
+- FEAT_EL3 (Support for execution at EL3)
 - FEAT_EPAC (Enhanced pointer authentication)
 - FEAT_ETS (Enhanced Translation Synchronization)
 - FEAT_EVT (Enhanced Virtualization Traps)
+- FEAT_F32MM (Single-precision Matrix Multiplication)
+- FEAT_F64MM (Double-precision Matrix Multiplication)
 - FEAT_FCMA (Floating-point complex number instructions)
 - FEAT_FGT (Fine-Grained Traps)
 - FEAT_FHM (Floating-point half-precision multiplication instructions)
+- FEAT_FP (Floating Point extensions)
 - FEAT_FP16 (Half-precision floating-point data processing)
 - FEAT_FPAC (Faulting on AUT* instructions)
 - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_LSE (Large System Extensions)
 - FEAT_LSE2 (Large System Extensions v2)
 - FEAT_LVA (Large Virtual Address space)
+- FEAT_MixedEnd (Mixed-endian support)
+- FEAT_MixdEndEL0 (Mixed-endian support at EL0)
 - FEAT_MOPS (Standardization of memory operations)
 - FEAT_MTE (Memory Tagging Extension)
 - FEAT_MTE2 (Memory Tagging Extension)
 - FEAT_MTE3 (MTE Asymmetric Fault Handling)
+- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
 - FEAT_NMI (Non-maskable Interrupt)
 - FEAT_NV (Nested Virtualization)
 - FEAT_NV2 (Enhanced nested virtualization support)
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_PAuth (Pointer authentication)
 - FEAT_PAuth2 (Enhancements to pointer authentication)
 - FEAT_PMULL (PMULL, PMULL2 instructions)
+- FEAT_PMUv3 (PMU extension version 3)
 - FEAT_PMUv3p1 (PMU Extensions v3.1)
 - FEAT_PMUv3p4 (PMU Extensions v3.4)
 - FEAT_PMUv3p5 (PMU Extensions v3.5)
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
 - FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
 - FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
+- FEAT_SVE (Scalable Vector Extension)
+- FEAT_SVE_AES (Scalable Vector AES instructions)
+- FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions)
+- FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions)
+- FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions)
+- FEAT_SVE_SM4 (Scalable Vector SM4 instructions)
+- FEAT_SVE2 (Scalable Vector Extension version 2)
 - FEAT_SPECRES (Speculation restriction instructions)
 - FEAT_SSBS (Speculative Store Bypass Safe)
+- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1)
+- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1)
+- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1)
 - FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality)
 - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
 - FEAT_TLBIRANGE (TLB invalidate range instructions)
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_VHE (Virtualization Host Extensions)
 - FEAT_VMID16 (16-bit VMID)
 - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
-- SVE (The Scalable Vector Extension)
-- SVE2 (The Scalable Vector Extension v2)
 
 For information on the specifics of these extensions, please refer
 to the `Armv8-A Arm Architecture Reference Manual
-- 
2.34.1

FEAT_CSV2_3 adds a mechanism to identify if hardware cannot disclose
information about whether branch targets and branch history trained
in one hardware described context can control speculative execution
in a different hardware context.

There is no branch prediction in TCG, so we don't need to do anything
to be compliant with this.  Upadte the '-cpu max' ID registers to
advertise the feature.

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
 - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
 - FEAT_CSV2_2 (Cache speculation variant 2, version 2)
+- FEAT_CSV2_3 (Cache speculation variant 2, version 3)
 - FEAT_CSV3 (Cache speculation variant 3)
 - FEAT_DGH (Data gathering hint)
 - FEAT_DIT (Data Independent Timing instructions)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
     t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);      /* FEAT_SEL2 */
     t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);       /* FEAT_DIT */
-    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2);      /* FEAT_CSV2_2 */
+    t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 3);      /* FEAT_CSV2_3 */
     t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1);      /* FEAT_CSV3 */
     cpu->isar.id_aa64pfr0 = t;
 
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);       /* FEAT_MTE3 */
     t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0);  /* FEAT_RASv1p1 + FEAT_DoubleFault */
     t = FIELD_DP64(t, ID_AA64PFR1, SME, 1);       /* FEAT_SME */
-    t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
+    t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */
     t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1);       /* FEAT_NMI */
     cpu->isar.id_aa64pfr1 = t;
 
-- 
2.34.1

FEAT_ETS2 is a tighter set of guarantees about memory ordering
involving translation table walks than the old FEAT_ETS; FEAT_ETS has
been retired from the Arm ARM and the old ID_AA64MMFR1.ETS == 1
now gives no greater guarantees than ETS == 0.

FEAT_ETS2 requires:
 * the virtual address of a load or store that appears in program
   order after a DSB cannot be translated until after the DSB
   completes (section B2.10.9)
 * TLB maintenance operations that only affect translations without
   execute permission are guaranteed complete after a DSB
   (R_BLDZX)
 * if a memory access RW2 is ordered-before memory access RW2,
   then RW1 is also ordered-before any translation table walk
   generated by RW2 that generates a Translation, Address size
   or Access flag fault (R_NNFPF, I_CLGHP)

As with FEAT_ETS, QEMU is already compliant, because we do not
reorder translation table walk memory accesses relative to other
memory accesses, and we always guarantee to have finished TLB
maintenance as soon as the TLB op is done.

Update the documentation to list FEAT_ETS2 instead of the
no-longer-existent FEAT_ETS, and update the 'max' CPU ID registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240418152004.2106516-4-peter.maydell@linaro.org
---
 docs/system/arm/emulation.rst | 2 +-
 target/arm/tcg/cpu32.c        | 2 +-
 target/arm/tcg/cpu64.c        | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_EL2 (Support for execution at EL2)
 - FEAT_EL3 (Support for execution at EL3)
 - FEAT_EPAC (Enhanced pointer authentication)
-- FEAT_ETS (Enhanced Translation Synchronization)
+- FEAT_ETS2 (Enhanced Translation Synchronization)
 - FEAT_EVT (Enhanced Virtualization Traps)
 - FEAT_F32MM (Single-precision Matrix Multiplication)
 - FEAT_F64MM (Double-precision Matrix Multiplication)
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
     cpu->isar.id_mmfr4 = t;
 
     t = cpu->isar.id_mmfr5;
-    t = FIELD_DP32(t, ID_MMFR5, ETS, 1);          /* FEAT_ETS */
+    t = FIELD_DP32(t, ID_MMFR5, ETS, 2);          /* FEAT_ETS2 */
     cpu->isar.id_mmfr5 = t;
 
     t = cpu->isar.id_pfr0;
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
     t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
-    t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1);      /* FEAT_ETS */
+    t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 2);      /* FEAT_ETS2 */
     t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1);      /* FEAT_HCX */
     t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1);   /* FEAT_TIDCP1 */
     cpu->isar.id_aa64mmfr1 = t;
-- 
2.34.1

Newer versions of the Arm ARM (e.g.  rev K.a) now define fields for
ID_AA64MMFR3_EL1.  Implement this register, so that we can set the
fields if we need to.  There's no behaviour change here since we
don't currently set the register value to non-zero.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240418152004.2106516-5-peter.maydell@linaro.org
---
 target/arm/cpu.h     | 17 +++++++++++++++++
 target/arm/helper.c  |  6 ++++--
 target/arm/hvf/hvf.c |  2 ++
 target/arm/kvm.c     |  2 ++
 4 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
         uint64_t id_aa64mmfr0;
         uint64_t id_aa64mmfr1;
         uint64_t id_aa64mmfr2;
+        uint64_t id_aa64mmfr3;
         uint64_t id_aa64dfr0;
         uint64_t id_aa64dfr1;
         uint64_t id_aa64zfr0;
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR2, BBM, 52, 4)
 FIELD(ID_AA64MMFR2, EVT, 56, 4)
 FIELD(ID_AA64MMFR2, E0PD, 60, 4)
 
+FIELD(ID_AA64MMFR3, TCRX, 0, 4)
+FIELD(ID_AA64MMFR3, SCTLRX, 4, 4)
+FIELD(ID_AA64MMFR3, S1PIE, 8, 4)
+FIELD(ID_AA64MMFR3, S2PIE, 12, 4)
+FIELD(ID_AA64MMFR3, S1POE, 16, 4)
+FIELD(ID_AA64MMFR3, S2POE, 20, 4)
+FIELD(ID_AA64MMFR3, AIE, 24, 4)
+FIELD(ID_AA64MMFR3, MEC, 28, 4)
+FIELD(ID_AA64MMFR3, D128, 32, 4)
+FIELD(ID_AA64MMFR3, D128_2, 36, 4)
+FIELD(ID_AA64MMFR3, SNERR, 40, 4)
+FIELD(ID_AA64MMFR3, ANERR, 44, 4)
+FIELD(ID_AA64MMFR3, SDERR, 52, 4)
+FIELD(ID_AA64MMFR3, ADERR, 56, 4)
+FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4)
+
 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa64_tid3,
               .resetvalue = cpu->isar.id_aa64mmfr2 },
-            { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
+            { .name = "ID_AA64MMFR3_EL1", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa64_tid3,
-              .resetvalue = 0 },
+              .resetvalue = cpu->isar.id_aa64mmfr3 },
             { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
               .access = PL1_R, .type = ARM_CP_CONST,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .exported_bits = R_ID_AA64MMFR1_AFP_MASK },
             { .name = "ID_AA64MMFR2_EL1",
               .exported_bits = R_ID_AA64MMFR2_AT_MASK },
+            { .name = "ID_AA64MMFR3_EL1",
+              .exported_bits = 0 },
             { .name = "ID_AA64MMFR*_EL1_RESERVED",
               .is_glob = true },
             { .name = "ID_AA64DFR0_EL1",
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@ static struct hvf_sreg_match hvf_sreg_match[] = {
 #endif
     { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) },
     { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) },
+    /* Add ID_AA64MMFR3_EL1 here when HVF supports it */
 
     { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) },
     { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) },
@@ -XXX,XX +XXX,XX @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
         { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
         { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
         { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },
+        /* Add ID_AA64MMFR3_EL1 here when HVF supports it */
     };
     hv_vcpu_t fd;
     hv_return_t r = HV_SUCCESS;
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
                               ARM64_SYS_REG(3, 0, 0, 7, 1));
         err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
                               ARM64_SYS_REG(3, 0, 0, 7, 2));
+        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3,
+                              ARM64_SYS_REG(3, 0, 0, 7, 3));
 
         /*
          * Note that if AArch32 support is not present in the host,
-- 
2.34.1

FEAT_Spec_FPACC is a feature describing speculative behaviour in the
event of a PAC authontication failure when FEAT_FPACCOMBINE is
implemented.  FEAT_Spec_FPACC means that the speculative use of
pointers processed by a PAC Authentication is not materially
different in terms of the impact on cached microarchitectural state
(caches, TLBs, etc) between passing and failing of the PAC
Authentication.

QEMU doesn't do speculative execution, so we can advertise
this feature.

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_FP16 (Half-precision floating-point data processing)
 - FEAT_FPAC (Faulting on AUT* instructions)
 - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
+- FEAT_FPACC_SPEC (Speculative behavior of combined pointer authentication instructions)
 - FEAT_FRINTTS (Floating-point to integer instructions)
 - FEAT_FlagM (Flag manipulation instructions v2)
 - FEAT_FlagM2 (Enhancements to flag manipulation instructions)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1);     /* FEAT_E0PD */
     cpu->isar.id_aa64mmfr2 = t;
 
+    t = cpu->isar.id_aa64mmfr3;
+    t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
+    cpu->isar.id_aa64mmfr3 = t;
+
     t = cpu->isar.id_aa64zfr0;
     t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
     t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2);       /* FEAT_SVE_PMULL128 */
-- 
2.34.1

The Linux kernel 5.10.16 binary for sunxi has been removed from
apt.armbian.com. This means that the avocado tests for these machines
will be skipped (status CANCEL) if the old binary isn't present in
the avocado cache.

Update to 6.6.16, in the same way we did in commit e384db41d8661
when we moved to 5.10.16 in 2021.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2284
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20240415151845.1564201-1-peter.maydell@linaro.org
---
 tests/avocado/boot_linux_console.py | 70 ++++++++++++++---------------
 tests/avocado/replay_kernel.py      |  8 ++--
 2 files changed, 39 insertions(+), 39 deletions(-)

diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
         :avocado: tags=accel:tcg
         """
         deb_url = ('https://apt.armbian.com/pool/main/l/'
-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
         initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
                       '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self):
         :avocado: tags=accel:tcg
         """
         deb_url = ('https://apt.armbian.com/pool/main/l/'
-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
         rootfs_url = ('https://github.com/groeck/linux-build-test/raw/'
                       '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u(self):
         :avocado: tags=machine:bpim2u
         :avocado: tags=accel:tcg
         """
-        deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
-                   'linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+        deb_url = ('https://apt.armbian.com/pool/main/l/'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = ('/usr/lib/linux-image-current-sunxi/'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
                     'sun8i-r40-bananapi-m2-ultra.dtb')
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
 
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u_initrd(self):
         :avocado: tags=accel:tcg
         :avocado: tags=machine:bpim2u
         """
-        deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
-                   'linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+        deb_url = ('https://apt.armbian.com/pool/main/l/'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = ('/usr/lib/linux-image-current-sunxi/'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
                     'sun8i-r40-bananapi-m2-ultra.dtb')
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
         initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u_gmac(self):
         """
         self.require_netdev('user')
 
-        deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
-                   'linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+        deb_url = ('https://apt.armbian.com/pool/main/l/'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = ('/usr/lib/linux-image-current-sunxi/'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
                     'sun8i-r40-bananapi-m2-ultra.dtb')
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
         rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi(self):
         :avocado: tags=accel:tcg
         """
         deb_url = ('https://apt.armbian.com/pool/main/l/'
-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
 
         self.vm.set_console()
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_initrd(self):
         :avocado: tags=machine:orangepi-pc
         """
         deb_url = ('https://apt.armbian.com/pool/main/l/'
-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
         initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
                       '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_sd(self):
         self.require_netdev('user')
 
         deb_url = ('https://apt.armbian.com/pool/main/l/'
-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
         rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
                       'buildroot-baseline/20221116.0/armel/rootfs.ext2.xz')
diff --git a/tests/avocado/replay_kernel.py b/tests/avocado/replay_kernel.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/replay_kernel.py
+++ b/tests/avocado/replay_kernel.py
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
         :avocado: tags=machine:cubieboard
         """
         deb_url = ('https://apt.armbian.com/pool/main/l/'
-                   'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
-        deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
+                   'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
+        deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
         kernel_path = self.extract_from_deb(deb_path,
-                                            '/boot/vmlinuz-5.10.16-sunxi')
-        dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
+                                            '/boot/vmlinuz-6.6.16-current-sunxi')
+        dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
         dtb_path = self.extract_from_deb(deb_path, dtb_path)
         initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
                       '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
-- 
2.34.1

The generic timer frequency is settable by board code via a QOM
property "cntfrq", but otherwise defaults to 62.5MHz.  The way this
is done includes some complication resulting from how this was
originally a fixed value with no QOM property.  Clean it up:

* always set cpu->gt_cntfrq_hz to some sensible value, whether
   the CPU has the generic timer or not, and whether it's system
   or user-only emulation
 * this means we can always use gt_cntfrq_hz, and never need
   the old GTIMER_SCALE define
 * set the default value in exactly one place, in the realize fn

The aim here is to pave the way for handling the ARMv8.6 requirement
that the generic timer frequency is always 1GHz.  We're going to do
that by having old CPU types keep their legacy-in-QEMU behaviour and
having the default for any new CPU types be a 1GHz rather han 62.5MHz
cntfrq, so we want the point where the default is decided to be in
one place, and in code, not in a DEFINE_PROP_UINT64() initializer.

This commit should have no behavioural changes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240426122913.3427983-2-peter.maydell@linaro.org
---
 target/arm/internals.h |  7 ++++---
 target/arm/cpu.c       | 31 +++++++++++++++++--------------
 target/arm/helper.c    | 16 ++++++++--------
 3 files changed, 29 insertions(+), 25 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
         || excp == EXCP_SEMIHOST;
 }
 
-/* Scale factor for generic timers, ie number of ns per tick.
- * This gives a 62.5MHz timer.
+/*
+ * Default frequency for the generic timer, in Hz.
+ * This is 62.5MHz, which gives a 16 ns tick period.
  */
-#define GTIMER_SCALE 16
+#define GTIMER_DEFAULT_HZ 62500000
 
 /* Bit definitions for the v7M CONTROL register */
 FIELD(V7M_CONTROL, NPRIV, 0, 1)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
     }
 }
 
+/*
+ * 0 means "unset, use the default value". That default might vary depending
+ * on the CPU type, and is set in the realize fn.
+ */
 static Property arm_cpu_gt_cntfrq_property =
-            DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz,
-                               NANOSECONDS_PER_SECOND / GTIMER_SCALE);
+            DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0);
 
 static Property arm_cpu_reset_cbar_property =
             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         return;
     }
 
+    if (!cpu->gt_cntfrq_hz) {
+        /*
+         * 0 means "the board didn't set a value, use the default".
+         * The default value of the generic timer frequency (as seen in
+         * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns.
+         * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the
+         * board doesn't set it.
+         */
+        cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
+    }
+
 #ifndef CONFIG_USER_ONLY
     /* The NVIC and M-profile CPU are two halves of a single piece of
      * hardware; trying to use one without the other is a command line
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
 
     {
-        uint64_t scale;
-
-        if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
-            if (!cpu->gt_cntfrq_hz) {
-                error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
-                           cpu->gt_cntfrq_hz);
-                return;
-            }
-            scale = gt_cntfrq_period_ns(cpu);
-        } else {
-            scale = GTIMER_SCALE;
-        }
+        uint64_t scale = gt_cntfrq_period_ns(cpu);
 
         cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
                                                arm_gt_ptimer_cb, cpu);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
       .resetvalue = 0 },
 };
 
+static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
+{
+    ARMCPU *cpu = env_archcpu(env);
+
+    cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
+}
+
 #ifndef CONFIG_USER_ONLY
 
 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ void arm_gt_hvtimer_cb(void *opaque)
     gt_recalc_timer(cpu, GTIMER_HYPVIRT);
 }
 
-static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
-{
-    ARMCPU *cpu = env_archcpu(env);
-
-    cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
-}
-
 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
     /*
      * Note that CNTFRQ is purely reads-as-written for the benefit
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
       .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */,
       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
-      .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE,
+      .resetfn = arm_gt_cntfrq_reset,
     },
     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
-- 
2.34.1

Currently QEMU CPUs always run with a generic timer counter frequency
of 62.5MHz, but ARMv8.6 CPUs will run at 1GHz.  For older versions of
the TF-A firmware that sbsa-ref runs, the frequency of the generic
timer is hardcoded into the firmware, and so if the CPU actually has
a different frequency then timers in the guest will be set
incorrectly.

The default frequency used by the 'max' CPU is about to change, so
make the sbsa-ref board force the CPU frequency to the value which
the firmware expects.

Newer versions of TF-A will read the frequency from the CPU's
CNTFRQ_EL0 register:
 https://github.com/ARM-software/arm-trusted-firmware/commit/4c77fac98dac0bebc63798aae9101ac865b87148
so in the longer term we could make this board use the 1GHz
frequency. We will need to make sure we update the binaries used
by our avocado test
 Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef
before we can do that.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Message-id: 20240426122913.3427983-3-peter.maydell@linaro.org
---
 hw/arm/sbsa-ref.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@
 #define NUM_SMMU_IRQS   4
 #define NUM_SATA_PORTS  6
 
+/*
+ * Generic timer frequency in Hz (which drives both the CPU generic timers
+ * and the SBSA watchdog-timer). Older versions of the TF-A firmware
+ * typically used with sbsa-ref (including the binaries in our Avocado test
+ * Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef
+ * assume it is this value.
+ *
+ * TODO: this value is not architecturally correct for an Armv8.6 or
+ * better CPU, so we should move to 1GHz once the TF-A fix above has
+ * made it into a release and into our Avocado test.
+ */
+#define SBSA_GTIMER_HZ 62500000
+
 enum {
     SBSA_FLASH,
     SBSA_MEM,
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
                                     &error_abort);
         }
 
+        object_property_set_int(cpuobj, "cntfrq", SBSA_GTIMER_HZ, &error_abort);
+
         object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
                                  &error_abort);
 
-- 
2.34.1

Currently the sbsa_gdwt watchdog device hardcodes its frequency at
62.5MHz. In real hardware, this watchdog is supposed to be driven
from the system counter, which also drives the CPU generic timers.
Newer CPU types (in particular from Armv8.6) should have a CPU
generic timer frequency of 1GHz, so we can't leave the watchdog
on the old QEMU default of 62.5GHz.

Make the frequency a QOM property so it can be set by the board,
and have our only board that uses this device set that frequency
to the same value it sets the CPU frequency.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240426122913.3427983-4-peter.maydell@linaro.org
---
 include/hw/watchdog/sbsa_gwdt.h |  3 +--
 hw/arm/sbsa-ref.c               |  1 +
 hw/watchdog/sbsa_gwdt.c         | 15 ++++++++++++++-
 3 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/include/hw/watchdog/sbsa_gwdt.h b/include/hw/watchdog/sbsa_gwdt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/watchdog/sbsa_gwdt.h
+++ b/include/hw/watchdog/sbsa_gwdt.h
@@ -XXX,XX +XXX,XX @@
 #define SBSA_GWDT_RMMIO_SIZE 0x1000
 #define SBSA_GWDT_CMMIO_SIZE 0x1000
 
-#define SBSA_TIMER_FREQ      62500000 /* Hz */
-
 typedef struct SBSA_GWDTState {
     /* <private> */
     SysBusDevice parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct SBSA_GWDTState {
     qemu_irq irq;
 
     QEMUTimer *timer;
+    uint64_t freq;
 
     uint32_t id;
     uint32_t wcs;
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static void create_wdt(const SBSAMachineState *sms)
     SysBusDevice *s = SYS_BUS_DEVICE(dev);
     int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0];
 
+    qdev_prop_set_uint64(dev, "clock-frequency", SBSA_GTIMER_HZ);
     sysbus_realize_and_unref(s, &error_fatal);
     sysbus_mmio_map(s, 0, rbase);
     sysbus_mmio_map(s, 1, cbase);
diff --git a/hw/watchdog/sbsa_gwdt.c b/hw/watchdog/sbsa_gwdt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/watchdog/sbsa_gwdt.c
+++ b/hw/watchdog/sbsa_gwdt.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "sysemu/reset.h"
 #include "sysemu/watchdog.h"
+#include "hw/qdev-properties.h"
 #include "hw/watchdog/sbsa_gwdt.h"
 #include "qemu/timer.h"
 #include "migration/vmstate.h"
@@ -XXX,XX +XXX,XX @@ static void sbsa_gwdt_update_timer(SBSA_GWDTState *s, WdtRefreshType rtype)
         timeout = s->woru;
         timeout <<= 32;
         timeout |= s->worl;
-        timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, SBSA_TIMER_FREQ);
+        timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, s->freq);
         timeout += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 
         if ((rtype == EXPLICIT_REFRESH) || ((rtype == TIMEOUT_REFRESH) &&
@@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_realize(DeviceState *dev, Error **errp)
                 dev);
 }
 
+static Property wdt_sbsa_gwdt_props[] = {
+    /*
+     * Timer frequency in Hz. This must match the frequency used by
+     * the CPU's generic timer. Default 62.5Hz matches QEMU's legacy
+     * CPU timer frequency default.
+     */
+    DEFINE_PROP_UINT64("clock-frequency", struct SBSA_GWDTState, freq,
+                       62500000),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
 static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
     set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
     dc->vmsd = &vmstate_sbsa_gwdt;
     dc->desc = "SBSA-compliant generic watchdog device";
+    device_class_set_props(dc, wdt_sbsa_gwdt_props);
 }
 
 static const TypeInfo wdt_sbsa_gwdt_info = {
-- 
2.34.1

In previous versions of the Arm architecture, the frequency of the
generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
In Armv8.6, the architecture standardized this frequency to 1GHz.

Because there is no ID register feature field that indicates whether
a CPU is v8.6 or that it ought to have this counter frequency, we
implement this by changing our default CNTFRQ value for all CPUs,
with exceptions for backwards compatibility:

* CPU types which we already implement will retain the old
   default value. None of these are v8.6 CPUs, so this is
   architecturally OK.
 * CPUs used in versioned machine types with a version of 9.0
   or earlier will retain the old default value.

The upshot is that the only CPU type that changes is 'max'; but any
new type we add in future (whether v8.6 or not) will also get the new
1GHz default.

It remains the case that the machine model can override the default
value via the 'cntfrq' QOM property (regardless of the CPU type).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240426122913.3427983-5-peter.maydell@linaro.org
---
 target/arm/cpu.h       | 11 +++++++++++
 target/arm/internals.h | 12 ++++++++++--
 hw/core/machine.c      |  4 +++-
 target/arm/cpu.c       | 23 +++++++++++++++++------
 target/arm/cpu64.c     |  2 ++
 target/arm/tcg/cpu32.c |  4 ++++
 target/arm/tcg/cpu64.c | 18 ++++++++++++++++++
 7 files changed, 65 insertions(+), 9 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
      */
     bool host_cpu_probe_failed;
 
+    /* QOM property to indicate we should use the back-compat CNTFRQ default */
+    bool backcompat_cntfrq;
+
     /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
      * register.
      */
@@ -XXX,XX +XXX,XX @@ enum arm_features {
     ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
     ARM_FEATURE_M_MAIN, /* M profile Main Extension */
     ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
+    /*
+     * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz
+     * if the board doesn't set a value, instead of 1GHz. It is for backwards
+     * compatibility and used only with CPU definitions that were already
+     * in QEMU before we changed the default. It should not be set on any
+     * CPU types added in future.
+     */
+    ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
 };
 
 static inline int arm_feature(CPUARMState *env, int feature)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
 
 /*
  * Default frequency for the generic timer, in Hz.
- * This is 62.5MHz, which gives a 16 ns tick period.
+ * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
+ * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
+ * which gives a 16ns tick period.
+ *
+ * We will use the back-compat value:
+ *  - for QEMU CPU types added before we standardized on 1GHz
+ *  - for versioned machine types with a version of 9.0 or earlier
+ * In any case, the machine model may override via the cntfrq property.
  */
-#define GTIMER_DEFAULT_HZ 62500000
+#define GTIMER_DEFAULT_HZ 1000000000
+#define GTIMER_BACKCOMPAT_HZ 62500000
 
 /* Bit definitions for the v7M CONTROL register */
 FIELD(V7M_CONTROL, NPRIV, 0, 1)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/virtio/virtio-iommu.h"
 #include "audio/audio.h"
 
-GlobalProperty hw_compat_9_0[] = {};
+GlobalProperty hw_compat_9_0[] = {
+    {"arm-cpu", "backcompat-cntfrq", "true" },
+};
 const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0);
 
 GlobalProperty hw_compat_8_2[] = {
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 
     if (!cpu->gt_cntfrq_hz) {
         /*
-         * 0 means "the board didn't set a value, use the default".
-         * The default value of the generic timer frequency (as seen in
-         * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns.
-         * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the
-         * board doesn't set it.
+         * 0 means "the board didn't set a value, use the default". (We also
+         * get here for the CONFIG_USER_ONLY case.)
+         * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
+         * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
+         * which gives a 16ns tick period.
+         *
+         * We will use the back-compat value:
+         *  - for QEMU CPU types added before we standardized on 1GHz
+         *  - for versioned machine types with a version of 9.0 or earlier
          */
-        cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
+        if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) ||
+            cpu->backcompat_cntfrq) {
+            cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
+        } else {
+            cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
+        }
     }
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_properties[] = {
                         mp_affinity, ARM64_AFFINITY_INVALID),
     DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
     DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
+    /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */
+    DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false),
     DEFINE_PROP_END_OF_LIST()
 };
 
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_PMSA);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
     cpu->midr = 0x411fd133; /* r1p3 */
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a55_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n1_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_a710_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n2_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     uint64_t t;
     uint32_t u;
 
+    /*
+     * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default
+     * to because we started with aarch64_a57_initfn(). A 'max' CPU might
+     * be a v8.6-or-later one, in which case the cntfrq must be 1GHz; and
+     * because it is our "may change" CPU type we are OK with it not being
+     * backwards-compatible with how it worked in old QEMU.
+     */
+    unset_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
+
     /*
      * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
      * one and try to apply errata workarounds or use impdef features we
-- 
2.34.1

From: Alexandra Diupina <adiupina@astralinux.ru>

The DMA descriptor structures for this device have
a set of "address extension" fields which extend the 32
bit source addresses with an extra 16 bits to give a
48 bit address:
 https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field

However, we misimplemented this address extension in several ways:
 * we only extracted 12 bits of the extension fields, not 16
 * we didn't shift the extension field up far enough
 * we accidentally did the shift as 32-bit arithmetic, which
   meant that we would have an overflow instead of setting
   bits [47:32] of the resulting 64-bit address

Add a type cast and use extract64() instead of extract32()
to avoid integer overflow on addition. Fix bit fields
extraction according to documentation.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Cc: qemu-stable@nongnu.org
Fixes: d3c6369a96 ("introduce xlnx-dpdma")
Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
Message-id: 20240428181131.23801-1-adiupina@astralinux.ru
[PMM: adjusted commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/dma/xlnx_dpdma.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/xlnx_dpdma.c
+++ b/hw/dma/xlnx_dpdma.c
@@ -XXX,XX +XXX,XX @@ static uint64_t xlnx_dpdma_desc_get_source_address(DPDMADescriptor *desc,
 
     switch (frag) {
     case 0:
-        addr = desc->source_address
-            + (extract32(desc->address_extension, 16, 12) << 20);
+        addr = (uint64_t)desc->source_address
+            + (extract64(desc->address_extension, 16, 16) << 32);
         break;
     case 1:
-        addr = desc->source_address2
-            + (extract32(desc->address_extension_23, 0, 12) << 8);
+        addr = (uint64_t)desc->source_address2
+            + (extract64(desc->address_extension_23, 0, 16) << 32);
         break;
     case 2:
-        addr = desc->source_address3
-            + (extract32(desc->address_extension_23, 16, 12) << 20);
+        addr = (uint64_t)desc->source_address3
+            + (extract64(desc->address_extension_23, 16, 16) << 32);
         break;
     case 3:
-        addr = desc->source_address4
-            + (extract32(desc->address_extension_45, 0, 12) << 8);
+        addr = (uint64_t)desc->source_address4
+            + (extract64(desc->address_extension_45, 0, 16) << 32);
         break;
     case 4:
-        addr = desc->source_address5
-            + (extract32(desc->address_extension_45, 16, 12) << 20);
+        addr = (uint64_t)desc->source_address5
+            + (extract64(desc->address_extension_45, 16, 16) << 32);
         break;
     default:
         addr = 0;
-- 
2.34.1

From: Thomas Huth <thuth@redhat.com>

"make check-qtest-aarch64" recently started failing on FreeBSD builds,
and valgrind on Linux also detected that there is something fishy with
the new stm32l4x5-usart: The code forgot to set the correct class_size
here, so the various class_init functions in this file wrote beyond
the allocated buffer when setting the subc->type field.

Fixes: 4fb37aea7e ("hw/char: Implement STM32L4x5 USART skeleton")
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240429075908.36302-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/stm32l4x5_usart.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/stm32l4x5_usart.c
+++ b/hw/char/stm32l4x5_usart.c
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stm32l4x5_usart_types[] = {
         .parent         = TYPE_SYS_BUS_DEVICE,
         .instance_size  = sizeof(Stm32l4x5UsartBaseState),
         .instance_init  = stm32l4x5_usart_base_init,
+        .class_size     = sizeof(Stm32l4x5UsartBaseClass),
         .class_init     = stm32l4x5_usart_base_class_init,
         .abstract       = true,
     }, {
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Use little endian for derivative OTP fuse key.

Cc: qemu-stable@nongnu.org
Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model")
Suggested-by: Avi Fishman <Avi.Fishman@nuvoton.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240422125813.1403-1-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/npcm7xx.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
 #include "qapi/error.h"
+#include "qemu/bswap.h"
 #include "qemu/units.h"
 #include "sysemu/sysemu.h"
 #include "target/arm/cpu-qom.h"
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
      * The initial mask of disabled modules indicates the chip derivative (e.g.
      * NPCM750 or NPCM730).
      */
-    value = tswap32(nc->disabled_modules);
+    value = cpu_to_le32(nc->disabled_modules);
     npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
                             sizeof(value));
 }
-- 
2.34.1

From: Inès Varhol <ines.varhol@telecom-paris.fr>

This device implements the IM120417002 colors shield v1.1 for Arduino
(which relies on the DM163 8x3-channel led driving logic) and features
a simple display of an 8x8 RGB matrix. The columns of the matrix are
driven by the DM163 and the rows are driven externally.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-2-ines.varhol@telecom-paris.fr
[PMM: updated to new reset hold method prototype]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/b-l475e-iot01a.rst |   3 +-
 include/hw/display/dm163.h         |  59 +++++
 hw/display/dm163.c                 | 349 +++++++++++++++++++++++++++++
 hw/display/Kconfig                 |   3 +
 hw/display/meson.build             |   1 +
 hw/display/trace-events            |  14 ++
 6 files changed, 428 insertions(+), 1 deletion(-)
 create mode 100644 include/hw/display/dm163.h
 create mode 100644 hw/display/dm163.c

diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/b-l475e-iot01a.rst
+++ b/docs/system/arm/b-l475e-iot01a.rst
@@ -XXX,XX +XXX,XX @@ USART, I2C, SPI, CAN and USB OTG, as well as a variety of sensors.
 Supported devices
 """""""""""""""""
 
-Currently B-L475E-IOT01A machine's only supports the following devices:
+Currently B-L475E-IOT01A machines support the following devices:
 
 - Cortex-M4F based STM32L4x5 SoC
 - STM32L4x5 EXTI (Extended interrupts and events controller)
@@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices:
 - STM32L4x5 RCC (Reset and clock control)
 - STM32L4x5 GPIOs (General-purpose I/Os)
 - STM32L4x5 USARTs, UARTs and LPUART (Serial ports)
+- optional 8x8 led display (based on DM163 driver)
 
 Missing devices
 """""""""""""""
diff --git a/include/hw/display/dm163.h b/include/hw/display/dm163.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/display/dm163.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU DM163 8x3-channel constant current led driver
+ * driving columns of associated 8x8 RGB matrix.
+ *
+ * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
+ * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_DISPLAY_DM163_H
+#define HW_DISPLAY_DM163_H
+
+#include "qom/object.h"
+#include "hw/qdev-core.h"
+
+#define TYPE_DM163 "dm163"
+OBJECT_DECLARE_SIMPLE_TYPE(DM163State, DM163);
+
+#define RGB_MATRIX_NUM_ROWS 8
+#define RGB_MATRIX_NUM_COLS 8
+#define DM163_NUM_LEDS (RGB_MATRIX_NUM_COLS * 3)
+/* The last row is filled with 0 (turned off row) */
+#define COLOR_BUFFER_SIZE (RGB_MATRIX_NUM_ROWS + 1)
+
+typedef struct DM163State {
+    DeviceState parent_obj;
+
+    /* DM163 driver */
+    uint64_t bank0_shift_register[3];
+    uint64_t bank1_shift_register[3];
+    uint16_t latched_outputs[DM163_NUM_LEDS];
+    uint16_t outputs[DM163_NUM_LEDS];
+    qemu_irq sout;
+
+    uint8_t sin;
+    uint8_t dck;
+    uint8_t rst_b;
+    uint8_t lat_b;
+    uint8_t selbk;
+    uint8_t en_b;
+
+    /* IM120417002 colors shield */
+    uint8_t activated_rows;
+
+    /* 8x8 RGB matrix */
+    QemuConsole *console;
+    uint8_t redraw;
+    /* Rows currently being displayed on the matrix. */
+    /* The last row is filled with 0 (turned off row) */
+    uint32_t buffer[COLOR_BUFFER_SIZE][RGB_MATRIX_NUM_COLS];
+    uint8_t last_buffer_idx;
+    uint8_t buffer_idx_of_row[RGB_MATRIX_NUM_ROWS];
+    /* Used to simulate retinal persistence of rows */
+    uint8_t row_persistence_delay[RGB_MATRIX_NUM_ROWS];
+} DM163State;
+
+#endif /* HW_DISPLAY_DM163_H */
diff --git a/hw/display/dm163.c b/hw/display/dm163.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/display/dm163.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU DM163 8x3-channel constant current led driver
+ * driving columns of associated 8x8 RGB matrix.
+ *
+ * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
+ * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+/*
+ * The reference used for the DM163 is the following :
+ * http://www.siti.com.tw/product/spec/LED/DM163.pdf
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/display/dm163.h"
+#include "ui/console.h"
+#include "trace.h"
+
+#define LED_SQUARE_SIZE 100
+/* Number of frames a row stays visible after being turned off. */
+#define ROW_PERSISTENCE 3
+#define TURNED_OFF_ROW (COLOR_BUFFER_SIZE - 1)
+
+static const VMStateDescription vmstate_dm163 = {
+    .name = TYPE_DM163,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (const VMStateField[]) {
+        VMSTATE_UINT64_ARRAY(bank0_shift_register, DM163State, 3),
+        VMSTATE_UINT64_ARRAY(bank1_shift_register, DM163State, 3),
+        VMSTATE_UINT16_ARRAY(latched_outputs, DM163State, DM163_NUM_LEDS),
+        VMSTATE_UINT16_ARRAY(outputs, DM163State, DM163_NUM_LEDS),
+        VMSTATE_UINT8(dck, DM163State),
+        VMSTATE_UINT8(en_b, DM163State),
+        VMSTATE_UINT8(lat_b, DM163State),
+        VMSTATE_UINT8(rst_b, DM163State),
+        VMSTATE_UINT8(selbk, DM163State),
+        VMSTATE_UINT8(sin, DM163State),
+        VMSTATE_UINT8(activated_rows, DM163State),
+        VMSTATE_UINT32_2DARRAY(buffer, DM163State, COLOR_BUFFER_SIZE,
+                               RGB_MATRIX_NUM_COLS),
+        VMSTATE_UINT8(last_buffer_idx, DM163State),
+        VMSTATE_UINT8_ARRAY(buffer_idx_of_row, DM163State, RGB_MATRIX_NUM_ROWS),
+        VMSTATE_UINT8_ARRAY(row_persistence_delay, DM163State,
+                            RGB_MATRIX_NUM_ROWS),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void dm163_reset_hold(Object *obj, ResetType type)
+{
+    DM163State *s = DM163(obj);
+
+    s->sin = 0;
+    s->dck = 0;
+    s->rst_b = 0;
+    /* Ensuring the first falling edge of lat_b isn't missed */
+    s->lat_b = 1;
+    s->selbk = 0;
+    s->en_b = 0;
+    /* Reset stops the PWM, not the shift and latched registers. */
+    memset(s->outputs, 0, sizeof(s->outputs));
+
+    s->activated_rows = 0;
+    s->redraw = 0;
+    trace_dm163_redraw(s->redraw);
+    for (unsigned i = 0; i < COLOR_BUFFER_SIZE; i++) {
+        memset(s->buffer[i], 0, sizeof(s->buffer[0]));
+    }
+    s->last_buffer_idx = 0;
+    memset(s->buffer_idx_of_row, TURNED_OFF_ROW, sizeof(s->buffer_idx_of_row));
+    memset(s->row_persistence_delay, 0, sizeof(s->row_persistence_delay));
+}
+
+static void dm163_dck_gpio_handler(void *opaque, int line, int new_state)
+{
+    DM163State *s = opaque;
+
+    if (new_state && !s->dck) {
+        /*
+         * On raising dck, sample selbk to get the bank to use, and
+         * sample sin for the bit to enter into the bank shift buffer.
+         */
+        uint64_t *sb =
+            s->selbk ? s->bank1_shift_register : s->bank0_shift_register;
+        /* Output the outgoing bit on sout */
+        const bool sout = (s->selbk ? sb[2] & MAKE_64BIT_MASK(63, 1) :
+                           sb[2] & MAKE_64BIT_MASK(15, 1)) != 0;
+        qemu_set_irq(s->sout, sout);
+        /* Enter sin into the shift buffer */
+        sb[2] = (sb[2] << 1) | ((sb[1] >> 63) & 1);
+        sb[1] = (sb[1] << 1) | ((sb[0] >> 63) & 1);
+        sb[0] = (sb[0] << 1) | s->sin;
+    }
+
+    s->dck = new_state;
+    trace_dm163_dck(new_state);
+}
+
+static void dm163_propagate_outputs(DM163State *s)
+{
+    s->last_buffer_idx = (s->last_buffer_idx + 1) % RGB_MATRIX_NUM_ROWS;
+    /* Values are output when reset is high and enable is low. */
+    if (s->rst_b && !s->en_b) {
+        memcpy(s->outputs, s->latched_outputs, sizeof(s->outputs));
+    } else {
+        memset(s->outputs, 0, sizeof(s->outputs));
+    }
+    for (unsigned x = 0; x < RGB_MATRIX_NUM_COLS; x++) {
+        /* Grouping the 3 RGB channels in a pixel value */
+        const uint16_t b = extract16(s->outputs[3 * x + 0], 6, 8);
+        const uint16_t g = extract16(s->outputs[3 * x + 1], 6, 8);
+        const uint16_t r = extract16(s->outputs[3 * x + 2], 6, 8);
+        uint32_t rgba = 0;
+
+        trace_dm163_channels(3 * x + 2, r);
+        trace_dm163_channels(3 * x + 1, g);
+        trace_dm163_channels(3 * x + 0, b);
+
+        rgba = deposit32(rgba,  0, 8, r);
+        rgba = deposit32(rgba,  8, 8, g);
+        rgba = deposit32(rgba, 16, 8, b);
+
+        /* Led values are sent from the last one to the first one */
+        s->buffer[s->last_buffer_idx][RGB_MATRIX_NUM_COLS - x - 1] = rgba;
+    }
+    for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) {
+        if (s->activated_rows & (1 << row)) {
+            s->buffer_idx_of_row[row] = s->last_buffer_idx;
+            s->redraw |= (1 << row);
+            trace_dm163_redraw(s->redraw);
+        }
+    }
+}
+
+static void dm163_en_b_gpio_handler(void *opaque, int line, int new_state)
+{
+    DM163State *s = opaque;
+
+    s->en_b = new_state;
+    dm163_propagate_outputs(s);
+    trace_dm163_en_b(new_state);
+}
+
+static uint8_t dm163_bank0(const DM163State *s, uint8_t led)
+{
+    /*
+     * Bank 0 uses 6 bits per led, so a value may be stored accross
+     * two uint64_t entries.
+     */
+    const uint8_t low_bit = 6 * led;
+    const uint8_t low_word = low_bit / 64;
+    const uint8_t high_word = (low_bit + 5) / 64;
+    const uint8_t low_shift = low_bit % 64;
+
+    if (low_word == high_word) {
+        /* Simple case: the value belongs to one entry. */
+        return extract64(s->bank0_shift_register[low_word], low_shift, 6);
+    }
+
+    const uint8_t nb_bits_in_low_word = 64 - low_shift;
+    const uint8_t nb_bits_in_high_word = 6 - nb_bits_in_low_word;
+
+    const uint64_t bits_in_low_word = \
+        extract64(s->bank0_shift_register[low_word], low_shift,
+                  nb_bits_in_low_word);
+    const uint64_t bits_in_high_word = \
+        extract64(s->bank0_shift_register[high_word], 0,
+                  nb_bits_in_high_word);
+    uint8_t val = 0;
+
+    val = deposit32(val, 0, nb_bits_in_low_word, bits_in_low_word);
+    val = deposit32(val, nb_bits_in_low_word, nb_bits_in_high_word,
+                    bits_in_high_word);
+
+    return val;
+}
+
+static uint8_t dm163_bank1(const DM163State *s, uint8_t led)
+{
+    const uint64_t entry = s->bank1_shift_register[led / RGB_MATRIX_NUM_COLS];
+    return extract64(entry, 8 * (led % RGB_MATRIX_NUM_COLS), 8);
+}
+
+static void dm163_lat_b_gpio_handler(void *opaque, int line, int new_state)
+{
+    DM163State *s = opaque;
+
+    if (s->lat_b && !new_state) {
+        for (int led = 0; led < DM163_NUM_LEDS; led++) {
+            s->latched_outputs[led] = dm163_bank0(s, led) * dm163_bank1(s, led);
+        }
+        dm163_propagate_outputs(s);
+    }
+
+    s->lat_b = new_state;
+    trace_dm163_lat_b(new_state);
+}
+
+static void dm163_rst_b_gpio_handler(void *opaque, int line, int new_state)
+{
+    DM163State *s = opaque;
+
+    s->rst_b = new_state;
+    dm163_propagate_outputs(s);
+    trace_dm163_rst_b(new_state);
+}
+
+static void dm163_selbk_gpio_handler(void *opaque, int line, int new_state)
+{
+    DM163State *s = opaque;
+
+    s->selbk = new_state;
+    trace_dm163_selbk(new_state);
+}
+
+static void dm163_sin_gpio_handler(void *opaque, int line, int new_state)
+{
+    DM163State *s = opaque;
+
+    s->sin = new_state;
+    trace_dm163_sin(new_state);
+}
+
+static void dm163_rows_gpio_handler(void *opaque, int line, int new_state)
+{
+    DM163State *s = opaque;
+
+    if (new_state) {
+        s->activated_rows |= (1 << line);
+        s->buffer_idx_of_row[line] = s->last_buffer_idx;
+        s->redraw |= (1 << line);
+        trace_dm163_redraw(s->redraw);
+    } else {
+        s->activated_rows &= ~(1 << line);
+        s->row_persistence_delay[line] = ROW_PERSISTENCE;
+    }
+    trace_dm163_activated_rows(s->activated_rows);
+}
+
+static void dm163_invalidate_display(void *opaque)
+{
+    DM163State *s = (DM163State *)opaque;
+    s->redraw = 0xFF;
+    trace_dm163_redraw(s->redraw);
+}
+
+static void update_row_persistence_delay(DM163State *s, unsigned row)
+{
+    if (s->row_persistence_delay[row]) {
+        s->row_persistence_delay[row]--;
+    } else {
+        /*
+         * If the ROW_PERSISTENCE delay is up,
+         * the row is turned off.
+         */
+        s->buffer_idx_of_row[row] = TURNED_OFF_ROW;
+        s->redraw |= (1 << row);
+        trace_dm163_redraw(s->redraw);
+    }
+}
+
+static uint32_t *update_display_of_row(DM163State *s, uint32_t *dest,
+                                       unsigned row)
+{
+    for (unsigned _ = 0; _ < LED_SQUARE_SIZE; _++) {
+        for (int x = 0; x < RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE; x++) {
+            /* UI layer guarantees that there's 32 bits per pixel (Mar 2024) */
+            *dest++ = s->buffer[s->buffer_idx_of_row[row]][x / LED_SQUARE_SIZE];
+        }
+    }
+
+    dpy_gfx_update(s->console, 0, LED_SQUARE_SIZE * row,
+                    RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE, LED_SQUARE_SIZE);
+    s->redraw &= ~(1 << row);
+    trace_dm163_redraw(s->redraw);
+
+    return dest;
+}
+
+static void dm163_update_display(void *opaque)
+{
+    DM163State *s = (DM163State *)opaque;
+    DisplaySurface *surface = qemu_console_surface(s->console);
+    uint32_t *dest;
+
+    dest = surface_data(surface);
+    for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) {
+        update_row_persistence_delay(s, row);
+        if (!extract8(s->redraw, row, 1)) {
+            dest += LED_SQUARE_SIZE * LED_SQUARE_SIZE * RGB_MATRIX_NUM_COLS;
+            continue;
+        }
+        dest = update_display_of_row(s, dest, row);
+    }
+}
+
+static const GraphicHwOps dm163_ops = {
+    .invalidate  = dm163_invalidate_display,
+    .gfx_update  = dm163_update_display,
+};
+
+static void dm163_realize(DeviceState *dev, Error **errp)
+{
+    DM163State *s = DM163(dev);
+
+    qdev_init_gpio_in(dev, dm163_rows_gpio_handler, RGB_MATRIX_NUM_ROWS);
+    qdev_init_gpio_in(dev, dm163_sin_gpio_handler, 1);
+    qdev_init_gpio_in(dev, dm163_dck_gpio_handler, 1);
+    qdev_init_gpio_in(dev, dm163_rst_b_gpio_handler, 1);
+    qdev_init_gpio_in(dev, dm163_lat_b_gpio_handler, 1);
+    qdev_init_gpio_in(dev, dm163_selbk_gpio_handler, 1);
+    qdev_init_gpio_in(dev, dm163_en_b_gpio_handler, 1);
+    qdev_init_gpio_out_named(dev, &s->sout, "sout", 1);
+
+    s->console = graphic_console_init(dev, 0, &dm163_ops, s);
+    qemu_console_resize(s->console, RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE,
+                        RGB_MATRIX_NUM_ROWS * LED_SQUARE_SIZE);
+}
+
+static void dm163_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+    dc->desc = "DM163";
+    dc->vmsd = &vmstate_dm163;
+    dc->realize = dm163_realize;
+    rc->phases.hold = dm163_reset_hold;
+    set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
+}
+
+static const TypeInfo dm163_types[] = {
+    {
+        .name = TYPE_DM163,
+        .parent = TYPE_DEVICE,
+        .instance_size = sizeof(DM163State),
+        .class_init = dm163_class_init
+    }
+};
+
+DEFINE_TYPES(dm163_types)
diff --git a/hw/display/Kconfig b/hw/display/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/Kconfig
+++ b/hw/display/Kconfig
@@ -XXX,XX +XXX,XX @@ config XLNX_DISPLAYPORT
     bool
     # defaults to "N", enabled by specific boards
     depends on PIXMAN
+
+config DM163
+    bool
diff --git a/hw/display/meson.build b/hw/display/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/meson.build
+++ b/hw/display/meson.build
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-fb.c'))
 
 system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c'))
 system_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-dmabuf.c'))
+system_ss.add(when: 'CONFIG_DM163', if_true: files('dm163.c'))
 
 if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or
     config_all_devices.has_key('CONFIG_VGA_PCI') or
diff --git a/hw/display/trace-events b/hw/display/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/trace-events
+++ b/hw/display/trace-events
@@ -XXX,XX +XXX,XX @@ macfb_ctrl_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%"PRI
 macfb_sense_read(uint32_t value) "video sense: 0x%"PRIx32
 macfb_sense_write(uint32_t value) "video sense: 0x%"PRIx32
 macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) "setting mode to width %"PRId32 " height %"PRId32 " size %d"
+
+# dm163.c
+dm163_redraw(uint8_t redraw) "0x%02x"
+dm163_dck(unsigned new_state) "dck : %u"
+dm163_en_b(unsigned new_state) "en_b : %u"
+dm163_rst_b(unsigned new_state) "rst_b : %u"
+dm163_lat_b(unsigned new_state) "lat_b : %u"
+dm163_sin(unsigned new_state) "sin : %u"
+dm163_selbk(unsigned new_state) "selbk : %u"
+dm163_activated_rows(int new_state) "Activated rows : 0x%" PRIx32 ""
+dm163_bits_ppi(unsigned dest_width) "dest_width : %u"
+dm163_leds(int led, uint32_t value) "led %d: 0x%x"
+dm163_channels(int channel, uint8_t value) "channel %d: 0x%x"
+dm163_refresh_rate(uint32_t rr) "refresh rate %d"
-- 
2.34.1

From: Inès Varhol <ines.varhol@telecom-paris.fr>

Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC
to the optional DM163 display from the board code (GPIOs outputs need
to be connected to both SYSCFG inputs and DM163 inputs).

STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly.

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-3-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/stm32l4x5_soc.c              |  6 ++++--
 tests/qtest/stm32l4x5_gpio-test.c   | 13 ++++++++-----
 tests/qtest/stm32l4x5_syscfg-test.c | 17 ++++++++++-------
 3 files changed, 22 insertions(+), 14 deletions(-)

diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stm32l4x5_soc.c
+++ b/hw/arm/stm32l4x5_soc.c
@@ -XXX,XX +XXX,XX @@
 /*
  * STM32L4x5 SoC family
  *
- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
  *
  * SPDX-License-Identifier: GPL-2.0-or-later
  *
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
         }
     }
 
+    qdev_pass_gpios(DEVICE(&s->syscfg), dev_soc, NULL);
+
     /* EXTI device */
     busdev = SYS_BUS_DEVICE(&s->exti);
     if (!sysbus_realize(busdev, errp)) {
diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/stm32l4x5_gpio-test.c
+++ b/tests/qtest/stm32l4x5_gpio-test.c
@@ -XXX,XX +XXX,XX @@
 #define OTYPER_PUSH_PULL 0
 #define OTYPER_OPEN_DRAIN 1
 
+/* SoC forwards GPIOs to SysCfg */
+#define SYSCFG "/machine/soc"
+
 const uint32_t moder_reset[NUM_GPIOS] = {
     0xABFFFFFF,
     0xFFFFFEBF,
@@ -XXX,XX +XXX,XX @@ static void test_gpio_output_mode(const void *data)
     uint32_t gpio = test_gpio_addr(data);
     unsigned int gpio_id = get_gpio_id(gpio);
 
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+    qtest_irq_intercept_in(global_qtest, SYSCFG);
 
     /* Set a bit in ODR and check nothing happens */
     gpio_set_bit(gpio, ODR, pin, 1);
@@ -XXX,XX +XXX,XX @@ static void test_gpio_input_mode(const void *data)
     uint32_t gpio = test_gpio_addr(data);
     unsigned int gpio_id = get_gpio_id(gpio);
 
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+    qtest_irq_intercept_in(global_qtest, SYSCFG);
 
     /* Configure a line as input, raise it, and check that the pin is high */
     gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
@@ -XXX,XX +XXX,XX @@ static void test_pull_up_pull_down(const void *data)
     uint32_t gpio = test_gpio_addr(data);
     unsigned int gpio_id = get_gpio_id(gpio);
 
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+    qtest_irq_intercept_in(global_qtest, SYSCFG);
 
     /* Configure a line as input with pull-up, check the line is set high */
     gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
@@ -XXX,XX +XXX,XX @@ static void test_push_pull(const void *data)
     uint32_t gpio = test_gpio_addr(data);
     uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
 
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+    qtest_irq_intercept_in(global_qtest, SYSCFG);
 
     /* Setting a line high externally, configuring it in push-pull output */
     /* And checking the pin was disconnected */
@@ -XXX,XX +XXX,XX @@ static void test_open_drain(const void *data)
     uint32_t gpio = test_gpio_addr(data);
     uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
 
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
+    qtest_irq_intercept_in(global_qtest, SYSCFG);
 
     /* Setting a line high externally, configuring it in open-drain output */
     /* And checking the pin was disconnected */
diff --git a/tests/qtest/stm32l4x5_syscfg-test.c b/tests/qtest/stm32l4x5_syscfg-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/stm32l4x5_syscfg-test.c
+++ b/tests/qtest/stm32l4x5_syscfg-test.c
@@ -XXX,XX +XXX,XX @@
 /*
  * QTest testcase for STM32L4x5_SYSCFG
  *
- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
  *
  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  * See the COPYING file in the top-level directory.
@@ -XXX,XX +XXX,XX @@
 #define SYSCFG_SWPR2 0x28
 #define INVALID_ADDR 0x2C
 
+/* SoC forwards GPIOs to SysCfg */
+#define SYSCFG "/machine/soc"
+#define EXTI "/machine/soc/exti"
+
 static void syscfg_writel(unsigned int offset, uint32_t value)
 {
     writel(SYSCFG_BASE_ADDR + offset, value);
@@ -XXX,XX +XXX,XX @@ static uint32_t syscfg_readl(unsigned int offset)
 
 static void syscfg_set_irq(int num, int level)
 {
-   qtest_set_irq_in(global_qtest, "/machine/soc/syscfg",
-                    NULL, num, level);
+   qtest_set_irq_in(global_qtest, SYSCFG, NULL, num, level);
 }
 
 static void system_reset(void)
@@ -XXX,XX +XXX,XX @@ static void test_interrupt(void)
      * Test that GPIO rising lines result in an irq
      * with the right configuration
      */
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
+    qtest_irq_intercept_in(global_qtest, EXTI);
 
     /* GPIOA is the default source for EXTI lines 0 to 15 */
 
@@ -XXX,XX +XXX,XX @@ static void test_irq_pin_multiplexer(void)
      * Test that syscfg irq sets the right exti irq
      */
 
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
+    qtest_irq_intercept_in(global_qtest, EXTI);
 
     syscfg_set_irq(0, 1);
 
@@ -XXX,XX +XXX,XX @@ static void test_irq_gpio_multiplexer(void)
      * Test that an irq is generated only by the right GPIO
      */
 
-    qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
+    qtest_irq_intercept_in(global_qtest, EXTI);
 
     /* GPIOA is the default source for EXTI lines 0 to 15 */
 
-- 
2.34.1

From: Inès Varhol <ines.varhol@telecom-paris.fr>

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-4-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/b-l475e-iot01a.c | 46 ++++++++++++++++++++++++++++-------------
 1 file changed, 32 insertions(+), 14 deletions(-)

diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -XXX,XX +XXX,XX @@
  * B-L475E-IOT01A Discovery Kit machine
  * (B-L475E-IOT01A IoT Node)
  *
- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
  *
  * SPDX-License-Identifier: GPL-2.0-or-later
  *
@@ -XXX,XX +XXX,XX @@
 
 /* B-L475E-IOT01A implementation is derived from netduinoplus2 */
 
-static void b_l475e_iot01a_init(MachineState *machine)
+#define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a")
+OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A)
+
+typedef struct Bl475eMachineState {
+    MachineState parent_obj;
+
+    Stm32l4x5SocState soc;
+} Bl475eMachineState;
+
+static void bl475e_init(MachineState *machine)
 {
+    Bl475eMachineState *s = B_L475E_IOT01A(machine);
     const Stm32l4x5SocClass *sc;
-    DeviceState *dev;
 
-    dev = qdev_new(TYPE_STM32L4X5XG_SOC);
-    object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
-    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    object_initialize_child(OBJECT(machine), "soc", &s->soc,
+                            TYPE_STM32L4X5XG_SOC);
+    sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
 
-    sc = STM32L4X5_SOC_GET_CLASS(dev);
-    armv7m_load_kernel(ARM_CPU(first_cpu),
-                       machine->kernel_filename,
-                       0, sc->flash_size);
+    sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
+    armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
+                       sc->flash_size);
 }
 
-static void b_l475e_iot01a_machine_init(MachineClass *mc)
+static void bl475e_machine_init(ObjectClass *oc, void *data)
 {
+    MachineClass *mc = MACHINE_CLASS(oc);
     static const char *machine_valid_cpu_types[] = {
         ARM_CPU_TYPE_NAME("cortex-m4"),
         NULL
     };
     mc->desc = "B-L475E-IOT01A Discovery Kit (Cortex-M4)";
-    mc->init = b_l475e_iot01a_init;
+    mc->init = bl475e_init;
     mc->valid_cpu_types = machine_valid_cpu_types;
 
     /* SRAM pre-allocated as part of the SoC instantiation */
     mc->default_ram_size = 0;
 }
 
-DEFINE_MACHINE("b-l475e-iot01a", b_l475e_iot01a_machine_init)
+static const TypeInfo bl475e_machine_type[] = {
+    {
+        .name           = TYPE_B_L475E_IOT01A,
+        .parent         = TYPE_MACHINE,
+        .instance_size  = sizeof(Bl475eMachineState),
+        .class_init     = bl475e_machine_init,
+    }
+};
+
+DEFINE_TYPES(bl475e_machine_type)
-- 
2.34.1

From: Inès Varhol <ines.varhol@telecom-paris.fr>

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-5-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/b-l475e-iot01a.c | 59 +++++++++++++++++++++++++++++++++++++++--
 hw/arm/Kconfig          |  1 +
 2 files changed, 58 insertions(+), 2 deletions(-)

diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "hw/qdev-properties.h"
 #include "qemu/error-report.h"
-#include "hw/arm/stm32l4x5_soc.h"
 #include "hw/arm/boot.h"
+#include "hw/core/split-irq.h"
+#include "hw/arm/stm32l4x5_soc.h"
+#include "hw/gpio/stm32l4x5_gpio.h"
+#include "hw/display/dm163.h"
 
-/* B-L475E-IOT01A implementation is derived from netduinoplus2 */
+/* B-L475E-IOT01A implementation is inspired from netduinoplus2 and arduino */
+
+/*
+ * There are actually 14 input pins in the DM163 device.
+ * Here the DM163 input pin EN isn't connected to the STM32L4x5
+ * GPIOs as the IM120417002 colors shield doesn't actually use
+ * this pin to drive the RGB matrix.
+ */
+#define NUM_DM163_INPUTS 13
+
+static const unsigned dm163_input[NUM_DM163_INPUTS] = {
+    1 * GPIO_NUM_PINS + 2,  /* ROW0  PB2       */
+    0 * GPIO_NUM_PINS + 15, /* ROW1  PA15      */
+    0 * GPIO_NUM_PINS + 2,  /* ROW2  PA2       */
+    0 * GPIO_NUM_PINS + 7,  /* ROW3  PA7       */
+    0 * GPIO_NUM_PINS + 6,  /* ROW4  PA6       */
+    0 * GPIO_NUM_PINS + 5,  /* ROW5  PA5       */
+    1 * GPIO_NUM_PINS + 0,  /* ROW6  PB0       */
+    0 * GPIO_NUM_PINS + 3,  /* ROW7  PA3       */
+    0 * GPIO_NUM_PINS + 4,  /* SIN (SDA) PA4   */
+    1 * GPIO_NUM_PINS + 1,  /* DCK (SCK) PB1   */
+    2 * GPIO_NUM_PINS + 3,  /* RST_B (RST) PC3 */
+    2 * GPIO_NUM_PINS + 4,  /* LAT_B (LAT) PC4 */
+    2 * GPIO_NUM_PINS + 5,  /* SELBK (SB)  PC5 */
+};
 
 #define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a")
 OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A)
@@ -XXX,XX +XXX,XX @@ typedef struct Bl475eMachineState {
     MachineState parent_obj;
 
     Stm32l4x5SocState soc;
+    SplitIRQ gpio_splitters[NUM_DM163_INPUTS];
+    DM163State dm163;
 } Bl475eMachineState;
 
 static void bl475e_init(MachineState *machine)
 {
     Bl475eMachineState *s = B_L475E_IOT01A(machine);
     const Stm32l4x5SocClass *sc;
+    DeviceState *dev, *gpio_out_splitter;
+    unsigned gpio, pin;
 
     object_initialize_child(OBJECT(machine), "soc", &s->soc,
                             TYPE_STM32L4X5XG_SOC);
@@ -XXX,XX +XXX,XX @@ static void bl475e_init(MachineState *machine)
     sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
     armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
                        sc->flash_size);
+
+    if (object_class_by_name(TYPE_DM163)) {
+        object_initialize_child(OBJECT(machine), "dm163",
+                                &s->dm163, TYPE_DM163);
+        dev = DEVICE(&s->dm163);
+        qdev_realize(dev, NULL, &error_abort);
+
+        for (unsigned i = 0; i < NUM_DM163_INPUTS; i++) {
+            object_initialize_child(OBJECT(machine), "gpio-out-splitters[*]",
+                                    &s->gpio_splitters[i], TYPE_SPLIT_IRQ);
+            gpio_out_splitter = DEVICE(&s->gpio_splitters[i]);
+            qdev_prop_set_uint32(gpio_out_splitter, "num-lines", 2);
+            qdev_realize(gpio_out_splitter, NULL, &error_fatal);
+
+            qdev_connect_gpio_out(gpio_out_splitter, 0,
+                qdev_get_gpio_in(DEVICE(&s->soc), dm163_input[i]));
+            qdev_connect_gpio_out(gpio_out_splitter, 1,
+                qdev_get_gpio_in(dev, i));
+            gpio = dm163_input[i] / GPIO_NUM_PINS;
+            pin = dm163_input[i] % GPIO_NUM_PINS;
+            qdev_connect_gpio_out(DEVICE(&s->soc.gpio[gpio]), pin,
+                qdev_get_gpio_in(DEVICE(gpio_out_splitter), 0));
+        }
+    }
 }
 
 static void bl475e_machine_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config B_L475E_IOT01A
     default y
     depends on TCG && ARM
     select STM32L4X5_SOC
+    imply DM163
 
 config STM32L4X5_SOC
     bool
-- 
2.34.1

From: Inès Varhol <ines.varhol@telecom-paris.fr>

`test_dm163_bank()`
Checks that the pin "sout" of the DM163 led driver outputs the values
received on pin "sin" with the expected latency (depending on the bank).

`test_dm163_gpio_connection()`
Check that changes to relevant STM32L4x5 GPIO pins are propagated to the
DM163 device.

Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240424200929.240921-6-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/dm163-test.c | 194 +++++++++++++++++++++++++++++++++++++++
 tests/qtest/meson.build  |   2 +
 2 files changed, 196 insertions(+)
 create mode 100644 tests/qtest/dm163-test.c

diff --git a/tests/qtest/dm163-test.c b/tests/qtest/dm163-test.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/dm163-test.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTest testcase for DM163
+ *
+ * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
+ * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest.h"
+
+enum DM163_INPUTS {
+    SIN = 8,
+    DCK = 9,
+    RST_B = 10,
+    LAT_B = 11,
+    SELBK = 12,
+    EN_B = 13
+};
+
+#define DEVICE_NAME "/machine/dm163"
+#define GPIO_OUT(name, value) qtest_set_irq_in(qts, DEVICE_NAME, NULL, name,   \
+                                               value)
+#define GPIO_PULSE(name)                                                       \
+  do {                                                                         \
+    GPIO_OUT(name, 1);                                                         \
+    GPIO_OUT(name, 0);                                                         \
+  } while (0)
+
+
+static void rise_gpio_pin_dck(QTestState *qts)
+{
+    /* Configure output mode for pin PB1 */
+    qtest_writel(qts, 0x48000400, 0xFFFFFEB7);
+    /* Write 1 in ODR for PB1 */
+    qtest_writel(qts, 0x48000414, 0x00000002);
+}
+
+static void lower_gpio_pin_dck(QTestState *qts)
+{
+    /* Configure output mode for pin PB1 */
+    qtest_writel(qts, 0x48000400, 0xFFFFFEB7);
+    /* Write 0 in ODR for PB1 */
+    qtest_writel(qts, 0x48000414, 0x00000000);
+}
+
+static void rise_gpio_pin_selbk(QTestState *qts)
+{
+    /* Configure output mode for pin PC5 */
+    qtest_writel(qts, 0x48000800, 0xFFFFF7FF);
+    /* Write 1 in ODR for PC5 */
+    qtest_writel(qts, 0x48000814, 0x00000020);
+}
+
+static void lower_gpio_pin_selbk(QTestState *qts)
+{
+    /* Configure output mode for pin PC5 */
+    qtest_writel(qts, 0x48000800, 0xFFFFF7FF);
+    /* Write 0 in ODR for PC5 */
+    qtest_writel(qts, 0x48000814, 0x00000000);
+}
+
+static void rise_gpio_pin_lat_b(QTestState *qts)
+{
+    /* Configure output mode for pin PC4 */
+    qtest_writel(qts, 0x48000800, 0xFFFFFDFF);
+    /* Write 1 in ODR for PC4 */
+    qtest_writel(qts, 0x48000814, 0x00000010);
+}
+
+static void lower_gpio_pin_lat_b(QTestState *qts)
+{
+    /* Configure output mode for pin PC4 */
+    qtest_writel(qts, 0x48000800, 0xFFFFFDFF);
+    /* Write 0 in ODR for PC4 */
+    qtest_writel(qts, 0x48000814, 0x00000000);
+}
+
+static void rise_gpio_pin_rst_b(QTestState *qts)
+{
+    /* Configure output mode for pin PC3 */
+    qtest_writel(qts, 0x48000800, 0xFFFFFF7F);
+    /* Write 1 in ODR for PC3 */
+    qtest_writel(qts, 0x48000814, 0x00000008);
+}
+
+static void lower_gpio_pin_rst_b(QTestState *qts)
+{
+    /* Configure output mode for pin PC3 */
+    qtest_writel(qts, 0x48000800, 0xFFFFFF7F);
+    /* Write 0 in ODR for PC3 */
+    qtest_writel(qts, 0x48000814, 0x00000000);
+}
+
+static void rise_gpio_pin_sin(QTestState *qts)
+{
+    /* Configure output mode for pin PA4 */
+    qtest_writel(qts, 0x48000000, 0xFFFFFDFF);
+    /* Write 1 in ODR for PA4 */
+    qtest_writel(qts, 0x48000014, 0x00000010);
+}
+
+static void lower_gpio_pin_sin(QTestState *qts)
+{
+    /* Configure output mode for pin PA4 */
+    qtest_writel(qts, 0x48000000, 0xFFFFFDFF);
+    /* Write 0 in ODR for PA4 */
+    qtest_writel(qts, 0x48000014, 0x00000000);
+}
+
+static void test_dm163_bank(const void *opaque)
+{
+    const unsigned bank = (uintptr_t) opaque;
+    const int width = bank ? 192 : 144;
+
+    QTestState *qts = qtest_initf("-M b-l475e-iot01a");
+    qtest_irq_intercept_out_named(qts, DEVICE_NAME, "sout");
+    GPIO_OUT(RST_B, 1);
+    GPIO_OUT(EN_B, 0);
+    GPIO_OUT(DCK, 0);
+    GPIO_OUT(SELBK, bank);
+    GPIO_OUT(LAT_B, 1);
+
+    /* Fill bank with zeroes */
+    GPIO_OUT(SIN, 0);
+    for (int i = 0; i < width; i++) {
+        GPIO_PULSE(DCK);
+    }
+    /* Fill bank with ones, check that we get the previous zeroes */
+    GPIO_OUT(SIN, 1);
+    for (int i = 0; i < width; i++) {
+        GPIO_PULSE(DCK);
+        g_assert(!qtest_get_irq(qts, 0));
+    }
+
+    /* Pulse one more bit in the bank, check that we get a one */
+    GPIO_PULSE(DCK);
+    g_assert(qtest_get_irq(qts, 0));
+
+    qtest_quit(qts);
+}
+
+static void test_dm163_gpio_connection(void)
+{
+    QTestState *qts = qtest_init("-M b-l475e-iot01a");
+    qtest_irq_intercept_in(qts, DEVICE_NAME);
+
+    g_assert_false(qtest_get_irq(qts, SIN));
+    g_assert_false(qtest_get_irq(qts, DCK));
+    g_assert_false(qtest_get_irq(qts, RST_B));
+    g_assert_false(qtest_get_irq(qts, LAT_B));
+    g_assert_false(qtest_get_irq(qts, SELBK));
+
+    rise_gpio_pin_dck(qts);
+    g_assert_true(qtest_get_irq(qts, DCK));
+    lower_gpio_pin_dck(qts);
+    g_assert_false(qtest_get_irq(qts, DCK));
+
+    rise_gpio_pin_lat_b(qts);
+    g_assert_true(qtest_get_irq(qts, LAT_B));
+    lower_gpio_pin_lat_b(qts);
+    g_assert_false(qtest_get_irq(qts, LAT_B));
+
+    rise_gpio_pin_selbk(qts);
+    g_assert_true(qtest_get_irq(qts, SELBK));
+    lower_gpio_pin_selbk(qts);
+    g_assert_false(qtest_get_irq(qts, SELBK));
+
+    rise_gpio_pin_rst_b(qts);
+    g_assert_true(qtest_get_irq(qts, RST_B));
+    lower_gpio_pin_rst_b(qts);
+    g_assert_false(qtest_get_irq(qts, RST_B));
+
+    rise_gpio_pin_sin(qts);
+    g_assert_true(qtest_get_irq(qts, SIN));
+    lower_gpio_pin_sin(qts);
+    g_assert_false(qtest_get_irq(qts, SIN));
+
+    g_assert_false(qtest_get_irq(qts, DCK));
+    g_assert_false(qtest_get_irq(qts, LAT_B));
+    g_assert_false(qtest_get_irq(qts, SELBK));
+    g_assert_false(qtest_get_irq(qts, RST_B));
+}
+
+int main(int argc, char **argv)
+{
+    g_test_init(&argc, &argv, NULL);
+    qtest_add_data_func("/dm163/bank0", (void *)0, test_dm163_bank);
+    qtest_add_data_func("/dm163/bank1", (void *)1, test_dm163_bank);
+    qtest_add_func("/dm163/gpio_connection", test_dm163_gpio_connection);
+    return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_arm = \
   (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
   (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 : []) + \
   (config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-test'] : []) + \
+  (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and
+   config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \
   ['arm-cpu-features',
    'boot-serial-test']
 
-- 
2.34.1