The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:

Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702

for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:

target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)

* more MVE instructions

* hw/gpio/gpio_pwr: use shutdown function for reboot

* target/arm: Check NaN mode before silencing NaN

* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine

* hw/arm: Add basic power management to raspi.

* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc

Joe Komlodi (1):

target/arm: Check NaN mode before silencing NaN

Maxim Uvarov (1):

hw/gpio/gpio_pwr: use shutdown function for reboot

Nolan Leake (1):

hw/arm: Add basic power management to raspi.

Patrick Venture (2):

docs/system/arm: Add quanta-q7l1-bmc reference

docs/system/arm: Add quanta-gbs-bmc reference

Peter Maydell (18):

target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation

target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH

target/arm: Make asimd_imm_const() public

target/arm: Use asimd_imm_const for A64 decode

target/arm: Use dup_const() instead of bitfield_replicate()

target/arm: Implement MVE logical immediate insns

target/arm: Implement MVE vector shift left by immediate insns

target/arm: Implement MVE vector shift right by immediate insns

target/arm: Implement MVE VSHLL

target/arm: Implement MVE VSRI, VSLI

target/arm: Implement MVE VSHRN, VRSHRN

target/arm: Implement MVE saturating narrowing shifts

target/arm: Implement MVE VSHLC

target/arm: Implement MVE VADDLV

target/arm: Implement MVE long shifts by immediate

target/arm: Implement MVE long shifts by register

target/arm: Implement MVE shifts by immediate

target/arm: Implement MVE shifts by register

tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine

docs/system/arm/aspeed.rst | 1 +

docs/system/arm/nuvoton.rst | 5 +-

include/hw/arm/bcm2835_peripherals.h | 3 +-

include/hw/misc/bcm2835_powermgt.h | 29 ++

target/arm/helper-mve.h | 108 +++++++

target/arm/translate.h | 41 +++

target/arm/mve.decode | 177 ++++++++++-

target/arm/t32.decode | 71 ++++-

hw/arm/bcm2835_peripherals.c | 13 +-

hw/gpio/gpio_pwr.c | 2 +-

hw/misc/bcm2835_powermgt.c | 160 ++++++++++

target/arm/helper-a64.c | 12 +-

target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--

target/arm/translate-a64.c | 86 +-----

target/arm/translate-mve.c | 261 +++++++++++++++-

target/arm/translate-neon.c | 81 -----

target/arm/translate.c | 327 +++++++++++++++++++-

target/arm/vfp_helper.c | 24 +-

hw/misc/meson.build | 1 +

tests/acceptance/boot_linux_console.py | 43 +++

20 files changed, 1760 insertions(+), 209 deletions(-)

create mode 100644 include/hw/misc/bcm2835_powermgt.h

create mode 100644 hw/misc/bcm2835_powermgt.c

Implement the MVE shifts by register, which perform

shifts on a single general-purpose register.

target/arm/helper-mve.h | 2 ++

target/arm/translate.h | 1 +

target/arm/t32.decode | 18 ++++++++++++++----

target/arm/mve_helper.c | 10 ++++++++++

target/arm/translate.c | 30 ++++++++++++++++++++++++++++++

5 files changed, 57 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h

--- a/target/arm/helper-mve.h

+++ b/target/arm/helper-mve.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)

DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)

DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)

+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)

+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)

diff --git a/target/arm/translate.h b/target/arm/translate.h

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);

typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);

typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);

typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);

+typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);

/**

* arm_tbflags_from_tb:

diff --git a/target/arm/t32.decode b/target/arm/t32.decode

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/t32.decode

+++ b/target/arm/t32.decode

&mve_shl_ri rdalo rdahi shim

&mve_shl_rr rdalo rdahi rm

&mve_sh_ri rda shim

+&mve_sh_rr rda rm

# rdahi: bits [3:1] from insn, bit 0 is 1

# rdalo: bits [3:1] from insn, bit 0 is 0

@@ -XXX,XX +XXX,XX @@

&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9

@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \

&mve_sh_ri shim=%imm5_12_6

+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr

{

TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi

@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi

SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri

}

- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr

- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr

- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr

- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr

+ {

+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr

+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr

+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr

+ }

+

+ {

+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr

+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr

+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr

+ }

+

UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr

SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr

]

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/mve_helper.c

+++ b/target/arm/mve_helper.c

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)

{

return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);

}

+

+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)

+{

+ return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);

+}

+

+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)

+{

+ return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);

+}

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)

return do_mve_sh_ri(s, a, gen_mve_uqshl);

}

+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)

+{

+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {

+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */

+ return false;

+ }

+ if (!dc_isar_feature(aa32_mve, s) ||

+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||

+ a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||

+ a->rm == a->rda) {

+ /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */

+ unallocated_encoding(s);

+ return true;

+ }

+

+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */

+ fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);

+ return true;

+}

+

+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)

+{

+ return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);

+}

+

+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)

+{

+ return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);

+}

+

/*

* Multiply and multiply accumulate

*/

2.20.1

The MVE extension to v8.1M includes some new shift instructions which

sit entirely within the non-coprocessor part of the encoding space

and which operate only on general-purpose registers. They take up

the space which was previously UNPREDICTABLE MOVS and ORRS encodings

with Rm == 13 or 15.

Implement the long shifts by immediate, which perform shifts on a

pair of general-purpose registers treated as a 64-bit quantity, with

an immediate shift count between 1 and 32.

Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for

the Rm==13,15 case, we need to explicitly emit code to UNDEF for the

cases where v8.1M now requires that. (Trying to change MOVS and ORRS

is too difficult, because the functions that generate the code are

shared between a dozen different kinds of arithmetic or logical

instruction for all A32, T16 and T32 encodings, and for some insns

and some encodings Rm==13,15 are valid.)

We make the helper functions we need for UQSHLL and SQSHLL take

a 32-bit value which the helper casts to int8_t because we'll need

these helpers also for the shift-by-register insns, where the shift

count might be < 0 or > 32.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210628135835.6690-16-peter.maydell@linaro.org

---

target/arm/helper-mve.h | 3 ++

target/arm/translate.h | 1 +

target/arm/t32.decode | 28 +++++++++++++

target/arm/mve_helper.c | 10 +++++

target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++

5 files changed, 132 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h

--- a/target/arm/helper-mve.h

+++ b/target/arm/helper-mve.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)

+

+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)

+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)

diff --git a/target/arm/translate.h b/target/arm/translate.h

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);

typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);

typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);

typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);

+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);

/**

* arm_tbflags_from_tb:

diff --git a/target/arm/t32.decode b/target/arm/t32.decode

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/t32.decode

+++ b/target/arm/t32.decode

&mcr !extern cp opc1 crn crm opc2 rt

&mcrr !extern cp opc1 crm rt rt2

+&mve_shl_ri rdalo rdahi shim

+

+# rdahi: bits [3:1] from insn, bit 0 is 1

+# rdalo: bits [3:1] from insn, bit 0 is 0

+%rdahi_9 9:3 !function=times_2_plus_1

+%rdalo_17 17:3 !function=times_2

+

# Data-processing (register)

%imm5_12_6 12:3 6:2

@@ -XXX,XX +XXX,XX @@

@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \

&s_rrr_shi shim=%imm5_12_6 s=1 rd=0

+@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \

+ &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9

+

{

TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi

AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi

}

BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi

{

+ # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS

+ # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE

+ # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that

+ # they explicitly call unallocated_encoding() for cases that must UNDEF

+ # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting

+ # the rest fall through (where ORR_rrri and MOV_rxri will end up

+ # handling them as r13 and r15 accesses with the same semantics as A32).

+ [

+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri

+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri

+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri

+

+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri

+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri

+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri

+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri

+ ]

+

MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi

ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi

}

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/mve_helper.c

+++ b/target/arm/mve_helper.c

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,

mve_advance_vpt(env);

return rdm;

}

+

+uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)

+{

+ return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);

+}

+

+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)

+{

+ return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);

+}

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)

return true;

}

+/*

+ * v8.1M MVE wide-shifts

+ */

+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,

+ WideShiftImmFn *fn)

+{

+ TCGv_i64 rda;

+ TCGv_i32 rdalo, rdahi;

+

+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {

+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */

+ return false;

+ }

+ if (a->rdahi == 15) {

+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */

+ return false;

+ }

+ if (!dc_isar_feature(aa32_mve, s) ||

+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||

+ a->rdahi == 13) {

+ /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */

+ unallocated_encoding(s);

+ return true;

+ }

+

+ if (a->shim == 0) {

+ a->shim = 32;

+ }

+

+ rda = tcg_temp_new_i64();

+ rdalo = load_reg(s, a->rdalo);

+ rdahi = load_reg(s, a->rdahi);

+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);

+

+ fn(rda, rda, a->shim);

+

+ tcg_gen_extrl_i64_i32(rdalo, rda);

+ tcg_gen_extrh_i64_i32(rdahi, rda);

+ store_reg(s, a->rdalo, rdalo);

+ store_reg(s, a->rdahi, rdahi);

+ tcg_temp_free_i64(rda);

+

+ return true;

+}

+

+static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)

+{

+ return do_mve_shl_ri(s, a, tcg_gen_sari_i64);

+}

+

+static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)

+{

+ return do_mve_shl_ri(s, a, tcg_gen_shli_i64);

+}

+

+static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)

+{

+ return do_mve_shl_ri(s, a, tcg_gen_shri_i64);

+}

+

+static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)

+{

+ gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));

+}

+

+static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)

+{

+ return do_mve_shl_ri(s, a, gen_mve_sqshll);

+}

+

+static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)

+{

+ gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));

+}

+

+static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)

+{

+ return do_mve_shl_ri(s, a, gen_mve_uqshll);

+}

+

+static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)

+{

+ return do_mve_shl_ri(s, a, gen_srshr64_i64);

+}

+

+static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)

+{

+ return do_mve_shl_ri(s, a, gen_urshr64_i64);

+}

+

/*

* Multiply and multiply accumulate

*/

2.20.1

The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH

insns had some bugs:

* the 32x32 multiply of elements was being done as 32x32->32,

not 32x32->64

* we were incorrectly maintaining the accumulator in its full

72-bit form across all 4 beats of the insn; in the pseudocode

it is squashed back into the 64 bits of the RdaHi:RdaLo

registers after each beat

In particular, fixing the second of these allows us to recast

the implementation to avoid 128-bit arithmetic entirely.

Since the element size here is always 4, we can also drop the

parameterization of ESIZE to make the code a little more readable.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210628135835.6690-3-peter.maydell@linaro.org

---

target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------

1 file changed, 21 insertions(+), 17 deletions(-)

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c

--- a/target/arm/mve_helper.c

+++ b/target/arm/mve_helper.c

*/

#include "qemu/osdep.h"

-#include "qemu/int128.h"

#include "cpu.h"

#include "internals.h"

#include "vec_internal.h"

@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)

DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)

/*

- * Rounding multiply add long dual accumulate high: we must keep

- * a 72-bit internal accumulator value and return the top 64 bits.

+ * Rounding multiply add long dual accumulate high. In the pseudocode

+ * this is implemented with a 72-bit internal accumulator value of which

+ * the top 64 bits are returned. We optimize this to avoid having to

+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator

+ * is squashed back into 64-bits after each beat.

*/

-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \

+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \

uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \

void *vm, uint64_t a) \

{ \

uint16_t mask = mve_element_mask(env); \

unsigned e; \

TYPE *n = vn, *m = vm; \

- Int128 acc = int128_lshift(TO128(a), 8); \

- for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \

+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \

if (mask & 1) { \

+ LTYPE mul; \

if (e & 1) { \

- acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \

- m[H##ESIZE(e)])); \

+ mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \

+ if (SUB) { \

+ mul = -mul; \

+ } \

} else { \

- acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \

- m[H##ESIZE(e)])); \

+ mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \

} \

- acc = int128_add(acc, int128_make64(1 << 7)); \

+ mul = (mul >> 8) + ((mul >> 7) & 1); \

+ a += mul; \

} \

} \

mve_advance_vpt(env); \

- return int128_getlo(int128_rshift(acc, 8)); \

+ return a; \

-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)

-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)

+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)

+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)

-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)

+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)

-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)

-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)

+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)

+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)

/* Vector add across vector */

#define DO_VADDV(OP, ESIZE, TYPE) \

2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Add a test booting and quickly shutdown a raspi2 machine,

to test the power management model:

(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:

console: [ 0.000000] Booting Linux on physical CPU 0xf00

console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019

console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d

console: [ 0.000000] CPU: div instructions available: patching division code

console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache

console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B

...

console: Boot successful.

console: cat /proc/cpuinfo

console: / # cat /proc/cpuinfo

...

console: processor : 3

console: model name : ARMv7 Processor rev 5 (v7l)

console: BogoMIPS : 125.00

console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm

console: CPU implementer : 0x41

console: CPU architecture: 7

console: CPU variant : 0x0

console: CPU part : 0xc07

console: CPU revision : 5

console: Hardware : BCM2835

console: Revision : 0000

console: Serial : 0000000000000000

console: cat /proc/iomem

console: / # cat /proc/iomem

console: 00000000-3bffffff : System RAM

console: 00008000-00afffff : Kernel code

console: 00c00000-00d468ef : Kernel data

console: 3f006000-3f006fff : dwc_otg

console: 3f007000-3f007eff : /soc/dma@7e007000

console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880

console: 3f100000-3f100027 : /soc/watchdog@7e100000

console: 3f101000-3f102fff : /soc/cprman@7e101000

console: 3f200000-3f2000b3 : /soc/gpio@7e200000

PASS (24.59 s)

RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0

JOB TIME : 25.02 s

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>

Message-id: 20210531113837.1689775-1-f4bug@amsat.org

tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++

1 file changed, 43 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py

--- a/tests/acceptance/boot_linux_console.py

+++ b/tests/acceptance/boot_linux_console.py

from avocado import skip

from avocado import skipUnless

from avocado_qemu import Test

+from avocado_qemu import exec_command

from avocado_qemu import exec_command_and_wait_for_pattern

from avocado_qemu import interrupt_interactive_console_until_pattern

from avocado_qemu import wait_for_console_pattern

@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):

"""

self.do_test_arm_raspi2(0)

+ def test_arm_raspi2_initrd(self):

+ """

+ :avocado: tags=arch:arm

+ :avocado: tags=machine:raspi2

+ """

+ deb_url = ('http://archive.raspberrypi.org/debian/'

+ 'pool/main/r/raspberrypi-firmware/'

+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')

+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'

+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)

+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')

+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')

+

+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'

+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'

+ 'arm/rootfs-armv7a.cpio.gz')

+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'

+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)

+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')

+ archive.gzip_uncompress(initrd_path_gz, initrd_path)

+

+ self.vm.set_console()

+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +

+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '

+ 'panic=-1 noreboot ' +

+ 'dwc_otg.fiq_fsm_enable=0')

+ self.vm.add_args('-kernel', kernel_path,

+ '-dtb', dtb_path,

+ '-initrd', initrd_path,

+ '-append', kernel_command_line,

+ '-no-reboot')

+ self.vm.launch()

+ self.wait_for_console_pattern('Boot successful.')

+

+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',

+ 'BCM2835')

+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',

+ '/soc/cprman@7e101000')

+ exec_command(self, 'halt')

+ # Wait for VM to shut down gracefully

+ self.vm.wait()

+

def test_arm_exynos4210_initrd(self):

"""

:avocado: tags=arch:arm

2.20.1

Implement the MVE VADDLV insn; this is similar to VADDV, except

that it accumulates 32-bit elements into a 64-bit accumulator

stored in a pair of general-purpose registers.

target/arm/helper-mve.h | 3 ++

target/arm/mve.decode | 6 +++-

target/arm/mve_helper.c | 19 ++++++++++++

target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++

4 files changed, 90 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h

--- a/target/arm/helper-mve.h

+++ b/target/arm/helper-mve.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)

DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)

DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)

+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)

+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)

+

DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)

DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)

DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)

diff --git a/target/arm/mve.decode b/target/arm/mve.decode

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/mve.decode

+++ b/target/arm/mve.decode

@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar

VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar

# Vector add across vector

-VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo

+{

+ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo

+ VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \

+ rdahi=%rdahi rdalo=%rdalo

+}

# Predicate operations

%mask_22_13 22:1 13:3

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/mve_helper.c

+++ b/target/arm/mve_helper.c

@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)

DO_VADDV(vaddvuh, 2, uint16_t)

DO_VADDV(vaddvuw, 4, uint32_t)

+#define DO_VADDLV(OP, TYPE, LTYPE) \

+ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \

+ uint64_t ra) \

+ { \

+ uint16_t mask = mve_element_mask(env); \

+ unsigned e; \

+ TYPE *m = vm; \

+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \

+ if (mask & 1) { \

+ ra += (LTYPE)m[H4(e)]; \

+ } \

+ } \

+ mve_advance_vpt(env); \

+ return ra; \

+ } \

+

+DO_VADDLV(vaddlv_s, int32_t, int64_t)

+DO_VADDLV(vaddlv_u, uint32_t, uint64_t)

+

/* Shifts by immediate */

#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \

void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-mve.c

+++ b/target/arm/translate-mve.c

@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)

return true;

+static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)

+{

+ /*

+ * Vector Add Long Across Vector: accumulate the 32-bit

+ * elements of the vector into a 64-bit result stored in

+ * a pair of general-purpose registers.

+ * No need to check Qm's bank: it is only 3 bits in decode.

+ */

+ TCGv_ptr qm;

+ TCGv_i64 rda;

+ TCGv_i32 rdalo, rdahi;

+

+ if (!dc_isar_feature(aa32_mve, s)) {

+ return false;

+ }

+ /*

+ * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related

+ * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.

+ */

+ if (a->rdahi == 13 || a->rdahi == 15) {

+ return false;

+ }

+ if (!mve_eci_check(s) || !vfp_access_check(s)) {

+ return true;

+ }

+

+ /*

+ * This insn is subject to beat-wise execution. Partial execution

+ * of an A=0 (no-accumulate) insn which does not execute the first

+ * beat must start with the current value of RdaHi:RdaLo, not zero.

+ */

+ if (a->a || mve_skip_first_beat(s)) {

+ /* Accumulate input from RdaHi:RdaLo */

+ rda = tcg_temp_new_i64();

+ rdalo = load_reg(s, a->rdalo);

+ rdahi = load_reg(s, a->rdahi);

+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);

+ tcg_temp_free_i32(rdalo);

+ tcg_temp_free_i32(rdahi);

+ } else {

+ /* Accumulate starting at zero */

+ rda = tcg_const_i64(0);

+ }

+

+ qm = mve_qreg_ptr(a->qm);

+ if (a->u) {

+ gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);

+ } else {

+ gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);

+ }

+ tcg_temp_free_ptr(qm);

+

+ rdalo = tcg_temp_new_i32();

+ rdahi = tcg_temp_new_i32();

+ tcg_gen_extrl_i64_i32(rdalo, rda);

+ tcg_gen_extrh_i64_i32(rdahi, rda);

+ store_reg(s, a->rdalo, rdalo);

+ store_reg(s, a->rdahi, rdahi);

+ tcg_temp_free_i64(rda);

+ mve_update_eci(s);

+ return true;

+}

+

static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)

TCGv_ptr qd;

2.20.1

Implement the MVE shifts by immediate, which perform shifts

on a single general-purpose register.

These patterns overlap with the long-shift-by-immediates,

so we have to rearrange the grouping a little here.

target/arm/helper-mve.h | 3 ++

target/arm/translate.h | 1 +

target/arm/t32.decode | 31 ++++++++++++++-----

target/arm/mve_helper.c | 10 ++++++

target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++--

5 files changed, 104 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h

--- a/target/arm/helper-mve.h

+++ b/target/arm/helper-mve.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)

DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)

DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)

DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)

+

+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)

+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)

diff --git a/target/arm/translate.h b/target/arm/translate.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);

typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);

typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);

typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);

+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);

/**

* arm_tbflags_from_tb:

diff --git a/target/arm/t32.decode b/target/arm/t32.decode

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/t32.decode

+++ b/target/arm/t32.decode

&mve_shl_ri rdalo rdahi shim

&mve_shl_rr rdalo rdahi rm

+&mve_sh_ri rda shim

# rdahi: bits [3:1] from insn, bit 0 is 1

# rdalo: bits [3:1] from insn, bit 0 is 0

@@ -XXX,XX +XXX,XX @@

&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9

@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \

&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9

+@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \

+ &mve_sh_ri shim=%imm5_12_6

{

TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi

@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi

# the rest fall through (where ORR_rrri and MOV_rxri will end up

# handling them as r13 and r15 accesses with the same semantics as A32).

[

- LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri

- LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri

- ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri

+ {

+ UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri

+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri

+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri

+ }

- UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri

- URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri

- SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri

- SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri

+ {

+ URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri

+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri

+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri

+ }

+

+ {

+ SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri

+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri

+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri

+ }

+

+ {

+ SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri

+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri

+ }

LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr

ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/mve_helper.c

+++ b/target/arm/mve_helper.c

@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)

{

return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);

}

+

+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)

+{

+ return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);

+}

+

+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)

+{

+ return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);

+}

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)

static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)

{

- TCGv_i32 t = tcg_temp_new_i32();

+ TCGv_i32 t;

+ /* Handle shift by the input size for the benefit of trans_SRSHR_ri */

+ if (sh == 32) {

+ tcg_gen_movi_i32(d, 0);

+ return;

+ }

+ t = tcg_temp_new_i32();

tcg_gen_extract_i32(t, a, sh - 1, 1);

tcg_gen_sari_i32(d, a, sh);

tcg_gen_add_i32(d, d, t);

@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)

static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)

{

- TCGv_i32 t = tcg_temp_new_i32();

+ TCGv_i32 t;

+ /* Handle shift by the input size for the benefit of trans_URSHR_ri */

+ if (sh == 32) {

+ tcg_gen_extract_i32(d, a, sh - 1, 1);

+ return;

+ }

+ t = tcg_temp_new_i32();

tcg_gen_extract_i32(t, a, sh - 1, 1);

tcg_gen_shri_i32(d, a, sh);

tcg_gen_add_i32(d, d, t);

@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)

return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);

}

+static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)

+{

+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {

+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */

+ return false;

+ }

+ if (!dc_isar_feature(aa32_mve, s) ||

+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||

+ a->rda == 13 || a->rda == 15) {

+ /* These rda cases are UNPREDICTABLE; we choose to UNDEF */

+ unallocated_encoding(s);

+ return true;

+ }

+

+ if (a->shim == 0) {

+ a->shim = 32;

+ }

+ fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);

+

+ return true;

+}

+

+static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)

+{

+ return do_mve_sh_ri(s, a, gen_urshr32_i32);

+}

+

+static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)

+{

+ return do_mve_sh_ri(s, a, gen_srshr32_i32);

+}

+

+static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)

+{

+ gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));

+}

+

+static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)

+{

+ return do_mve_sh_ri(s, a, gen_mve_sqshl);

+}

+

+static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)

+{

+ gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));

+}

+

+static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)

+{

+ return do_mve_sh_ri(s, a, gen_mve_uqshl);

+}

+

/*

* Multiply and multiply accumulate

*/

2.20.1

Use dup_const() instead of bitfield_replicate() in

disas_simd_mod_imm().

(We can't replace the other use of bitfield_replicate() in this file,

in logic_imm_decode_wmask(), because that location needs to handle 2

and 4 bit elements, which dup_const() cannot.)

target/arm/translate-a64.c | 2 +-

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)

/* FMOV (vector, immediate) - half-precision */

imm = vfp_expand_imm(MO_16, abcdefgh);

/* now duplicate across the lanes */

- imm = bitfield_replicate(imm, 16);

+ imm = dup_const(MO_16, imm);

} else {

imm = asimd_imm_const(abcdefgh, cmode, is_neg);

2.20.1

Implement the MVE long shifts by register, which perform shifts on a

pair of general-purpose registers treated as a 64-bit quantity, with

the shift count in another general-purpose register, which might be

either positive or negative.

Like the long-shifts-by-immediate, these encodings sit in the space

that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.

Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and

also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),

we have to move the CSEL pattern into the same decodetree group.

target/arm/helper-mve.h | 6 +++

target/arm/translate.h | 1 +

target/arm/t32.decode | 16 +++++--

target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++

target/arm/translate.c | 69 ++++++++++++++++++++++++++++++

5 files changed, 182 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h

--- a/target/arm/helper-mve.h

+++ b/target/arm/helper-mve.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)

+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)

+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)

DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)

DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)

+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)

+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)

+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)

+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)

diff --git a/target/arm/translate.h b/target/arm/translate.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);

typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);

typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);

typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);

+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);

/**

* arm_tbflags_from_tb:

diff --git a/target/arm/t32.decode b/target/arm/t32.decode

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/t32.decode

+++ b/target/arm/t32.decode