Series comparison

-[PULL 00/24] target-arm queue
+[PULL 00/11] target-arm queue
-The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
+Just a collection of bug fixes this time around...
-  Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
+thanks
 -- PMM
 The following changes since commit 2a6ae69154542caa91dd17c40fd3f5ffbec300de:
   Merge tag 'pull-maintainer-ominbus-030723-1' of https://gitlab.com/stsquad/qemu into staging (2023-07-04 08:36:44 +0200)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230704
-for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
+for you to fetch changes up to 86a78272f094857b4eda79d721c116e93942aa9a:
-  target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
+  target/xtensa: Assert that interrupt level is within bounds (2023-07-04 14:27:08 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * more MVE instructions
+ * Add raw_writes ops for register whose write induce TLB maintenance
- * hw/gpio/gpio_pwr: use shutdown function for reboot
+ * hw/arm/sbsa-ref: use XHCI to replace EHCI
- * target/arm: Check NaN mode before silencing NaN
+ * Avoid splitting Zregs across lines in dump
- * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
+ * Dump ZA[] when active
- * hw/arm: Add basic power management to raspi.
+ * Fix SME full tile indexing
- * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
+ * Handle IC IVAU to improve compatibility with JITs
  * xlnx-canfd-test: Fix code coverity issues
  * gdbstub: Guard M-profile code with CONFIG_TCG
  * allwinner-sramc: Set class_size
  * target/xtensa: Assert that interrupt level is within bounds
 ----------------------------------------------------------------
-Joe Komlodi (1):
+Akihiko Odaki (1):
-      target/arm: Check NaN mode before silencing NaN
+      hw: arm: allwinner-sramc: Set class_size
-Maxim Uvarov (1):
+Eric Auger (1):
-      hw/gpio/gpio_pwr: use shutdown function for reboot
+      target/arm: Add raw_writes ops for register whose write induce TLB maintenance
-Nolan Leake (1):
+Fabiano Rosas (1):
-      hw/arm: Add basic power management to raspi.
+      target/arm: gdbstub: Guard M-profile code with CONFIG_TCG
-Patrick Venture (2):
+John Högberg (2):
-      docs/system/arm: Add quanta-q7l1-bmc reference
+      target/arm: Handle IC IVAU to improve compatibility with JITs
-      docs/system/arm: Add quanta-gbs-bmc reference
+      tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code
-Peter Maydell (18):
+Peter Maydell (1):
-      target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
+      target/xtensa: Assert that interrupt level is within bounds
       target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
       target/arm: Make asimd_imm_const() public
       target/arm: Use asimd_imm_const for A64 decode
       target/arm: Use dup_const() instead of bitfield_replicate()
       target/arm: Implement MVE logical immediate insns
       target/arm: Implement MVE vector shift left by immediate insns
       target/arm: Implement MVE vector shift right by immediate insns
       target/arm: Implement MVE VSHLL
       target/arm: Implement MVE VSRI, VSLI
       target/arm: Implement MVE VSHRN, VRSHRN
       target/arm: Implement MVE saturating narrowing shifts
       target/arm: Implement MVE VSHLC
       target/arm: Implement MVE VADDLV
       target/arm: Implement MVE long shifts by immediate
       target/arm: Implement MVE long shifts by register
       target/arm: Implement MVE shifts by immediate
       target/arm: Implement MVE shifts by register
-Philippe Mathieu-Daudé (1):
+Richard Henderson (3):
-      tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
+      target/arm: Avoid splitting Zregs across lines in dump
       target/arm: Dump ZA[] when active
       target/arm: Fix SME full tile indexing
- docs/system/arm/aspeed.rst             |   1 +
+Vikram Garhwal (1):
- docs/system/arm/nuvoton.rst            |   5 +-
+      tests/qtest: xlnx-canfd-test: Fix code coverity issues
  include/hw/arm/bcm2835_peripherals.h   |   3 +-
  include/hw/misc/bcm2835_powermgt.h     |  29 ++
  target/arm/helper-mve.h                | 108 +++++++
  target/arm/translate.h                 |  41 +++
  target/arm/mve.decode                  | 177 ++++++++++-
  target/arm/t32.decode                  |  71 ++++-
  hw/arm/bcm2835_peripherals.c           |  13 +-
  hw/gpio/gpio_pwr.c                     |   2 +-
  hw/misc/bcm2835_powermgt.c             | 160 ++++++++++
  target/arm/helper-a64.c                |  12 +-
  target/arm/mve_helper.c                | 524 +++++++++++++++++++++++++++++++--
  target/arm/translate-a64.c             |  86 +-----
  target/arm/translate-mve.c             | 261 +++++++++++++++-
  target/arm/translate-neon.c            |  81 -----
  target/arm/translate.c                 | 327 +++++++++++++++++++-
  target/arm/vfp_helper.c                |  24 +-
  hw/misc/meson.build                    |   1 +
  tests/acceptance/boot_linux_console.py |  43 +++
 files changed, 1760 insertions(+), 209 deletions(-)
  create mode 100644 include/hw/misc/bcm2835_powermgt.h
  create mode 100644 hw/misc/bcm2835_powermgt.c
+Yuquan Wang (1):
+      hw/arm/sbsa-ref: use XHCI to replace EHCI
+ docs/system/arm/sbsa.rst          |   5 +-
+ hw/arm/sbsa-ref.c                 |  23 +++--
+ hw/misc/allwinner-sramc.c         |   1 +
+ target/arm/cpu.c                  |  65 ++++++++-----
+ target/arm/gdbstub.c              |   4 +
+ target/arm/helper.c               |  70 +++++++++++---
+ target/arm/tcg/translate-sme.c    |  24 +++--
+ target/xtensa/exc_helper.c        |   3 +
+ tests/qtest/xlnx-canfd-test.c     |  33 +++----
+ tests/tcg/aarch64/icivau.c        | 189 ++++++++++++++++++++++++++++++++++++++
+ tests/tcg/aarch64/sme-outprod1.c  |  83 +++++++++++++++++
+ hw/arm/Kconfig                    |   2 +-
+ tests/tcg/aarch64/Makefile.target |  13 ++-
+files changed, 436 insertions(+), 79 deletions(-)
+ create mode 100644 tests/tcg/aarch64/icivau.c
+ create mode 100644 tests/tcg/aarch64/sme-outprod1.c

-[PULL 05/24] target/arm: Check NaN mode before silencing NaN
+[PULL 01/11] target/arm: Add raw_writes ops for register whose write induce TLB maintenance
-From: Joe Komlodi <joe.komlodi@xilinx.com>
+From: Eric Auger <eric.auger@redhat.com>
-If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
+Some registers whose 'cooked' writefns induce TLB maintenance do
-FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
+not have raw_writefn ops defined. If only the writefn ops is set
-assert due to fpst->default_nan_mode being set.
+(ie. no raw_writefn is provided), it is assumed the cooked also
 work as the raw one. For those registers it is not obvious the
 tlb_flush works on KVM mode so better/safer setting the raw write.
-To avoid this, we check to see what NaN mode we're running in before we call
+Signed-off-by: Eric Auger <eric.auger@redhat.com>
-floatxx_silence_nan().
+Suggested-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper-a64.c | 12 +++++++++---
+ target/arm/helper.c | 23 +++++++++++++----------
- target/arm/vfp_helper.c | 24 ++++++++++++++++++------
+file changed, 13 insertions(+), 10 deletions(-)
 files changed, 27 insertions(+), 9 deletions(-)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
+--- a/target/arm/helper.c
-+++ b/target/arm/helper-a64.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
-         float16 nan = a;
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
-         if (float16_is_signaling_nan(a, fpst)) {
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
-             float_raise(float_flag_invalid, fpst);
+       .fgt = FGT_TTBR0_EL1,
--            nan = float16_silence_nan(a, fpst);
+-      .writefn = vmsa_ttbr_write, .resetvalue = 0,
-+            if (!fpst->default_nan_mode) {
++      .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write,
-+                nan = float16_silence_nan(a, fpst);
+       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
-+            }
+                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
-         }
+     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
-         if (fpst->default_nan_mode) {
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
-             nan = float16_default_nan(fpst);
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
-@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
+       .fgt = FGT_TTBR1_EL1,
-         float32 nan = a;
+-      .writefn = vmsa_ttbr_write, .resetvalue = 0,
-         if (float32_is_signaling_nan(a, fpst)) {
++      .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write,
-             float_raise(float_flag_invalid, fpst);
+       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
--            nan = float32_silence_nan(a, fpst);
+                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
-+            if (!fpst->default_nan_mode) {
+     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
-+                nan = float32_silence_nan(a, fpst);
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
-+            }
+       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
-         }
+       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
-         if (fpst->default_nan_mode) {
+                              offsetof(CPUARMState, cp15.ttbr0_ns) },
-             nan = float32_default_nan(fpst);
+-      .writefn = vmsa_ttbr_write, },
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
++      .writefn = vmsa_ttbr_write, .raw_writefn = raw_write },
-         float64 nan = a;
+     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
-         if (float64_is_signaling_nan(a, fpst)) {
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
-             float_raise(float_flag_invalid, fpst);
+       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
--            nan = float64_silence_nan(a, fpst);
+       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
-+            if (!fpst->default_nan_mode) {
+                              offsetof(CPUARMState, cp15.ttbr1_ns) },
-+                nan = float64_silence_nan(a, fpst);
+-      .writefn = vmsa_ttbr_write, },
-+            }
++      .writefn = vmsa_ttbr_write, .raw_writefn = raw_write },
-         }
+ };
-         if (fpst->default_nan_mode) {
-             nan = float64_default_nan(fpst);
+ static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
-diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
-index XXXXXXX..XXXXXXX 100644
+       .type = ARM_CP_IO,
---- a/target/arm/vfp_helper.c
+       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
-+++ b/target/arm/vfp_helper.c
+       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
+-      .writefn = hcr_write },
-         float16 nan = f16;
++      .writefn = hcr_write, .raw_writefn = raw_write },
-         if (float16_is_signaling_nan(f16, fpst)) {
+     { .name = "HCR", .state = ARM_CP_STATE_AA32,
-             float_raise(float_flag_invalid, fpst);
+       .type = ARM_CP_ALIAS | ARM_CP_IO,
--            nan = float16_silence_nan(f16, fpst);
+       .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
-+            if (!fpst->default_nan_mode) {
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
-+                nan = float16_silence_nan(f16, fpst);
+     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
-+            }
+       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
-         }
+       .access = PL2_RW, .writefn = vmsa_tcr_el12_write,
-         if (fpst->default_nan_mode) {
++      .raw_writefn = raw_write,
-             nan =  float16_default_nan(fpst);
+       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
-@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
+     { .name = "VTCR", .state = ARM_CP_STATE_AA32,
-         float32 nan = f32;
+       .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
-         if (float32_is_signaling_nan(f32, fpst)) {
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
-             float_raise(float_flag_invalid, fpst);
+       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
--            nan = float32_silence_nan(f32, fpst);
+       .access = PL2_RW, .accessfn = access_el3_aa32ns,
-+            if (!fpst->default_nan_mode) {
+       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
-+                nan = float32_silence_nan(f32, fpst);
+-      .writefn = vttbr_write },
-+            }
++      .writefn = vttbr_write, .raw_writefn = raw_write },
-         }
+     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
-         if (fpst->default_nan_mode) {
+       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
-             nan =  float32_default_nan(fpst);
+-      .access = PL2_RW, .writefn = vttbr_write,
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
++      .access = PL2_RW, .writefn = vttbr_write, .raw_writefn = raw_write,
-         float64 nan = f64;
+       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
-         if (float64_is_signaling_nan(f64, fpst)) {
+     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
-             float_raise(float_flag_invalid, fpst);
+       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
--            nan = float64_silence_nan(f64, fpst);
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
-+            if (!fpst->default_nan_mode) {
+       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
-+                nan = float64_silence_nan(f64, fpst);
+     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
-+            }
+       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
-         }
+-      .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write,
-         if (fpst->default_nan_mode) {
++      .access = PL2_RW, .resetvalue = 0,
-             nan =  float64_default_nan(fpst);
++      .writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write,
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
+       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
-         float16 nan = f16;
+     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
-         if (float16_is_signaling_nan(f16, s)) {
+       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
-             float_raise(float_flag_invalid, s);
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
--            nan = float16_silence_nan(f16, s);
+     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
-+            if (!s->default_nan_mode) {
+       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
-+                nan = float16_silence_nan(f16, fpstp);
+       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
-+            }
+-      .resetfn = scr_reset, .writefn = scr_write },
-         }
++      .resetfn = scr_reset, .writefn = scr_write, .raw_writefn = raw_write },
-         if (s->default_nan_mode) {
+     { .name = "SCR",  .type = ARM_CP_ALIAS | ARM_CP_NEWEL,
-             nan =  float16_default_nan(s);
+       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
-@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
+       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
-         float32 nan = f32;
+       .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
-         if (float32_is_signaling_nan(f32, s)) {
+-      .writefn = scr_write },
-             float_raise(float_flag_invalid, s);
++      .writefn = scr_write, .raw_writefn = raw_write },
--            nan = float32_silence_nan(f32, s);
+     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
-+            if (!s->default_nan_mode) {
+       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
-+                nan = float32_silence_nan(f32, fpstp);
+       .access = PL3_RW, .resetvalue = 0,
-+            }
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
-         }
+     { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
-         if (s->default_nan_mode) {
+       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
-             nan =  float32_default_nan(s);
+       .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
++      .raw_writefn = raw_write,
-         float64 nan = f64;
+       .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) },
-         if (float64_is_signaling_nan(f64, s)) {
+ #ifndef CONFIG_USER_ONLY
-             float_raise(float_flag_invalid, s);
+     { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64,
 -            nan = float64_silence_nan(f64, s);
 +            if (!s->default_nan_mode) {
 +                nan = float64_silence_nan(f64, fpstp);
 +            }
          }
          if (s->default_nan_mode) {
              nan =  float64_default_nan(s);
 --
-.20.1
+.34.1

-[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
+[PULL 02/11] hw/arm/sbsa-ref: use XHCI to replace EHCI
-Implement the MVE saturating shift-right-and-narrow insns
+From: Yuquan Wang <wangyuquan1236@phytium.com.cn>
 VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
-do_srshr() is borrowed from sve_helper.c.
+The current sbsa-ref cannot use EHCI controller which is only
 able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
 Hence, this uses XHCI to provide a usb controller with 64-bit
 DMA capablity instead of EHCI.
+We bump the platform version to 0.3 with this change.  Although the
+hardware at the USB controller address changes, the firmware and
+Linux can both cope with this -- on an older non-XHCI-aware
+firmware/kernel setup the probe routine simply fails and the guest
+proceeds without any USB.  (This isn't a loss of functionality,
+because the old USB controller never worked in the first place.) So
+we can call this a backwards-compatible change and only bump the
+minor version.
+Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn>
+Message-id: 20230621103847.447508-2-wangyuquan1236@phytium.com.cn
+[PMM: tweaked commit message; add line to docs about what
+ changes in platform version 0.3]
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    |  30 +++++++++++
+ docs/system/arm/sbsa.rst |  5 ++++-
- target/arm/mve.decode      |  28 ++++++++++
+ hw/arm/sbsa-ref.c        | 23 +++++++++++++----------
- target/arm/mve_helper.c    | 104 +++++++++++++++++++++++++++++++++++++
+ hw/arm/Kconfig           |  2 +-
- target/arm/translate-mve.c |  12 +++++
+files changed, 18 insertions(+), 12 deletions(-)
 files changed, 174 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/docs/system/arm/sbsa.rst
-+++ b/target/arm/helper-mve.h
++++ b/docs/system/arm/sbsa.rst
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ The ``sbsa-ref`` board supports:
- DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+   - A configurable number of AArch64 CPUs
- DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+   - GIC version 3
- DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+   - System bus AHCI controller
 -  - System bus EHCI controller
 +  - System bus XHCI controller
    - CDROM and hard disc on AHCI bus
    - E1000E ethernet card on PCIe bus
    - Bochs display adapter on PCIe bus
@@ -XXX,XX +XXX,XX @@ Platform version changes:
 .2
    GIC ITS information is present in devicetree.
 +
-+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++0.3
-+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++  The USB controller is an XHCI device, not EHCI
-+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 +DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
+--- a/hw/arm/sbsa-ref.c
-+++ b/target/arm/mve.decode
++++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
+@@ -XXX,XX +XXX,XX @@
- VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
+ #include "hw/pci-host/gpex.h"
- VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
+ #include "hw/qdev-properties.h"
- VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
+ #include "hw/usb.h"
-+
++#include "hw/usb/xhci.h"
-+VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
+ #include "hw/char/pl011.h"
-+VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
+ #include "hw/watchdog/sbsa_gwdt.h"
-+VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
+ #include "net/net.h"
-+VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
+@@ -XXX,XX +XXX,XX @@ enum {
-+VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
+     SBSA_SECURE_UART_MM,
-+VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
+     SBSA_SECURE_MEM,
-+VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
+     SBSA_AHCI,
-+VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
+-    SBSA_EHCI,
-+
++    SBSA_XHCI,
-+VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+ };
-+VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
-+VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+ struct SBSAMachineState {
-+VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
+@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sbsa_ref_memmap[] = {
-+
+     [SBSA_SMMU] =               { 0x60050000, 0x00020000 },
-+VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
+     /* Space here reserved for more SMMUs */
-+VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
+     [SBSA_AHCI] =               { 0x60100000, 0x00010000 },
-+VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
+-    [SBSA_EHCI] =               { 0x60110000, 0x00010000 },
-+VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
++    [SBSA_XHCI] =               { 0x60110000, 0x00010000 },
-+VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
+     /* Space here reserved for other devices */
-+VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
+     [SBSA_PCIE_PIO] =           { 0x7fff0000, 0x00010000 },
-+VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
+     /* 32-bit address PCIE MMIO space */
-+VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
+@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
-+
+     [SBSA_SECURE_UART] = 8,
-+VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+     [SBSA_SECURE_UART_MM] = 9,
-+VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+     [SBSA_AHCI] = 10,
-+VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+-    [SBSA_EHCI] = 11,
-+VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
++    [SBSA_XHCI] = 11,
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
+     [SBSA_SMMU] = 12, /* ... to 15 */
-index XXXXXXX..XXXXXXX 100644
+     [SBSA_GWDT_WS0] = 16,
---- a/target/arm/mve_helper.c
+ };
-+++ b/target/arm/mve_helper.c
+@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
-@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
+      *                        fw compatibility.
       */
      qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
 -    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 2);
 +    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3);
      if (ms->numa_state->have_numa_distance) {
          int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ static void create_ahci(const SBSAMachineState *sms)
      }
  }
-+static inline int64_t do_srshr(int64_t x, unsigned sh)
+-static void create_ehci(const SBSAMachineState *sms)
-+{
++static void create_xhci(const SBSAMachineState *sms)
-+    if (likely(sh < 64)) {
+ {
-+        return (x >> sh) + ((x >> (sh - 1)) & 1);
+-    hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
-+    } else {
+-    int irq = sbsa_ref_irqmap[SBSA_EHCI];
-+        /* Rounding the sign bit always produces 0. */
++    hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base;
-+        return 0;
++    int irq = sbsa_ref_irqmap[SBSA_XHCI];
-+    }
++    DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
-+}
-+
+-    sysbus_create_simple("platform-ehci-usb", base,
- DO_VSHRN_ALL(vshrn, DO_SHR)
+-                         qdev_get_gpio_in(sms->gic, irq));
- DO_VSHRN_ALL(vrshrn, do_urshr)
++    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-+
++    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
-+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
++    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
-+                                 bool *satp)
+ }
-+{
-+    if (val > max) {
+ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
-+        *satp = true;
+@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
-+        return max;
-+    } else if (val < min) {
+     create_ahci(sms);
-+        *satp = true;
-+        return min;
+-    create_ehci(sms);
-+    } else {
++    create_xhci(sms);
-+        return val;
-+    }
+     create_pcie(sms);
-+}
-+
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 +/* Saturating narrowing right shifts */
 +#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)   \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 +                                void *vm, uint32_t shift)       \
 +    {                                                           \
 +        LTYPE *m = vm;                                          \
 +        TYPE *d = vd;                                           \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        bool qc = false;                                        \
 +        unsigned le;                                            \
 +        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
 +            bool sat = false;                                   \
 +            TYPE r = FN(m[H##LESIZE(le)], shift, &sat);         \
 +            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
 +            qc |= sat && (mask & 1 << (TOP * ESIZE));           \
 +        }                                                       \
 +        if (qc) {                                               \
 +            env->vfp.qc[0] = qc;                                \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +    }
 +
 +#define DO_VSHRN_SAT_UB(BOP, TOP, FN)                           \
 +    DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN)       \
 +    DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
 +
 +#define DO_VSHRN_SAT_UH(BOP, TOP, FN)                           \
 +    DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN)      \
 +    DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
 +
 +#define DO_VSHRN_SAT_SB(BOP, TOP, FN)                           \
 +    DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN)         \
 +    DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
 +
 +#define DO_VSHRN_SAT_SH(BOP, TOP, FN)                           \
 +    DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN)        \
 +    DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
 +
 +#define DO_SHRN_SB(N, M, SATP)                                  \
 +    do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
 +#define DO_SHRN_UB(N, M, SATP)                                  \
 +    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
 +#define DO_SHRUN_B(N, M, SATP)                                  \
 +    do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
 +
 +#define DO_SHRN_SH(N, M, SATP)                                  \
 +    do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
 +#define DO_SHRN_UH(N, M, SATP)                                  \
 +    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
 +#define DO_SHRUN_H(N, M, SATP)                                  \
 +    do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
 +
 +#define DO_RSHRN_SB(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
 +#define DO_RSHRN_UB(N, M, SATP)                                 \
 +    do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
 +#define DO_RSHRUN_B(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
 +
 +#define DO_RSHRN_SH(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
 +#define DO_RSHRN_UH(N, M, SATP)                                 \
 +    do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
 +#define DO_RSHRUN_H(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
 +
 +DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
 +DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
 +DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
 +DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
 +DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
 +DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
 +
 +DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
 +DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
 +DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
 +DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
 +DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
 +DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
+--- a/hw/arm/Kconfig
-+++ b/target/arm/translate-mve.c
++++ b/hw/arm/Kconfig
-@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
+@@ -XXX,XX +XXX,XX @@ config SBSA_REF
- DO_2SHIFT_N(VSHRNT, vshrnt)
+     select PL011 # UART
- DO_2SHIFT_N(VRSHRNB, vrshrnb)
+     select PL031 # RTC
- DO_2SHIFT_N(VRSHRNT, vrshrnt)
+     select PL061 # GPIO
-+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
+-    select USB_EHCI_SYSBUS
-+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
++    select USB_XHCI_SYSBUS
-+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
+     select WDT_SBSA
-+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
+     select BOCHS_DISPLAY
-+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
 +DO_2SHIFT_N(VQSHRUNT, vqshrunt)
 +DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
 +DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
 +DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
 +DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
 +DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
 +DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
 --
-.20.1
+.34.1

-[PULL 24/24] target/arm: Implement MVE shifts by register
+[PULL 03/11] target/arm: Avoid splitting Zregs across lines in dump
-Implement the MVE shifts by register, which perform
+From: Richard Henderson <richard.henderson@linaro.org>
 shifts on a single general-purpose register.
+Allow the line length to extend to 548 columns.  While annoyingly wide,
+it's still less confusing than the continuations we print.  Also, the
+default VL used by Linux (and max for A64FX) uses only 140 columns.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230622151201.1578522-2-richard.henderson@linaro.org
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h |  2 ++
+ target/arm/cpu.c | 36 ++++++++++++++----------------------
- target/arm/translate.h  |  1 +
+file changed, 14 insertions(+), 22 deletions(-)
  target/arm/t32.decode   | 18 ++++++++++++++----
  target/arm/mve_helper.c | 10 ++++++++++
  target/arm/translate.c  | 30 ++++++++++++++++++++++++++++++
 files changed, 57 insertions(+), 4 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/cpu.c
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
+@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+     ARMCPU *cpu = ARM_CPU(cs);
- DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
+     CPUARMState *env = &cpu->env;
- DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
+     uint32_t psr = pstate_read(env);
-+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
+-    int i;
-+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
++    int i, j;
-diff --git a/target/arm/translate.h b/target/arm/translate.h
+     int el = arm_current_el(env);
-index XXXXXXX..XXXXXXX 100644
+     const char *ns_status;
---- a/target/arm/translate.h
+     bool sve;
-+++ b/target/arm/translate.h
+@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
  typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
  typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
  typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
 +typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
  /**
   * arm_tbflags_from_tb:
 diff --git a/target/arm/t32.decode b/target/arm/t32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/t32.decode
 +++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@
  &mve_shl_ri      rdalo rdahi shim
  &mve_shl_rr      rdalo rdahi rm
  &mve_sh_ri       rda shim
 +&mve_sh_rr       rda rm
  # rdahi: bits [3:1] from insn, bit 0 is 1
  # rdalo: bits [3:1] from insn, bit 0 is 0
@@ -XXX,XX +XXX,XX @@
                   &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
  @mve_sh_ri       ....... .... . rda:4 . ... ... . .. .. .... \
                   &mve_sh_ri shim=%imm5_12_6
 +@mve_sh_rr       ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
  {
    TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
        SQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
      }
--    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
+     if (sve) {
--    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
+-        int j, zcr_len = sve_vqm1_for_el(env, el);
--    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
++        int zcr_len = sve_vqm1_for_el(env, el);
--    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
-+    {
+         for (i = 0; i <= FFR_PRED_NUM; i++) {
-+      UQRSHL_rr    1110101 0010 1 ....  ....  1111 0000 1101  @mve_sh_rr
+             bool eol;
-+      LSLL_rr      1110101 0010 1 ... 0 .... ... 1 0000 1101  @mve_shl_rr
+@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-+      UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101  @mve_shl_rr
+             }
-+    }
+         }
-+
-+    {
+-        for (i = 0; i < 32; i++) {
-+      SQRSHR_rr    1110101 0010 1 ....  ....  1111 0010 1101  @mve_sh_rr
+-            if (zcr_len == 0) {
-+      ASRL_rr      1110101 0010 1 ... 0 .... ... 1 0010 1101  @mve_shl_rr
++        if (zcr_len == 0) {
-+      SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101  @mve_shl_rr
++            /*
-+    }
++             * With vl=16, there are only 37 columns per register,
-+
++             * so output two registers per line.
-     UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
++             */
-     SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
++            for (i = 0; i < 32; i++) {
-   ]
+                 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
+                              i, env->vfp.zregs[i].d[1],
-index XXXXXXX..XXXXXXX 100644
+                              env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
---- a/target/arm/mve_helper.c
+-            } else if (zcr_len == 1) {
-+++ b/target/arm/mve_helper.c
+-                qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
+-                             ":%016" PRIx64 ":%016" PRIx64 "\n",
- {
+-                             i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
-     return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
+-                             env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
- }
+-            } else {
-+
++            }
-+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
++        } else {
-+{
++            for (i = 0; i < 32; i++) {
-+    return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
++                qemu_fprintf(f, "Z%02d=", i);
-+}
+                 for (j = zcr_len; j >= 0; j--) {
-+
+-                    bool odd = (zcr_len - j) % 2 != 0;
-+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
+-                    if (j == zcr_len) {
-+{
+-                        qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
-+    return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
+-                    } else if (!odd) {
-+}
+-                        if (j > 0) {
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+-                            qemu_fprintf(f, "   [%x-%x]=", j, j - 1);
-index XXXXXXX..XXXXXXX 100644
+-                        } else {
---- a/target/arm/translate.c
+-                            qemu_fprintf(f, "     [%x]=", j);
-+++ b/target/arm/translate.c
+-                        }
-@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
+-                    }
-     return do_mve_sh_ri(s, a, gen_mve_uqshl);
+                     qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
- }
+                                  env->vfp.zregs[i].d[j * 2 + 1],
+-                                 env->vfp.zregs[i].d[j * 2],
-+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
+-                                 odd || j == 0 ? "\n" : ":");
-+{
++                                 env->vfp.zregs[i].d[j * 2 + 0],
-+    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
++                                 j ? ":" : "\n");
-+        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
+                 }
-+        return false;
+             }
-+    }
+         }
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
 +        a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
 +        a->rm == a->rda) {
 +        /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
 +    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
 +    fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
 +    return true;
 +}
 +
 +static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
 +{
 +    return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
 +}
 +
 +static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
 +{
 +    return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
 +}
 +
  /*
   * Multiply and multiply accumulate
   */
 --
-.20.1
+.34.1

-[PULL 20/24] target/arm: Implement MVE VADDLV
+[PULL 04/11] target/arm: Dump ZA[] when active
-Implement the MVE VADDLV insn; this is similar to VADDV, except
+From: Richard Henderson <richard.henderson@linaro.org>
 that it accumulates 32-bit elements into a 64-bit accumulator
 stored in a pair of general-purpose registers.
+Always print each matrix row whole, one per line, so that we
+get the entire matrix in the proper shape.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230622151201.1578522-3-richard.henderson@linaro.org
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    |  3 ++
+ target/arm/cpu.c | 18 ++++++++++++++++++
- target/arm/mve.decode      |  6 +++-
+file changed, 18 insertions(+)
  target/arm/mve_helper.c    | 19 ++++++++++++
  target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
 files changed, 90 insertions(+), 1 deletion(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/cpu.c
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
- DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
+                          i, q[1], q[0], (i & 1 ? "\n" : " "));
- DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
+         }
+     }
 +DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
 +DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
 +
- DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
++    if (cpu_isar_feature(aa64_sme, cpu) &&
- DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
++        FIELD_EX64(env->svcr, SVCR, ZA) &&
- DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
++        sme_exception_el(env, el) == 0) {
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
++        int zcr_len = sve_vqm1_for_el_sm(env, el, true);
-index XXXXXXX..XXXXXXX 100644
++        int svl = (zcr_len + 1) * 16;
---- a/target/arm/mve.decode
++        int svl_lg10 = svl < 100 ? 2 : 3;
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar   1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
  VQRDMULH_scalar  1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
  # Vector add across vector
 -VADDV            111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
 +{
 +  VADDV          111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
 +  VADDLV         111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
 +                 rdahi=%rdahi rdalo=%rdalo
 +}
  # Predicate operations
  %mask_22_13      22:1 13:3
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
  DO_VADDV(vaddvuh, 2, uint16_t)
  DO_VADDV(vaddvuw, 4, uint32_t)
 +#define DO_VADDLV(OP, TYPE, LTYPE)                              \
 +    uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
 +                                    uint64_t ra)                \
 +    {                                                           \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned e;                                             \
 +        TYPE *m = vm;                                           \
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {              \
 +            if (mask & 1) {                                     \
 +                ra += (LTYPE)m[H4(e)];                          \
 +            }                                                   \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +        return ra;                                              \
 +    }                                                           \
 +
-+DO_VADDLV(vaddlv_s, int32_t, int64_t)
++        for (i = 0; i < svl; i++) {
-+DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
++            qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i);
-+
++            for (j = zcr_len; j >= 0; --j) {
- /* Shifts by immediate */
++                qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c",
- #define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
++                             env->zarray[i].d[2 * j + 1],
-     void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
++                             env->zarray[i].d[2 * j],
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
++                             j ? ':' : '\n');
-index XXXXXXX..XXXXXXX 100644
++            }
---- a/target/arm/translate-mve.c
++        }
-+++ b/target/arm/translate-mve.c
++    }
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
      return true;
  }
-+static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
+ #else
 +{
 +    /*
 +     * Vector Add Long Across Vector: accumulate the 32-bit
 +     * elements of the vector into a 64-bit result stored in
 +     * a pair of general-purpose registers.
 +     * No need to check Qm's bank: it is only 3 bits in decode.
 +     */
 +    TCGv_ptr qm;
 +    TCGv_i64 rda;
 +    TCGv_i32 rdalo, rdahi;
 +
 +    if (!dc_isar_feature(aa32_mve, s)) {
 +        return false;
 +    }
 +    /*
 +     * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
 +     * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
 +     */
 +    if (a->rdahi == 13 || a->rdahi == 15) {
 +        return false;
 +    }
 +    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    /*
 +     * This insn is subject to beat-wise execution. Partial execution
 +     * of an A=0 (no-accumulate) insn which does not execute the first
 +     * beat must start with the current value of RdaHi:RdaLo, not zero.
 +     */
 +    if (a->a || mve_skip_first_beat(s)) {
 +        /* Accumulate input from RdaHi:RdaLo */
 +        rda = tcg_temp_new_i64();
 +        rdalo = load_reg(s, a->rdalo);
 +        rdahi = load_reg(s, a->rdahi);
 +        tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
 +        tcg_temp_free_i32(rdalo);
 +        tcg_temp_free_i32(rdahi);
 +    } else {
 +        /* Accumulate starting at zero */
 +        rda = tcg_const_i64(0);
 +    }
 +
 +    qm = mve_qreg_ptr(a->qm);
 +    if (a->u) {
 +        gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
 +    } else {
 +        gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
 +    }
 +    tcg_temp_free_ptr(qm);
 +
 +    rdalo = tcg_temp_new_i32();
 +    rdahi = tcg_temp_new_i32();
 +    tcg_gen_extrl_i64_i32(rdalo, rda);
 +    tcg_gen_extrh_i64_i32(rdahi, rda);
 +    store_reg(s, a->rdalo, rdalo);
 +    store_reg(s, a->rdahi, rdahi);
 +    tcg_temp_free_i64(rda);
 +    mve_update_eci(s);
 +    return true;
 +}
 +
  static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
  {
      TCGv_ptr qd;
 --
-.20.1
+.34.1

-[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
+[PULL 05/11] target/arm: Fix SME full tile indexing
-In do_ldst(), the calculation of the offset needs to be based on the
+From: Richard Henderson <richard.henderson@linaro.org>
-size of the memory access, not the size of the elements in the
-vector.  This meant we were getting it wrong for the widening and
+For the outer product set of insns, which take an entire matrix
-narrowing variants of the various VLDR and VSTR insns.
+tile as output, the argument is not a combined tile+column.
+Therefore using get_tile_rowcol was incorrect, as we extracted
 the tile number from itself.
 The test case relies only on assembler support for SME, since
 no release of GCC recognizes -march=armv9-a+sme yet.
 Cc: qemu-stable@nongnu.org
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1620
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230622151201.1578522-5-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
 ---
- target/arm/translate-mve.c | 17 +++++++++--------
+ target/arm/tcg/translate-sme.c    | 24 ++++++---
-file changed, 9 insertions(+), 8 deletions(-)
+ tests/tcg/aarch64/sme-outprod1.c  | 83 +++++++++++++++++++++++++++++++
+ tests/tcg/aarch64/Makefile.target | 10 ++--
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
+files changed, 108 insertions(+), 9 deletions(-)
  create mode 100644 tests/tcg/aarch64/sme-outprod1.c
 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
+--- a/target/arm/tcg/translate-sme.c
-+++ b/target/arm/translate-mve.c
++++ b/target/arm/tcg/translate-sme.c
-@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs,
-     }
+     return addr;
  }
--static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
++/*
-+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
++ * Resolve tile.size[0] to a host pointer.
-+                    unsigned msize)
++ * Used by e.g. outer product insns where we require the entire tile.
 + */
 +static TCGv_ptr get_tile(DisasContext *s, int esz, int tile)
 +{
 +    TCGv_ptr addr = tcg_temp_new_ptr();
 +    int offset;
 +
 +    offset = tile * sizeof(ARMVectorReg) + offsetof(CPUARMState, zarray);
 +
 +    tcg_gen_addi_ptr(addr, cpu_env, offset);
 +    return addr;
 +}
 +
  static bool trans_ZERO(DisasContext *s, arg_ZERO *a)
  {
-     TCGv_i32 addr;
+     if (!dc_isar_feature(aa64_sme, s)) {
-     uint32_t offset;
+@@ -XXX,XX +XXX,XX @@ static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz,
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
          return true;
      }
--    offset = a->imm << a->size;
+-    /* Sum XZR+zad to find ZAd. */
-+    offset = a->imm << msize;
+-    za = get_tile_rowcol(s, esz, 31, a->zad, false);
-     if (!a->a) {
++    za = get_tile(s, esz, a->zad);
-         offset = -offset;
+     zn = vec_full_reg_ptr(s, a->zn);
      pn = pred_full_reg_ptr(s, a->pn);
      pm = pred_full_reg_ptr(s, a->pm);
@@ -XXX,XX +XXX,XX @@ static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz,
          return true;
      }
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
-         { gen_helper_mve_vstrw, gen_helper_mve_vldrw },
+-    /* Sum XZR+zad to find ZAd. */
-         { NULL, NULL }
+-    za = get_tile_rowcol(s, esz, 31, a->zad, false);
-     };
++    za = get_tile(s, esz, a->zad);
--    return do_ldst(s, a, ldstfns[a->size][a->l]);
+     zn = vec_full_reg_ptr(s, a->zn);
-+    return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
+     zm = vec_full_reg_ptr(s, a->zm);
- }
+     pn = pred_full_reg_ptr(s, a->pn);
+@@ -XXX,XX +XXX,XX @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
--#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST)                  \
+         return true;
 +#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE)           \
      static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
      {                                                           \
          static MVEGenLdStFn * const ldstfns[2][2] = {           \
              { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
              { NULL, gen_helper_mve_##ULD },                     \
          };                                                      \
 -        return do_ldst(s, a, ldstfns[a->u][a->l]);              \
 +        return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE);       \
      }
--DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
+-    /* Sum XZR+zad to find ZAd. */
--DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
+-    za = get_tile_rowcol(s, esz, 31, a->zad, false);
--DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
++    za = get_tile(s, esz, a->zad);
-+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
+     zn = vec_full_reg_ptr(s, a->zn);
-+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
+     zm = vec_full_reg_ptr(s, a->zm);
-+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
+     pn = pred_full_reg_ptr(s, a->pn);
+diff --git a/tests/tcg/aarch64/sme-outprod1.c b/tests/tcg/aarch64/sme-outprod1.c
- static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
+new file mode 100644
- {
+index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/tcg/aarch64/sme-outprod1.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SME outer product, 1 x 1.
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + */
 +
 +#include <stdio.h>
 +
 +extern void foo(float *dst);
 +
 +asm(
 +"    .arch_extension sme\n"
 +"    .type foo, @function\n"
 +"foo:\n"
 +"    stp x29, x30, [sp, -80]!\n"
 +"    mov x29, sp\n"
 +"    stp d8, d9, [sp, 16]\n"
 +"    stp d10, d11, [sp, 32]\n"
 +"    stp d12, d13, [sp, 48]\n"
 +"    stp d14, d15, [sp, 64]\n"
 +"    smstart\n"
 +"    ptrue p0.s, vl4\n"
 +"    fmov z0.s, #1.0\n"
 +/*
 + * An outer product of a vector of 1.0 by itself should be a matrix of 1.0.
 + * Note that we are using tile 1 here (za1.s) rather than tile 0.
 + */
 +"    zero {za}\n"
 +"    fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n"
 +/*
 + * Read the first 4x4 sub-matrix of elements from tile 1:
 + * Note that za1h should be interchangable here.
 + */
 +"    mov w12, #0\n"
 +"    mova z0.s, p0/m, za1v.s[w12, #0]\n"
 +"    mova z1.s, p0/m, za1v.s[w12, #1]\n"
 +"    mova z2.s, p0/m, za1v.s[w12, #2]\n"
 +"    mova z3.s, p0/m, za1v.s[w12, #3]\n"
 +/*
 + * And store them to the input pointer (dst in the C code):
 + */
 +"    st1w {z0.s}, p0, [x0]\n"
 +"    add x0, x0, #16\n"
 +"    st1w {z1.s}, p0, [x0]\n"
 +"    add x0, x0, #16\n"
 +"    st1w {z2.s}, p0, [x0]\n"
 +"    add x0, x0, #16\n"
 +"    st1w {z3.s}, p0, [x0]\n"
 +"    smstop\n"
 +"    ldp d8, d9, [sp, 16]\n"
 +"    ldp d10, d11, [sp, 32]\n"
 +"    ldp d12, d13, [sp, 48]\n"
 +"    ldp d14, d15, [sp, 64]\n"
 +"    ldp x29, x30, [sp], 80\n"
 +"    ret\n"
 +"    .size foo, . - foo"
 +);
 +
 +int main()
 +{
 +    float dst[16];
 +    int i, j;
 +
 +    foo(dst);
 +
 +    for (i = 0; i < 16; i++) {
 +        if (dst[i] != 1.0f) {
 +            break;
 +        }
 +    }
 +
 +    if (i == 16) {
 +        return 0; /* success */
 +    }
 +
 +    /* failure */
 +    for (i = 0; i < 4; ++i) {
 +        for (j = 0; j < 4; ++j) {
 +            printf("%f ", (double)dst[i * 4 + j]);
 +        }
 +        printf("\n");
 +    }
 +    return 1;
 +}
 diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/tcg/aarch64/Makefile.target
 +++ b/tests/tcg/aarch64/Makefile.target
@@ -XXX,XX +XXX,XX @@ config-cc.mak: Makefile
          $(call cc-option,-march=armv8.5-a,              CROSS_CC_HAS_ARMV8_5); \
          $(call cc-option,-mbranch-protection=standard,  CROSS_CC_HAS_ARMV8_BTI); \
          $(call cc-option,-march=armv8.5-a+memtag,       CROSS_CC_HAS_ARMV8_MTE); \
 -        $(call cc-option,-march=armv9-a+sme,            CROSS_CC_HAS_ARMV9_SME)) 3> config-cc.mak
 +        $(call cc-option,-Wa$(COMMA)-march=armv9-a+sme, CROSS_AS_HAS_ARMV9_SME)) 3> config-cc.mak
  -include config-cc.mak
  ifneq ($(CROSS_CC_HAS_ARMV8_2),)
@@ -XXX,XX +XXX,XX @@ AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7
  mte-%: CFLAGS += -march=armv8.5-a+memtag
  endif
 +ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
 +AARCH64_TESTS += sme-outprod1
 +endif
 +
  ifneq ($(CROSS_CC_HAS_SVE),)
  # System Registers Tests
  AARCH64_TESTS += sysregs
 -ifneq ($(CROSS_CC_HAS_ARMV9_SME),)
 -sysregs: CFLAGS+=-march=armv9-a+sme -DHAS_ARMV9_SME
 +ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
 +sysregs: CFLAGS+=-Wa,-march=armv9-a+sme -DHAS_ARMV9_SME
  else
  sysregs: CFLAGS+=-march=armv8.1-a+sve
  endif
 --
-.20.1
+.34.1

-[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
+[PULL 06/11] target/arm: Handle IC IVAU to improve compatibility with JITs
-The A64 AdvSIMD modified-immediate grouping uses almost the same
+From: John Högberg <john.hogberg@ericsson.com>
 constant encoding that A32 Neon does; reuse asimd_imm_const() (to
 which we add the AArch64-specific case for cmode 15 op 1) instead of
 reimplementing it all.
+Unlike architectures with precise self-modifying code semantics
+(e.g. x86) ARM processors do not maintain coherency for instruction
+execution and memory, requiring an instruction synchronization
+barrier on every core that will execute the new code, and on many
+models also the explicit use of cache management instructions.
+While this is required to make JITs work on actual hardware, QEMU
+has gotten away with not handling this since it does not emulate
+caches, and unconditionally invalidates code whenever the softmmu
+or the user-mode page protection logic detects that code has been
+modified.
+Unfortunately the latter does not work in the face of dual-mapped
+code (a common W^X workaround), where one page is executable and
+the other is writable: user-mode has no way to connect one with the
+other as that is only known to the kernel and the emulated
+application.
+This commit works around the issue by telling software that
+instruction cache invalidation is required by clearing the
+CPR_EL0.DIC flag (regardless of whether the emulated processor
+needs it), and then invalidating code in IC IVAU instructions.
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1034
+Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: John Högberg <john.hogberg@ericsson.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 168778890374.24232.3402138851538068785-1@git.sr.ht
+[PMM: removed unnecessary AArch64 feature check; moved
+ "clear CTR_EL1.DIC" code up a bit so it's not in the middle
+ of the vfp/neon related tests]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
 ---
- target/arm/translate.h     |  3 +-
+ target/arm/cpu.c    | 11 +++++++++++
- target/arm/translate-a64.c | 86 ++++----------------------------------
+ target/arm/helper.c | 47 ++++++++++++++++++++++++++++++++++++++++++---
- target/arm/translate.c     | 17 +++++++-
+files changed, 55 insertions(+), 3 deletions(-)
 files changed, 24 insertions(+), 82 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
+--- a/target/arm/cpu.c
-+++ b/target/arm/translate.h
++++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
   * VMVN and VBIC (when cmode < 14 && op == 1).
   *
   * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
 - * callers must catch this.
 + * callers must catch this; we return the 64-bit constant value defined
 + * for AArch64.
   *
   * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
   * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
  {
      int rd = extract32(insn, 0, 5);
      int cmode = extract32(insn, 12, 4);
 -    int cmode_3_1 = extract32(cmode, 1, 3);
 -    int cmode_0 = extract32(cmode, 0, 1);
      int o2 = extract32(insn, 11, 1);
      uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
      bool is_neg = extract32(insn, 29, 1);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
          return;
      }
--    /* See AdvSIMDExpandImm() in ARM ARM */
++#ifdef CONFIG_USER_ONLY
--    switch (cmode_3_1) {
++    /*
--    case 0: /* Replicate(Zeros(24):imm8, 2) */
++     * User mode relies on IC IVAU instructions to catch modification of
--    case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
++     * dual-mapped code.
--    case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
++     *
--    case 3: /* Replicate(imm8:Zeros(24), 2) */
++     * Clear CTR_EL0.DIC to ensure that software that honors these flags uses
--    {
++     * IC IVAU even if the emulated processor does not normally require it.
--        int shift = cmode_3_1 * 8;
++     */
--        imm = bitfield_replicate(abcdefgh << shift, 32);
++    cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0);
--        break;
++#endif
--    }
++
--    case 4: /* Replicate(Zeros(8):imm8, 4) */
+     if (arm_feature(env, ARM_FEATURE_AARCH64) &&
--    case 5: /* Replicate(imm8:Zeros(8), 4) */
+         cpu->has_vfp != cpu->has_neon) {
--    {
+         /*
--        int shift = (cmode_3_1 & 0x1) * 8;
+diff --git a/target/arm/helper.c b/target/arm/helper.c
--        imm = bitfield_replicate(abcdefgh << shift, 16);
+index XXXXXXX..XXXXXXX 100644
--        break;
+--- a/target/arm/helper.c
--    }
++++ b/target/arm/helper.c
--    case 6:
+@@ -XXX,XX +XXX,XX @@ static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
 -        if (cmode_0) {
 -            /* Replicate(Zeros(8):imm8:Ones(16), 2) */
 -            imm = (abcdefgh << 16) | 0xffff;
 -        } else {
 -            /* Replicate(Zeros(16):imm8:Ones(8), 2) */
 -            imm = (abcdefgh << 8) | 0xff;
 -        }
 -        imm = bitfield_replicate(imm, 32);
 -        break;
 -    case 7:
 -        if (!cmode_0 && !is_neg) {
 -            imm = bitfield_replicate(abcdefgh, 8);
 -        } else if (!cmode_0 && is_neg) {
 -            int i;
 -            imm = 0;
 -            for (i = 0; i < 8; i++) {
 -                if ((abcdefgh) & (1 << i)) {
 -                    imm |= 0xffULL << (i * 8);
 -                }
 -            }
 -        } else if (cmode_0) {
 -            if (is_neg) {
 -                imm = (abcdefgh & 0x3f) << 48;
 -                if (abcdefgh & 0x80) {
 -                    imm |= 0x8000000000000000ULL;
 -                }
 -                if (abcdefgh & 0x40) {
 -                    imm |= 0x3fc0000000000000ULL;
 -                } else {
 -                    imm |= 0x4000000000000000ULL;
 -                }
 -            } else {
 -                if (o2) {
 -                    /* FMOV (vector, immediate) - half-precision */
 -                    imm = vfp_expand_imm(MO_16, abcdefgh);
 -                    /* now duplicate across the lanes */
 -                    imm = bitfield_replicate(imm, 16);
 -                } else {
 -                    imm = (abcdefgh & 0x3f) << 19;
 -                    if (abcdefgh & 0x80) {
 -                        imm |= 0x80000000;
 -                    }
 -                    if (abcdefgh & 0x40) {
 -                        imm |= 0x3e000000;
 -                    } else {
 -                        imm |= 0x40000000;
 -                    }
 -                    imm |= (imm << 32);
 -                }
 -            }
 -        }
 -        break;
 -    default:
 -        g_assert_not_reached();
 -    }
 -
 -    if (cmode_3_1 != 7 && is_neg) {
 -        imm = ~imm;
 +    if (cmode == 15 && o2 && !is_neg) {
 +        /* FMOV (vector, immediate) - half-precision */
 +        imm = vfp_expand_imm(MO_16, abcdefgh);
 +        /* now duplicate across the lanes */
 +        imm = bitfield_replicate(imm, 16);
 +    } else {
 +        imm = asimd_imm_const(abcdefgh, cmode, is_neg);
      }
+ }
-     if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
-diff --git a/target/arm/translate.c b/target/arm/translate.c
++#ifdef CONFIG_USER_ONLY
-index XXXXXXX..XXXXXXX 100644
++/*
---- a/target/arm/translate.c
++ * `IC IVAU` is handled to improve compatibility with JITs that dual-map their
-+++ b/target/arm/translate.c
++ * code to get around W^X restrictions, where one region is writable and the
-@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
++ * other is executable.
-     case 14:
++ *
-         if (op) {
++ * Since the executable region is never written to we cannot detect code
-             /*
++ * changes when running in user mode, and rely on the emulated JIT telling us
--             * This is the only case where the top and bottom 32 bits
++ * that the code has changed by executing this instruction.
--             * of the encoded constant differ.
++ */
-+             * This and cmode == 15 op == 1 are the only cases where
++static void ic_ivau_write(CPUARMState *env, const ARMCPRegInfo *ri,
-+             * the top and bottom 32 bits of the encoded constant differ.
++                          uint64_t value)
-              */
++{
-             uint64_t imm64 = 0;
++    uint64_t icache_line_mask, start_address, end_address;
-             int n;
++    const ARMCPU *cpu;
-@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
++
-         imm |= (imm << 8) | (imm << 16) | (imm << 24);
++    cpu = env_archcpu(env);
-         break;
++
-     case 15:
++    icache_line_mask = (4 << extract32(cpu->ctr, 0, 4)) - 1;
-+        if (op) {
++    start_address = value & ~icache_line_mask;
-+            /* Reserved encoding for AArch32; valid for AArch64 */
++    end_address = value | icache_line_mask;
-+            uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
++
-+            if (imm & 0x80) {
++    mmap_lock();
-+                imm64 |= 0x8000000000000000ULL;
++
-+            }
++    tb_invalidate_phys_range(start_address, end_address);
-+            if (imm & 0x40) {
++
-+                imm64 |= 0x3fc0000000000000ULL;
++    mmap_unlock();
-+            } else {
++}
-+                imm64 |= 0x4000000000000000ULL;
++#endif
-+            }
++
-+            return imm64;
+ static const ARMCPRegInfo v8_cp_reginfo[] = {
-+        }
+     /*
-         imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
+      * Minimal set of EL0-visible registers. This will need to be expanded
-             | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-         break;
+     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
        .access = PL1_R, .type = ARM_CP_CURRENTEL },
 -    /* Cache ops: all NOPs since we don't emulate caches */
 +    /*
 +     * Instruction cache ops. All of these except `IC IVAU` NOP because we
 +     * don't emulate caches.
 +     */
      { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
        .access = PL1_W, .type = ARM_CP_NOP,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
        .accessfn = access_tocu },
      { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
 -      .access = PL0_W, .type = ARM_CP_NOP,
 +      .access = PL0_W,
        .fgt = FGT_ICIVAU,
 -      .accessfn = access_tocu },
 +      .accessfn = access_tocu,
 +#ifdef CONFIG_USER_ONLY
 +      .type = ARM_CP_NO_RAW,
 +      .writefn = ic_ivau_write
 +#else
 +      .type = ARM_CP_NOP
 +#endif
 +    },
 +    /* Cache ops: all NOPs since we don't emulate caches */
      { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
        .access = PL1_W, .accessfn = aa64_cacheop_poc_access,
 --
-.20.1
+.34.1

-[PULL 03/24] hw/arm: Add basic power management to raspi.
+[PULL 07/11] tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code
-From: Nolan Leake <nolan@sigbus.net>
+From: John Högberg <john.hogberg@ericsson.com>
-This is just enough to make reboot and poweroff work. Works for
+https://gitlab.com/qemu-project/qemu/-/issues/1034
-linux, u-boot, and the arm trusted firmware. Not tested, but should
-work for plan9, and bare-metal/hobby OSes, since they seem to generally
+Signed-off-by: John Högberg <john.hogberg@ericsson.com>
-do what linux does for reset.
+Message-id: 168778890374.24232.3402138851538068785-2@git.sr.ht
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-The watchdog timer functionality is not yet implemented.
+[PMM: fixed typo in comment]
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
 Signed-off-by: Nolan Leake <nolan@sigbus.net>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20210625210209.1870217-1-nolan@sigbus.net
 [PMM: tweaked commit title; fixed region size to 0x200;
  moved header file to include/]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/bcm2835_peripherals.h |   3 +-
+ tests/tcg/aarch64/icivau.c        | 189 ++++++++++++++++++++++++++++++
- include/hw/misc/bcm2835_powermgt.h   |  29 +++++
+ tests/tcg/aarch64/Makefile.target |   3 +-
- hw/arm/bcm2835_peripherals.c         |  13 ++-
+files changed, 191 insertions(+), 1 deletion(-)
- hw/misc/bcm2835_powermgt.c           | 160 +++++++++++++++++++++++++++
+ create mode 100644 tests/tcg/aarch64/icivau.c
- hw/misc/meson.build                  |   1 +
-files changed, 204 insertions(+), 2 deletions(-)
+diff --git a/tests/tcg/aarch64/icivau.c b/tests/tcg/aarch64/icivau.c
  create mode 100644 include/hw/misc/bcm2835_powermgt.h
  create mode 100644 hw/misc/bcm2835_powermgt.c
 diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/bcm2835_peripherals.h
 +++ b/include/hw/arm/bcm2835_peripherals.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/misc/bcm2835_mphi.h"
  #include "hw/misc/bcm2835_thermal.h"
  #include "hw/misc/bcm2835_cprman.h"
 +#include "hw/misc/bcm2835_powermgt.h"
  #include "hw/sd/sdhci.h"
  #include "hw/sd/bcm2835_sdhost.h"
  #include "hw/gpio/bcm2835_gpio.h"
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
      BCM2835MphiState mphi;
      UnimplementedDeviceState txp;
      UnimplementedDeviceState armtmr;
 -    UnimplementedDeviceState powermgt;
 +    BCM2835PowerMgtState powermgt;
      BCM2835CprmanState cprman;
      PL011State uart0;
      BCM2835AuxState aux;
 diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/misc/bcm2835_powermgt.h
++++ b/tests/tcg/aarch64/icivau.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * BCM2835 Power Management emulation
++ * Tests the IC IVAU-driven workaround for catching changes made to dual-mapped
 + * code that would otherwise go unnoticed in user mode.
 + *
-+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
++ * Copyright (c) 2023 Ericsson AB
-+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
++ * SPDX-License-Identifier: GPL-2.0-or-later
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + */
 +
-+#ifndef BCM2835_POWERMGT_H
++#include <sys/mman.h>
-+#define BCM2835_POWERMGT_H
++#include <sys/stat.h>
-+
++#include <string.h>
-+#include "hw/sysbus.h"
++#include <stdint.h>
-+#include "qom/object.h"
++#include <stdlib.h>
-+
++#include <unistd.h>
-+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
++#include <fcntl.h>
-+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
++
-+
++#define MAX_CODE_SIZE 128
-+struct BCM2835PowerMgtState {
++
-+    SysBusDevice busdev;
++typedef int (SelfModTest)(uint32_t, uint32_t*);
-+    MemoryRegion iomem;
++typedef int (BasicTest)(int);
 +
-+    uint32_t rstc;
++static void mark_code_modified(const uint32_t *exec_data, size_t length)
-+    uint32_t rsts;
++{
-+    uint32_t wdog;
++    int dc_required, ic_required;
-+};
++    unsigned long ctr_el0;
 +
-+#endif
++    /*
-diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
++     * Clear the data/instruction cache, as indicated by the CTR_ELO.{DIC,IDC}
 +     * flags.
 +     *
 +     * For completeness we might be tempted to assert that we should fail when
 +     * the whole code update sequence is omitted, but that would make the test
 +     * flaky as it can succeed by coincidence on actual hardware.
 +     */
 +    asm ("mrs %0, ctr_el0\n" : "=r"(ctr_el0));
 +
 +    /* CTR_EL0.IDC */
 +    dc_required = !((ctr_el0 >> 28) & 1);
 +
 +    /* CTR_EL0.DIC */
 +    ic_required = !((ctr_el0 >> 29) & 1);
 +
 +    if (dc_required) {
 +        size_t dcache_stride, i;
 +
 +        /*
 +         * Step according to the minimum cache size, as the cache maintenance
 +         * instructions operate on the cache line of the given address.
 +         *
 +         * We assume that exec_data is properly aligned.
 +         */
 +        dcache_stride = (4 << ((ctr_el0 >> 16) & 0xF));
 +
 +        for (i = 0; i < length; i += dcache_stride) {
 +            const char *dc_addr = &((const char *)exec_data)[i];
 +            asm volatile ("dc cvau, %x[dc_addr]\n"
 +                          : /* no outputs */
 +                          : [dc_addr] "r"(dc_addr)
 +                          : "memory");
 +        }
 +
 +        asm volatile ("dmb ish\n");
 +    }
 +
 +    if (ic_required) {
 +        size_t icache_stride, i;
 +
 +        icache_stride = (4 << (ctr_el0 & 0xF));
 +
 +        for (i = 0; i < length; i += icache_stride) {
 +            const char *ic_addr = &((const char *)exec_data)[i];
 +            asm volatile ("ic ivau, %x[ic_addr]\n"
 +                          : /* no outputs */
 +                          : [ic_addr] "r"(ic_addr)
 +                          : "memory");
 +        }
 +
 +        asm volatile ("dmb ish\n");
 +    }
 +
 +    asm volatile ("isb sy\n");
 +}
 +
 +static int basic_test(uint32_t *rw_data, const uint32_t *exec_data)
 +{
 +    /*
 +     * As user mode only misbehaved for dual-mapped code when previously
 +     * translated code had been changed, we'll start off with this basic test
 +     * function to ensure that there's already some translated code at
 +     * exec_data before the next test. This should cause the next test to fail
 +     * if `mark_code_modified` fails to invalidate the code.
 +     *
 +     * Note that the payload is in binary form instead of inline assembler
 +     * because we cannot use __attribute__((naked)) on this platform and the
 +     * workarounds are at least as ugly as this is.
 +     */
 +    static const uint32_t basic_payload[] = {
 +        0xD65F03C0 /* 0x00: RET */
 +    };
 +
 +    BasicTest *copied_ptr = (BasicTest *)exec_data;
 +
 +    memcpy(rw_data, basic_payload, sizeof(basic_payload));
 +    mark_code_modified(exec_data, sizeof(basic_payload));
 +
 +    return copied_ptr(1234) == 1234;
 +}
 +
 +static int self_modification_test(uint32_t *rw_data, const uint32_t *exec_data)
 +{
 +    /*
 +     * This test is self-modifying in an attempt to cover an edge case where
 +     * the IC IVAU instruction invalidates itself.
 +     *
 +     * Note that the IC IVAU instruction is 16 bytes into the function, in what
 +     * will be the same cache line as the modified instruction on machines with
 +     * a cache line size >= 16 bytes.
 +     */
 +    static const uint32_t self_mod_payload[] = {
 +        /* Overwrite the placeholder instruction with the new one. */
 +        0xB9001C20, /* 0x00: STR w0, [x1, 0x1C] */
 +
 +        /* Get the executable address of the modified instruction. */
 +        0x100000A8, /* 0x04: ADR x8, <0x1C> */
 +
 +        /* Mark the modified instruction as updated. */
 +        0xD50B7B28, /* 0x08: DC CVAU x8 */
 +        0xD5033BBF, /* 0x0C: DMB ISH */
 +        0xD50B7528, /* 0x10: IC IVAU x8 */
 +        0xD5033BBF, /* 0x14: DMB ISH */
 +        0xD5033FDF, /* 0x18: ISB */
 +
 +        /* Placeholder instruction, overwritten above. */
 +        0x52800000, /* 0x1C: MOV w0, 0 */
 +
 +        0xD65F03C0  /* 0x20: RET */
 +    };
 +
 +    SelfModTest *copied_ptr = (SelfModTest *)exec_data;
 +    int i;
 +
 +    memcpy(rw_data, self_mod_payload, sizeof(self_mod_payload));
 +    mark_code_modified(exec_data, sizeof(self_mod_payload));
 +
 +    for (i = 1; i < 10; i++) {
 +        /* Replace the placeholder instruction with `MOV w0, i` */
 +        uint32_t new_instr = 0x52800000 | (i << 5);
 +
 +        if (copied_ptr(new_instr, rw_data) != i) {
 +            return 0;
 +        }
 +    }
 +
 +    return 1;
 +}
 +
 +int main(int argc, char **argv)
 +{
 +    const char *shm_name = "qemu-test-tcg-aarch64-icivau";
 +    int fd;
 +
 +    fd = shm_open(shm_name, O_CREAT | O_RDWR, S_IRUSR | S_IWUSR);
 +
 +    if (fd < 0) {
 +        return EXIT_FAILURE;
 +    }
 +
 +    /* Unlink early to avoid leaving garbage in case the test crashes. */
 +    shm_unlink(shm_name);
 +
 +    if (ftruncate(fd, MAX_CODE_SIZE) == 0) {
 +        const uint32_t *exec_data;
 +        uint32_t *rw_data;
 +
 +        rw_data = mmap(0, MAX_CODE_SIZE, PROT_READ | PROT_WRITE,
 +                       MAP_SHARED, fd, 0);
 +        exec_data = mmap(0, MAX_CODE_SIZE, PROT_READ | PROT_EXEC,
 +                         MAP_SHARED, fd, 0);
 +
 +        if (rw_data && exec_data) {
 +            if (basic_test(rw_data, exec_data) &&
 +                self_modification_test(rw_data, exec_data)) {
 +                return EXIT_SUCCESS;
 +            }
 +        }
 +    }
 +
 +    return EXIT_FAILURE;
 +}
 diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2835_peripherals.c
+--- a/tests/tcg/aarch64/Makefile.target
-+++ b/hw/arm/bcm2835_peripherals.c
++++ b/tests/tcg/aarch64/Makefile.target
-@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
+ VPATH         += $(AARCH64_SRC)
-     object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
-                                    OBJECT(&s->gpu_bus_mr));
+ # Base architecture tests
-+
+-AARCH64_TESTS=fcvt pcalign-a64
-+    /* Power Management */
++AARCH64_TESTS=fcvt pcalign-a64 icivau
-+    object_initialize_child(obj, "powermgt", &s->powermgt,
-+                            TYPE_BCM2835_POWERMGT);
+ fcvt: LDFLAGS+=-lm
- }
++icivau: LDFLAGS+=-lrt
- static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
+ run-fcvt: fcvt
-@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
+     $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)")
          qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
                                 INTERRUPT_USB));
 +    /* Power Management */
 +    if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
 +        return;
 +    }
 +
 +    memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
 +                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
 +
      create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
      create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
 -    create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
      create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
      create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
      create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
 diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/bcm2835_powermgt.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * BCM2835 Power Management emulation
 + *
 + * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
 + * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/log.h"
 +#include "qemu/module.h"
 +#include "hw/misc/bcm2835_powermgt.h"
 +#include "migration/vmstate.h"
 +#include "sysemu/runstate.h"
 +
 +#define PASSWORD 0x5a000000
 +#define PASSWORD_MASK 0xff000000
 +
 +#define R_RSTC 0x1c
 +#define V_RSTC_RESET 0x20
 +#define R_RSTS 0x20
 +#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
 +#define R_WDOG 0x24
 +
 +static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
 +                                      unsigned size)
 +{
 +    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
 +    uint32_t res = 0;
 +
 +    switch (offset) {
 +    case R_RSTC:
 +        res = s->rstc;
 +        break;
 +    case R_RSTS:
 +        res = s->rsts;
 +        break;
 +    case R_WDOG:
 +        res = s->wdog;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
 +                      "\n", offset);
 +        res = 0;
 +        break;
 +    }
 +
 +    return res;
 +}
 +
 +static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
 +                                   uint64_t value, unsigned size)
 +{
 +    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
 +
 +    if ((value & PASSWORD_MASK) != PASSWORD) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "bcm2835_powermgt_write: Bad password 0x%"PRIx64
 +                      " at offset 0x%08"HWADDR_PRIx"\n",
 +                      value, offset);
 +        return;
 +    }
 +
 +    value = value & ~PASSWORD_MASK;
 +
 +    switch (offset) {
 +    case R_RSTC:
 +        s->rstc = value;
 +        if (value & V_RSTC_RESET) {
 +            if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
 +                qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 +            } else {
 +                qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 +            }
 +        }
 +        break;
 +    case R_RSTS:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "bcm2835_powermgt_write: RSTS\n");
 +        s->rsts = value;
 +        break;
 +    case R_WDOG:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "bcm2835_powermgt_write: WDOG\n");
 +        s->wdog = value;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
 +                      "\n", offset);
 +        break;
 +    }
 +}
 +
 +static const MemoryRegionOps bcm2835_powermgt_ops = {
 +    .read = bcm2835_powermgt_read,
 +    .write = bcm2835_powermgt_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .impl.min_access_size = 4,
 +    .impl.max_access_size = 4,
 +};
 +
 +static const VMStateDescription vmstate_bcm2835_powermgt = {
 +    .name = TYPE_BCM2835_POWERMGT,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
 +        VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
 +        VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
 +static void bcm2835_powermgt_init(Object *obj)
 +{
 +    BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
 +
 +    memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
 +                          TYPE_BCM2835_POWERMGT, 0x200);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 +}
 +
 +static void bcm2835_powermgt_reset(DeviceState *dev)
 +{
 +    BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
 +
 +    /* https://elinux.org/BCM2835_registers#PM */
 +    s->rstc = 0x00000102;
 +    s->rsts = 0x00001000;
 +    s->wdog = 0x00000000;
 +}
 +
 +static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->reset = bcm2835_powermgt_reset;
 +    dc->vmsd = &vmstate_bcm2835_powermgt;
 +}
 +
 +static TypeInfo bcm2835_powermgt_info = {
 +    .name          = TYPE_BCM2835_POWERMGT,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(BCM2835PowerMgtState),
 +    .class_init    = bcm2835_powermgt_class_init,
 +    .instance_init = bcm2835_powermgt_init,
 +};
 +
 +static void bcm2835_powermgt_register_types(void)
 +{
 +    type_register_static(&bcm2835_powermgt_info);
 +}
 +
 +type_init(bcm2835_powermgt_register_types)
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
    'bcm2835_rng.c',
    'bcm2835_thermal.c',
    'bcm2835_cprman.c',
 +  'bcm2835_powermgt.c',
  ))
  softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
  softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
 --
-.20.1
+.34.1

-[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
+[PULL 08/11] tests/qtest: xlnx-canfd-test: Fix code coverity issues
-From: Maxim Uvarov <maxim.uvarov@linaro.org>
+From: Vikram Garhwal <vikram.garhwal@amd.com>
-qemu has 2 type of functions: shutdown and reboot. Shutdown
+Following are done to fix the coverity issues:
-function has to be used for machine shutdown. Otherwise we cause
+. Change read_data to fix the CID 1512899: Out-of-bounds access (OVERRUN)
-a reset with a bogus "cause" value, when we intended a shutdown.
+. Fix match_rx_tx_data to fix CID 1512900: Logically dead code (DEADCODE)
 . Replace rand() in generate_random_data() with g_rand_int()
-Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
+Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
 Message-id: 20230628202758.16398-1-vikram.garhwal@amd.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
-[PMM: tweaked commit message]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/gpio/gpio_pwr.c | 2 +-
+ tests/qtest/xlnx-canfd-test.c | 33 +++++++++++----------------------
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 11 insertions(+), 22 deletions(-)
-diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
+diff --git a/tests/qtest/xlnx-canfd-test.c b/tests/qtest/xlnx-canfd-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/gpio/gpio_pwr.c
+--- a/tests/qtest/xlnx-canfd-test.c
-+++ b/hw/gpio/gpio_pwr.c
++++ b/tests/qtest/xlnx-canfd-test.c
-@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
+@@ -XXX,XX +XXX,XX @@ static void generate_random_data(uint32_t *buf_tx, bool is_canfd_frame)
- static void gpio_pwr_shutdown(void *opaque, int n, int level)
+     /* Generate random TX data for CANFD frame. */
- {
+     if (is_canfd_frame) {
-     if (level) {
+         for (int i = 0; i < CANFD_FRAME_SIZE - 2; i++) {
--        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+-            buf_tx[2 + i] = rand();
-+        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
++            buf_tx[2 + i] = g_random_int();
          }
      } else {
          /* Generate random TX data for CAN frame. */
          for (int i = 0; i < CAN_FRAME_SIZE - 2; i++) {
 -            buf_tx[2 + i] = rand();
 +            buf_tx[2 + i] = g_random_int();
          }
      }
  }
+-static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx)
++static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx,
++                      uint32_t frame_size)
+ {
+     uint32_t int_status;
+     uint32_t fifo_status_reg_value;
+     /* At which RX FIFO the received data is stored. */
+     uint8_t store_ind = 0;
+-    bool is_canfd_frame = false;
+     /* Read the interrupt on CANFD rx. */
+     int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK;
+@@ -XXX,XX +XXX,XX @@ static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx)
+     buf_rx[0] = qtest_readl(qts, can_base_addr + R_RX0_ID_OFFSET);
+     buf_rx[1] = qtest_readl(qts, can_base_addr + R_RX0_DLC_OFFSET);
+-    is_canfd_frame = (buf_rx[1] >> DLC_FD_BIT_SHIFT) & 1;
+-
+-    if (is_canfd_frame) {
+-        for (int i = 0; i < CANFD_FRAME_SIZE - 2; i++) {
+-            buf_rx[i + 2] = qtest_readl(qts,
+-                                    can_base_addr + R_RX0_DATA1_OFFSET + 4 * i);
+-        }
+-    } else {
+-        buf_rx[2] = qtest_readl(qts, can_base_addr + R_RX0_DATA1_OFFSET);
+-        buf_rx[3] = qtest_readl(qts, can_base_addr + R_RX0_DATA2_OFFSET);
++    for (int i = 0; i < frame_size - 2; i++) {
++        buf_rx[i + 2] = qtest_readl(qts,
++                                can_base_addr + R_RX0_DATA1_OFFSET + 4 * i);
+     }
+     /* Clear the RX interrupt. */
+@@ -XXX,XX +XXX,XX @@ static void match_rx_tx_data(const uint32_t *buf_tx, const uint32_t *buf_rx,
+             g_assert_cmpint((buf_rx[size] & DLC_FD_BIT_MASK), ==,
+                             (buf_tx[size] & DLC_FD_BIT_MASK));
+         } else {
+-            if (!is_canfd_frame && size == 4) {
+-                break;
+-            }
+-
+             g_assert_cmpint(buf_rx[size], ==, buf_tx[size]);
+         }
+@@ -XXX,XX +XXX,XX @@ static void test_can_data_transfer(void)
+     write_data(qts, CANFD0_BASE_ADDR, buf_tx, false);
+     send_data(qts, CANFD0_BASE_ADDR);
+-    read_data(qts, CANFD1_BASE_ADDR, buf_rx);
++    read_data(qts, CANFD1_BASE_ADDR, buf_rx, CAN_FRAME_SIZE);
+     match_rx_tx_data(buf_tx, buf_rx, false);
+     qtest_quit(qts);
+@@ -XXX,XX +XXX,XX @@ static void test_canfd_data_transfer(void)
+     write_data(qts, CANFD0_BASE_ADDR, buf_tx, true);
+     send_data(qts, CANFD0_BASE_ADDR);
+-    read_data(qts, CANFD1_BASE_ADDR, buf_rx);
++    read_data(qts, CANFD1_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE);
+     match_rx_tx_data(buf_tx, buf_rx, true);
+     qtest_quit(qts);
+@@ -XXX,XX +XXX,XX @@ static void test_can_loopback(void)
+     write_data(qts, CANFD0_BASE_ADDR, buf_tx, true);
+     send_data(qts, CANFD0_BASE_ADDR);
+-    read_data(qts, CANFD0_BASE_ADDR, buf_rx);
++    read_data(qts, CANFD0_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE);
+     match_rx_tx_data(buf_tx, buf_rx, true);
+     generate_random_data(buf_tx, true);
+@@ -XXX,XX +XXX,XX @@ static void test_can_loopback(void)
+     write_data(qts, CANFD1_BASE_ADDR, buf_tx, true);
+     send_data(qts, CANFD1_BASE_ADDR);
+-    read_data(qts, CANFD1_BASE_ADDR, buf_rx);
++    read_data(qts, CANFD1_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE);
+     match_rx_tx_data(buf_tx, buf_rx, true);
+     qtest_quit(qts);
 --
-.20.1
+.34.1

-[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
+[PULL 09/11] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG
-Implement the MVE vector shift right by immediate insns VSHRI and
+From: Fabiano Rosas <farosas@suse.de>
 VRSHRI.  As with Neon, we implement these by using helper functions
 which perform left shifts but allow negative shift counts to indicate
 right shifts.
+This code is only relevant when TCG is present in the build. Building
+with --disable-tcg --enable-xen on an x86 host we get:
+$ ../configure --target-list=x86_64-softmmu,aarch64-softmmu --disable-tcg --enable-xen
+$ make -j$(nproc)
+...
+libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `m_sysreg_ptr':
+ ../target/arm/gdbstub.c:358: undefined reference to `arm_v7m_get_sp_ptr'
+ ../target/arm/gdbstub.c:361: undefined reference to `arm_v7m_get_sp_ptr'
+libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `arm_gdb_get_m_systemreg':
+../target/arm/gdbstub.c:405: undefined reference to `arm_v7m_mrs_control'
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Message-id: 20230628164821.16771-1-farosas@suse.de
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h     | 12 ++++++++++++
+ target/arm/gdbstub.c | 4 ++++
- target/arm/translate.h      | 20 ++++++++++++++++++++
+file changed, 4 insertions(+)
  target/arm/mve.decode       | 28 ++++++++++++++++++++++++++++
  target/arm/mve_helper.c     |  7 +++++++
  target/arm/translate-mve.c  |  5 +++++
  target/arm/translate-neon.c | 18 ------------------
 files changed, 72 insertions(+), 18 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/gdbstub.c
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
+@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
- DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
+     return cpu->dyn_sysreg_xml.num;
  DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
 +DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
  DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
  DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
      return x * 2 + 1;
  }
-+static inline int rsub_64(DisasContext *s, int x)
++#ifdef CONFIG_TCG
-+{
+ typedef enum {
-+    return 64 - x;
+     M_SYSREG_MSP,
-+}
+     M_SYSREG_PSP,
-+
+@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)
-+static inline int rsub_32(DisasContext *s, int x)
+     return cpu->dyn_m_secextreg_xml.num;
-+{
+ }
-+    return 32 - x;
+ #endif
-+}
++#endif /* CONFIG_TCG */
-+
-+static inline int rsub_16(DisasContext *s, int x)
+ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 +{
 +    return 16 - x;
 +}
 +
 +static inline int rsub_8(DisasContext *s, int x)
 +{
 +    return 8 - x;
 +}
 +
  static inline int arm_dc_feature(DisasContext *dc, int feature)
  {
-     return (dc->features & (1ULL << feature)) != 0;
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
+                              arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
-index XXXXXXX..XXXXXXX 100644
+                              "system-registers.xml", 0);
---- a/target/arm/mve.decode
-+++ b/target/arm/mve.decode
++#ifdef CONFIG_TCG
-@@ -XXX,XX +XXX,XX @@
+     if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
- @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+         gdb_register_coprocessor(cs,
- @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
+             arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
-+# Right shifts are encoded as N - shift, where N is the element size in bits.
+         }
-+%rshift_i5  16:5 !function=rsub_32
+ #endif
-+%rshift_i4  16:4 !function=rsub_16
+     }
-+%rshift_i3  16:3 !function=rsub_8
++#endif /* CONFIG_TCG */
 +
 +@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
 +         size=0 shift=%rshift_i3
 +@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
 +         size=1 shift=%rshift_i4
 +@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
 +         size=2 shift=%rshift_i5
 +
  # Vector loads and stores
  # Widening loads and narrowing stores:
@@ -XXX,XX +XXX,XX @@ VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
  VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
  VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
  VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
 +
 +VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
 +VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
 +VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
 +
 +VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
 +VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
 +VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
 +
 +VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 +VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 +VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 +
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
      DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
      DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
      DO_2SHIFT(OP##w, 4, uint32_t, FN)
 +#define DO_2SHIFT_S(OP, FN)                     \
 +    DO_2SHIFT(OP##b, 1, int8_t, FN)             \
 +    DO_2SHIFT(OP##h, 2, int16_t, FN)            \
 +    DO_2SHIFT(OP##w, 4, int32_t, FN)
  #define DO_2SHIFT_SAT_U(OP, FN)                 \
      DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
      DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
  DO_2SHIFT_U(vshli_u, DO_VSHLU)
 +DO_2SHIFT_S(vshli_s, DO_VSHLS)
  DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
  DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
  DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
 +DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
 +DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
  DO_2SHIFT(VQSHLI_S, vqshli_s, false)
  DO_2SHIFT(VQSHLI_U, vqshli_u, false)
  DO_2SHIFT(VQSHLUI, vqshlui_s, false)
 +/* These right shifts use a left-shift helper with negated shift count */
 +DO_2SHIFT(VSHRI_S, vshli_s, true)
 +DO_2SHIFT(VSHRI_U, vshli_u, true)
 +DO_2SHIFT(VRSHRI_S, vrshli_s, true)
 +DO_2SHIFT(VRSHRI_U, vrshli_u, true)
 diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.c
 +++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
      return x + 1;
  }
--static inline int rsub_64(DisasContext *s, int x)
--{
--    return 64 - x;
--}
--
--static inline int rsub_32(DisasContext *s, int x)
--{
--    return 32 - x;
--}
--static inline int rsub_16(DisasContext *s, int x)
--{
--    return 16 - x;
--}
--static inline int rsub_8(DisasContext *s, int x)
--{
--    return 8 - x;
--}
--
- static inline int neon_3same_fp_size(DisasContext *s, int x)
- {
-     /* Convert 0==fp32, 1==fp16 into a MO_* value */
 --
-.20.1
+.34.1

-[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
+[PULL 10/11] hw: arm: allwinner-sramc: Set class_size
-From: Patrick Venture <venture@google.com>
+From: Akihiko Odaki <akihiko.odaki@daynix.com>
-Adds a line-item reference to the supported quanta-q71l-bmc aspeed
+AwSRAMCClass is larger than SysBusDeviceClass so the class size must be
-entry.
+advertised accordingly.
-Signed-off-by: Patrick Venture <venture@google.com>
+Fixes: 05def917e1 ("hw: arm: allwinner-sramc: Add SRAM Controller support for R40")
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
+Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
-Message-id: 20210615192848.1065297-2-venture@google.com
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230628110905.38125-1-akihiko.odaki@daynix.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/aspeed.rst | 1 +
+ hw/misc/allwinner-sramc.c | 1 +
 file changed, 1 insertion(+)
-diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
+diff --git a/hw/misc/allwinner-sramc.c b/hw/misc/allwinner-sramc.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/aspeed.rst
+--- a/hw/misc/allwinner-sramc.c
-+++ b/docs/system/arm/aspeed.rst
++++ b/hw/misc/allwinner-sramc.c
-@@ -XXX,XX +XXX,XX @@ etc.
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo allwinner_sramc_info = {
- AST2400 SoC based machines :
+     .parent        = TYPE_SYS_BUS_DEVICE,
+     .instance_init = allwinner_sramc_init,
- - ``palmetto-bmc``         OpenPOWER Palmetto POWER8 BMC
+     .instance_size = sizeof(AwSRAMCState),
-+- ``quanta-q71l-bmc``      OpenBMC Quanta BMC
++    .class_size    = sizeof(AwSRAMCClass),
+     .class_init    = allwinner_sramc_class_init,
- AST2500 SoC based machines :
+ };
 --
-.20.1
+.34.1

-[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
+Deleted patch
-From: Patrick Venture <venture@google.com>
-Add line item reference to quanta-gbs-bmc machine.
-Signed-off-by: Patrick Venture <venture@google.com>
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Message-id: 20210615192848.1065297-3-venture@google.com
-[PMM: fixed underline Sphinx warning]
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- docs/system/arm/nuvoton.rst | 5 +++--
-file changed, 3 insertions(+), 2 deletions(-)
-diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/nuvoton.rst
-+++ b/docs/system/arm/nuvoton.rst
-@@ -XXX,XX +XXX,XX @@
--Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
--=====================================================
-+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
-+================================================================
- The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
- designed to be used as Baseboard Management Controllers (BMCs) in various
-@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
- The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
- Hyperscale applications. The following machines are based on this chip :
-+- ``quanta-gbs-bmc``    Quanta GBS server BMC
- - ``quanta-gsj``        Quanta GSJ server BMC
- There are also two more SoCs, NPCM710 and NPCM705, which are single-core
---
-.20.1

-[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
+Deleted patch
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Add a test booting and quickly shutdown a raspi2 machine,
-to test the power management model:
-   (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
-  console: [    0.000000] Booting Linux on physical CPU 0xf00
-  console: [    0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
-  console: [    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
-  console: [    0.000000] CPU: div instructions available: patching division code
-  console: [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
-  console: [    0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
-  ...
-  console: Boot successful.
-  console: cat /proc/cpuinfo
-  console: / # cat /proc/cpuinfo
-  ...
-  console: processor      : 3
-  console: model name     : ARMv7 Processor rev 5 (v7l)
-  console: BogoMIPS       : 125.00
-  console: Features       : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
-  console: CPU implementer        : 0x41
-  console: CPU architecture: 7
-  console: CPU variant    : 0x0
-  console: CPU part       : 0xc07
-  console: CPU revision   : 5
-  console: Hardware       : BCM2835
-  console: Revision       : 0000
-  console: Serial         : 0000000000000000
-  console: cat /proc/iomem
-  console: / # cat /proc/iomem
-  console: 00000000-3bffffff : System RAM
-  console: 00008000-00afffff : Kernel code
-  console: 00c00000-00d468ef : Kernel data
-  console: 3f006000-3f006fff : dwc_otg
-  console: 3f007000-3f007eff : /soc/dma@7e007000
-  console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
-  console: 3f100000-3f100027 : /soc/watchdog@7e100000
-  console: 3f101000-3f102fff : /soc/cprman@7e101000
-  console: 3f200000-3f2000b3 : /soc/gpio@7e200000
-  PASS (24.59 s)
-  RESULTS    : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
-  JOB TIME   : 25.02 s
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
-Message-id: 20210531113837.1689775-1-f4bug@amsat.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
-file changed, 43 insertions(+)
-diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
-index XXXXXXX..XXXXXXX 100644
---- a/tests/acceptance/boot_linux_console.py
-+++ b/tests/acceptance/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@
- from avocado import skip
- from avocado import skipUnless
- from avocado_qemu import Test
-+from avocado_qemu import exec_command
- from avocado_qemu import exec_command_and_wait_for_pattern
- from avocado_qemu import interrupt_interactive_console_until_pattern
- from avocado_qemu import wait_for_console_pattern
-@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
-         """
-         self.do_test_arm_raspi2(0)
-+    def test_arm_raspi2_initrd(self):
-+        """
-+        :avocado: tags=arch:arm
-+        :avocado: tags=machine:raspi2
-+        """
-+        deb_url = ('http://archive.raspberrypi.org/debian/'
-+                   'pool/main/r/raspberrypi-firmware/'
-+                   'raspberrypi-kernel_1.20190215-1_armhf.deb')
-+        deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
-+        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
-+        kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
-+        dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
-+
-+        initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
-+                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
-+                      'arm/rootfs-armv7a.cpio.gz')
-+        initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
-+        initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
-+        initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
-+        archive.gzip_uncompress(initrd_path_gz, initrd_path)
-+
-+        self.vm.set_console()
-+        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
-+                               'earlycon=pl011,0x3f201000 console=ttyAMA0 '
-+                               'panic=-1 noreboot ' +
-+                               'dwc_otg.fiq_fsm_enable=0')
-+        self.vm.add_args('-kernel', kernel_path,
-+                         '-dtb', dtb_path,
-+                         '-initrd', initrd_path,
-+                         '-append', kernel_command_line,
-+                         '-no-reboot')
-+        self.vm.launch()
-+        self.wait_for_console_pattern('Boot successful.')
-+
-+        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
-+                                                'BCM2835')
-+        exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
-+                                                '/soc/cprman@7e101000')
-+        exec_command(self, 'halt')
-+        # Wait for VM to shut down gracefully
-+        self.vm.wait()
-+
-     def test_arm_exynos4210_initrd(self):
-         """
-         :avocado: tags=arch:arm
---
-.20.1

-[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
+Deleted patch
-The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
-insns had some bugs:
- * the 32x32 multiply of elements was being done as 32x32->32,
-   not 32x32->64
- * we were incorrectly maintaining the accumulator in its full
--bit form across all 4 beats of the insn; in the pseudocode
-   it is squashed back into the 64 bits of the RdaHi:RdaLo
-   registers after each beat
-In particular, fixing the second of these allows us to recast
-the implementation to avoid 128-bit arithmetic entirely.
-Since the element size here is always 4, we can also drop the
-parameterization of ESIZE to make the code a little more readable.
-Suggested-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
----
- target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
-file changed, 21 insertions(+), 17 deletions(-)
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve_helper.c
-+++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@
-  */
- #include "qemu/osdep.h"
--#include "qemu/int128.h"
- #include "cpu.h"
- #include "internals.h"
- #include "vec_internal.h"
-@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
- DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
- /*
-- * Rounding multiply add long dual accumulate high: we must keep
-- * a 72-bit internal accumulator value and return the top 64 bits.
-+ * Rounding multiply add long dual accumulate high. In the pseudocode
-+ * this is implemented with a 72-bit internal accumulator value of which
-+ * the top 64 bits are returned. We optimize this to avoid having to
-+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
-+ * is squashed back into 64-bits after each beat.
-  */
--#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128)         \
-+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB)                            \
-     uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn,         \
-                                     void *vm, uint64_t a)               \
-     {                                                                   \
-         uint16_t mask = mve_element_mask(env);                          \
-         unsigned e;                                                     \
-         TYPE *n = vn, *m = vm;                                          \
--        Int128 acc = int128_lshift(TO128(a), 8);                        \
--        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {              \
-+        for (e = 0; e < 16 / 4; e++, mask >>= 4) {                      \
-             if (mask & 1) {                                             \
-+                LTYPE mul;                                              \
-                 if (e & 1) {                                            \
--                    acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
--                                            m[H##ESIZE(e)]));           \
-+                    mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)];        \
-+                    if (SUB) {                                          \
-+                        mul = -mul;                                     \
-+                    }                                                   \
-                 } else {                                                \
--                    acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
--                                             m[H##ESIZE(e)]));          \
-+                    mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)];        \
-                 }                                                       \
--                acc = int128_add(acc, int128_make64(1 << 7));           \
-+                mul = (mul >> 8) + ((mul >> 7) & 1);                    \
-+                a += mul;                                               \
-             }                                                           \
-         }                                                               \
-         mve_advance_vpt(env);                                           \
--        return int128_getlo(int128_rshift(acc, 8));                     \
-+        return a;                                                       \
-     }
--DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
--DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
-+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
-+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
--DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
-+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
--DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
--DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
-+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
-+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
- /* Vector add across vector */
- #define DO_VADDV(OP, ESIZE, TYPE)                               \
---
-.20.1

-[PULL 09/24] target/arm: Make asimd_imm_const() public
+Deleted patch
-The function asimd_imm_const() in translate-neon.c is an
-implementation of the pseudocode AdvSIMDExpandImm(), which we will
-also want for MVE.  Move the implementation to translate.c, with a
-prototype in translate.h.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
----
- target/arm/translate.h      | 16 ++++++++++
- target/arm/translate-neon.c | 63 -------------------------------------
- target/arm/translate.c      | 57 +++++++++++++++++++++++++++++++++
-files changed, 73 insertions(+), 63 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
-+++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
-     return opc | s->be_data;
- }
-+/**
-+ * asimd_imm_const: Expand an encoded SIMD constant value
-+ *
-+ * Expand a SIMD constant value. This is essentially the pseudocode
-+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
-+ * VMVN and VBIC (when cmode < 14 && op == 1).
-+ *
-+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
-+ * callers must catch this.
-+ *
-+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
-+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
-+ * we produce an immediate constant value of 0 in these cases.
-+ */
-+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
-+
- #endif /* TARGET_ARM_TRANSLATE_H */
-diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.c
-+++ b/target/arm/translate-neon.c
-@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
- DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
- DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
--static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
--{
--    /*
--     * Expand the encoded constant.
--     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
--     * We choose to not special-case this and will behave as if a
--     * valid constant encoding of 0 had been given.
--     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
--     */
--    switch (cmode) {
--    case 0: case 1:
--        /* no-op */
--        break;
--    case 2: case 3:
--        imm <<= 8;
--        break;
--    case 4: case 5:
--        imm <<= 16;
--        break;
--    case 6: case 7:
--        imm <<= 24;
--        break;
--    case 8: case 9:
--        imm |= imm << 16;
--        break;
--    case 10: case 11:
--        imm = (imm << 8) | (imm << 24);
--        break;
--    case 12:
--        imm = (imm << 8) | 0xff;
--        break;
--    case 13:
--        imm = (imm << 16) | 0xffff;
--        break;
--    case 14:
--        if (op) {
--            /*
--             * This is the only case where the top and bottom 32 bits
--             * of the encoded constant differ.
--             */
--            uint64_t imm64 = 0;
--            int n;
--
--            for (n = 0; n < 8; n++) {
--                if (imm & (1 << n)) {
--                    imm64 |= (0xffULL << (n * 8));
--                }
--            }
--            return imm64;
--        }
--        imm |= (imm << 8) | (imm << 16) | (imm << 24);
--        break;
--    case 15:
--        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
--            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
--        break;
--    }
--    if (op) {
--        imm = ~imm;
--    }
--    return dup_const(MO_32, imm);
--}
--
- static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
-                         GVecGen2iFn *fn)
- {
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
-     a64_translate_init();
- }
-+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
-+{
-+    /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
-+    switch (cmode) {
-+    case 0: case 1:
-+        /* no-op */
-+        break;
-+    case 2: case 3:
-+        imm <<= 8;
-+        break;
-+    case 4: case 5:
-+        imm <<= 16;
-+        break;
-+    case 6: case 7:
-+        imm <<= 24;
-+        break;
-+    case 8: case 9:
-+        imm |= imm << 16;
-+        break;
-+    case 10: case 11:
-+        imm = (imm << 8) | (imm << 24);
-+        break;
-+    case 12:
-+        imm = (imm << 8) | 0xff;
-+        break;
-+    case 13:
-+        imm = (imm << 16) | 0xffff;
-+        break;
-+    case 14:
-+        if (op) {
-+            /*
-+             * This is the only case where the top and bottom 32 bits
-+             * of the encoded constant differ.
-+             */
-+            uint64_t imm64 = 0;
-+            int n;
-+
-+            for (n = 0; n < 8; n++) {
-+                if (imm & (1 << n)) {
-+                    imm64 |= (0xffULL << (n * 8));
-+                }
-+            }
-+            return imm64;
-+        }
-+        imm |= (imm << 8) | (imm << 16) | (imm << 24);
-+        break;
-+    case 15:
-+        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
-+            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
-+        break;
-+    }
-+    if (op) {
-+        imm = ~imm;
-+    }
-+    return dup_const(MO_32, imm);
-+}
-+
- /* Generate a label used for skipping this instruction */
- void arm_gen_condlabel(DisasContext *s)
- {
---
-.20.1

-[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
+Deleted patch
-Use dup_const() instead of bitfield_replicate() in
-disas_simd_mod_imm().
-(We can't replace the other use of bitfield_replicate() in this file,
-in logic_imm_decode_wmask(), because that location needs to handle 2
-and 4 bit elements, which dup_const() cannot.)
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
----
- target/arm/translate-a64.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
-         /* FMOV (vector, immediate) - half-precision */
-         imm = vfp_expand_imm(MO_16, abcdefgh);
-         /* now duplicate across the lanes */
--        imm = bitfield_replicate(imm, 16);
-+        imm = dup_const(MO_16, imm);
-     } else {
-         imm = asimd_imm_const(abcdefgh, cmode, is_neg);
-     }
---
-.20.1

-[PULL 12/24] target/arm: Implement MVE logical immediate insns
+Deleted patch
-Implement the MVE logical-immediate insns (VMOV, VMVN,
-VORR and VBIC). These have essentially the same encoding
-as their Neon equivalents, and we implement the decode
-in the same way.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
----
- target/arm/helper-mve.h    |  4 +++
- target/arm/mve.decode      | 17 +++++++++++++
- target/arm/mve_helper.c    | 24 ++++++++++++++++++
- target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
-files changed, 95 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
-+++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
- DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
- DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
- DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
-+
-+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
-+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
-+DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
-+++ b/target/arm/mve.decode
-@@ -XXX,XX +XXX,XX @@
- # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
- %size_28 28:1 !function=plus_1
-+# 1imm format immediate
-+%imm_28_16_0 28:1 16:3 0:4
-+
- &vldr_vstr rn qd imm p a w size l u
- &1op qd qm size
- &2op qd qm qn size
- &2scalar qd qn rm size
-+&1imm qd imm cmode op
- @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
- # Note that both Rn and Qd are 3 bits only (no D bit)
-@@ -XXX,XX +XXX,XX @@
- @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
- @2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
-      size=%size_28
-+@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
- # The _rev suffix indicates that Vn and Vm are reversed. This is
- # the case for shifts. In the Arm ARM these insns are documented
-@@ -XXX,XX +XXX,XX @@ VADDV            111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
- # Predicate operations
- %mask_22_13      22:1 13:3
- VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
-+
-+# Logical immediate operations (1 reg and modified-immediate)
-+
-+# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
-+# not in a way we can conveniently represent in decodetree without
-+# a lot of repetition:
-+# VORR: op=0, (cmode & 1) && cmode < 12
-+# VBIC: op=1, (cmode & 1) && cmode < 12
-+# VMOV: everything else
-+# So we have a single decode line and check the cmode/op in the
-+# trans function.
-+Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve_helper.c
-+++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
- DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
- DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
-+/*
-+ * 1 operand immediates: Vda is destination and possibly also one source.
-+ * All these insns work at 64-bit widths.
-+ */
-+#define DO_1OP_IMM(OP, FN)                                              \
-+    void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm)    \
-+    {                                                                   \
-+        uint64_t *da = vda;                                             \
-+        uint16_t mask = mve_element_mask(env);                          \
-+        unsigned e;                                                     \
-+        for (e = 0; e < 16 / 8; e++, mask >>= 8) {                      \
-+            mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask);            \
-+        }                                                               \
-+        mve_advance_vpt(env);                                           \
-+    }
-+
-+#define DO_MOVI(N, I) (I)
-+#define DO_ANDI(N, I) ((N) & (I))
-+#define DO_ORRI(N, I) ((N) | (I))
-+
-+DO_1OP_IMM(vmovi, DO_MOVI)
-+DO_1OP_IMM(vandi, DO_ANDI)
-+DO_1OP_IMM(vorri, DO_ORRI)
-+
- #define DO_2OP(OP, ESIZE, TYPE, FN)                                     \
-     void HELPER(glue(mve_, OP))(CPUARMState *env,                       \
-                                 void *vd, void *vn, void *vm)           \
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
-+++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
- typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
- typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
- typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
-+typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
- /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
- static inline long mve_qreg_offset(unsigned reg)
-@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
-     mve_update_eci(s);
-     return true;
- }
-+
-+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
-+{
-+    TCGv_ptr qd;
-+    uint64_t imm;
-+
-+    if (!dc_isar_feature(aa32_mve, s) ||
-+        !mve_check_qreg_bank(s, a->qd) ||
-+        !fn) {
-+        return false;
-+    }
-+    if (!mve_eci_check(s) || !vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    imm = asimd_imm_const(a->imm, a->cmode, a->op);
-+
-+    qd = mve_qreg_ptr(a->qd);
-+    fn(cpu_env, qd, tcg_constant_i64(imm));
-+    tcg_temp_free_ptr(qd);
-+    mve_update_eci(s);
-+    return true;
-+}
-+
-+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
-+{
-+    /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
-+    MVEGenOneOpImmFn *fn;
-+
-+    if ((a->cmode & 1) && a->cmode < 12) {
-+        if (a->op) {
-+            /*
-+             * For op=1, the immediate will be inverted by asimd_imm_const(),
-+             * so the VBIC becomes a logical AND operation.
-+             */
-+            fn = gen_helper_mve_vandi;
-+        } else {
-+            fn = gen_helper_mve_vorri;
-+        }
-+    } else {
-+        /* There is one unallocated cmode/op combination in this space */
-+        if (a->cmode == 15 && a->op == 1) {
-+            return false;
-+        }
-+        /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
-+        fn = gen_helper_mve_vmovi;
-+    }
-+    return do_1imm(s, a, fn);
-+}
---
-.20.1

-[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
+Deleted patch
-Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
-and VQSHLU.
-The size-and-immediate encoding here is the same as Neon, and we
-handle it the same way neon-dp.decode does.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
----
- target/arm/helper-mve.h    | 16 +++++++++++
- target/arm/mve.decode      | 23 +++++++++++++++
- target/arm/mve_helper.c    | 57 ++++++++++++++++++++++++++++++++++++++
- target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
-files changed, 147 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
-+++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
- DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
- DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
- DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
-+
-+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+
-+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+
-+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+
-+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
-+++ b/target/arm/mve.decode
-@@ -XXX,XX +XXX,XX @@
- &2op qd qm qn size
- &2scalar qd qn rm size
- &1imm qd imm cmode op
-+&2shift qd qm shift size
- @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
- # Note that both Rn and Qd are 3 bits only (no D bit)
-@@ -XXX,XX +XXX,XX @@
- @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
- @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
-+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
-+@2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
-+@2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
-+
- # Vector loads and stores
- # Widening loads and narrowing stores:
-@@ -XXX,XX +XXX,XX @@ VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
- # So we have a single decode line and check the cmode/op in the
- # trans function.
- Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
-+
-+# Shifts by immediate
-+
-+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
-+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
-+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
-+
-+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
-+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
-+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
-+
-+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
-+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
-+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
-+
-+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
-+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
-+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve_helper.c
-+++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
-     WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
- #define DO_UQRSHL_OP(N, M, satp) \
-     WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
-+#define DO_SUQSHL_OP(N, M, satp) \
-+    WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
- DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
- DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
-@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
- DO_VADDV(vaddvub, 1, uint8_t)
- DO_VADDV(vaddvuh, 2, uint16_t)
- DO_VADDV(vaddvuw, 4, uint32_t)
-+
-+/* Shifts by immediate */
-+#define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
-+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
-+                                void *vm, uint32_t shift)       \
-+    {                                                           \
-+        TYPE *d = vd, *m = vm;                                  \
-+        uint16_t mask = mve_element_mask(env);                  \
-+        unsigned e;                                             \
-+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
-+            mergemask(&d[H##ESIZE(e)],                          \
-+                      FN(m[H##ESIZE(e)], shift), mask);         \
-+        }                                                       \
-+        mve_advance_vpt(env);                                   \
-+    }
-+
-+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN)                      \
-+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
-+                                void *vm, uint32_t shift)       \
-+    {                                                           \
-+        TYPE *d = vd, *m = vm;                                  \
-+        uint16_t mask = mve_element_mask(env);                  \
-+        unsigned e;                                             \
-+        bool qc = false;                                        \
-+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
-+            bool sat = false;                                   \
-+            mergemask(&d[H##ESIZE(e)],                          \
-+                      FN(m[H##ESIZE(e)], shift, &sat), mask);   \
-+            qc |= sat & mask & 1;                               \
-+        }                                                       \
-+        if (qc) {                                               \
-+            env->vfp.qc[0] = qc;                                \
-+        }                                                       \
-+        mve_advance_vpt(env);                                   \
-+    }
-+
-+/* provide unsigned 2-op shift helpers for all sizes */
-+#define DO_2SHIFT_U(OP, FN)                     \
-+    DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
-+    DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
-+    DO_2SHIFT(OP##w, 4, uint32_t, FN)
-+
-+#define DO_2SHIFT_SAT_U(OP, FN)                 \
-+    DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
-+    DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN)       \
-+    DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
-+#define DO_2SHIFT_SAT_S(OP, FN)                 \
-+    DO_2SHIFT_SAT(OP##b, 1, int8_t, FN)         \
-+    DO_2SHIFT_SAT(OP##h, 2, int16_t, FN)        \
-+    DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
-+
-+DO_2SHIFT_U(vshli_u, DO_VSHLU)
-+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
-+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
-+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
-+++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
- typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
- typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
- typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
-+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
- typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
- typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
- typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
-@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
-     }
-     return do_1imm(s, a, fn);
- }
-+
-+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
-+                      bool negateshift)
-+{
-+    TCGv_ptr qd, qm;
-+    int shift = a->shift;
-+
-+    if (!dc_isar_feature(aa32_mve, s) ||
-+        !mve_check_qreg_bank(s, a->qd | a->qm) ||
-+        !fn) {
-+        return false;
-+    }
-+    if (!mve_eci_check(s) || !vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    /*
-+     * When we handle a right shift insn using a left-shift helper
-+     * which permits a negative shift count to indicate a right-shift,
-+     * we must negate the shift count.
-+     */
-+    if (negateshift) {
-+        shift = -shift;
-+    }
-+
-+    qd = mve_qreg_ptr(a->qd);
-+    qm = mve_qreg_ptr(a->qm);
-+    fn(cpu_env, qd, qm, tcg_constant_i32(shift));
-+    tcg_temp_free_ptr(qd);
-+    tcg_temp_free_ptr(qm);
-+    mve_update_eci(s);
-+    return true;
-+}
-+
-+#define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
-+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
-+    {                                                           \
-+        static MVEGenTwoOpShiftFn * const fns[] = {             \
-+            gen_helper_mve_##FN##b,                             \
-+            gen_helper_mve_##FN##h,                             \
-+            gen_helper_mve_##FN##w,                             \
-+            NULL,                                               \
-+        };                                                      \
-+        return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
-+    }
-+
-+DO_2SHIFT(VSHLI, vshli_u, false)
-+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
-+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
-+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
---
-.20.1

-[PULL 15/24] target/arm: Implement MVE VSHLL
+Deleted patch
-Implement the MVE VHLL (vector shift left long) insn.  This has two
-encodings: the T1 encoding is the usual shift-by-immediate format,
-and the T2 encoding is a special case where the shift count is always
-equal to the element size.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
----
- target/arm/helper-mve.h    |  9 +++++++
- target/arm/mve.decode      | 53 +++++++++++++++++++++++++++++++++++---
- target/arm/mve_helper.c    | 32 +++++++++++++++++++++++
- target/arm/translate-mve.c | 15 +++++++++++
-files changed, 105 insertions(+), 4 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
-+++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+
-+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
-+++ b/target/arm/mve.decode
-@@ -XXX,XX +XXX,XX @@
- @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
- @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
-+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
-+@2_shll_h .... .... ... 1  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
-+# VSHLL encoding T2 where shift == esize
-+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
-+                qd=%qd qm=%qm size=0 shift=8
-+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
-+                qd=%qd qm=%qm size=1 shift=16
-+
- # Right shifts are encoded as N - shift, where N is the element size in bits.
- %rshift_i5  16:5 !function=rsub_32
- %rshift_i4  16:4 !function=rsub_16
-@@ -XXX,XX +XXX,XX @@ VADD             1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
- VSUB             1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
- VMUL             1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
--VMULH_S          111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
--VMULH_U          111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
-+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
-+# overlaps what would be size=0b11 VMULH/VRMULH
-+{
-+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
-+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
--VRMULH_S         111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
--VRMULH_U         111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
-+  VMULH_S        111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
-+}
-+
-+{
-+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
-+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
-+
-+  VMULH_U        111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
-+}
-+
-+{
-+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
-+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
-+
-+  VRMULH_S       111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
-+}
-+
-+{
-+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
-+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
-+
-+  VRMULH_U       111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
-+}
- VMAX_S           111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
- VMAX_U           111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
-@@ -XXX,XX +XXX,XX @@ VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
- VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
- VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
- VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
-+
-+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
-+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
-+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
-+
-+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
-+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
-+
-+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
-+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
-+
-+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
-+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve_helper.c
-+++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
- DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
- DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
- DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
-+
-+/*
-+ * Long shifts taking half-sized inputs from top or bottom of the input
-+ * vector and producing a double-width result. ESIZE, TYPE are for
-+ * the input, and LESIZE, LTYPE for the output.
-+ * Unlike the normal shift helpers, we do not handle negative shift counts,
-+ * because the long shift is strictly left-only.
-+ */
-+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE)                   \
-+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
-+                                void *vm, uint32_t shift)               \
-+    {                                                                   \
-+        LTYPE *d = vd;                                                  \
-+        TYPE *m = vm;                                                   \
-+        uint16_t mask = mve_element_mask(env);                          \
-+        unsigned le;                                                    \
-+        assert(shift <= 16);                                            \
-+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) {         \
-+            LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift;        \
-+            mergemask(&d[H##LESIZE(le)], r, mask);                      \
-+        }                                                               \
-+        mve_advance_vpt(env);                                           \
-+    }
-+
-+#define DO_VSHLL_ALL(OP, TOP)                                \
-+    DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t)             \
-+    DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t)           \
-+    DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t)            \
-+    DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t)          \
-+
-+DO_VSHLL_ALL(vshllb, false)
-+DO_VSHLL_ALL(vshllt, true)
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
-+++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
- DO_2SHIFT(VSHRI_U, vshli_u, true)
- DO_2SHIFT(VRSHRI_S, vrshli_s, true)
- DO_2SHIFT(VRSHRI_U, vrshli_u, true)
-+
-+#define DO_VSHLL(INSN, FN)                                      \
-+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
-+    {                                                           \
-+        static MVEGenTwoOpShiftFn * const fns[] = {             \
-+            gen_helper_mve_##FN##b,                             \
-+            gen_helper_mve_##FN##h,                             \
-+        };                                                      \
-+        return do_2shift(s, a, fns[a->size], false);            \
-+    }
-+
-+DO_VSHLL(VSHLL_BS, vshllbs)
-+DO_VSHLL(VSHLL_BU, vshllbu)
-+DO_VSHLL(VSHLL_TS, vshllts)
-+DO_VSHLL(VSHLL_TU, vshlltu)
---
-.20.1

-[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
+Deleted patch
-Implement the MVE VSRI and VSLI insns, which perform a
-shift-and-insert operation.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
----
- target/arm/helper-mve.h    |  8 ++++++++
- target/arm/mve.decode      |  9 ++++++++
- target/arm/mve_helper.c    | 42 ++++++++++++++++++++++++++++++++++++++
- target/arm/translate-mve.c |  3 +++
-files changed, 62 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
-+++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+
-+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+
-+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
-+++ b/target/arm/mve.decode
-@@ -XXX,XX +XXX,XX @@ VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
- VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
- VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
-+
-+# Shift-and-insert
-+VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
-+VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
-+VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
-+
-+VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
-+VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
-+VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve_helper.c
-+++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
- DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
- DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
-+/* Shift-and-insert; we always work with 64 bits at a time */
-+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN)                    \
-+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
-+                                void *vm, uint32_t shift)               \
-+    {                                                                   \
-+        uint64_t *d = vd, *m = vm;                                      \
-+        uint16_t mask;                                                  \
-+        uint64_t shiftmask;                                             \
-+        unsigned e;                                                     \
-+        if (shift == 0 || shift == ESIZE * 8) {                         \
-+            /*                                                          \
-+             * Only VSLI can shift by 0; only VSRI can shift by <dt>.   \
-+             * The generic logic would give the right answer for 0 but  \
-+             * fails for <dt>.                                          \
-+             */                                                         \
-+            goto done;                                                  \
-+        }                                                               \
-+        assert(shift < ESIZE * 8);                                      \
-+        mask = mve_element_mask(env);                                   \
-+        /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */     \
-+        shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift));     \
-+        for (e = 0; e < 16 / 8; e++, mask >>= 8) {                      \
-+            uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) |       \
-+                (d[H8(e)] & ~shiftmask);                                \
-+            mergemask(&d[H8(e)], r, mask);                              \
-+        }                                                               \
-+done:                                                                   \
-+        mve_advance_vpt(env);                                           \
-+    }
-+
-+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
-+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
-+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
-+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
-+
-+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
-+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
-+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
-+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
-+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
-+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
-+
- /*
-  * Long shifts taking half-sized inputs from top or bottom of the input
-  * vector and producing a double-width result. ESIZE, TYPE are for
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
-+++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
- DO_2SHIFT(VRSHRI_S, vrshli_s, true)
- DO_2SHIFT(VRSHRI_U, vrshli_u, true)
-+DO_2SHIFT(VSRI, vsri, false)
-+DO_2SHIFT(VSLI, vsli, false)
-+
- #define DO_VSHLL(INSN, FN)                                      \
-     static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
-     {                                                           \
---
-.20.1

-[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
+Deleted patch
-Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
-do_urshr() is borrowed from sve_helper.c.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
----
- target/arm/helper-mve.h    | 10 ++++++++++
- target/arm/mve.decode      | 11 +++++++++++
- target/arm/mve_helper.c    | 40 ++++++++++++++++++++++++++++++++++++++
- target/arm/translate-mve.c | 15 ++++++++++++++
-files changed, 76 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
-+++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+
-+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+
-+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
-+++ b/target/arm/mve.decode
-@@ -XXX,XX +XXX,XX @@ VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
- VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
- VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
- VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
-+
-+# Narrowing shifts (which only support b and h sizes)
-+VSHRNB            111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
-+VSHRNB            111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
-+VSHRNT            111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
-+VSHRNT            111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
-+
-+VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
-+VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
-+VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
-+VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve_helper.c
-+++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
- DO_VSHLL_ALL(vshllb, false)
- DO_VSHLL_ALL(vshllt, true)
-+
-+/*
-+ * Narrowing right shifts, taking a double sized input, shifting it
-+ * and putting the result in either the top or bottom half of the output.
-+ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
-+ */
-+#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)       \
-+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
-+                                void *vm, uint32_t shift)       \
-+    {                                                           \
-+        LTYPE *m = vm;                                          \
-+        TYPE *d = vd;                                           \
-+        uint16_t mask = mve_element_mask(env);                  \
-+        unsigned le;                                            \
-+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
-+            TYPE r = FN(m[H##LESIZE(le)], shift);               \
-+            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
-+        }                                                       \
-+        mve_advance_vpt(env);                                   \
-+    }
-+
-+#define DO_VSHRN_ALL(OP, FN)                                    \
-+    DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN)        \
-+    DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN)       \
-+    DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN)         \
-+    DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
-+
-+static inline uint64_t do_urshr(uint64_t x, unsigned sh)
-+{
-+    if (likely(sh < 64)) {
-+        return (x >> sh) + ((x >> (sh - 1)) & 1);
-+    } else if (sh == 64) {
-+        return x >> 63;
-+    } else {
-+        return 0;
-+    }
-+}
-+
-+DO_VSHRN_ALL(vshrn, DO_SHR)
-+DO_VSHRN_ALL(vrshrn, do_urshr)
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
-+++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
- DO_VSHLL(VSHLL_BU, vshllbu)
- DO_VSHLL(VSHLL_TS, vshllts)
- DO_VSHLL(VSHLL_TU, vshlltu)
-+
-+#define DO_2SHIFT_N(INSN, FN)                                   \
-+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
-+    {                                                           \
-+        static MVEGenTwoOpShiftFn * const fns[] = {             \
-+            gen_helper_mve_##FN##b,                             \
-+            gen_helper_mve_##FN##h,                             \
-+        };                                                      \
-+        return do_2shift(s, a, fns[a->size], false);            \
-+    }
-+
-+DO_2SHIFT_N(VSHRNB, vshrnb)
-+DO_2SHIFT_N(VSHRNT, vshrnt)
-+DO_2SHIFT_N(VRSHRNB, vrshrnb)
-+DO_2SHIFT_N(VRSHRNT, vrshrnt)
---
-.20.1

-[PULL 19/24] target/arm: Implement MVE VSHLC
+Deleted patch
-Implement the MVE VSHLC insn, which performs a shift left of the
-entire vector with carry in bits provided from a general purpose
-register and carry out bits written back to that register.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
----
- target/arm/helper-mve.h    |  2 ++
- target/arm/mve.decode      |  2 ++
- target/arm/mve_helper.c    | 38 ++++++++++++++++++++++++++++++++++++++
- target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
-files changed, 72 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
-+++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+
-+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
-+++ b/target/arm/mve.decode
-@@ -XXX,XX +XXX,XX @@ VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
- VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
- VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
- VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
-+
-+VSHLC             111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve_helper.c
-+++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
- DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
- DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
- DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
-+
-+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
-+                           uint32_t shift)
-+{
-+    uint32_t *d = vd;
-+    uint16_t mask = mve_element_mask(env);
-+    unsigned e;
-+    uint32_t r;
-+
-+    /*
-+     * For each 32-bit element, we shift it left, bringing in the
-+     * low 'shift' bits of rdm at the bottom. Bits shifted out at
-+     * the top become the new rdm, if the predicate mask permits.
-+     * The final rdm value is returned to update the register.
-+     * shift == 0 here means "shift by 32 bits".
-+     */
-+    if (shift == 0) {
-+        for (e = 0; e < 16 / 4; e++, mask >>= 4) {
-+            r = rdm;
-+            if (mask & 1) {
-+                rdm = d[H4(e)];
-+            }
-+            mergemask(&d[H4(e)], r, mask);
-+        }
-+    } else {
-+        uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
-+
-+        for (e = 0; e < 16 / 4; e++, mask >>= 4) {
-+            r = (d[H4(e)] << shift) | (rdm & shiftmask);
-+            if (mask & 1) {
-+                rdm = d[H4(e)] >> (32 - shift);
-+            }
-+            mergemask(&d[H4(e)], r, mask);
-+        }
-+    }
-+    mve_advance_vpt(env);
-+    return rdm;
-+}
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
-+++ b/target/arm/translate-mve.c
-@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
- DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
- DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
- DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
-+
-+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
-+{
-+    /*
-+     * Whole Vector Left Shift with Carry. The carry is taken
-+     * from a general purpose register and written back there.
-+     * An imm of 0 means "shift by 32".
-+     */
-+    TCGv_ptr qd;
-+    TCGv_i32 rdm;
-+
-+    if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
-+        return false;
-+    }
-+    if (a->rdm == 13 || a->rdm == 15) {
-+        /* CONSTRAINED UNPREDICTABLE: we UNDEF */
-+        return false;
-+    }
-+    if (!mve_eci_check(s) || !vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    qd = mve_qreg_ptr(a->qd);
-+    rdm = load_reg(s, a->rdm);
-+    gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
-+    store_reg(s, a->rdm, rdm);
-+    tcg_temp_free_ptr(qd);
-+    mve_update_eci(s);
-+    return true;
-+}
---
-.20.1

-[PULL 21/24] target/arm: Implement MVE long shifts by immediate
+Deleted patch
-The MVE extension to v8.1M includes some new shift instructions which
-sit entirely within the non-coprocessor part of the encoding space
-and which operate only on general-purpose registers.  They take up
-the space which was previously UNPREDICTABLE MOVS and ORRS encodings
-with Rm == 13 or 15.
-Implement the long shifts by immediate, which perform shifts on a
-pair of general-purpose registers treated as a 64-bit quantity, with
-an immediate shift count between 1 and 32.
-Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
-the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
-cases where v8.1M now requires that.  (Trying to change MOVS and ORRS
-is too difficult, because the functions that generate the code are
-shared between a dozen different kinds of arithmetic or logical
-instruction for all A32, T16 and T32 encodings, and for some insns
-and some encodings Rm==13,15 are valid.)
-We make the helper functions we need for UQSHLL and SQSHLL take
-a 32-bit value which the helper casts to int8_t because we'll need
-these helpers also for the shift-by-register insns, where the shift
-count might be < 0 or > 32.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
----
- target/arm/helper-mve.h |  3 ++
- target/arm/translate.h  |  1 +
- target/arm/t32.decode   | 28 +++++++++++++
- target/arm/mve_helper.c | 10 +++++
- target/arm/translate.c  | 90 +++++++++++++++++++++++++++++++++++++++++
-files changed, 132 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
-+++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
-+
-+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
-+++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
- typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
- typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
- typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
-+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
- /**
-  * arm_tbflags_from_tb:
-diff --git a/target/arm/t32.decode b/target/arm/t32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/t32.decode
-+++ b/target/arm/t32.decode
-@@ -XXX,XX +XXX,XX @@
- &mcr             !extern cp opc1 crn crm opc2 rt
- &mcrr            !extern cp opc1 crm rt rt2
-+&mve_shl_ri      rdalo rdahi shim
-+
-+# rdahi: bits [3:1] from insn, bit 0 is 1
-+# rdalo: bits [3:1] from insn, bit 0 is 0
-+%rdahi_9 9:3 !function=times_2_plus_1
-+%rdalo_17 17:3 !function=times_2
-+
- # Data-processing (register)
- %imm5_12_6       12:3 6:2
-@@ -XXX,XX +XXX,XX @@
- @S_xrr_shi       ....... .... .   rn:4 .... .... .. shty:2 rm:4 \
-                  &s_rrr_shi shim=%imm5_12_6 s=1 rd=0
-+@mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
-+                 &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
-+
- {
-   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
-   AND_rrri       1110101 0000 . .... 0 ... .... .... ....     @s_rrr_shi
- }
- BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
- {
-+  # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
-+  # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
-+  # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
-+  # they explicitly call unallocated_encoding() for cases that must UNDEF
-+  # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
-+  # the rest fall through (where ORR_rrri and MOV_rxri will end up
-+  # handling them as r13 and r15 accesses with the same semantics as A32).
-+  [
-+    LSLL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
-+    LSRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
-+    ASRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
-+
-+    UQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
-+    URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
-+    SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
-+    SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
-+  ]
-+
-   MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
-   ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
- }
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve_helper.c
-+++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
-     mve_advance_vpt(env);
-     return rdm;
- }
-+
-+uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
-+{
-+    return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
-+}
-+
-+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
-+{
-+    return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
-     return true;
- }
-+/*
-+ * v8.1M MVE wide-shifts
-+ */
-+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
-+                          WideShiftImmFn *fn)
-+{
-+    TCGv_i64 rda;
-+    TCGv_i32 rdalo, rdahi;
-+
-+    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
-+        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
-+        return false;
-+    }
-+    if (a->rdahi == 15) {
-+        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
-+        return false;
-+    }
-+    if (!dc_isar_feature(aa32_mve, s) ||
-+        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
-+        a->rdahi == 13) {
-+        /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
-+        unallocated_encoding(s);
-+        return true;
-+    }
-+
-+    if (a->shim == 0) {
-+        a->shim = 32;
-+    }
-+
-+    rda = tcg_temp_new_i64();
-+    rdalo = load_reg(s, a->rdalo);
-+    rdahi = load_reg(s, a->rdahi);
-+    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
-+
-+    fn(rda, rda, a->shim);
-+
-+    tcg_gen_extrl_i64_i32(rdalo, rda);
-+    tcg_gen_extrh_i64_i32(rdahi, rda);
-+    store_reg(s, a->rdalo, rdalo);
-+    store_reg(s, a->rdahi, rdahi);
-+    tcg_temp_free_i64(rda);
-+
-+    return true;
-+}
-+
-+static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
-+{
-+    return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
-+}
-+
-+static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
-+{
-+    return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
-+}
-+
-+static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
-+{
-+    return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
-+}
-+
-+static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
-+{
-+    gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
-+}
-+
-+static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
-+{
-+    return do_mve_shl_ri(s, a, gen_mve_sqshll);
-+}
-+
-+static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
-+{
-+    gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
-+}
-+
-+static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
-+{
-+    return do_mve_shl_ri(s, a, gen_mve_uqshll);
-+}
-+
-+static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
-+{
-+    return do_mve_shl_ri(s, a, gen_srshr64_i64);
-+}
-+
-+static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
-+{
-+    return do_mve_shl_ri(s, a, gen_urshr64_i64);
-+}
-+
- /*
-  * Multiply and multiply accumulate
-  */
---
-.20.1

-[PULL 22/24] target/arm: Implement MVE long shifts by register
+Deleted patch
-Implement the MVE long shifts by register, which perform shifts on a
-pair of general-purpose registers treated as a 64-bit quantity, with
-the shift count in another general-purpose register, which might be
-either positive or negative.
-Like the long-shifts-by-immediate, these encodings sit in the space
-that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
-Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
-also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
-we have to move the CSEL pattern into the same decodetree group.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
----
- target/arm/helper-mve.h |  6 +++
- target/arm/translate.h  |  1 +
- target/arm/t32.decode   | 16 +++++--
- target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
- target/arm/translate.c  | 69 ++++++++++++++++++++++++++++++
-files changed, 182 insertions(+), 3 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
-+++ b/target/arm/helper-mve.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
- DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
-+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
- DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
- DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
-+++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
- typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
- typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
- typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
-+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
- /**
-  * arm_tbflags_from_tb:
-diff --git a/target/arm/t32.decode b/target/arm/t32.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/t32.decode
-+++ b/target/arm/t32.decode
-@@ -XXX,XX +XXX,XX @@
- &mcrr            !extern cp opc1 crm rt rt2
- &mve_shl_ri      rdalo rdahi shim
-+&mve_shl_rr      rdalo rdahi rm
- # rdahi: bits [3:1] from insn, bit 0 is 1
- # rdalo: bits [3:1] from insn, bit 0 is 0
-@@ -XXX,XX +XXX,XX @@
- @mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
-                  &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
-+@mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
-+                 &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
- {
-   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
-@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
-     URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
-     SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
-     SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
-+
-+    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
-+    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
-+    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
-+    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
-+    UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
-+    SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
-   ]
-   MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
-   ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
-+
-+  # v8.1M CSEL and friends
-+  CSEL           1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
- }
- {
-   MVN_rxri       1110101 0011 . 1111 0 ... .... .... ....     @s_rxr_shi
-@@ -XXX,XX +XXX,XX @@ SBC_rrri         1110101 1011 . .... 0 ... .... .... ....     @s_rrr_shi
- }
- RSB_rrri         1110101 1110 . .... 0 ... .... .... ....     @s_rrr_shi
--# v8.1M CSEL and friends
--CSEL             1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
--
- # Data-processing (register-shifted register)
- MOV_rxrr         1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve_helper.c
-+++ b/target/arm/mve_helper.c
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
-     return rdm;
- }
-+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
-+{
-+    return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
-+}
-+
-+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
-+{
-+    return do_uqrshl_d(n, (int8_t)shift, false, NULL);
-+}
-+
- uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
- {
-     return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
-@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
- {
-     return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
- }
-+
-+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
-+{
-+    return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
-+}
-+
-+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
-+{
-+    return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
-+}
-+
-+/* Operate on 64-bit values, but saturate at 48 bits */
-+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
-+                                    bool round, uint32_t *sat)
-+{
-+    if (shift <= -48) {
-+        /* Rounding the sign bit always produces 0. */
-+        if (round) {
-+            return 0;
-+        }
-+        return src >> 63;
-+    } else if (shift < 0) {
-+        if (round) {
-+            src >>= -shift - 1;
-+            return (src >> 1) + (src & 1);
-+        }
-+        return src >> -shift;
-+    } else if (shift < 48) {
-+        int64_t val = src << shift;
-+        int64_t extval = sextract64(val, 0, 48);
-+        if (!sat || val == extval) {
-+            return extval;
-+        }
-+    } else if (!sat || src == 0) {
-+        return 0;
-+    }
-+
-+    *sat = 1;
-+    return (1ULL << 47) - (src >= 0);
-+}
-+
-+/* Operate on 64-bit values, but saturate at 48 bits */
-+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
-+                                     bool round, uint32_t *sat)
-+{
-+    uint64_t val, extval;
-+
-+    if (shift <= -(48 + round)) {
-+        return 0;
-+    } else if (shift < 0) {
-+        if (round) {
-+            val = src >> (-shift - 1);
-+            val = (val >> 1) + (val & 1);
-+        } else {
-+            val = src >> -shift;
-+        }
-+        extval = extract64(val, 0, 48);
-+        if (!sat || val == extval) {
-+            return extval;
-+        }
-+    } else if (shift < 48) {
-+        uint64_t val = src << shift;
-+        uint64_t extval = extract64(val, 0, 48);
-+        if (!sat || val == extval) {
-+            return extval;
-+        }
-+    } else if (!sat || src == 0) {
-+        return 0;
-+    }
-+
-+    *sat = 1;
-+    return MAKE_64BIT_MASK(0, 48);
-+}
-+
-+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
-+{
-+    return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
-+}
-+
-+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
-+{
-+    return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
-     return do_mve_shl_ri(s, a, gen_urshr64_i64);
- }
-+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
-+{
-+    TCGv_i64 rda;
-+    TCGv_i32 rdalo, rdahi;
-+
-+    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
-+        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
-+        return false;
-+    }
-+    if (a->rdahi == 15) {
-+        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
-+        return false;
-+    }
-+    if (!dc_isar_feature(aa32_mve, s) ||
-+        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
-+        a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
-+        a->rm == a->rdahi || a->rm == a->rdalo) {
-+        /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
-+        unallocated_encoding(s);
-+        return true;
-+    }
-+
-+    rda = tcg_temp_new_i64();
-+    rdalo = load_reg(s, a->rdalo);
-+    rdahi = load_reg(s, a->rdahi);
-+    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
-+
-+    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
-+    fn(rda, cpu_env, rda, cpu_R[a->rm]);
-+
-+    tcg_gen_extrl_i64_i32(rdalo, rda);
-+    tcg_gen_extrh_i64_i32(rdahi, rda);
-+    store_reg(s, a->rdalo, rdalo);
-+    store_reg(s, a->rdahi, rdahi);
-+    tcg_temp_free_i64(rda);
-+
-+    return true;
-+}
-+
-+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
-+{
-+    return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
-+}
-+
-+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
-+{
-+    return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
-+}
-+
-+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
-+{
-+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
-+}
-+
-+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
-+{
-+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
-+}
-+
-+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
-+{
-+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
-+}
-+
-+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
-+{
-+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
-+}
-+
- /*
-  * Multiply and multiply accumulate
-  */
---
-.20.1

-[PULL 23/24] target/arm: Implement MVE shifts by immediate
+[PULL 11/11] target/xtensa: Assert that interrupt level is within bounds
-Implement the MVE shifts by immediate, which perform shifts
+In handle_interrupt() we use level as an index into the interrupt_vector[]
-on a single general-purpose register.
+array. This is safe because we have checked it against env->config->nlevel,
 but Coverity can't see that (and it is only true because each CPU config
 sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it
 complains about a possible array overrun (CID 1507131)
-These patterns overlap with the long-shift-by-immediates,
+Add an assert() which will make Coverity happy and catch the unlikely
-so we have to rearrange the grouping a little here.
+case of a mis-set XCHAL_NUM_INTLEVELS in future.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Acked-by: Max Filippov <jcmvbkbc@gmail.com>
-Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
+Message-id: 20230623154135.1930261-1-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h |  3 ++
+ target/xtensa/exc_helper.c | 3 +++
- target/arm/translate.h  |  1 +
+file changed, 3 insertions(+)
  target/arm/t32.decode   | 31 ++++++++++++++-----
  target/arm/mve_helper.c | 10 ++++++
  target/arm/translate.c  | 68 +++++++++++++++++++++++++++++++++++++++--
 files changed, 104 insertions(+), 9 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/xtensa/exc_helper.c
-+++ b/target/arm/helper-mve.h
++++ b/target/xtensa/exc_helper.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+@@ -XXX,XX +XXX,XX @@ static void handle_interrupt(CPUXtensaState *env)
- DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+         CPUState *cs = env_cpu(env);
- DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
- DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
+         if (level > 1) {
 +            /* env->config->nlevel check should have ensured this */
 +            assert(level < sizeof(env->config->interrupt_vector));
 +
-+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
+             env->sregs[EPC1 + level - 1] = env->pc;
-+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
+             env->sregs[EPS2 + level - 2] = env->sregs[PS];
-diff --git a/target/arm/translate.h b/target/arm/translate.h
+             env->sregs[PS] =
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
  typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
  typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
 +typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
  /**
   * arm_tbflags_from_tb:
 diff --git a/target/arm/t32.decode b/target/arm/t32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/t32.decode
 +++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@
  &mve_shl_ri      rdalo rdahi shim
  &mve_shl_rr      rdalo rdahi rm
 +&mve_sh_ri       rda shim
  # rdahi: bits [3:1] from insn, bit 0 is 1
  # rdalo: bits [3:1] from insn, bit 0 is 0
@@ -XXX,XX +XXX,XX @@
                   &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
  @mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
                   &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
 +@mve_sh_ri       ....... .... . rda:4 . ... ... . .. .. .... \
 +                 &mve_sh_ri shim=%imm5_12_6
  {
    TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
    # the rest fall through (where ORR_rrri and MOV_rxri will end up
    # handling them as r13 and r15 accesses with the same semantics as A32).
    [
 -    LSLL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
 -    LSRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
 -    ASRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +    {
 +      UQSHL_ri   1110101 0010 1 ....  0 ...  1111 .. 00 1111  @mve_sh_ri
 +      LSLL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +      UQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +    }
 -    UQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
 -    URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
 -    SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
 -    SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +    {
 +      URSHR_ri   1110101 0010 1 ....  0 ...  1111 .. 01 1111  @mve_sh_ri
 +      LSRL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +      URSHRL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +    }
 +
 +    {
 +      SRSHR_ri   1110101 0010 1 ....  0 ...  1111 .. 10 1111  @mve_sh_ri
 +      ASRL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +      SRSHRL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +    }
 +
 +    {
 +      SQSHL_ri   1110101 0010 1 ....  0 ...  1111 .. 11 1111  @mve_sh_ri
 +      SQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +    }
      LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
      ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
  {
      return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
  }
 +
 +uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
 +{
 +    return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
 +}
 +
 +uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
 +{
 +    return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
  static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
  {
 -    TCGv_i32 t = tcg_temp_new_i32();
 +    TCGv_i32 t;
 +    /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
 +    if (sh == 32) {
 +        tcg_gen_movi_i32(d, 0);
 +        return;
 +    }
 +    t = tcg_temp_new_i32();
      tcg_gen_extract_i32(t, a, sh - 1, 1);
      tcg_gen_sari_i32(d, a, sh);
      tcg_gen_add_i32(d, d, t);
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
  static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
  {
 -    TCGv_i32 t = tcg_temp_new_i32();
 +    TCGv_i32 t;
 +    /* Handle shift by the input size for the benefit of trans_URSHR_ri */
 +    if (sh == 32) {
 +        tcg_gen_extract_i32(d, a, sh - 1, 1);
 +        return;
 +    }
 +    t = tcg_temp_new_i32();
      tcg_gen_extract_i32(t, a, sh - 1, 1);
      tcg_gen_shri_i32(d, a, sh);
      tcg_gen_add_i32(d, d, t);
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
      return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
  }
 +static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
 +{
 +    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 +        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
 +        return false;
 +    }
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
 +        a->rda == 13 || a->rda == 15) {
 +        /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
 +    if (a->shim == 0) {
 +        a->shim = 32;
 +    }
 +    fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
 +
 +    return true;
 +}
 +
 +static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_urshr32_i32);
 +}
 +
 +static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_srshr32_i32);
 +}
 +
 +static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
 +{
 +    gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_mve_sqshl);
 +}
 +
 +static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
 +{
 +    gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_mve_uqshl);
 +}
 +
  /*
   * Multiply and multiply accumulate
   */
 --
-.20.1
+.34.1

The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:

Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702

for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:

target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)

----------------------------------------------------------------
target-arm queue:
 * more MVE instructions
 * hw/gpio/gpio_pwr: use shutdown function for reboot
 * target/arm: Check NaN mode before silencing NaN
 * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
 * hw/arm: Add basic power management to raspi.
 * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc

----------------------------------------------------------------
Joe Komlodi (1):
      target/arm: Check NaN mode before silencing NaN

Maxim Uvarov (1):
      hw/gpio/gpio_pwr: use shutdown function for reboot

Nolan Leake (1):
      hw/arm: Add basic power management to raspi.

Patrick Venture (2):
      docs/system/arm: Add quanta-q7l1-bmc reference
      docs/system/arm: Add quanta-gbs-bmc reference

Peter Maydell (18):
      target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
      target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
      target/arm: Make asimd_imm_const() public
      target/arm: Use asimd_imm_const for A64 decode
      target/arm: Use dup_const() instead of bitfield_replicate()
      target/arm: Implement MVE logical immediate insns
      target/arm: Implement MVE vector shift left by immediate insns
      target/arm: Implement MVE vector shift right by immediate insns
      target/arm: Implement MVE VSHLL
      target/arm: Implement MVE VSRI, VSLI
      target/arm: Implement MVE VSHRN, VRSHRN
      target/arm: Implement MVE saturating narrowing shifts
      target/arm: Implement MVE VSHLC
      target/arm: Implement MVE VADDLV
      target/arm: Implement MVE long shifts by immediate
      target/arm: Implement MVE long shifts by register
      target/arm: Implement MVE shifts by immediate
      target/arm: Implement MVE shifts by register

Philippe Mathieu-Daudé (1):
      tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine

docs/system/arm/aspeed.rst             |   1 +
 docs/system/arm/nuvoton.rst            |   5 +-
 include/hw/arm/bcm2835_peripherals.h   |   3 +-
 include/hw/misc/bcm2835_powermgt.h     |  29 ++
 target/arm/helper-mve.h                | 108 +++++++
 target/arm/translate.h                 |  41 +++
 target/arm/mve.decode                  | 177 ++++++++++-
 target/arm/t32.decode                  |  71 ++++-
 hw/arm/bcm2835_peripherals.c           |  13 +-
 hw/gpio/gpio_pwr.c                     |   2 +-
 hw/misc/bcm2835_powermgt.c             | 160 ++++++++++
 target/arm/helper-a64.c                |  12 +-
 target/arm/mve_helper.c                | 524 +++++++++++++++++++++++++++++++--
 target/arm/translate-a64.c             |  86 +-----
 target/arm/translate-mve.c             | 261 +++++++++++++++-
 target/arm/translate-neon.c            |  81 -----
 target/arm/translate.c                 | 327 +++++++++++++++++++-
 target/arm/vfp_helper.c                |  24 +-
 hw/misc/meson.build                    |   1 +
 tests/acceptance/boot_linux_console.py |  43 +++
 20 files changed, 1760 insertions(+), 209 deletions(-)
 create mode 100644 include/hw/misc/bcm2835_powermgt.h
 create mode 100644 hw/misc/bcm2835_powermgt.c

From: Patrick Venture <venture@google.com>

Add line item reference to quanta-gbs-bmc machine.

Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20210615192848.1065297-3-venture@google.com
[PMM: fixed underline Sphinx warning]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
-=====================================================
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
+================================================================
 
 The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
 designed to be used as Baseboard Management Controllers (BMCs) in various
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
 Hyperscale applications. The following machines are based on this chip :
 
+- ``quanta-gbs-bmc``    Quanta GBS server BMC
 - ``quanta-gsj``        Quanta GSJ server BMC
 
 There are also two more SoCs, NPCM710 and NPCM705, which are single-core
-- 
2.20.1

From: Nolan Leake <nolan@sigbus.net>

This is just enough to make reboot and poweroff work. Works for
linux, u-boot, and the arm trusted firmware. Not tested, but should
work for plan9, and bare-metal/hobby OSes, since they seem to generally
do what linux does for reset.

The watchdog timer functionality is not yet implemented.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
Signed-off-by: Nolan Leake <nolan@sigbus.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
[PMM: tweaked commit title; fixed region size to 0x200;
 moved header file to include/]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bcm2835_peripherals.h |   3 +-
 include/hw/misc/bcm2835_powermgt.h   |  29 +++++
 hw/arm/bcm2835_peripherals.c         |  13 ++-
 hw/misc/bcm2835_powermgt.c           | 160 +++++++++++++++++++++++++++
 hw/misc/meson.build                  |   1 +
 5 files changed, 204 insertions(+), 2 deletions(-)
 create mode 100644 include/hw/misc/bcm2835_powermgt.h
 create mode 100644 hw/misc/bcm2835_powermgt.c

diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2835_peripherals.h
+++ b/include/hw/arm/bcm2835_peripherals.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/bcm2835_mphi.h"
 #include "hw/misc/bcm2835_thermal.h"
 #include "hw/misc/bcm2835_cprman.h"
+#include "hw/misc/bcm2835_powermgt.h"
 #include "hw/sd/sdhci.h"
 #include "hw/sd/bcm2835_sdhost.h"
 #include "hw/gpio/bcm2835_gpio.h"
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
     BCM2835MphiState mphi;
     UnimplementedDeviceState txp;
     UnimplementedDeviceState armtmr;
-    UnimplementedDeviceState powermgt;
+    BCM2835PowerMgtState powermgt;
     BCM2835CprmanState cprman;
     PL011State uart0;
     BCM2835AuxState aux;
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/bcm2835_powermgt.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 Power Management emulation
+ *
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef BCM2835_POWERMGT_H
+#define BCM2835_POWERMGT_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
+
+struct BCM2835PowerMgtState {
+    SysBusDevice busdev;
+    MemoryRegion iomem;
+
+    uint32_t rstc;
+    uint32_t rsts;
+    uint32_t wdog;
+};
+
+#endif
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
 
     object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
                                    OBJECT(&s->gpu_bus_mr));
+
+    /* Power Management */
+    object_initialize_child(obj, "powermgt", &s->powermgt,
+                            TYPE_BCM2835_POWERMGT);
 }
 
 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
         qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
                                INTERRUPT_USB));
 
+    /* Power Management */
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
+        return;
+    }
+
+    memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
+                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
+
     create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
-    create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
     create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
     create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
     create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/bcm2835_powermgt.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 Power Management emulation
+ *
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/bcm2835_powermgt.h"
+#include "migration/vmstate.h"
+#include "sysemu/runstate.h"
+
+#define PASSWORD 0x5a000000
+#define PASSWORD_MASK 0xff000000
+
+#define R_RSTC 0x1c
+#define V_RSTC_RESET 0x20
+#define R_RSTS 0x20
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
+#define R_WDOG 0x24
+
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
+                                      unsigned size)
+{
+    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
+    uint32_t res = 0;
+
+    switch (offset) {
+    case R_RSTC:
+        res = s->rstc;
+        break;
+    case R_RSTS:
+        res = s->rsts;
+        break;
+    case R_WDOG:
+        res = s->wdog;
+        break;
+
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
+                      "\n", offset);
+        res = 0;
+        break;
+    }
+
+    return res;
+}
+
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
+                                   uint64_t value, unsigned size)
+{
+    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
+
+    if ((value & PASSWORD_MASK) != PASSWORD) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "bcm2835_powermgt_write: Bad password 0x%"PRIx64
+                      " at offset 0x%08"HWADDR_PRIx"\n",
+                      value, offset);
+        return;
+    }
+
+    value = value & ~PASSWORD_MASK;
+
+    switch (offset) {
+    case R_RSTC:
+        s->rstc = value;
+        if (value & V_RSTC_RESET) {
+            if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
+                qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+            } else {
+                qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+            }
+        }
+        break;
+    case R_RSTS:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: RSTS\n");
+        s->rsts = value;
+        break;
+    case R_WDOG:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: WDOG\n");
+        s->wdog = value;
+        break;
+
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
+                      "\n", offset);
+        break;
+    }
+}
+
+static const MemoryRegionOps bcm2835_powermgt_ops = {
+    .read = bcm2835_powermgt_read,
+    .write = bcm2835_powermgt_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const VMStateDescription vmstate_bcm2835_powermgt = {
+    .name = TYPE_BCM2835_POWERMGT,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
+        VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
+        VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void bcm2835_powermgt_init(Object *obj)
+{
+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
+
+    memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
+                          TYPE_BCM2835_POWERMGT, 0x200);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static void bcm2835_powermgt_reset(DeviceState *dev)
+{
+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
+
+    /* https://elinux.org/BCM2835_registers#PM */
+    s->rstc = 0x00000102;
+    s->rsts = 0x00001000;
+    s->wdog = 0x00000000;
+}
+
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = bcm2835_powermgt_reset;
+    dc->vmsd = &vmstate_bcm2835_powermgt;
+}
+
+static TypeInfo bcm2835_powermgt_info = {
+    .name          = TYPE_BCM2835_POWERMGT,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(BCM2835PowerMgtState),
+    .class_init    = bcm2835_powermgt_class_init,
+    .instance_init = bcm2835_powermgt_init,
+};
+
+static void bcm2835_powermgt_register_types(void)
+{
+    type_register_static(&bcm2835_powermgt_info);
+}
+
+type_init(bcm2835_powermgt_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
   'bcm2835_rng.c',
   'bcm2835_thermal.c',
   'bcm2835_cprman.c',
+  'bcm2835_powermgt.c',
 ))
 softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
 softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Add a test booting and quickly shutdown a raspi2 machine,
to test the power management model:

(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
  console: [    0.000000] Booting Linux on physical CPU 0xf00
  console: [    0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
  console: [    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
  console: [    0.000000] CPU: div instructions available: patching division code
  console: [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  console: [    0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
  ...
  console: Boot successful.
  console: cat /proc/cpuinfo
  console: / # cat /proc/cpuinfo
  ...
  console: processor      : 3
  console: model name     : ARMv7 Processor rev 5 (v7l)
  console: BogoMIPS       : 125.00
  console: Features       : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
  console: CPU implementer        : 0x41
  console: CPU architecture: 7
  console: CPU variant    : 0x0
  console: CPU part       : 0xc07
  console: CPU revision   : 5
  console: Hardware       : BCM2835
  console: Revision       : 0000
  console: Serial         : 0000000000000000
  console: cat /proc/iomem
  console: / # cat /proc/iomem
  console: 00000000-3bffffff : System RAM
  console: 00008000-00afffff : Kernel code
  console: 00c00000-00d468ef : Kernel data
  console: 3f006000-3f006fff : dwc_otg
  console: 3f007000-3f007eff : /soc/dma@7e007000
  console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
  console: 3f100000-3f100027 : /soc/watchdog@7e100000
  console: 3f101000-3f102fff : /soc/cprman@7e101000
  console: 3f200000-3f2000b3 : /soc/gpio@7e200000
  PASS (24.59 s)
  RESULTS    : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
  JOB TIME   : 25.02 s

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@
 from avocado import skip
 from avocado import skipUnless
 from avocado_qemu import Test
+from avocado_qemu import exec_command
 from avocado_qemu import exec_command_and_wait_for_pattern
 from avocado_qemu import interrupt_interactive_console_until_pattern
 from avocado_qemu import wait_for_console_pattern
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
         """
         self.do_test_arm_raspi2(0)
 
+    def test_arm_raspi2_initrd(self):
+        """
+        :avocado: tags=arch:arm
+        :avocado: tags=machine:raspi2
+        """
+        deb_url = ('http://archive.raspberrypi.org/debian/'
+                   'pool/main/r/raspberrypi-firmware/'
+                   'raspberrypi-kernel_1.20190215-1_armhf.deb')
+        deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
+        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+        kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
+        dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
+
+        initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
+                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
+                      'arm/rootfs-armv7a.cpio.gz')
+        initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
+        initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
+        initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
+        archive.gzip_uncompress(initrd_path_gz, initrd_path)
+
+        self.vm.set_console()
+        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+                               'earlycon=pl011,0x3f201000 console=ttyAMA0 '
+                               'panic=-1 noreboot ' +
+                               'dwc_otg.fiq_fsm_enable=0')
+        self.vm.add_args('-kernel', kernel_path,
+                         '-dtb', dtb_path,
+                         '-initrd', initrd_path,
+                         '-append', kernel_command_line,
+                         '-no-reboot')
+        self.vm.launch()
+        self.wait_for_console_pattern('Boot successful.')
+
+        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+                                                'BCM2835')
+        exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
+                                                '/soc/cprman@7e101000')
+        exec_command(self, 'halt')
+        # Wait for VM to shut down gracefully
+        self.vm.wait()
+
     def test_arm_exynos4210_initrd(self):
         """
         :avocado: tags=arch:arm
-- 
2.20.1

From: Joe Komlodi <joe.komlodi@xilinx.com>

If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
assert due to fpst->default_nan_mode being set.

To avoid this, we check to see what NaN mode we're running in before we call
floatxx_silence_nan().

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.c | 12 +++++++++---
 target/arm/vfp_helper.c | 24 ++++++++++++++++++------
 2 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
         float16 nan = a;
         if (float16_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float16_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float16_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
         float32 nan = a;
         if (float32_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float32_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float32_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
         float64 nan = a;
         if (float64_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float64_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float64_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float64_default_nan(fpst);
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
         float16 nan = f16;
         if (float16_is_signaling_nan(f16, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float16_silence_nan(f16, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float16_silence_nan(f16, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
         float32 nan = f32;
         if (float32_is_signaling_nan(f32, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float32_silence_nan(f32, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float32_silence_nan(f32, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
         float64 nan = f64;
         if (float64_is_signaling_nan(f64, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float64_silence_nan(f64, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float64_silence_nan(f64, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float64_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
         float16 nan = f16;
         if (float16_is_signaling_nan(f16, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float16_silence_nan(f16, s);
+            if (!s->default_nan_mode) {
+                nan = float16_silence_nan(f16, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float16_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
         float32 nan = f32;
         if (float32_is_signaling_nan(f32, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float32_silence_nan(f32, s);
+            if (!s->default_nan_mode) {
+                nan = float32_silence_nan(f32, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float32_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
         float64 nan = f64;
         if (float64_is_signaling_nan(f64, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float64_silence_nan(f64, s);
+            if (!s->default_nan_mode) {
+                nan = float64_silence_nan(f64, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float64_default_nan(s);
-- 
2.20.1

From: Maxim Uvarov <maxim.uvarov@linaro.org>

qemu has 2 type of functions: shutdown and reboot. Shutdown
function has to be used for machine shutdown. Otherwise we cause
a reset with a bogus "cause" value, when we intended a shutdown.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/gpio/gpio_pwr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/gpio_pwr.c
+++ b/hw/gpio/gpio_pwr.c
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
 static void gpio_pwr_shutdown(void *opaque, int n, int level)
 {
     if (level) {
-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
     }
 }
 
-- 
2.20.1

In do_ldst(), the calculation of the offset needs to be based on the
size of the memory access, not the size of the elements in the
vector.  This meant we were getting it wrong for the widening and
narrowing variants of the various VLDR and VSTR insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
---
 target/arm/translate-mve.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
     }
 }
 
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
+                    unsigned msize)
 {
     TCGv_i32 addr;
     uint32_t offset;
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
         return true;
     }
 
-    offset = a->imm << a->size;
+    offset = a->imm << msize;
     if (!a->a) {
         offset = -offset;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
         { gen_helper_mve_vstrw, gen_helper_mve_vldrw },
         { NULL, NULL }
     };
-    return do_ldst(s, a, ldstfns[a->size][a->l]);
+    return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
 }
 
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST)                  \
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE)           \
     static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
     {                                                           \
         static MVEGenLdStFn * const ldstfns[2][2] = {           \
             { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
             { NULL, gen_helper_mve_##ULD },                     \
         };                                                      \
-        return do_ldst(s, a, ldstfns[a->u][a->l]);              \
+        return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE);       \
     }
 
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
 
 static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
 {
-- 
2.20.1

The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
insns had some bugs:
 * the 32x32 multiply of elements was being done as 32x32->32,
   not 32x32->64
 * we were incorrectly maintaining the accumulator in its full
   72-bit form across all 4 beats of the insn; in the pseudocode
   it is squashed back into the 64 bits of the RdaHi:RdaLo
   registers after each beat

In particular, fixing the second of these allows us to recast
the implementation to avoid 128-bit arithmetic entirely.

Since the element size here is always 4, we can also drop the
parameterization of ESIZE to make the code a little more readable.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
---
 target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
 1 file changed, 21 insertions(+), 17 deletions(-)

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu/int128.h"
 #include "cpu.h"
 #include "internals.h"
 #include "vec_internal.h"
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
 
 /*
- * Rounding multiply add long dual accumulate high: we must keep
- * a 72-bit internal accumulator value and return the top 64 bits.
+ * Rounding multiply add long dual accumulate high. In the pseudocode
+ * this is implemented with a 72-bit internal accumulator value of which
+ * the top 64 bits are returned. We optimize this to avoid having to
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
+ * is squashed back into 64-bits after each beat.
  */
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128)         \
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB)                            \
     uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn,         \
                                     void *vm, uint64_t a)               \
     {                                                                   \
         uint16_t mask = mve_element_mask(env);                          \
         unsigned e;                                                     \
         TYPE *n = vn, *m = vm;                                          \
-        Int128 acc = int128_lshift(TO128(a), 8);                        \
-        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {              \
+        for (e = 0; e < 16 / 4; e++, mask >>= 4) {                      \
             if (mask & 1) {                                             \
+                LTYPE mul;                                              \
                 if (e & 1) {                                            \
-                    acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
-                                            m[H##ESIZE(e)]));           \
+                    mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)];        \
+                    if (SUB) {                                          \
+                        mul = -mul;                                     \
+                    }                                                   \
                 } else {                                                \
-                    acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
-                                             m[H##ESIZE(e)]));          \
+                    mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)];        \
                 }                                                       \
-                acc = int128_add(acc, int128_make64(1 << 7));           \
+                mul = (mul >> 8) + ((mul >> 7) & 1);                    \
+                a += mul;                                               \
             }                                                           \
         }                                                               \
         mve_advance_vpt(env);                                           \
-        return int128_getlo(int128_rshift(acc, 8));                     \
+        return a;                                                       \
     }
 
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
 
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
 
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
 
 /* Vector add across vector */
 #define DO_VADDV(OP, ESIZE, TYPE)                               \
-- 
2.20.1

The function asimd_imm_const() in translate-neon.c is an
implementation of the pseudocode AdvSIMDExpandImm(), which we will
also want for MVE.  Move the implementation to translate.c, with a
prototype in translate.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
---
 target/arm/translate.h      | 16 ++++++++++
 target/arm/translate-neon.c | 63 -------------------------------------
 target/arm/translate.c      | 57 +++++++++++++++++++++++++++++++++
 3 files changed, 73 insertions(+), 63 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
     return opc | s->be_data;
 }
 
+/**
+ * asimd_imm_const: Expand an encoded SIMD constant value
+ *
+ * Expand a SIMD constant value. This is essentially the pseudocode
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
+ * VMVN and VBIC (when cmode < 14 && op == 1).
+ *
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
+ * callers must catch this.
+ *
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
+ * we produce an immediate constant value of 0 in these cases.
+ */
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
+
 #endif /* TARGET_ARM_TRANSLATE_H */
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
 DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
 DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
 
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
-{
-    /*
-     * Expand the encoded constant.
-     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
-     * We choose to not special-case this and will behave as if a
-     * valid constant encoding of 0 had been given.
-     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
-     */
-    switch (cmode) {
-    case 0: case 1:
-        /* no-op */
-        break;
-    case 2: case 3:
-        imm <<= 8;
-        break;
-    case 4: case 5:
-        imm <<= 16;
-        break;
-    case 6: case 7:
-        imm <<= 24;
-        break;
-    case 8: case 9:
-        imm |= imm << 16;
-        break;
-    case 10: case 11:
-        imm = (imm << 8) | (imm << 24);
-        break;
-    case 12:
-        imm = (imm << 8) | 0xff;
-        break;
-    case 13:
-        imm = (imm << 16) | 0xffff;
-        break;
-    case 14:
-        if (op) {
-            /*
-             * This is the only case where the top and bottom 32 bits
-             * of the encoded constant differ.
-             */
-            uint64_t imm64 = 0;
-            int n;
-
-            for (n = 0; n < 8; n++) {
-                if (imm & (1 << n)) {
-                    imm64 |= (0xffULL << (n * 8));
-                }
-            }
-            return imm64;
-        }
-        imm |= (imm << 8) | (imm << 16) | (imm << 24);
-        break;
-    case 15:
-        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
-            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
-        break;
-    }
-    if (op) {
-        imm = ~imm;
-    }
-    return dup_const(MO_32, imm);
-}
-
 static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
                         GVecGen2iFn *fn)
 {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
     a64_translate_init();
 }
 
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
+{
+    /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
+    switch (cmode) {
+    case 0: case 1:
+        /* no-op */
+        break;
+    case 2: case 3:
+        imm <<= 8;
+        break;
+    case 4: case 5:
+        imm <<= 16;
+        break;
+    case 6: case 7:
+        imm <<= 24;
+        break;
+    case 8: case 9:
+        imm |= imm << 16;
+        break;
+    case 10: case 11:
+        imm = (imm << 8) | (imm << 24);
+        break;
+    case 12:
+        imm = (imm << 8) | 0xff;
+        break;
+    case 13:
+        imm = (imm << 16) | 0xffff;
+        break;
+    case 14:
+        if (op) {
+            /*
+             * This is the only case where the top and bottom 32 bits
+             * of the encoded constant differ.
+             */
+            uint64_t imm64 = 0;
+            int n;
+
+            for (n = 0; n < 8; n++) {
+                if (imm & (1 << n)) {
+                    imm64 |= (0xffULL << (n * 8));
+                }
+            }
+            return imm64;
+        }
+        imm |= (imm << 8) | (imm << 16) | (imm << 24);
+        break;
+    case 15:
+        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
+            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
+        break;
+    }
+    if (op) {
+        imm = ~imm;
+    }
+    return dup_const(MO_32, imm);
+}
+
 /* Generate a label used for skipping this instruction */
 void arm_gen_condlabel(DisasContext *s)
 {
-- 
2.20.1

The A64 AdvSIMD modified-immediate grouping uses almost the same
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
which we add the AArch64-specific case for cmode 15 op 1) instead of
reimplementing it all.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
---
 target/arm/translate.h     |  3 +-
 target/arm/translate-a64.c | 86 ++++----------------------------------
 target/arm/translate.c     | 17 +++++++-
 3 files changed, 24 insertions(+), 82 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
  * VMVN and VBIC (when cmode < 14 && op == 1).
  *
  * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
- * callers must catch this.
+ * callers must catch this; we return the 64-bit constant value defined
+ * for AArch64.
  *
  * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
  * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
 {
     int rd = extract32(insn, 0, 5);
     int cmode = extract32(insn, 12, 4);
-    int cmode_3_1 = extract32(cmode, 1, 3);
-    int cmode_0 = extract32(cmode, 0, 1);
     int o2 = extract32(insn, 11, 1);
     uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
     bool is_neg = extract32(insn, 29, 1);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
         return;
     }
 
-    /* See AdvSIMDExpandImm() in ARM ARM */
-    switch (cmode_3_1) {
-    case 0: /* Replicate(Zeros(24):imm8, 2) */
-    case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
-    case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
-    case 3: /* Replicate(imm8:Zeros(24), 2) */
-    {
-        int shift = cmode_3_1 * 8;
-        imm = bitfield_replicate(abcdefgh << shift, 32);
-        break;
-    }
-    case 4: /* Replicate(Zeros(8):imm8, 4) */
-    case 5: /* Replicate(imm8:Zeros(8), 4) */
-    {
-        int shift = (cmode_3_1 & 0x1) * 8;
-        imm = bitfield_replicate(abcdefgh << shift, 16);
-        break;
-    }
-    case 6:
-        if (cmode_0) {
-            /* Replicate(Zeros(8):imm8:Ones(16), 2) */
-            imm = (abcdefgh << 16) | 0xffff;
-        } else {
-            /* Replicate(Zeros(16):imm8:Ones(8), 2) */
-            imm = (abcdefgh << 8) | 0xff;
-        }
-        imm = bitfield_replicate(imm, 32);
-        break;
-    case 7:
-        if (!cmode_0 && !is_neg) {
-            imm = bitfield_replicate(abcdefgh, 8);
-        } else if (!cmode_0 && is_neg) {
-            int i;
-            imm = 0;
-            for (i = 0; i < 8; i++) {
-                if ((abcdefgh) & (1 << i)) {
-                    imm |= 0xffULL << (i * 8);
-                }
-            }
-        } else if (cmode_0) {
-            if (is_neg) {
-                imm = (abcdefgh & 0x3f) << 48;
-                if (abcdefgh & 0x80) {
-                    imm |= 0x8000000000000000ULL;
-                }
-                if (abcdefgh & 0x40) {
-                    imm |= 0x3fc0000000000000ULL;
-                } else {
-                    imm |= 0x4000000000000000ULL;
-                }
-            } else {
-                if (o2) {
-                    /* FMOV (vector, immediate) - half-precision */
-                    imm = vfp_expand_imm(MO_16, abcdefgh);
-                    /* now duplicate across the lanes */
-                    imm = bitfield_replicate(imm, 16);
-                } else {
-                    imm = (abcdefgh & 0x3f) << 19;
-                    if (abcdefgh & 0x80) {
-                        imm |= 0x80000000;
-                    }
-                    if (abcdefgh & 0x40) {
-                        imm |= 0x3e000000;
-                    } else {
-                        imm |= 0x40000000;
-                    }
-                    imm |= (imm << 32);
-                }
-            }
-        }
-        break;
-    default:
-        g_assert_not_reached();
-    }
-
-    if (cmode_3_1 != 7 && is_neg) {
-        imm = ~imm;
+    if (cmode == 15 && o2 && !is_neg) {
+        /* FMOV (vector, immediate) - half-precision */
+        imm = vfp_expand_imm(MO_16, abcdefgh);
+        /* now duplicate across the lanes */
+        imm = bitfield_replicate(imm, 16);
+    } else {
+        imm = asimd_imm_const(abcdefgh, cmode, is_neg);
     }
 
     if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
     case 14:
         if (op) {
             /*
-             * This is the only case where the top and bottom 32 bits
-             * of the encoded constant differ.
+             * This and cmode == 15 op == 1 are the only cases where
+             * the top and bottom 32 bits of the encoded constant differ.
              */
             uint64_t imm64 = 0;
             int n;
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
         imm |= (imm << 8) | (imm << 16) | (imm << 24);
         break;
     case 15:
+        if (op) {
+            /* Reserved encoding for AArch32; valid for AArch64 */
+            uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
+            if (imm & 0x80) {
+                imm64 |= 0x8000000000000000ULL;
+            }
+            if (imm & 0x40) {
+                imm64 |= 0x3fc0000000000000ULL;
+            } else {
+                imm64 |= 0x4000000000000000ULL;
+            }
+            return imm64;
+        }
         imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
             | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
         break;
-- 
2.20.1

Use dup_const() instead of bitfield_replicate() in
disas_simd_mod_imm().

(We can't replace the other use of bitfield_replicate() in this file,
in logic_imm_decode_wmask(), because that location needs to handle 2
and 4 bit elements, which dup_const() cannot.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
---
 target/arm/translate-a64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
         /* FMOV (vector, immediate) - half-precision */
         imm = vfp_expand_imm(MO_16, abcdefgh);
         /* now duplicate across the lanes */
-        imm = bitfield_replicate(imm, 16);
+        imm = dup_const(MO_16, imm);
     } else {
         imm = asimd_imm_const(abcdefgh, cmode, is_neg);
     }
-- 
2.20.1

Implement the MVE logical-immediate insns (VMOV, VMVN,
VORR and VBIC). These have essentially the same encoding
as their Neon equivalents, and we implement the decode
in the same way.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  4 +++
 target/arm/mve.decode      | 17 +++++++++++++
 target/arm/mve_helper.c    | 24 ++++++++++++++++++
 target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 95 insertions(+)

Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
and VQSHLU.

The size-and-immediate encoding here is the same as Neon, and we
handle it the same way neon-dp.decode does.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    | 16 +++++++++++
 target/arm/mve.decode      | 23 +++++++++++++++
 target/arm/mve_helper.c    | 57 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
 4 files changed, 147 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
 DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
 DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
 DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
+
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
 &2op qd qm qn size
 &2scalar qd qn rm size
 &1imm qd imm cmode op
+&2shift qd qm shift size
 
 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
 # Note that both Rn and Qd are 3 bits only (no D bit)
@@ -XXX,XX +XXX,XX @@
 @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
+@2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+@2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
+
 # Vector loads and stores
 
 # Widening loads and narrowing stores:
@@ -XXX,XX +XXX,XX @@ VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
 # So we have a single decode line and check the cmode/op in the
 # trans function.
 Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
+
+# Shifts by immediate
+
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
     WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
 #define DO_UQRSHL_OP(N, M, satp) \
     WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
+#define DO_SUQSHL_OP(N, M, satp) \
+    WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
 
 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
 DO_VADDV(vaddvub, 1, uint8_t)
 DO_VADDV(vaddvuh, 2, uint16_t)
 DO_VADDV(vaddvuw, 4, uint32_t)
+
+/* Shifts by immediate */
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        TYPE *d = vd, *m = vm;                                  \
+        uint16_t mask = mve_element_mask(env);                  \
+        unsigned e;                                             \
+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
+            mergemask(&d[H##ESIZE(e)],                          \
+                      FN(m[H##ESIZE(e)], shift), mask);         \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN)                      \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        TYPE *d = vd, *m = vm;                                  \
+        uint16_t mask = mve_element_mask(env);                  \
+        unsigned e;                                             \
+        bool qc = false;                                        \
+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
+            bool sat = false;                                   \
+            mergemask(&d[H##ESIZE(e)],                          \
+                      FN(m[H##ESIZE(e)], shift, &sat), mask);   \
+            qc |= sat & mask & 1;                               \
+        }                                                       \
+        if (qc) {                                               \
+            env->vfp.qc[0] = qc;                                \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+/* provide unsigned 2-op shift helpers for all sizes */
+#define DO_2SHIFT_U(OP, FN)                     \
+    DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
+    DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
+    DO_2SHIFT(OP##w, 4, uint32_t, FN)
+
+#define DO_2SHIFT_SAT_U(OP, FN)                 \
+    DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
+    DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN)       \
+    DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
+#define DO_2SHIFT_SAT_S(OP, FN)                 \
+    DO_2SHIFT_SAT(OP##b, 1, int8_t, FN)         \
+    DO_2SHIFT_SAT(OP##h, 2, int16_t, FN)        \
+    DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
+
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
 typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
     }
     return do_1imm(s, a, fn);
 }
+
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
+                      bool negateshift)
+{
+    TCGv_ptr qd, qm;
+    int shift = a->shift;
+
+    if (!dc_isar_feature(aa32_mve, s) ||
+        !mve_check_qreg_bank(s, a->qd | a->qm) ||
+        !fn) {
+        return false;
+    }
+    if (!mve_eci_check(s) || !vfp_access_check(s)) {
+        return true;
+    }
+
+    /*
+     * When we handle a right shift insn using a left-shift helper
+     * which permits a negative shift count to indicate a right-shift,
+     * we must negate the shift count.
+     */
+    if (negateshift) {
+        shift = -shift;
+    }
+
+    qd = mve_qreg_ptr(a->qd);
+    qm = mve_qreg_ptr(a->qm);
+    fn(cpu_env, qd, qm, tcg_constant_i32(shift));
+    tcg_temp_free_ptr(qd);
+    tcg_temp_free_ptr(qm);
+    mve_update_eci(s);
+    return true;
+}
+
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+    {                                                           \
+        static MVEGenTwoOpShiftFn * const fns[] = {             \
+            gen_helper_mve_##FN##b,                             \
+            gen_helper_mve_##FN##h,                             \
+            gen_helper_mve_##FN##w,                             \
+            NULL,                                               \
+        };                                                      \
+        return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
+    }
+
+DO_2SHIFT(VSHLI, vshli_u, false)
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
-- 
2.20.1

Implement the MVE vector shift right by immediate insns VSHRI and
VRSHRI.  As with Neon, we implement these by using helper functions
which perform left shifts but allow negative shift counts to indicate
right shifts.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
---
 target/arm/helper-mve.h     | 12 ++++++++++++
 target/arm/translate.h      | 20 ++++++++++++++++++++
 target/arm/mve.decode       | 28 ++++++++++++++++++++++++++++
 target/arm/mve_helper.c     |  7 +++++++
 target/arm/translate-mve.c  |  5 +++++
 target/arm/translate-neon.c | 18 ------------------
 6 files changed, 72 insertions(+), 18 deletions(-)

Implement the MVE VHLL (vector shift left long) insn.  This has two
encodings: the T1 encoding is the usual shift-by-immediate format,
and the T2 encoding is a special case where the shift count is always
equal to the element size.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  9 +++++++
 target/arm/mve.decode      | 53 +++++++++++++++++++++++++++++++++++---
 target/arm/mve_helper.c    | 32 +++++++++++++++++++++++
 target/arm/translate-mve.c | 15 +++++++++++
 4 files changed, 105 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
 @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
 @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
 
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
+@2_shll_h .... .... ... 1  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+# VSHLL encoding T2 where shift == esize
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
+                qd=%qd qm=%qm size=0 shift=8
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
+                qd=%qd qm=%qm size=1 shift=16
+
 # Right shifts are encoded as N - shift, where N is the element size in bits.
 %rshift_i5  16:5 !function=rsub_32
 %rshift_i4  16:4 !function=rsub_16
@@ -XXX,XX +XXX,XX @@ VADD             1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
 VSUB             1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
 VMUL             1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
 
-VMULH_S          111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
-VMULH_U          111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
+# overlaps what would be size=0b11 VMULH/VRMULH
+{
+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
 
-VRMULH_S         111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
-VRMULH_U         111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+  VMULH_S        111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VMULH_U        111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VRMULH_S       111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VRMULH_U       111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+}
 
 VMAX_S           111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
 VMAX_U           111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
@@ -XXX,XX +XXX,XX @@ VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
+
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
 DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
 DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
+
+/*
+ * Long shifts taking half-sized inputs from top or bottom of the input
+ * vector and producing a double-width result. ESIZE, TYPE are for
+ * the input, and LESIZE, LTYPE for the output.
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
+ * because the long shift is strictly left-only.
+ */
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE)                   \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
+                                void *vm, uint32_t shift)               \
+    {                                                                   \
+        LTYPE *d = vd;                                                  \
+        TYPE *m = vm;                                                   \
+        uint16_t mask = mve_element_mask(env);                          \
+        unsigned le;                                                    \
+        assert(shift <= 16);                                            \
+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) {         \
+            LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift;        \
+            mergemask(&d[H##LESIZE(le)], r, mask);                      \
+        }                                                               \
+        mve_advance_vpt(env);                                           \
+    }
+
+#define DO_VSHLL_ALL(OP, TOP)                                \
+    DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t)             \
+    DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t)           \
+    DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t)            \
+    DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t)          \
+
+DO_VSHLL_ALL(vshllb, false)
+DO_VSHLL_ALL(vshllt, true)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
 DO_2SHIFT(VSHRI_U, vshli_u, true)
 DO_2SHIFT(VRSHRI_S, vrshli_s, true)
 DO_2SHIFT(VRSHRI_U, vrshli_u, true)
+
+#define DO_VSHLL(INSN, FN)                                      \
+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+    {                                                           \
+        static MVEGenTwoOpShiftFn * const fns[] = {             \
+            gen_helper_mve_##FN##b,                             \
+            gen_helper_mve_##FN##h,                             \
+        };                                                      \
+        return do_2shift(s, a, fns[a->size], false);            \
+    }
+
+DO_VSHLL(VSHLL_BS, vshllbs)
+DO_VSHLL(VSHLL_BU, vshllbu)
+DO_VSHLL(VSHLL_TS, vshllts)
+DO_VSHLL(VSHLL_TU, vshlltu)
-- 
2.20.1

Implement the MVE VSRI and VSLI insns, which perform a
shift-and-insert operation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  8 ++++++++
 target/arm/mve.decode      |  9 ++++++++
 target/arm/mve_helper.c    | 42 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  3 +++
 4 files changed, 62 insertions(+)

Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.

do_urshr() is borrowed from sve_helper.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    | 10 ++++++++++
 target/arm/mve.decode      | 11 +++++++++++
 target/arm/mve_helper.c    | 40 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 15 ++++++++++++++
 4 files changed, 76 insertions(+)

Implement the MVE saturating shift-right-and-narrow insns
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.

do_srshr() is borrowed from sve_helper.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  30 +++++++++++
 target/arm/mve.decode      |  28 ++++++++++
 target/arm/mve_helper.c    | 104 +++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  12 +++++
 4 files changed, 174 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
 VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
 VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
 VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
+
+VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
+
+VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
+
+VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
+
+VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
     }
 }
 
+static inline int64_t do_srshr(int64_t x, unsigned sh)
+{
+    if (likely(sh < 64)) {
+        return (x >> sh) + ((x >> (sh - 1)) & 1);
+    } else {
+        /* Rounding the sign bit always produces 0. */
+        return 0;
+    }
+}
+
 DO_VSHRN_ALL(vshrn, DO_SHR)
 DO_VSHRN_ALL(vrshrn, do_urshr)
+
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
+                                 bool *satp)
+{
+    if (val > max) {
+        *satp = true;
+        return max;
+    } else if (val < min) {
+        *satp = true;
+        return min;
+    } else {
+        return val;
+    }
+}
+
+/* Saturating narrowing right shifts */
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)   \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        LTYPE *m = vm;                                          \
+        TYPE *d = vd;                                           \
+        uint16_t mask = mve_element_mask(env);                  \
+        bool qc = false;                                        \
+        unsigned le;                                            \
+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
+            bool sat = false;                                   \
+            TYPE r = FN(m[H##LESIZE(le)], shift, &sat);         \
+            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
+            qc |= sat && (mask & 1 << (TOP * ESIZE));           \
+        }                                                       \
+        if (qc) {                                               \
+            env->vfp.qc[0] = qc;                                \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN)       \
+    DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
+
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN)      \
+    DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
+
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN)         \
+    DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
+
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN)        \
+    DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
+
+#define DO_SHRN_SB(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
+#define DO_SHRN_UB(N, M, SATP)                                  \
+    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
+#define DO_SHRUN_B(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
+
+#define DO_SHRN_SH(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
+#define DO_SHRN_UH(N, M, SATP)                                  \
+    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
+#define DO_SHRUN_H(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
+
+#define DO_RSHRN_SB(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
+#define DO_RSHRN_UB(N, M, SATP)                                 \
+    do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
+#define DO_RSHRUN_B(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
+
+#define DO_RSHRN_SH(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
+#define DO_RSHRN_UH(N, M, SATP)                                 \
+    do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
+#define DO_RSHRUN_H(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
+
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
+
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
 DO_2SHIFT_N(VSHRNT, vshrnt)
 DO_2SHIFT_N(VRSHRNB, vrshrnb)
 DO_2SHIFT_N(VRSHRNT, vrshrnt)
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
-- 
2.20.1

Implement the MVE VSHLC insn, which performs a shift left of the
entire vector with carry in bits provided from a general purpose
register and carry out bits written back to that register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  2 ++
 target/arm/mve.decode      |  2 ++
 target/arm/mve_helper.c    | 38 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
 4 files changed, 72 insertions(+)

Implement the MVE VADDLV insn; this is similar to VADDV, except
that it accumulates 32-bit elements into a 64-bit accumulator
stored in a pair of general-purpose registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  3 ++
 target/arm/mve.decode      |  6 +++-
 target/arm/mve_helper.c    | 19 ++++++++++++
 target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 90 insertions(+), 1 deletion(-)

The MVE extension to v8.1M includes some new shift instructions which
sit entirely within the non-coprocessor part of the encoding space
and which operate only on general-purpose registers.  They take up
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
with Rm == 13 or 15.

Implement the long shifts by immediate, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
an immediate shift count between 1 and 32.

Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
cases where v8.1M now requires that.  (Trying to change MOVS and ORRS
is too difficult, because the functions that generate the code are
shared between a dozen different kinds of arithmetic or logical
instruction for all A32, T16 and T32 encodings, and for some insns
and some encodings Rm==13,15 are valid.)

We make the helper functions we need for UQSHLL and SQSHLL take
a 32-bit value which the helper casts to int8_t because we'll need
these helpers also for the shift-by-register insns, where the shift
count might be < 0 or > 32.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  3 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 28 +++++++++++++
 target/arm/mve_helper.c | 10 +++++
 target/arm/translate.c  | 90 +++++++++++++++++++++++++++++++++++++++++
 5 files changed, 132 insertions(+)

Implement the MVE long shifts by register, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
the shift count in another general-purpose register, which might be
either positive or negative.

Like the long-shifts-by-immediate, these encodings sit in the space
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
we have to move the CSEL pattern into the same decodetree group.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  6 +++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 16 +++++--
 target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
 target/arm/translate.c  | 69 ++++++++++++++++++++++++++++++
 5 files changed, 182 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
 
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
 typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
 
 /**
  * arm_tbflags_from_tb:
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@
 &mcrr            !extern cp opc1 crm rt rt2
 
 &mve_shl_ri      rdalo rdahi shim
+&mve_shl_rr      rdalo rdahi rm
 
 # rdahi: bits [3:1] from insn, bit 0 is 1
 # rdalo: bits [3:1] from insn, bit 0 is 0
@@ -XXX,XX +XXX,XX @@
 
 @mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
                  &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
+@mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
+                 &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
 
 {
   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
     URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
     SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
     SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
+
+    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
+    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
+    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
+    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
+    UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
+    SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
   ]
 
   MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
   ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
+
+  # v8.1M CSEL and friends
+  CSEL           1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
 }
 {
   MVN_rxri       1110101 0011 . 1111 0 ... .... .... ....     @s_rxr_shi
@@ -XXX,XX +XXX,XX @@ SBC_rrri         1110101 1011 . .... 0 ... .... .... ....     @s_rrr_shi
 }
 RSB_rrri         1110101 1110 . .... 0 ... .... .... ....     @s_rrr_shi
 
-# v8.1M CSEL and friends
-CSEL             1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
-
 # Data-processing (register-shifted register)
 
 MOV_rxrr         1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
     return rdm;
 }
 
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
+}
+
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl_d(n, (int8_t)shift, false, NULL);
+}
+
 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 {
     return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 {
     return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
 }
+
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
+}
+
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
+}
+
+/* Operate on 64-bit values, but saturate at 48 bits */
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
+                                    bool round, uint32_t *sat)
+{
+    if (shift <= -48) {
+        /* Rounding the sign bit always produces 0. */
+        if (round) {
+            return 0;
+        }
+        return src >> 63;
+    } else if (shift < 0) {
+        if (round) {
+            src >>= -shift - 1;
+            return (src >> 1) + (src & 1);
+        }
+        return src >> -shift;
+    } else if (shift < 48) {
+        int64_t val = src << shift;
+        int64_t extval = sextract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (!sat || src == 0) {
+        return 0;
+    }
+
+    *sat = 1;
+    return (1ULL << 47) - (src >= 0);
+}
+
+/* Operate on 64-bit values, but saturate at 48 bits */
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
+                                     bool round, uint32_t *sat)
+{
+    uint64_t val, extval;
+
+    if (shift <= -(48 + round)) {
+        return 0;
+    } else if (shift < 0) {
+        if (round) {
+            val = src >> (-shift - 1);
+            val = (val >> 1) + (val & 1);
+        } else {
+            val = src >> -shift;
+        }
+        extval = extract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (shift < 48) {
+        uint64_t val = src << shift;
+        uint64_t extval = extract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (!sat || src == 0) {
+        return 0;
+    }
+
+    *sat = 1;
+    return MAKE_64BIT_MASK(0, 48);
+}
+
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
+}
+
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
     return do_mve_shl_ri(s, a, gen_urshr64_i64);
 }
 
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
+{
+    TCGv_i64 rda;
+    TCGv_i32 rdalo, rdahi;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
+        return false;
+    }
+    if (a->rdahi == 15) {
+        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
+        return false;
+    }
+    if (!dc_isar_feature(aa32_mve, s) ||
+        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
+        a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
+        a->rm == a->rdahi || a->rm == a->rdalo) {
+        /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
+        unallocated_encoding(s);
+        return true;
+    }
+
+    rda = tcg_temp_new_i64();
+    rdalo = load_reg(s, a->rdalo);
+    rdahi = load_reg(s, a->rdahi);
+    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
+
+    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
+    fn(rda, cpu_env, rda, cpu_R[a->rm]);
+
+    tcg_gen_extrl_i64_i32(rdalo, rda);
+    tcg_gen_extrh_i64_i32(rdahi, rda);
+    store_reg(s, a->rdalo, rdalo);
+    store_reg(s, a->rdahi, rdahi);
+    tcg_temp_free_i64(rda);
+
+    return true;
+}
+
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
+}
+
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
+}
+
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
+}
+
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
+}
+
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
+}
+
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
+}
+
 /*
  * Multiply and multiply accumulate
  */
-- 
2.20.1

Implement the MVE shifts by immediate, which perform shifts
on a single general-purpose register.

These patterns overlap with the long-shift-by-immediates,
so we have to rearrange the grouping a little here.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  3 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 31 ++++++++++++++-----
 target/arm/mve_helper.c | 10 ++++++
 target/arm/translate.c  | 68 +++++++++++++++++++++++++++++++++++++++--
 5 files changed, 104 insertions(+), 9 deletions(-)

Implement the MVE shifts by register, which perform
shifts on a single general-purpose register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  2 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 18 ++++++++++++++----
 target/arm/mve_helper.c | 10 ++++++++++
 target/arm/translate.c  | 30 ++++++++++++++++++++++++++++++
 5 files changed, 57 insertions(+), 4 deletions(-)

Just a collection of bug fixes this time around...

thanks
-- PMM

The following changes since commit 2a6ae69154542caa91dd17c40fd3f5ffbec300de:

Merge tag 'pull-maintainer-ominbus-030723-1' of https://gitlab.com/stsquad/qemu into staging (2023-07-04 08:36:44 +0200)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230704

for you to fetch changes up to 86a78272f094857b4eda79d721c116e93942aa9a:

target/xtensa: Assert that interrupt level is within bounds (2023-07-04 14:27:08 +0100)

----------------------------------------------------------------
target-arm queue:
 * Add raw_writes ops for register whose write induce TLB maintenance
 * hw/arm/sbsa-ref: use XHCI to replace EHCI
 * Avoid splitting Zregs across lines in dump
 * Dump ZA[] when active
 * Fix SME full tile indexing
 * Handle IC IVAU to improve compatibility with JITs
 * xlnx-canfd-test: Fix code coverity issues
 * gdbstub: Guard M-profile code with CONFIG_TCG
 * allwinner-sramc: Set class_size
 * target/xtensa: Assert that interrupt level is within bounds

----------------------------------------------------------------
Akihiko Odaki (1):
      hw: arm: allwinner-sramc: Set class_size

Eric Auger (1):
      target/arm: Add raw_writes ops for register whose write induce TLB maintenance

Fabiano Rosas (1):
      target/arm: gdbstub: Guard M-profile code with CONFIG_TCG

John Högberg (2):
      target/arm: Handle IC IVAU to improve compatibility with JITs
      tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code

Peter Maydell (1):
      target/xtensa: Assert that interrupt level is within bounds

Richard Henderson (3):
      target/arm: Avoid splitting Zregs across lines in dump
      target/arm: Dump ZA[] when active
      target/arm: Fix SME full tile indexing

Vikram Garhwal (1):
      tests/qtest: xlnx-canfd-test: Fix code coverity issues

Yuquan Wang (1):
      hw/arm/sbsa-ref: use XHCI to replace EHCI

docs/system/arm/sbsa.rst          |   5 +-
 hw/arm/sbsa-ref.c                 |  23 +++--
 hw/misc/allwinner-sramc.c         |   1 +
 target/arm/cpu.c                  |  65 ++++++++-----
 target/arm/gdbstub.c              |   4 +
 target/arm/helper.c               |  70 +++++++++++---
 target/arm/tcg/translate-sme.c    |  24 +++--
 target/xtensa/exc_helper.c        |   3 +
 tests/qtest/xlnx-canfd-test.c     |  33 +++----
 tests/tcg/aarch64/icivau.c        | 189 ++++++++++++++++++++++++++++++++++++++
 tests/tcg/aarch64/sme-outprod1.c  |  83 +++++++++++++++++
 hw/arm/Kconfig                    |   2 +-
 tests/tcg/aarch64/Makefile.target |  13 ++-
 13 files changed, 436 insertions(+), 79 deletions(-)
 create mode 100644 tests/tcg/aarch64/icivau.c
 create mode 100644 tests/tcg/aarch64/sme-outprod1.c

From: Eric Auger <eric.auger@redhat.com>

Some registers whose 'cooked' writefns induce TLB maintenance do
not have raw_writefn ops defined. If only the writefn ops is set
(ie. no raw_writefn is provided), it is assumed the cooked also
work as the raw one. For those registers it is not obvious the
tlb_flush works on KVM mode so better/safer setting the raw write.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
       .fgt = FGT_TTBR0_EL1,
-      .writefn = vmsa_ttbr_write, .resetvalue = 0,
+      .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write,
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
       .fgt = FGT_TTBR1_EL1,
-      .writefn = vmsa_ttbr_write, .resetvalue = 0,
+      .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write,
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
                              offsetof(CPUARMState, cp15.ttbr0_ns) },
-      .writefn = vmsa_ttbr_write, },
+      .writefn = vmsa_ttbr_write, .raw_writefn = raw_write },
     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
                              offsetof(CPUARMState, cp15.ttbr1_ns) },
-      .writefn = vmsa_ttbr_write, },
+      .writefn = vmsa_ttbr_write, .raw_writefn = raw_write },
 };
 
 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .type = ARM_CP_IO,
       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
-      .writefn = hcr_write },
+      .writefn = hcr_write, .raw_writefn = raw_write },
     { .name = "HCR", .state = ARM_CP_STATE_AA32,
       .type = ARM_CP_ALIAS | ARM_CP_IO,
       .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
       .access = PL2_RW, .writefn = vmsa_tcr_el12_write,
+      .raw_writefn = raw_write,
       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
     { .name = "VTCR", .state = ARM_CP_STATE_AA32,
       .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
       .access = PL2_RW, .accessfn = access_el3_aa32ns,
       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
-      .writefn = vttbr_write },
+      .writefn = vttbr_write, .raw_writefn = raw_write },
     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
-      .access = PL2_RW, .writefn = vttbr_write,
+      .access = PL2_RW, .writefn = vttbr_write, .raw_writefn = raw_write,
       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
-      .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write,
+      .access = PL2_RW, .resetvalue = 0,
+      .writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write,
       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
-      .resetfn = scr_reset, .writefn = scr_write },
+      .resetfn = scr_reset, .writefn = scr_write, .raw_writefn = raw_write },
     { .name = "SCR",  .type = ARM_CP_ALIAS | ARM_CP_NEWEL,
       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
-      .writefn = scr_write },
+      .writefn = scr_write, .raw_writefn = raw_write },
     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
       .access = PL3_RW, .resetvalue = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
     { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
       .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
+      .raw_writefn = raw_write,
       .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) },
 #ifndef CONFIG_USER_ONLY
     { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64,
-- 
2.34.1

From: Yuquan Wang <wangyuquan1236@phytium.com.cn>

The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses XHCI to provide a usb controller with 64-bit
DMA capablity instead of EHCI.

We bump the platform version to 0.3 with this change.  Although the
hardware at the USB controller address changes, the firmware and
Linux can both cope with this -- on an older non-XHCI-aware
firmware/kernel setup the probe routine simply fails and the guest
proceeds without any USB.  (This isn't a loss of functionality,
because the old USB controller never worked in the first place.) So
we can call this a backwards-compatible change and only bump the
minor version.

Signed-off-by: Yuquan Wang <wangyuquan1236@phytium.com.cn>
Message-id: 20230621103847.447508-2-wangyuquan1236@phytium.com.cn
[PMM: tweaked commit message; add line to docs about what
 changes in platform version 0.3]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/sbsa.rst |  5 ++++-
 hw/arm/sbsa-ref.c        | 23 +++++++++++++----------
 hw/arm/Kconfig           |  2 +-
 3 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/sbsa.rst
+++ b/docs/system/arm/sbsa.rst
@@ -XXX,XX +XXX,XX @@ The ``sbsa-ref`` board supports:
   - A configurable number of AArch64 CPUs
   - GIC version 3
   - System bus AHCI controller
-  - System bus EHCI controller
+  - System bus XHCI controller
   - CDROM and hard disc on AHCI bus
   - E1000E ethernet card on PCIe bus
   - Bochs display adapter on PCIe bus
@@ -XXX,XX +XXX,XX @@ Platform version changes:
 
 0.2
   GIC ITS information is present in devicetree.
+
+0.3
+  The USB controller is an XHCI device, not EHCI
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/pci-host/gpex.h"
 #include "hw/qdev-properties.h"
 #include "hw/usb.h"
+#include "hw/usb/xhci.h"
 #include "hw/char/pl011.h"
 #include "hw/watchdog/sbsa_gwdt.h"
 #include "net/net.h"
@@ -XXX,XX +XXX,XX @@ enum {
     SBSA_SECURE_UART_MM,
     SBSA_SECURE_MEM,
     SBSA_AHCI,
-    SBSA_EHCI,
+    SBSA_XHCI,
 };
 
 struct SBSAMachineState {
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sbsa_ref_memmap[] = {
     [SBSA_SMMU] =               { 0x60050000, 0x00020000 },
     /* Space here reserved for more SMMUs */
     [SBSA_AHCI] =               { 0x60100000, 0x00010000 },
-    [SBSA_EHCI] =               { 0x60110000, 0x00010000 },
+    [SBSA_XHCI] =               { 0x60110000, 0x00010000 },
     /* Space here reserved for other devices */
     [SBSA_PCIE_PIO] =           { 0x7fff0000, 0x00010000 },
     /* 32-bit address PCIE MMIO space */
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
     [SBSA_SECURE_UART] = 8,
     [SBSA_SECURE_UART_MM] = 9,
     [SBSA_AHCI] = 10,
-    [SBSA_EHCI] = 11,
+    [SBSA_XHCI] = 11,
     [SBSA_SMMU] = 12, /* ... to 15 */
     [SBSA_GWDT_WS0] = 16,
 };
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
      *                        fw compatibility.
      */
     qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
-    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 2);
+    qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3);
 
     if (ms->numa_state->have_numa_distance) {
         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ static void create_ahci(const SBSAMachineState *sms)
     }
 }
 
-static void create_ehci(const SBSAMachineState *sms)
+static void create_xhci(const SBSAMachineState *sms)
 {
-    hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
-    int irq = sbsa_ref_irqmap[SBSA_EHCI];
+    hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base;
+    int irq = sbsa_ref_irqmap[SBSA_XHCI];
+    DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
 
-    sysbus_create_simple("platform-ehci-usb", base,
-                         qdev_get_gpio_in(sms->gic, irq));
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
+    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
 }
 
 static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
 
     create_ahci(sms);
 
-    create_ehci(sms);
+    create_xhci(sms);
 
     create_pcie(sms);
 
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config SBSA_REF
     select PL011 # UART
     select PL031 # RTC
     select PL061 # GPIO
-    select USB_EHCI_SYSBUS
+    select USB_XHCI_SYSBUS
     select WDT_SBSA
     select BOCHS_DISPLAY
 
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Allow the line length to extend to 548 columns.  While annoyingly wide,
it's still less confusing than the continuations we print.  Also, the
default VL used by Linux (and max for A64FX) uses only 140 columns.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230622151201.1578522-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 36 ++++++++++++++----------------------
 1 file changed, 14 insertions(+), 22 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
     uint32_t psr = pstate_read(env);
-    int i;
+    int i, j;
     int el = arm_current_el(env);
     const char *ns_status;
     bool sve;
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
     }
 
     if (sve) {
-        int j, zcr_len = sve_vqm1_for_el(env, el);
+        int zcr_len = sve_vqm1_for_el(env, el);
 
         for (i = 0; i <= FFR_PRED_NUM; i++) {
             bool eol;
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
             }
         }
 
-        for (i = 0; i < 32; i++) {
-            if (zcr_len == 0) {
+        if (zcr_len == 0) {
+            /*
+             * With vl=16, there are only 37 columns per register,
+             * so output two registers per line.
+             */
+            for (i = 0; i < 32; i++) {
                 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
                              i, env->vfp.zregs[i].d[1],
                              env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
-            } else if (zcr_len == 1) {
-                qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
-                             ":%016" PRIx64 ":%016" PRIx64 "\n",
-                             i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
-                             env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
-            } else {
+            }
+        } else {
+            for (i = 0; i < 32; i++) {
+                qemu_fprintf(f, "Z%02d=", i);
                 for (j = zcr_len; j >= 0; j--) {
-                    bool odd = (zcr_len - j) % 2 != 0;
-                    if (j == zcr_len) {
-                        qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
-                    } else if (!odd) {
-                        if (j > 0) {
-                            qemu_fprintf(f, "   [%x-%x]=", j, j - 1);
-                        } else {
-                            qemu_fprintf(f, "     [%x]=", j);
-                        }
-                    }
                     qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
                                  env->vfp.zregs[i].d[j * 2 + 1],
-                                 env->vfp.zregs[i].d[j * 2],
-                                 odd || j == 0 ? "\n" : ":");
+                                 env->vfp.zregs[i].d[j * 2 + 0],
+                                 j ? ":" : "\n");
                 }
             }
         }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Always print each matrix row whole, one per line, so that we
get the entire matrix in the proper shape.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230622151201.1578522-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
                          i, q[1], q[0], (i & 1 ? "\n" : " "));
         }
     }
+
+    if (cpu_isar_feature(aa64_sme, cpu) &&
+        FIELD_EX64(env->svcr, SVCR, ZA) &&
+        sme_exception_el(env, el) == 0) {
+        int zcr_len = sve_vqm1_for_el_sm(env, el, true);
+        int svl = (zcr_len + 1) * 16;
+        int svl_lg10 = svl < 100 ? 2 : 3;
+
+        for (i = 0; i < svl; i++) {
+            qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i);
+            for (j = zcr_len; j >= 0; --j) {
+                qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c",
+                             env->zarray[i].d[2 * j + 1],
+                             env->zarray[i].d[2 * j],
+                             j ? ':' : '\n');
+            }
+        }
+    }
 }
 
 #else
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

For the outer product set of insns, which take an entire matrix
tile as output, the argument is not a combined tile+column.
Therefore using get_tile_rowcol was incorrect, as we extracted
the tile number from itself.

The test case relies only on assembler support for SME, since
no release of GCC recognizes -march=armv9-a+sme yet.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1620
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230622151201.1578522-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/translate-sme.c    | 24 ++++++---
 tests/tcg/aarch64/sme-outprod1.c  | 83 +++++++++++++++++++++++++++++++
 tests/tcg/aarch64/Makefile.target | 10 ++--
 3 files changed, 108 insertions(+), 9 deletions(-)
 create mode 100644 tests/tcg/aarch64/sme-outprod1.c

diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate-sme.c
+++ b/target/arm/tcg/translate-sme.c
@@ -XXX,XX +XXX,XX @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs,
     return addr;
 }
 
+/*
+ * Resolve tile.size[0] to a host pointer.
+ * Used by e.g. outer product insns where we require the entire tile.
+ */
+static TCGv_ptr get_tile(DisasContext *s, int esz, int tile)
+{
+    TCGv_ptr addr = tcg_temp_new_ptr();
+    int offset;
+
+    offset = tile * sizeof(ARMVectorReg) + offsetof(CPUARMState, zarray);
+
+    tcg_gen_addi_ptr(addr, cpu_env, offset);
+    return addr;
+}
+
 static bool trans_ZERO(DisasContext *s, arg_ZERO *a)
 {
     if (!dc_isar_feature(aa64_sme, s)) {
@@ -XXX,XX +XXX,XX @@ static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz,
         return true;
     }
 
-    /* Sum XZR+zad to find ZAd. */
-    za = get_tile_rowcol(s, esz, 31, a->zad, false);
+    za = get_tile(s, esz, a->zad);
     zn = vec_full_reg_ptr(s, a->zn);
     pn = pred_full_reg_ptr(s, a->pn);
     pm = pred_full_reg_ptr(s, a->pm);
@@ -XXX,XX +XXX,XX @@ static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz,
         return true;
     }
 
-    /* Sum XZR+zad to find ZAd. */
-    za = get_tile_rowcol(s, esz, 31, a->zad, false);
+    za = get_tile(s, esz, a->zad);
     zn = vec_full_reg_ptr(s, a->zn);
     zm = vec_full_reg_ptr(s, a->zm);
     pn = pred_full_reg_ptr(s, a->pn);
@@ -XXX,XX +XXX,XX @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
         return true;
     }
 
-    /* Sum XZR+zad to find ZAd. */
-    za = get_tile_rowcol(s, esz, 31, a->zad, false);
+    za = get_tile(s, esz, a->zad);
     zn = vec_full_reg_ptr(s, a->zn);
     zm = vec_full_reg_ptr(s, a->zm);
     pn = pred_full_reg_ptr(s, a->pn);
diff --git a/tests/tcg/aarch64/sme-outprod1.c b/tests/tcg/aarch64/sme-outprod1.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/tcg/aarch64/sme-outprod1.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * SME outer product, 1 x 1.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <stdio.h>
+
+extern void foo(float *dst);
+
+asm(
+"	.arch_extension sme\n"
+"	.type foo, @function\n"
+"foo:\n"
+"	stp x29, x30, [sp, -80]!\n"
+"	mov x29, sp\n"
+"	stp d8, d9, [sp, 16]\n"
+"	stp d10, d11, [sp, 32]\n"
+"	stp d12, d13, [sp, 48]\n"
+"	stp d14, d15, [sp, 64]\n"
+"	smstart\n"
+"	ptrue p0.s, vl4\n"
+"	fmov z0.s, #1.0\n"
+/*
+ * An outer product of a vector of 1.0 by itself should be a matrix of 1.0.
+ * Note that we are using tile 1 here (za1.s) rather than tile 0.
+ */
+"	zero {za}\n"
+"	fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n"
+/*
+ * Read the first 4x4 sub-matrix of elements from tile 1:
+ * Note that za1h should be interchangable here.
+ */
+"	mov w12, #0\n"
+"	mova z0.s, p0/m, za1v.s[w12, #0]\n"
+"	mova z1.s, p0/m, za1v.s[w12, #1]\n"
+"	mova z2.s, p0/m, za1v.s[w12, #2]\n"
+"	mova z3.s, p0/m, za1v.s[w12, #3]\n"
+/*
+ * And store them to the input pointer (dst in the C code):
+ */
+"	st1w {z0.s}, p0, [x0]\n"
+"	add x0, x0, #16\n"
+"	st1w {z1.s}, p0, [x0]\n"
+"	add x0, x0, #16\n"
+"	st1w {z2.s}, p0, [x0]\n"
+"	add x0, x0, #16\n"
+"	st1w {z3.s}, p0, [x0]\n"
+"	smstop\n"
+"	ldp d8, d9, [sp, 16]\n"
+"	ldp d10, d11, [sp, 32]\n"
+"	ldp d12, d13, [sp, 48]\n"
+"	ldp d14, d15, [sp, 64]\n"
+"	ldp x29, x30, [sp], 80\n"
+"	ret\n"
+"	.size foo, . - foo"
+);
+
+int main()
+{
+    float dst[16];
+    int i, j;
+
+    foo(dst);
+
+    for (i = 0; i < 16; i++) {
+        if (dst[i] != 1.0f) {
+            break;
+        }
+    }
+
+    if (i == 16) {
+        return 0; /* success */
+    }
+
+    /* failure */
+    for (i = 0; i < 4; ++i) {
+        for (j = 0; j < 4; ++j) {
+            printf("%f ", (double)dst[i * 4 + j]);
+        }
+        printf("\n");
+    }
+    return 1;
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -XXX,XX +XXX,XX @@ config-cc.mak: Makefile
 	    $(call cc-option,-march=armv8.5-a,              CROSS_CC_HAS_ARMV8_5); \
 	    $(call cc-option,-mbranch-protection=standard,  CROSS_CC_HAS_ARMV8_BTI); \
 	    $(call cc-option,-march=armv8.5-a+memtag,       CROSS_CC_HAS_ARMV8_MTE); \
-	    $(call cc-option,-march=armv9-a+sme,            CROSS_CC_HAS_ARMV9_SME)) 3> config-cc.mak
+	    $(call cc-option,-Wa$(COMMA)-march=armv9-a+sme, CROSS_AS_HAS_ARMV9_SME)) 3> config-cc.mak
 -include config-cc.mak
 
 ifneq ($(CROSS_CC_HAS_ARMV8_2),)
@@ -XXX,XX +XXX,XX @@ AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7
 mte-%: CFLAGS += -march=armv8.5-a+memtag
 endif
 
+ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
+AARCH64_TESTS += sme-outprod1
+endif
+
 ifneq ($(CROSS_CC_HAS_SVE),)
 # System Registers Tests
 AARCH64_TESTS += sysregs
-ifneq ($(CROSS_CC_HAS_ARMV9_SME),)
-sysregs: CFLAGS+=-march=armv9-a+sme -DHAS_ARMV9_SME
+ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
+sysregs: CFLAGS+=-Wa,-march=armv9-a+sme -DHAS_ARMV9_SME
 else
 sysregs: CFLAGS+=-march=armv8.1-a+sve
 endif
-- 
2.34.1

From: John Högberg <john.hogberg@ericsson.com>

Unlike architectures with precise self-modifying code semantics
(e.g. x86) ARM processors do not maintain coherency for instruction
execution and memory, requiring an instruction synchronization
barrier on every core that will execute the new code, and on many
models also the explicit use of cache management instructions.

While this is required to make JITs work on actual hardware, QEMU
has gotten away with not handling this since it does not emulate
caches, and unconditionally invalidates code whenever the softmmu
or the user-mode page protection logic detects that code has been
modified.

Unfortunately the latter does not work in the face of dual-mapped
code (a common W^X workaround), where one page is executable and
the other is writable: user-mode has no way to connect one with the
other as that is only known to the kernel and the emulated
application.

This commit works around the issue by telling software that
instruction cache invalidation is required by clearing the
CPR_EL0.DIC flag (regardless of whether the emulated processor
needs it), and then invalidating code in IC IVAU instructions.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1034

Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: John Högberg <john.hogberg@ericsson.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 168778890374.24232.3402138851538068785-1@git.sr.ht
[PMM: removed unnecessary AArch64 feature check; moved
 "clear CTR_EL1.DIC" code up a bit so it's not in the middle
 of the vfp/neon related tests]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c    | 11 +++++++++++
 target/arm/helper.c | 47 ++++++++++++++++++++++++++++++++++++++++++---
 2 files changed, 55 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         return;
     }
 
+#ifdef CONFIG_USER_ONLY
+    /*
+     * User mode relies on IC IVAU instructions to catch modification of
+     * dual-mapped code.
+     *
+     * Clear CTR_EL0.DIC to ensure that software that honors these flags uses
+     * IC IVAU even if the emulated processor does not normally require it.
+     */
+    cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0);
+#endif
+
     if (arm_feature(env, ARM_FEATURE_AARCH64) &&
         cpu->has_vfp != cpu->has_neon) {
         /*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
     }
 }
 
+#ifdef CONFIG_USER_ONLY
+/*
+ * `IC IVAU` is handled to improve compatibility with JITs that dual-map their
+ * code to get around W^X restrictions, where one region is writable and the
+ * other is executable.
+ *
+ * Since the executable region is never written to we cannot detect code
+ * changes when running in user mode, and rely on the emulated JIT telling us
+ * that the code has changed by executing this instruction.
+ */
+static void ic_ivau_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                          uint64_t value)
+{
+    uint64_t icache_line_mask, start_address, end_address;
+    const ARMCPU *cpu;
+
+    cpu = env_archcpu(env);
+
+    icache_line_mask = (4 << extract32(cpu->ctr, 0, 4)) - 1;
+    start_address = value & ~icache_line_mask;
+    end_address = value | icache_line_mask;
+
+    mmap_lock();
+
+    tb_invalidate_phys_range(start_address, end_address);
+
+    mmap_unlock();
+}
+#endif
+
 static const ARMCPRegInfo v8_cp_reginfo[] = {
     /*
      * Minimal set of EL0-visible registers. This will need to be expanded
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
       .access = PL1_R, .type = ARM_CP_CURRENTEL },
-    /* Cache ops: all NOPs since we don't emulate caches */
+    /*
+     * Instruction cache ops. All of these except `IC IVAU` NOP because we
+     * don't emulate caches.
+     */
     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NOP,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .accessfn = access_tocu },
     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
-      .access = PL0_W, .type = ARM_CP_NOP,
+      .access = PL0_W,
       .fgt = FGT_ICIVAU,
-      .accessfn = access_tocu },
+      .accessfn = access_tocu,
+#ifdef CONFIG_USER_ONLY
+      .type = ARM_CP_NO_RAW,
+      .writefn = ic_ivau_write
+#else
+      .type = ARM_CP_NOP
+#endif
+    },
+    /* Cache ops: all NOPs since we don't emulate caches */
     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
       .access = PL1_W, .accessfn = aa64_cacheop_poc_access,
-- 
2.34.1

From: John Högberg <john.hogberg@ericsson.com>

https://gitlab.com/qemu-project/qemu/-/issues/1034

Signed-off-by: John Högberg <john.hogberg@ericsson.com>
Message-id: 168778890374.24232.3402138851538068785-2@git.sr.ht
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: fixed typo in comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/tcg/aarch64/icivau.c        | 189 ++++++++++++++++++++++++++++++
 tests/tcg/aarch64/Makefile.target |   3 +-
 2 files changed, 191 insertions(+), 1 deletion(-)
 create mode 100644 tests/tcg/aarch64/icivau.c

diff --git a/tests/tcg/aarch64/icivau.c b/tests/tcg/aarch64/icivau.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/tcg/aarch64/icivau.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Tests the IC IVAU-driven workaround for catching changes made to dual-mapped
+ * code that would otherwise go unnoticed in user mode.
+ *
+ * Copyright (c) 2023 Ericsson AB
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <fcntl.h>
+
+#define MAX_CODE_SIZE 128
+
+typedef int (SelfModTest)(uint32_t, uint32_t*);
+typedef int (BasicTest)(int);
+
+static void mark_code_modified(const uint32_t *exec_data, size_t length)
+{
+    int dc_required, ic_required;
+    unsigned long ctr_el0;
+
+    /*
+     * Clear the data/instruction cache, as indicated by the CTR_ELO.{DIC,IDC}
+     * flags.
+     *
+     * For completeness we might be tempted to assert that we should fail when
+     * the whole code update sequence is omitted, but that would make the test
+     * flaky as it can succeed by coincidence on actual hardware.
+     */
+    asm ("mrs %0, ctr_el0\n" : "=r"(ctr_el0));
+
+    /* CTR_EL0.IDC */
+    dc_required = !((ctr_el0 >> 28) & 1);
+
+    /* CTR_EL0.DIC */
+    ic_required = !((ctr_el0 >> 29) & 1);
+
+    if (dc_required) {
+        size_t dcache_stride, i;
+
+        /*
+         * Step according to the minimum cache size, as the cache maintenance
+         * instructions operate on the cache line of the given address.
+         *
+         * We assume that exec_data is properly aligned.
+         */
+        dcache_stride = (4 << ((ctr_el0 >> 16) & 0xF));
+
+        for (i = 0; i < length; i += dcache_stride) {
+            const char *dc_addr = &((const char *)exec_data)[i];
+            asm volatile ("dc cvau, %x[dc_addr]\n"
+                          : /* no outputs */
+                          : [dc_addr] "r"(dc_addr)
+                          : "memory");
+        }
+
+        asm volatile ("dmb ish\n");
+    }
+
+    if (ic_required) {
+        size_t icache_stride, i;
+
+        icache_stride = (4 << (ctr_el0 & 0xF));
+
+        for (i = 0; i < length; i += icache_stride) {
+            const char *ic_addr = &((const char *)exec_data)[i];
+            asm volatile ("ic ivau, %x[ic_addr]\n"
+                          : /* no outputs */
+                          : [ic_addr] "r"(ic_addr)
+                          : "memory");
+        }
+
+        asm volatile ("dmb ish\n");
+    }
+
+    asm volatile ("isb sy\n");
+}
+
+static int basic_test(uint32_t *rw_data, const uint32_t *exec_data)
+{
+    /*
+     * As user mode only misbehaved for dual-mapped code when previously
+     * translated code had been changed, we'll start off with this basic test
+     * function to ensure that there's already some translated code at
+     * exec_data before the next test. This should cause the next test to fail
+     * if `mark_code_modified` fails to invalidate the code.
+     *
+     * Note that the payload is in binary form instead of inline assembler
+     * because we cannot use __attribute__((naked)) on this platform and the
+     * workarounds are at least as ugly as this is.
+     */
+    static const uint32_t basic_payload[] = {
+        0xD65F03C0 /* 0x00: RET */
+    };
+
+    BasicTest *copied_ptr = (BasicTest *)exec_data;
+
+    memcpy(rw_data, basic_payload, sizeof(basic_payload));
+    mark_code_modified(exec_data, sizeof(basic_payload));
+
+    return copied_ptr(1234) == 1234;
+}
+
+static int self_modification_test(uint32_t *rw_data, const uint32_t *exec_data)
+{
+    /*
+     * This test is self-modifying in an attempt to cover an edge case where
+     * the IC IVAU instruction invalidates itself.
+     *
+     * Note that the IC IVAU instruction is 16 bytes into the function, in what
+     * will be the same cache line as the modified instruction on machines with
+     * a cache line size >= 16 bytes.
+     */
+    static const uint32_t self_mod_payload[] = {
+        /* Overwrite the placeholder instruction with the new one. */
+        0xB9001C20, /* 0x00: STR w0, [x1, 0x1C] */
+
+        /* Get the executable address of the modified instruction. */
+        0x100000A8, /* 0x04: ADR x8, <0x1C> */
+
+        /* Mark the modified instruction as updated. */
+        0xD50B7B28, /* 0x08: DC CVAU x8 */
+        0xD5033BBF, /* 0x0C: DMB ISH */
+        0xD50B7528, /* 0x10: IC IVAU x8 */
+        0xD5033BBF, /* 0x14: DMB ISH */
+        0xD5033FDF, /* 0x18: ISB */
+
+        /* Placeholder instruction, overwritten above. */
+        0x52800000, /* 0x1C: MOV w0, 0 */
+
+        0xD65F03C0  /* 0x20: RET */
+    };
+
+    SelfModTest *copied_ptr = (SelfModTest *)exec_data;
+    int i;
+
+    memcpy(rw_data, self_mod_payload, sizeof(self_mod_payload));
+    mark_code_modified(exec_data, sizeof(self_mod_payload));
+
+    for (i = 1; i < 10; i++) {
+        /* Replace the placeholder instruction with `MOV w0, i` */
+        uint32_t new_instr = 0x52800000 | (i << 5);
+
+        if (copied_ptr(new_instr, rw_data) != i) {
+            return 0;
+        }
+    }
+
+    return 1;
+}
+
+int main(int argc, char **argv)
+{
+    const char *shm_name = "qemu-test-tcg-aarch64-icivau";
+    int fd;
+
+    fd = shm_open(shm_name, O_CREAT | O_RDWR, S_IRUSR | S_IWUSR);
+
+    if (fd < 0) {
+        return EXIT_FAILURE;
+    }
+
+    /* Unlink early to avoid leaving garbage in case the test crashes. */
+    shm_unlink(shm_name);
+
+    if (ftruncate(fd, MAX_CODE_SIZE) == 0) {
+        const uint32_t *exec_data;
+        uint32_t *rw_data;
+
+        rw_data = mmap(0, MAX_CODE_SIZE, PROT_READ | PROT_WRITE,
+                       MAP_SHARED, fd, 0);
+        exec_data = mmap(0, MAX_CODE_SIZE, PROT_READ | PROT_EXEC,
+                         MAP_SHARED, fd, 0);
+
+        if (rw_data && exec_data) {
+            if (basic_test(rw_data, exec_data) &&
+                self_modification_test(rw_data, exec_data)) {
+                return EXIT_SUCCESS;
+            }
+        }
+    }
+
+    return EXIT_FAILURE;
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -XXX,XX +XXX,XX @@ AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
 VPATH 		+= $(AARCH64_SRC)
 
 # Base architecture tests
-AARCH64_TESTS=fcvt pcalign-a64
+AARCH64_TESTS=fcvt pcalign-a64 icivau
 
 fcvt: LDFLAGS+=-lm
+icivau: LDFLAGS+=-lrt
 
 run-fcvt: fcvt
 	$(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)")
-- 
2.34.1

From: Vikram Garhwal <vikram.garhwal@amd.com>

Following are done to fix the coverity issues:
1. Change read_data to fix the CID 1512899: Out-of-bounds access (OVERRUN)
2. Fix match_rx_tx_data to fix CID 1512900: Logically dead code (DEADCODE)
3. Replace rand() in generate_random_data() with g_rand_int()

Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
Message-id: 20230628202758.16398-1-vikram.garhwal@amd.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/xlnx-canfd-test.c | 33 +++++++++++----------------------
 1 file changed, 11 insertions(+), 22 deletions(-)

diff --git a/tests/qtest/xlnx-canfd-test.c b/tests/qtest/xlnx-canfd-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/xlnx-canfd-test.c
+++ b/tests/qtest/xlnx-canfd-test.c
@@ -XXX,XX +XXX,XX @@ static void generate_random_data(uint32_t *buf_tx, bool is_canfd_frame)
     /* Generate random TX data for CANFD frame. */
     if (is_canfd_frame) {
         for (int i = 0; i < CANFD_FRAME_SIZE - 2; i++) {
-            buf_tx[2 + i] = rand();
+            buf_tx[2 + i] = g_random_int();
         }
     } else {
         /* Generate random TX data for CAN frame. */
         for (int i = 0; i < CAN_FRAME_SIZE - 2; i++) {
-            buf_tx[2 + i] = rand();
+            buf_tx[2 + i] = g_random_int();
         }
     }
 }
 
-static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx)
+static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx,
+                      uint32_t frame_size)
 {
     uint32_t int_status;
     uint32_t fifo_status_reg_value;
     /* At which RX FIFO the received data is stored. */
     uint8_t store_ind = 0;
-    bool is_canfd_frame = false;
 
     /* Read the interrupt on CANFD rx. */
     int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK;
@@ -XXX,XX +XXX,XX @@ static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx)
     buf_rx[0] = qtest_readl(qts, can_base_addr + R_RX0_ID_OFFSET);
     buf_rx[1] = qtest_readl(qts, can_base_addr + R_RX0_DLC_OFFSET);
 
-    is_canfd_frame = (buf_rx[1] >> DLC_FD_BIT_SHIFT) & 1;
-
-    if (is_canfd_frame) {
-        for (int i = 0; i < CANFD_FRAME_SIZE - 2; i++) {
-            buf_rx[i + 2] = qtest_readl(qts,
-                                    can_base_addr + R_RX0_DATA1_OFFSET + 4 * i);
-        }
-    } else {
-        buf_rx[2] = qtest_readl(qts, can_base_addr + R_RX0_DATA1_OFFSET);
-        buf_rx[3] = qtest_readl(qts, can_base_addr + R_RX0_DATA2_OFFSET);
+    for (int i = 0; i < frame_size - 2; i++) {
+        buf_rx[i + 2] = qtest_readl(qts,
+                                can_base_addr + R_RX0_DATA1_OFFSET + 4 * i);
     }
 
     /* Clear the RX interrupt. */
@@ -XXX,XX +XXX,XX @@ static void match_rx_tx_data(const uint32_t *buf_tx, const uint32_t *buf_rx,
             g_assert_cmpint((buf_rx[size] & DLC_FD_BIT_MASK), ==,
                             (buf_tx[size] & DLC_FD_BIT_MASK));
         } else {
-            if (!is_canfd_frame && size == 4) {
-                break;
-            }
-
             g_assert_cmpint(buf_rx[size], ==, buf_tx[size]);
         }
 
@@ -XXX,XX +XXX,XX @@ static void test_can_data_transfer(void)
     write_data(qts, CANFD0_BASE_ADDR, buf_tx, false);
 
     send_data(qts, CANFD0_BASE_ADDR);
-    read_data(qts, CANFD1_BASE_ADDR, buf_rx);
+    read_data(qts, CANFD1_BASE_ADDR, buf_rx, CAN_FRAME_SIZE);
     match_rx_tx_data(buf_tx, buf_rx, false);
 
     qtest_quit(qts);
@@ -XXX,XX +XXX,XX @@ static void test_canfd_data_transfer(void)
     write_data(qts, CANFD0_BASE_ADDR, buf_tx, true);
 
     send_data(qts, CANFD0_BASE_ADDR);
-    read_data(qts, CANFD1_BASE_ADDR, buf_rx);
+    read_data(qts, CANFD1_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE);
     match_rx_tx_data(buf_tx, buf_rx, true);
 
     qtest_quit(qts);
@@ -XXX,XX +XXX,XX @@ static void test_can_loopback(void)
     write_data(qts, CANFD0_BASE_ADDR, buf_tx, true);
 
     send_data(qts, CANFD0_BASE_ADDR);
-    read_data(qts, CANFD0_BASE_ADDR, buf_rx);
+    read_data(qts, CANFD0_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE);
     match_rx_tx_data(buf_tx, buf_rx, true);
 
     generate_random_data(buf_tx, true);
@@ -XXX,XX +XXX,XX @@ static void test_can_loopback(void)
     write_data(qts, CANFD1_BASE_ADDR, buf_tx, true);
 
     send_data(qts, CANFD1_BASE_ADDR);
-    read_data(qts, CANFD1_BASE_ADDR, buf_rx);
+    read_data(qts, CANFD1_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE);
     match_rx_tx_data(buf_tx, buf_rx, true);
 
     qtest_quit(qts);
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

This code is only relevant when TCG is present in the build. Building
with --disable-tcg --enable-xen on an x86 host we get:

$ ../configure --target-list=x86_64-softmmu,aarch64-softmmu --disable-tcg --enable-xen
$ make -j$(nproc)
...
libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `m_sysreg_ptr':
 ../target/arm/gdbstub.c:358: undefined reference to `arm_v7m_get_sp_ptr'
 ../target/arm/gdbstub.c:361: undefined reference to `arm_v7m_get_sp_ptr'

libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `arm_gdb_get_m_systemreg':
../target/arm/gdbstub.c:405: undefined reference to `arm_v7m_mrs_control'

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20230628164821.16771-1-farosas@suse.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
     return cpu->dyn_sysreg_xml.num;
 }
 
+#ifdef CONFIG_TCG
 typedef enum {
     M_SYSREG_MSP,
     M_SYSREG_PSP,
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)
     return cpu->dyn_m_secextreg_xml.num;
 }
 #endif
+#endif /* CONFIG_TCG */
 
 const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 {
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
                              arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
                              "system-registers.xml", 0);
 
+#ifdef CONFIG_TCG
     if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
         gdb_register_coprocessor(cs,
             arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
         }
 #endif
     }
+#endif /* CONFIG_TCG */
 }
-- 
2.34.1

From: Akihiko Odaki <akihiko.odaki@daynix.com>

AwSRAMCClass is larger than SysBusDeviceClass so the class size must be
advertised accordingly.

Fixes: 05def917e1 ("hw: arm: allwinner-sramc: Add SRAM Controller support for R40")
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230628110905.38125-1-akihiko.odaki@daynix.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/allwinner-sramc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/misc/allwinner-sramc.c b/hw/misc/allwinner-sramc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/allwinner-sramc.c
+++ b/hw/misc/allwinner-sramc.c
@@ -XXX,XX +XXX,XX @@ static const TypeInfo allwinner_sramc_info = {
     .parent        = TYPE_SYS_BUS_DEVICE,
     .instance_init = allwinner_sramc_init,
     .instance_size = sizeof(AwSRAMCState),
+    .class_size    = sizeof(AwSRAMCClass),
     .class_init    = allwinner_sramc_class_init,
 };
 
-- 
2.34.1

In handle_interrupt() we use level as an index into the interrupt_vector[]
array. This is safe because we have checked it against env->config->nlevel,
but Coverity can't see that (and it is only true because each CPU config
sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it
complains about a possible array overrun (CID 1507131)

Add an assert() which will make Coverity happy and catch the unlikely
case of a mis-set XCHAL_NUM_INTLEVELS in future.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Message-id: 20230623154135.1930261-1-peter.maydell@linaro.org
---
 target/xtensa/exc_helper.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/xtensa/exc_helper.c
+++ b/target/xtensa/exc_helper.c
@@ -XXX,XX +XXX,XX @@ static void handle_interrupt(CPUXtensaState *env)
         CPUState *cs = env_cpu(env);
 
         if (level > 1) {
+            /* env->config->nlevel check should have ensured this */
+            assert(level < sizeof(env->config->interrupt_vector));
+
             env->sregs[EPC1 + level - 1] = env->pc;
             env->sregs[EPS2 + level - 2] = env->sregs[PS];
             env->sregs[PS] =
-- 
2.34.1