[PULL 00/24] target-arm queue
[PULL 00/21] target-arm queue
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The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
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The following changes since commit f003dd8d81f7d88f4b1f8802309eaa76f6eb223a:
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Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
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Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging (2023-03-06 10:20:04 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230306
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for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
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for you to fetch changes up to 2ddc45954f97cd1d7ee5cbca0def05e980d1da9f:
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target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
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hw: arm: allwinner-h3: Fix and complete H3 i2c devices (2023-03-06 15:31:24 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* more MVE instructions
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* allwinner-h3: Fix I2C controller model for Sun6i SoCs
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* hw/gpio/gpio_pwr: use shutdown function for reboot
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* allwinner-h3: Add missing i2c controllers
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* target/arm: Check NaN mode before silencing NaN
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* Expose M-profile system registers to gdbstub
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* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
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* Expose pauth information to gdbstub
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* hw/arm: Add basic power management to raspi.
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* Support direct boot for Linux/arm64 EFI zboot images
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* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
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* Fix incorrect stage 2 MMU setup validation
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----------------------------------------------------------------
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----------------------------------------------------------------
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Joe Komlodi (1):
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Ard Biesheuvel (1):
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target/arm: Check NaN mode before silencing NaN
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hw: arm: Support direct boot for Linux/arm64 EFI zboot images
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Maxim Uvarov (1):
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David Reiss (2):
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hw/gpio/gpio_pwr: use shutdown function for reboot
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target/arm: Export arm_v7m_mrs_control
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target/arm: Export arm_v7m_get_sp_ptr
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29
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Nolan Leake (1):
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Richard Henderson (16):
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hw/arm: Add basic power management to raspi.
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target/arm: Normalize aarch64 gdbstub get/set function names
32
target/arm: Unexport arm_gen_dynamic_sysreg_xml
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target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
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target/arm: Split out output_vector_union_type
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target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
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target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
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target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
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target/arm: Add name argument to output_vector_union_type
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target/arm: Simplify iteration over bit widths
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target/arm: Create pauth_ptr_mask
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target/arm: Implement gdbstub pauth extension
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target/arm: Implement gdbstub m-profile systemreg and secext
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target/arm: Handle m-profile in arm_is_secure
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target/arm: Stub arm_hcr_el2_eff for m-profile
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target/arm: Diagnose incorrect usage of arm_is_secure subroutines
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target/arm: Rewrite check_s2_mmu_setup
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47
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Patrick Venture (2):
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qianfan Zhao (2):
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docs/system/arm: Add quanta-q7l1-bmc reference
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hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
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docs/system/arm: Add quanta-gbs-bmc reference
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hw: arm: allwinner-h3: Fix and complete H3 i2c devices
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Peter Maydell (18):
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configs/targets/aarch64-linux-user.mak | 2 +-
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target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
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configs/targets/aarch64-softmmu.mak | 2 +-
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target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
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configs/targets/aarch64_be-linux-user.mak | 2 +-
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target/arm: Make asimd_imm_const() public
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include/hw/arm/allwinner-h3.h | 6 +
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target/arm: Use asimd_imm_const for A64 decode
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include/hw/i2c/allwinner-i2c.h | 6 +
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target/arm: Use dup_const() instead of bitfield_replicate()
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include/hw/loader.h | 19 ++
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target/arm: Implement MVE logical immediate insns
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target/arm/cpu.h | 17 +-
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target/arm: Implement MVE vector shift left by immediate insns
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target/arm/internals.h | 34 +++-
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target/arm: Implement MVE vector shift right by immediate insns
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hw/arm/allwinner-h3.c | 29 +++-
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target/arm: Implement MVE VSHLL
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hw/arm/boot.c | 6 +
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target/arm: Implement MVE VSRI, VSLI
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hw/core/loader.c | 91 ++++++++++
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target/arm: Implement MVE VSHRN, VRSHRN
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hw/i2c/allwinner-i2c.c | 26 ++-
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target/arm: Implement MVE saturating narrowing shifts
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target/arm/gdbstub.c | 278 ++++++++++++++++++------------
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target/arm: Implement MVE VSHLC
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target/arm/gdbstub64.c | 175 ++++++++++++++++++-
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target/arm: Implement MVE VADDLV
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target/arm/helper.c | 3 +
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target/arm: Implement MVE long shifts by immediate
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target/arm/ptw.c | 173 +++++++++++--------
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target/arm: Implement MVE long shifts by register
68
target/arm/tcg/m_helper.c | 90 +++++-----
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target/arm: Implement MVE shifts by immediate
69
target/arm/tcg/pauth_helper.c | 26 ++-
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target/arm: Implement MVE shifts by register
70
gdb-xml/aarch64-pauth.xml | 15 ++
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19 files changed, 742 insertions(+), 258 deletions(-)
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Philippe Mathieu-Daudé (1):
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create mode 100644 gdb-xml/aarch64-pauth.xml
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tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
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docs/system/arm/aspeed.rst | 1 +
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docs/system/arm/nuvoton.rst | 5 +-
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include/hw/arm/bcm2835_peripherals.h | 3 +-
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include/hw/misc/bcm2835_powermgt.h | 29 ++
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target/arm/helper-mve.h | 108 +++++++
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target/arm/translate.h | 41 +++
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target/arm/mve.decode | 177 ++++++++++-
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target/arm/t32.decode | 71 ++++-
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hw/arm/bcm2835_peripherals.c | 13 +-
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hw/gpio/gpio_pwr.c | 2 +-
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hw/misc/bcm2835_powermgt.c | 160 ++++++++++
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target/arm/helper-a64.c | 12 +-
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target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--
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target/arm/translate-a64.c | 86 +-----
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target/arm/translate-mve.c | 261 +++++++++++++++-
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target/arm/translate-neon.c | 81 -----
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target/arm/translate.c | 327 +++++++++++++++++++-
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target/arm/vfp_helper.c | 24 +-
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hw/misc/meson.build | 1 +
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tests/acceptance/boot_linux_console.py | 43 +++
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20 files changed, 1760 insertions(+), 209 deletions(-)
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create mode 100644 include/hw/misc/bcm2835_powermgt.h
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create mode 100644 hw/misc/bcm2835_powermgt.c
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diff view generated by jsdifflib
[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
[PULL 01/21] target/arm: Normalize aarch64 gdbstub get/set function names
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In do_ldst(), the calculation of the offset needs to be based on the
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From: Richard Henderson <richard.henderson@linaro.org>
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size of the memory access, not the size of the elements in the
3
vector. This meant we were getting it wrong for the widening and
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narrowing variants of the various VLDR and VSTR insns.
5
2
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Make the form of the function names between fp and sve the same:
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- arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg.
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- aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg.
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Reviewed-by: Fabiano Rosas <farosas@suse.de>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20230227213329.793795-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
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---
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---
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target/arm/translate-mve.c | 17 +++++++++--------
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target/arm/internals.h | 8 ++++----
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1 file changed, 9 insertions(+), 8 deletions(-)
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target/arm/gdbstub.c | 9 +++++----
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target/arm/gdbstub64.c | 8 ++++----
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3 files changed, 13 insertions(+), 12 deletions(-)
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17
13
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-mve.c
20
--- a/target/arm/internals.h
16
+++ b/target/arm/translate-mve.c
21
+++ b/target/arm/internals.h
17
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
22
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
23
}
24
25
#ifdef TARGET_AARCH64
26
-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);
27
-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);
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-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
29
-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
30
+int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
31
+int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
32
+int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
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+int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
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void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
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void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
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void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
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diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
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index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/gdbstub.c
40
+++ b/target/arm/gdbstub.c
41
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
42
*/
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#ifdef TARGET_AARCH64
44
if (isar_feature_aa64_sve(&cpu->isar)) {
45
- gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
46
- arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
47
+ int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs);
48
+ gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
49
+ aarch64_gdb_set_sve_reg, nreg,
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"sve-registers.xml", 0);
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} else {
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- gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
53
- aarch64_fpu_gdb_set_reg,
54
+ gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,
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+ aarch64_gdb_set_fpu_reg,
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34, "aarch64-fpu.xml", 0);
57
}
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#endif
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diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/target/arm/gdbstub64.c
62
+++ b/target/arm/gdbstub64.c
63
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
64
return 0;
65
}
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-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
68
+int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)
69
{
70
switch (reg) {
71
case 0 ... 31:
72
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
18
}
73
}
19
}
74
}
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75
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-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
76
-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
22
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
77
+int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)
23
+ unsigned msize)
24
{
78
{
25
TCGv_i32 addr;
79
switch (reg) {
26
uint32_t offset;
80
case 0 ... 31:
27
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
81
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
28
return true;
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}
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}
30
31
- offset = a->imm << a->size;
32
+ offset = a->imm << msize;
33
if (!a->a) {
34
offset = -offset;
35
}
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@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
37
{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
38
{ NULL, NULL }
39
};
40
- return do_ldst(s, a, ldstfns[a->size][a->l]);
41
+ return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
42
}
83
}
43
84
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-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \
85
-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
45
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \
86
+int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)
46
static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \
47
{ \
48
static MVEGenLdStFn * const ldstfns[2][2] = { \
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{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
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{ NULL, gen_helper_mve_##ULD }, \
51
}; \
52
- return do_ldst(s, a, ldstfns[a->u][a->l]); \
53
+ return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \
54
}
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56
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
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-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
58
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
59
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
60
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
61
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
62
63
static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
64
{
87
{
88
ARMCPU *cpu = env_archcpu(env);
89
90
@@ -XXX,XX +XXX,XX @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
91
return 0;
92
}
93
94
-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
95
+int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
96
{
97
ARMCPU *cpu = env_archcpu(env);
98
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--
99
--
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2.20.1
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2.34.1
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101
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diff view generated by jsdifflib
[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
[PULL 02/21] target/arm: Unexport arm_gen_dynamic_sysreg_xml
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From: Maxim Uvarov <maxim.uvarov@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
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2
3
qemu has 2 type of functions: shutdown and reboot. Shutdown
3
This function is not used outside gdbstub.c.
4
function has to be used for machine shutdown. Otherwise we cause
5
a reset with a bogus "cause" value, when we intended a shutdown.
6
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Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
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Reviewed-by: Fabiano Rosas <farosas@suse.de>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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[PMM: tweaked commit message]
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Message-id: 20230227213329.793795-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
10
---
13
hw/gpio/gpio_pwr.c | 2 +-
11
target/arm/cpu.h | 1 -
14
1 file changed, 1 insertion(+), 1 deletion(-)
12
target/arm/gdbstub.c | 2 +-
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2 files changed, 1 insertion(+), 2 deletions(-)
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14
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diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
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diff --git a/target/arm/cpu.h b/target/arm/cpu.h
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index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/gpio/gpio_pwr.c
17
--- a/target/arm/cpu.h
19
+++ b/hw/gpio/gpio_pwr.c
18
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
19
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
21
static void gpio_pwr_shutdown(void *opaque, int n, int level)
20
* Helpers to dynamically generates XML descriptions of the sysregs
22
{
21
* and SVE registers. Returns the number of registers in each set.
23
if (level) {
22
*/
24
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
23
-int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
25
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
24
int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
25
26
/* Returns the dynamically generated XML for the gdb stub.
27
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/gdbstub.c
30
+++ b/target/arm/gdbstub.c
31
@@ -XXX,XX +XXX,XX @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
26
}
32
}
27
}
33
}
28
34
35
-int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
36
+static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
37
{
38
ARMCPU *cpu = ARM_CPU(cs);
39
GString *s = g_string_new(NULL);
29
--
40
--
30
2.20.1
41
2.34.1
31
42
32
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diff view generated by jsdifflib
[PULL 12/24] target/arm: Implement MVE logical immediate insns
[PULL 03/21] target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
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Implement the MVE logical-immediate insns (VMOV, VMVN,
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From: Richard Henderson <richard.henderson@linaro.org>
2
VORR and VBIC). These have essentially the same encoding
2
3
as their Neon equivalents, and we implement the decode
3
The function is only used for aarch64, so move it to the
4
in the same way.
4
file that has the other aarch64 gdbstub stuff. Move the
5
5
declaration to internals.h.
6
7
Reviewed-by: Fabiano Rosas <farosas@suse.de>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20230227213329.793795-4-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
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---
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---
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target/arm/helper-mve.h | 4 +++
13
target/arm/cpu.h | 6 ---
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target/arm/mve.decode | 17 +++++++++++++
14
target/arm/internals.h | 1 +
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target/arm/mve_helper.c | 24 ++++++++++++++++++
15
target/arm/gdbstub.c | 120 -----------------------------------------
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target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
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target/arm/gdbstub64.c | 118 ++++++++++++++++++++++++++++++++++++++++
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4 files changed, 95 insertions(+)
17
4 files changed, 119 insertions(+), 126 deletions(-)
15
18
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-mve.h
21
--- a/target/arm/cpu.h
19
+++ b/target/arm/helper-mve.h
22
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
23
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
21
DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
24
int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
22
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
25
int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
23
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
26
24
+
27
-/*
25
+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
28
- * Helpers to dynamically generates XML descriptions of the sysregs
26
+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
29
- * and SVE registers. Returns the number of registers in each set.
27
+DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
30
- */
28
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
31
-int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
32
-
33
/* Returns the dynamically generated XML for the gdb stub.
34
* Returns a pointer to the XML contents for the specified XML file or NULL
35
* if the XML name doesn't match the predefined one.
36
diff --git a/target/arm/internals.h b/target/arm/internals.h
29
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/mve.decode
38
--- a/target/arm/internals.h
31
+++ b/target/arm/mve.decode
39
+++ b/target/arm/internals.h
32
@@ -XXX,XX +XXX,XX @@
40
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
33
# VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
41
}
34
%size_28 28:1 !function=plus_1
42
35
43
#ifdef TARGET_AARCH64
36
+# 1imm format immediate
44
+int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
37
+%imm_28_16_0 28:1 16:3 0:4
45
int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
38
+
46
int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
39
&vldr_vstr rn qd imm p a w size l u
47
int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
40
&1op qd qm size
48
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
41
&2op qd qm qn size
42
&2scalar qd qn rm size
43
+&1imm qd imm cmode op
44
45
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
46
# Note that both Rn and Qd are 3 bits only (no D bit)
47
@@ -XXX,XX +XXX,XX @@
48
@2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
49
@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
50
size=%size_28
51
+@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
52
53
# The _rev suffix indicates that Vn and Vm are reversed. This is
54
# the case for shifts. In the Arm ARM these insns are documented
55
@@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
56
# Predicate operations
57
%mask_22_13 22:1 13:3
58
VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
59
+
60
+# Logical immediate operations (1 reg and modified-immediate)
61
+
62
+# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
63
+# not in a way we can conveniently represent in decodetree without
64
+# a lot of repetition:
65
+# VORR: op=0, (cmode & 1) && cmode < 12
66
+# VBIC: op=1, (cmode & 1) && cmode < 12
67
+# VMOV: everything else
68
+# So we have a single decode line and check the cmode/op in the
69
+# trans function.
70
+Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
71
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
72
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/mve_helper.c
50
--- a/target/arm/gdbstub.c
74
+++ b/target/arm/mve_helper.c
51
+++ b/target/arm/gdbstub.c
75
@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
52
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
76
DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
53
return cpu->dyn_sysreg_xml.num;
77
DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
54
}
78
55
79
+/*
56
-struct TypeSize {
80
+ * 1 operand immediates: Vda is destination and possibly also one source.
57
- const char *gdb_type;
81
+ * All these insns work at 64-bit widths.
58
- int size;
82
+ */
59
- const char sz, suffix;
83
+#define DO_1OP_IMM(OP, FN) \
60
-};
84
+ void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \
61
-
85
+ { \
62
-static const struct TypeSize vec_lanes[] = {
86
+ uint64_t *da = vda; \
63
- /* quads */
87
+ uint16_t mask = mve_element_mask(env); \
64
- { "uint128", 128, 'q', 'u' },
88
+ unsigned e; \
65
- { "int128", 128, 'q', 's' },
89
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
66
- /* 64 bit */
90
+ mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \
67
- { "ieee_double", 64, 'd', 'f' },
91
+ } \
68
- { "uint64", 64, 'd', 'u' },
92
+ mve_advance_vpt(env); \
69
- { "int64", 64, 'd', 's' },
93
+ }
70
- /* 32 bit */
94
+
71
- { "ieee_single", 32, 's', 'f' },
95
+#define DO_MOVI(N, I) (I)
72
- { "uint32", 32, 's', 'u' },
96
+#define DO_ANDI(N, I) ((N) & (I))
73
- { "int32", 32, 's', 's' },
97
+#define DO_ORRI(N, I) ((N) | (I))
74
- /* 16 bit */
98
+
75
- { "ieee_half", 16, 'h', 'f' },
99
+DO_1OP_IMM(vmovi, DO_MOVI)
76
- { "uint16", 16, 'h', 'u' },
100
+DO_1OP_IMM(vandi, DO_ANDI)
77
- { "int16", 16, 'h', 's' },
101
+DO_1OP_IMM(vorri, DO_ORRI)
78
- /* bytes */
102
+
79
- { "uint8", 8, 'b', 'u' },
103
#define DO_2OP(OP, ESIZE, TYPE, FN) \
80
- { "int8", 8, 'b', 's' },
104
void HELPER(glue(mve_, OP))(CPUARMState *env, \
81
-};
105
void *vd, void *vn, void *vm) \
82
-
106
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
83
-
84
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
85
-{
86
- ARMCPU *cpu = ARM_CPU(cs);
87
- GString *s = g_string_new(NULL);
88
- DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
89
- g_autoptr(GString) ts = g_string_new("");
90
- int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
91
- info->num = 0;
92
- g_string_printf(s, "<?xml version=\"1.0\"?>");
93
- g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
94
- g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
95
-
96
- /* First define types and totals in a whole VL */
97
- for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
98
- int count = reg_width / vec_lanes[i].size;
99
- g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
100
- g_string_append_printf(s,
101
- "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
102
- ts->str, vec_lanes[i].gdb_type, count);
103
- }
104
- /*
105
- * Now define a union for each size group containing unsigned and
106
- * signed and potentially float versions of each size from 128 to
107
- * 8 bits.
108
- */
109
- for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
110
- const char suf[] = { 'q', 'd', 's', 'h', 'b' };
111
- g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
112
- for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
113
- if (vec_lanes[j].size == bits) {
114
- g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
115
- vec_lanes[j].suffix,
116
- vec_lanes[j].sz, vec_lanes[j].suffix);
117
- }
118
- }
119
- g_string_append(s, "</union>");
120
- }
121
- /* And now the final union of unions */
122
- g_string_append(s, "<union id=\"svev\">");
123
- for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
124
- const char suf[] = { 'q', 'd', 's', 'h', 'b' };
125
- g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
126
- suf[i], suf[i]);
127
- }
128
- g_string_append(s, "</union>");
129
-
130
- /* Finally the sve prefix type */
131
- g_string_append_printf(s,
132
- "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
133
- reg_width / 8);
134
-
135
- /* Then define each register in parts for each vq */
136
- for (i = 0; i < 32; i++) {
137
- g_string_append_printf(s,
138
- "<reg name=\"z%d\" bitsize=\"%d\""
139
- " regnum=\"%d\" type=\"svev\"/>",
140
- i, reg_width, base_reg++);
141
- info->num++;
142
- }
143
- /* fpscr & status registers */
144
- g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
145
- " regnum=\"%d\" group=\"float\""
146
- " type=\"int\"/>", base_reg++);
147
- g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
148
- " regnum=\"%d\" group=\"float\""
149
- " type=\"int\"/>", base_reg++);
150
- info->num += 2;
151
-
152
- for (i = 0; i < 16; i++) {
153
- g_string_append_printf(s,
154
- "<reg name=\"p%d\" bitsize=\"%d\""
155
- " regnum=\"%d\" type=\"svep\"/>",
156
- i, cpu->sve_max_vq * 16, base_reg++);
157
- info->num++;
158
- }
159
- g_string_append_printf(s,
160
- "<reg name=\"ffr\" bitsize=\"%d\""
161
- " regnum=\"%d\" group=\"vector\""
162
- " type=\"svep\"/>",
163
- cpu->sve_max_vq * 16, base_reg++);
164
- g_string_append_printf(s,
165
- "<reg name=\"vg\" bitsize=\"64\""
166
- " regnum=\"%d\" type=\"int\"/>",
167
- base_reg++);
168
- info->num += 2;
169
- g_string_append_printf(s, "</feature>");
170
- cpu->dyn_svereg_xml.desc = g_string_free(s, false);
171
-
172
- return cpu->dyn_svereg_xml.num;
173
-}
174
-
175
-
176
const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
177
{
178
ARMCPU *cpu = ARM_CPU(cs);
179
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
107
index XXXXXXX..XXXXXXX 100644
180
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-mve.c
181
--- a/target/arm/gdbstub64.c
109
+++ b/target/arm/translate-mve.c
182
+++ b/target/arm/gdbstub64.c
110
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
183
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
111
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
184
112
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
185
return 0;
113
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
114
+typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
115
116
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
117
static inline long mve_qreg_offset(unsigned reg)
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
119
mve_update_eci(s);
120
return true;
121
}
186
}
122
+
187
+
123
+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
188
+struct TypeSize {
189
+ const char *gdb_type;
190
+ short size;
191
+ char sz, suffix;
192
+};
193
+
194
+static const struct TypeSize vec_lanes[] = {
195
+ /* quads */
196
+ { "uint128", 128, 'q', 'u' },
197
+ { "int128", 128, 'q', 's' },
198
+ /* 64 bit */
199
+ { "ieee_double", 64, 'd', 'f' },
200
+ { "uint64", 64, 'd', 'u' },
201
+ { "int64", 64, 'd', 's' },
202
+ /* 32 bit */
203
+ { "ieee_single", 32, 's', 'f' },
204
+ { "uint32", 32, 's', 'u' },
205
+ { "int32", 32, 's', 's' },
206
+ /* 16 bit */
207
+ { "ieee_half", 16, 'h', 'f' },
208
+ { "uint16", 16, 'h', 'u' },
209
+ { "int16", 16, 'h', 's' },
210
+ /* bytes */
211
+ { "uint8", 8, 'b', 'u' },
212
+ { "int8", 8, 'b', 's' },
213
+};
214
+
215
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
124
+{
216
+{
125
+ TCGv_ptr qd;
217
+ ARMCPU *cpu = ARM_CPU(cs);
126
+ uint64_t imm;
218
+ GString *s = g_string_new(NULL);
127
+
219
+ DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
128
+ if (!dc_isar_feature(aa32_mve, s) ||
220
+ g_autoptr(GString) ts = g_string_new("");
129
+ !mve_check_qreg_bank(s, a->qd) ||
221
+ int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
130
+ !fn) {
222
+ info->num = 0;
131
+ return false;
223
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
132
+ }
224
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
133
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
225
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
134
+ return true;
226
+
135
+ }
227
+ /* First define types and totals in a whole VL */
136
+
228
+ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
137
+ imm = asimd_imm_const(a->imm, a->cmode, a->op);
229
+ int count = reg_width / vec_lanes[i].size;
138
+
230
+ g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
139
+ qd = mve_qreg_ptr(a->qd);
231
+ g_string_append_printf(s,
140
+ fn(cpu_env, qd, tcg_constant_i64(imm));
232
+ "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
141
+ tcg_temp_free_ptr(qd);
233
+ ts->str, vec_lanes[i].gdb_type, count);
142
+ mve_update_eci(s);
234
+ }
143
+ return true;
235
+ /*
144
+}
236
+ * Now define a union for each size group containing unsigned and
145
+
237
+ * signed and potentially float versions of each size from 128 to
146
+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
238
+ * 8 bits.
147
+{
239
+ */
148
+ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
240
+ for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
149
+ MVEGenOneOpImmFn *fn;
241
+ const char suf[] = { 'q', 'd', 's', 'h', 'b' };
150
+
242
+ g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
151
+ if ((a->cmode & 1) && a->cmode < 12) {
243
+ for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
152
+ if (a->op) {
244
+ if (vec_lanes[j].size == bits) {
153
+ /*
245
+ g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
154
+ * For op=1, the immediate will be inverted by asimd_imm_const(),
246
+ vec_lanes[j].suffix,
155
+ * so the VBIC becomes a logical AND operation.
247
+ vec_lanes[j].sz, vec_lanes[j].suffix);
156
+ */
248
+ }
157
+ fn = gen_helper_mve_vandi;
158
+ } else {
159
+ fn = gen_helper_mve_vorri;
160
+ }
249
+ }
161
+ } else {
250
+ g_string_append(s, "</union>");
162
+ /* There is one unallocated cmode/op combination in this space */
251
+ }
163
+ if (a->cmode == 15 && a->op == 1) {
252
+ /* And now the final union of unions */
164
+ return false;
253
+ g_string_append(s, "<union id=\"svev\">");
165
+ }
254
+ for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
166
+ /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
255
+ const char suf[] = { 'q', 'd', 's', 'h', 'b' };
167
+ fn = gen_helper_mve_vmovi;
256
+ g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
168
+ }
257
+ suf[i], suf[i]);
169
+ return do_1imm(s, a, fn);
258
+ }
259
+ g_string_append(s, "</union>");
260
+
261
+ /* Finally the sve prefix type */
262
+ g_string_append_printf(s,
263
+ "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
264
+ reg_width / 8);
265
+
266
+ /* Then define each register in parts for each vq */
267
+ for (i = 0; i < 32; i++) {
268
+ g_string_append_printf(s,
269
+ "<reg name=\"z%d\" bitsize=\"%d\""
270
+ " regnum=\"%d\" type=\"svev\"/>",
271
+ i, reg_width, base_reg++);
272
+ info->num++;
273
+ }
274
+ /* fpscr & status registers */
275
+ g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
276
+ " regnum=\"%d\" group=\"float\""
277
+ " type=\"int\"/>", base_reg++);
278
+ g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
279
+ " regnum=\"%d\" group=\"float\""
280
+ " type=\"int\"/>", base_reg++);
281
+ info->num += 2;
282
+
283
+ for (i = 0; i < 16; i++) {
284
+ g_string_append_printf(s,
285
+ "<reg name=\"p%d\" bitsize=\"%d\""
286
+ " regnum=\"%d\" type=\"svep\"/>",
287
+ i, cpu->sve_max_vq * 16, base_reg++);
288
+ info->num++;
289
+ }
290
+ g_string_append_printf(s,
291
+ "<reg name=\"ffr\" bitsize=\"%d\""
292
+ " regnum=\"%d\" group=\"vector\""
293
+ " type=\"svep\"/>",
294
+ cpu->sve_max_vq * 16, base_reg++);
295
+ g_string_append_printf(s,
296
+ "<reg name=\"vg\" bitsize=\"64\""
297
+ " regnum=\"%d\" type=\"int\"/>",
298
+ base_reg++);
299
+ info->num += 2;
300
+ g_string_append_printf(s, "</feature>");
301
+ info->desc = g_string_free(s, false);
302
+
303
+ return info->num;
170
+}
304
+}
171
--
305
--
172
2.20.1
306
2.34.1
173
307
174
308
diff view generated by jsdifflib
[PULL 24/24] target/arm: Implement MVE shifts by register
[PULL 04/21] target/arm: Split out output_vector_union_type
1
Implement the MVE shifts by register, which perform
1
From: Richard Henderson <richard.henderson@linaro.org>
2
shifts on a single general-purpose register.
3
2
3
Create a subroutine for creating the union of unions
4
of the various type sizes that a vector may contain.
5
6
Reviewed-by: Fabiano Rosas <farosas@suse.de>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230227213329.793795-5-richard.henderson@linaro.org
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
7
---
11
---
8
target/arm/helper-mve.h | 2 ++
12
target/arm/gdbstub64.c | 83 +++++++++++++++++++++++-------------------
9
target/arm/translate.h | 1 +
13
1 file changed, 45 insertions(+), 38 deletions(-)
10
target/arm/t32.decode | 18 ++++++++++++++----
11
target/arm/mve_helper.c | 10 ++++++++++
12
target/arm/translate.c | 30 ++++++++++++++++++++++++++++++
13
5 files changed, 57 insertions(+), 4 deletions(-)
14
14
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
15
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-mve.h
17
--- a/target/arm/gdbstub64.c
18
+++ b/target/arm/helper-mve.h
18
+++ b/target/arm/gdbstub64.c
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
19
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
20
20
return 0;
21
DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
21
}
22
DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
22
23
+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
23
-struct TypeSize {
24
+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
24
- const char *gdb_type;
25
diff --git a/target/arm/translate.h b/target/arm/translate.h
25
- short size;
26
index XXXXXXX..XXXXXXX 100644
26
- char sz, suffix;
27
--- a/target/arm/translate.h
27
-};
28
+++ b/target/arm/translate.h
28
-
29
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
29
-static const struct TypeSize vec_lanes[] = {
30
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
30
- /* quads */
31
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
31
- { "uint128", 128, 'q', 'u' },
32
typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
32
- { "int128", 128, 'q', 's' },
33
+typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
33
- /* 64 bit */
34
34
- { "ieee_double", 64, 'd', 'f' },
35
/**
35
- { "uint64", 64, 'd', 'u' },
36
* arm_tbflags_from_tb:
36
- { "int64", 64, 'd', 's' },
37
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
37
- /* 32 bit */
38
index XXXXXXX..XXXXXXX 100644
38
- { "ieee_single", 32, 's', 'f' },
39
--- a/target/arm/t32.decode
39
- { "uint32", 32, 's', 'u' },
40
+++ b/target/arm/t32.decode
40
- { "int32", 32, 's', 's' },
41
@@ -XXX,XX +XXX,XX @@
41
- /* 16 bit */
42
&mve_shl_ri rdalo rdahi shim
42
- { "ieee_half", 16, 'h', 'f' },
43
&mve_shl_rr rdalo rdahi rm
43
- { "uint16", 16, 'h', 'u' },
44
&mve_sh_ri rda shim
44
- { "int16", 16, 'h', 's' },
45
+&mve_sh_rr rda rm
45
- /* bytes */
46
46
- { "uint8", 8, 'b', 'u' },
47
# rdahi: bits [3:1] from insn, bit 0 is 1
47
- { "int8", 8, 'b', 's' },
48
# rdalo: bits [3:1] from insn, bit 0 is 0
48
-};
49
@@ -XXX,XX +XXX,XX @@
49
-
50
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
50
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
51
@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
51
+static void output_vector_union_type(GString *s, int reg_width)
52
&mve_sh_ri shim=%imm5_12_6
53
+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
54
55
{
52
{
56
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
53
- ARMCPU *cpu = ARM_CPU(cs);
57
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
54
- GString *s = g_string_new(NULL);
58
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
55
- DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
56
+ struct TypeSize {
57
+ const char *gdb_type;
58
+ short size;
59
+ char sz, suffix;
60
+ };
61
+
62
+ static const struct TypeSize vec_lanes[] = {
63
+ /* quads */
64
+ { "uint128", 128, 'q', 'u' },
65
+ { "int128", 128, 'q', 's' },
66
+ /* 64 bit */
67
+ { "ieee_double", 64, 'd', 'f' },
68
+ { "uint64", 64, 'd', 'u' },
69
+ { "int64", 64, 'd', 's' },
70
+ /* 32 bit */
71
+ { "ieee_single", 32, 's', 'f' },
72
+ { "uint32", 32, 's', 'u' },
73
+ { "int32", 32, 's', 's' },
74
+ /* 16 bit */
75
+ { "ieee_half", 16, 'h', 'f' },
76
+ { "uint16", 16, 'h', 'u' },
77
+ { "int16", 16, 'h', 's' },
78
+ /* bytes */
79
+ { "uint8", 8, 'b', 'u' },
80
+ { "int8", 8, 'b', 's' },
81
+ };
82
+
83
+ static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
84
+
85
g_autoptr(GString) ts = g_string_new("");
86
- int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
87
- info->num = 0;
88
- g_string_printf(s, "<?xml version=\"1.0\"?>");
89
- g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
90
- g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
91
+ int i, j, bits;
92
93
/* First define types and totals in a whole VL */
94
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
95
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
96
* 8 bits.
97
*/
98
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
99
- const char suf[] = { 'q', 'd', 's', 'h', 'b' };
100
g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
101
for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
102
if (vec_lanes[j].size == bits) {
103
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
104
/* And now the final union of unions */
105
g_string_append(s, "<union id=\"svev\">");
106
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
107
- const char suf[] = { 'q', 'd', 's', 'h', 'b' };
108
g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
109
suf[i], suf[i]);
59
}
110
}
60
111
g_string_append(s, "</union>");
61
- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
62
- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
63
- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
64
- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
65
+ {
66
+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr
67
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
68
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
69
+ }
70
+
71
+ {
72
+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr
73
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
74
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
75
+ }
76
+
77
UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
78
SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
79
]
80
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/mve_helper.c
83
+++ b/target/arm/mve_helper.c
84
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
85
{
86
return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
87
}
88
+
89
+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
90
+{
91
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
92
+}
112
+}
93
+
113
+
94
+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
114
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
95
+{
115
+{
96
+ return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
116
+ ARMCPU *cpu = ARM_CPU(cs);
97
+}
117
+ GString *s = g_string_new(NULL);
98
diff --git a/target/arm/translate.c b/target/arm/translate.c
118
+ DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
99
index XXXXXXX..XXXXXXX 100644
119
+ int i, reg_width = (cpu->sve_max_vq * 128);
100
--- a/target/arm/translate.c
120
+ info->num = 0;
101
+++ b/target/arm/translate.c
121
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
102
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
122
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
103
return do_mve_sh_ri(s, a, gen_mve_uqshl);
123
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
104
}
105
106
+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
107
+{
108
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
109
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
110
+ return false;
111
+ }
112
+ if (!dc_isar_feature(aa32_mve, s) ||
113
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
114
+ a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
115
+ a->rm == a->rda) {
116
+ /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
117
+ unallocated_encoding(s);
118
+ return true;
119
+ }
120
+
124
+
121
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
125
+ output_vector_union_type(s, reg_width);
122
+ fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
126
123
+ return true;
127
/* Finally the sve prefix type */
124
+}
128
g_string_append_printf(s,
125
+
126
+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
127
+{
128
+ return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
129
+}
130
+
131
+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
132
+{
133
+ return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
134
+}
135
+
136
/*
137
* Multiply and multiply accumulate
138
*/
139
--
129
--
140
2.20.1
130
2.34.1
141
142
diff view generated by jsdifflib
[PULL 23/24] target/arm: Implement MVE shifts by immediate
[PULL 05/21] target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
1
Implement the MVE shifts by immediate, which perform shifts
1
From: Richard Henderson <richard.henderson@linaro.org>
2
on a single general-purpose register.
3
2
4
These patterns overlap with the long-shift-by-immediates,
3
Rather than increment base_reg and num, compute num from the change
5
so we have to rearrange the grouping a little here.
4
to base_reg at the end. Clean up some nearby comments.
6
5
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230227213329.793795-6-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
10
---
10
---
11
target/arm/helper-mve.h | 3 ++
11
target/arm/gdbstub64.c | 27 ++++++++++++++++-----------
12
target/arm/translate.h | 1 +
12
1 file changed, 16 insertions(+), 11 deletions(-)
13
target/arm/t32.decode | 31 ++++++++++++++-----
14
target/arm/mve_helper.c | 10 ++++++
15
target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++--
16
5 files changed, 104 insertions(+), 9 deletions(-)
17
13
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
14
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper-mve.h
16
--- a/target/arm/gdbstub64.c
21
+++ b/target/arm/helper-mve.h
17
+++ b/target/arm/gdbstub64.c
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
18
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
23
DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
19
g_string_append(s, "</union>");
24
DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
20
}
25
DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
21
22
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
23
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
24
{
25
ARMCPU *cpu = ARM_CPU(cs);
26
GString *s = g_string_new(NULL);
27
DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
28
- int i, reg_width = (cpu->sve_max_vq * 128);
29
- info->num = 0;
30
+ int reg_width = cpu->sve_max_vq * 128;
31
+ int base_reg = orig_base_reg;
32
+ int i;
26
+
33
+
27
+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
34
g_string_printf(s, "<?xml version=\"1.0\"?>");
28
+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
35
g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
36
g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
30
index XXXXXXX..XXXXXXX 100644
37
31
--- a/target/arm/translate.h
38
+ /* Create the vector union type. */
32
+++ b/target/arm/translate.h
39
output_vector_union_type(s, reg_width);
33
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
40
34
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
41
- /* Finally the sve prefix type */
35
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
42
+ /* Create the predicate vector type. */
36
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
43
g_string_append_printf(s,
37
+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
44
"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
38
45
reg_width / 8);
39
/**
46
40
* arm_tbflags_from_tb:
47
- /* Then define each register in parts for each vq */
41
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
48
+ /* Define the vector registers. */
42
index XXXXXXX..XXXXXXX 100644
49
for (i = 0; i < 32; i++) {
43
--- a/target/arm/t32.decode
50
g_string_append_printf(s,
44
+++ b/target/arm/t32.decode
51
"<reg name=\"z%d\" bitsize=\"%d\""
45
@@ -XXX,XX +XXX,XX @@
52
" regnum=\"%d\" type=\"svev\"/>",
46
53
i, reg_width, base_reg++);
47
&mve_shl_ri rdalo rdahi shim
54
- info->num++;
48
&mve_shl_rr rdalo rdahi rm
55
}
49
+&mve_sh_ri rda shim
50
51
# rdahi: bits [3:1] from insn, bit 0 is 1
52
# rdalo: bits [3:1] from insn, bit 0 is 0
53
@@ -XXX,XX +XXX,XX @@
54
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
55
@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
56
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
57
+@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
58
+ &mve_sh_ri shim=%imm5_12_6
59
60
{
61
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
62
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
63
# the rest fall through (where ORR_rrri and MOV_rxri will end up
64
# handling them as r13 and r15 accesses with the same semantics as A32).
65
[
66
- LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
67
- LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
68
- ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
69
+ {
70
+ UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri
71
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
72
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
73
+ }
74
75
- UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
76
- URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
77
- SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
78
- SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
79
+ {
80
+ URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri
81
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
82
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
83
+ }
84
+
56
+
85
+ {
57
/* fpscr & status registers */
86
+ SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri
58
g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
87
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
59
" regnum=\"%d\" group=\"float\""
88
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
60
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
89
+ }
61
g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
62
" regnum=\"%d\" group=\"float\""
63
" type=\"int\"/>", base_reg++);
64
- info->num += 2;
65
66
+ /* Define the predicate registers. */
67
for (i = 0; i < 16; i++) {
68
g_string_append_printf(s,
69
"<reg name=\"p%d\" bitsize=\"%d\""
70
" regnum=\"%d\" type=\"svep\"/>",
71
i, cpu->sve_max_vq * 16, base_reg++);
72
- info->num++;
73
}
74
g_string_append_printf(s,
75
"<reg name=\"ffr\" bitsize=\"%d\""
76
" regnum=\"%d\" group=\"vector\""
77
" type=\"svep\"/>",
78
cpu->sve_max_vq * 16, base_reg++);
90
+
79
+
91
+ {
80
+ /* Define the vector length pseudo-register. */
92
+ SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri
81
g_string_append_printf(s,
93
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
82
"<reg name=\"vg\" bitsize=\"64\""
94
+ }
83
" regnum=\"%d\" type=\"int\"/>",
95
84
base_reg++);
96
LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
85
- info->num += 2;
97
ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
86
- g_string_append_printf(s, "</feature>");
98
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
87
- info->desc = g_string_free(s, false);
99
index XXXXXXX..XXXXXXX 100644
88
100
--- a/target/arm/mve_helper.c
89
+ g_string_append_printf(s, "</feature>");
101
+++ b/target/arm/mve_helper.c
90
+
102
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
91
+ info->desc = g_string_free(s, false);
103
{
92
+ info->num = base_reg - orig_base_reg;
104
return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
93
return info->num;
105
}
94
}
106
+
107
+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
108
+{
109
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
110
+}
111
+
112
+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
113
+{
114
+ return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
115
+}
116
diff --git a/target/arm/translate.c b/target/arm/translate.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/target/arm/translate.c
119
+++ b/target/arm/translate.c
120
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
121
122
static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
123
{
124
- TCGv_i32 t = tcg_temp_new_i32();
125
+ TCGv_i32 t;
126
127
+ /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
128
+ if (sh == 32) {
129
+ tcg_gen_movi_i32(d, 0);
130
+ return;
131
+ }
132
+ t = tcg_temp_new_i32();
133
tcg_gen_extract_i32(t, a, sh - 1, 1);
134
tcg_gen_sari_i32(d, a, sh);
135
tcg_gen_add_i32(d, d, t);
136
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
137
138
static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
139
{
140
- TCGv_i32 t = tcg_temp_new_i32();
141
+ TCGv_i32 t;
142
143
+ /* Handle shift by the input size for the benefit of trans_URSHR_ri */
144
+ if (sh == 32) {
145
+ tcg_gen_extract_i32(d, a, sh - 1, 1);
146
+ return;
147
+ }
148
+ t = tcg_temp_new_i32();
149
tcg_gen_extract_i32(t, a, sh - 1, 1);
150
tcg_gen_shri_i32(d, a, sh);
151
tcg_gen_add_i32(d, d, t);
152
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
153
return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
154
}
155
156
+static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
157
+{
158
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
159
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
160
+ return false;
161
+ }
162
+ if (!dc_isar_feature(aa32_mve, s) ||
163
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
164
+ a->rda == 13 || a->rda == 15) {
165
+ /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
166
+ unallocated_encoding(s);
167
+ return true;
168
+ }
169
+
170
+ if (a->shim == 0) {
171
+ a->shim = 32;
172
+ }
173
+ fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
174
+
175
+ return true;
176
+}
177
+
178
+static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
179
+{
180
+ return do_mve_sh_ri(s, a, gen_urshr32_i32);
181
+}
182
+
183
+static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
184
+{
185
+ return do_mve_sh_ri(s, a, gen_srshr32_i32);
186
+}
187
+
188
+static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
189
+{
190
+ gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
191
+}
192
+
193
+static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
194
+{
195
+ return do_mve_sh_ri(s, a, gen_mve_sqshl);
196
+}
197
+
198
+static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
199
+{
200
+ gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
201
+}
202
+
203
+static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
204
+{
205
+ return do_mve_sh_ri(s, a, gen_mve_uqshl);
206
+}
207
+
208
/*
209
* Multiply and multiply accumulate
210
*/
211
--
95
--
212
2.20.1
96
2.34.1
213
97
214
98
diff view generated by jsdifflib
[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
[PULL 06/21] target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
1
From: Patrick Venture <venture@google.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add line item reference to quanta-gbs-bmc machine.
3
Reviewed-by: Fabiano Rosas <farosas@suse.de>
4
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Patrick Venture <venture@google.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
6
Message-id: 20230227213329.793795-7-richard.henderson@linaro.org
7
Message-id: 20210615192848.1065297-3-venture@google.com
8
[PMM: fixed underline Sphinx warning]
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
8
---
11
docs/system/arm/nuvoton.rst | 5 +++--
9
target/arm/gdbstub64.c | 5 +++--
12
1 file changed, 3 insertions(+), 2 deletions(-)
10
1 file changed, 3 insertions(+), 2 deletions(-)
13
11
14
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
12
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/nuvoton.rst
14
--- a/target/arm/gdbstub64.c
17
+++ b/docs/system/arm/nuvoton.rst
15
+++ b/target/arm/gdbstub64.c
18
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
19
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
17
GString *s = g_string_new(NULL);
20
-=====================================================
18
DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
21
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
19
int reg_width = cpu->sve_max_vq * 128;
22
+================================================================
20
+ int pred_width = cpu->sve_max_vq * 16;
23
21
int base_reg = orig_base_reg;
24
The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
22
int i;
25
designed to be used as Baseboard Management Controllers (BMCs) in various
23
26
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
24
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
27
The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
25
g_string_append_printf(s,
28
Hyperscale applications. The following machines are based on this chip :
26
"<reg name=\"p%d\" bitsize=\"%d\""
29
27
" regnum=\"%d\" type=\"svep\"/>",
30
+- ``quanta-gbs-bmc`` Quanta GBS server BMC
28
- i, cpu->sve_max_vq * 16, base_reg++);
31
- ``quanta-gsj`` Quanta GSJ server BMC
29
+ i, pred_width, base_reg++);
32
30
}
33
There are also two more SoCs, NPCM710 and NPCM705, which are single-core
31
g_string_append_printf(s,
32
"<reg name=\"ffr\" bitsize=\"%d\""
33
" regnum=\"%d\" group=\"vector\""
34
" type=\"svep\"/>",
35
- cpu->sve_max_vq * 16, base_reg++);
36
+ pred_width, base_reg++);
37
38
/* Define the vector length pseudo-register. */
39
g_string_append_printf(s,
34
--
40
--
35
2.20.1
41
2.34.1
36
42
37
43
diff view generated by jsdifflib
[PULL 19/24] target/arm: Implement MVE VSHLC
[PULL 07/21] target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
1
Implement the MVE VSHLC insn, which performs a shift left of the
1
From: Richard Henderson <richard.henderson@linaro.org>
2
entire vector with carry in bits provided from a general purpose
3
register and carry out bits written back to that register.
4
2
3
Define svep based on the size of the predicates,
4
not the primary vector registers.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230227213329.793795-8-richard.henderson@linaro.org
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
8
---
10
---
9
target/arm/helper-mve.h | 2 ++
11
target/arm/gdbstub64.c | 2 +-
10
target/arm/mve.decode | 2 ++
12
1 file changed, 1 insertion(+), 1 deletion(-)
11
target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
13
4 files changed, 72 insertions(+)
14
13
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
14
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-mve.h
16
--- a/target/arm/gdbstub64.c
18
+++ b/target/arm/helper-mve.h
17
+++ b/target/arm/gdbstub64.c
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
18
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
20
DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
/* Create the predicate vector type. */
21
DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
g_string_append_printf(s,
22
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
23
+
22
- reg_width / 8);
24
+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
23
+ pred_width / 8);
25
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
24
26
index XXXXXXX..XXXXXXX 100644
25
/* Define the vector registers. */
27
--- a/target/arm/mve.decode
26
for (i = 0; i < 32; i++) {
28
+++ b/target/arm/mve.decode
29
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
30
VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
31
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
32
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
33
+
34
+VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
35
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/mve_helper.c
38
+++ b/target/arm/mve_helper.c
39
@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
40
DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
41
DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
42
DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
43
+
44
+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
45
+ uint32_t shift)
46
+{
47
+ uint32_t *d = vd;
48
+ uint16_t mask = mve_element_mask(env);
49
+ unsigned e;
50
+ uint32_t r;
51
+
52
+ /*
53
+ * For each 32-bit element, we shift it left, bringing in the
54
+ * low 'shift' bits of rdm at the bottom. Bits shifted out at
55
+ * the top become the new rdm, if the predicate mask permits.
56
+ * The final rdm value is returned to update the register.
57
+ * shift == 0 here means "shift by 32 bits".
58
+ */
59
+ if (shift == 0) {
60
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
61
+ r = rdm;
62
+ if (mask & 1) {
63
+ rdm = d[H4(e)];
64
+ }
65
+ mergemask(&d[H4(e)], r, mask);
66
+ }
67
+ } else {
68
+ uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
69
+
70
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
71
+ r = (d[H4(e)] << shift) | (rdm & shiftmask);
72
+ if (mask & 1) {
73
+ rdm = d[H4(e)] >> (32 - shift);
74
+ }
75
+ mergemask(&d[H4(e)], r, mask);
76
+ }
77
+ }
78
+ mve_advance_vpt(env);
79
+ return rdm;
80
+}
81
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/translate-mve.c
84
+++ b/target/arm/translate-mve.c
85
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
86
DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
87
DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
88
DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
89
+
90
+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
91
+{
92
+ /*
93
+ * Whole Vector Left Shift with Carry. The carry is taken
94
+ * from a general purpose register and written back there.
95
+ * An imm of 0 means "shift by 32".
96
+ */
97
+ TCGv_ptr qd;
98
+ TCGv_i32 rdm;
99
+
100
+ if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
101
+ return false;
102
+ }
103
+ if (a->rdm == 13 || a->rdm == 15) {
104
+ /* CONSTRAINED UNPREDICTABLE: we UNDEF */
105
+ return false;
106
+ }
107
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
108
+ return true;
109
+ }
110
+
111
+ qd = mve_qreg_ptr(a->qd);
112
+ rdm = load_reg(s, a->rdm);
113
+ gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
114
+ store_reg(s, a->rdm, rdm);
115
+ tcg_temp_free_ptr(qd);
116
+ mve_update_eci(s);
117
+ return true;
118
+}
119
--
27
--
120
2.20.1
28
2.34.1
121
122
diff view generated by jsdifflib
[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
[PULL 08/21] target/arm: Add name argument to output_vector_union_type
1
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
do_urshr() is borrowed from sve_helper.c.
3
This will make the function usable between SVE and SME.
4
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230227213329.793795-9-richard.henderson@linaro.org
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
8
---
10
---
9
target/arm/helper-mve.h | 10 ++++++++++
11
target/arm/gdbstub64.c | 28 ++++++++++++++--------------
10
target/arm/mve.decode | 11 +++++++++++
12
1 file changed, 14 insertions(+), 14 deletions(-)
11
target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 15 ++++++++++++++
13
4 files changed, 76 insertions(+)
14
13
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
14
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-mve.h
16
--- a/target/arm/gdbstub64.c
18
+++ b/target/arm/helper-mve.h
17
+++ b/target/arm/gdbstub64.c
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
18
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
20
DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
return 0;
21
DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
}
22
DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
22
-static void output_vector_union_type(GString *s, int reg_width)
23
+static void output_vector_union_type(GString *s, int reg_width,
24
+ const char *name)
25
{
26
struct TypeSize {
27
const char *gdb_type;
28
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
29
};
30
31
static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
32
-
33
- g_autoptr(GString) ts = g_string_new("");
34
int i, j, bits;
35
36
/* First define types and totals in a whole VL */
37
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
38
- int count = reg_width / vec_lanes[i].size;
39
- g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
40
g_string_append_printf(s,
41
- "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
42
- ts->str, vec_lanes[i].gdb_type, count);
43
+ "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",
44
+ name, vec_lanes[i].sz, vec_lanes[i].suffix,
45
+ vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);
46
}
23
+
47
+
24
+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
/*
25
+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
* Now define a union for each size group containing unsigned and
26
+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
50
* signed and potentially float versions of each size from 128 to
27
+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
* 8 bits.
52
*/
53
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
54
- g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
55
+ g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
56
for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
57
if (vec_lanes[j].size == bits) {
58
- g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
59
- vec_lanes[j].suffix,
60
+ g_string_append_printf(s, "<field name=\"%c\" type=\"%s%c%c\"/>",
61
+ vec_lanes[j].suffix, name,
62
vec_lanes[j].sz, vec_lanes[j].suffix);
63
}
64
}
65
g_string_append(s, "</union>");
66
}
28
+
67
+
29
+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
68
/* And now the final union of unions */
30
+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
69
- g_string_append(s, "<union id=\"svev\">");
31
+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
70
+ g_string_append_printf(s, "<union id=\"%s\">", name);
32
+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
71
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
72
- g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
34
index XXXXXXX..XXXXXXX 100644
73
- suf[i], suf[i]);
35
--- a/target/arm/mve.decode
74
+ g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
36
+++ b/target/arm/mve.decode
75
+ suf[i], name, suf[i]);
37
@@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
76
}
38
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
77
g_string_append(s, "</union>");
39
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
78
}
40
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
79
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
41
+
80
g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
42
+# Narrowing shifts (which only support b and h sizes)
81
43
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
82
/* Create the vector union type. */
44
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
83
- output_vector_union_type(s, reg_width);
45
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
84
+ output_vector_union_type(s, reg_width, "svev");
46
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
85
47
+
86
/* Create the predicate vector type. */
48
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
87
g_string_append_printf(s,
49
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
50
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
51
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
52
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/mve_helper.c
55
+++ b/target/arm/mve_helper.c
56
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
57
58
DO_VSHLL_ALL(vshllb, false)
59
DO_VSHLL_ALL(vshllt, true)
60
+
61
+/*
62
+ * Narrowing right shifts, taking a double sized input, shifting it
63
+ * and putting the result in either the top or bottom half of the output.
64
+ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
65
+ */
66
+#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
67
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
68
+ void *vm, uint32_t shift) \
69
+ { \
70
+ LTYPE *m = vm; \
71
+ TYPE *d = vd; \
72
+ uint16_t mask = mve_element_mask(env); \
73
+ unsigned le; \
74
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
75
+ TYPE r = FN(m[H##LESIZE(le)], shift); \
76
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
77
+ } \
78
+ mve_advance_vpt(env); \
79
+ }
80
+
81
+#define DO_VSHRN_ALL(OP, FN) \
82
+ DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \
83
+ DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \
84
+ DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \
85
+ DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
86
+
87
+static inline uint64_t do_urshr(uint64_t x, unsigned sh)
88
+{
89
+ if (likely(sh < 64)) {
90
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
91
+ } else if (sh == 64) {
92
+ return x >> 63;
93
+ } else {
94
+ return 0;
95
+ }
96
+}
97
+
98
+DO_VSHRN_ALL(vshrn, DO_SHR)
99
+DO_VSHRN_ALL(vrshrn, do_urshr)
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
105
DO_VSHLL(VSHLL_BU, vshllbu)
106
DO_VSHLL(VSHLL_TS, vshllts)
107
DO_VSHLL(VSHLL_TU, vshlltu)
108
+
109
+#define DO_2SHIFT_N(INSN, FN) \
110
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
111
+ { \
112
+ static MVEGenTwoOpShiftFn * const fns[] = { \
113
+ gen_helper_mve_##FN##b, \
114
+ gen_helper_mve_##FN##h, \
115
+ }; \
116
+ return do_2shift(s, a, fns[a->size], false); \
117
+ }
118
+
119
+DO_2SHIFT_N(VSHRNB, vshrnb)
120
+DO_2SHIFT_N(VSHRNT, vshrnt)
121
+DO_2SHIFT_N(VRSHRNB, vrshrnb)
122
+DO_2SHIFT_N(VRSHRNT, vrshrnt)
123
--
88
--
124
2.20.1
89
2.34.1
125
90
126
91
diff view generated by jsdifflib
[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
[PULL 09/21] target/arm: Simplify iteration over bit widths
1
Implement the MVE VSRI and VSLI insns, which perform a
1
From: Richard Henderson <richard.henderson@linaro.org>
2
shift-and-insert operation.
3
2
3
Order suf[] by the log8 of the width.
4
Use ARRAY_SIZE instead of hard-coding 128.
5
6
This changes the order of the union definitions,
7
but retains the order of the union-of-union members.
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20230227213329.793795-10-richard.henderson@linaro.org
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
7
---
13
---
8
target/arm/helper-mve.h | 8 ++++++++
14
target/arm/gdbstub64.c | 10 ++++++----
9
target/arm/mve.decode | 9 ++++++++
15
1 file changed, 6 insertions(+), 4 deletions(-)
10
target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++
11
target/arm/translate-mve.c | 3 +++
12
4 files changed, 62 insertions(+)
13
16
14
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
17
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper-mve.h
19
--- a/target/arm/gdbstub64.c
17
+++ b/target/arm/helper-mve.h
20
+++ b/target/arm/gdbstub64.c
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
19
DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
{ "int8", 8, 'b', 's' },
20
DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
};
21
DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
25
- static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
26
- int i, j, bits;
27
+ static const char suf[] = { 'b', 'h', 's', 'd', 'q' };
28
+ int i, j;
29
30
/* First define types and totals in a whole VL */
31
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
32
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
33
* signed and potentially float versions of each size from 128 to
34
* 8 bits.
35
*/
36
- for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
37
+ for (i = 0; i < ARRAY_SIZE(suf); i++) {
38
+ int bits = 8 << i;
22
+
39
+
23
+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
24
+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
25
+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
if (vec_lanes[j].size == bits) {
26
+
43
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
27
+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
28
+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
45
/* And now the final union of unions */
29
+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
46
g_string_append_printf(s, "<union id=\"%s\">", name);
30
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
47
- for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
31
index XXXXXXX..XXXXXXX 100644
48
+ for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {
32
--- a/target/arm/mve.decode
49
g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
33
+++ b/target/arm/mve.decode
50
suf[i], name, suf[i]);
34
@@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
51
}
35
36
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
37
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
38
+
39
+# Shift-and-insert
40
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
41
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
42
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
43
+
44
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
45
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
46
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
47
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/mve_helper.c
50
+++ b/target/arm/mve_helper.c
51
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
52
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
53
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
54
55
+/* Shift-and-insert; we always work with 64 bits at a time */
56
+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \
57
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
58
+ void *vm, uint32_t shift) \
59
+ { \
60
+ uint64_t *d = vd, *m = vm; \
61
+ uint16_t mask; \
62
+ uint64_t shiftmask; \
63
+ unsigned e; \
64
+ if (shift == 0 || shift == ESIZE * 8) { \
65
+ /* \
66
+ * Only VSLI can shift by 0; only VSRI can shift by <dt>. \
67
+ * The generic logic would give the right answer for 0 but \
68
+ * fails for <dt>. \
69
+ */ \
70
+ goto done; \
71
+ } \
72
+ assert(shift < ESIZE * 8); \
73
+ mask = mve_element_mask(env); \
74
+ /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \
75
+ shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \
76
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
77
+ uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \
78
+ (d[H8(e)] & ~shiftmask); \
79
+ mergemask(&d[H8(e)], r, mask); \
80
+ } \
81
+done: \
82
+ mve_advance_vpt(env); \
83
+ }
84
+
85
+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
86
+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
87
+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
88
+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
89
+
90
+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
91
+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
92
+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
93
+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
94
+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
95
+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
96
+
97
/*
98
* Long shifts taking half-sized inputs from top or bottom of the input
99
* vector and producing a double-width result. ESIZE, TYPE are for
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
105
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
106
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
107
108
+DO_2SHIFT(VSRI, vsri, false)
109
+DO_2SHIFT(VSLI, vsli, false)
110
+
111
#define DO_VSHLL(INSN, FN) \
112
static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
113
{ \
114
--
52
--
115
2.20.1
53
2.34.1
116
117
diff view generated by jsdifflib
[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
[PULL 10/21] target/arm: Create pauth_ptr_mask
1
Implement the MVE vector shift right by immediate insns VSHRI and
1
From: Richard Henderson <richard.henderson@linaro.org>
2
VRSHRI. As with Neon, we implement these by using helper functions
3
which perform left shifts but allow negative shift counts to indicate
4
right shifts.
5
2
3
Keep the logic for pauth within pauth_helper.c, and expose
4
a helper function for use with the gdbstub pac extension.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230227213329.793795-11-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
9
---
10
---
10
target/arm/helper-mve.h | 12 ++++++++++++
11
target/arm/internals.h | 10 ++++++++++
11
target/arm/translate.h | 20 ++++++++++++++++++++
12
target/arm/tcg/pauth_helper.c | 26 ++++++++++++++++++++++----
12
target/arm/mve.decode | 28 ++++++++++++++++++++++++++++
13
2 files changed, 32 insertions(+), 4 deletions(-)
13
target/arm/mve_helper.c | 7 +++++++
14
target/arm/translate-mve.c | 5 +++++
15
target/arm/translate-neon.c | 18 ------------------
16
6 files changed, 72 insertions(+), 18 deletions(-)
17
14
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
15
diff --git a/target/arm/internals.h b/target/arm/internals.h
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper-mve.h
17
--- a/target/arm/internals.h
21
+++ b/target/arm/helper-mve.h
18
+++ b/target/arm/internals.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
19
@@ -XXX,XX +XXX,XX @@ int exception_target_el(CPUARMState *env);
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
20
bool arm_singlestep_active(CPUARMState *env);
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
21
bool arm_generate_debug_exceptions(CPUARMState *env);
25
22
26
+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+/**
27
+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+ * pauth_ptr_mask:
28
+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
+ * @env: cpu context
26
+ * @ptr: selects between TTBR0 and TTBR1
27
+ * @data: selects between TBI and TBID
28
+ *
29
+ * Return a mask of the bits of @ptr that contain the authentication code.
30
+ */
31
+uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data);
29
+
32
+
30
DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
/* Add the cpreg definitions for debug related system registers */
31
DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
void define_debug_regs(ARMCPU *cpu);
32
DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
33
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c
34
DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+
42
+DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
45
diff --git a/target/arm/translate.h b/target/arm/translate.h
46
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/translate.h
38
--- a/target/arm/tcg/pauth_helper.c
48
+++ b/target/arm/translate.h
39
+++ b/target/arm/tcg/pauth_helper.c
49
@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
40
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
50
return x * 2 + 1;
41
return pac | ext | ptr;
51
}
42
}
52
43
53
+static inline int rsub_64(DisasContext *s, int x)
44
-static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
54
+{
45
+static uint64_t pauth_ptr_mask_internal(ARMVAParameters param)
55
+ return 64 - x;
46
{
47
- /* Note that bit 55 is used whether or not the regime has 2 ranges. */
48
- uint64_t extfield = sextract64(ptr, 55, 1);
49
int bot_pac_bit = 64 - param.tsz;
50
int top_pac_bit = 64 - 8 * param.tbi;
51
52
- return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield);
53
+ return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);
56
+}
54
+}
57
+
55
+
58
+static inline int rsub_32(DisasContext *s, int x)
56
+static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
59
+{
57
+{
60
+ return 32 - x;
58
+ uint64_t mask = pauth_ptr_mask_internal(param);
59
+
60
+ /* Note that bit 55 is used whether or not the regime has 2 ranges. */
61
+ if (extract64(ptr, 55, 1)) {
62
+ return ptr | mask;
63
+ } else {
64
+ return ptr & ~mask;
65
+ }
61
+}
66
+}
62
+
67
+
63
+static inline int rsub_16(DisasContext *s, int x)
68
+uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data)
64
+{
69
+{
65
+ return 16 - x;
70
+ ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
66
+}
71
+ ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
67
+
72
+
68
+static inline int rsub_8(DisasContext *s, int x)
73
+ return pauth_ptr_mask_internal(param);
69
+{
70
+ return 8 - x;
71
+}
72
+
73
static inline int arm_dc_feature(DisasContext *dc, int feature)
74
{
75
return (dc->features & (1ULL << feature)) != 0;
76
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/mve.decode
79
+++ b/target/arm/mve.decode
80
@@ -XXX,XX +XXX,XX @@
81
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
82
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
83
84
+# Right shifts are encoded as N - shift, where N is the element size in bits.
85
+%rshift_i5 16:5 !function=rsub_32
86
+%rshift_i4 16:4 !function=rsub_16
87
+%rshift_i3 16:3 !function=rsub_8
88
+
89
+@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
90
+ size=0 shift=%rshift_i3
91
+@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
92
+ size=1 shift=%rshift_i4
93
+@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
94
+ size=2 shift=%rshift_i5
95
+
96
# Vector loads and stores
97
98
# Widening loads and narrowing stores:
99
@@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
100
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
101
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
102
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
103
+
104
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
105
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
106
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
107
+
108
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
109
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
110
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
111
+
112
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
113
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
114
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
115
+
116
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
117
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
118
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
119
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/arm/mve_helper.c
122
+++ b/target/arm/mve_helper.c
123
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
124
DO_2SHIFT(OP##b, 1, uint8_t, FN) \
125
DO_2SHIFT(OP##h, 2, uint16_t, FN) \
126
DO_2SHIFT(OP##w, 4, uint32_t, FN)
127
+#define DO_2SHIFT_S(OP, FN) \
128
+ DO_2SHIFT(OP##b, 1, int8_t, FN) \
129
+ DO_2SHIFT(OP##h, 2, int16_t, FN) \
130
+ DO_2SHIFT(OP##w, 4, int32_t, FN)
131
132
#define DO_2SHIFT_SAT_U(OP, FN) \
133
DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
134
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
135
DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
136
137
DO_2SHIFT_U(vshli_u, DO_VSHLU)
138
+DO_2SHIFT_S(vshli_s, DO_VSHLS)
139
DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
140
DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
141
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
142
+DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
143
+DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
144
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
145
index XXXXXXX..XXXXXXX 100644
146
--- a/target/arm/translate-mve.c
147
+++ b/target/arm/translate-mve.c
148
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
149
DO_2SHIFT(VQSHLI_S, vqshli_s, false)
150
DO_2SHIFT(VQSHLI_U, vqshli_u, false)
151
DO_2SHIFT(VQSHLUI, vqshlui_s, false)
152
+/* These right shifts use a left-shift helper with negated shift count */
153
+DO_2SHIFT(VSHRI_S, vshli_s, true)
154
+DO_2SHIFT(VSHRI_U, vshli_u, true)
155
+DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
+DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/target/arm/translate-neon.c
160
+++ b/target/arm/translate-neon.c
161
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
162
return x + 1;
163
}
74
}
164
75
165
-static inline int rsub_64(DisasContext *s, int x)
76
static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
166
-{
167
- return 64 - x;
168
-}
169
-
170
-static inline int rsub_32(DisasContext *s, int x)
171
-{
172
- return 32 - x;
173
-}
174
-static inline int rsub_16(DisasContext *s, int x)
175
-{
176
- return 16 - x;
177
-}
178
-static inline int rsub_8(DisasContext *s, int x)
179
-{
180
- return 8 - x;
181
-}
182
-
183
static inline int neon_3same_fp_size(DisasContext *s, int x)
184
{
185
/* Convert 0==fp32, 1==fp16 into a MO_* value */
186
--
77
--
187
2.20.1
78
2.34.1
188
189
diff view generated by jsdifflib
[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
[PULL 11/21] target/arm: Implement gdbstub pauth extension
1
Implement the MVE saturating shift-right-and-narrow insns
1
From: Richard Henderson <richard.henderson@linaro.org>
2
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
3
2
4
do_srshr() is borrowed from sve_helper.c.
3
The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK
4
ptrace register set.
5
5
6
The original gdb feature consists of two masks, data and code, which are
7
used to mask out the authentication code within a pointer. Following
8
discussion with Luis Machado, add two more masks in order to support
9
pointers within the high half of the address space (i.e. TTBR1 vs TTBR0).
10
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20230227213329.793795-12-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
9
---
16
---
10
target/arm/helper-mve.h | 30 +++++++++++
17
configs/targets/aarch64-linux-user.mak | 2 +-
11
target/arm/mve.decode | 28 ++++++++++
18
configs/targets/aarch64-softmmu.mak | 2 +-
12
target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++
19
configs/targets/aarch64_be-linux-user.mak | 2 +-
13
target/arm/translate-mve.c | 12 +++++
20
target/arm/internals.h | 2 ++
14
4 files changed, 174 insertions(+)
21
target/arm/gdbstub.c | 5 ++++
22
target/arm/gdbstub64.c | 34 +++++++++++++++++++++++
23
gdb-xml/aarch64-pauth.xml | 15 ++++++++++
24
7 files changed, 59 insertions(+), 3 deletions(-)
25
create mode 100644 gdb-xml/aarch64-pauth.xml
15
26
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
27
diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak
17
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-mve.h
29
--- a/configs/targets/aarch64-linux-user.mak
19
+++ b/target/arm/helper-mve.h
30
+++ b/configs/targets/aarch64-linux-user.mak
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
@@ -XXX,XX +XXX,XX @@
21
DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
TARGET_ARCH=aarch64
22
DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
TARGET_BASE_ARCH=arm
23
DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
24
+
35
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
25
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
TARGET_HAS_BFLT=y
26
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
CONFIG_SEMIHOSTING=y
27
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
28
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
+
35
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+
40
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+
45
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
46
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
+
50
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
53
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
54
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
55
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/mve.decode
41
--- a/configs/targets/aarch64-softmmu.mak
57
+++ b/target/arm/mve.decode
42
+++ b/configs/targets/aarch64-softmmu.mak
58
@@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
43
@@ -XXX,XX +XXX,XX @@
59
VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
44
TARGET_ARCH=aarch64
60
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
45
TARGET_BASE_ARCH=arm
61
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
46
TARGET_SUPPORTS_MTTCG=y
62
+
47
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml
63
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
48
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml
64
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
49
TARGET_NEED_FDT=y
65
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
50
diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak
66
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
67
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
68
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
69
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
70
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
71
+
72
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
73
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
74
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
75
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
76
+
77
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
78
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
79
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
80
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
81
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
82
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
83
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
84
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
85
+
86
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
87
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
88
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
89
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
90
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
91
index XXXXXXX..XXXXXXX 100644
51
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/mve_helper.c
52
--- a/configs/targets/aarch64_be-linux-user.mak
93
+++ b/target/arm/mve_helper.c
53
+++ b/configs/targets/aarch64_be-linux-user.mak
94
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
54
@@ -XXX,XX +XXX,XX @@
95
}
55
TARGET_ARCH=aarch64
56
TARGET_BASE_ARCH=arm
57
TARGET_BIG_ENDIAN=y
58
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
59
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
60
TARGET_HAS_BFLT=y
61
CONFIG_SEMIHOSTING=y
62
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
63
diff --git a/target/arm/internals.h b/target/arm/internals.h
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/internals.h
66
+++ b/target/arm/internals.h
67
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
68
int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
69
int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
70
int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
71
+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);
72
+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);
73
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
74
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
75
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
76
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/gdbstub.c
79
+++ b/target/arm/gdbstub.c
80
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
81
aarch64_gdb_set_fpu_reg,
82
34, "aarch64-fpu.xml", 0);
83
}
84
+ if (isar_feature_aa64_pauth(&cpu->isar)) {
85
+ gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
86
+ aarch64_gdb_set_pauth_reg,
87
+ 4, "aarch64-pauth.xml", 0);
88
+ }
89
#endif
90
} else {
91
if (arm_feature(env, ARM_FEATURE_NEON)) {
92
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/target/arm/gdbstub64.c
95
+++ b/target/arm/gdbstub64.c
96
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
97
return 0;
96
}
98
}
97
99
98
+static inline int64_t do_srshr(int64_t x, unsigned sh)
100
+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
99
+{
101
+{
100
+ if (likely(sh < 64)) {
102
+ switch (reg) {
101
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
103
+ case 0: /* pauth_dmask */
102
+ } else {
104
+ case 1: /* pauth_cmask */
103
+ /* Rounding the sign bit always produces 0. */
105
+ case 2: /* pauth_dmask_high */
106
+ case 3: /* pauth_cmask_high */
107
+ /*
108
+ * Note that older versions of this feature only contained
109
+ * pauth_{d,c}mask, for use with Linux user processes, and
110
+ * thus exclusively in the low half of the address space.
111
+ *
112
+ * To support system mode, and to debug kernels, two new regs
113
+ * were added to cover the high half of the address space.
114
+ * For the purpose of pauth_ptr_mask, we can use any well-formed
115
+ * address within the address space half -- here, 0 and -1.
116
+ */
117
+ {
118
+ bool is_data = !(reg & 1);
119
+ bool is_high = reg & 2;
120
+ uint64_t mask = pauth_ptr_mask(env, -is_high, is_data);
121
+ return gdb_get_reg64(buf, mask);
122
+ }
123
+ default:
104
+ return 0;
124
+ return 0;
105
+ }
125
+ }
106
+}
126
+}
107
+
127
+
108
DO_VSHRN_ALL(vshrn, DO_SHR)
128
+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)
109
DO_VSHRN_ALL(vrshrn, do_urshr)
110
+
111
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
112
+ bool *satp)
113
+{
129
+{
114
+ if (val > max) {
130
+ /* All pseudo registers are read-only. */
115
+ *satp = true;
131
+ return 0;
116
+ return max;
117
+ } else if (val < min) {
118
+ *satp = true;
119
+ return min;
120
+ } else {
121
+ return val;
122
+ }
123
+}
132
+}
124
+
133
+
125
+/* Saturating narrowing right shifts */
134
static void output_vector_union_type(GString *s, int reg_width,
126
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
135
const char *name)
127
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
136
{
128
+ void *vm, uint32_t shift) \
137
diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml
129
+ { \
138
new file mode 100644
130
+ LTYPE *m = vm; \
139
index XXXXXXX..XXXXXXX
131
+ TYPE *d = vd; \
140
--- /dev/null
132
+ uint16_t mask = mve_element_mask(env); \
141
+++ b/gdb-xml/aarch64-pauth.xml
133
+ bool qc = false; \
142
@@ -XXX,XX +XXX,XX @@
134
+ unsigned le; \
143
+<?xml version="1.0"?>
135
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
144
+<!-- Copyright (C) 2018-2022 Free Software Foundation, Inc.
136
+ bool sat = false; \
137
+ TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \
138
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
139
+ qc |= sat && (mask & 1 << (TOP * ESIZE)); \
140
+ } \
141
+ if (qc) { \
142
+ env->vfp.qc[0] = qc; \
143
+ } \
144
+ mve_advance_vpt(env); \
145
+ }
146
+
145
+
147
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \
146
+ Copying and distribution of this file, with or without modification,
148
+ DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \
147
+ are permitted in any medium without royalty provided the copyright
149
+ DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
148
+ notice and this notice are preserved. -->
150
+
149
+
151
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \
150
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
152
+ DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \
151
+<feature name="org.gnu.gdb.aarch64.pauth">
153
+ DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
152
+ <reg name="pauth_dmask" bitsize="64"/>
153
+ <reg name="pauth_cmask" bitsize="64"/>
154
+ <reg name="pauth_dmask_high" bitsize="64"/>
155
+ <reg name="pauth_cmask_high" bitsize="64"/>
156
+</feature>
154
+
157
+
155
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \
156
+ DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \
157
+ DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
158
+
159
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \
160
+ DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \
161
+ DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
162
+
163
+#define DO_SHRN_SB(N, M, SATP) \
164
+ do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
165
+#define DO_SHRN_UB(N, M, SATP) \
166
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
167
+#define DO_SHRUN_B(N, M, SATP) \
168
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
169
+
170
+#define DO_SHRN_SH(N, M, SATP) \
171
+ do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
172
+#define DO_SHRN_UH(N, M, SATP) \
173
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
174
+#define DO_SHRUN_H(N, M, SATP) \
175
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
176
+
177
+#define DO_RSHRN_SB(N, M, SATP) \
178
+ do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
179
+#define DO_RSHRN_UB(N, M, SATP) \
180
+ do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
181
+#define DO_RSHRUN_B(N, M, SATP) \
182
+ do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
183
+
184
+#define DO_RSHRN_SH(N, M, SATP) \
185
+ do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
186
+#define DO_RSHRN_UH(N, M, SATP) \
187
+ do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
188
+#define DO_RSHRUN_H(N, M, SATP) \
189
+ do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
190
+
191
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
192
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
193
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
194
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
195
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
196
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
197
+
198
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
199
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
200
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
201
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
202
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
203
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
204
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
205
index XXXXXXX..XXXXXXX 100644
206
--- a/target/arm/translate-mve.c
207
+++ b/target/arm/translate-mve.c
208
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
209
DO_2SHIFT_N(VSHRNT, vshrnt)
210
DO_2SHIFT_N(VRSHRNB, vrshrnb)
211
DO_2SHIFT_N(VRSHRNT, vrshrnt)
212
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
213
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
214
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
215
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
216
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
217
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
218
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
219
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
220
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
221
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
222
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
223
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
224
--
158
--
225
2.20.1
159
2.34.1
226
227
diff view generated by jsdifflib
[PULL 03/24] hw/arm: Add basic power management to raspi.
[PULL 12/21] target/arm: Export arm_v7m_mrs_control
1
From: Nolan Leake <nolan@sigbus.net>
1
From: David Reiss <dreiss@meta.com>
2
2
3
This is just enough to make reboot and poweroff work. Works for
3
Allow the function to be used outside of m_helper.c.
4
linux, u-boot, and the arm trusted firmware. Not tested, but should
4
Rename with an "arm_" prefix.
5
work for plan9, and bare-metal/hobby OSes, since they seem to generally
6
do what linux does for reset.
7
5
8
The watchdog timer functionality is not yet implemented.
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
8
Signed-off-by: David Reiss <dreiss@meta.com>
11
Signed-off-by: Nolan Leake <nolan@sigbus.net>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20230227213329.793795-13-richard.henderson@linaro.org
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
[rth: Split out of a larger patch]
14
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
[PMM: tweaked commit title; fixed region size to 0x200;
16
moved header file to include/]
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
14
---
19
include/hw/arm/bcm2835_peripherals.h | 3 +-
15
target/arm/internals.h | 3 +++
20
include/hw/misc/bcm2835_powermgt.h | 29 +++++
16
target/arm/tcg/m_helper.c | 6 +++---
21
hw/arm/bcm2835_peripherals.c | 13 ++-
17
2 files changed, 6 insertions(+), 3 deletions(-)
22
hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++
23
hw/misc/meson.build | 1 +
24
5 files changed, 204 insertions(+), 2 deletions(-)
25
create mode 100644 include/hw/misc/bcm2835_powermgt.h
26
create mode 100644 hw/misc/bcm2835_powermgt.c
27
18
28
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
29
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/bcm2835_peripherals.h
21
--- a/target/arm/internals.h
31
+++ b/include/hw/arm/bcm2835_peripherals.h
22
+++ b/target/arm/internals.h
32
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
33
#include "hw/misc/bcm2835_mphi.h"
24
void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
34
#include "hw/misc/bcm2835_thermal.h"
25
#endif
35
#include "hw/misc/bcm2835_cprman.h"
26
36
+#include "hw/misc/bcm2835_powermgt.h"
27
+/* Read the CONTROL register as the MRS instruction would. */
37
#include "hw/sd/sdhci.h"
28
+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
38
#include "hw/sd/bcm2835_sdhost.h"
39
#include "hw/gpio/bcm2835_gpio.h"
40
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
41
BCM2835MphiState mphi;
42
UnimplementedDeviceState txp;
43
UnimplementedDeviceState armtmr;
44
- UnimplementedDeviceState powermgt;
45
+ BCM2835PowerMgtState powermgt;
46
BCM2835CprmanState cprman;
47
PL011State uart0;
48
BCM2835AuxState aux;
49
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
50
new file mode 100644
51
index XXXXXXX..XXXXXXX
52
--- /dev/null
53
+++ b/include/hw/misc/bcm2835_powermgt.h
54
@@ -XXX,XX +XXX,XX @@
55
+/*
56
+ * BCM2835 Power Management emulation
57
+ *
58
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
59
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
60
+ *
61
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
62
+ * See the COPYING file in the top-level directory.
63
+ */
64
+
29
+
65
+#ifndef BCM2835_POWERMGT_H
30
#ifdef CONFIG_USER_ONLY
66
+#define BCM2835_POWERMGT_H
31
static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
67
+
32
#else
68
+#include "hw/sysbus.h"
33
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
69
+#include "qom/object.h"
70
+
71
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
72
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
73
+
74
+struct BCM2835PowerMgtState {
75
+ SysBusDevice busdev;
76
+ MemoryRegion iomem;
77
+
78
+ uint32_t rstc;
79
+ uint32_t rsts;
80
+ uint32_t wdog;
81
+};
82
+
83
+#endif
84
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
85
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/arm/bcm2835_peripherals.c
35
--- a/target/arm/tcg/m_helper.c
87
+++ b/hw/arm/bcm2835_peripherals.c
36
+++ b/target/arm/tcg/m_helper.c
88
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
37
@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el)
89
38
return xpsr_read(env) & mask;
90
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
91
OBJECT(&s->gpu_bus_mr));
92
+
93
+ /* Power Management */
94
+ object_initialize_child(obj, "powermgt", &s->powermgt,
95
+ TYPE_BCM2835_POWERMGT);
96
}
39
}
97
40
98
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
41
-static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure)
99
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
42
+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure)
100
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
43
{
101
INTERRUPT_USB));
44
uint32_t value = env->v7m.control[secure];
102
45
103
+ /* Power Management */
46
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
104
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
47
case 0 ... 7: /* xPSR sub-fields */
105
+ return;
48
return v7m_mrs_xpsr(env, reg, 0);
106
+ }
49
case 20: /* CONTROL */
107
+
50
- return v7m_mrs_control(env, 0);
108
+ memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
51
+ return arm_v7m_mrs_control(env, 0);
109
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
52
default:
110
+
53
/* Unprivileged reads others as zero. */
111
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
54
return 0;
112
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
55
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
113
- create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
56
case 0 ... 7: /* xPSR sub-fields */
114
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
57
return v7m_mrs_xpsr(env, reg, el);
115
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
58
case 20: /* CONTROL */
116
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
59
- return v7m_mrs_control(env, env->v7m.secure);
117
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
60
+ return arm_v7m_mrs_control(env, env->v7m.secure);
118
new file mode 100644
61
case 0x94: /* CONTROL_NS */
119
index XXXXXXX..XXXXXXX
62
/*
120
--- /dev/null
63
* We have to handle this here because unprivileged Secure code
121
+++ b/hw/misc/bcm2835_powermgt.c
122
@@ -XXX,XX +XXX,XX @@
123
+/*
124
+ * BCM2835 Power Management emulation
125
+ *
126
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
127
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
128
+ *
129
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
130
+ * See the COPYING file in the top-level directory.
131
+ */
132
+
133
+#include "qemu/osdep.h"
134
+#include "qemu/log.h"
135
+#include "qemu/module.h"
136
+#include "hw/misc/bcm2835_powermgt.h"
137
+#include "migration/vmstate.h"
138
+#include "sysemu/runstate.h"
139
+
140
+#define PASSWORD 0x5a000000
141
+#define PASSWORD_MASK 0xff000000
142
+
143
+#define R_RSTC 0x1c
144
+#define V_RSTC_RESET 0x20
145
+#define R_RSTS 0x20
146
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
147
+#define R_WDOG 0x24
148
+
149
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
150
+ unsigned size)
151
+{
152
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
153
+ uint32_t res = 0;
154
+
155
+ switch (offset) {
156
+ case R_RSTC:
157
+ res = s->rstc;
158
+ break;
159
+ case R_RSTS:
160
+ res = s->rsts;
161
+ break;
162
+ case R_WDOG:
163
+ res = s->wdog;
164
+ break;
165
+
166
+ default:
167
+ qemu_log_mask(LOG_UNIMP,
168
+ "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
169
+ "\n", offset);
170
+ res = 0;
171
+ break;
172
+ }
173
+
174
+ return res;
175
+}
176
+
177
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
178
+ uint64_t value, unsigned size)
179
+{
180
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
181
+
182
+ if ((value & PASSWORD_MASK) != PASSWORD) {
183
+ qemu_log_mask(LOG_GUEST_ERROR,
184
+ "bcm2835_powermgt_write: Bad password 0x%"PRIx64
185
+ " at offset 0x%08"HWADDR_PRIx"\n",
186
+ value, offset);
187
+ return;
188
+ }
189
+
190
+ value = value & ~PASSWORD_MASK;
191
+
192
+ switch (offset) {
193
+ case R_RSTC:
194
+ s->rstc = value;
195
+ if (value & V_RSTC_RESET) {
196
+ if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
197
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
198
+ } else {
199
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
200
+ }
201
+ }
202
+ break;
203
+ case R_RSTS:
204
+ qemu_log_mask(LOG_UNIMP,
205
+ "bcm2835_powermgt_write: RSTS\n");
206
+ s->rsts = value;
207
+ break;
208
+ case R_WDOG:
209
+ qemu_log_mask(LOG_UNIMP,
210
+ "bcm2835_powermgt_write: WDOG\n");
211
+ s->wdog = value;
212
+ break;
213
+
214
+ default:
215
+ qemu_log_mask(LOG_UNIMP,
216
+ "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
217
+ "\n", offset);
218
+ break;
219
+ }
220
+}
221
+
222
+static const MemoryRegionOps bcm2835_powermgt_ops = {
223
+ .read = bcm2835_powermgt_read,
224
+ .write = bcm2835_powermgt_write,
225
+ .endianness = DEVICE_NATIVE_ENDIAN,
226
+ .impl.min_access_size = 4,
227
+ .impl.max_access_size = 4,
228
+};
229
+
230
+static const VMStateDescription vmstate_bcm2835_powermgt = {
231
+ .name = TYPE_BCM2835_POWERMGT,
232
+ .version_id = 1,
233
+ .minimum_version_id = 1,
234
+ .fields = (VMStateField[]) {
235
+ VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
236
+ VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
237
+ VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
238
+ VMSTATE_END_OF_LIST()
239
+ }
240
+};
241
+
242
+static void bcm2835_powermgt_init(Object *obj)
243
+{
244
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
245
+
246
+ memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
247
+ TYPE_BCM2835_POWERMGT, 0x200);
248
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
249
+}
250
+
251
+static void bcm2835_powermgt_reset(DeviceState *dev)
252
+{
253
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
254
+
255
+ /* https://elinux.org/BCM2835_registers#PM */
256
+ s->rstc = 0x00000102;
257
+ s->rsts = 0x00001000;
258
+ s->wdog = 0x00000000;
259
+}
260
+
261
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
262
+{
263
+ DeviceClass *dc = DEVICE_CLASS(klass);
264
+
265
+ dc->reset = bcm2835_powermgt_reset;
266
+ dc->vmsd = &vmstate_bcm2835_powermgt;
267
+}
268
+
269
+static TypeInfo bcm2835_powermgt_info = {
270
+ .name = TYPE_BCM2835_POWERMGT,
271
+ .parent = TYPE_SYS_BUS_DEVICE,
272
+ .instance_size = sizeof(BCM2835PowerMgtState),
273
+ .class_init = bcm2835_powermgt_class_init,
274
+ .instance_init = bcm2835_powermgt_init,
275
+};
276
+
277
+static void bcm2835_powermgt_register_types(void)
278
+{
279
+ type_register_static(&bcm2835_powermgt_info);
280
+}
281
+
282
+type_init(bcm2835_powermgt_register_types)
283
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
284
index XXXXXXX..XXXXXXX 100644
285
--- a/hw/misc/meson.build
286
+++ b/hw/misc/meson.build
287
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
288
'bcm2835_rng.c',
289
'bcm2835_thermal.c',
290
'bcm2835_cprman.c',
291
+ 'bcm2835_powermgt.c',
292
))
293
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
294
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
295
--
64
--
296
2.20.1
65
2.34.1
297
66
298
67
diff view generated by jsdifflib
[PULL 09/24] target/arm: Make asimd_imm_const() public
[PULL 13/21] target/arm: Export arm_v7m_get_sp_ptr
1
The function asimd_imm_const() in translate-neon.c is an
1
From: David Reiss <dreiss@meta.com>
2
implementation of the pseudocode AdvSIMDExpandImm(), which we will
3
also want for MVE. Move the implementation to translate.c, with a
4
prototype in translate.h.
5
2
3
Allow the function to be used outside of m_helper.c.
4
Move to be outside of ifndef CONFIG_USER_ONLY block.
5
Rename from get_v7m_sp_ptr.
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: David Reiss <dreiss@meta.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20230227213329.793795-14-richard.henderson@linaro.org
12
[rth: Split out of a larger patch]
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
9
---
15
---
10
target/arm/translate.h | 16 ++++++++++
16
target/arm/internals.h | 10 +++++
11
target/arm/translate-neon.c | 63 -------------------------------------
17
target/arm/tcg/m_helper.c | 84 +++++++++++++++++++--------------------
12
target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++
18
2 files changed, 51 insertions(+), 43 deletions(-)
13
3 files changed, 73 insertions(+), 63 deletions(-)
14
19
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
20
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.h
22
--- a/target/arm/internals.h
18
+++ b/target/arm/translate.h
23
+++ b/target/arm/internals.h
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
24
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
20
return opc | s->be_data;
25
/* Read the CONTROL register as the MRS instruction would. */
26
uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
27
28
+/*
29
+ * Return a pointer to the location where we currently store the
30
+ * stack pointer for the requested security state and thread mode.
31
+ * This pointer will become invalid if the CPU state is updated
32
+ * such that the stack pointers are switched around (eg changing
33
+ * the SPSEL control bit).
34
+ */
35
+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,
36
+ bool threadmode, bool spsel);
37
+
38
#ifdef CONFIG_USER_ONLY
39
static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
40
#else
41
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/tcg/m_helper.c
44
+++ b/target/arm/tcg/m_helper.c
45
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
46
arm_rebuild_hflags(env);
21
}
47
}
22
48
23
+/**
49
-static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
24
+ * asimd_imm_const: Expand an encoded SIMD constant value
50
- bool spsel)
25
+ *
26
+ * Expand a SIMD constant value. This is essentially the pseudocode
27
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
28
+ * VMVN and VBIC (when cmode < 14 && op == 1).
29
+ *
30
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
31
+ * callers must catch this.
32
+ *
33
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
34
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
35
+ * we produce an immediate constant value of 0 in these cases.
36
+ */
37
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
38
+
39
#endif /* TARGET_ARM_TRANSLATE_H */
40
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/translate-neon.c
43
+++ b/target/arm/translate-neon.c
44
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
45
DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
46
DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
47
48
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
49
-{
51
-{
50
- /*
52
- /*
51
- * Expand the encoded constant.
53
- * Return a pointer to the location where we currently store the
52
- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
54
- * stack pointer for the requested security state and thread mode.
53
- * We choose to not special-case this and will behave as if a
55
- * This pointer will become invalid if the CPU state is updated
54
- * valid constant encoding of 0 had been given.
56
- * such that the stack pointers are switched around (eg changing
55
- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
57
- * the SPSEL control bit).
58
- * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
59
- * Unlike that pseudocode, we require the caller to pass us in the
60
- * SPSEL control bit value; this is because we also use this
61
- * function in handling of pushing of the callee-saves registers
62
- * part of the v8M stack frame (pseudocode PushCalleeStack()),
63
- * and in the tailchain codepath the SPSEL bit comes from the exception
64
- * return magic LR value from the previous exception. The pseudocode
65
- * opencodes the stack-selection in PushCalleeStack(), but we prefer
66
- * to make this utility function generic enough to do the job.
56
- */
67
- */
57
- switch (cmode) {
68
- bool want_psp = threadmode && spsel;
58
- case 0: case 1:
59
- /* no-op */
60
- break;
61
- case 2: case 3:
62
- imm <<= 8;
63
- break;
64
- case 4: case 5:
65
- imm <<= 16;
66
- break;
67
- case 6: case 7:
68
- imm <<= 24;
69
- break;
70
- case 8: case 9:
71
- imm |= imm << 16;
72
- break;
73
- case 10: case 11:
74
- imm = (imm << 8) | (imm << 24);
75
- break;
76
- case 12:
77
- imm = (imm << 8) | 0xff;
78
- break;
79
- case 13:
80
- imm = (imm << 16) | 0xffff;
81
- break;
82
- case 14:
83
- if (op) {
84
- /*
85
- * This is the only case where the top and bottom 32 bits
86
- * of the encoded constant differ.
87
- */
88
- uint64_t imm64 = 0;
89
- int n;
90
-
69
-
91
- for (n = 0; n < 8; n++) {
70
- if (secure == env->v7m.secure) {
92
- if (imm & (1 << n)) {
71
- if (want_psp == v7m_using_psp(env)) {
93
- imm64 |= (0xffULL << (n * 8));
72
- return &env->regs[13];
94
- }
73
- } else {
95
- }
74
- return &env->v7m.other_sp;
96
- return imm64;
97
- }
75
- }
98
- imm |= (imm << 8) | (imm << 16) | (imm << 24);
76
- } else {
99
- break;
77
- if (want_psp) {
100
- case 15:
78
- return &env->v7m.other_ss_psp;
101
- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
79
- } else {
102
- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
80
- return &env->v7m.other_ss_msp;
103
- break;
81
- }
104
- }
82
- }
105
- if (op) {
106
- imm = ~imm;
107
- }
108
- return dup_const(MO_32, imm);
109
-}
83
-}
110
-
84
-
111
static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
85
static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
112
GVecGen2iFn *fn)
86
uint32_t *pvec)
113
{
87
{
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
88
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
115
index XXXXXXX..XXXXXXX 100644
89
!mode;
116
--- a/target/arm/translate.c
90
117
+++ b/target/arm/translate.c
91
mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv);
118
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
92
- frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode,
119
a64_translate_init();
93
- lr & R_V7M_EXCRET_SPSEL_MASK);
94
+ frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode,
95
+ lr & R_V7M_EXCRET_SPSEL_MASK);
96
want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK);
97
if (want_psp) {
98
limit = env->v7m.psplim[M_REG_S];
99
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
100
* use 'frame_sp_p' after we do something that makes it invalid.
101
*/
102
bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK;
103
- uint32_t *frame_sp_p = get_v7m_sp_ptr(env,
104
- return_to_secure,
105
- !return_to_handler,
106
- spsel);
107
+ uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure,
108
+ !return_to_handler, spsel);
109
uint32_t frameptr = *frame_sp_p;
110
bool pop_ok = true;
111
ARMMMUIdx mmu_idx;
112
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
113
threadmode = !arm_v7m_is_handler_mode(env);
114
spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
115
116
- frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
117
+ frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel);
118
frameptr = *frame_sp_p;
119
120
/*
121
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
120
}
122
}
121
123
122
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
124
#endif /* !CONFIG_USER_ONLY */
125
+
126
+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
127
+ bool spsel)
123
+{
128
+{
124
+ /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
129
+ /*
125
+ switch (cmode) {
130
+ * Return a pointer to the location where we currently store the
126
+ case 0: case 1:
131
+ * stack pointer for the requested security state and thread mode.
127
+ /* no-op */
132
+ * This pointer will become invalid if the CPU state is updated
128
+ break;
133
+ * such that the stack pointers are switched around (eg changing
129
+ case 2: case 3:
134
+ * the SPSEL control bit).
130
+ imm <<= 8;
135
+ * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
131
+ break;
136
+ * Unlike that pseudocode, we require the caller to pass us in the
132
+ case 4: case 5:
137
+ * SPSEL control bit value; this is because we also use this
133
+ imm <<= 16;
138
+ * function in handling of pushing of the callee-saves registers
134
+ break;
139
+ * part of the v8M stack frame (pseudocode PushCalleeStack()),
135
+ case 6: case 7:
140
+ * and in the tailchain codepath the SPSEL bit comes from the exception
136
+ imm <<= 24;
141
+ * return magic LR value from the previous exception. The pseudocode
137
+ break;
142
+ * opencodes the stack-selection in PushCalleeStack(), but we prefer
138
+ case 8: case 9:
143
+ * to make this utility function generic enough to do the job.
139
+ imm |= imm << 16;
144
+ */
140
+ break;
145
+ bool want_psp = threadmode && spsel;
141
+ case 10: case 11:
142
+ imm = (imm << 8) | (imm << 24);
143
+ break;
144
+ case 12:
145
+ imm = (imm << 8) | 0xff;
146
+ break;
147
+ case 13:
148
+ imm = (imm << 16) | 0xffff;
149
+ break;
150
+ case 14:
151
+ if (op) {
152
+ /*
153
+ * This is the only case where the top and bottom 32 bits
154
+ * of the encoded constant differ.
155
+ */
156
+ uint64_t imm64 = 0;
157
+ int n;
158
+
146
+
159
+ for (n = 0; n < 8; n++) {
147
+ if (secure == env->v7m.secure) {
160
+ if (imm & (1 << n)) {
148
+ if (want_psp == v7m_using_psp(env)) {
161
+ imm64 |= (0xffULL << (n * 8));
149
+ return &env->regs[13];
162
+ }
150
+ } else {
163
+ }
151
+ return &env->v7m.other_sp;
164
+ return imm64;
165
+ }
152
+ }
166
+ imm |= (imm << 8) | (imm << 16) | (imm << 24);
153
+ } else {
167
+ break;
154
+ if (want_psp) {
168
+ case 15:
155
+ return &env->v7m.other_ss_psp;
169
+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
156
+ } else {
170
+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
157
+ return &env->v7m.other_ss_msp;
171
+ break;
158
+ }
172
+ }
159
+ }
173
+ if (op) {
174
+ imm = ~imm;
175
+ }
176
+ return dup_const(MO_32, imm);
177
+}
160
+}
178
+
179
/* Generate a label used for skipping this instruction */
180
void arm_gen_condlabel(DisasContext *s)
181
{
182
--
161
--
183
2.20.1
162
2.34.1
184
163
185
164
diff view generated by jsdifflib
[PULL 20/24] target/arm: Implement MVE VADDLV
[PULL 14/21] target/arm: Implement gdbstub m-profile systemreg and secext
1
Implement the MVE VADDLV insn; this is similar to VADDV, except
1
From: Richard Henderson <richard.henderson@linaro.org>
2
that it accumulates 32-bit elements into a 64-bit accumulator
2
3
stored in a pair of general-purpose registers.
3
The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but
4
4
go ahead and implement the other system registers as well.
5
6
Since there is significant overlap between the two, implement
7
them with common code. The only exception is the systemreg
8
view of CONTROL, which merges the banked bits as per MRS.
9
10
Signed-off-by: David Reiss <dreiss@meta.com>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20230227213329.793795-15-richard.henderson@linaro.org
13
[rth: Substatial rewrite using enumerator and shared code.]
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
8
---
17
---
9
target/arm/helper-mve.h | 3 ++
18
target/arm/cpu.h | 2 +
10
target/arm/mve.decode | 6 +++-
19
target/arm/gdbstub.c | 178 +++++++++++++++++++++++++++++++++++++++++++
11
target/arm/mve_helper.c | 19 ++++++++++++
20
2 files changed, 180 insertions(+)
12
target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
21
13
4 files changed, 90 insertions(+), 1 deletion(-)
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
16
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-mve.h
24
--- a/target/arm/cpu.h
18
+++ b/target/arm/helper-mve.h
25
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
26
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
20
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
27
21
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
28
DynamicGDBXMLInfo dyn_sysreg_xml;
22
29
DynamicGDBXMLInfo dyn_svereg_xml;
23
+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
30
+ DynamicGDBXMLInfo dyn_m_systemreg_xml;
24
+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
31
+ DynamicGDBXMLInfo dyn_m_secextreg_xml;
25
+
32
26
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
33
/* Timers used by the generic (architected) timer */
27
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
34
QEMUTimer *gt_timer[NUM_GTIMERS];
28
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
35
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
29
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
30
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/mve.decode
37
--- a/target/arm/gdbstub.c
32
+++ b/target/arm/mve.decode
38
+++ b/target/arm/gdbstub.c
33
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
39
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
34
VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
40
return cpu->dyn_sysreg_xml.num;
35
36
# Vector add across vector
37
-VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
38
+{
39
+ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
40
+ VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
41
+ rdahi=%rdahi rdalo=%rdalo
42
+}
43
44
# Predicate operations
45
%mask_22_13 22:1 13:3
46
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/mve_helper.c
49
+++ b/target/arm/mve_helper.c
50
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
51
DO_VADDV(vaddvuh, 2, uint16_t)
52
DO_VADDV(vaddvuw, 4, uint32_t)
53
54
+#define DO_VADDLV(OP, TYPE, LTYPE) \
55
+ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
56
+ uint64_t ra) \
57
+ { \
58
+ uint16_t mask = mve_element_mask(env); \
59
+ unsigned e; \
60
+ TYPE *m = vm; \
61
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
62
+ if (mask & 1) { \
63
+ ra += (LTYPE)m[H4(e)]; \
64
+ } \
65
+ } \
66
+ mve_advance_vpt(env); \
67
+ return ra; \
68
+ } \
69
+
70
+DO_VADDLV(vaddlv_s, int32_t, int64_t)
71
+DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
72
+
73
/* Shifts by immediate */
74
#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
75
void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
76
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/translate-mve.c
79
+++ b/target/arm/translate-mve.c
80
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
81
return true;
82
}
41
}
83
42
84
+static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
43
+typedef enum {
44
+ M_SYSREG_MSP,
45
+ M_SYSREG_PSP,
46
+ M_SYSREG_PRIMASK,
47
+ M_SYSREG_CONTROL,
48
+ M_SYSREG_BASEPRI,
49
+ M_SYSREG_FAULTMASK,
50
+ M_SYSREG_MSPLIM,
51
+ M_SYSREG_PSPLIM,
52
+} MProfileSysreg;
53
+
54
+static const struct {
55
+ const char *name;
56
+ int feature;
57
+} m_sysreg_def[] = {
58
+ [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M },
59
+ [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M },
60
+ [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M },
61
+ [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M },
62
+ [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN },
63
+ [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN },
64
+ [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 },
65
+ [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 },
66
+};
67
+
68
+static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec)
69
+{
70
+ uint32_t *ptr;
71
+
72
+ switch (reg) {
73
+ case M_SYSREG_MSP:
74
+ ptr = arm_v7m_get_sp_ptr(env, sec, false, true);
75
+ break;
76
+ case M_SYSREG_PSP:
77
+ ptr = arm_v7m_get_sp_ptr(env, sec, true, true);
78
+ break;
79
+ case M_SYSREG_MSPLIM:
80
+ ptr = &env->v7m.msplim[sec];
81
+ break;
82
+ case M_SYSREG_PSPLIM:
83
+ ptr = &env->v7m.psplim[sec];
84
+ break;
85
+ case M_SYSREG_PRIMASK:
86
+ ptr = &env->v7m.primask[sec];
87
+ break;
88
+ case M_SYSREG_BASEPRI:
89
+ ptr = &env->v7m.basepri[sec];
90
+ break;
91
+ case M_SYSREG_FAULTMASK:
92
+ ptr = &env->v7m.faultmask[sec];
93
+ break;
94
+ case M_SYSREG_CONTROL:
95
+ ptr = &env->v7m.control[sec];
96
+ break;
97
+ default:
98
+ return NULL;
99
+ }
100
+ return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL;
101
+}
102
+
103
+static int m_sysreg_get(CPUARMState *env, GByteArray *buf,
104
+ MProfileSysreg reg, bool secure)
105
+{
106
+ uint32_t *ptr = m_sysreg_ptr(env, reg, secure);
107
+
108
+ if (ptr == NULL) {
109
+ return 0;
110
+ }
111
+ return gdb_get_reg32(buf, *ptr);
112
+}
113
+
114
+static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)
85
+{
115
+{
86
+ /*
116
+ /*
87
+ * Vector Add Long Across Vector: accumulate the 32-bit
117
+ * Here, we emulate MRS instruction, where CONTROL has a mix of
88
+ * elements of the vector into a 64-bit result stored in
118
+ * banked and non-banked bits.
89
+ * a pair of general-purpose registers.
90
+ * No need to check Qm's bank: it is only 3 bits in decode.
91
+ */
119
+ */
92
+ TCGv_ptr qm;
120
+ if (reg == M_SYSREG_CONTROL) {
93
+ TCGv_i64 rda;
121
+ return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure));
94
+ TCGv_i32 rdalo, rdahi;
122
+ }
95
+
123
+ return m_sysreg_get(env, buf, reg, env->v7m.secure);
96
+ if (!dc_isar_feature(aa32_mve, s)) {
124
+}
97
+ return false;
125
+
98
+ }
126
+static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)
99
+ /*
127
+{
100
+ * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
128
+ return 0; /* TODO */
101
+ * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
129
+}
102
+ */
130
+
103
+ if (a->rdahi == 13 || a->rdahi == 15) {
131
+static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg)
104
+ return false;
132
+{
105
+ }
133
+ ARMCPU *cpu = ARM_CPU(cs);
106
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
134
+ CPUARMState *env = &cpu->env;
107
+ return true;
135
+ GString *s = g_string_new(NULL);
108
+ }
136
+ int base_reg = orig_base_reg;
109
+
137
+ int i;
110
+ /*
138
+
111
+ * This insn is subject to beat-wise execution. Partial execution
139
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
112
+ * of an A=0 (no-accumulate) insn which does not execute the first
140
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
113
+ * beat must start with the current value of RdaHi:RdaLo, not zero.
141
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.m-system\">\n");
114
+ */
142
+
115
+ if (a->a || mve_skip_first_beat(s)) {
143
+ for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
116
+ /* Accumulate input from RdaHi:RdaLo */
144
+ if (arm_feature(env, m_sysreg_def[i].feature)) {
117
+ rda = tcg_temp_new_i64();
145
+ g_string_append_printf(s,
118
+ rdalo = load_reg(s, a->rdalo);
146
+ "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n",
119
+ rdahi = load_reg(s, a->rdahi);
147
+ m_sysreg_def[i].name, base_reg++);
120
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
148
+ }
121
+ tcg_temp_free_i32(rdalo);
149
+ }
122
+ tcg_temp_free_i32(rdahi);
150
+
123
+ } else {
151
+ g_string_append_printf(s, "</feature>");
124
+ /* Accumulate starting at zero */
152
+ cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false);
125
+ rda = tcg_const_i64(0);
153
+ cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg;
126
+ }
154
+
127
+
155
+ return cpu->dyn_m_systemreg_xml.num;
128
+ qm = mve_qreg_ptr(a->qm);
156
+}
129
+ if (a->u) {
157
+
130
+ gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
158
+#ifndef CONFIG_USER_ONLY
131
+ } else {
159
+/*
132
+ gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
160
+ * For user-only, we see the non-secure registers via m_systemreg above.
133
+ }
161
+ * For secext, encode the non-secure view as even and secure view as odd.
134
+ tcg_temp_free_ptr(qm);
162
+ */
135
+
163
+static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg)
136
+ rdalo = tcg_temp_new_i32();
164
+{
137
+ rdahi = tcg_temp_new_i32();
165
+ return m_sysreg_get(env, buf, reg >> 1, reg & 1);
138
+ tcg_gen_extrl_i64_i32(rdalo, rda);
166
+}
139
+ tcg_gen_extrh_i64_i32(rdahi, rda);
167
+
140
+ store_reg(s, a->rdalo, rdalo);
168
+static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)
141
+ store_reg(s, a->rdahi, rdahi);
169
+{
142
+ tcg_temp_free_i64(rda);
170
+ return 0; /* TODO */
143
+ mve_update_eci(s);
171
+}
144
+ return true;
172
+
145
+}
173
+static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)
146
+
174
+{
147
static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
175
+ ARMCPU *cpu = ARM_CPU(cs);
176
+ GString *s = g_string_new(NULL);
177
+ int base_reg = orig_base_reg;
178
+ int i;
179
+
180
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
181
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
182
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.secext\">\n");
183
+
184
+ for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
185
+ g_string_append_printf(s,
186
+ "<reg name=\"%s_ns\" bitsize=\"32\" regnum=\"%d\"/>\n",
187
+ m_sysreg_def[i].name, base_reg++);
188
+ g_string_append_printf(s,
189
+ "<reg name=\"%s_s\" bitsize=\"32\" regnum=\"%d\"/>\n",
190
+ m_sysreg_def[i].name, base_reg++);
191
+ }
192
+
193
+ g_string_append_printf(s, "</feature>");
194
+ cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false);
195
+ cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg;
196
+
197
+ return cpu->dyn_m_secextreg_xml.num;
198
+}
199
+#endif
200
+
201
const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
148
{
202
{
149
TCGv_ptr qd;
203
ARMCPU *cpu = ARM_CPU(cs);
204
@@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
205
return cpu->dyn_sysreg_xml.desc;
206
} else if (strcmp(xmlname, "sve-registers.xml") == 0) {
207
return cpu->dyn_svereg_xml.desc;
208
+ } else if (strcmp(xmlname, "arm-m-system.xml") == 0) {
209
+ return cpu->dyn_m_systemreg_xml.desc;
210
+#ifndef CONFIG_USER_ONLY
211
+ } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) {
212
+ return cpu->dyn_m_secextreg_xml.desc;
213
+#endif
214
}
215
return NULL;
216
}
217
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
218
arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
219
"system-registers.xml", 0);
220
221
+ if (arm_feature(env, ARM_FEATURE_M)) {
222
+ gdb_register_coprocessor(cs,
223
+ arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
224
+ arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
225
+ "arm-m-system.xml", 0);
226
+#ifndef CONFIG_USER_ONLY
227
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
228
+ gdb_register_coprocessor(cs,
229
+ arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,
230
+ arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs),
231
+ "arm-m-secext.xml", 0);
232
+ }
233
+#endif
234
+ }
235
}
150
--
236
--
151
2.20.1
237
2.34.1
152
153
diff view generated by jsdifflib
[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
[PULL 15/21] target/arm: Handle m-profile in arm_is_secure
1
Use dup_const() instead of bitfield_replicate() in
1
From: Richard Henderson <richard.henderson@linaro.org>
2
disas_simd_mod_imm().
3
2
4
(We can't replace the other use of bitfield_replicate() in this file,
3
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1421
5
in logic_imm_decode_wmask(), because that location needs to handle 2
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
and 4 bit elements, which dup_const() cannot.)
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20230227225832.816605-2-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/cpu.h | 3 +++
10
1 file changed, 3 insertions(+)
7
11
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
11
---
12
target/arm/translate-a64.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
14
--- a/target/arm/cpu.h
18
+++ b/target/arm/translate-a64.c
15
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
16
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el3_or_mon(CPUARMState *env)
20
/* FMOV (vector, immediate) - half-precision */
17
/* Return true if the processor is in secure state */
21
imm = vfp_expand_imm(MO_16, abcdefgh);
18
static inline bool arm_is_secure(CPUARMState *env)
22
/* now duplicate across the lanes */
19
{
23
- imm = bitfield_replicate(imm, 16);
20
+ if (arm_feature(env, ARM_FEATURE_M)) {
24
+ imm = dup_const(MO_16, imm);
21
+ return env->v7m.secure;
25
} else {
22
+ }
26
imm = asimd_imm_const(abcdefgh, cmode, is_neg);
23
if (arm_is_el3_or_mon(env)) {
24
return true;
27
}
25
}
28
--
26
--
29
2.20.1
27
2.34.1
30
31
diff view generated by jsdifflib
[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
[PULL 16/21] target/arm: Stub arm_hcr_el2_eff for m-profile
1
From: Patrick Venture <venture@google.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Adds a line-item reference to the supported quanta-q71l-bmc aspeed
3
M-profile doesn't have HCR_EL2. While we could test features
4
entry.
4
before each call, zero is a generally safe return value to
5
disable the code in the caller. This test is required to
6
avoid an assert in arm_is_secure_below_el3.
5
7
6
Signed-off-by: Patrick Venture <venture@google.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210615192848.1065297-2-venture@google.com
10
Message-id: 20230227225832.816605-3-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
docs/system/arm/aspeed.rst | 1 +
13
target/arm/helper.c | 3 +++
12
1 file changed, 1 insertion(+)
14
1 file changed, 3 insertions(+)
13
15
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/aspeed.rst
18
--- a/target/arm/helper.c
17
+++ b/docs/system/arm/aspeed.rst
19
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ etc.
20
@@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure)
19
AST2400 SoC based machines :
21
20
22
uint64_t arm_hcr_el2_eff(CPUARMState *env)
21
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
23
{
22
+- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
24
+ if (arm_feature(env, ARM_FEATURE_M)) {
23
25
+ return 0;
24
AST2500 SoC based machines :
26
+ }
27
return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env));
28
}
25
29
26
--
30
--
27
2.20.1
31
2.34.1
28
29
diff view generated by jsdifflib
[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
[PULL 17/21] target/arm: Diagnose incorrect usage of arm_is_secure subroutines
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add a test booting and quickly shutdown a raspi2 machine,
3
In several places we use arm_is_secure_below_el3 and
4
to test the power management model:
4
arm_is_el3_or_mon separately from arm_is_secure.
5
These functions make no sense for m-profile, and
6
would indicate prior incorrect feature testing.
5
7
6
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
console: [ 0.000000] Booting Linux on physical CPU 0xf00
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
11
Message-id: 20230227225832.816605-4-richard.henderson@linaro.org
10
console: [ 0.000000] CPU: div instructions available: patching division code
11
console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
12
console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
13
...
14
console: Boot successful.
15
console: cat /proc/cpuinfo
16
console: / # cat /proc/cpuinfo
17
...
18
console: processor : 3
19
console: model name : ARMv7 Processor rev 5 (v7l)
20
console: BogoMIPS : 125.00
21
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
22
console: CPU implementer : 0x41
23
console: CPU architecture: 7
24
console: CPU variant : 0x0
25
console: CPU part : 0xc07
26
console: CPU revision : 5
27
console: Hardware : BCM2835
28
console: Revision : 0000
29
console: Serial : 0000000000000000
30
console: cat /proc/iomem
31
console: / # cat /proc/iomem
32
console: 00000000-3bffffff : System RAM
33
console: 00008000-00afffff : Kernel code
34
console: 00c00000-00d468ef : Kernel data
35
console: 3f006000-3f006fff : dwc_otg
36
console: 3f007000-3f007eff : /soc/dma@7e007000
37
console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
38
console: 3f100000-3f100027 : /soc/watchdog@7e100000
39
console: 3f101000-3f102fff : /soc/cprman@7e101000
40
console: 3f200000-3f2000b3 : /soc/gpio@7e200000
41
PASS (24.59 s)
42
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
43
JOB TIME : 25.02 s
44
45
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
46
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
47
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
48
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
49
---
13
---
50
tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
14
target/arm/cpu.h | 5 ++++-
51
1 file changed, 43 insertions(+)
15
1 file changed, 4 insertions(+), 1 deletion(-)
52
16
53
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
54
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
55
--- a/tests/acceptance/boot_linux_console.py
19
--- a/target/arm/cpu.h
56
+++ b/tests/acceptance/boot_linux_console.py
20
+++ b/target/arm/cpu.h
57
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
58
from avocado import skip
22
void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
59
from avocado import skipUnless
23
60
from avocado_qemu import Test
24
#if !defined(CONFIG_USER_ONLY)
61
+from avocado_qemu import exec_command
25
-/* Return true if exception levels below EL3 are in secure state,
62
from avocado_qemu import exec_command_and_wait_for_pattern
26
+/*
63
from avocado_qemu import interrupt_interactive_console_until_pattern
27
+ * Return true if exception levels below EL3 are in secure state,
64
from avocado_qemu import wait_for_console_pattern
28
* or would be following an exception return to that level.
65
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
29
* Unlike arm_is_secure() (which is always a question about the
66
"""
30
* _current_ state of the CPU) this doesn't care about the current
67
self.do_test_arm_raspi2(0)
31
@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
68
32
*/
69
+ def test_arm_raspi2_initrd(self):
33
static inline bool arm_is_secure_below_el3(CPUARMState *env)
70
+ """
34
{
71
+ :avocado: tags=arch:arm
35
+ assert(!arm_feature(env, ARM_FEATURE_M));
72
+ :avocado: tags=machine:raspi2
36
if (arm_feature(env, ARM_FEATURE_EL3)) {
73
+ """
37
return !(env->cp15.scr_el3 & SCR_NS);
74
+ deb_url = ('http://archive.raspberrypi.org/debian/'
38
} else {
75
+ 'pool/main/r/raspberrypi-firmware/'
39
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
76
+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')
40
/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
77
+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
41
static inline bool arm_is_el3_or_mon(CPUARMState *env)
78
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
42
{
79
+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
43
+ assert(!arm_feature(env, ARM_FEATURE_M));
80
+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
44
if (arm_feature(env, ARM_FEATURE_EL3)) {
81
+
45
if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
82
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
46
/* CPU currently in AArch64 state and EL3 */
83
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
84
+ 'arm/rootfs-armv7a.cpio.gz')
85
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
86
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
87
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
88
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
89
+
90
+ self.vm.set_console()
91
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
92
+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '
93
+ 'panic=-1 noreboot ' +
94
+ 'dwc_otg.fiq_fsm_enable=0')
95
+ self.vm.add_args('-kernel', kernel_path,
96
+ '-dtb', dtb_path,
97
+ '-initrd', initrd_path,
98
+ '-append', kernel_command_line,
99
+ '-no-reboot')
100
+ self.vm.launch()
101
+ self.wait_for_console_pattern('Boot successful.')
102
+
103
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
104
+ 'BCM2835')
105
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
106
+ '/soc/cprman@7e101000')
107
+ exec_command(self, 'halt')
108
+ # Wait for VM to shut down gracefully
109
+ self.vm.wait()
110
+
111
def test_arm_exynos4210_initrd(self):
112
"""
113
:avocado: tags=arch:arm
114
--
47
--
115
2.20.1
48
2.34.1
116
49
117
50
diff view generated by jsdifflib
[PULL 15/24] target/arm: Implement MVE VSHLL
[PULL 18/21] target/arm: Rewrite check_s2_mmu_setup
1
Implement the MVE VHLL (vector shift left long) insn. This has two
1
From: Richard Henderson <richard.henderson@linaro.org>
2
encodings: the T1 encoding is the usual shift-by-immediate format,
2
3
and the T2 encoding is a special case where the shift count is always
3
Integrate neighboring code from get_phys_addr_lpae which computed
4
equal to the element size.
4
starting level, as it is easier to validate when doing both at the
5
5
same time. Mirror the checks at the start of AArch{64,32}.S2Walk,
6
especially S2InvalidSL and S2InconsistentSL.
7
8
This reverts 49ba115bb74, which was incorrect -- there is nothing
9
in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the
10
pseudocode is consistent in referencing PAMax.
11
12
Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup")
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20230227225832.816605-5-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
9
---
17
---
10
target/arm/helper-mve.h | 9 +++++++
18
target/arm/ptw.c | 173 ++++++++++++++++++++++++++---------------------
11
target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++---
19
1 file changed, 97 insertions(+), 76 deletions(-)
12
target/arm/mve_helper.c | 32 +++++++++++++++++++++++
20
13
target/arm/translate-mve.c | 15 +++++++++++
21
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
14
4 files changed, 105 insertions(+), 4 deletions(-)
15
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
17
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-mve.h
23
--- a/target/arm/ptw.c
19
+++ b/target/arm/helper-mve.h
24
+++ b/target/arm/ptw.c
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
21
DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
* check_s2_mmu_setup
22
DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
* @cpu: ARMCPU
23
DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
* @is_aa64: True if the translation regime is in AArch64 state
24
+
29
- * @startlevel: Suggested starting level
25
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
- * @inputsize: Bitsize of IPAs
26
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+ * @tcr: VTCR_EL2 or VSTCR_EL2
27
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+ * @ds: Effective value of TCR.DS.
28
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+ * @iasize: Bitsize of IPAs
29
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
* @stride: Page-table stride (See the ARM ARM)
30
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
*
31
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
- * Returns true if the suggested S2 translation parameters are OK and
32
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
- * false otherwise.
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
38
+ * Decode the starting level of the S2 lookup, returning INT_MIN if
34
index XXXXXXX..XXXXXXX 100644
39
+ * the configuration is invalid.
35
--- a/target/arm/mve.decode
40
*/
36
+++ b/target/arm/mve.decode
41
-static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
37
@@ -XXX,XX +XXX,XX @@
42
- int inputsize, int stride, int outputsize)
38
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
43
+static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr,
39
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
44
+ bool ds, int iasize, int stride)
40
45
{
41
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
46
- const int grainsize = stride + 3;
42
+@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
47
- int startsizecheck;
43
+# VSHLL encoding T2 where shift == esize
48
-
44
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
49
- /*
45
+ qd=%qd qm=%qm size=0 shift=8
50
- * Negative levels are usually not allowed...
46
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
51
- * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
47
+ qd=%qd qm=%qm size=1 shift=16
52
- * begins with level -1. Note that previous feature tests will have
48
+
53
- * eliminated this combination if it is not enabled.
49
# Right shifts are encoded as N - shift, where N is the element size in bits.
54
- */
50
%rshift_i5 16:5 !function=rsub_32
55
- if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) {
51
%rshift_i4 16:4 !function=rsub_16
56
- return false;
52
@@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
57
- }
53
VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
58
-
54
VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
59
- startsizecheck = inputsize - ((3 - level) * stride + grainsize);
55
60
- if (startsizecheck < 1 || startsizecheck > stride + 4) {
56
-VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
61
- return false;
57
-VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
62
- }
58
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
63
+ int sl0, sl2, startlevel, granulebits, levels;
59
+# overlaps what would be size=0b11 VMULH/VRMULH
64
+ int s1_min_iasize, s1_max_iasize;
60
+{
65
61
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
66
+ sl0 = extract32(tcr, 6, 2);
62
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
67
if (is_aa64) {
63
68
+ /*
64
-VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
69
+ * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of
65
-VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
70
+ * get_phys_addr_lpae, that used aa64_va_parameters which apply
66
+ VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
71
+ * to aarch64. If Stage1 is aarch32, the min_txsz is larger.
67
+}
72
+ * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to
68
+
73
+ * inputsize is 64 - 24 = 40.
69
+{
74
+ */
70
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
75
+ if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) {
71
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
76
+ goto fail;
72
+
77
+ }
73
+ VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
78
+
74
+}
79
+ /*
75
+
80
+ * AArch64.S2InvalidSL: Interpretation of SL depends on the page size,
76
+{
81
+ * so interleave AArch64.S2StartLevel.
77
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
82
+ */
78
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
83
switch (stride) {
79
+
84
- case 13: /* 64KB Pages. */
80
+ VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
85
- if (level == 0 || (level == 1 && outputsize <= 42)) {
81
+}
86
- return false;
82
+
87
+ case 9: /* 4KB */
83
+{
88
+ /* SL2 is RES0 unless DS=1 & 4KB granule. */
84
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
89
+ sl2 = extract64(tcr, 33, 1);
85
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
90
+ if (ds && sl2) {
86
+
91
+ if (sl0 != 0) {
87
+ VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
92
+ goto fail;
88
+}
93
+ }
89
94
+ startlevel = -1;
90
VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
95
+ } else {
91
VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
96
+ startlevel = 2 - sl0;
92
@@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
97
+ switch (sl0) {
93
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
98
+ case 2:
94
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
99
+ if (arm_pamax(cpu) < 44) {
95
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
100
+ goto fail;
96
+
101
+ }
97
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
102
+ break;
98
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
103
+ case 3:
99
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
104
+ if (!cpu_isar_feature(aa64_st, cpu)) {
100
+
105
+ goto fail;
101
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
106
+ }
102
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
107
+ startlevel = 3;
103
+
108
+ break;
104
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
109
+ }
105
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
110
}
106
+
111
break;
107
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
112
- case 11: /* 16KB Pages. */
108
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
113
- if (level == 0 || (level == 1 && outputsize <= 40)) {
109
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
114
- return false;
110
index XXXXXXX..XXXXXXX 100644
115
+ case 11: /* 16KB */
111
--- a/target/arm/mve_helper.c
116
+ switch (sl0) {
112
+++ b/target/arm/mve_helper.c
117
+ case 2:
113
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
118
+ if (arm_pamax(cpu) < 42) {
114
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
119
+ goto fail;
115
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
120
+ }
116
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
121
+ break;
117
+
122
+ case 3:
118
+/*
123
+ if (!ds) {
119
+ * Long shifts taking half-sized inputs from top or bottom of the input
124
+ goto fail;
120
+ * vector and producing a double-width result. ESIZE, TYPE are for
125
+ }
121
+ * the input, and LESIZE, LTYPE for the output.
126
+ break;
122
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
127
}
123
+ * because the long shift is strictly left-only.
128
+ startlevel = 3 - sl0;
124
+ */
129
break;
125
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \
130
- case 9: /* 4KB Pages. */
126
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
131
- if (level == 0 && outputsize <= 42) {
127
+ void *vm, uint32_t shift) \
132
- return false;
128
+ { \
133
+ case 13: /* 64KB */
129
+ LTYPE *d = vd; \
134
+ switch (sl0) {
130
+ TYPE *m = vm; \
135
+ case 2:
131
+ uint16_t mask = mve_element_mask(env); \
136
+ if (arm_pamax(cpu) < 44) {
132
+ unsigned le; \
137
+ goto fail;
133
+ assert(shift <= 16); \
138
+ }
134
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
139
+ break;
135
+ LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \
140
+ case 3:
136
+ mergemask(&d[H##LESIZE(le)], r, mask); \
141
+ goto fail;
137
+ } \
142
}
138
+ mve_advance_vpt(env); \
143
+ startlevel = 3 - sl0;
144
break;
145
default:
146
g_assert_not_reached();
147
}
148
-
149
- /* Inputsize checks. */
150
- if (inputsize > outputsize &&
151
- (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) {
152
- /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
153
- return false;
154
- }
155
} else {
156
- /* AArch32 only supports 4KB pages. Assert on that. */
157
+ /*
158
+ * Things are simpler for AArch32 EL2, with only 4k pages.
159
+ * There is no separate S2InvalidSL function, but AArch32.S2Walk
160
+ * begins with walkparms.sl0 in {'1x'}.
161
+ */
162
assert(stride == 9);
163
-
164
- if (level == 0) {
165
- return false;
166
+ if (sl0 >= 2) {
167
+ goto fail;
168
}
169
+ startlevel = 2 - sl0;
170
}
171
- return true;
172
+
173
+ /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */
174
+ levels = 3 - startlevel;
175
+ granulebits = stride + 3;
176
+
177
+ s1_min_iasize = levels * stride + granulebits + 1;
178
+ s1_max_iasize = s1_min_iasize + (stride - 1) + 4;
179
+
180
+ if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) {
181
+ return startlevel;
139
+ }
182
+ }
140
+
183
+
141
+#define DO_VSHLL_ALL(OP, TOP) \
184
+ fail:
142
+ DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \
185
+ return INT_MIN;
143
+ DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \
186
}
144
+ DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \
187
145
+ DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \
188
/**
146
+
189
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
147
+DO_VSHLL_ALL(vshllb, false)
190
*/
148
+DO_VSHLL_ALL(vshllt, true)
191
level = 4 - (inputsize - 4) / stride;
149
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
192
} else {
150
index XXXXXXX..XXXXXXX 100644
193
- /*
151
--- a/target/arm/translate-mve.c
194
- * For stage 2 translations the starting level is specified by the
152
+++ b/target/arm/translate-mve.c
195
- * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
153
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
196
- */
154
DO_2SHIFT(VSHRI_U, vshli_u, true)
197
- uint32_t sl0 = extract32(tcr, 6, 2);
155
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
198
- uint32_t sl2 = extract64(tcr, 33, 1);
156
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
199
- int32_t startlevel;
157
+
200
- bool ok;
158
+#define DO_VSHLL(INSN, FN) \
201
-
159
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
202
- /* SL2 is RES0 unless DS=1 & 4kb granule. */
160
+ { \
203
- if (param.ds && stride == 9 && sl2) {
161
+ static MVEGenTwoOpShiftFn * const fns[] = { \
204
- if (sl0 != 0) {
162
+ gen_helper_mve_##FN##b, \
205
- level = 0;
163
+ gen_helper_mve_##FN##h, \
206
- goto do_translation_fault;
164
+ }; \
207
- }
165
+ return do_2shift(s, a, fns[a->size], false); \
208
- startlevel = -1;
166
+ }
209
- } else if (!aarch64 || stride == 9) {
167
+
210
- /* AArch32 or 4KB pages */
168
+DO_VSHLL(VSHLL_BS, vshllbs)
211
- startlevel = 2 - sl0;
169
+DO_VSHLL(VSHLL_BU, vshllbu)
212
-
170
+DO_VSHLL(VSHLL_TS, vshllts)
213
- if (cpu_isar_feature(aa64_st, cpu)) {
171
+DO_VSHLL(VSHLL_TU, vshlltu)
214
- startlevel &= 3;
215
- }
216
- } else {
217
- /* 16KB or 64KB pages */
218
- startlevel = 3 - sl0;
219
- }
220
-
221
- /* Check that the starting level is valid. */
222
- ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
223
- inputsize, stride, outputsize);
224
- if (!ok) {
225
+ int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds,
226
+ inputsize, stride);
227
+ if (startlevel == INT_MIN) {
228
+ level = 0;
229
goto do_translation_fault;
230
}
231
level = startlevel;
172
--
232
--
173
2.20.1
233
2.34.1
174
175
diff view generated by jsdifflib
[PULL 22/24] target/arm: Implement MVE long shifts by register
[PULL 19/21] hw: arm: Support direct boot for Linux/arm64 EFI zboot images
1
Implement the MVE long shifts by register, which perform shifts on a
1
From: Ard Biesheuvel <ardb@kernel.org>
2
pair of general-purpose registers treated as a 64-bit quantity, with
3
the shift count in another general-purpose register, which might be
4
either positive or negative.
5
2
6
Like the long-shifts-by-immediate, these encodings sit in the space
3
Fedora 39 will ship its arm64 kernels in the new generic EFI zboot
7
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
4
format, using gzip compression for the payload.
8
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
9
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
10
we have to move the CSEL pattern into the same decodetree group.
11
5
6
For doing EFI boot in QEMU, this is completely transparent, as the
7
firmware or bootloader will take care of this. However, for direct
8
kernel boot without firmware, we will lose the ability to boot such
9
distro kernels unless we deal with the new format directly.
10
11
EFI zboot images contain metadata in the header regarding the placement
12
of the compressed payload inside the image, and the type of compression
13
used. This means we can wire up the existing gzip support without too
14
much hassle, by parsing the header and grabbing the payload from inside
15
the loaded zboot image.
16
17
Cc: Peter Maydell <peter.maydell@linaro.org>
18
Cc: Alex Bennée <alex.bennee@linaro.org>
19
Cc: Richard Henderson <richard.henderson@linaro.org>
20
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
22
Message-id: 20230303160109.3626966-1-ardb@kernel.org
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
[PMM: tweaked comment formatting, fixed checkpatch nits]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
15
---
26
---
16
target/arm/helper-mve.h | 6 +++
27
include/hw/loader.h | 19 ++++++++++
17
target/arm/translate.h | 1 +
28
hw/arm/boot.c | 6 +++
18
target/arm/t32.decode | 16 +++++--
29
hw/core/loader.c | 91 +++++++++++++++++++++++++++++++++++++++++++++
19
target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
30
3 files changed, 116 insertions(+)
20
target/arm/translate.c | 69 ++++++++++++++++++++++++++++++
21
5 files changed, 182 insertions(+), 3 deletions(-)
22
31
23
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
32
diff --git a/include/hw/loader.h b/include/hw/loader.h
24
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/helper-mve.h
34
--- a/include/hw/loader.h
26
+++ b/target/arm/helper-mve.h
35
+++ b/include/hw/loader.h
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
28
37
uint8_t **buffer);
29
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
38
ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz);
30
39
31
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
40
+/**
32
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
41
+ * unpack_efi_zboot_image:
33
DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
42
+ * @buffer: pointer to a variable holding the address of a buffer containing the
34
DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
43
+ * image
35
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
44
+ * @size: pointer to a variable holding the size of the buffer
36
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
45
+ *
37
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
46
+ * Check whether the buffer contains a EFI zboot image, and if it does, extract
38
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
47
+ * the compressed payload and decompress it into a new buffer. If successful,
39
diff --git a/target/arm/translate.h b/target/arm/translate.h
48
+ * the old buffer is freed, and the *buffer and size variables pointed to by the
49
+ * function arguments are updated to refer to the newly populated buffer.
50
+ *
51
+ * Returns 0 if the image could not be identified as a EFI zboot image.
52
+ * Returns -1 if the buffer contents were identified as a EFI zboot image, but
53
+ * unpacking failed for any reason.
54
+ * Returns the size of the decompressed payload if decompression was performed
55
+ * successfully.
56
+ */
57
+ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size);
58
+
59
#define ELF_LOAD_FAILED -1
60
#define ELF_LOAD_NOT_ELF -2
61
#define ELF_LOAD_WRONG_ARCH -3
62
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
40
index XXXXXXX..XXXXXXX 100644
63
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/translate.h
64
--- a/hw/arm/boot.c
42
+++ b/target/arm/translate.h
65
+++ b/hw/arm/boot.c
43
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
66
@@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
44
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
67
return -1;
45
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
68
}
46
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
69
size = len;
47
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
70
+
48
71
+ /* Unpack the image if it is a EFI zboot image */
49
/**
72
+ if (unpack_efi_zboot_image(&buffer, &size) < 0) {
50
* arm_tbflags_from_tb:
73
+ g_free(buffer);
51
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
74
+ return -1;
75
+ }
76
}
77
78
/* check the arm64 magic header value -- very old kernels may not have it */
79
diff --git a/hw/core/loader.c b/hw/core/loader.c
52
index XXXXXXX..XXXXXXX 100644
80
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/t32.decode
81
--- a/hw/core/loader.c
54
+++ b/target/arm/t32.decode
82
+++ b/hw/core/loader.c
55
@@ -XXX,XX +XXX,XX @@
83
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz)
56
&mcrr !extern cp opc1 crm rt rt2
84
return bytes;
57
85
}
58
&mve_shl_ri rdalo rdahi shim
86
59
+&mve_shl_rr rdalo rdahi rm
87
+/* The PE/COFF MS-DOS stub magic number */
60
88
+#define EFI_PE_MSDOS_MAGIC "MZ"
61
# rdahi: bits [3:1] from insn, bit 0 is 1
62
# rdalo: bits [3:1] from insn, bit 0 is 0
63
@@ -XXX,XX +XXX,XX @@
64
65
@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
66
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
67
+@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
68
+ &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
69
70
{
71
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
72
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
73
URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
74
SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
75
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
76
+
89
+
77
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
90
+/*
78
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
91
+ * The Linux header magic number for a EFI PE/COFF
79
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
92
+ * image targetting an unspecified architecture.
80
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
93
+ */
81
+ UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
94
+#define EFI_PE_LINUX_MAGIC "\xcd\x23\x82\x81"
82
+ SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
83
]
84
85
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
86
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
87
+
95
+
88
+ # v8.1M CSEL and friends
96
+/*
89
+ CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
97
+ * Bootable Linux kernel images may be packaged as EFI zboot images, which are
90
}
98
+ * self-decompressing executables when loaded via EFI. The compressed payload
91
{
99
+ * can also be extracted from the image and decompressed by a non-EFI loader.
92
MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
100
+ *
93
@@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
101
+ * The de facto specification for this format is at the following URL:
94
}
102
+ *
95
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
103
+ * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/efi/libstub/zboot-header.S
96
104
+ *
97
-# v8.1M CSEL and friends
105
+ * This definition is based on Linux upstream commit 29636a5ce87beba.
98
-CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
106
+ */
99
-
107
+struct linux_efi_zboot_header {
100
# Data-processing (register-shifted register)
108
+ uint8_t msdos_magic[2]; /* PE/COFF 'MZ' magic number */
101
109
+ uint8_t reserved0[2];
102
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
110
+ uint8_t zimg[4]; /* "zimg" for Linux EFI zboot images */
103
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
111
+ uint32_t payload_offset; /* LE offset to compressed payload */
104
index XXXXXXX..XXXXXXX 100644
112
+ uint32_t payload_size; /* LE size of the compressed payload */
105
--- a/target/arm/mve_helper.c
113
+ uint8_t reserved1[8];
106
+++ b/target/arm/mve_helper.c
114
+ char compression_type[32]; /* Compression type, NUL terminated */
107
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
115
+ uint8_t linux_magic[4]; /* Linux header magic */
108
return rdm;
116
+ uint32_t pe_header_offset; /* LE offset to the PE header */
109
}
117
+};
110
118
+
111
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
119
+/*
120
+ * Check whether *buffer points to a Linux EFI zboot image in memory.
121
+ *
122
+ * If it does, attempt to decompress it to a new buffer, and free the old one.
123
+ * If any of this fails, return an error to the caller.
124
+ *
125
+ * If the image is not a Linux EFI zboot image, do nothing and return success.
126
+ */
127
+ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size)
112
+{
128
+{
113
+ return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
129
+ const struct linux_efi_zboot_header *header;
114
+}
130
+ uint8_t *data = NULL;
131
+ int ploff, plsize;
132
+ ssize_t bytes;
115
+
133
+
116
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
134
+ /* ignore if this is too small to be a EFI zboot image */
117
+{
135
+ if (*size < sizeof(*header)) {
118
+ return do_uqrshl_d(n, (int8_t)shift, false, NULL);
119
+}
120
+
121
uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
122
{
123
return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
124
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
{
126
return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
}
128
+
129
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
130
+{
131
+ return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
132
+}
133
+
134
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
135
+{
136
+ return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
137
+}
138
+
139
+/* Operate on 64-bit values, but saturate at 48 bits */
140
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
141
+ bool round, uint32_t *sat)
142
+{
143
+ if (shift <= -48) {
144
+ /* Rounding the sign bit always produces 0. */
145
+ if (round) {
146
+ return 0;
147
+ }
148
+ return src >> 63;
149
+ } else if (shift < 0) {
150
+ if (round) {
151
+ src >>= -shift - 1;
152
+ return (src >> 1) + (src & 1);
153
+ }
154
+ return src >> -shift;
155
+ } else if (shift < 48) {
156
+ int64_t val = src << shift;
157
+ int64_t extval = sextract64(val, 0, 48);
158
+ if (!sat || val == extval) {
159
+ return extval;
160
+ }
161
+ } else if (!sat || src == 0) {
162
+ return 0;
136
+ return 0;
163
+ }
137
+ }
164
+
138
+
165
+ *sat = 1;
139
+ header = (struct linux_efi_zboot_header *)*buffer;
166
+ return (1ULL << 47) - (src >= 0);
167
+}
168
+
140
+
169
+/* Operate on 64-bit values, but saturate at 48 bits */
141
+ /* ignore if this is not a Linux EFI zboot image */
170
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
142
+ if (memcmp(&header->msdos_magic, EFI_PE_MSDOS_MAGIC, 2) != 0 ||
171
+ bool round, uint32_t *sat)
143
+ memcmp(&header->zimg, "zimg", 4) != 0 ||
172
+{
144
+ memcmp(&header->linux_magic, EFI_PE_LINUX_MAGIC, 4) != 0) {
173
+ uint64_t val, extval;
174
+
175
+ if (shift <= -(48 + round)) {
176
+ return 0;
177
+ } else if (shift < 0) {
178
+ if (round) {
179
+ val = src >> (-shift - 1);
180
+ val = (val >> 1) + (val & 1);
181
+ } else {
182
+ val = src >> -shift;
183
+ }
184
+ extval = extract64(val, 0, 48);
185
+ if (!sat || val == extval) {
186
+ return extval;
187
+ }
188
+ } else if (shift < 48) {
189
+ uint64_t val = src << shift;
190
+ uint64_t extval = extract64(val, 0, 48);
191
+ if (!sat || val == extval) {
192
+ return extval;
193
+ }
194
+ } else if (!sat || src == 0) {
195
+ return 0;
145
+ return 0;
196
+ }
146
+ }
197
+
147
+
198
+ *sat = 1;
148
+ if (strcmp(header->compression_type, "gzip") != 0) {
199
+ return MAKE_64BIT_MASK(0, 48);
149
+ fprintf(stderr,
200
+}
150
+ "unable to handle EFI zboot image with \"%.*s\" compression\n",
201
+
151
+ (int)sizeof(header->compression_type) - 1,
202
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
152
+ header->compression_type);
203
+{
153
+ return -1;
204
+ return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
205
+}
206
+
207
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
208
+{
209
+ return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
210
+}
211
diff --git a/target/arm/translate.c b/target/arm/translate.c
212
index XXXXXXX..XXXXXXX 100644
213
--- a/target/arm/translate.c
214
+++ b/target/arm/translate.c
215
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
216
return do_mve_shl_ri(s, a, gen_urshr64_i64);
217
}
218
219
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
220
+{
221
+ TCGv_i64 rda;
222
+ TCGv_i32 rdalo, rdahi;
223
+
224
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
225
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
226
+ return false;
227
+ }
228
+ if (a->rdahi == 15) {
229
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
230
+ return false;
231
+ }
232
+ if (!dc_isar_feature(aa32_mve, s) ||
233
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
234
+ a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
235
+ a->rm == a->rdahi || a->rm == a->rdalo) {
236
+ /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
237
+ unallocated_encoding(s);
238
+ return true;
239
+ }
154
+ }
240
+
155
+
241
+ rda = tcg_temp_new_i64();
156
+ ploff = ldl_le_p(&header->payload_offset);
242
+ rdalo = load_reg(s, a->rdalo);
157
+ plsize = ldl_le_p(&header->payload_size);
243
+ rdahi = load_reg(s, a->rdahi);
244
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
245
+
158
+
246
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
159
+ if (ploff < 0 || plsize < 0 || ploff + plsize > *size) {
247
+ fn(rda, cpu_env, rda, cpu_R[a->rm]);
160
+ fprintf(stderr, "unable to handle corrupt EFI zboot image\n");
161
+ return -1;
162
+ }
248
+
163
+
249
+ tcg_gen_extrl_i64_i32(rdalo, rda);
164
+ data = g_malloc(LOAD_IMAGE_MAX_GUNZIP_BYTES);
250
+ tcg_gen_extrh_i64_i32(rdahi, rda);
165
+ bytes = gunzip(data, LOAD_IMAGE_MAX_GUNZIP_BYTES, *buffer + ploff, plsize);
251
+ store_reg(s, a->rdalo, rdalo);
166
+ if (bytes < 0) {
252
+ store_reg(s, a->rdahi, rdahi);
167
+ fprintf(stderr, "failed to decompress EFI zboot image\n");
253
+ tcg_temp_free_i64(rda);
168
+ g_free(data);
169
+ return -1;
170
+ }
254
+
171
+
255
+ return true;
172
+ g_free(*buffer);
256
+}
173
+ *buffer = g_realloc(data, bytes);
257
+
174
+ *size = bytes;
258
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
175
+ return bytes;
259
+{
260
+ return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
261
+}
262
+
263
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
264
+{
265
+ return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
266
+}
267
+
268
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
269
+{
270
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
271
+}
272
+
273
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
274
+{
275
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
276
+}
277
+
278
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
279
+{
280
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
281
+}
282
+
283
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
284
+{
285
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
286
+}
176
+}
287
+
177
+
288
/*
178
/*
289
* Multiply and multiply accumulate
179
* Functions for reboot-persistent memory regions.
290
*/
180
* - used for vga bios and option roms.
291
--
181
--
292
2.20.1
182
2.34.1
293
183
294
184
diff view generated by jsdifflib
[PULL 21/24] target/arm: Implement MVE long shifts by immediate
[PULL 20/21] hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
1
The MVE extension to v8.1M includes some new shift instructions which
1
From: qianfan Zhao <qianfanguijin@163.com>
2
sit entirely within the non-coprocessor part of the encoding space
3
and which operate only on general-purpose registers. They take up
4
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
5
with Rm == 13 or 15.
6
2
7
Implement the long shifts by immediate, which perform shifts on a
3
TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect)
8
pair of general-purpose registers treated as a 64-bit quantity, with
4
register on SUN6i based SoCs, we should lower interrupt when the guest
9
an immediate shift count between 1 and 32.
5
set this bit.
10
6
11
Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
7
The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no
12
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
8
device connected on the i2c bus, next is the trace log:
13
cases where v8.1M now requires that. (Trying to change MOVS and ORRS
14
is too difficult, because the functions that generate the code are
15
shared between a dozen different kinds of arithmetic or logical
16
instruction for all A32, T16 and T32 encodings, and for some insns
17
and some encodings Rm==13,15 are valid.)
18
9
19
We make the helper functions we need for UQSHLL and SQSHLL take
10
allwinner_i2c_write write CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN
20
a 32-bit value which the helper casts to int8_t because we'll need
11
allwinner_i2c_write write CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
21
these helpers also for the shift-by-register insns, where the shift
12
allwinner_i2c_read read CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
22
count might be < 0 or > 32.
13
allwinner_i2c_read read STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK
14
allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
15
allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
16
allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
17
allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE
18
allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
19
allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
20
allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
21
allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE
22
...
23
23
24
Fix it.
25
26
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
27
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
28
Tested-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
29
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
27
---
31
---
28
target/arm/helper-mve.h | 3 ++
32
include/hw/i2c/allwinner-i2c.h | 6 ++++++
29
target/arm/translate.h | 1 +
33
hw/i2c/allwinner-i2c.c | 26 ++++++++++++++++++++++++--
30
target/arm/t32.decode | 28 +++++++++++++
34
2 files changed, 30 insertions(+), 2 deletions(-)
31
target/arm/mve_helper.c | 10 +++++
32
target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++
33
5 files changed, 132 insertions(+)
34
35
35
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
36
diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h
36
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper-mve.h
38
--- a/include/hw/i2c/allwinner-i2c.h
38
+++ b/target/arm/helper-mve.h
39
+++ b/include/hw/i2c/allwinner-i2c.h
39
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
@@ -XXX,XX +XXX,XX @@
40
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
#include "qom/object.h"
41
42
42
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
43
#define TYPE_AW_I2C "allwinner.i2c"
43
+
44
+
44
+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
45
+/** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */
45
+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
46
+#define TYPE_AW_I2C_SUN6I TYPE_AW_I2C "-sun6i"
46
diff --git a/target/arm/translate.h b/target/arm/translate.h
47
+
48
OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
49
50
#define AW_I2C_MEM_SIZE 0x24
51
@@ -XXX,XX +XXX,XX @@ struct AWI2CState {
52
uint8_t srst;
53
uint8_t efr;
54
uint8_t lcr;
55
+
56
+ bool irq_clear_inverted;
57
};
58
59
#endif /* ALLWINNER_I2C_H */
60
diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
47
index XXXXXXX..XXXXXXX 100644
61
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/translate.h
62
--- a/hw/i2c/allwinner-i2c.c
49
+++ b/target/arm/translate.h
63
+++ b/hw/i2c/allwinner-i2c.c
50
@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
64
@@ -XXX,XX +XXX,XX @@ static void allwinner_i2c_write(void *opaque, hwaddr offset,
51
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
65
s->stat = STAT_FROM_STA(STAT_IDLE);
52
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
66
s->cntr &= ~TWI_CNTR_M_STP;
53
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
67
}
54
+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
68
- if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
55
69
- /* Interrupt flag cleared */
56
/**
57
* arm_tbflags_from_tb:
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
61
+++ b/target/arm/t32.decode
62
@@ -XXX,XX +XXX,XX @@
63
&mcr !extern cp opc1 crn crm opc2 rt
64
&mcrr !extern cp opc1 crm rt rt2
65
66
+&mve_shl_ri rdalo rdahi shim
67
+
70
+
68
+# rdahi: bits [3:1] from insn, bit 0 is 1
71
+ if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) {
69
+# rdalo: bits [3:1] from insn, bit 0 is 0
72
+ /* Write 0 to clear this flag */
70
+%rdahi_9 9:3 !function=times_2_plus_1
73
+ qemu_irq_lower(s->irq);
71
+%rdalo_17 17:3 !function=times_2
74
+ } else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) {
75
+ /* Write 1 to clear this flag */
76
+ s->cntr &= ~TWI_CNTR_INT_FLAG;
77
qemu_irq_lower(s->irq);
78
}
72
+
79
+
73
# Data-processing (register)
80
if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
74
81
if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
75
%imm5_12_6 12:3 6:2
82
s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
76
@@ -XXX,XX +XXX,XX @@
83
@@ -XXX,XX +XXX,XX @@ static const TypeInfo allwinner_i2c_type_info = {
77
@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
84
.class_init = allwinner_i2c_class_init,
78
&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
85
};
79
86
80
+@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
87
+static void allwinner_i2c_sun6i_init(Object *obj)
81
+ &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
88
+{
89
+ AWI2CState *s = AW_I2C(obj);
82
+
90
+
83
{
91
+ s->irq_clear_inverted = true;
84
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
85
AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
86
}
87
BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
88
{
89
+ # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
90
+ # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
91
+ # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
92
+ # they explicitly call unallocated_encoding() for cases that must UNDEF
93
+ # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
94
+ # the rest fall through (where ORR_rrri and MOV_rxri will end up
95
+ # handling them as r13 and r15 accesses with the same semantics as A32).
96
+ [
97
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
98
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
99
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
100
+
101
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
102
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
103
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
104
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
105
+ ]
106
+
107
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
108
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
109
}
110
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/arm/mve_helper.c
113
+++ b/target/arm/mve_helper.c
114
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
115
mve_advance_vpt(env);
116
return rdm;
117
}
118
+
119
+uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
120
+{
121
+ return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
122
+}
92
+}
123
+
93
+
124
+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
94
+static const TypeInfo allwinner_i2c_sun6i_type_info = {
125
+{
95
+ .name = TYPE_AW_I2C_SUN6I,
126
+ return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
96
+ .parent = TYPE_SYS_BUS_DEVICE,
127
+}
97
+ .instance_size = sizeof(AWI2CState),
128
diff --git a/target/arm/translate.c b/target/arm/translate.c
98
+ .instance_init = allwinner_i2c_sun6i_init,
129
index XXXXXXX..XXXXXXX 100644
99
+ .class_init = allwinner_i2c_class_init,
130
--- a/target/arm/translate.c
100
+};
131
+++ b/target/arm/translate.c
101
+
132
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
102
static void allwinner_i2c_register_types(void)
133
return true;
103
{
104
type_register_static(&allwinner_i2c_type_info);
105
+ type_register_static(&allwinner_i2c_sun6i_type_info);
134
}
106
}
135
107
136
+/*
108
type_init(allwinner_i2c_register_types)
137
+ * v8.1M MVE wide-shifts
138
+ */
139
+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
140
+ WideShiftImmFn *fn)
141
+{
142
+ TCGv_i64 rda;
143
+ TCGv_i32 rdalo, rdahi;
144
+
145
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
146
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
147
+ return false;
148
+ }
149
+ if (a->rdahi == 15) {
150
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
151
+ return false;
152
+ }
153
+ if (!dc_isar_feature(aa32_mve, s) ||
154
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
155
+ a->rdahi == 13) {
156
+ /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
157
+ unallocated_encoding(s);
158
+ return true;
159
+ }
160
+
161
+ if (a->shim == 0) {
162
+ a->shim = 32;
163
+ }
164
+
165
+ rda = tcg_temp_new_i64();
166
+ rdalo = load_reg(s, a->rdalo);
167
+ rdahi = load_reg(s, a->rdahi);
168
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
169
+
170
+ fn(rda, rda, a->shim);
171
+
172
+ tcg_gen_extrl_i64_i32(rdalo, rda);
173
+ tcg_gen_extrh_i64_i32(rdahi, rda);
174
+ store_reg(s, a->rdalo, rdalo);
175
+ store_reg(s, a->rdahi, rdahi);
176
+ tcg_temp_free_i64(rda);
177
+
178
+ return true;
179
+}
180
+
181
+static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
182
+{
183
+ return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
184
+}
185
+
186
+static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
187
+{
188
+ return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
189
+}
190
+
191
+static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
192
+{
193
+ return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
194
+}
195
+
196
+static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
197
+{
198
+ gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
199
+}
200
+
201
+static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
202
+{
203
+ return do_mve_shl_ri(s, a, gen_mve_sqshll);
204
+}
205
+
206
+static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
207
+{
208
+ gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
209
+}
210
+
211
+static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
212
+{
213
+ return do_mve_shl_ri(s, a, gen_mve_uqshll);
214
+}
215
+
216
+static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
217
+{
218
+ return do_mve_shl_ri(s, a, gen_srshr64_i64);
219
+}
220
+
221
+static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
222
+{
223
+ return do_mve_shl_ri(s, a, gen_urshr64_i64);
224
+}
225
+
226
/*
227
* Multiply and multiply accumulate
228
*/
229
--
109
--
230
2.20.1
110
2.34.1
231
232
diff view generated by jsdifflib
[PULL 05/24] target/arm: Check NaN mode before silencing NaN
[PULL 21/21] hw: arm: allwinner-h3: Fix and complete H3 i2c devices
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
1
From: qianfan Zhao <qianfanguijin@163.com>
2
2
3
If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
3
Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi.
4
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
4
The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear
5
assert due to fpst->default_nan_mode being set.
5
control register's INT_FLAG bit.
6
6
7
To avoid this, we check to see what NaN mode we're running in before we call
7
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
8
floatxx_silence_nan().
8
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
9
10
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
11
---
16
target/arm/helper-a64.c | 12 +++++++++---
12
include/hw/arm/allwinner-h3.h | 6 ++++++
17
target/arm/vfp_helper.c | 24 ++++++++++++++++++------
13
hw/arm/allwinner-h3.c | 29 +++++++++++++++++++++++++----
18
2 files changed, 27 insertions(+), 9 deletions(-)
14
2 files changed, 31 insertions(+), 4 deletions(-)
19
15
20
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
16
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
21
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper-a64.c
18
--- a/include/hw/arm/allwinner-h3.h
23
+++ b/target/arm/helper-a64.c
19
+++ b/include/hw/arm/allwinner-h3.h
24
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
20
@@ -XXX,XX +XXX,XX @@ enum {
25
float16 nan = a;
21
AW_H3_DEV_UART3,
26
if (float16_is_signaling_nan(a, fpst)) {
22
AW_H3_DEV_EMAC,
27
float_raise(float_flag_invalid, fpst);
23
AW_H3_DEV_TWI0,
28
- nan = float16_silence_nan(a, fpst);
24
+ AW_H3_DEV_TWI1,
29
+ if (!fpst->default_nan_mode) {
25
+ AW_H3_DEV_TWI2,
30
+ nan = float16_silence_nan(a, fpst);
26
AW_H3_DEV_DRAMCOM,
31
+ }
27
AW_H3_DEV_DRAMCTL,
32
}
28
AW_H3_DEV_DRAMPHY,
33
if (fpst->default_nan_mode) {
29
@@ -XXX,XX +XXX,XX @@ enum {
34
nan = float16_default_nan(fpst);
30
AW_H3_DEV_GIC_VCPU,
35
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
31
AW_H3_DEV_RTC,
36
float32 nan = a;
32
AW_H3_DEV_CPUCFG,
37
if (float32_is_signaling_nan(a, fpst)) {
33
+ AW_H3_DEV_R_TWI,
38
float_raise(float_flag_invalid, fpst);
34
AW_H3_DEV_SDRAM
39
- nan = float32_silence_nan(a, fpst);
35
};
40
+ if (!fpst->default_nan_mode) {
36
41
+ nan = float32_silence_nan(a, fpst);
37
@@ -XXX,XX +XXX,XX @@ struct AwH3State {
42
+ }
38
AwSidState sid;
43
}
39
AwSdHostState mmc0;
44
if (fpst->default_nan_mode) {
40
AWI2CState i2c0;
45
nan = float32_default_nan(fpst);
41
+ AWI2CState i2c1;
46
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
42
+ AWI2CState i2c2;
47
float64 nan = a;
43
+ AWI2CState r_twi;
48
if (float64_is_signaling_nan(a, fpst)) {
44
AwSun8iEmacState emac;
49
float_raise(float_flag_invalid, fpst);
45
AwRtcState rtc;
50
- nan = float64_silence_nan(a, fpst);
46
GICState gic;
51
+ if (!fpst->default_nan_mode) {
47
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
52
+ nan = float64_silence_nan(a, fpst);
53
+ }
54
}
55
if (fpst->default_nan_mode) {
56
nan = float64_default_nan(fpst);
57
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
58
index XXXXXXX..XXXXXXX 100644
48
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/vfp_helper.c
49
--- a/hw/arm/allwinner-h3.c
60
+++ b/target/arm/vfp_helper.c
50
+++ b/hw/arm/allwinner-h3.c
61
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
51
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
62
float16 nan = f16;
52
[AW_H3_DEV_UART2] = 0x01c28800,
63
if (float16_is_signaling_nan(f16, fpst)) {
53
[AW_H3_DEV_UART3] = 0x01c28c00,
64
float_raise(float_flag_invalid, fpst);
54
[AW_H3_DEV_TWI0] = 0x01c2ac00,
65
- nan = float16_silence_nan(f16, fpst);
55
+ [AW_H3_DEV_TWI1] = 0x01c2b000,
66
+ if (!fpst->default_nan_mode) {
56
+ [AW_H3_DEV_TWI2] = 0x01c2b400,
67
+ nan = float16_silence_nan(f16, fpst);
57
[AW_H3_DEV_EMAC] = 0x01c30000,
68
+ }
58
[AW_H3_DEV_DRAMCOM] = 0x01c62000,
69
}
59
[AW_H3_DEV_DRAMCTL] = 0x01c63000,
70
if (fpst->default_nan_mode) {
60
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
71
nan = float16_default_nan(fpst);
61
[AW_H3_DEV_GIC_VCPU] = 0x01c86000,
72
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
62
[AW_H3_DEV_RTC] = 0x01f00000,
73
float32 nan = f32;
63
[AW_H3_DEV_CPUCFG] = 0x01f01c00,
74
if (float32_is_signaling_nan(f32, fpst)) {
64
+ [AW_H3_DEV_R_TWI] = 0x01f02400,
75
float_raise(float_flag_invalid, fpst);
65
[AW_H3_DEV_SDRAM] = 0x40000000
76
- nan = float32_silence_nan(f32, fpst);
66
};
77
+ if (!fpst->default_nan_mode) {
67
78
+ nan = float32_silence_nan(f32, fpst);
68
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
79
+ }
69
{ "uart1", 0x01c28400, 1 * KiB },
80
}
70
{ "uart2", 0x01c28800, 1 * KiB },
81
if (fpst->default_nan_mode) {
71
{ "uart3", 0x01c28c00, 1 * KiB },
82
nan = float32_default_nan(fpst);
72
- { "twi1", 0x01c2b000, 1 * KiB },
83
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
73
- { "twi2", 0x01c2b400, 1 * KiB },
84
float64 nan = f64;
74
{ "scr", 0x01c2c400, 1 * KiB },
85
if (float64_is_signaling_nan(f64, fpst)) {
75
{ "gpu", 0x01c40000, 64 * KiB },
86
float_raise(float_flag_invalid, fpst);
76
{ "hstmr", 0x01c60000, 4 * KiB },
87
- nan = float64_silence_nan(f64, fpst);
77
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
88
+ if (!fpst->default_nan_mode) {
78
{ "r_prcm", 0x01f01400, 1 * KiB },
89
+ nan = float64_silence_nan(f64, fpst);
79
{ "r_twd", 0x01f01800, 1 * KiB },
90
+ }
80
{ "r_cir-rx", 0x01f02000, 1 * KiB },
91
}
81
- { "r_twi", 0x01f02400, 1 * KiB },
92
if (fpst->default_nan_mode) {
82
{ "r_uart", 0x01f02800, 1 * KiB },
93
nan = float64_default_nan(fpst);
83
{ "r_pio", 0x01f02c00, 1 * KiB },
94
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
84
{ "r_pwm", 0x01f03800, 1 * KiB },
95
float16 nan = f16;
85
@@ -XXX,XX +XXX,XX @@ enum {
96
if (float16_is_signaling_nan(f16, s)) {
86
AW_H3_GIC_SPI_UART2 = 2,
97
float_raise(float_flag_invalid, s);
87
AW_H3_GIC_SPI_UART3 = 3,
98
- nan = float16_silence_nan(f16, s);
88
AW_H3_GIC_SPI_TWI0 = 6,
99
+ if (!s->default_nan_mode) {
89
+ AW_H3_GIC_SPI_TWI1 = 7,
100
+ nan = float16_silence_nan(f16, fpstp);
90
+ AW_H3_GIC_SPI_TWI2 = 8,
101
+ }
91
AW_H3_GIC_SPI_TIMER0 = 18,
102
}
92
AW_H3_GIC_SPI_TIMER1 = 19,
103
if (s->default_nan_mode) {
93
+ AW_H3_GIC_SPI_R_TWI = 44,
104
nan = float16_default_nan(s);
94
AW_H3_GIC_SPI_MMC0 = 60,
105
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
95
AW_H3_GIC_SPI_EHCI0 = 72,
106
float32 nan = f32;
96
AW_H3_GIC_SPI_OHCI0 = 73,
107
if (float32_is_signaling_nan(f32, s)) {
97
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
108
float_raise(float_flag_invalid, s);
98
109
- nan = float32_silence_nan(f32, s);
99
object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
110
+ if (!s->default_nan_mode) {
100
111
+ nan = float32_silence_nan(f32, fpstp);
101
- object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
112
+ }
102
+ object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
113
}
103
+ object_initialize_child(obj, "twi1", &s->i2c1, TYPE_AW_I2C_SUN6I);
114
if (s->default_nan_mode) {
104
+ object_initialize_child(obj, "twi2", &s->i2c2, TYPE_AW_I2C_SUN6I);
115
nan = float32_default_nan(s);
105
+ object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I);
116
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
106
}
117
float64 nan = f64;
107
118
if (float64_is_signaling_nan(f64, s)) {
108
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
119
float_raise(float_flag_invalid, s);
109
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
120
- nan = float64_silence_nan(f64, s);
110
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
121
+ if (!s->default_nan_mode) {
111
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
122
+ nan = float64_silence_nan(f64, fpstp);
112
123
+ }
113
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal);
124
}
114
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]);
125
if (s->default_nan_mode) {
115
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0,
126
nan = float64_default_nan(s);
116
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1));
117
+
118
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal);
119
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]);
120
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0,
121
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2));
122
+
123
+ sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal);
124
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]);
125
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0,
126
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI));
127
+
128
/* Unimplemented devices */
129
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
130
create_unimplemented_device(unimplemented[i].device_name,
127
--
131
--
128
2.20.1
132
2.34.1
129
130
diff view generated by jsdifflib
[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
Deleted patch
1
The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
2
insns had some bugs:
3
* the 32x32 multiply of elements was being done as 32x32->32,
4
not 32x32->64
5
* we were incorrectly maintaining the accumulator in its full
6
72-bit form across all 4 beats of the insn; in the pseudocode
7
it is squashed back into the 64 bits of the RdaHi:RdaLo
8
registers after each beat
9
1
10
In particular, fixing the second of these allows us to recast
11
the implementation to avoid 128-bit arithmetic entirely.
12
13
Since the element size here is always 4, we can also drop the
14
parameterization of ESIZE to make the code a little more readable.
15
16
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
20
---
21
target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
22
1 file changed, 21 insertions(+), 17 deletions(-)
23
24
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/mve_helper.c
27
+++ b/target/arm/mve_helper.c
28
@@ -XXX,XX +XXX,XX @@
29
*/
30
31
#include "qemu/osdep.h"
32
-#include "qemu/int128.h"
33
#include "cpu.h"
34
#include "internals.h"
35
#include "vec_internal.h"
36
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
37
DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
38
39
/*
40
- * Rounding multiply add long dual accumulate high: we must keep
41
- * a 72-bit internal accumulator value and return the top 64 bits.
42
+ * Rounding multiply add long dual accumulate high. In the pseudocode
43
+ * this is implemented with a 72-bit internal accumulator value of which
44
+ * the top 64 bits are returned. We optimize this to avoid having to
45
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
46
+ * is squashed back into 64-bits after each beat.
47
*/
48
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \
49
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \
50
uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
51
void *vm, uint64_t a) \
52
{ \
53
uint16_t mask = mve_element_mask(env); \
54
unsigned e; \
55
TYPE *n = vn, *m = vm; \
56
- Int128 acc = int128_lshift(TO128(a), 8); \
57
- for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
58
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
59
if (mask & 1) { \
60
+ LTYPE mul; \
61
if (e & 1) { \
62
- acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
63
- m[H##ESIZE(e)])); \
64
+ mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \
65
+ if (SUB) { \
66
+ mul = -mul; \
67
+ } \
68
} else { \
69
- acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
70
- m[H##ESIZE(e)])); \
71
+ mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \
72
} \
73
- acc = int128_add(acc, int128_make64(1 << 7)); \
74
+ mul = (mul >> 8) + ((mul >> 7) & 1); \
75
+ a += mul; \
76
} \
77
} \
78
mve_advance_vpt(env); \
79
- return int128_getlo(int128_rshift(acc, 8)); \
80
+ return a; \
81
}
82
83
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
84
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
85
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
86
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
87
88
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
89
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
90
91
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
92
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
93
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
94
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
95
96
/* Vector add across vector */
97
#define DO_VADDV(OP, ESIZE, TYPE) \
98
--
99
2.20.1
100
101
diff view generated by jsdifflib
[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
Deleted patch
1
The A64 AdvSIMD modified-immediate grouping uses almost the same
2
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
3
which we add the AArch64-specific case for cmode 15 op 1) instead of
4
reimplementing it all.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
9
---
10
target/arm/translate.h | 3 +-
11
target/arm/translate-a64.c | 86 ++++----------------------------------
12
target/arm/translate.c | 17 +++++++-
13
3 files changed, 24 insertions(+), 82 deletions(-)
14
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.h
18
+++ b/target/arm/translate.h
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
20
* VMVN and VBIC (when cmode < 14 && op == 1).
21
*
22
* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
23
- * callers must catch this.
24
+ * callers must catch this; we return the 64-bit constant value defined
25
+ * for AArch64.
26
*
27
* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
28
* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
29
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate-a64.c
32
+++ b/target/arm/translate-a64.c
33
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
34
{
35
int rd = extract32(insn, 0, 5);
36
int cmode = extract32(insn, 12, 4);
37
- int cmode_3_1 = extract32(cmode, 1, 3);
38
- int cmode_0 = extract32(cmode, 0, 1);
39
int o2 = extract32(insn, 11, 1);
40
uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
41
bool is_neg = extract32(insn, 29, 1);
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
43
return;
44
}
45
46
- /* See AdvSIMDExpandImm() in ARM ARM */
47
- switch (cmode_3_1) {
48
- case 0: /* Replicate(Zeros(24):imm8, 2) */
49
- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
50
- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
51
- case 3: /* Replicate(imm8:Zeros(24), 2) */
52
- {
53
- int shift = cmode_3_1 * 8;
54
- imm = bitfield_replicate(abcdefgh << shift, 32);
55
- break;
56
- }
57
- case 4: /* Replicate(Zeros(8):imm8, 4) */
58
- case 5: /* Replicate(imm8:Zeros(8), 4) */
59
- {
60
- int shift = (cmode_3_1 & 0x1) * 8;
61
- imm = bitfield_replicate(abcdefgh << shift, 16);
62
- break;
63
- }
64
- case 6:
65
- if (cmode_0) {
66
- /* Replicate(Zeros(8):imm8:Ones(16), 2) */
67
- imm = (abcdefgh << 16) | 0xffff;
68
- } else {
69
- /* Replicate(Zeros(16):imm8:Ones(8), 2) */
70
- imm = (abcdefgh << 8) | 0xff;
71
- }
72
- imm = bitfield_replicate(imm, 32);
73
- break;
74
- case 7:
75
- if (!cmode_0 && !is_neg) {
76
- imm = bitfield_replicate(abcdefgh, 8);
77
- } else if (!cmode_0 && is_neg) {
78
- int i;
79
- imm = 0;
80
- for (i = 0; i < 8; i++) {
81
- if ((abcdefgh) & (1 << i)) {
82
- imm |= 0xffULL << (i * 8);
83
- }
84
- }
85
- } else if (cmode_0) {
86
- if (is_neg) {
87
- imm = (abcdefgh & 0x3f) << 48;
88
- if (abcdefgh & 0x80) {
89
- imm |= 0x8000000000000000ULL;
90
- }
91
- if (abcdefgh & 0x40) {
92
- imm |= 0x3fc0000000000000ULL;
93
- } else {
94
- imm |= 0x4000000000000000ULL;
95
- }
96
- } else {
97
- if (o2) {
98
- /* FMOV (vector, immediate) - half-precision */
99
- imm = vfp_expand_imm(MO_16, abcdefgh);
100
- /* now duplicate across the lanes */
101
- imm = bitfield_replicate(imm, 16);
102
- } else {
103
- imm = (abcdefgh & 0x3f) << 19;
104
- if (abcdefgh & 0x80) {
105
- imm |= 0x80000000;
106
- }
107
- if (abcdefgh & 0x40) {
108
- imm |= 0x3e000000;
109
- } else {
110
- imm |= 0x40000000;
111
- }
112
- imm |= (imm << 32);
113
- }
114
- }
115
- }
116
- break;
117
- default:
118
- g_assert_not_reached();
119
- }
120
-
121
- if (cmode_3_1 != 7 && is_neg) {
122
- imm = ~imm;
123
+ if (cmode == 15 && o2 && !is_neg) {
124
+ /* FMOV (vector, immediate) - half-precision */
125
+ imm = vfp_expand_imm(MO_16, abcdefgh);
126
+ /* now duplicate across the lanes */
127
+ imm = bitfield_replicate(imm, 16);
128
+ } else {
129
+ imm = asimd_imm_const(abcdefgh, cmode, is_neg);
130
}
131
132
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
133
diff --git a/target/arm/translate.c b/target/arm/translate.c
134
index XXXXXXX..XXXXXXX 100644
135
--- a/target/arm/translate.c
136
+++ b/target/arm/translate.c
137
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
138
case 14:
139
if (op) {
140
/*
141
- * This is the only case where the top and bottom 32 bits
142
- * of the encoded constant differ.
143
+ * This and cmode == 15 op == 1 are the only cases where
144
+ * the top and bottom 32 bits of the encoded constant differ.
145
*/
146
uint64_t imm64 = 0;
147
int n;
148
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
149
imm |= (imm << 8) | (imm << 16) | (imm << 24);
150
break;
151
case 15:
152
+ if (op) {
153
+ /* Reserved encoding for AArch32; valid for AArch64 */
154
+ uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
155
+ if (imm & 0x80) {
156
+ imm64 |= 0x8000000000000000ULL;
157
+ }
158
+ if (imm & 0x40) {
159
+ imm64 |= 0x3fc0000000000000ULL;
160
+ } else {
161
+ imm64 |= 0x4000000000000000ULL;
162
+ }
163
+ return imm64;
164
+ }
165
imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
166
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
167
break;
168
--
169
2.20.1
170
171
diff view generated by jsdifflib
[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
Deleted patch
1
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
2
and VQSHLU.
3
1
4
The size-and-immediate encoding here is the same as Neon, and we
5
handle it the same way neon-dp.decode does.
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
10
---
11
target/arm/helper-mve.h | 16 +++++++++++
12
target/arm/mve.decode | 23 +++++++++++++++
13
target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++
14
target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
15
4 files changed, 147 insertions(+)
16
17
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper-mve.h
20
+++ b/target/arm/helper-mve.h
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
25
+
26
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+
34
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/mve.decode
44
+++ b/target/arm/mve.decode
45
@@ -XXX,XX +XXX,XX @@
46
&2op qd qm qn size
47
&2scalar qd qn rm size
48
&1imm qd imm cmode op
49
+&2shift qd qm shift size
50
51
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
52
# Note that both Rn and Qd are 3 bits only (no D bit)
53
@@ -XXX,XX +XXX,XX @@
54
@2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
55
@2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
56
57
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
58
+@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
59
+@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
60
+
61
# Vector loads and stores
62
63
# Widening loads and narrowing stores:
64
@@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
65
# So we have a single decode line and check the cmode/op in the
66
# trans function.
67
Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
68
+
69
+# Shifts by immediate
70
+
71
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
72
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
73
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
74
+
75
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
76
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
77
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
78
+
79
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
80
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
81
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
82
+
83
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
84
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
85
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
86
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/mve_helper.c
89
+++ b/target/arm/mve_helper.c
90
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
91
WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
92
#define DO_UQRSHL_OP(N, M, satp) \
93
WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
94
+#define DO_SUQSHL_OP(N, M, satp) \
95
+ WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
96
97
DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
98
DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
99
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
100
DO_VADDV(vaddvub, 1, uint8_t)
101
DO_VADDV(vaddvuh, 2, uint16_t)
102
DO_VADDV(vaddvuw, 4, uint32_t)
103
+
104
+/* Shifts by immediate */
105
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
106
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
107
+ void *vm, uint32_t shift) \
108
+ { \
109
+ TYPE *d = vd, *m = vm; \
110
+ uint16_t mask = mve_element_mask(env); \
111
+ unsigned e; \
112
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
113
+ mergemask(&d[H##ESIZE(e)], \
114
+ FN(m[H##ESIZE(e)], shift), mask); \
115
+ } \
116
+ mve_advance_vpt(env); \
117
+ }
118
+
119
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \
120
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
121
+ void *vm, uint32_t shift) \
122
+ { \
123
+ TYPE *d = vd, *m = vm; \
124
+ uint16_t mask = mve_element_mask(env); \
125
+ unsigned e; \
126
+ bool qc = false; \
127
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
128
+ bool sat = false; \
129
+ mergemask(&d[H##ESIZE(e)], \
130
+ FN(m[H##ESIZE(e)], shift, &sat), mask); \
131
+ qc |= sat & mask & 1; \
132
+ } \
133
+ if (qc) { \
134
+ env->vfp.qc[0] = qc; \
135
+ } \
136
+ mve_advance_vpt(env); \
137
+ }
138
+
139
+/* provide unsigned 2-op shift helpers for all sizes */
140
+#define DO_2SHIFT_U(OP, FN) \
141
+ DO_2SHIFT(OP##b, 1, uint8_t, FN) \
142
+ DO_2SHIFT(OP##h, 2, uint16_t, FN) \
143
+ DO_2SHIFT(OP##w, 4, uint32_t, FN)
144
+
145
+#define DO_2SHIFT_SAT_U(OP, FN) \
146
+ DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
147
+ DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \
148
+ DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
149
+#define DO_2SHIFT_SAT_S(OP, FN) \
150
+ DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \
151
+ DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \
152
+ DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
153
+
154
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
155
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
156
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
157
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
158
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/target/arm/translate-mve.c
161
+++ b/target/arm/translate-mve.c
162
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
163
typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
164
typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
165
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
166
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
167
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
168
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
169
typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
170
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
171
}
172
return do_1imm(s, a, fn);
173
}
174
+
175
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
176
+ bool negateshift)
177
+{
178
+ TCGv_ptr qd, qm;
179
+ int shift = a->shift;
180
+
181
+ if (!dc_isar_feature(aa32_mve, s) ||
182
+ !mve_check_qreg_bank(s, a->qd | a->qm) ||
183
+ !fn) {
184
+ return false;
185
+ }
186
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
187
+ return true;
188
+ }
189
+
190
+ /*
191
+ * When we handle a right shift insn using a left-shift helper
192
+ * which permits a negative shift count to indicate a right-shift,
193
+ * we must negate the shift count.
194
+ */
195
+ if (negateshift) {
196
+ shift = -shift;
197
+ }
198
+
199
+ qd = mve_qreg_ptr(a->qd);
200
+ qm = mve_qreg_ptr(a->qm);
201
+ fn(cpu_env, qd, qm, tcg_constant_i32(shift));
202
+ tcg_temp_free_ptr(qd);
203
+ tcg_temp_free_ptr(qm);
204
+ mve_update_eci(s);
205
+ return true;
206
+}
207
+
208
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \
209
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
210
+ { \
211
+ static MVEGenTwoOpShiftFn * const fns[] = { \
212
+ gen_helper_mve_##FN##b, \
213
+ gen_helper_mve_##FN##h, \
214
+ gen_helper_mve_##FN##w, \
215
+ NULL, \
216
+ }; \
217
+ return do_2shift(s, a, fns[a->size], NEGATESHIFT); \
218
+ }
219
+
220
+DO_2SHIFT(VSHLI, vshli_u, false)
221
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
222
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
223
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
224
--
225
2.20.1
226
227
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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