Series comparison

-[PULL 00/24] target-arm queue
+[PULL 00/33] target-arm queue
-The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
+The following changes since commit bf4460a8d9a86f6cfe05d7a7f470c48e3a93d8b2:
-  Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
+  Merge tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu into staging (2023-02-03 09:30:45 +0000)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230203
-for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
+for you to fetch changes up to bb18151d8bd9bedc497ee9d4e8d81b39a4e5bbf6:
-  target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
+  target/arm: Enable FEAT_FGT on '-cpu max' (2023-02-03 12:59:24 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * more MVE instructions
+ * Fix physical address resolution for Stage2
- * hw/gpio/gpio_pwr: use shutdown function for reboot
+ * pl011: refactoring, implement reset method
- * target/arm: Check NaN mode before silencing NaN
+ * Support GICv3 with hvf acceleration
- * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
+ * sbsa-ref: remove cortex-a76 from list of supported cpus
- * hw/arm: Add basic power management to raspi.
+ * Correct syndrome for ATS12NSO* traps at Secure EL1
- * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
+ * Fix priority of HSTR_EL2 traps vs UNDEFs
  * Implement FEAT_FGT for '-cpu max'
 ----------------------------------------------------------------
-Joe Komlodi (1):
+Alexander Graf (3):
-      target/arm: Check NaN mode before silencing NaN
+      hvf: arm: Add support for GICv3
       hw/arm/virt: Consolidate GIC finalize logic
       hw/arm/virt: Make accels in GIC finalize logic explicit
-Maxim Uvarov (1):
+Evgeny Iakovlev (4):
-      hw/gpio/gpio_pwr: use shutdown function for reboot
+      hw/char/pl011: refactor FIFO depth handling code
       hw/char/pl011: add post_load hook for backwards-compatibility
       hw/char/pl011: implement a reset method
       hw/char/pl011: better handling of FIFO flags on LCR reset
-Nolan Leake (1):
+Marcin Juszkiewicz (1):
-      hw/arm: Add basic power management to raspi.
+      sbsa-ref: remove cortex-a76 from list of supported cpus
-Patrick Venture (2):
+Peter Maydell (23):
-      docs/system/arm: Add quanta-q7l1-bmc reference
+      target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly
-      docs/system/arm: Add quanta-gbs-bmc reference
+      target/arm: Correct syndrome for ATS12NSO* at Secure EL1
       target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}
       target/arm: Move do_coproc_insn() syndrome calculation earlier
       target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
       target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
       target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
       target/arm: Define the FEAT_FGT registers
       target/arm: Implement FGT trapping infrastructure
       target/arm: Mark up sysregs for HFGRTR bits 0..11
       target/arm: Mark up sysregs for HFGRTR bits 12..23
       target/arm: Mark up sysregs for HFGRTR bits 24..35
       target/arm: Mark up sysregs for HFGRTR bits 36..63
       target/arm: Mark up sysregs for HDFGRTR bits 0..11
       target/arm: Mark up sysregs for HDFGRTR bits 12..63
       target/arm: Mark up sysregs for HFGITR bits 0..11
       target/arm: Mark up sysregs for HFGITR bits 12..17
       target/arm: Mark up sysregs for HFGITR bits 18..47
       target/arm: Mark up sysregs for HFGITR bits 48..63
       target/arm: Implement the HFGITR_EL2.ERET trap
       target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
       target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
       target/arm: Enable FEAT_FGT on '-cpu max'
-Peter Maydell (18):
+Richard Henderson (2):
-      target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
+      hw/arm: Use TYPE_ARM_SMMUV3
-      target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
+      target/arm: Fix physical address resolution for Stage2
       target/arm: Make asimd_imm_const() public
       target/arm: Use asimd_imm_const for A64 decode
       target/arm: Use dup_const() instead of bitfield_replicate()
       target/arm: Implement MVE logical immediate insns
       target/arm: Implement MVE vector shift left by immediate insns
       target/arm: Implement MVE vector shift right by immediate insns
       target/arm: Implement MVE VSHLL
       target/arm: Implement MVE VSRI, VSLI
       target/arm: Implement MVE VSHRN, VRSHRN
       target/arm: Implement MVE saturating narrowing shifts
       target/arm: Implement MVE VSHLC
       target/arm: Implement MVE VADDLV
       target/arm: Implement MVE long shifts by immediate
       target/arm: Implement MVE long shifts by register
       target/arm: Implement MVE shifts by immediate
       target/arm: Implement MVE shifts by register
-Philippe Mathieu-Daudé (1):
+ docs/system/arm/emulation.rst |   1 +
-      tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
+ include/hw/arm/virt.h         |  15 +-
+ include/hw/char/pl011.h       |   5 +-
- docs/system/arm/aspeed.rst             |   1 +
+ target/arm/cpregs.h           | 484 +++++++++++++++++++++++++++++++++++++++++-
- docs/system/arm/nuvoton.rst            |   5 +-
+ target/arm/cpu.h              |  18 ++
- include/hw/arm/bcm2835_peripherals.h   |   3 +-
+ target/arm/internals.h        |  20 ++
- include/hw/misc/bcm2835_powermgt.h     |  29 ++
+ target/arm/syndrome.h         |  10 +
- target/arm/helper-mve.h                | 108 +++++++
+ target/arm/translate.h        |   6 +
- target/arm/translate.h                 |  41 +++
+ hw/arm/sbsa-ref.c             |   4 +-
- target/arm/mve.decode                  | 177 ++++++++++-
+ hw/arm/virt.c                 | 203 +++++++++---------
- target/arm/t32.decode                  |  71 ++++-
+ hw/char/pl011.c               |  93 ++++++--
- hw/arm/bcm2835_peripherals.c           |  13 +-
+ hw/intc/arm_gicv3_cpuif.c     |  18 +-
- hw/gpio/gpio_pwr.c                     |   2 +-
+ target/arm/cpu64.c            |   1 +
- hw/misc/bcm2835_powermgt.c             | 160 ++++++++++
+ target/arm/debug_helper.c     |  46 +++-
- target/arm/helper-a64.c                |  12 +-
+ target/arm/helper.c           | 245 ++++++++++++++++++++-
- target/arm/mve_helper.c                | 524 +++++++++++++++++++++++++++++++--
+ target/arm/hvf/hvf.c          | 151 +++++++++++++
- target/arm/translate-a64.c             |  86 +-----
+ target/arm/op_helper.c        |  58 ++++-
- target/arm/translate-mve.c             | 261 +++++++++++++++-
+ target/arm/ptw.c              |   2 +-
- target/arm/translate-neon.c            |  81 -----
+ target/arm/translate-a64.c    |  22 +-
- target/arm/translate.c                 | 327 +++++++++++++++++++-
+ target/arm/translate.c        | 125 +++++++----
- target/arm/vfp_helper.c                |  24 +-
+ target/arm/hvf/trace-events   |   2 +
- hw/misc/meson.build                    |   1 +
+files changed, 1340 insertions(+), 189 deletions(-)
  tests/acceptance/boot_linux_console.py |  43 +++
 files changed, 1760 insertions(+), 209 deletions(-)
  create mode 100644 include/hw/misc/bcm2835_powermgt.h
  create mode 100644 hw/misc/bcm2835_powermgt.c

-[PULL 05/24] target/arm: Check NaN mode before silencing NaN
+[PULL 01/33] hw/arm: Use TYPE_ARM_SMMUV3
-From: Joe Komlodi <joe.komlodi@xilinx.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
+Use the macro instead of two explicit string literals.
 FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
 assert due to fpst->default_nan_mode being set.
-To avoid this, we check to see what NaN mode we're running in before we call
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-floatxx_silence_nan().
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
+Message-id: 20230124232059.4017615-1-richard.henderson@linaro.org
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper-a64.c | 12 +++++++++---
+ hw/arm/sbsa-ref.c | 3 ++-
- target/arm/vfp_helper.c | 24 ++++++++++++++++++------
+ hw/arm/virt.c     | 2 +-
-files changed, 27 insertions(+), 9 deletions(-)
+files changed, 3 insertions(+), 2 deletions(-)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
+diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
+--- a/hw/arm/sbsa-ref.c
-+++ b/target/arm/helper-a64.c
++++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
+@@ -XXX,XX +XXX,XX @@
-         float16 nan = a;
+ #include "exec/hwaddr.h"
-         if (float16_is_signaling_nan(a, fpst)) {
+ #include "kvm_arm.h"
-             float_raise(float_flag_invalid, fpst);
+ #include "hw/arm/boot.h"
--            nan = float16_silence_nan(a, fpst);
++#include "hw/arm/smmuv3.h"
-+            if (!fpst->default_nan_mode) {
+ #include "hw/block/flash.h"
-+                nan = float16_silence_nan(a, fpst);
+ #include "hw/boards.h"
-+            }
+ #include "hw/ide/internal.h"
-         }
+@@ -XXX,XX +XXX,XX @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
-         if (fpst->default_nan_mode) {
+     DeviceState *dev;
-             nan = float16_default_nan(fpst);
+     int i;
-@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
-         float32 nan = a;
+-    dev = qdev_new("arm-smmuv3");
-         if (float32_is_signaling_nan(a, fpst)) {
++    dev = qdev_new(TYPE_ARM_SMMUV3);
-             float_raise(float_flag_invalid, fpst);
--            nan = float32_silence_nan(a, fpst);
+     object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
-+            if (!fpst->default_nan_mode) {
+                              &error_abort);
-+                nan = float32_silence_nan(a, fpst);
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 +            }
          }
          if (fpst->default_nan_mode) {
              nan = float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
          float64 nan = a;
          if (float64_is_signaling_nan(a, fpst)) {
              float_raise(float_flag_invalid, fpst);
 -            nan = float64_silence_nan(a, fpst);
 +            if (!fpst->default_nan_mode) {
 +                nan = float64_silence_nan(a, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan = float64_default_nan(fpst);
 diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/vfp_helper.c
+--- a/hw/arm/virt.c
-+++ b/target/arm/vfp_helper.c
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
+@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
-         float16 nan = f16;
+         return;
-         if (float16_is_signaling_nan(f16, fpst)) {
+     }
-             float_raise(float_flag_invalid, fpst);
--            nan = float16_silence_nan(f16, fpst);
+-    dev = qdev_new("arm-smmuv3");
-+            if (!fpst->default_nan_mode) {
++    dev = qdev_new(TYPE_ARM_SMMUV3);
-+                nan = float16_silence_nan(f16, fpst);
-+            }
+     object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
-         }
+                              &error_abort);
          if (fpst->default_nan_mode) {
              nan =  float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
          float32 nan = f32;
          if (float32_is_signaling_nan(f32, fpst)) {
              float_raise(float_flag_invalid, fpst);
 -            nan = float32_silence_nan(f32, fpst);
 +            if (!fpst->default_nan_mode) {
 +                nan = float32_silence_nan(f32, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan =  float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
          float64 nan = f64;
          if (float64_is_signaling_nan(f64, fpst)) {
              float_raise(float_flag_invalid, fpst);
 -            nan = float64_silence_nan(f64, fpst);
 +            if (!fpst->default_nan_mode) {
 +                nan = float64_silence_nan(f64, fpst);
 +            }
          }
          if (fpst->default_nan_mode) {
              nan =  float64_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
          float16 nan = f16;
          if (float16_is_signaling_nan(f16, s)) {
              float_raise(float_flag_invalid, s);
 -            nan = float16_silence_nan(f16, s);
 +            if (!s->default_nan_mode) {
 +                nan = float16_silence_nan(f16, fpstp);
 +            }
          }
          if (s->default_nan_mode) {
              nan =  float16_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
          float32 nan = f32;
          if (float32_is_signaling_nan(f32, s)) {
              float_raise(float_flag_invalid, s);
 -            nan = float32_silence_nan(f32, s);
 +            if (!s->default_nan_mode) {
 +                nan = float32_silence_nan(f32, fpstp);
 +            }
          }
          if (s->default_nan_mode) {
              nan =  float32_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
          float64 nan = f64;
          if (float64_is_signaling_nan(f64, s)) {
              float_raise(float_flag_invalid, s);
 -            nan = float64_silence_nan(f64, s);
 +            if (!s->default_nan_mode) {
 +                nan = float64_silence_nan(f64, fpstp);
 +            }
          }
          if (s->default_nan_mode) {
              nan =  float64_default_nan(s);
 --
-.20.1
+.34.1

-[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
+[PULL 02/33] target/arm: Fix physical address resolution for Stage2
-From: Maxim Uvarov <maxim.uvarov@linaro.org>
+From: Richard Henderson <richard.henderson@linaro.org>
-qemu has 2 type of functions: shutdown and reboot. Shutdown
+Conversion to probe_access_full missed applying the page offset.
 function has to be used for machine shutdown. Otherwise we cause
 a reset with a bogus "cause" value, when we intended a shutdown.
-Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
+Cc: qemu-stable@nongnu.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reported-by: Sid Manning <sidneym@quicinc.com>
-Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-[PMM: tweaked commit message]
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20230126233134.103193-1-richard.henderson@linaro.org
 Fixes: f3639a64f602 ("target/arm: Use softmmu tlbs for page table walking")
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/gpio/gpio_pwr.c | 2 +-
+ target/arm/ptw.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/gpio/gpio_pwr.c
+--- a/target/arm/ptw.c
-+++ b/hw/gpio/gpio_pwr.c
++++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
+@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
- static void gpio_pwr_shutdown(void *opaque, int n, int level)
+         if (unlikely(flags & TLB_INVALID_MASK)) {
- {
+             goto fail;
-     if (level) {
+         }
--        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+-        ptw->out_phys = full->phys_addr;
-+        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
++        ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK);
-     }
+         ptw->out_rw = full->prot & PAGE_WRITE;
- }
+         pte_attrs = full->pte_attrs;
+         pte_secure = full->attrs.secure;
 --
-.20.1
+.34.1

-[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
+[PULL 03/33] hw/char/pl011: refactor FIFO depth handling code
-Implement the MVE saturating shift-right-and-narrow insns
+From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
 VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
-do_srshr() is borrowed from sve_helper.c.
+PL011 can be in either of 2 modes depending guest config: FIFO and
 single register. The last mode could be viewed as a 1-element-deep FIFO.
+Current code open-codes a bunch of depth-dependent logic. Refactor FIFO
+depth handling code to isolate calculating current FIFO depth.
+One functional (albeit guest-invisible) side-effect of this change is
+that previously we would always increment s->read_pos in UARTDR read
+handler even if FIFO was disabled, now we are limiting read_pos to not
+exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO).
+Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230123162304.26254-2-eiakovlev@linux.microsoft.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    |  30 +++++++++++
+ include/hw/char/pl011.h |  5 ++++-
- target/arm/mve.decode      |  28 ++++++++++
+ hw/char/pl011.c         | 30 ++++++++++++++++++------------
- target/arm/mve_helper.c    | 104 +++++++++++++++++++++++++++++++++++++
+files changed, 22 insertions(+), 13 deletions(-)
  target/arm/translate-mve.c |  12 +++++
 files changed, 174 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/include/hw/char/pl011.h
-+++ b/target/arm/helper-mve.h
++++ b/include/hw/char/pl011.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011)
- DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ /* This shares the same struct (and cast macro) as the base pl011 device */
- DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ #define TYPE_PL011_LUMINARY "pl011_luminary"
- DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +/* Depth of UART FIFO in bytes, when FIFO mode is enabled (else depth == 1) */
 +#define PL011_FIFO_DEPTH 16
 +
-+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ struct PL011State {
-+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     SysBusDevice parent_obj;
-+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ struct PL011State {
-+
+     uint32_t dmacr;
-+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     uint32_t int_enabled;
-+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     uint32_t int_level;
-+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+-    uint32_t read_fifo[16];
-+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    uint32_t read_fifo[PL011_FIFO_DEPTH];
-+
+     uint32_t ilpr;
-+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     uint32_t ibrd;
-+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     uint32_t fbrd;
-+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+diff --git a/hw/char/pl011.c b/hw/char/pl011.c
 +DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
+--- a/hw/char/pl011.c
-+++ b/target/arm/mve.decode
++++ b/hw/char/pl011.c
-@@ -XXX,XX +XXX,XX @@ VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
+@@ -XXX,XX +XXX,XX @@ static void pl011_update(PL011State *s)
  VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
  VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
  VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
 +
 +VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
 +VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
 +VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
 +VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
 +VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
 +VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
 +VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
 +VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
 +
 +VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
 +VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
 +VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
 +VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
 +
 +VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
 +VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
 +VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
 +VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
 +VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
 +
 +VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
 +VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
 +VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
 +VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
      }
  }
-+static inline int64_t do_srshr(int64_t x, unsigned sh)
++static bool pl011_is_fifo_enabled(PL011State *s)
 +{
-+    if (likely(sh < 64)) {
++    return (s->lcr & 0x10) != 0;
 +        return (x >> sh) + ((x >> (sh - 1)) & 1);
 +    } else {
 +        /* Rounding the sign bit always produces 0. */
 +        return 0;
 +    }
 +}
 +
- DO_VSHRN_ALL(vshrn, DO_SHR)
++static inline unsigned pl011_get_fifo_depth(PL011State *s)
  DO_VSHRN_ALL(vrshrn, do_urshr)
 +
 +static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
 +                                 bool *satp)
 +{
-+    if (val > max) {
++    /* Note: FIFO depth is expected to be power-of-2 */
-+        *satp = true;
++    return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
 +        return max;
 +    } else if (val < min) {
 +        *satp = true;
 +        return min;
 +    } else {
 +        return val;
 +    }
 +}
 +
-+/* Saturating narrowing right shifts */
+ static uint64_t pl011_read(void *opaque, hwaddr offset,
-+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)   \
+                            unsigned size)
-+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+ {
-+                                void *vm, uint32_t shift)       \
+@@ -XXX,XX +XXX,XX @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
-+    {                                                           \
+         c = s->read_fifo[s->read_pos];
-+        LTYPE *m = vm;                                          \
+         if (s->read_count > 0) {
-+        TYPE *d = vd;                                           \
+             s->read_count--;
-+        uint16_t mask = mve_element_mask(env);                  \
+-            if (++s->read_pos == 16)
-+        bool qc = false;                                        \
+-                s->read_pos = 0;
-+        unsigned le;                                            \
++            s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1);
-+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
+         }
-+            bool sat = false;                                   \
+         if (s->read_count == 0) {
-+            TYPE r = FN(m[H##LESIZE(le)], shift, &sat);         \
+             s->flags |= PL011_FLAG_RXFE;
-+            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
+@@ -XXX,XX +XXX,XX @@ static int pl011_can_receive(void *opaque)
-+            qc |= sat && (mask & 1 << (TOP * ESIZE));           \
+     PL011State *s = (PL011State *)opaque;
-+        }                                                       \
+     int r;
-+        if (qc) {                                               \
-+            env->vfp.qc[0] = qc;                                \
+-    if (s->lcr & 0x10) {
-+        }                                                       \
+-        r = s->read_count < 16;
-+        mve_advance_vpt(env);                                   \
+-    } else {
-+    }
+-        r = s->read_count < 1;
-+
+-    }
-+#define DO_VSHRN_SAT_UB(BOP, TOP, FN)                           \
++    r = s->read_count < pl011_get_fifo_depth(s);
-+    DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN)       \
+     trace_pl011_can_receive(s->lcr, s->read_count, r);
-+    DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
+     return r;
-+
+ }
-+#define DO_VSHRN_SAT_UH(BOP, TOP, FN)                           \
+@@ -XXX,XX +XXX,XX @@ static void pl011_put_fifo(void *opaque, uint32_t value)
-+    DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN)      \
+ {
-+    DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
+     PL011State *s = (PL011State *)opaque;
-+
+     int slot;
-+#define DO_VSHRN_SAT_SB(BOP, TOP, FN)                           \
++    unsigned pipe_depth;
-+    DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN)         \
-+    DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
+-    slot = s->read_pos + s->read_count;
-+
+-    if (slot >= 16)
-+#define DO_VSHRN_SAT_SH(BOP, TOP, FN)                           \
+-        slot -= 16;
-+    DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN)        \
++    pipe_depth = pl011_get_fifo_depth(s);
-+    DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
++    slot = (s->read_pos + s->read_count) & (pipe_depth - 1);
-+
+     s->read_fifo[slot] = value;
-+#define DO_SHRN_SB(N, M, SATP)                                  \
+     s->read_count++;
-+    do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
+     s->flags &= ~PL011_FLAG_RXFE;
-+#define DO_SHRN_UB(N, M, SATP)                                  \
+     trace_pl011_put_fifo(value, s->read_count);
-+    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
+-    if (!(s->lcr & 0x10) || s->read_count == 16) {
-+#define DO_SHRUN_B(N, M, SATP)                                  \
++    if (s->read_count == pipe_depth) {
-+    do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
+         trace_pl011_put_fifo_full();
-+
+         s->flags |= PL011_FLAG_RXFF;
-+#define DO_SHRN_SH(N, M, SATP)                                  \
+     }
-+    do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011 = {
-+#define DO_SHRN_UH(N, M, SATP)                                  \
+         VMSTATE_UINT32(dmacr, PL011State),
-+    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
+         VMSTATE_UINT32(int_enabled, PL011State),
-+#define DO_SHRUN_H(N, M, SATP)                                  \
+         VMSTATE_UINT32(int_level, PL011State),
-+    do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
+-        VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16),
-+
++        VMSTATE_UINT32_ARRAY(read_fifo, PL011State, PL011_FIFO_DEPTH),
-+#define DO_RSHRN_SB(N, M, SATP)                                 \
+         VMSTATE_UINT32(ilpr, PL011State),
-+    do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
+         VMSTATE_UINT32(ibrd, PL011State),
-+#define DO_RSHRN_UB(N, M, SATP)                                 \
+         VMSTATE_UINT32(fbrd, PL011State),
 +    do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
 +#define DO_RSHRUN_B(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
 +
 +#define DO_RSHRN_SH(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
 +#define DO_RSHRN_UH(N, M, SATP)                                 \
 +    do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
 +#define DO_RSHRUN_H(N, M, SATP)                                 \
 +    do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
 +
 +DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
 +DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
 +DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
 +DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
 +DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
 +DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
 +
 +DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
 +DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
 +DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
 +DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
 +DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
 +DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
  DO_2SHIFT_N(VSHRNT, vshrnt)
  DO_2SHIFT_N(VRSHRNB, vrshrnb)
  DO_2SHIFT_N(VRSHRNT, vrshrnt)
 +DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
 +DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
 +DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
 +DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
 +DO_2SHIFT_N(VQSHRUNB, vqshrunb)
 +DO_2SHIFT_N(VQSHRUNT, vqshrunt)
 +DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
 +DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
 +DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
 +DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
 +DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
 +DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
 --
-.20.1
+.34.1

-[PULL 23/24] target/arm: Implement MVE shifts by immediate
+[PULL 04/33] hw/char/pl011: add post_load hook for backwards-compatibility
-Implement the MVE shifts by immediate, which perform shifts
+From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
 on a single general-purpose register.
-These patterns overlap with the long-shift-by-immediates,
+Previous change slightly modified the way we handle data writes when
-so we have to rearrange the grouping a little here.
+FIFO is disabled. Previously we kept incrementing read_pos and were
 storing data at that position, although we only have a
 single-register-deep FIFO now. Then we changed it to always store data
 at pos 0.
+If guest disables FIFO and the proceeds to read data, it will work out
+fine, because we still read from current read_pos before setting it to
+.
+However, to make code less fragile, introduce a post_load hook for
+PL011State and move fixup read FIFO state when FIFO is disabled. Since
+we are introducing a post_load hook, also do some sanity checking on
+untrusted incoming input state.
+Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
+Message-id: 20230123162304.26254-3-eiakovlev@linux.microsoft.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h |  3 ++
+ hw/char/pl011.c | 25 +++++++++++++++++++++++++
- target/arm/translate.h  |  1 +
+file changed, 25 insertions(+)
  target/arm/t32.decode   | 31 ++++++++++++++-----
  target/arm/mve_helper.c | 10 ++++++
  target/arm/translate.c  | 68 +++++++++++++++++++++++++++++++++++++++--
 files changed, 104 insertions(+), 9 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/hw/char/pl011.c b/hw/char/pl011.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/hw/char/pl011.c
-+++ b/target/arm/helper-mve.h
++++ b/hw/char/pl011.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011_clock = {
- DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+     }
- DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
+ };
- DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
 +static int pl011_post_load(void *opaque, int version_id)
 +{
 +    PL011State* s = opaque;
 +
-+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
++    /* Sanity-check input state */
-+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
++    if (s->read_pos >= ARRAY_SIZE(s->read_fifo) ||
-diff --git a/target/arm/translate.h b/target/arm/translate.h
++        s->read_count > ARRAY_SIZE(s->read_fifo)) {
-index XXXXXXX..XXXXXXX 100644
++        return -1;
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
  typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
  typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
 +typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
  /**
   * arm_tbflags_from_tb:
 diff --git a/target/arm/t32.decode b/target/arm/t32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/t32.decode
 +++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@
  &mve_shl_ri      rdalo rdahi shim
  &mve_shl_rr      rdalo rdahi rm
 +&mve_sh_ri       rda shim
  # rdahi: bits [3:1] from insn, bit 0 is 1
  # rdalo: bits [3:1] from insn, bit 0 is 0
@@ -XXX,XX +XXX,XX @@
                   &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
  @mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
                   &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
 +@mve_sh_ri       ....... .... . rda:4 . ... ... . .. .. .... \
 +                 &mve_sh_ri shim=%imm5_12_6
  {
    TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
    # the rest fall through (where ORR_rrri and MOV_rxri will end up
    # handling them as r13 and r15 accesses with the same semantics as A32).
    [
 -    LSLL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
 -    LSRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
 -    ASRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +    {
 +      UQSHL_ri   1110101 0010 1 ....  0 ...  1111 .. 00 1111  @mve_sh_ri
 +      LSLL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +      UQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +    }
 -    UQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
 -    URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
 -    SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
 -    SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +    {
 +      URSHR_ri   1110101 0010 1 ....  0 ...  1111 .. 01 1111  @mve_sh_ri
 +      LSRL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +      URSHRL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +    }
 +
-+    {
++    if (!pl011_is_fifo_enabled(s) && s->read_count > 0 && s->read_pos > 0) {
-+      SRSHR_ri   1110101 0010 1 ....  0 ...  1111 .. 10 1111  @mve_sh_ri
++        /*
-+      ASRL_ri    1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
++         * Older versions of PL011 didn't ensure that the single
-+      SRSHRL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
++         * character in the FIFO in FIFO-disabled mode is in
 +         * element 0 of the array; convert to follow the current
 +         * code's assumptions.
 +         */
 +        s->read_fifo[0] = s->read_fifo[s->read_pos];
 +        s->read_pos = 0;
 +    }
 +
-+    {
++    return 0;
 +      SQSHL_ri   1110101 0010 1 ....  0 ...  1111 .. 11 1111  @mve_sh_ri
 +      SQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +    }
      LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
      ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
  {
      return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
  }
 +
 +uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
 +{
 +    return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
 +}
 +
-+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
+ static const VMStateDescription vmstate_pl011 = {
-+{
+     .name = "pl011",
-+    return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
+     .version_id = 2,
-+}
+     .minimum_version_id = 2,
-diff --git a/target/arm/translate.c b/target/arm/translate.c
++    .post_load = pl011_post_load,
-index XXXXXXX..XXXXXXX 100644
+     .fields = (VMStateField[]) {
---- a/target/arm/translate.c
+         VMSTATE_UINT32(readbuff, PL011State),
-+++ b/target/arm/translate.c
+         VMSTATE_UINT32(flags, PL011State),
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
  static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
  {
 -    TCGv_i32 t = tcg_temp_new_i32();
 +    TCGv_i32 t;
 +    /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
 +    if (sh == 32) {
 +        tcg_gen_movi_i32(d, 0);
 +        return;
 +    }
 +    t = tcg_temp_new_i32();
      tcg_gen_extract_i32(t, a, sh - 1, 1);
      tcg_gen_sari_i32(d, a, sh);
      tcg_gen_add_i32(d, d, t);
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
  static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
  {
 -    TCGv_i32 t = tcg_temp_new_i32();
 +    TCGv_i32 t;
 +    /* Handle shift by the input size for the benefit of trans_URSHR_ri */
 +    if (sh == 32) {
 +        tcg_gen_extract_i32(d, a, sh - 1, 1);
 +        return;
 +    }
 +    t = tcg_temp_new_i32();
      tcg_gen_extract_i32(t, a, sh - 1, 1);
      tcg_gen_shri_i32(d, a, sh);
      tcg_gen_add_i32(d, d, t);
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
      return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
  }
 +static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
 +{
 +    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 +        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
 +        return false;
 +    }
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
 +        a->rda == 13 || a->rda == 15) {
 +        /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
 +    if (a->shim == 0) {
 +        a->shim = 32;
 +    }
 +    fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
 +
 +    return true;
 +}
 +
 +static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_urshr32_i32);
 +}
 +
 +static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_srshr32_i32);
 +}
 +
 +static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
 +{
 +    gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_mve_sqshl);
 +}
 +
 +static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
 +{
 +    gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
 +{
 +    return do_mve_sh_ri(s, a, gen_mve_uqshl);
 +}
 +
  /*
   * Multiply and multiply accumulate
   */
 --
-.20.1
+.34.1

-[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
+[PULL 05/33] hw/char/pl011: implement a reset method
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
-Add a test booting and quickly shutdown a raspi2 machine,
+PL011 currently lacks a reset method. Implement it.
 to test the power management model:
-   (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
+Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
-  console: [    0.000000] Booting Linux on physical CPU 0xf00
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-  console: [    0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-  console: [    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
+Message-id: 20230123162304.26254-4-eiakovlev@linux.microsoft.com
   console: [    0.000000] CPU: div instructions available: patching division code
   console: [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
   console: [    0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
   ...
   console: Boot successful.
   console: cat /proc/cpuinfo
   console: / # cat /proc/cpuinfo
   ...
   console: processor      : 3
   console: model name     : ARMv7 Processor rev 5 (v7l)
   console: BogoMIPS       : 125.00
   console: Features       : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
   console: CPU implementer        : 0x41
   console: CPU architecture: 7
   console: CPU variant    : 0x0
   console: CPU part       : 0xc07
   console: CPU revision   : 5
   console: Hardware       : BCM2835
   console: Revision       : 0000
   console: Serial         : 0000000000000000
   console: cat /proc/iomem
   console: / # cat /proc/iomem
   console: 00000000-3bffffff : System RAM
   console: 00008000-00afffff : Kernel code
   console: 00c00000-00d468ef : Kernel data
   console: 3f006000-3f006fff : dwc_otg
   console: 3f007000-3f007eff : /soc/dma@7e007000
   console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
   console: 3f100000-3f100027 : /soc/watchdog@7e100000
   console: 3f101000-3f102fff : /soc/cprman@7e101000
   console: 3f200000-3f2000b3 : /soc/gpio@7e200000
   PASS (24.59 s)
   RESULTS    : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
   JOB TIME   : 25.02 s
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
 Message-id: 20210531113837.1689775-1-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
+ hw/char/pl011.c | 26 +++++++++++++++++++++-----
-file changed, 43 insertions(+)
+file changed, 21 insertions(+), 5 deletions(-)
-diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
+diff --git a/hw/char/pl011.c b/hw/char/pl011.c
 index XXXXXXX..XXXXXXX 100644
---- a/tests/acceptance/boot_linux_console.py
+--- a/hw/char/pl011.c
-+++ b/tests/acceptance/boot_linux_console.py
++++ b/hw/char/pl011.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void pl011_init(Object *obj)
- from avocado import skip
+     s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s,
- from avocado import skipUnless
+                                 ClockUpdate);
- from avocado_qemu import Test
-+from avocado_qemu import exec_command
+-    s->read_trigger = 1;
- from avocado_qemu import exec_command_and_wait_for_pattern
+-    s->ifl = 0x12;
- from avocado_qemu import interrupt_interactive_console_until_pattern
+-    s->cr = 0x300;
- from avocado_qemu import wait_for_console_pattern
+-    s->flags = 0x90;
-@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
+-
-         """
+     s->id = pl011_id_arm;
-         self.do_test_arm_raspi2(0)
+ }
-+    def test_arm_raspi2_initrd(self):
+@@ -XXX,XX +XXX,XX @@ static void pl011_realize(DeviceState *dev, Error **errp)
-+        """
+                              pl011_event, NULL, s, NULL, true);
-+        :avocado: tags=arch:arm
+ }
-+        :avocado: tags=machine:raspi2
-+        """
++static void pl011_reset(DeviceState *dev)
-+        deb_url = ('http://archive.raspberrypi.org/debian/'
++{
-+                   'pool/main/r/raspberrypi-firmware/'
++    PL011State *s = PL011(dev);
 +                   'raspberrypi-kernel_1.20190215-1_armhf.deb')
 +        deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
 +        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
 +        kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
 +        dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
 +
-+        initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
++    s->lcr = 0;
-+                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
++    s->rsr = 0;
-+                      'arm/rootfs-armv7a.cpio.gz')
++    s->dmacr = 0;
-+        initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
++    s->int_enabled = 0;
-+        initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
++    s->int_level = 0;
-+        initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
++    s->ilpr = 0;
-+        archive.gzip_uncompress(initrd_path_gz, initrd_path)
++    s->ibrd = 0;
 +    s->fbrd = 0;
 +    s->read_pos = 0;
 +    s->read_count = 0;
 +    s->read_trigger = 1;
 +    s->ifl = 0x12;
 +    s->cr = 0x300;
 +    s->flags = 0x90;
 +}
 +
-+        self.vm.set_console()
+ static void pl011_class_init(ObjectClass *oc, void *data)
-+        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+ {
-+                               'earlycon=pl011,0x3f201000 console=ttyAMA0 '
+     DeviceClass *dc = DEVICE_CLASS(oc);
-+                               'panic=-1 noreboot ' +
-+                               'dwc_otg.fiq_fsm_enable=0')
+     dc->realize = pl011_realize;
-+        self.vm.add_args('-kernel', kernel_path,
++    dc->reset = pl011_reset;
-+                         '-dtb', dtb_path,
+     dc->vmsd = &vmstate_pl011;
-+                         '-initrd', initrd_path,
+     device_class_set_props(dc, pl011_properties);
-+                         '-append', kernel_command_line,
+ }
 +                         '-no-reboot')
 +        self.vm.launch()
 +        self.wait_for_console_pattern('Boot successful.')
 +
 +        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
 +                                                'BCM2835')
 +        exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
 +                                                '/soc/cprman@7e101000')
 +        exec_command(self, 'halt')
 +        # Wait for VM to shut down gracefully
 +        self.vm.wait()
 +
      def test_arm_exynos4210_initrd(self):
          """
          :avocado: tags=arch:arm
 --
-.20.1
+.34.1

-New patch
+[PULL 06/33] hw/char/pl011: better handling of FIFO flags on LCR reset
+From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
+Current FIFO handling code does not reset RXFE/RXFF flags when guest
+resets FIFO by writing to UARTLCR register, although internal FIFO state
+is reset to 0 read count. Actual guest-visible flag update will happen
+only on next data read or write attempt. As a result of that any guest
+that expects RXFE flag to be set (and RXFF to be cleared) after resetting
+FIFO will never see that happen.
+Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230123162304.26254-5-eiakovlev@linux.microsoft.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/char/pl011.c | 18 +++++++++++++-----
+file changed, 13 insertions(+), 5 deletions(-)
+diff --git a/hw/char/pl011.c b/hw/char/pl011.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/char/pl011.c
++++ b/hw/char/pl011.c
+@@ -XXX,XX +XXX,XX @@ static inline unsigned pl011_get_fifo_depth(PL011State *s)
+     return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
+ }
++static inline void pl011_reset_fifo(PL011State *s)
++{
++    s->read_count = 0;
++    s->read_pos = 0;
++
++    /* Reset FIFO flags */
++    s->flags &= ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF);
++    s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE;
++}
++
+ static uint64_t pl011_read(void *opaque, hwaddr offset,
+                            unsigned size)
+ {
+@@ -XXX,XX +XXX,XX @@ static void pl011_write(void *opaque, hwaddr offset,
+     case 11: /* UARTLCR_H */
+         /* Reset the FIFO state on FIFO enable or disable */
+         if ((s->lcr ^ value) & 0x10) {
+-            s->read_count = 0;
+-            s->read_pos = 0;
++            pl011_reset_fifo(s);
+         }
+         if ((s->lcr ^ value) & 0x1) {
+             int break_enable = value & 0x1;
+@@ -XXX,XX +XXX,XX @@ static void pl011_reset(DeviceState *dev)
+     s->ilpr = 0;
+     s->ibrd = 0;
+     s->fbrd = 0;
+-    s->read_pos = 0;
+-    s->read_count = 0;
+     s->read_trigger = 1;
+     s->ifl = 0x12;
+     s->cr = 0x300;
+-    s->flags = 0x90;
++    s->flags = 0;
++    pl011_reset_fifo(s);
+ }
+ static void pl011_class_init(ObjectClass *oc, void *data)
+--
+.34.1

-[PULL 22/24] target/arm: Implement MVE long shifts by register
+[PULL 07/33] hvf: arm: Add support for GICv3
-Implement the MVE long shifts by register, which perform shifts on a
+From: Alexander Graf <agraf@csgraf.de>
-pair of general-purpose registers treated as a 64-bit quantity, with
-the shift count in another general-purpose register, which might be
+We currently only support GICv2 emulation. To also support GICv3, we will
-either positive or negative.
+need to pass a few system registers into their respective handler functions.
-Like the long-shifts-by-immediate, these encodings sit in the space
+This patch adds support for HVF to call into the TCG callbacks for GICv3
-that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
+system register handlers. This is safe because the GICv3 TCG code is generic
-Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
+as long as we limit ourselves to EL0 and EL1 - which are the only modes
-also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
+supported by HVF.
-we have to move the CSEL pattern into the same decodetree group.
+To make sure nobody trips over that, we also annotate callbacks that don't
 work in HVF mode, such as EL state change hooks.
 With GICv3 support in place, we can run with more than 8 vCPUs.
 Signed-off-by: Alexander Graf <agraf@csgraf.de>
 Message-id: 20230128224459.70676-1-agraf@csgraf.de
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h |  6 +++
+ hw/intc/arm_gicv3_cpuif.c   |  16 +++-
- target/arm/translate.h  |  1 +
+ target/arm/hvf/hvf.c        | 151 ++++++++++++++++++++++++++++++++++++
- target/arm/t32.decode   | 16 +++++--
+ target/arm/hvf/trace-events |   2 +
- target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
+files changed, 168 insertions(+), 1 deletion(-)
- target/arm/translate.c  | 69 ++++++++++++++++++++++++++++++
-files changed, 182 insertions(+), 3 deletions(-)
+diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/target/arm/helper-mve.h
++++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/irq.h"
- DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
+ #include "cpu.h"
+ #include "target/arm/cpregs.h"
-+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
++#include "sysemu/tcg.h"
-+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
++#include "sysemu/qtest.h"
- DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
- DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+ /*
-+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+  * Special case return value from hppvi_index(); must be larger than
-+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
-+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
+          * which case we'd get the wrong value.
-+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
+          * So instead we define the regs with no ri->opaque info, and
-diff --git a/target/arm/translate.h b/target/arm/translate.h
+          * get back to the GICv3CPUState from the CPUARMState.
 +         *
 +         * These CP regs callbacks can be called from either TCG or HVF code.
           */
          define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
                  define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo);
              }
          }
 -        arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs);
 +        if (tcg_enabled() || qtest_enabled()) {
 +            /*
 +             * We can only trap EL changes with TCG. However the GIC interrupt
 +             * state only changes on EL changes involving EL2 or EL3, so for
 +             * the non-TCG case this is OK, as EL2 and EL3 can't exist.
 +             */
 +            arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs);
 +        } else {
 +            assert(!arm_feature(&cpu->env, ARM_FEATURE_EL2));
 +            assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3));
 +        }
      }
  }
 diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
+--- a/target/arm/hvf/hvf.c
-+++ b/target/arm/translate.h
++++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
  typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
 +typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
  /**
   * arm_tbflags_from_tb:
 diff --git a/target/arm/t32.decode b/target/arm/t32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/t32.decode
 +++ b/target/arm/t32.decode
 @@ -XXX,XX +XXX,XX @@
- &mcrr            !extern cp opc1 crm rt rt2
+ #define SYSREG_PMCCNTR_EL0    SYSREG(3, 3, 9, 13, 0)
+ #define SYSREG_PMCCFILTR_EL0  SYSREG(3, 3, 14, 15, 7)
- &mve_shl_ri      rdalo rdahi shim
-+&mve_shl_rr      rdalo rdahi rm
++#define SYSREG_ICC_AP0R0_EL1     SYSREG(3, 0, 12, 8, 4)
++#define SYSREG_ICC_AP0R1_EL1     SYSREG(3, 0, 12, 8, 5)
- # rdahi: bits [3:1] from insn, bit 0 is 1
++#define SYSREG_ICC_AP0R2_EL1     SYSREG(3, 0, 12, 8, 6)
- # rdalo: bits [3:1] from insn, bit 0 is 0
++#define SYSREG_ICC_AP0R3_EL1     SYSREG(3, 0, 12, 8, 7)
-@@ -XXX,XX +XXX,XX @@
++#define SYSREG_ICC_AP1R0_EL1     SYSREG(3, 0, 12, 9, 0)
++#define SYSREG_ICC_AP1R1_EL1     SYSREG(3, 0, 12, 9, 1)
- @mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
++#define SYSREG_ICC_AP1R2_EL1     SYSREG(3, 0, 12, 9, 2)
-                  &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
++#define SYSREG_ICC_AP1R3_EL1     SYSREG(3, 0, 12, 9, 3)
-+@mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
++#define SYSREG_ICC_ASGI1R_EL1    SYSREG(3, 0, 12, 11, 6)
-+                 &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
++#define SYSREG_ICC_BPR0_EL1      SYSREG(3, 0, 12, 8, 3)
++#define SYSREG_ICC_BPR1_EL1      SYSREG(3, 0, 12, 12, 3)
- {
++#define SYSREG_ICC_CTLR_EL1      SYSREG(3, 0, 12, 12, 4)
-   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
++#define SYSREG_ICC_DIR_EL1       SYSREG(3, 0, 12, 11, 1)
-@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
++#define SYSREG_ICC_EOIR0_EL1     SYSREG(3, 0, 12, 8, 1)
-     URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
++#define SYSREG_ICC_EOIR1_EL1     SYSREG(3, 0, 12, 12, 1)
-     SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
++#define SYSREG_ICC_HPPIR0_EL1    SYSREG(3, 0, 12, 8, 2)
-     SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
++#define SYSREG_ICC_HPPIR1_EL1    SYSREG(3, 0, 12, 12, 2)
-+
++#define SYSREG_ICC_IAR0_EL1      SYSREG(3, 0, 12, 8, 0)
-+    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
++#define SYSREG_ICC_IAR1_EL1      SYSREG(3, 0, 12, 12, 0)
-+    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
++#define SYSREG_ICC_IGRPEN0_EL1   SYSREG(3, 0, 12, 12, 6)
-+    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
++#define SYSREG_ICC_IGRPEN1_EL1   SYSREG(3, 0, 12, 12, 7)
-+    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
++#define SYSREG_ICC_PMR_EL1       SYSREG(3, 0, 4, 6, 0)
-+    UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
++#define SYSREG_ICC_RPR_EL1       SYSREG(3, 0, 12, 11, 3)
-+    SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
++#define SYSREG_ICC_SGI0R_EL1     SYSREG(3, 0, 12, 11, 7)
-   ]
++#define SYSREG_ICC_SGI1R_EL1     SYSREG(3, 0, 12, 11, 5)
++#define SYSREG_ICC_SRE_EL1       SYSREG(3, 0, 12, 12, 5)
-   MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
++
-   ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
+ #define WFX_IS_WFE (1 << 0)
-+
-+  # v8.1M CSEL and friends
+ #define TMR_CTL_ENABLE  (1 << 0)
-+  CSEL           1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
+@@ -XXX,XX +XXX,XX @@ static bool is_id_sysreg(uint32_t reg)
             SYSREG_CRM(reg) < 8;
  }
- {
-   MVN_rxri       1110101 0011 . 1111 0 ... .... .... ....     @s_rxr_shi
++static uint32_t hvf_reg2cp_reg(uint32_t reg)
@@ -XXX,XX +XXX,XX @@ SBC_rrri         1110101 1011 . .... 0 ... .... .... ....     @s_rrr_shi
  }
  RSB_rrri         1110101 1110 . .... 0 ... .... .... ....     @s_rrr_shi
 -# v8.1M CSEL and friends
 -CSEL             1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
 -
  # Data-processing (register-shifted register)
  MOV_rxrr         1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
      return rdm;
  }
 +uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
-+    return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
++    return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
 +                              (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
 +                              (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK,
 +                              (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK,
 +                              (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK,
 +                              (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK);
 +}
 +
-+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
++static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val)
 +{
-+    return do_uqrshl_d(n, (int8_t)shift, false, NULL);
++    ARMCPU *arm_cpu = ARM_CPU(cpu);
-+}
++    CPUARMState *env = &arm_cpu->env;
-+
++    const ARMCPRegInfo *ri;
- uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
++
- {
++    ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
-     return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
++    if (ri) {
-@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
++        if (ri->accessfn) {
- {
++            if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) {
-     return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
++                return false;
- }
++            }
-+
++        }
-+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
++        if (ri->type & ARM_CP_CONST) {
-+{
++            *val = ri->resetvalue;
-+    return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
++        } else if (ri->readfn) {
-+}
++            *val = ri->readfn(env, ri);
 +
 +uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
 +}
 +
 +/* Operate on 64-bit values, but saturate at 48 bits */
 +static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
 +                                    bool round, uint32_t *sat)
 +{
 +    if (shift <= -48) {
 +        /* Rounding the sign bit always produces 0. */
 +        if (round) {
 +            return 0;
 +        }
 +        return src >> 63;
 +    } else if (shift < 0) {
 +        if (round) {
 +            src >>= -shift - 1;
 +            return (src >> 1) + (src & 1);
 +        }
 +        return src >> -shift;
 +    } else if (shift < 48) {
 +        int64_t val = src << shift;
 +        int64_t extval = sextract64(val, 0, 48);
 +        if (!sat || val == extval) {
 +            return extval;
 +        }
 +    } else if (!sat || src == 0) {
 +        return 0;
 +    }
 +
 +    *sat = 1;
 +    return (1ULL << 47) - (src >= 0);
 +}
 +
 +/* Operate on 64-bit values, but saturate at 48 bits */
 +static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
 +                                     bool round, uint32_t *sat)
 +{
 +    uint64_t val, extval;
 +
 +    if (shift <= -(48 + round)) {
 +        return 0;
 +    } else if (shift < 0) {
 +        if (round) {
 +            val = src >> (-shift - 1);
 +            val = (val >> 1) + (val & 1);
 +        } else {
-+            val = src >> -shift;
++            *val = CPREG_FIELD64(env, ri);
 +        }
-+        extval = extract64(val, 0, 48);
++        trace_hvf_vgic_read(ri->name, *val);
 +        if (!sat || val == extval) {
 +            return extval;
 +        }
 +    } else if (shift < 48) {
 +        uint64_t val = src << shift;
 +        uint64_t extval = extract64(val, 0, 48);
 +        if (!sat || val == extval) {
 +            return extval;
 +        }
 +    } else if (!sat || src == 0) {
 +        return 0;
 +    }
 +
 +    *sat = 1;
 +    return MAKE_64BIT_MASK(0, 48);
 +}
 +
 +uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
 +}
 +
 +uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
 +    return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
      return do_mve_shl_ri(s, a, gen_urshr64_i64);
  }
 +static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
 +{
 +    TCGv_i64 rda;
 +    TCGv_i32 rdalo, rdahi;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 +        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
 +        return false;
 +    }
 +    if (a->rdahi == 15) {
 +        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
 +        return false;
 +    }
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
 +        a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
 +        a->rm == a->rdahi || a->rm == a->rdalo) {
 +        /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
-+    rda = tcg_temp_new_i64();
++    return false;
 +    rdalo = load_reg(s, a->rdalo);
 +    rdahi = load_reg(s, a->rdahi);
 +    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
 +
 +    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
 +    fn(rda, cpu_env, rda, cpu_R[a->rm]);
 +
 +    tcg_gen_extrl_i64_i32(rdalo, rda);
 +    tcg_gen_extrh_i64_i32(rdahi, rda);
 +    store_reg(s, a->rdalo, rdalo);
 +    store_reg(s, a->rdahi, rdahi);
 +    tcg_temp_free_i64(rda);
 +
 +    return true;
 +}
 +
-+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
+ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
  {
      ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
      case SYSREG_OSDLR_EL1:
          /* Dummy register */
          break;
 +    case SYSREG_ICC_AP0R0_EL1:
 +    case SYSREG_ICC_AP0R1_EL1:
 +    case SYSREG_ICC_AP0R2_EL1:
 +    case SYSREG_ICC_AP0R3_EL1:
 +    case SYSREG_ICC_AP1R0_EL1:
 +    case SYSREG_ICC_AP1R1_EL1:
 +    case SYSREG_ICC_AP1R2_EL1:
 +    case SYSREG_ICC_AP1R3_EL1:
 +    case SYSREG_ICC_ASGI1R_EL1:
 +    case SYSREG_ICC_BPR0_EL1:
 +    case SYSREG_ICC_BPR1_EL1:
 +    case SYSREG_ICC_DIR_EL1:
 +    case SYSREG_ICC_EOIR0_EL1:
 +    case SYSREG_ICC_EOIR1_EL1:
 +    case SYSREG_ICC_HPPIR0_EL1:
 +    case SYSREG_ICC_HPPIR1_EL1:
 +    case SYSREG_ICC_IAR0_EL1:
 +    case SYSREG_ICC_IAR1_EL1:
 +    case SYSREG_ICC_IGRPEN0_EL1:
 +    case SYSREG_ICC_IGRPEN1_EL1:
 +    case SYSREG_ICC_PMR_EL1:
 +    case SYSREG_ICC_SGI0R_EL1:
 +    case SYSREG_ICC_SGI1R_EL1:
 +    case SYSREG_ICC_SRE_EL1:
 +    case SYSREG_ICC_CTLR_EL1:
 +        /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
 +        if (!hvf_sysreg_read_cp(cpu, reg, &val)) {
 +            hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
 +        }
 +        break;
      default:
          if (is_id_sysreg(reg)) {
              /* ID system registers read as RES0 */
@@ -XXX,XX +XXX,XX @@ static void pmswinc_write(CPUARMState *env, uint64_t value)
      }
  }
 +static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val)
 +{
-+    return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
++    ARMCPU *arm_cpu = ARM_CPU(cpu);
 +    CPUARMState *env = &arm_cpu->env;
 +    const ARMCPRegInfo *ri;
 +
 +    ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
 +
 +    if (ri) {
 +        if (ri->accessfn) {
 +            if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) {
 +                return false;
 +            }
 +        }
 +        if (ri->writefn) {
 +            ri->writefn(env, ri, val);
 +        } else {
 +            CPREG_FIELD64(env, ri) = val;
 +        }
 +
 +        trace_hvf_vgic_write(ri->name, val);
 +        return true;
 +    }
 +
 +    return false;
 +}
 +
-+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
+ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
-+{
+ {
-+    return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
+     ARMCPU *arm_cpu = ARM_CPU(cpu);
-+}
+@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
-+
+     case SYSREG_OSDLR_EL1:
-+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
+         /* Dummy register */
-+{
+         break;
-+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
++    case SYSREG_ICC_AP0R0_EL1:
-+}
++    case SYSREG_ICC_AP0R1_EL1:
-+
++    case SYSREG_ICC_AP0R2_EL1:
-+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
++    case SYSREG_ICC_AP0R3_EL1:
-+{
++    case SYSREG_ICC_AP1R0_EL1:
-+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
++    case SYSREG_ICC_AP1R1_EL1:
-+}
++    case SYSREG_ICC_AP1R2_EL1:
-+
++    case SYSREG_ICC_AP1R3_EL1:
-+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
++    case SYSREG_ICC_ASGI1R_EL1:
-+{
++    case SYSREG_ICC_BPR0_EL1:
-+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
++    case SYSREG_ICC_BPR1_EL1:
-+}
++    case SYSREG_ICC_CTLR_EL1:
-+
++    case SYSREG_ICC_DIR_EL1:
-+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
++    case SYSREG_ICC_EOIR0_EL1:
-+{
++    case SYSREG_ICC_EOIR1_EL1:
-+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
++    case SYSREG_ICC_HPPIR0_EL1:
-+}
++    case SYSREG_ICC_HPPIR1_EL1:
-+
++    case SYSREG_ICC_IAR0_EL1:
- /*
++    case SYSREG_ICC_IAR1_EL1:
-  * Multiply and multiply accumulate
++    case SYSREG_ICC_IGRPEN0_EL1:
-  */
++    case SYSREG_ICC_IGRPEN1_EL1:
 +    case SYSREG_ICC_PMR_EL1:
 +    case SYSREG_ICC_SGI0R_EL1:
 +    case SYSREG_ICC_SGI1R_EL1:
 +    case SYSREG_ICC_SRE_EL1:
 +        /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
 +        if (!hvf_sysreg_write_cp(cpu, reg, val)) {
 +            hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
 +        }
 +        break;
      default:
          cpu_synchronize_state(cpu);
          trace_hvf_unhandled_sysreg_write(env->pc, reg,
 diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/hvf/trace-events
 +++ b/target/arm/hvf/trace-events
@@ -XXX,XX +XXX,XX @@ hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64
  hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64
  hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]"
  hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpu=0x%x"
 +hvf_vgic_write(const char *name, uint64_t val) "vgic write to %s [val=0x%016"PRIx64"]"
 +hvf_vgic_read(const char *name, uint64_t val) "vgic read from %s [val=0x%016"PRIx64"]"
 --
-.20.1
+.34.1

-[PULL 03/24] hw/arm: Add basic power management to raspi.
+[PULL 08/33] hw/arm/virt: Consolidate GIC finalize logic
-From: Nolan Leake <nolan@sigbus.net>
+From: Alexander Graf <agraf@csgraf.de>
-This is just enough to make reboot and poweroff work. Works for
+Up to now, the finalize_gic_version() code open coded what is essentially
-linux, u-boot, and the arm trusted firmware. Not tested, but should
+a support bitmap match between host/emulation environment and desired
-work for plan9, and bare-metal/hobby OSes, since they seem to generally
+target GIC type.
-do what linux does for reset.
+This open coding leads to undesirable side effects. For example, a VM with
-The watchdog timer functionality is not yet implemented.
+KVM and -smp 10 will automatically choose GICv3 while the same command
+line with TCG will stay on GICv2 and fail the launch.
-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
-Signed-off-by: Nolan Leake <nolan@sigbus.net>
+This patch combines the TCG and KVM matching code paths by making
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+everything a 2 pass process. First, we determine which GIC versions the
-Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+current environment is able to support, then we go through a single
-Message-id: 20210625210209.1870217-1-nolan@sigbus.net
+state machine to determine which target GIC mode that means for us.
-[PMM: tweaked commit title; fixed region size to 0x200;
- moved header file to include/]
+After this patch, the only user noticable changes should be consolidated
 error messages as well as TCG -M virt supporting -smp > 8 automatically.
 Signed-off-by: Alexander Graf <agraf@csgraf.de>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Cornelia Huck <cohuck@redhat.com>
 Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
 Message-id: 20221223090107.98888-2-agraf@csgraf.de
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/bcm2835_peripherals.h |   3 +-
+ include/hw/arm/virt.h |  15 ++--
- include/hw/misc/bcm2835_powermgt.h   |  29 +++++
+ hw/arm/virt.c         | 198 ++++++++++++++++++++++--------------------
- hw/arm/bcm2835_peripherals.c         |  13 ++-
+files changed, 112 insertions(+), 101 deletions(-)
- hw/misc/bcm2835_powermgt.c           | 160 +++++++++++++++++++++++++++
- hw/misc/meson.build                  |   1 +
+diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
 files changed, 204 insertions(+), 2 deletions(-)
  create mode 100644 include/hw/misc/bcm2835_powermgt.h
  create mode 100644 hw/misc/bcm2835_powermgt.c
 diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/bcm2835_peripherals.h
+--- a/include/hw/arm/virt.h
-+++ b/include/hw/arm/bcm2835_peripherals.h
++++ b/include/hw/arm/virt.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef enum VirtMSIControllerType {
- #include "hw/misc/bcm2835_mphi.h"
+ } VirtMSIControllerType;
- #include "hw/misc/bcm2835_thermal.h"
- #include "hw/misc/bcm2835_cprman.h"
+ typedef enum VirtGICType {
-+#include "hw/misc/bcm2835_powermgt.h"
+-    VIRT_GIC_VERSION_MAX,
- #include "hw/sd/sdhci.h"
+-    VIRT_GIC_VERSION_HOST,
- #include "hw/sd/bcm2835_sdhost.h"
+-    VIRT_GIC_VERSION_2,
- #include "hw/gpio/bcm2835_gpio.h"
+-    VIRT_GIC_VERSION_3,
-@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
+-    VIRT_GIC_VERSION_4,
-     BCM2835MphiState mphi;
++    VIRT_GIC_VERSION_MAX = 0,
-     UnimplementedDeviceState txp;
++    VIRT_GIC_VERSION_HOST = 1,
-     UnimplementedDeviceState armtmr;
++    /* The concrete GIC values have to match the GIC version number */
--    UnimplementedDeviceState powermgt;
++    VIRT_GIC_VERSION_2 = 2,
-+    BCM2835PowerMgtState powermgt;
++    VIRT_GIC_VERSION_3 = 3,
-     BCM2835CprmanState cprman;
++    VIRT_GIC_VERSION_4 = 4,
-     PL011State uart0;
+     VIRT_GIC_VERSION_NOSEL,
-     BCM2835AuxState aux;
+ } VirtGICType;
-diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
-new file mode 100644
++#define VIRT_GIC_VERSION_2_MASK BIT(VIRT_GIC_VERSION_2)
-index XXXXXXX..XXXXXXX
++#define VIRT_GIC_VERSION_3_MASK BIT(VIRT_GIC_VERSION_3)
---- /dev/null
++#define VIRT_GIC_VERSION_4_MASK BIT(VIRT_GIC_VERSION_4)
-+++ b/include/hw/misc/bcm2835_powermgt.h
++
-@@ -XXX,XX +XXX,XX @@
+ struct VirtMachineClass {
-+/*
+     MachineClass parent;
-+ * BCM2835 Power Management emulation
+     bool disallow_affinity_adjustment;
-+ *
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 + * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
 + * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + */
 +
 +#ifndef BCM2835_POWERMGT_H
 +#define BCM2835_POWERMGT_H
 +
 +#include "hw/sysbus.h"
 +#include "qom/object.h"
 +
 +#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
 +OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
 +
 +struct BCM2835PowerMgtState {
 +    SysBusDevice busdev;
 +    MemoryRegion iomem;
 +
 +    uint32_t rstc;
 +    uint32_t rsts;
 +    uint32_t wdog;
 +};
 +
 +#endif
 diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2835_peripherals.c
+--- a/hw/arm/virt.c
-+++ b/hw/arm/bcm2835_peripherals.c
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
+     }
      object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
                                     OBJECT(&s->gpu_bus_mr));
 +
 +    /* Power Management */
 +    object_initialize_child(obj, "powermgt", &s->powermgt,
 +                            TYPE_BCM2835_POWERMGT);
  }
- static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
++static VirtGICType finalize_gic_version_do(const char *accel_name,
-@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
++                                           VirtGICType gic_version,
-         qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
++                                           int gics_supported,
-                                INTERRUPT_USB));
++                                           unsigned int max_cpus)
++{
-+    /* Power Management */
++    /* Convert host/max/nosel to GIC version number */
-+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
++    switch (gic_version) {
-+        return;
++    case VIRT_GIC_VERSION_HOST:
 +        if (!kvm_enabled()) {
 +            error_report("gic-version=host requires KVM");
 +            exit(1);
 +        }
 +
 +        /* For KVM, gic-version=host means gic-version=max */
 +        return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
 +                                       gics_supported, max_cpus);
 +    case VIRT_GIC_VERSION_MAX:
 +        if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
 +            gic_version = VIRT_GIC_VERSION_4;
 +        } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
 +            gic_version = VIRT_GIC_VERSION_3;
 +        } else {
 +            gic_version = VIRT_GIC_VERSION_2;
 +        }
 +        break;
 +    case VIRT_GIC_VERSION_NOSEL:
 +        if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
 +            max_cpus <= GIC_NCPU) {
 +            gic_version = VIRT_GIC_VERSION_2;
 +        } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
 +            /*
 +             * in case the host does not support v2 emulation or
 +             * the end-user requested more than 8 VCPUs we now default
 +             * to v3. In any case defaulting to v2 would be broken.
 +             */
 +            gic_version = VIRT_GIC_VERSION_3;
 +        } else if (max_cpus > GIC_NCPU) {
 +            error_report("%s only supports GICv2 emulation but more than 8 "
 +                         "vcpus are requested", accel_name);
 +            exit(1);
 +        }
 +        break;
 +    case VIRT_GIC_VERSION_2:
 +    case VIRT_GIC_VERSION_3:
 +    case VIRT_GIC_VERSION_4:
 +        break;
 +    }
 +
-+    memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
++    /* Check chosen version is effectively supported */
-+                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
++    switch (gic_version) {
-+
++    case VIRT_GIC_VERSION_2:
-     create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
++        if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
-     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
++            error_report("%s does not support GICv2 emulation", accel_name);
--    create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
++            exit(1);
-     create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
++        }
-     create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
++        break;
-     create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
++    case VIRT_GIC_VERSION_3:
-diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
++        if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
-new file mode 100644
++            error_report("%s does not support GICv3 emulation", accel_name);
-index XXXXXXX..XXXXXXX
++            exit(1);
---- /dev/null
++        }
-+++ b/hw/misc/bcm2835_powermgt.c
++        break;
-@@ -XXX,XX +XXX,XX @@
++    case VIRT_GIC_VERSION_4:
-+/*
++        if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
-+ * BCM2835 Power Management emulation
++            error_report("%s does not support GICv4 emulation, is virtualization=on?",
-+ *
++                         accel_name);
-+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
++            exit(1);
-+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
++        }
-+ *
++        break;
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/log.h"
 +#include "qemu/module.h"
 +#include "hw/misc/bcm2835_powermgt.h"
 +#include "migration/vmstate.h"
 +#include "sysemu/runstate.h"
 +
 +#define PASSWORD 0x5a000000
 +#define PASSWORD_MASK 0xff000000
 +
 +#define R_RSTC 0x1c
 +#define V_RSTC_RESET 0x20
 +#define R_RSTS 0x20
 +#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
 +#define R_WDOG 0x24
 +
 +static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
 +                                      unsigned size)
 +{
 +    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
 +    uint32_t res = 0;
 +
 +    switch (offset) {
 +    case R_RSTC:
 +        res = s->rstc;
 +        break;
 +    case R_RSTS:
 +        res = s->rsts;
 +        break;
 +    case R_WDOG:
 +        res = s->wdog;
 +        break;
 +
 +    default:
-+        qemu_log_mask(LOG_UNIMP,
++        error_report("logic error in finalize_gic_version");
-+                      "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
++        exit(1);
 +                      "\n", offset);
 +        res = 0;
 +        break;
 +    }
 +
-+    return res;
++    return gic_version;
 +}
 +
-+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
+ /*
-+                                   uint64_t value, unsigned size)
+  * finalize_gic_version - Determines the final gic_version
-+{
+  * according to the gic-version property
-+    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
+@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
-+
+  */
-+    if ((value & PASSWORD_MASK) != PASSWORD) {
+ static void finalize_gic_version(VirtMachineState *vms)
-+        qemu_log_mask(LOG_GUEST_ERROR,
+ {
-+                      "bcm2835_powermgt_write: Bad password 0x%"PRIx64
++    const char *accel_name = current_accel_name();
-+                      " at offset 0x%08"HWADDR_PRIx"\n",
+     unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
-+                      value, offset);
++    int gics_supported = 0;
-+        return;
-+    }
+-    if (kvm_enabled()) {
-+
+-        int probe_bitmap;
-+    value = value & ~PASSWORD_MASK;
++    /* Determine which GIC versions the current environment supports */
-+
++    if (kvm_enabled() && kvm_irqchip_in_kernel()) {
-+    switch (offset) {
++        int probe_bitmap = kvm_arm_vgic_probe();
-+    case R_RSTC:
-+        s->rstc = value;
+-        if (!kvm_irqchip_in_kernel()) {
-+        if (value & V_RSTC_RESET) {
+-            switch (vms->gic_version) {
-+            if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
+-            case VIRT_GIC_VERSION_HOST:
-+                qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+-                warn_report(
-+            } else {
+-                    "gic-version=host not relevant with kernel-irqchip=off "
-+                qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+-                     "as only userspace GICv2 is supported. Using v2 ...");
-+            }
+-                return;
-+        }
+-            case VIRT_GIC_VERSION_MAX:
-+        break;
+-            case VIRT_GIC_VERSION_NOSEL:
-+    case R_RSTS:
+-                vms->gic_version = VIRT_GIC_VERSION_2;
-+        qemu_log_mask(LOG_UNIMP,
+-                return;
-+                      "bcm2835_powermgt_write: RSTS\n");
+-            case VIRT_GIC_VERSION_2:
-+        s->rsts = value;
+-                return;
-+        break;
+-            case VIRT_GIC_VERSION_3:
-+    case R_WDOG:
+-                error_report(
-+        qemu_log_mask(LOG_UNIMP,
+-                    "gic-version=3 is not supported with kernel-irqchip=off");
-+                      "bcm2835_powermgt_write: WDOG\n");
+-                exit(1);
-+        s->wdog = value;
+-            case VIRT_GIC_VERSION_4:
-+        break;
+-                error_report(
-+
+-                    "gic-version=4 is not supported with kernel-irqchip=off");
-+    default:
+-                exit(1);
-+        qemu_log_mask(LOG_UNIMP,
+-            }
-+                      "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
+-        }
-+                      "\n", offset);
+-
-+        break;
+-        probe_bitmap = kvm_arm_vgic_probe();
-+    }
+         if (!probe_bitmap) {
-+}
+             error_report("Unable to determine GIC version supported by host");
-+
+             exit(1);
-+static const MemoryRegionOps bcm2835_powermgt_ops = {
+         }
-+    .read = bcm2835_powermgt_read,
-+    .write = bcm2835_powermgt_write,
+-        switch (vms->gic_version) {
-+    .endianness = DEVICE_NATIVE_ENDIAN,
+-        case VIRT_GIC_VERSION_HOST:
-+    .impl.min_access_size = 4,
+-        case VIRT_GIC_VERSION_MAX:
-+    .impl.max_access_size = 4,
+-            if (probe_bitmap & KVM_ARM_VGIC_V3) {
-+};
+-                vms->gic_version = VIRT_GIC_VERSION_3;
-+
+-            } else {
-+static const VMStateDescription vmstate_bcm2835_powermgt = {
+-                vms->gic_version = VIRT_GIC_VERSION_2;
-+    .name = TYPE_BCM2835_POWERMGT,
+-            }
-+    .version_id = 1,
+-            return;
-+    .minimum_version_id = 1,
+-        case VIRT_GIC_VERSION_NOSEL:
-+    .fields = (VMStateField[]) {
+-            if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
-+        VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
+-                vms->gic_version = VIRT_GIC_VERSION_2;
-+        VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
+-            } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
-+        VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
+-                /*
-+        VMSTATE_END_OF_LIST()
+-                 * in case the host does not support v2 in-kernel emulation or
-+    }
+-                 * the end-user requested more than 8 VCPUs we now default
-+};
+-                 * to v3. In any case defaulting to v2 would be broken.
-+
+-                 */
-+static void bcm2835_powermgt_init(Object *obj)
+-                vms->gic_version = VIRT_GIC_VERSION_3;
-+{
+-            } else if (max_cpus > GIC_NCPU) {
-+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
+-                error_report("host only supports in-kernel GICv2 emulation "
-+
+-                             "but more than 8 vcpus are requested");
-+    memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
+-                exit(1);
-+                          TYPE_BCM2835_POWERMGT, 0x200);
+-            }
-+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+-            break;
-+}
+-        case VIRT_GIC_VERSION_2:
-+
+-        case VIRT_GIC_VERSION_3:
-+static void bcm2835_powermgt_reset(DeviceState *dev)
+-            break;
-+{
+-        case VIRT_GIC_VERSION_4:
-+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
+-            error_report("gic-version=4 is not supported with KVM");
-+
+-            exit(1);
-+    /* https://elinux.org/BCM2835_registers#PM */
++        if (probe_bitmap & KVM_ARM_VGIC_V2) {
-+    s->rstc = 0x00000102;
++            gics_supported |= VIRT_GIC_VERSION_2_MASK;
-+    s->rsts = 0x00001000;
+         }
-+    s->wdog = 0x00000000;
+-
-+}
+-        /* Check chosen version is effectively supported by the host */
-+
+-        if (vms->gic_version == VIRT_GIC_VERSION_2 &&
-+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
+-            !(probe_bitmap & KVM_ARM_VGIC_V2)) {
-+{
+-            error_report("host does not support in-kernel GICv2 emulation");
-+    DeviceClass *dc = DEVICE_CLASS(klass);
+-            exit(1);
-+
+-        } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
-+    dc->reset = bcm2835_powermgt_reset;
+-                   !(probe_bitmap & KVM_ARM_VGIC_V3)) {
-+    dc->vmsd = &vmstate_bcm2835_powermgt;
+-            error_report("host does not support in-kernel GICv3 emulation");
-+}
+-            exit(1);
-+
++        if (probe_bitmap & KVM_ARM_VGIC_V3) {
-+static TypeInfo bcm2835_powermgt_info = {
++            gics_supported |= VIRT_GIC_VERSION_3_MASK;
-+    .name          = TYPE_BCM2835_POWERMGT,
+         }
-+    .parent        = TYPE_SYS_BUS_DEVICE,
+-        return;
-+    .instance_size = sizeof(BCM2835PowerMgtState),
+-    }
-+    .class_init    = bcm2835_powermgt_class_init,
+-
-+    .instance_init = bcm2835_powermgt_init,
+-    /* TCG mode */
-+};
+-    switch (vms->gic_version) {
-+
+-    case VIRT_GIC_VERSION_NOSEL:
-+static void bcm2835_powermgt_register_types(void)
+-        vms->gic_version = VIRT_GIC_VERSION_2;
-+{
+-        break;
-+    type_register_static(&bcm2835_powermgt_info);
+-    case VIRT_GIC_VERSION_MAX:
-+}
++    } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
-+
++        /* KVM w/o kernel irqchip can only deal with GICv2 */
-+type_init(bcm2835_powermgt_register_types)
++        gics_supported |= VIRT_GIC_VERSION_2_MASK;
-diff --git a/hw/misc/meson.build b/hw/misc/meson.build
++        accel_name = "KVM with kernel-irqchip=off";
-index XXXXXXX..XXXXXXX 100644
++    } else {
---- a/hw/misc/meson.build
++        gics_supported |= VIRT_GIC_VERSION_2_MASK;
-+++ b/hw/misc/meson.build
+         if (module_object_class_by_name("arm-gicv3")) {
-@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
+-            /* CONFIG_ARM_GICV3_TCG was set */
-   'bcm2835_rng.c',
++            gics_supported |= VIRT_GIC_VERSION_3_MASK;
-   'bcm2835_thermal.c',
+             if (vms->virt) {
-   'bcm2835_cprman.c',
+                 /* GICv4 only makes sense if CPU has EL2 */
-+  'bcm2835_powermgt.c',
+-                vms->gic_version = VIRT_GIC_VERSION_4;
- ))
+-            } else {
- softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
+-                vms->gic_version = VIRT_GIC_VERSION_3;
- softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
++                gics_supported |= VIRT_GIC_VERSION_4_MASK;
              }
 -        } else {
 -            vms->gic_version = VIRT_GIC_VERSION_2;
          }
 -        break;
 -    case VIRT_GIC_VERSION_HOST:
 -        error_report("gic-version=host requires KVM");
 -        exit(1);
 -    case VIRT_GIC_VERSION_4:
 -        if (!vms->virt) {
 -            error_report("gic-version=4 requires virtualization enabled");
 -            exit(1);
 -        }
 -        break;
 -    case VIRT_GIC_VERSION_2:
 -    case VIRT_GIC_VERSION_3:
 -        break;
      }
 +
 +    /*
 +     * Then convert helpers like host/max to concrete GIC versions and ensure
 +     * the desired version is supported
 +     */
 +    vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
 +                                               gics_supported, max_cpus);
  }
  /*
 --
-.20.1
+.34.1

-[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
+[PULL 09/33] hw/arm/virt: Make accels in GIC finalize logic explicit
-From: Patrick Venture <venture@google.com>
+From: Alexander Graf <agraf@csgraf.de>
-Add line item reference to quanta-gbs-bmc machine.
+Let's explicitly list out all accelerators that we support when trying to
 determine the supported set of GIC versions. KVM was already separate, so
 the only missing one is HVF which simply reuses all of TCG's emulation
 code and thus has the same compatibility matrix.
-Signed-off-by: Patrick Venture <venture@google.com>
+Signed-off-by: Alexander Graf <agraf@csgraf.de>
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20210615192848.1065297-3-venture@google.com
+Reviewed-by: Cornelia Huck <cohuck@redhat.com>
-[PMM: fixed underline Sphinx warning]
+Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20221223090107.98888-3-agraf@csgraf.de
 [PMM: Added qtest to the list of accelerators]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/nuvoton.rst | 5 +++--
+ hw/arm/virt.c | 7 ++++++-
-file changed, 3 insertions(+), 2 deletions(-)
+file changed, 6 insertions(+), 1 deletion(-)
-diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/nuvoton.rst
+--- a/hw/arm/virt.c
-+++ b/docs/system/arm/nuvoton.rst
++++ b/hw/arm/virt.c
 @@ -XXX,XX +XXX,XX @@
--Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
+ #include "sysemu/numa.h"
--=====================================================
+ #include "sysemu/runstate.h"
-+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
+ #include "sysemu/tpm.h"
-+================================================================
++#include "sysemu/tcg.h"
+ #include "sysemu/kvm.h"
- The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
+ #include "sysemu/hvf.h"
- designed to be used as Baseboard Management Controllers (BMCs) in various
++#include "sysemu/qtest.h"
-@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
+ #include "hw/loader.h"
- The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
+ #include "qapi/error.h"
- Hyperscale applications. The following machines are based on this chip :
+ #include "qemu/bitops.h"
+@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
-+- ``quanta-gbs-bmc``    Quanta GBS server BMC
+         /* KVM w/o kernel irqchip can only deal with GICv2 */
- - ``quanta-gsj``        Quanta GSJ server BMC
+         gics_supported |= VIRT_GIC_VERSION_2_MASK;
+         accel_name = "KVM with kernel-irqchip=off";
- There are also two more SoCs, NPCM710 and NPCM705, which are single-core
+-    } else {
 +    } else if (tcg_enabled() || hvf_enabled() || qtest_enabled())  {
          gics_supported |= VIRT_GIC_VERSION_2_MASK;
          if (module_object_class_by_name("arm-gicv3")) {
              gics_supported |= VIRT_GIC_VERSION_3_MASK;
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
                  gics_supported |= VIRT_GIC_VERSION_4_MASK;
              }
          }
 +    } else {
 +        error_report("Unsupported accelerator, can not determine GIC support");
 +        exit(1);
      }
      /*
 --
-.20.1
+.34.1

-[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
+[PULL 10/33] sbsa-ref: remove cortex-a76 from list of supported cpus
-From: Patrick Venture <venture@google.com>
+From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Adds a line-item reference to the supported quanta-q71l-bmc aspeed
+Cortex-A76 supports 40bits of address space. sbsa-ref's memory
-entry.
+starts above this limit.
-Signed-off-by: Patrick Venture <venture@google.com>
+Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20210615192848.1065297-2-venture@google.com
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230126114416.2447685-1-marcin.juszkiewicz@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/aspeed.rst | 1 +
+ hw/arm/sbsa-ref.c | 1 -
-file changed, 1 insertion(+)
+file changed, 1 deletion(-)
-diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
+diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/aspeed.rst
+--- a/hw/arm/sbsa-ref.c
-+++ b/docs/system/arm/aspeed.rst
++++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ etc.
+@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
- AST2400 SoC based machines :
+ static const char * const valid_cpus[] = {
+     ARM_CPU_TYPE_NAME("cortex-a57"),
- - ``palmetto-bmc``         OpenPOWER Palmetto POWER8 BMC
+     ARM_CPU_TYPE_NAME("cortex-a72"),
-+- ``quanta-q71l-bmc``      OpenBMC Quanta BMC
+-    ARM_CPU_TYPE_NAME("cortex-a76"),
+     ARM_CPU_TYPE_NAME("neoverse-n1"),
- AST2500 SoC based machines :
+     ARM_CPU_TYPE_NAME("max"),
+ };
 --
-.20.1
+.34.1

-New patch
+[PULL 11/33] target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly
+The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT
+S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name
+them AT S1E1R and AT S1E1W (which are entirely different
+instructions).  Fix the names.
+(This has no guest-visible effect as the names are for debug purposes
+only.)
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-2-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-2-peter.maydell@linaro.org
+---
+ target/arm/helper.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
+ #ifndef CONFIG_USER_ONLY
+ static const ARMCPRegInfo ats1e1_reginfo[] = {
+-    { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
++    { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
+       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+       .writefn = ats_write64 },
+-    { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
++    { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
+       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+       .writefn = ats_write64 },
+--
+.34.1

-New patch
+[PULL 12/33] target/arm: Correct syndrome for ATS12NSO* at Secure EL1
+The AArch32 ATS12NSO* address translation operations are supposed to
+trap to either EL2 or EL3 if they're executed at Secure EL1 (which
+can only happen if EL3 is AArch64).  We implement this, but we got
+the syndrome value wrong: like other traps to EL2 or EL3 on an
+AArch32 cpreg access, they should report the 0x3 syndrome, not the
+x0 'uncategorized' syndrome.  This is clear in the access pseudocode
+for these instructions.
+Fix the syndrome value for these operations by correcting the
+returned value from the ats_access() function.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-3-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-3-peter.maydell@linaro.org
+---
+ target/arm/helper.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
+         if (arm_current_el(env) == 1) {
+             if (arm_is_secure_below_el3(env)) {
+                 if (env->cp15.scr_el3 & SCR_EEL2) {
+-                    return CP_ACCESS_TRAP_UNCATEGORIZED_EL2;
++                    return CP_ACCESS_TRAP_EL2;
+                 }
+-                return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
++                return CP_ACCESS_TRAP_EL3;
+             }
+             return CP_ACCESS_TRAP_UNCATEGORIZED;
+         }
+--
+.34.1

-New patch
+[PULL 13/33] target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}
+We added the CPAccessResult values CP_ACCESS_TRAP_UNCATEGORIZED_EL2
+and CP_ACCESS_TRAP_UNCATEGORIZED_EL3 purely in order to use them in
+the ats_access() function, but doing so was incorrect (a bug fixed in
+a previous commit).  There aren't any cases where we want an access
+function to be able to request a trap to EL2 or EL3 with a zero
+syndrome value, so remove these enum values.
+As well as cleaning up dead code, the motivation here is that
+we'd like to implement fine-grained-trap handling in
+helper_access_check_cp_reg(). Although the fine-grained traps
+to EL2 are always lower priority than trap-to-same-EL and
+higher priority than trap-to-EL3, they are in the middle of
+various other kinds of trap-to-EL2. Knowing that a trap-to-EL2
+must always for us have the same syndrome (ie that an access
+function will return CP_ACCESS_TRAP_EL2 and there is no other
+kind of trap-to-EL2 enum value) means we don't have to try
+to choose which of the two syndrome values to report if the
+access would trap to EL2 both for the fine-grained-trap and
+because the access function requires it.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-4-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-4-peter.maydell@linaro.org
+---
+ target/arm/cpregs.h    | 4 ++--
+ target/arm/op_helper.c | 2 ++
+files changed, 4 insertions(+), 2 deletions(-)
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpregs.h
++++ b/target/arm/cpregs.h
+@@ -XXX,XX +XXX,XX @@ typedef enum CPAccessResult {
+      * Access fails and results in an exception syndrome 0x0 ("uncategorized").
+      * Note that this is not a catch-all case -- the set of cases which may
+      * result in this failure is specifically defined by the architecture.
++     * This trap is always to the usual target EL, never directly to a
++     * specified target EL.
+      */
+     CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
+-    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
+-    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
+ } CPAccessResult;
+ typedef struct ARMCPRegInfo ARMCPRegInfo;
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/op_helper.c
++++ b/target/arm/op_helper.c
+@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
+     case CP_ACCESS_TRAP:
+         break;
+     case CP_ACCESS_TRAP_UNCATEGORIZED:
++        /* Only CP_ACCESS_TRAP traps are direct to a specified EL */
++        assert((res & CP_ACCESS_EL_MASK) == 0);
+         if (cpu_isar_feature(aa64_ids, cpu) && isread &&
+             arm_cpreg_in_idspace(ri)) {
+             /*
+--
+.34.1

-[PULL 09/24] target/arm: Make asimd_imm_const() public
+[PULL 14/33] target/arm: Move do_coproc_insn() syndrome calculation earlier
-The function asimd_imm_const() in translate-neon.c is an
+Rearrange the code in do_coproc_insn() so that we calculate the
-implementation of the pseudocode AdvSIMDExpandImm(), which we will
+syndrome value for a potential trap early; we're about to add a
-also want for MVE.  Move the implementation to translate.c, with a
+second check that wants this value earlier than where it is currently
-prototype in translate.h.
+determined.
 (Specifically, a trap to EL2 because of HSTR_EL2 should take
 priority over an UNDEF to EL1, even when the UNDEF is because
 the register does not exist at all or because its ri->access
 bits non-configurably fail the access. So the check we put in
 for HSTR_EL2 trapping at EL1 (which needs the syndrome) is
 going to have to be done before the check "is the ARMCPRegInfo
 pointer NULL".)
 This commit is just code motion; the change to HSTR_EL2
 handling that will use the 'syndrome' variable is in a
 subsequent commit.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-5-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-5-peter.maydell@linaro.org
 ---
- target/arm/translate.h      | 16 ++++++++++
+ target/arm/translate.c | 83 +++++++++++++++++++++---------------------
- target/arm/translate-neon.c | 63 -------------------------------------
+file changed, 41 insertions(+), 42 deletions(-)
  target/arm/translate.c      | 57 +++++++++++++++++++++++++++++++++
 files changed, 73 insertions(+), 63 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
-+++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
-     return opc | s->be_data;
- }
-+/**
-+ * asimd_imm_const: Expand an encoded SIMD constant value
-+ *
-+ * Expand a SIMD constant value. This is essentially the pseudocode
-+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
-+ * VMVN and VBIC (when cmode < 14 && op == 1).
-+ *
-+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
-+ * callers must catch this.
-+ *
-+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
-+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
-+ * we produce an immediate constant value of 0 in these cases.
-+ */
-+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
-+
- #endif /* TARGET_ARM_TRANSLATE_H */
-diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.c
-+++ b/target/arm/translate-neon.c
-@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
- DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
- DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
--static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
--{
--    /*
--     * Expand the encoded constant.
--     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
--     * We choose to not special-case this and will behave as if a
--     * valid constant encoding of 0 had been given.
--     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
--     */
--    switch (cmode) {
--    case 0: case 1:
--        /* no-op */
--        break;
--    case 2: case 3:
--        imm <<= 8;
--        break;
--    case 4: case 5:
--        imm <<= 16;
--        break;
--    case 6: case 7:
--        imm <<= 24;
--        break;
--    case 8: case 9:
--        imm |= imm << 16;
--        break;
--    case 10: case 11:
--        imm = (imm << 8) | (imm << 24);
--        break;
--    case 12:
--        imm = (imm << 8) | 0xff;
--        break;
--    case 13:
--        imm = (imm << 16) | 0xffff;
--        break;
--    case 14:
--        if (op) {
--            /*
--             * This is the only case where the top and bottom 32 bits
--             * of the encoded constant differ.
--             */
--            uint64_t imm64 = 0;
--            int n;
--
--            for (n = 0; n < 8; n++) {
--                if (imm & (1 << n)) {
--                    imm64 |= (0xffULL << (n * 8));
--                }
--            }
--            return imm64;
--        }
--        imm |= (imm << 8) | (imm << 16) | (imm << 24);
--        break;
--    case 15:
--        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
--            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
--        break;
--    }
--    if (op) {
--        imm = ~imm;
--    }
--    return dup_const(MO_32, imm);
--}
--
- static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
-                         GVecGen2iFn *fn)
- {
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
+@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
-     a64_translate_init();
+     const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key);
- }
+     TCGv_ptr tcg_ri = NULL;
+     bool need_exit_tb;
-+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
++    uint32_t syndrome;
-+{
++
-+    /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
++    /*
-+    switch (cmode) {
++     * Note that since we are an implementation which takes an
-+    case 0: case 1:
++     * exception on a trapped conditional instruction only if the
-+        /* no-op */
++     * instruction passes its condition code check, we can take
-+        break;
++     * advantage of the clause in the ARM ARM that allows us to set
-+    case 2: case 3:
++     * the COND field in the instruction to 0xE in all cases.
-+        imm <<= 8;
++     * We could fish the actual condition out of the insn (ARM)
-+        break;
++     * or the condexec bits (Thumb) but it isn't necessary.
-+    case 4: case 5:
++     */
-+        imm <<= 16;
++    switch (cpnum) {
 +        break;
 +    case 6: case 7:
 +        imm <<= 24;
 +        break;
 +    case 8: case 9:
 +        imm |= imm << 16;
 +        break;
 +    case 10: case 11:
 +        imm = (imm << 8) | (imm << 24);
 +        break;
 +    case 12:
 +        imm = (imm << 8) | 0xff;
 +        break;
 +    case 13:
 +        imm = (imm << 16) | 0xffff;
 +        break;
 +    case 14:
-+        if (op) {
++        if (is64) {
-+            /*
++            syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
-+             * This is the only case where the top and bottom 32 bits
++                                         isread, false);
-+             * of the encoded constant differ.
++        } else {
-+             */
++            syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
-+            uint64_t imm64 = 0;
++                                        rt, isread, false);
 +            int n;
 +
 +            for (n = 0; n < 8; n++) {
 +                if (imm & (1 << n)) {
 +                    imm64 |= (0xffULL << (n * 8));
 +                }
 +            }
 +            return imm64;
 +        }
-+        imm |= (imm << 8) | (imm << 16) | (imm << 24);
 +        break;
 +    case 15:
-+        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
++        if (is64) {
-+            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
++            syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
 +                                         isread, false);
 +        } else {
 +            syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
 +                                        rt, isread, false);
 +        }
 +        break;
 +    default:
 +        /*
 +         * ARMv8 defines that only coprocessors 14 and 15 exist,
 +         * so this can only happen if this is an ARMv7 or earlier CPU,
 +         * in which case the syndrome information won't actually be
 +         * guest visible.
 +         */
 +        assert(!arm_dc_feature(s, ARM_FEATURE_V8));
 +        syndrome = syn_uncategorized();
 +        break;
 +    }
-+    if (op) {
-+        imm = ~imm;
+     if (!ri) {
-+    }
+         /*
-+    return dup_const(MO_32, imm);
+@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
-+}
+          * Note that on XScale all cp0..c13 registers do an access check
-+
+          * call in order to handle c15_cpar.
- /* Generate a label used for skipping this instruction */
+          */
- void arm_gen_condlabel(DisasContext *s)
+-        uint32_t syndrome;
- {
+-
 -        /*
 -         * Note that since we are an implementation which takes an
 -         * exception on a trapped conditional instruction only if the
 -         * instruction passes its condition code check, we can take
 -         * advantage of the clause in the ARM ARM that allows us to set
 -         * the COND field in the instruction to 0xE in all cases.
 -         * We could fish the actual condition out of the insn (ARM)
 -         * or the condexec bits (Thumb) but it isn't necessary.
 -         */
 -        switch (cpnum) {
 -        case 14:
 -            if (is64) {
 -                syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
 -                                             isread, false);
 -            } else {
 -                syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
 -                                            rt, isread, false);
 -            }
 -            break;
 -        case 15:
 -            if (is64) {
 -                syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
 -                                             isread, false);
 -            } else {
 -                syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
 -                                            rt, isread, false);
 -            }
 -            break;
 -        default:
 -            /*
 -             * ARMv8 defines that only coprocessors 14 and 15 exist,
 -             * so this can only happen if this is an ARMv7 or earlier CPU,
 -             * in which case the syndrome information won't actually be
 -             * guest visible.
 -             */
 -            assert(!arm_dc_feature(s, ARM_FEATURE_V8));
 -            syndrome = syn_uncategorized();
 -            break;
 -        }
 -
          gen_set_condexec(s);
          gen_update_pc(s, 0);
          tcg_ri = tcg_temp_new_ptr();
 --
-.20.1
+.34.1

-[PULL 20/24] target/arm: Implement MVE VADDLV
+[PULL 15/33] target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
-Implement the MVE VADDLV insn; this is similar to VADDV, except
+The HSTR_EL2 register has a collection of trap bits which allow
-that it accumulates 32-bit elements into a 64-bit accumulator
+trapping to EL2 for AArch32 EL0 or EL1 accesses to coprocessor
-stored in a pair of general-purpose registers.
+registers.  The specification of these bits is that when the bit is
 set we should trap
  * EL1 accesses
  * EL0 accesses, if the access is not UNDEFINED when the
    trap bit is 0
 In other words, all UNDEF traps from EL0 to EL1 take precedence over
 the HSTR_EL2 trap to EL2.  (Since this is all AArch32, the only kind
 of trap-to-EL1 is the UNDEF.)
 Our implementation doesn't quite get this right -- we check for traps
 in the order:
  * no such register
  * ARMCPRegInfo::access bits
  * HSTR_EL2 trap bits
  * ARMCPRegInfo::accessfn
 So UNDEFs that happen because of the access bits or because the
 register doesn't exist at all correctly take priority over the
 HSTR_EL2 trap, but where a register can UNDEF at EL0 because of the
 accessfn we are incorrectly always taking the HSTR_EL2 trap.  There
 aren't many of these, but one example is the PMCR; if you look at the
 access pseudocode for this register you can see that UNDEFs taken
 because of the value of PMUSERENR.EN are checked before the HSTR_EL2
 bit.
 Rearrange helper_access_check_cp_reg() so that we always call the
 accessfn, and use its return value if it indicates that the access
 traps to EL0 rather than continuing to do the HSTR_EL2 check.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-6-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-6-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    |  3 ++
+ target/arm/op_helper.c | 21 ++++++++++++++++-----
- target/arm/mve.decode      |  6 +++-
+file changed, 16 insertions(+), 5 deletions(-)
  target/arm/mve_helper.c    | 19 ++++++++++++
  target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
 files changed, 90 insertions(+), 1 deletion(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/op_helper.c
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/op_helper.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
- DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
+         goto fail;
- DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
+     }
-+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
++    if (ri->accessfn) {
-+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
++        res = ri->accessfn(env, ri, isread);
 +
  DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
  DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
  DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar   1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
  VQRDMULH_scalar  1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
  # Vector add across vector
 -VADDV            111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
 +{
 +  VADDV          111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
 +  VADDLV         111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
 +                 rdahi=%rdahi rdalo=%rdalo
 +}
  # Predicate operations
  %mask_22_13      22:1 13:3
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
  DO_VADDV(vaddvuh, 2, uint16_t)
  DO_VADDV(vaddvuw, 4, uint32_t)
 +#define DO_VADDLV(OP, TYPE, LTYPE)                              \
 +    uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
 +                                    uint64_t ra)                \
 +    {                                                           \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned e;                                             \
 +        TYPE *m = vm;                                           \
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {              \
 +            if (mask & 1) {                                     \
 +                ra += (LTYPE)m[H4(e)];                          \
 +            }                                                   \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +        return ra;                                              \
 +    }                                                           \
 +
 +DO_VADDLV(vaddlv_s, int32_t, int64_t)
 +DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
 +
  /* Shifts by immediate */
  #define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
      void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
      return true;
  }
 +static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
 +{
 +    /*
 +     * Vector Add Long Across Vector: accumulate the 32-bit
 +     * elements of the vector into a 64-bit result stored in
 +     * a pair of general-purpose registers.
 +     * No need to check Qm's bank: it is only 3 bits in decode.
 +     */
 +    TCGv_ptr qm;
 +    TCGv_i64 rda;
 +    TCGv_i32 rdalo, rdahi;
 +
 +    if (!dc_isar_feature(aa32_mve, s)) {
 +        return false;
 +    }
 +    /*
 +     * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
 +     * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
 +     */
 +    if (a->rdahi == 13 || a->rdahi == 15) {
 +        return false;
 +    }
 +    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +        return true;
 +    }
 +
-+    /*
+     /*
-+     * This insn is subject to beat-wise execution. Partial execution
+-     * Check for an EL2 trap due to HSTR_EL2. We expect EL0 accesses
-+     * of an A=0 (no-accumulate) insn which does not execute the first
+-     * to sysregs non accessible at EL0 to have UNDEF-ed already.
-+     * beat must start with the current value of RdaHi:RdaLo, not zero.
++     * If the access function indicates a trap from EL0 to EL1 then
-+     */
++     * that always takes priority over the HSTR_EL2 trap. (If it indicates
-+    if (a->a || mve_skip_first_beat(s)) {
++     * a trap to EL3, then the HSTR_EL2 trap takes priority; if it indicates
-+        /* Accumulate input from RdaHi:RdaLo */
++     * a trap to EL2, then the syndrome is the same either way so we don't
-+        rda = tcg_temp_new_i64();
++     * care whether technically the architecture says that HSTR_EL2 trap or
-+        rdalo = load_reg(s, a->rdalo);
++     * the other trap takes priority. So we take the "check HSTR_EL2" path
-+        rdahi = load_reg(s, a->rdahi);
++     * for all of those cases.)
-+        tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
+      */
-+        tcg_temp_free_i32(rdalo);
++    if (res != CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) == 0) &&
-+        tcg_temp_free_i32(rdahi);
++        arm_current_el(env) == 0) {
-+    } else {
++        goto fail;
 +        /* Accumulate starting at zero */
 +        rda = tcg_const_i64(0);
 +    }
 +
-+    qm = mve_qreg_ptr(a->qm);
+     if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 &&
-+    if (a->u) {
+         (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
-+        gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
+         uint32_t mask = 1 << ri->crn;
-+    } else {
+@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
-+        gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
+         }
-+    }
+     }
-+    tcg_temp_free_ptr(qm);
-+
+-    if (ri->accessfn) {
-+    rdalo = tcg_temp_new_i32();
+-        res = ri->accessfn(env, ri, isread);
-+    rdahi = tcg_temp_new_i32();
+-    }
-+    tcg_gen_extrl_i64_i32(rdalo, rda);
+     if (likely(res == CP_ACCESS_OK)) {
-+    tcg_gen_extrh_i64_i32(rdahi, rda);
+         return ri;
-+    store_reg(s, a->rdalo, rdalo);
+     }
 +    store_reg(s, a->rdahi, rdahi);
 +    tcg_temp_free_i64(rda);
 +    mve_update_eci(s);
 +    return true;
 +}
 +
  static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
  {
      TCGv_ptr qd;
 --
-.20.1
+.34.1

-[PULL 24/24] target/arm: Implement MVE shifts by register
+[PULL 16/33] target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
-Implement the MVE shifts by register, which perform
+The semantics of HSTR_EL2 require that it traps cpreg accesses
-shifts on a single general-purpose register.
+to EL2 for:
  * EL1 accesses
  * EL0 accesses, if the access is not UNDEFINED when the
    trap bit is 0
 (You can see this in the I_ZFGJP priority ordering, where HSTR_EL2
 traps from EL1 to EL2 are priority 12, UNDEFs are priority 13, and
 HSTR_EL2 traps from EL0 are priority 15.)
 However, we don't get this right for EL1 accesses which UNDEF because
 the register doesn't exist at all or because its ri->access bits
 non-configurably forbid the access.  At EL1, check for the HSTR_EL2
 trap early, before either of these UNDEF reasons.
 We have to retain the HSTR_EL2 check in access_check_cp_reg(),
 because at EL0 any kind of UNDEF-to-EL1 (including "no such
 register", "bad ri->access" and "ri->accessfn returns 'trap to EL1'")
 takes precedence over the trap to EL2.  But we only need to do that
 check for EL0 now.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
+Message-id: 20230130182459.3309057-7-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-7-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h |  2 ++
+ target/arm/op_helper.c |  6 +++++-
- target/arm/translate.h  |  1 +
+ target/arm/translate.c | 28 +++++++++++++++++++++++++++-
- target/arm/t32.decode   | 18 ++++++++++++++----
+files changed, 32 insertions(+), 2 deletions(-)
  target/arm/mve_helper.c | 10 ++++++++++
  target/arm/translate.c  | 30 ++++++++++++++++++++++++++++++
 files changed, 57 insertions(+), 4 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/op_helper.c
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/op_helper.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
+@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
+         goto fail;
  DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
  DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
 +DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
 +DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
  typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
  typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
  typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
 +typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
  /**
   * arm_tbflags_from_tb:
 diff --git a/target/arm/t32.decode b/target/arm/t32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/t32.decode
 +++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@
  &mve_shl_ri      rdalo rdahi shim
  &mve_shl_rr      rdalo rdahi rm
  &mve_sh_ri       rda shim
 +&mve_sh_rr       rda rm
  # rdahi: bits [3:1] from insn, bit 0 is 1
  # rdalo: bits [3:1] from insn, bit 0 is 0
@@ -XXX,XX +XXX,XX @@
                   &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
  @mve_sh_ri       ....... .... . rda:4 . ... ... . .. .. .... \
                   &mve_sh_ri shim=%imm5_12_6
 +@mve_sh_rr       ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
  {
    TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
        SQSHLL_ri  1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
      }
--    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
+-    if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 &&
--    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
++    /*
--    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
++     * HSTR_EL2 traps from EL1 are checked earlier, in generated code;
--    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
++     * we only need to check here for traps from EL0.
-+    {
++     */
-+      UQRSHL_rr    1110101 0010 1 ....  ....  1111 0000 1101  @mve_sh_rr
++    if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
-+      LSLL_rr      1110101 0010 1 ... 0 .... ... 1 0000 1101  @mve_shl_rr
+         (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
-+      UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101  @mve_shl_rr
+         uint32_t mask = 1 << ri->crn;
-+    }
 +
 +    {
 +      SQRSHR_rr    1110101 0010 1 ....  ....  1111 0010 1101  @mve_sh_rr
 +      ASRL_rr      1110101 0010 1 ... 0 .... ... 1 0010 1101  @mve_shl_rr
 +      SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101  @mve_shl_rr
 +    }
 +
      UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
      SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
    ]
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
  {
      return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
  }
 +
 +uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
 +{
 +    return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
 +}
 +
 +uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
 +{
 +    return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
+@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
-     return do_mve_sh_ri(s, a, gen_mve_uqshl);
+         break;
- }
+     }
-+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
++    if (s->hstr_active && cpnum == 15 && s->current_el == 1) {
-+{
++        /*
-+    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
++         * At EL1, check for a HSTR_EL2 trap, which must take precedence
-+        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
++         * over the UNDEF for "no such register" or the UNDEF for "access
-+        return false;
++         * permissions forbid this EL1 access". HSTR_EL2 traps from EL0
-+    }
++         * only happen if the cpreg doesn't UNDEF at EL0, so we do those in
-+    if (!dc_isar_feature(aa32_mve, s) ||
++         * access_check_cp_reg(), after the checks for whether the access
-+        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
++         * configurably trapped to EL1.
-+        a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
++         */
-+        a->rm == a->rda) {
++        uint32_t maskbit = is64 ? crm : crn;
-+        /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
++
-+        unallocated_encoding(s);
++        if (maskbit != 4 && maskbit != 14) {
-+        return true;
++            /* T4 and T14 are RES0 so never cause traps */
 +            TCGv_i32 t;
 +            DisasLabel over = gen_disas_label(s);
 +
 +            t = load_cpu_offset(offsetoflow32(CPUARMState, cp15.hstr_el2));
 +            tcg_gen_andi_i32(t, t, 1u << maskbit);
 +            tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label);
 +            tcg_temp_free_i32(t);
 +
 +            gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
 +            set_disas_label(s, over);
 +        }
 +    }
 +
-+    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
+     if (!ri) {
-+    fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
+         /*
-+    return true;
+          * Unknown register; this might be a guest error or a QEMU
-+}
+@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
-+
+         return;
-+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
+     }
-+{
-+    return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
+-    if (s->hstr_active || ri->accessfn ||
-+}
++    if ((s->hstr_active && s->current_el == 0) || ri->accessfn ||
-+
+         (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
-+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
+         /*
-+{
+          * Emit code to perform further access permissions checks at
 +    return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
 +}
 +
  /*
   * Multiply and multiply accumulate
   */
 --
-.20.1
+.34.1

-[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
+[PULL 17/33] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
-The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
+The HSTR_EL2 register is not supposed to have an effect unless EL2 is
-insns had some bugs:
+enabled in the current security state.  We weren't checking for this,
- * the 32x32 multiply of elements was being done as 32x32->32,
+which meant that if the guest set up the HSTR_EL2 register we would
-   not 32x32->64
+incorrectly trap even for accesses from Secure EL0 and EL1.
  * we were incorrectly maintaining the accumulator in its full
 -bit form across all 4 beats of the insn; in the pseudocode
    it is squashed back into the 64 bits of the RdaHi:RdaLo
    registers after each beat
-In particular, fixing the second of these allows us to recast
+Add the missing checks. (Other places where we look at HSTR_EL2
-the implementation to avoid 128-bit arithmetic entirely.
+for the not-in-v8A bits TTEE and TJDBX are already checking that
 we are in NS EL0 or EL1, so there we alredy know EL2 is enabled.)
-Since the element size here is always 4, we can also drop the
-parameterization of ESIZE to make the code a little more readable.
-Suggested-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-8-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-8-peter.maydell@linaro.org
 ---
- target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
+ target/arm/helper.c    | 2 +-
-file changed, 21 insertions(+), 17 deletions(-)
+ target/arm/op_helper.c | 1 +
 files changed, 2 insertions(+), 1 deletion(-)
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve_helper.c
+--- a/target/arm/helper.c
-+++ b/target/arm/mve_helper.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
-  */
+         DP_TBFLAG_A32(flags, VFPEN, 1);
  #include "qemu/osdep.h"
 -#include "qemu/int128.h"
  #include "cpu.h"
  #include "internals.h"
  #include "vec_internal.h"
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
  DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
  /*
 - * Rounding multiply add long dual accumulate high: we must keep
 - * a 72-bit internal accumulator value and return the top 64 bits.
 + * Rounding multiply add long dual accumulate high. In the pseudocode
 + * this is implemented with a 72-bit internal accumulator value of which
 + * the top 64 bits are returned. We optimize this to avoid having to
 + * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
 + * is squashed back into 64-bits after each beat.
   */
 -#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128)         \
 +#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB)                            \
      uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn,         \
                                      void *vm, uint64_t a)               \
      {                                                                   \
          uint16_t mask = mve_element_mask(env);                          \
          unsigned e;                                                     \
          TYPE *n = vn, *m = vm;                                          \
 -        Int128 acc = int128_lshift(TO128(a), 8);                        \
 -        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {              \
 +        for (e = 0; e < 16 / 4; e++, mask >>= 4) {                      \
              if (mask & 1) {                                             \
 +                LTYPE mul;                                              \
                  if (e & 1) {                                            \
 -                    acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
 -                                            m[H##ESIZE(e)]));           \
 +                    mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)];        \
 +                    if (SUB) {                                          \
 +                        mul = -mul;                                     \
 +                    }                                                   \
                  } else {                                                \
 -                    acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
 -                                             m[H##ESIZE(e)]));          \
 +                    mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)];        \
                  }                                                       \
 -                acc = int128_add(acc, int128_make64(1 << 7));           \
 +                mul = (mul >> 8) + ((mul >> 7) & 1);                    \
 +                a += mul;                                               \
              }                                                           \
          }                                                               \
          mve_advance_vpt(env);                                           \
 -        return int128_getlo(int128_rshift(acc, 8));                     \
 +        return a;                                                       \
      }
--DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
+-    if (el < 2 && env->cp15.hstr_el2 &&
--DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
++    if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
-+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
+         (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
-+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
+         DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
+     }
--DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
-+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/op_helper.c
--DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
++++ b/target/arm/op_helper.c
--DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
+@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
-+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
+      * we only need to check here for traps from EL0.
-+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
+      */
+     if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
- /* Vector add across vector */
++        arm_is_el2_enabled(env) &&
- #define DO_VADDV(OP, ESIZE, TYPE)                               \
+         (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
          uint32_t mask = 1 << ri->crn;
 --
-.20.1
+.34.1

-[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
+[PULL 18/33] target/arm: Define the FEAT_FGT registers
-Implement the MVE vector shift right by immediate insns VSHRI and
+Define the system registers which are provided by the
-VRSHRI.  As with Neon, we implement these by using helper functions
+FEAT_FGT fine-grained trap architectural feature:
-which perform left shifts but allow negative shift counts to indicate
+ HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2
-right shifts.
 All these registers are a set of bit fields, where each bit is set
 for a trap and clear to not trap on a particular system register
 access.  The R and W register pairs are for system registers,
 allowing trapping to be done separately for reads and writes; the I
 register is for system instructions where trapping is on instruction
 execution.
 The data storage in the CPU state struct is arranged as a set of
 arrays rather than separate fields so that when we're looking up the
 bits for a system register access we can just index into the array
 rather than having to use a switch to select a named struct member.
 The later FEAT_FGT2 will add extra elements to these arrays.
 The field definitions for the new registers are in cpregs.h because
 in practice the code that needs them is code that also needs
 the cpregs information; cpu.h is included in a lot more files.
 We're also going to add some FGT-specific definitions to cpregs.h
 in the next commit.
 We do not implement HAFGRTR_EL2, because we don't implement
 FEAT_AMUv1.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-9-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-9-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h     | 12 ++++++++++++
+ target/arm/cpregs.h | 285 ++++++++++++++++++++++++++++++++++++++++++++
- target/arm/translate.h      | 20 ++++++++++++++++++++
+ target/arm/cpu.h    |  15 +++
- target/arm/mve.decode       | 28 ++++++++++++++++++++++++++++
+ target/arm/helper.c |  40 +++++++
- target/arm/mve_helper.c     |  7 +++++++
+files changed, 340 insertions(+)
- target/arm/translate-mve.c  |  5 +++++
- target/arm/translate-neon.c | 18 ------------------
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 files changed, 72 insertions(+), 18 deletions(-)
 diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/cpregs.h
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
+@@ -XXX,XX +XXX,XX @@ typedef enum CPAccessResult {
- DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
+     CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
- DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
+ } CPAccessResult;
-+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++/* Indexes into fgt_read[] */
-+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++#define FGTREG_HFGRTR 0
-+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++#define FGTREG_HDFGRTR 1
-+
++/* Indexes into fgt_write[] */
- DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++#define FGTREG_HFGWTR 0
- DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++#define FGTREG_HDFGWTR 1
- DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++/* Indexes into fgt_exec[] */
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++#define FGTREG_HFGITR 0
- DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++
- DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1)
- DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1)
-+
++FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1)
-+DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1)
-+DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++FIELD(HFGRTR_EL2, APDAKEY, 4, 1)
-+DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++FIELD(HFGRTR_EL2, APDBKEY, 5, 1)
-+
++FIELD(HFGRTR_EL2, APGAKEY, 6, 1)
-+DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++FIELD(HFGRTR_EL2, APIAKEY, 7, 1)
-+DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++FIELD(HFGRTR_EL2, APIBKEY, 8, 1)
-+DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
++FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1)
 +FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1)
 +FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1)
 +FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1)
 +FIELD(HFGRTR_EL2, CTR_EL0, 14, 1)
 +FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1)
 +FIELD(HFGRTR_EL2, ESR_EL1, 16, 1)
 +FIELD(HFGRTR_EL2, FAR_EL1, 17, 1)
 +FIELD(HFGRTR_EL2, ISR_EL1, 18, 1)
 +FIELD(HFGRTR_EL2, LORC_EL1, 19, 1)
 +FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1)
 +FIELD(HFGRTR_EL2, LORID_EL1, 21, 1)
 +FIELD(HFGRTR_EL2, LORN_EL1, 22, 1)
 +FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1)
 +FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1)
 +FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1)
 +FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1)
 +FIELD(HFGRTR_EL2, PAR_EL1, 27, 1)
 +FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1)
 +FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1)
 +FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1)
 +FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1)
 +FIELD(HFGRTR_EL2, TCR_EL1, 32, 1)
 +FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1)
 +FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1)
 +FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1)
 +FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1)
 +FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1)
 +FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1)
 +FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1)
 +FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1)
 +FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1)
 +FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1)
 +FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1)
 +FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1)
 +FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1)
 +FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1)
 +FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1)
 +FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1)
 +FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1)
 +FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1)
 +/* 51-53: RES0 */
 +FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1)
 +FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1)
 +/* 56-63: RES0 */
 +
 +/* These match HFGRTR but bits for RO registers are RES0 */
 +FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1)
 +FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1)
 +FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1)
 +FIELD(HFGWTR_EL2, APDAKEY, 4, 1)
 +FIELD(HFGWTR_EL2, APDBKEY, 5, 1)
 +FIELD(HFGWTR_EL2, APGAKEY, 6, 1)
 +FIELD(HFGWTR_EL2, APIAKEY, 7, 1)
 +FIELD(HFGWTR_EL2, APIBKEY, 8, 1)
 +FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1)
 +FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1)
 +FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1)
 +FIELD(HFGWTR_EL2, ESR_EL1, 16, 1)
 +FIELD(HFGWTR_EL2, FAR_EL1, 17, 1)
 +FIELD(HFGWTR_EL2, LORC_EL1, 19, 1)
 +FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1)
 +FIELD(HFGWTR_EL2, LORN_EL1, 22, 1)
 +FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1)
 +FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1)
 +FIELD(HFGWTR_EL2, PAR_EL1, 27, 1)
 +FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1)
 +FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1)
 +FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1)
 +FIELD(HFGWTR_EL2, TCR_EL1, 32, 1)
 +FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1)
 +FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1)
 +FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1)
 +FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1)
 +FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1)
 +FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1)
 +FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1)
 +FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1)
 +FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1)
 +FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1)
 +FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1)
 +FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1)
 +FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1)
 +FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1)
 +FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1)
 +FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1)
 +FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1)
 +
 +FIELD(HFGITR_EL2, ICIALLUIS, 0, 1)
 +FIELD(HFGITR_EL2, ICIALLU, 1, 1)
 +FIELD(HFGITR_EL2, ICIVAU, 2, 1)
 +FIELD(HFGITR_EL2, DCIVAC, 3, 1)
 +FIELD(HFGITR_EL2, DCISW, 4, 1)
 +FIELD(HFGITR_EL2, DCCSW, 5, 1)
 +FIELD(HFGITR_EL2, DCCISW, 6, 1)
 +FIELD(HFGITR_EL2, DCCVAU, 7, 1)
 +FIELD(HFGITR_EL2, DCCVAP, 8, 1)
 +FIELD(HFGITR_EL2, DCCVADP, 9, 1)
 +FIELD(HFGITR_EL2, DCCIVAC, 10, 1)
 +FIELD(HFGITR_EL2, DCZVA, 11, 1)
 +FIELD(HFGITR_EL2, ATS1E1R, 12, 1)
 +FIELD(HFGITR_EL2, ATS1E1W, 13, 1)
 +FIELD(HFGITR_EL2, ATS1E0R, 14, 1)
 +FIELD(HFGITR_EL2, ATS1E0W, 15, 1)
 +FIELD(HFGITR_EL2, ATS1E1RP, 16, 1)
 +FIELD(HFGITR_EL2, ATS1E1WP, 17, 1)
 +FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1)
 +FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1)
 +FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1)
 +FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1)
 +FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1)
 +FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1)
 +FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1)
 +FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1)
 +FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1)
 +FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1)
 +FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1)
 +FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1)
 +FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1)
 +FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1)
 +FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1)
 +FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1)
 +FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1)
 +FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1)
 +FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1)
 +FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1)
 +FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1)
 +FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1)
 +FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1)
 +FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1)
 +FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1)
 +FIELD(HFGITR_EL2, TLBIVAE1, 43, 1)
 +FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1)
 +FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1)
 +FIELD(HFGITR_EL2, TLBIVALE1, 46, 1)
 +FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1)
 +FIELD(HFGITR_EL2, CFPRCTX, 48, 1)
 +FIELD(HFGITR_EL2, DVPRCTX, 49, 1)
 +FIELD(HFGITR_EL2, CPPRCTX, 50, 1)
 +FIELD(HFGITR_EL2, ERET, 51, 1)
 +FIELD(HFGITR_EL2, SVC_EL0, 52, 1)
 +FIELD(HFGITR_EL2, SVC_EL1, 53, 1)
 +FIELD(HFGITR_EL2, DCCVAC, 54, 1)
 +FIELD(HFGITR_EL2, NBRBINJ, 55, 1)
 +FIELD(HFGITR_EL2, NBRBIALL, 56, 1)
 +
 +FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1)
 +FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1)
 +FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1)
 +FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1)
 +FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1)
 +FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1)
 +FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1)
 +FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1)
 +/* 8: RES0: OSLAR_EL1 is WO */
 +FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1)
 +FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1)
 +FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1)
 +FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1)
 +FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1)
 +FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1)
 +FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1)
 +FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1)
 +FIELD(HDFGRTR_EL2, PMINTEN, 17, 1)
 +FIELD(HDFGRTR_EL2, PMOVS, 18, 1)
 +FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1)
 +/* 20: RES0: PMSWINC_EL0 is WO */
 +/* 21: RES0: PMCR_EL0 is WO */
 +FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1)
 +FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1)
 +FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1)
 +FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1)
 +FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1)
 +FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1)
 +FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1)
 +FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1)
 +FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1)
 +FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1)
 +FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1)
 +FIELD(HDFGRTR_EL2, TRC, 33, 1)
 +FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1)
 +FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1)
 +FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1)
 +FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1)
 +/* 38, 39: RES0 */
 +FIELD(HDFGRTR_EL2, TRCID, 40, 1)
 +FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1)
 +/* 42: RES0: TRCOSLAR is WO */
 +FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1)
 +FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1)
 +FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1)
 +FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1)
 +FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1)
 +FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1)
 +/* 49: RES0: TRFCR_EL1 is WO */
 +FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1)
 +FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1)
 +FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1)
 +FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1)
 +FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1)
 +FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1)
 +FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1)
 +FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1)
 +FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1)
 +FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1)
 +FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1)
 +FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1)
 +FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1)
 +FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1)
 +
 +/*
 + * These match HDFGRTR_EL2, but bits for RO registers are RES0.
 + * A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0.
 + */
 +FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1)
 +FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1)
 +FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1)
 +FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1)
 +FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1)
 +FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1)
 +FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1)
 +FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1)
 +FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1)
 +FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1)
 +FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1)
 +FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1)
 +FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1)
 +FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1)
 +FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1)
 +FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1)
 +FIELD(HDFGWTR_EL2, PMINTEN, 17, 1)
 +FIELD(HDFGWTR_EL2, PMOVS, 18, 1)
 +FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1)
 +FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1)
 +FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1)
 +FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1)
 +FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1)
 +FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1)
 +FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1)
 +FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1)
 +FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1)
 +FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1)
 +FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1)
 +FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1)
 +FIELD(HDFGWTR_EL2, TRC, 33, 1)
 +FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1)
 +FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1)
 +FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1)
 +FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1)
 +FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1)
 +FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1)
 +FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1)
 +FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1)
 +FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1)
 +FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1)
 +FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1)
 +FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1)
 +FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1)
 +FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1)
 +FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1)
 +FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1)
 +FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1)
 +FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
 +FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
 +FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
 +
  typedef struct ARMCPRegInfo ARMCPRegInfo;
  /*
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
+--- a/target/arm/cpu.h
-+++ b/target/arm/translate.h
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
-     return x * 2 + 1;
+         uint64_t disr_el1;
          uint64_t vdisr_el2;
          uint64_t vsesr_el2;
 +
 +        /*
 +         * Fine-Grained Trap registers. We store these as arrays so the
 +         * access checking code doesn't have to manually select
 +         * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test.
 +         * FEAT_FGT2 will add more elements to these arrays.
 +         */
 +        uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
 +        uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */
 +        uint64_t fgt_exec[1]; /* HFGITR */
      } cp15;
      struct {
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
      return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
  }
-+static inline int rsub_64(DisasContext *s, int x)
++static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
 +{
-+    return 64 - x;
++    return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
 +}
 +
-+static inline int rsub_32(DisasContext *s, int x)
+ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
  {
      return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
          if (cpu_isar_feature(aa64_hcx, cpu)) {
              valid_mask |= SCR_HXEN;
          }
 +        if (cpu_isar_feature(aa64_fgt, cpu)) {
 +            valid_mask |= SCR_FGTEN;
 +        }
      } else {
          valid_mask &= ~(SCR_RW | SCR_ST);
          if (cpu_isar_feature(aa32_ras, cpu)) {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
        .access = PL3_RW,
        .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
  };
 +
 +static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri,
 +                                 bool isread)
 +{
-+    return 32 - x;
++    if (arm_current_el(env) == 2 &&
 +        arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_FGTEN)) {
 +        return CP_ACCESS_TRAP_EL3;
 +    }
 +    return CP_ACCESS_OK;
 +}
 +
-+static inline int rsub_16(DisasContext *s, int x)
++static const ARMCPRegInfo fgt_reginfo[] = {
-+{
++    { .name = "HFGRTR_EL2", .state = ARM_CP_STATE_AA64,
-+    return 16 - x;
++      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
-+}
++      .access = PL2_RW, .accessfn = access_fgt,
-+
++      .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR]) },
-+static inline int rsub_8(DisasContext *s, int x)
++    { .name = "HFGWTR_EL2", .state = ARM_CP_STATE_AA64,
-+{
++      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 5,
-+    return 8 - x;
++      .access = PL2_RW, .accessfn = access_fgt,
-+}
++      .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]) },
-+
++    { .name = "HDFGRTR_EL2", .state = ARM_CP_STATE_AA64,
- static inline int arm_dc_feature(DisasContext *dc, int feature)
++      .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 4,
- {
++      .access = PL2_RW, .accessfn = access_fgt,
-     return (dc->features & (1ULL << feature)) != 0;
++      .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]) },
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
++    { .name = "HDFGWTR_EL2", .state = ARM_CP_STATE_AA64,
-index XXXXXXX..XXXXXXX 100644
++      .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 5,
---- a/target/arm/mve.decode
++      .access = PL2_RW, .accessfn = access_fgt,
-+++ b/target/arm/mve.decode
++      .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR]) },
-@@ -XXX,XX +XXX,XX @@
++    { .name = "HFGITR_EL2", .state = ARM_CP_STATE_AA64,
- @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
++      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 6,
- @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
++      .access = PL2_RW, .accessfn = access_fgt,
++      .fieldoffset = offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR]) },
-+# Right shifts are encoded as N - shift, where N is the element size in bits.
++};
-+%rshift_i5  16:5 !function=rsub_32
+ #endif /* TARGET_AARCH64 */
-+%rshift_i4  16:4 !function=rsub_16
-+%rshift_i3  16:3 !function=rsub_8
+ static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
-+
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-+@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
+     if (cpu_isar_feature(aa64_scxtnum, cpu)) {
-+         size=0 shift=%rshift_i3
+         define_arm_cp_regs(cpu, scxtnum_reginfo);
-+@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
+     }
-+         size=1 shift=%rshift_i4
++
-+@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
++    if (cpu_isar_feature(aa64_fgt, cpu)) {
-+         size=2 shift=%rshift_i5
++        define_arm_cp_regs(cpu, fgt_reginfo);
-+
++    }
- # Vector loads and stores
+ #endif
- # Widening loads and narrowing stores:
+     if (cpu_isar_feature(any_predinv, cpu)) {
@@ -XXX,XX +XXX,XX @@ VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
  VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
  VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
  VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
 +
 +VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
 +VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
 +VSHRI_S           111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
 +
 +VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
 +VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
 +VSHRI_U           111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
 +
 +VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 +VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 +VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 +
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 +VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
      DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
      DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
      DO_2SHIFT(OP##w, 4, uint32_t, FN)
 +#define DO_2SHIFT_S(OP, FN)                     \
 +    DO_2SHIFT(OP##b, 1, int8_t, FN)             \
 +    DO_2SHIFT(OP##h, 2, int16_t, FN)            \
 +    DO_2SHIFT(OP##w, 4, int32_t, FN)
  #define DO_2SHIFT_SAT_U(OP, FN)                 \
      DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
      DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
  DO_2SHIFT_U(vshli_u, DO_VSHLU)
 +DO_2SHIFT_S(vshli_s, DO_VSHLS)
  DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
  DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
  DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
 +DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
 +DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
  DO_2SHIFT(VQSHLI_S, vqshli_s, false)
  DO_2SHIFT(VQSHLI_U, vqshli_u, false)
  DO_2SHIFT(VQSHLUI, vqshlui_s, false)
 +/* These right shifts use a left-shift helper with negated shift count */
 +DO_2SHIFT(VSHRI_S, vshli_s, true)
 +DO_2SHIFT(VSHRI_U, vshli_u, true)
 +DO_2SHIFT(VRSHRI_S, vrshli_s, true)
 +DO_2SHIFT(VRSHRI_U, vrshli_u, true)
 diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.c
 +++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
      return x + 1;
  }
 -static inline int rsub_64(DisasContext *s, int x)
 -{
 -    return 64 - x;
 -}
 -
 -static inline int rsub_32(DisasContext *s, int x)
 -{
 -    return 32 - x;
 -}
 -static inline int rsub_16(DisasContext *s, int x)
 -{
 -    return 16 - x;
 -}
 -static inline int rsub_8(DisasContext *s, int x)
 -{
 -    return 8 - x;
 -}
 -
  static inline int neon_3same_fp_size(DisasContext *s, int x)
  {
      /* Convert 0==fp32, 1==fp16 into a MO_* value */
 --
-.20.1
+.34.1

-[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
+[PULL 19/33] target/arm: Implement FGT trapping infrastructure
-The A64 AdvSIMD modified-immediate grouping uses almost the same
+Implement the machinery for fine-grained traps on normal sysregs.
-constant encoding that A32 Neon does; reuse asimd_imm_const() (to
+Any sysreg with a fine-grained trap will set the new field to
-which we add the AArch64-specific case for cmode 15 op 1) instead of
+indicate which FGT register bit it should trap on.
-reimplementing it all.
 FGT traps only happen when an AArch64 EL2 enables them for
 an AArch64 EL1. They therefore are only relevant for AArch32
 cpregs when the cpreg can be accessed from EL0. The logic
 in access_check_cp_reg() will check this, so it is safe to
 add a .fgt marking to an ARM_CP_STATE_BOTH ARMCPRegInfo.
 The DO_BIT and DO_REV_BIT macros define enum constants FGT_##bitname
 which can be used to specify the FGT bit, eg
    .fgt = FGT_AFSR0_EL1
 (We assume that there is no bit name duplication across the FGT
 registers, for brevity's sake.)
 Subsequent commits will add the .fgt fields to the relevant register
 definitions and define the FGT_nnn values for them.
 Note that some of the FGT traps are for instructions that we don't
 handle via the cpregs mechanisms (mostly these are instruction traps).
 Those we will have to handle separately.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-10-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-10-peter.maydell@linaro.org
 ---
- target/arm/translate.h     |  3 +-
+ target/arm/cpregs.h        | 72 ++++++++++++++++++++++++++++++++++++++
- target/arm/translate-a64.c | 86 ++++----------------------------------
+ target/arm/cpu.h           |  1 +
- target/arm/translate.c     | 17 +++++++-
+ target/arm/internals.h     | 20 +++++++++++
-files changed, 24 insertions(+), 82 deletions(-)
+ target/arm/translate.h     |  2 ++
+ target/arm/helper.c        |  9 +++++
  target/arm/op_helper.c     | 30 ++++++++++++++++
  target/arm/translate-a64.c |  3 +-
  target/arm/translate.c     |  2 ++
 files changed, 138 insertions(+), 1 deletion(-)
 diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpregs.h
 +++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
  FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
  FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
 +/* Which fine-grained trap bit register to check, if any */
 +FIELD(FGT, TYPE, 10, 3)
 +FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */
 +FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */
 +FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */
 +
 +/*
 + * Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::fgt
 + * fields. We assume for brevity's sake that there are no duplicated
 + * bit names across the various FGT registers.
 + */
 +#define DO_BIT(REG, BITNAME)                                    \
 +    FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT
 +
 +/* Some bits have reversed sense, so 0 means trap and 1 means not */
 +#define DO_REV_BIT(REG, BITNAME)                                        \
 +    FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT
 +
 +typedef enum FGTBit {
 +    /*
 +     * These bits tell us which register arrays to use:
 +     * if FGT_R is set then reads are checked against fgt_read[];
 +     * if FGT_W is set then writes are checked against fgt_write[];
 +     * if FGT_EXEC is set then all accesses are checked against fgt_exec[].
 +     *
 +     * For almost all bits in the R/W register pairs, the bit exists in
 +     * both registers for a RW register, in HFGRTR/HDFGRTR for a RO register
 +     * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa
 +     * for a WO register. There are unfortunately a couple of exceptions
 +     * (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but
 +     * the FGT system only allows trapping of writes, not reads.
 +     *
 +     * Note that we arrange these bits so that a 0 FGTBit means "no trap".
 +     */
 +    FGT_R = 1 << R_FGT_TYPE_SHIFT,
 +    FGT_W = 2 << R_FGT_TYPE_SHIFT,
 +    FGT_EXEC = 4 << R_FGT_TYPE_SHIFT,
 +    FGT_RW = FGT_R | FGT_W,
 +    /* Bit to identify whether trap bit is reversed sense */
 +    FGT_REV = R_FGT_REV_MASK,
 +
 +    /*
 +     * If a bit exists in HFGRTR/HDFGRTR then either the register being
 +     * trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either
 +     * want to trap for both reads and writes or else it's harmless to mark
 +     * it as trap-on-writes.
 +     * If a bit exists only in HFGWTR/HDFGWTR then either the register being
 +     * trapped is WO, or else it is one of the two oddball special cases
 +     * which are RW but have only a write trap. We mark these as only
 +     * FGT_W so we get the right behaviour for those special cases.
 +     * (If a bit was added in future that provided only a read trap for an
 +     * RW register we'd need to do something special to get the FGT_R bit
 +     * only. But this seems unlikely to happen.)
 +     *
 +     * So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if
 +     * the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGWTR.
 +     */
 +    FGT_HFGRTR = FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT),
 +    FGT_HFGWTR = FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT),
 +    FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
 +    FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
 +    FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
 +} FGTBit;
 +
 +#undef DO_BIT
 +#undef DO_REV_BIT
 +
  typedef struct ARMCPRegInfo ARMCPRegInfo;
  /*
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
      CPAccessRights access;
      /* Security state: ARM_CP_SECSTATE_* bits/values */
      CPSecureState secure;
 +    /*
 +     * Which fine-grained trap register bit to check, if any. This
 +     * value encodes both the trap register and bit within it.
 +     */
 +    FGTBit fgt;
      /*
       * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
       * this register was defined: can be used to hand data through to the
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
  /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
  FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
  FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
 +FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
  /*
   * Bit usage when in AArch32 state, both A- and M-profile.
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
      ((1 << (1 - 1)) | (1 << (2 - 1)) |                  \
       (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1)))
 +/*
 + * Return true if it is possible to take a fine-grained-trap to EL2.
 + */
 +static inline bool arm_fgt_active(CPUARMState *env, int el)
 +{
 +    /*
 +     * The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps
 +     * that can affect EL0, but it is harmless to do the test also for
 +     * traps on registers that are only accessible at EL1 because if the test
 +     * returns true then we can't be executing at EL1 anyway.
 +     * FGT traps only happen when EL2 is enabled and EL1 is AArch64;
 +     * traps from AArch32 only happen for the EL0 is AArch32 case.
 +     */
 +    return cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
 +        el < 2 && arm_is_el2_enabled(env) &&
 +        arm_el_is_aa64(env, 1) &&
 +        (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE) &&
 +        (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN));
 +}
 +
  #endif
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-  * VMVN and VBIC (when cmode < 14 && op == 1).
+     bool is_nonstreaming;
-  *
+     /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
-  * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
+     bool mve_no_pred;
-- * callers must catch this.
++    /* True if fine-grained traps are active */
-+ * callers must catch this; we return the 64-bit constant value defined
++    bool fgt_active;
-+ * for AArch64.
+     /*
-  *
+      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
-  * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
+      *  < 0, set by the current instruction.
-  * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
      if (arm_singlestep_active(env)) {
          DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
      }
 +
      return flags;
  }
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
          DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
      }
 +    if (arm_fgt_active(env, el)) {
 +        DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
 +    }
 +
      if (env->uncached_cpsr & CPSR_IL) {
          DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
      }
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
          DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
      }
 +    if (arm_fgt_active(env, el)) {
 +        DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
 +    }
 +
      if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
          /*
           * Set MTE_ACTIVE if any access may be Checked, and leave clear
 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/op_helper.c
 +++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
          }
      }
 +    /*
 +     * Fine-grained traps also are lower priority than undef-to-EL1,
 +     * higher priority than trap-to-EL3, and we don't care about priority
 +     * order with other EL2 traps because the syndrome value is the same.
 +     */
 +    if (arm_fgt_active(env, arm_current_el(env))) {
 +        uint64_t trapword = 0;
 +        unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX);
 +        unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS);
 +        bool rev = FIELD_EX32(ri->fgt, FGT, REV);
 +        bool trapbit;
 +
 +        if (ri->fgt & FGT_EXEC) {
 +            assert(idx < ARRAY_SIZE(env->cp15.fgt_exec));
 +            trapword = env->cp15.fgt_exec[idx];
 +        } else if (isread && (ri->fgt & FGT_R)) {
 +            assert(idx < ARRAY_SIZE(env->cp15.fgt_read));
 +            trapword = env->cp15.fgt_read[idx];
 +        } else if (!isread && (ri->fgt & FGT_W)) {
 +            assert(idx < ARRAY_SIZE(env->cp15.fgt_write));
 +            trapword = env->cp15.fgt_write[idx];
 +        }
 +
 +        trapbit = extract64(trapword, bitpos, 1);
 +        if (trapbit != rev) {
 +            res = CP_ACCESS_TRAP_EL2;
 +            goto fail;
 +        }
 +    }
 +
      if (likely(res == CP_ACCESS_OK)) {
          return ri;
      }
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
  {
      int rd = extract32(insn, 0, 5);
      int cmode = extract32(insn, 12, 4);
 -    int cmode_3_1 = extract32(cmode, 1, 3);
 -    int cmode_0 = extract32(cmode, 0, 1);
      int o2 = extract32(insn, 11, 1);
      uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
      bool is_neg = extract32(insn, 29, 1);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
          return;
      }
--    /* See AdvSIMDExpandImm() in ARM ARM */
+-    if (ri->accessfn) {
--    switch (cmode_3_1) {
++    if (ri->accessfn || (ri->fgt && s->fgt_active)) {
--    case 0: /* Replicate(Zeros(24):imm8, 2) */
+         /* Emit code to perform further access permissions checks at
--    case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
+          * runtime; this may result in an exception.
--    case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
+          */
--    case 3: /* Replicate(imm8:Zeros(24), 2) */
+@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
--    {
+     dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
--        int shift = cmode_3_1 * 8;
+     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
--        imm = bitfield_replicate(abcdefgh << shift, 32);
+     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
--        break;
++    dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
--    }
+     dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
--    case 4: /* Replicate(Zeros(8):imm8, 4) */
+     dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
--    case 5: /* Replicate(imm8:Zeros(8), 4) */
+     dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;
 -    {
 -        int shift = (cmode_3_1 & 0x1) * 8;
 -        imm = bitfield_replicate(abcdefgh << shift, 16);
 -        break;
 -    }
 -    case 6:
 -        if (cmode_0) {
 -            /* Replicate(Zeros(8):imm8:Ones(16), 2) */
 -            imm = (abcdefgh << 16) | 0xffff;
 -        } else {
 -            /* Replicate(Zeros(16):imm8:Ones(8), 2) */
 -            imm = (abcdefgh << 8) | 0xff;
 -        }
 -        imm = bitfield_replicate(imm, 32);
 -        break;
 -    case 7:
 -        if (!cmode_0 && !is_neg) {
 -            imm = bitfield_replicate(abcdefgh, 8);
 -        } else if (!cmode_0 && is_neg) {
 -            int i;
 -            imm = 0;
 -            for (i = 0; i < 8; i++) {
 -                if ((abcdefgh) & (1 << i)) {
 -                    imm |= 0xffULL << (i * 8);
 -                }
 -            }
 -        } else if (cmode_0) {
 -            if (is_neg) {
 -                imm = (abcdefgh & 0x3f) << 48;
 -                if (abcdefgh & 0x80) {
 -                    imm |= 0x8000000000000000ULL;
 -                }
 -                if (abcdefgh & 0x40) {
 -                    imm |= 0x3fc0000000000000ULL;
 -                } else {
 -                    imm |= 0x4000000000000000ULL;
 -                }
 -            } else {
 -                if (o2) {
 -                    /* FMOV (vector, immediate) - half-precision */
 -                    imm = vfp_expand_imm(MO_16, abcdefgh);
 -                    /* now duplicate across the lanes */
 -                    imm = bitfield_replicate(imm, 16);
 -                } else {
 -                    imm = (abcdefgh & 0x3f) << 19;
 -                    if (abcdefgh & 0x80) {
 -                        imm |= 0x80000000;
 -                    }
 -                    if (abcdefgh & 0x40) {
 -                        imm |= 0x3e000000;
 -                    } else {
 -                        imm |= 0x40000000;
 -                    }
 -                    imm |= (imm << 32);
 -                }
 -            }
 -        }
 -        break;
 -    default:
 -        g_assert_not_reached();
 -    }
 -
 -    if (cmode_3_1 != 7 && is_neg) {
 -        imm = ~imm;
 +    if (cmode == 15 && o2 && !is_neg) {
 +        /* FMOV (vector, immediate) - half-precision */
 +        imm = vfp_expand_imm(MO_16, abcdefgh);
 +        /* now duplicate across the lanes */
 +        imm = bitfield_replicate(imm, 16);
 +    } else {
 +        imm = asimd_imm_const(abcdefgh, cmode, is_neg);
      }
      if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
+@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
-     case 14:
+     }
-         if (op) {
-             /*
+     if ((s->hstr_active && s->current_el == 0) || ri->accessfn ||
--             * This is the only case where the top and bottom 32 bits
++        (ri->fgt && s->fgt_active) ||
--             * of the encoded constant differ.
+         (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
-+             * This and cmode == 15 op == 1 are the only cases where
+         /*
-+             * the top and bottom 32 bits of the encoded constant differ.
+          * Emit code to perform further access permissions checks at
-              */
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-             uint64_t imm64 = 0;
+     dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
-             int n;
+     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
-@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
+     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
-         imm |= (imm << 8) | (imm << 16) | (imm << 24);
++    dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
-         break;
-     case 15:
+     if (arm_feature(env, ARM_FEATURE_M)) {
-+        if (op) {
+         dc->vfp_enabled = 1;
 +            /* Reserved encoding for AArch32; valid for AArch64 */
 +            uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
 +            if (imm & 0x80) {
 +                imm64 |= 0x8000000000000000ULL;
 +            }
 +            if (imm & 0x40) {
 +                imm64 |= 0x3fc0000000000000ULL;
 +            } else {
 +                imm64 |= 0x4000000000000000ULL;
 +            }
 +            return imm64;
 +        }
          imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
              | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
          break;
 --
-.20.1
+.34.1

-New patch
+[PULL 20/33] target/arm: Mark up sysregs for HFGRTR bits 0..11
+Mark up the sysreg definitions for the registers trapped
+by HFGRTR/HFGWTR bits 0..11.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-11-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-11-peter.maydell@linaro.org
+---
+ target/arm/cpregs.h | 14 ++++++++++++++
+ target/arm/helper.c | 17 +++++++++++++++++
+files changed, 31 insertions(+)
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpregs.h
++++ b/target/arm/cpregs.h
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
+     FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
+     FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
+     FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
++
++    /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */
++    DO_BIT(HFGRTR, AFSR0_EL1),
++    DO_BIT(HFGRTR, AFSR1_EL1),
++    DO_BIT(HFGRTR, AIDR_EL1),
++    DO_BIT(HFGRTR, AMAIR_EL1),
++    DO_BIT(HFGRTR, APDAKEY),
++    DO_BIT(HFGRTR, APDBKEY),
++    DO_BIT(HFGRTR, APGAKEY),
++    DO_BIT(HFGRTR, APIAKEY),
++    DO_BIT(HFGRTR, APIBKEY),
++    DO_BIT(HFGRTR, CCSIDR_EL1),
++    DO_BIT(HFGRTR, CLIDR_EL1),
++    DO_BIT(HFGRTR, CONTEXTIDR_EL1),
+ } FGTBit;
+ #undef DO_BIT
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
+     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
+       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
++      .fgt = FGT_CONTEXTIDR_EL1,
+       .secure = ARM_CP_SECSTATE_NS,
+       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
+       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
+       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
+       .access = PL1_R,
+       .accessfn = access_tid4,
++      .fgt = FGT_CCSIDR_EL1,
+       .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
+     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
+       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
+       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
+       .access = PL1_R, .type = ARM_CP_CONST,
+       .accessfn = access_aa64_tid1,
++      .fgt = FGT_AIDR_EL1,
+       .resetvalue = 0 },
+     /*
+      * Auxiliary fault status registers: these also are IMPDEF, and we
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
+     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
+       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
++      .fgt = FGT_AFSR0_EL1,
+       .type = ARM_CP_CONST, .resetvalue = 0 },
+     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
+       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
++      .fgt = FGT_AFSR1_EL1,
+       .type = ARM_CP_CONST, .resetvalue = 0 },
+     /*
+      * MAIR can just read-as-written because we don't implement caches
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
+     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
+       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
++      .fgt = FGT_AMAIR_EL1,
+       .type = ARM_CP_CONST, .resetvalue = 0 },
+     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
+     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
+     { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_pauth,
++      .fgt = FGT_APDAKEY,
+       .fieldoffset = offsetof(CPUARMState, keys.apda.lo) },
+     { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1,
+       .access = PL1_RW, .accessfn = access_pauth,
++      .fgt = FGT_APDAKEY,
+       .fieldoffset = offsetof(CPUARMState, keys.apda.hi) },
+     { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2,
+       .access = PL1_RW, .accessfn = access_pauth,
++      .fgt = FGT_APDBKEY,
+       .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) },
+     { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3,
+       .access = PL1_RW, .accessfn = access_pauth,
++      .fgt = FGT_APDBKEY,
+       .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) },
+     { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_pauth,
++      .fgt = FGT_APGAKEY,
+       .fieldoffset = offsetof(CPUARMState, keys.apga.lo) },
+     { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1,
+       .access = PL1_RW, .accessfn = access_pauth,
++      .fgt = FGT_APGAKEY,
+       .fieldoffset = offsetof(CPUARMState, keys.apga.hi) },
+     { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_pauth,
++      .fgt = FGT_APIAKEY,
+       .fieldoffset = offsetof(CPUARMState, keys.apia.lo) },
+     { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1,
+       .access = PL1_RW, .accessfn = access_pauth,
++      .fgt = FGT_APIAKEY,
+       .fieldoffset = offsetof(CPUARMState, keys.apia.hi) },
+     { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2,
+       .access = PL1_RW, .accessfn = access_pauth,
++      .fgt = FGT_APIBKEY,
+       .fieldoffset = offsetof(CPUARMState, keys.apib.lo) },
+     { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
+       .access = PL1_RW, .accessfn = access_pauth,
++      .fgt = FGT_APIBKEY,
+       .fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
+ };
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
+             .access = PL1_R, .type = ARM_CP_CONST,
+             .accessfn = access_tid4,
++            .fgt = FGT_CLIDR_EL1,
+             .resetvalue = cpu->clidr
+         };
+         define_one_arm_cp_reg(cpu, &clidr);
+--
+.34.1

-New patch
+[PULL 21/33] target/arm: Mark up sysregs for HFGRTR bits 12..23
+Mark up the sysreg definitions for the registers trapped
+by HFGRTR/HFGWTR bits 12..23.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-12-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-12-peter.maydell@linaro.org
+---
+ target/arm/cpregs.h | 12 ++++++++++++
+ target/arm/helper.c | 12 ++++++++++++
+files changed, 24 insertions(+)
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpregs.h
++++ b/target/arm/cpregs.h
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
+     DO_BIT(HFGRTR, CCSIDR_EL1),
+     DO_BIT(HFGRTR, CLIDR_EL1),
+     DO_BIT(HFGRTR, CONTEXTIDR_EL1),
++    DO_BIT(HFGRTR, CPACR_EL1),
++    DO_BIT(HFGRTR, CSSELR_EL1),
++    DO_BIT(HFGRTR, CTR_EL0),
++    DO_BIT(HFGRTR, DCZID_EL0),
++    DO_BIT(HFGRTR, ESR_EL1),
++    DO_BIT(HFGRTR, FAR_EL1),
++    DO_BIT(HFGRTR, ISR_EL1),
++    DO_BIT(HFGRTR, LORC_EL1),
++    DO_BIT(HFGRTR, LOREA_EL1),
++    DO_BIT(HFGRTR, LORID_EL1),
++    DO_BIT(HFGRTR, LORN_EL1),
++    DO_BIT(HFGRTR, LORSA_EL1),
+ } FGTBit;
+ #undef DO_BIT
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
+       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
+     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
+       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
++      .fgt = FGT_CPACR_EL1,
+       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
+       .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
+ };
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
+       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
+       .access = PL1_RW,
+       .accessfn = access_tid4,
++      .fgt = FGT_CSSELR_EL1,
+       .writefn = csselr_write, .resetvalue = 0,
+       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
+                              offsetof(CPUARMState, cp15.csselr_ns) } },
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
+       .resetfn = arm_cp_reset_ignore },
+     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
+       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
++      .fgt = FGT_ISR_EL1,
+       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
+     /* 32 bit ITLB invalidates */
+     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
+     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
++      .fgt = FGT_FAR_EL1,
+       .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
+       .resetvalue = 0, },
+ };
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
+     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
++      .fgt = FGT_ESR_EL1,
+       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
+     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
+     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
+       .access = PL0_R, .type = ARM_CP_NO_RAW,
++      .fgt = FGT_DCZID_EL0,
+       .readfn = aa64_dczid_read },
+     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
+     { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_lor_other,
++      .fgt = FGT_LORSA_EL1,
+       .type = ARM_CP_CONST, .resetvalue = 0 },
+     { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
+       .access = PL1_RW, .accessfn = access_lor_other,
++      .fgt = FGT_LOREA_EL1,
+       .type = ARM_CP_CONST, .resetvalue = 0 },
+     { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
+       .access = PL1_RW, .accessfn = access_lor_other,
++      .fgt = FGT_LORN_EL1,
+       .type = ARM_CP_CONST, .resetvalue = 0 },
+     { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
+       .access = PL1_RW, .accessfn = access_lor_other,
++      .fgt = FGT_LORC_EL1,
+       .type = ARM_CP_CONST, .resetvalue = 0 },
+     { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
+       .access = PL1_R, .accessfn = access_lor_ns,
++      .fgt = FGT_LORID_EL1,
+       .type = ARM_CP_CONST, .resetvalue = 0 },
+ };
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
+               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
+               .access = PL0_R, .accessfn = ctr_el0_access,
++              .fgt = FGT_CTR_EL0,
+               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
+             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
+             { .name = "TCMTR",
+--
+.34.1

-New patch
+[PULL 22/33] target/arm: Mark up sysregs for HFGRTR bits 24..35
+Mark up the sysreg definitions for the registers trapped
+by HFGRTR/HFGWTR bits 24..35.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-13-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-13-peter.maydell@linaro.org
+---
+ target/arm/cpregs.h | 12 ++++++++++++
+ target/arm/helper.c | 14 ++++++++++++++
+files changed, 26 insertions(+)
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpregs.h
++++ b/target/arm/cpregs.h
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
+     DO_BIT(HFGRTR, LORID_EL1),
+     DO_BIT(HFGRTR, LORN_EL1),
+     DO_BIT(HFGRTR, LORSA_EL1),
++    DO_BIT(HFGRTR, MAIR_EL1),
++    DO_BIT(HFGRTR, MIDR_EL1),
++    DO_BIT(HFGRTR, MPIDR_EL1),
++    DO_BIT(HFGRTR, PAR_EL1),
++    DO_BIT(HFGRTR, REVIDR_EL1),
++    DO_BIT(HFGRTR, SCTLR_EL1),
++    DO_BIT(HFGRTR, SCXTNUM_EL1),
++    DO_BIT(HFGRTR, SCXTNUM_EL0),
++    DO_BIT(HFGRTR, TCR_EL1),
++    DO_BIT(HFGRTR, TPIDR_EL1),
++    DO_BIT(HFGRTR, TPIDRRO_EL0),
++    DO_BIT(HFGRTR, TPIDR_EL0),
+ } FGTBit;
+ #undef DO_BIT
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
+     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
++      .fgt = FGT_MAIR_EL1,
+       .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
+       .resetvalue = 0 },
+     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
+     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
+       .access = PL0_RW,
++      .fgt = FGT_TPIDR_EL0,
+       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
+     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
+       .access = PL0_RW,
++      .fgt = FGT_TPIDR_EL0,
+       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
+                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
+       .resetfn = arm_cp_reset_ignore },
+     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
+       .access = PL0_R | PL1_W,
++      .fgt = FGT_TPIDRRO_EL0,
+       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
+       .resetvalue = 0},
+     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
+       .access = PL0_R | PL1_W,
++      .fgt = FGT_TPIDRRO_EL0,
+       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
+                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
+       .resetfn = arm_cp_reset_ignore },
+     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
+       .access = PL1_RW,
++      .fgt = FGT_TPIDR_EL1,
+       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
+     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
+       .access = PL1_RW,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
+     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
++      .fgt = FGT_TCR_EL1,
+       .writefn = vmsa_tcr_el12_write,
+       .raw_writefn = raw_write,
+       .resetvalue = 0,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
+       .type = ARM_CP_ALIAS,
+       .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
+       .access = PL1_RW, .resetvalue = 0,
++      .fgt = FGT_PAR_EL1,
+       .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
+       .writefn = par_write },
+ #endif
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
+     { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
+       .access = PL0_RW, .accessfn = access_scxtnum,
++      .fgt = FGT_SCXTNUM_EL0,
+       .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
+     { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
+       .access = PL1_RW, .accessfn = access_scxtnum,
++      .fgt = FGT_SCXTNUM_EL1,
+       .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
+     { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
+               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
+               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
++              .fgt = FGT_MIDR_EL1,
+               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
+               .readfn = midr_read },
+             /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
+               .access = PL1_R,
+               .accessfn = access_aa64_tid1,
++              .fgt = FGT_REVIDR_EL1,
+               .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
+         };
+         ARMCPRegInfo id_v8_midr_alias_cp_reginfo = {
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+         ARMCPRegInfo mpidr_cp_reginfo[] = {
+             { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
+               .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
++              .fgt = FGT_MPIDR_EL1,
+               .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
+         };
+ #ifdef CONFIG_USER_ONLY
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
+             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
+             .access = PL1_RW, .accessfn = access_tvm_trvm,
++            .fgt = FGT_SCTLR_EL1,
+             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
+                                    offsetof(CPUARMState, cp15.sctlr_ns) },
+             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
+--
+.34.1

-New patch
+[PULL 23/33] target/arm: Mark up sysregs for HFGRTR bits 36..63
+Mark up the sysreg definitions for the registers trapped
+by HFGRTR/HFGWTR bits 36..63.
+Of these, some correspond to RAS registers which we implement as
+always-UNDEF: these don't need any extra handling for FGT because the
+UNDEF-to-EL1 always takes priority over any theoretical
+FGT-trap-to-EL2.
+Bit 50 (NACCDATA_EL1) is for the ACCDATA_EL1 register which is part
+of the FEAT_LS64_ACCDATA feature which we don't yet implement.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-14-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-14-peter.maydell@linaro.org
+---
+ target/arm/cpregs.h       |  7 +++++++
+ hw/intc/arm_gicv3_cpuif.c |  2 ++
+ target/arm/helper.c       | 10 ++++++++++
+files changed, 19 insertions(+)
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpregs.h
++++ b/target/arm/cpregs.h
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
+     DO_BIT(HFGRTR, TPIDR_EL1),
+     DO_BIT(HFGRTR, TPIDRRO_EL0),
+     DO_BIT(HFGRTR, TPIDR_EL0),
++    DO_BIT(HFGRTR, TTBR0_EL1),
++    DO_BIT(HFGRTR, TTBR1_EL1),
++    DO_BIT(HFGRTR, VBAR_EL1),
++    DO_BIT(HFGRTR, ICC_IGRPENN_EL1),
++    DO_BIT(HFGRTR, ERRIDR_EL1),
++    DO_REV_BIT(HFGRTR, NSMPRI_EL1),
++    DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
+ } FGTBit;
+ #undef DO_BIT
+diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/arm_gicv3_cpuif.c
++++ b/hw/intc/arm_gicv3_cpuif.c
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
+       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 6,
+       .type = ARM_CP_IO | ARM_CP_NO_RAW,
+       .access = PL1_RW, .accessfn = gicv3_fiq_access,
++      .fgt = FGT_ICC_IGRPENN_EL1,
+       .readfn = icc_igrpen_read,
+       .writefn = icc_igrpen_write,
+     },
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
+       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7,
+       .type = ARM_CP_IO | ARM_CP_NO_RAW,
+       .access = PL1_RW, .accessfn = gicv3_irq_access,
++      .fgt = FGT_ICC_IGRPENN_EL1,
+       .readfn = icc_igrpen_read,
+       .writefn = icc_igrpen_write,
+     },
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
+     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
++      .fgt = FGT_TTBR0_EL1,
+       .writefn = vmsa_ttbr_write, .resetvalue = 0,
+       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
+                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
+     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
++      .fgt = FGT_TTBR1_EL1,
+       .writefn = vmsa_ttbr_write, .resetvalue = 0,
+       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
+                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
+@@ -XXX,XX +XXX,XX @@ static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
+  *   ERRSELR_EL1
+  * may generate UNDEFINED, which is the effect we get by not
+  * listing them at all.
++ *
++ * These registers have fine-grained trap bits, but UNDEF-to-EL1
++ * is higher priority than FGT-to-EL2 so we do not need to list them
++ * in order to check for an FGT.
+  */
+ static const ARMCPRegInfo minimal_ras_reginfo[] = {
+     { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo minimal_ras_reginfo[] = {
+     { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
+       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
+       .access = PL1_R, .accessfn = access_terr,
++      .fgt = FGT_ERRIDR_EL1,
+       .type = ARM_CP_CONST, .resetvalue = 0 },
+     { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
+       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {
+     { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5,
+       .access = PL0_RW, .accessfn = access_tpidr2,
++      .fgt = FGT_NTPIDR2_EL0,
+       .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) },
+     { .name = "SVCR", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {
+     { .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4,
+       .access = PL1_RW, .accessfn = access_esm,
++      .fgt = FGT_NSMPRI_EL1,
+       .type = ARM_CP_CONST, .resetvalue = 0 },
+     { .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5,
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+             { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
+               .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
+               .access = PL1_RW, .writefn = vbar_write,
++              .fgt = FGT_VBAR_EL1,
+               .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
+                                      offsetof(CPUARMState, cp15.vbar_ns) },
+               .resetvalue = 0 },
+--
+.34.1

-New patch
+[PULL 24/33] target/arm: Mark up sysregs for HDFGRTR bits 0..11
+Mark up the sysreg definitons for the registers trapped
+by HDFGRTR/HDFGWTR bits 0..11. These cover various debug
+related registers.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-15-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-15-peter.maydell@linaro.org
+---
+ target/arm/cpregs.h       | 12 ++++++++++++
+ target/arm/debug_helper.c | 11 +++++++++++
+files changed, 23 insertions(+)
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpregs.h
++++ b/target/arm/cpregs.h
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
+     DO_BIT(HFGRTR, ERRIDR_EL1),
+     DO_REV_BIT(HFGRTR, NSMPRI_EL1),
+     DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
++
++    /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */
++    DO_BIT(HDFGRTR, DBGBCRN_EL1),
++    DO_BIT(HDFGRTR, DBGBVRN_EL1),
++    DO_BIT(HDFGRTR, DBGWCRN_EL1),
++    DO_BIT(HDFGRTR, DBGWVRN_EL1),
++    DO_BIT(HDFGRTR, MDSCR_EL1),
++    DO_BIT(HDFGRTR, DBGCLAIM),
++    DO_BIT(HDFGWTR, OSLAR_EL1),
++    DO_BIT(HDFGRTR, OSLSR_EL1),
++    DO_BIT(HDFGRTR, OSECCR_EL1),
++    DO_BIT(HDFGRTR, OSDLR_EL1),
+ } FGTBit;
+ #undef DO_BIT
+diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/debug_helper.c
++++ b/target/arm/debug_helper.c
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
+     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
+       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
+       .access = PL1_RW, .accessfn = access_tda,
++      .fgt = FGT_MDSCR_EL1,
+       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
+       .resetvalue = 0 },
+     /*
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
+     { .name = "OSECCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
+       .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
+       .access = PL1_RW, .accessfn = access_tda,
++      .fgt = FGT_OSECCR_EL1,
+       .type = ARM_CP_CONST, .resetvalue = 0 },
+     /*
+      * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2].  Map all bits as
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
+       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
+       .access = PL1_W, .type = ARM_CP_NO_RAW,
+       .accessfn = access_tdosa,
++      .fgt = FGT_OSLAR_EL1,
+       .writefn = oslar_write },
+     { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
+       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
+       .access = PL1_R, .resetvalue = 10,
+       .accessfn = access_tdosa,
++      .fgt = FGT_OSLSR_EL1,
+       .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
+     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
+     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
+       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
+       .access = PL1_RW, .accessfn = access_tdosa,
++      .fgt = FGT_OSDLR_EL1,
+       .writefn = osdlr_write,
+       .fieldoffset = offsetof(CPUARMState, cp15.osdlr_el1) },
+     /*
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
+       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
+       .type = ARM_CP_ALIAS,
+       .access = PL1_RW, .accessfn = access_tda,
++      .fgt = FGT_DBGCLAIM,
+       .writefn = dbgclaimset_write, .readfn = dbgclaimset_read },
+     { .name = "DBGCLAIMCLR_EL1", .state = ARM_CP_STATE_BOTH,
+       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 6,
+       .access = PL1_RW, .accessfn = access_tda,
++      .fgt = FGT_DBGCLAIM,
+       .writefn = dbgclaimclr_write, .raw_writefn = raw_write,
+       .fieldoffset = offsetof(CPUARMState, cp15.dbgclaim) },
+ };
+@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
+             { .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH,
+               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
+               .access = PL1_RW, .accessfn = access_tda,
++              .fgt = FGT_DBGBVRN_EL1,
+               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
+               .writefn = dbgbvr_write, .raw_writefn = raw_write
+             },
+             { .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH,
+               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
+               .access = PL1_RW, .accessfn = access_tda,
++              .fgt = FGT_DBGBCRN_EL1,
+               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
+               .writefn = dbgbcr_write, .raw_writefn = raw_write
+             },
+@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
+             { .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH,
+               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
+               .access = PL1_RW, .accessfn = access_tda,
++              .fgt = FGT_DBGWVRN_EL1,
+               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
+               .writefn = dbgwvr_write, .raw_writefn = raw_write
+             },
+             { .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH,
+               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
+               .access = PL1_RW, .accessfn = access_tda,
++              .fgt = FGT_DBGWCRN_EL1,
+               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
+               .writefn = dbgwcr_write, .raw_writefn = raw_write
+             },
+--
+.34.1

-[PULL 19/24] target/arm: Implement MVE VSHLC
+[PULL 25/33] target/arm: Mark up sysregs for HDFGRTR bits 12..63
-Implement the MVE VSHLC insn, which performs a shift left of the
+Mark up the sysreg definitions for the registers trapped
-entire vector with carry in bits provided from a general purpose
+by HDFGRTR/HDFGWTR bits 12..x.
-register and carry out bits written back to that register.
 Bits 12..22 and bit 58 are for PMU registers.
 The remaining bits in HDFGRTR/HDFGWTR are for traps on
 registers that are part of features we don't implement:
 Bits 23..32 and 63 : FEAT_SPE
 Bits 33..48 : FEAT_ETE
 Bits 50..56 : FEAT_TRBE
 Bits 59..61 : FEAT_BRBE
 Bit 62 : FEAT_SPEv1p2.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-16-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-16-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    |  2 ++
+ target/arm/cpregs.h | 12 ++++++++++++
- target/arm/mve.decode      |  2 ++
+ target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++
- target/arm/mve_helper.c    | 38 ++++++++++++++++++++++++++++++++++++++
+files changed, 49 insertions(+)
- target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
-files changed, 72 insertions(+)
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/cpregs.h
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
- DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     DO_BIT(HDFGRTR, OSLSR_EL1),
- DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     DO_BIT(HDFGRTR, OSECCR_EL1),
- DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     DO_BIT(HDFGRTR, OSDLR_EL1),
-+
++    DO_BIT(HDFGRTR, PMEVCNTRN_EL0),
-+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
++    DO_BIT(HDFGRTR, PMEVTYPERN_EL0),
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
++    DO_BIT(HDFGRTR, PMCCFILTR_EL0),
 +    DO_BIT(HDFGRTR, PMCCNTR_EL0),
 +    DO_BIT(HDFGRTR, PMCNTEN),
 +    DO_BIT(HDFGRTR, PMINTEN),
 +    DO_BIT(HDFGRTR, PMOVS),
 +    DO_BIT(HDFGRTR, PMSELR_EL0),
 +    DO_BIT(HDFGWTR, PMSWINC_EL0),
 +    DO_BIT(HDFGWTR, PMCR_EL0),
 +    DO_BIT(HDFGRTR, PMMIR_EL1),
 +    DO_BIT(HDFGRTR, PMCEIDN_EL0),
  } FGTBit;
  #undef DO_BIT
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
+--- a/target/arm/helper.c
-+++ b/target/arm/mve.decode
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
- VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
- VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+       .writefn = pmcntenset_write,
- VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
+       .accessfn = pmreg_access,
-+
++      .fgt = FGT_PMCNTEN,
-+VSHLC             111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
+       .raw_writefn = raw_write },
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
+     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
-index XXXXXXX..XXXXXXX 100644
+       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
---- a/target/arm/mve_helper.c
+       .access = PL0_RW, .accessfn = pmreg_access,
-+++ b/target/arm/mve_helper.c
++      .fgt = FGT_PMCNTEN,
-@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
+       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
- DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
+       .writefn = pmcntenset_write, .raw_writefn = raw_write },
- DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
+     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
- DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
+       .access = PL0_RW,
-+
+       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
-+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
+       .accessfn = pmreg_access,
-+                           uint32_t shift)
++      .fgt = FGT_PMCNTEN,
-+{
+       .writefn = pmcntenclr_write,
-+    uint32_t *d = vd;
+       .type = ARM_CP_ALIAS | ARM_CP_IO },
-+    uint16_t mask = mve_element_mask(env);
+     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
-+    unsigned e;
+       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
-+    uint32_t r;
+       .access = PL0_RW, .accessfn = pmreg_access,
-+
++      .fgt = FGT_PMCNTEN,
-+    /*
+       .type = ARM_CP_ALIAS | ARM_CP_IO,
-+     * For each 32-bit element, we shift it left, bringing in the
+       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
-+     * low 'shift' bits of rdm at the bottom. Bits shifted out at
+       .writefn = pmcntenclr_write },
-+     * the top become the new rdm, if the predicate mask permits.
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
-+     * The final rdm value is returned to update the register.
+       .access = PL0_RW, .type = ARM_CP_IO,
-+     * shift == 0 here means "shift by 32 bits".
+       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
-+     */
+       .accessfn = pmreg_access,
-+    if (shift == 0) {
++      .fgt = FGT_PMOVS,
-+        for (e = 0; e < 16 / 4; e++, mask >>= 4) {
+       .writefn = pmovsr_write,
-+            r = rdm;
+       .raw_writefn = raw_write },
-+            if (mask & 1) {
+     { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
-+                rdm = d[H4(e)];
+       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
-+            }
+       .access = PL0_RW, .accessfn = pmreg_access,
-+            mergemask(&d[H4(e)], r, mask);
++      .fgt = FGT_PMOVS,
-+        }
+       .type = ARM_CP_ALIAS | ARM_CP_IO,
-+    } else {
+       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
-+        uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
+       .writefn = pmovsr_write,
-+
+       .raw_writefn = raw_write },
-+        for (e = 0; e < 16 / 4; e++, mask >>= 4) {
+     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
-+            r = (d[H4(e)] << shift) | (rdm & shiftmask);
+       .access = PL0_W, .accessfn = pmreg_access_swinc,
-+            if (mask & 1) {
++      .fgt = FGT_PMSWINC_EL0,
-+                rdm = d[H4(e)] >> (32 - shift);
+       .type = ARM_CP_NO_RAW | ARM_CP_IO,
-+            }
+       .writefn = pmswinc_write },
-+            mergemask(&d[H4(e)], r, mask);
+     { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
-+        }
+       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4,
-+    }
+       .access = PL0_W, .accessfn = pmreg_access_swinc,
-+    mve_advance_vpt(env);
++      .fgt = FGT_PMSWINC_EL0,
-+    return rdm;
+       .type = ARM_CP_NO_RAW | ARM_CP_IO,
-+}
+       .writefn = pmswinc_write },
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
+     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
-index XXXXXXX..XXXXXXX 100644
+       .access = PL0_RW, .type = ARM_CP_ALIAS,
---- a/target/arm/translate-mve.c
++      .fgt = FGT_PMSELR_EL0,
-+++ b/target/arm/translate-mve.c
+       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
-@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
+       .accessfn = pmreg_access_selr, .writefn = pmselr_write,
- DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
+       .raw_writefn = raw_write},
- DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
+     { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
- DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
+       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
-+
+       .access = PL0_RW, .accessfn = pmreg_access_selr,
-+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
++      .fgt = FGT_PMSELR_EL0,
-+{
+       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
-+    /*
+       .writefn = pmselr_write, .raw_writefn = raw_write, },
-+     * Whole Vector Left Shift with Carry. The carry is taken
+     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
-+     * from a general purpose register and written back there.
+       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
-+     * An imm of 0 means "shift by 32".
++      .fgt = FGT_PMCCNTR_EL0,
-+     */
+       .readfn = pmccntr_read, .writefn = pmccntr_write32,
-+    TCGv_ptr qd;
+       .accessfn = pmreg_access_ccntr },
-+    TCGv_i32 rdm;
+     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
-+
+       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
-+    if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
+       .access = PL0_RW, .accessfn = pmreg_access_ccntr,
-+        return false;
++      .fgt = FGT_PMCCNTR_EL0,
-+    }
+       .type = ARM_CP_IO,
-+    if (a->rdm == 13 || a->rdm == 15) {
+       .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
-+        /* CONSTRAINED UNPREDICTABLE: we UNDEF */
+       .readfn = pmccntr_read, .writefn = pmccntr_write,
-+        return false;
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
-+    }
+     { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7,
-+    if (!mve_eci_check(s) || !vfp_access_check(s)) {
+       .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
-+        return true;
+       .access = PL0_RW, .accessfn = pmreg_access,
-+    }
++      .fgt = FGT_PMCCFILTR_EL0,
-+
+       .type = ARM_CP_ALIAS | ARM_CP_IO,
-+    qd = mve_qreg_ptr(a->qd);
+       .resetvalue = 0, },
-+    rdm = load_reg(s, a->rdm);
+     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
-+    gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
+       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
-+    store_reg(s, a->rdm, rdm);
+       .writefn = pmccfiltr_write, .raw_writefn = raw_write,
-+    tcg_temp_free_ptr(qd);
+       .access = PL0_RW, .accessfn = pmreg_access,
-+    mve_update_eci(s);
++      .fgt = FGT_PMCCFILTR_EL0,
-+    return true;
+       .type = ARM_CP_IO,
-+}
+       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
        .resetvalue = 0, },
      { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
        .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
        .accessfn = pmreg_access,
 +      .fgt = FGT_PMEVTYPERN_EL0,
        .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
      { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
        .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
        .accessfn = pmreg_access,
 +      .fgt = FGT_PMEVTYPERN_EL0,
        .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
      { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
        .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
        .accessfn = pmreg_access_xevcntr,
 +      .fgt = FGT_PMEVCNTRN_EL0,
        .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
      { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2,
        .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
        .accessfn = pmreg_access_xevcntr,
 +      .fgt = FGT_PMEVCNTRN_EL0,
        .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
      { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
        .access = PL0_R | PL1_RW, .accessfn = access_tpm,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
        .writefn = pmuserenr_write, .raw_writefn = raw_write },
      { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_tpm,
 +      .fgt = FGT_PMINTEN,
        .type = ARM_CP_ALIAS | ARM_CP_IO,
        .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
        .resetvalue = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
      { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_tpm,
 +      .fgt = FGT_PMINTEN,
        .type = ARM_CP_IO,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
        .writefn = pmintenset_write, .raw_writefn = raw_write,
        .resetvalue = 0x0 },
      { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
        .access = PL1_RW, .accessfn = access_tpm,
 +      .fgt = FGT_PMINTEN,
        .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
        .writefn = pmintenclr_write, },
      { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
        .access = PL1_RW, .accessfn = access_tpm,
 +      .fgt = FGT_PMINTEN,
        .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
        .writefn = pmintenclr_write },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
      /* PMOVSSET is not implemented in v7 before v7ve */
      { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
        .access = PL0_RW, .accessfn = pmreg_access,
 +      .fgt = FGT_PMOVS,
        .type = ARM_CP_ALIAS | ARM_CP_IO,
        .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
        .writefn = pmovsset_write,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
      { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
        .access = PL0_RW, .accessfn = pmreg_access,
 +      .fgt = FGT_PMOVS,
        .type = ARM_CP_ALIAS | ARM_CP_IO,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
        .writefn = pmovsset_write,
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
      ARMCPRegInfo pmcr = {
          .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
          .access = PL0_RW,
 +        .fgt = FGT_PMCR_EL0,
          .type = ARM_CP_IO | ARM_CP_ALIAS,
          .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
          .accessfn = pmreg_access, .writefn = pmcr_write,
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
          .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
          .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
          .access = PL0_RW, .accessfn = pmreg_access,
 +        .fgt = FGT_PMCR_EL0,
          .type = ARM_CP_IO,
          .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
          .resetvalue = cpu->isar.reset_pmcr_el0,
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
              { .name = pmevcntr_name, .cp = 15, .crn = 14,
                .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
                .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
 +              .fgt = FGT_PMEVCNTRN_EL0,
                .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
                .accessfn = pmreg_access_xevcntr },
              { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
                .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr,
                .type = ARM_CP_IO,
 +              .fgt = FGT_PMEVCNTRN_EL0,
                .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
                .raw_readfn = pmevcntr_rawread,
                .raw_writefn = pmevcntr_rawwrite },
              { .name = pmevtyper_name, .cp = 15, .crn = 14,
                .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
                .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
 +              .fgt = FGT_PMEVTYPERN_EL0,
                .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
                .accessfn = pmreg_access },
              { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
                .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
 +              .fgt = FGT_PMEVTYPERN_EL0,
                .type = ARM_CP_IO,
                .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
                .raw_writefn = pmevtyper_rawwrite },
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
              { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
                .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
 +              .fgt = FGT_PMCEIDN_EL0,
                .resetvalue = extract64(cpu->pmceid0, 32, 32) },
              { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
                .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
 +              .fgt = FGT_PMCEIDN_EL0,
                .resetvalue = extract64(cpu->pmceid1, 32, 32) },
          };
          define_arm_cp_regs(cpu, v81_pmu_regs);
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
              .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH,
              .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6,
              .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
 +            .fgt = FGT_PMMIR_EL1,
              .resetvalue = 0
          };
          define_one_arm_cp_reg(cpu, &v84_pmmir);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
                .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
 +              .fgt = FGT_PMCEIDN_EL0,
                .resetvalue = extract64(cpu->pmceid0, 0, 32) },
              { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
 +              .fgt = FGT_PMCEIDN_EL0,
                .resetvalue = cpu->pmceid0 },
              { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
                .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
 +              .fgt = FGT_PMCEIDN_EL0,
                .resetvalue = extract64(cpu->pmceid1, 0, 32) },
              { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
 +              .fgt = FGT_PMCEIDN_EL0,
                .resetvalue = cpu->pmceid1 },
          };
  #ifdef CONFIG_USER_ONLY
 --
-.20.1
+.34.1

-[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
+[PULL 26/33] target/arm: Mark up sysregs for HFGITR bits 0..11
-Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
+Mark up the sysreg definitions for the system instructions
+trapped by HFGITR bits 0..11. These bits cover various
-do_urshr() is borrowed from sve_helper.c.
+cache maintenance operations.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-17-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-17-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    | 10 ++++++++++
+ target/arm/cpregs.h | 14 ++++++++++++++
- target/arm/mve.decode      | 11 +++++++++++
+ target/arm/helper.c | 28 ++++++++++++++++++++++++++++
- target/arm/mve_helper.c    | 40 ++++++++++++++++++++++++++++++++++++++
+files changed, 42 insertions(+)
  target/arm/translate-mve.c | 15 ++++++++++++++
 files changed, 76 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/cpregs.h
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
- DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     DO_BIT(HDFGWTR, PMCR_EL0),
- DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     DO_BIT(HDFGRTR, PMMIR_EL1),
- DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     DO_BIT(HDFGRTR, PMCEIDN_EL0),
 +
-+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    /* Trap bits in HFGITR_EL2, starting from bit 0 */
-+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, ICIALLUIS),
-+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, ICIALLU),
-+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, ICIVAU),
-+
++    DO_BIT(HFGITR, DCIVAC),
-+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, DCISW),
-+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, DCCSW),
-+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, DCCISW),
-+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, DCCVAU),
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
++    DO_BIT(HFGITR, DCCVAP),
 +    DO_BIT(HFGITR, DCCVADP),
 +    DO_BIT(HFGITR, DCCIVAC),
 +    DO_BIT(HFGITR, DCZVA),
  } FGTBit;
  #undef DO_BIT
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
+--- a/target/arm/helper.c
-+++ b/target/arm/mve.decode
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
- VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
+ #ifndef CONFIG_USER_ONLY
- VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
+       /* Avoid overhead of an access check that always passes in user-mode */
- VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
+       .accessfn = aa64_zva_access,
-+
++      .fgt = FGT_DCZVA,
-+# Narrowing shifts (which only support b and h sizes)
+ #endif
-+VSHRNB            111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
+     },
-+VSHRNB            111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
+     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
-+VSHRNT            111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-+VSHRNT            111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
+     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
-+
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
-+VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
+       .access = PL1_W, .type = ARM_CP_NOP,
-+VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
++      .fgt = FGT_ICIALLUIS,
-+VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
+       .accessfn = access_ticab },
-+VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
+     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
-index XXXXXXX..XXXXXXX 100644
+       .access = PL1_W, .type = ARM_CP_NOP,
---- a/target/arm/mve_helper.c
++      .fgt = FGT_ICIALLU,
-+++ b/target/arm/mve_helper.c
+       .accessfn = access_tocu },
-@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
+     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
- DO_VSHLL_ALL(vshllb, false)
+       .access = PL0_W, .type = ARM_CP_NOP,
- DO_VSHLL_ALL(vshllt, true)
++      .fgt = FGT_ICIVAU,
-+
+       .accessfn = access_tocu },
-+/*
+     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
-+ * Narrowing right shifts, taking a double sized input, shifting it
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
-+ * and putting the result in either the top or bottom half of the output.
+       .access = PL1_W, .accessfn = aa64_cacheop_poc_access,
-+ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
++      .fgt = FGT_DCIVAC,
-+ */
+       .type = ARM_CP_NOP },
-+#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)       \
+     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
-+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
-+                                void *vm, uint32_t shift)       \
++      .fgt = FGT_DCISW,
-+    {                                                           \
+       .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
-+        LTYPE *m = vm;                                          \
+     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
-+        TYPE *d = vd;                                           \
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
-+        uint16_t mask = mve_element_mask(env);                  \
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-+        unsigned le;                                            \
+       .accessfn = aa64_cacheop_poc_access },
-+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
+     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
-+            TYPE r = FN(m[H##LESIZE(le)], shift);               \
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
-+            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
++      .fgt = FGT_DCCSW,
-+        }                                                       \
+       .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
-+        mve_advance_vpt(env);                                   \
+     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
-+    }
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
-+
+       .access = PL0_W, .type = ARM_CP_NOP,
-+#define DO_VSHRN_ALL(OP, FN)                                    \
++      .fgt = FGT_DCCVAU,
-+    DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN)        \
+       .accessfn = access_tocu },
-+    DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN)       \
+     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
-+    DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN)         \
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
-+    DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
+       .access = PL0_W, .type = ARM_CP_NOP,
-+
++      .fgt = FGT_DCCIVAC,
-+static inline uint64_t do_urshr(uint64_t x, unsigned sh)
+       .accessfn = aa64_cacheop_poc_access },
-+{
+     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
-+    if (likely(sh < 64)) {
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
-+        return (x >> sh) + ((x >> (sh - 1)) & 1);
++      .fgt = FGT_DCCISW,
-+    } else if (sh == 64) {
+       .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
-+        return x >> 63;
+     /* TLBI operations */
-+    } else {
+     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
-+        return 0;
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = {
-+    }
+     { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64,
-+}
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
-+
+       .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
-+DO_VSHRN_ALL(vshrn, DO_SHR)
++      .fgt = FGT_DCCVAP,
-+DO_VSHRN_ALL(vrshrn, do_urshr)
+       .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
+ };
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = {
-+++ b/target/arm/translate-mve.c
+     { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64,
-@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
- DO_VSHLL(VSHLL_BU, vshllbu)
+       .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
- DO_VSHLL(VSHLL_TS, vshllts)
++      .fgt = FGT_DCCVADP,
- DO_VSHLL(VSHLL_TU, vshlltu)
+       .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
-+
+ };
-+#define DO_2SHIFT_N(INSN, FN)                                   \
+ #endif /*CONFIG_USER_ONLY*/
-+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
-+    {                                                           \
+     { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64,
-+        static MVEGenTwoOpShiftFn * const fns[] = {             \
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
-+            gen_helper_mve_##FN##b,                             \
+       .type = ARM_CP_NOP, .access = PL1_W,
-+            gen_helper_mve_##FN##h,                             \
++      .fgt = FGT_DCIVAC,
-+        };                                                      \
+       .accessfn = aa64_cacheop_poc_access },
-+        return do_2shift(s, a, fns[a->size], false);            \
+     { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64,
-+    }
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4,
-+
++      .fgt = FGT_DCISW,
-+DO_2SHIFT_N(VSHRNB, vshrnb)
+       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
-+DO_2SHIFT_N(VSHRNT, vshrnt)
+     { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64,
-+DO_2SHIFT_N(VRSHRNB, vrshrnb)
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5,
-+DO_2SHIFT_N(VRSHRNT, vrshrnt)
+       .type = ARM_CP_NOP, .access = PL1_W,
 +      .fgt = FGT_DCIVAC,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6,
 +      .fgt = FGT_DCISW,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
      { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4,
 +      .fgt = FGT_DCCSW,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
      { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6,
 +      .fgt = FGT_DCCSW,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
      { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4,
 +      .fgt = FGT_DCCISW,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
      { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
 +      .fgt = FGT_DCCISW,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
  };
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
      { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
        .type = ARM_CP_NOP, .access = PL0_W,
 +      .fgt = FGT_DCCVAP,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
        .type = ARM_CP_NOP, .access = PL0_W,
 +      .fgt = FGT_DCCVAP,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
        .type = ARM_CP_NOP, .access = PL0_W,
 +      .fgt = FGT_DCCVADP,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
        .type = ARM_CP_NOP, .access = PL0_W,
 +      .fgt = FGT_DCCVADP,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
        .type = ARM_CP_NOP, .access = PL0_W,
 +      .fgt = FGT_DCCIVAC,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
        .type = ARM_CP_NOP, .access = PL0_W,
 +      .fgt = FGT_DCCIVAC,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_GVA", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
  #ifndef CONFIG_USER_ONLY
        /* Avoid overhead of an access check that always passes in user-mode */
        .accessfn = aa64_zva_access,
 +      .fgt = FGT_DCZVA,
  #endif
      },
      { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
  #ifndef CONFIG_USER_ONLY
        /* Avoid overhead of an access check that always passes in user-mode */
        .accessfn = aa64_zva_access,
 +      .fgt = FGT_DCZVA,
  #endif
      },
  };
 --
-.20.1
+.34.1

-[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
+[PULL 27/33] target/arm: Mark up sysregs for HFGITR bits 12..17
-Implement the MVE VSRI and VSLI insns, which perform a
+Mark up the sysreg definitions for the system instructions
-shift-and-insert operation.
+trapped by HFGITR bits 12..17. These bits cover AT address
 translation instructions.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-18-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-18-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    |  8 ++++++++
+ target/arm/cpregs.h | 6 ++++++
- target/arm/mve.decode      |  9 ++++++++
+ target/arm/helper.c | 6 ++++++
- target/arm/mve_helper.c    | 42 ++++++++++++++++++++++++++++++++++++++
+files changed, 12 insertions(+)
  target/arm/translate-mve.c |  3 +++
 files changed, 62 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/cpregs.h
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
- DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     DO_BIT(HFGITR, DCCVADP),
- DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     DO_BIT(HFGITR, DCCIVAC),
- DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     DO_BIT(HFGITR, DCZVA),
-+
++    DO_BIT(HFGITR, ATS1E1R),
-+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, ATS1E1W),
-+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, ATS1E0R),
-+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, ATS1E0W),
-+
++    DO_BIT(HFGITR, ATS1E1RP),
-+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, ATS1E1WP),
-+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ } FGTBit;
-+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
+ #undef DO_BIT
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
+--- a/target/arm/helper.c
-+++ b/target/arm/mve.decode
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
+     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
- VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
- VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
+       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
-+
++      .fgt = FGT_ATS1E1R,
-+# Shift-and-insert
+       .writefn = ats_write64 },
-+VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
+     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
-+VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
-+VSRI              111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
+       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
-+
++      .fgt = FGT_ATS1E1W,
-+VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
+       .writefn = ats_write64 },
-+VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
+     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
-+VSLI              111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
+       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
-index XXXXXXX..XXXXXXX 100644
++      .fgt = FGT_ATS1E0R,
---- a/target/arm/mve_helper.c
+       .writefn = ats_write64 },
-+++ b/target/arm/mve_helper.c
+     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
-@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
- DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
+       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
- DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
++      .fgt = FGT_ATS1E0W,
+       .writefn = ats_write64 },
-+/* Shift-and-insert; we always work with 64 bits at a time */
+     { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
-+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN)                    \
+       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
-+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
-+                                void *vm, uint32_t shift)               \
+     { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
-+    {                                                                   \
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
-+        uint64_t *d = vd, *m = vm;                                      \
+       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
-+        uint16_t mask;                                                  \
++      .fgt = FGT_ATS1E1RP,
-+        uint64_t shiftmask;                                             \
+       .writefn = ats_write64 },
-+        unsigned e;                                                     \
+     { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
-+        if (shift == 0 || shift == ESIZE * 8) {                         \
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
-+            /*                                                          \
+       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
-+             * Only VSLI can shift by 0; only VSRI can shift by <dt>.   \
++      .fgt = FGT_ATS1E1WP,
-+             * The generic logic would give the right answer for 0 but  \
+       .writefn = ats_write64 },
-+             * fails for <dt>.                                          \
+ };
-+             */                                                         \
 +            goto done;                                                  \
 +        }                                                               \
 +        assert(shift < ESIZE * 8);                                      \
 +        mask = mve_element_mask(env);                                   \
 +        /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */     \
 +        shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift));     \
 +        for (e = 0; e < 16 / 8; e++, mask >>= 8) {                      \
 +            uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) |       \
 +                (d[H8(e)] & ~shiftmask);                                \
 +            mergemask(&d[H8(e)], r, mask);                              \
 +        }                                                               \
 +done:                                                                   \
 +        mve_advance_vpt(env);                                           \
 +    }
 +
 +#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
 +#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
 +#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
 +#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
 +
 +DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
 +DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
 +DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
 +DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
 +DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
 +DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
 +
  /*
   * Long shifts taking half-sized inputs from top or bottom of the input
   * vector and producing a double-width result. ESIZE, TYPE are for
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
  DO_2SHIFT(VRSHRI_S, vrshli_s, true)
  DO_2SHIFT(VRSHRI_U, vrshli_u, true)
 +DO_2SHIFT(VSRI, vsri, false)
 +DO_2SHIFT(VSLI, vsli, false)
 +
  #define DO_VSHLL(INSN, FN)                                      \
      static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
      {                                                           \
 --
-.20.1
+.34.1

-[PULL 15/24] target/arm: Implement MVE VSHLL
+[PULL 28/33] target/arm: Mark up sysregs for HFGITR bits 18..47
-Implement the MVE VHLL (vector shift left long) insn.  This has two
+Mark up the sysreg definitions for the system instructions
-encodings: the T1 encoding is the usual shift-by-immediate format,
+trapped by HFGITR bits 18..47. These bits cover TLBI
-and the T2 encoding is a special case where the shift count is always
+TLB maintenance instructions.
-equal to the element size.
 (If we implemented FEAT_XS we would need to trap some of the
 instructions added by that feature using these bits; but we don't
 yet, so will need to add the .fgt markup when we do.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-19-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-19-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    |  9 +++++++
+ target/arm/cpregs.h | 30 ++++++++++++++++++++++++++++++
- target/arm/mve.decode      | 53 +++++++++++++++++++++++++++++++++++---
+ target/arm/helper.c | 30 ++++++++++++++++++++++++++++++
- target/arm/mve_helper.c    | 32 +++++++++++++++++++++++
+files changed, 60 insertions(+)
  target/arm/translate-mve.c | 15 +++++++++++
 files changed, 105 insertions(+), 4 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/cpregs.h
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
- DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     DO_BIT(HFGITR, ATS1E0W),
- DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     DO_BIT(HFGITR, ATS1E1RP),
- DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+     DO_BIT(HFGITR, ATS1E1WP),
-+
++    DO_BIT(HFGITR, TLBIVMALLE1OS),
-+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, TLBIVAE1OS),
-+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, TLBIASIDE1OS),
-+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, TLBIVAAE1OS),
-+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, TLBIVALE1OS),
-+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, TLBIVAALE1OS),
-+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, TLBIRVAE1OS),
-+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, TLBIRVAAE1OS),
-+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, TLBIRVALE1OS),
-diff --git a/target/arm/mve.decode b/target/arm/mve.decode
++    DO_BIT(HFGITR, TLBIRVAALE1OS),
 +    DO_BIT(HFGITR, TLBIVMALLE1IS),
 +    DO_BIT(HFGITR, TLBIVAE1IS),
 +    DO_BIT(HFGITR, TLBIASIDE1IS),
 +    DO_BIT(HFGITR, TLBIVAAE1IS),
 +    DO_BIT(HFGITR, TLBIVALE1IS),
 +    DO_BIT(HFGITR, TLBIVAALE1IS),
 +    DO_BIT(HFGITR, TLBIRVAE1IS),
 +    DO_BIT(HFGITR, TLBIRVAAE1IS),
 +    DO_BIT(HFGITR, TLBIRVALE1IS),
 +    DO_BIT(HFGITR, TLBIRVAALE1IS),
 +    DO_BIT(HFGITR, TLBIRVAE1),
 +    DO_BIT(HFGITR, TLBIRVAAE1),
 +    DO_BIT(HFGITR, TLBIRVALE1),
 +    DO_BIT(HFGITR, TLBIRVAALE1),
 +    DO_BIT(HFGITR, TLBIVMALLE1),
 +    DO_BIT(HFGITR, TLBIVAE1),
 +    DO_BIT(HFGITR, TLBIASIDE1),
 +    DO_BIT(HFGITR, TLBIVAAE1),
 +    DO_BIT(HFGITR, TLBIVALE1),
 +    DO_BIT(HFGITR, TLBIVAALE1),
  } FGTBit;
  #undef DO_BIT
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
+--- a/target/arm/helper.c
-+++ b/target/arm/mve.decode
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
- @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
- @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
-+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
++      .fgt = FGT_TLBIVMALLE1IS,
-+@2_shll_h .... .... ... 1  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+       .writefn = tlbi_aa64_vmalle1is_write },
-+# VSHLL encoding T2 where shift == esize
+     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
-+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
-+                qd=%qd qm=%qm size=0 shift=8
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
-+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
++      .fgt = FGT_TLBIVAE1IS,
-+                qd=%qd qm=%qm size=1 shift=16
+       .writefn = tlbi_aa64_vae1is_write },
-+
+     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
- # Right shifts are encoded as N - shift, where N is the element size in bits.
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
- %rshift_i5  16:5 !function=rsub_32
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
- %rshift_i4  16:4 !function=rsub_16
++      .fgt = FGT_TLBIASIDE1IS,
-@@ -XXX,XX +XXX,XX @@ VADD             1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
+       .writefn = tlbi_aa64_vmalle1is_write },
- VSUB             1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
+     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
- VMUL             1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
--VMULH_S          111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
++      .fgt = FGT_TLBIVAAE1IS,
--VMULH_U          111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+       .writefn = tlbi_aa64_vae1is_write },
-+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
+     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
-+# overlaps what would be size=0b11 VMULH/VRMULH
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
-+{
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
-+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
++      .fgt = FGT_TLBIVALE1IS,
-+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
+       .writefn = tlbi_aa64_vae1is_write },
+     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
--VRMULH_S         111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
--VRMULH_U         111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
-+  VMULH_S        111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
++      .fgt = FGT_TLBIVAALE1IS,
-+}
+       .writefn = tlbi_aa64_vae1is_write },
-+
+     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
-+{
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
-+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
+       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
-+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
++      .fgt = FGT_TLBIVMALLE1,
-+
+       .writefn = tlbi_aa64_vmalle1_write },
-+  VMULH_U        111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
-+}
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
-+
+       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
-+{
++      .fgt = FGT_TLBIVAE1,
-+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
+       .writefn = tlbi_aa64_vae1_write },
-+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
+     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
-+
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
-+  VRMULH_S       111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
-+}
++      .fgt = FGT_TLBIASIDE1,
-+
+       .writefn = tlbi_aa64_vmalle1_write },
-+{
+     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
-+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
-+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
+       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
-+
++      .fgt = FGT_TLBIVAAE1,
-+  VRMULH_U       111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+       .writefn = tlbi_aa64_vae1_write },
-+}
+     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
- VMAX_S           111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
+       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
- VMAX_U           111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
++      .fgt = FGT_TLBIVALE1,
-@@ -XXX,XX +XXX,XX @@ VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
+       .writefn = tlbi_aa64_vae1_write },
- VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
+     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
- VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
- VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
+       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
-+
++      .fgt = FGT_TLBIVAALE1,
-+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
+       .writefn = tlbi_aa64_vae1_write },
-+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
+     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
-+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
-+
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
-+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
+     { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
-+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
-+
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
-+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
++      .fgt = FGT_TLBIRVAE1IS,
-+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
+       .writefn = tlbi_aa64_rvae1is_write },
-+
+     { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
-+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
-+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
++      .fgt = FGT_TLBIRVAAE1IS,
-index XXXXXXX..XXXXXXX 100644
+       .writefn = tlbi_aa64_rvae1is_write },
---- a/target/arm/mve_helper.c
+    { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
-+++ b/target/arm/mve_helper.c
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
-@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
- DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
++      .fgt = FGT_TLBIRVALE1IS,
- DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
+       .writefn = tlbi_aa64_rvae1is_write },
- DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
+     { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
-+
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
-+/*
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
-+ * Long shifts taking half-sized inputs from top or bottom of the input
++      .fgt = FGT_TLBIRVAALE1IS,
-+ * vector and producing a double-width result. ESIZE, TYPE are for
+       .writefn = tlbi_aa64_rvae1is_write },
-+ * the input, and LESIZE, LTYPE for the output.
+     { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
-+ * Unlike the normal shift helpers, we do not handle negative shift counts,
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
-+ * because the long shift is strictly left-only.
+       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
-+ */
++      .fgt = FGT_TLBIRVAE1OS,
-+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE)                   \
+       .writefn = tlbi_aa64_rvae1is_write },
-+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
+     { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
-+                                void *vm, uint32_t shift)               \
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
-+    {                                                                   \
+       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
-+        LTYPE *d = vd;                                                  \
++      .fgt = FGT_TLBIRVAAE1OS,
-+        TYPE *m = vm;                                                   \
+       .writefn = tlbi_aa64_rvae1is_write },
-+        uint16_t mask = mve_element_mask(env);                          \
+    { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
-+        unsigned le;                                                    \
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
-+        assert(shift <= 16);                                            \
+       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
-+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) {         \
++      .fgt = FGT_TLBIRVALE1OS,
-+            LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift;        \
+       .writefn = tlbi_aa64_rvae1is_write },
-+            mergemask(&d[H##LESIZE(le)], r, mask);                      \
+     { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
-+        }                                                               \
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
-+        mve_advance_vpt(env);                                           \
+       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
-+    }
++      .fgt = FGT_TLBIRVAALE1OS,
-+
+       .writefn = tlbi_aa64_rvae1is_write },
-+#define DO_VSHLL_ALL(OP, TOP)                                \
+     { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
-+    DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t)             \
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
-+    DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t)           \
+       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
-+    DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t)            \
++      .fgt = FGT_TLBIRVAE1,
-+    DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t)          \
+       .writefn = tlbi_aa64_rvae1_write },
-+
+     { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64,
-+DO_VSHLL_ALL(vshllb, false)
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
-+DO_VSHLL_ALL(vshllt, true)
+       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
++      .fgt = FGT_TLBIRVAAE1,
-index XXXXXXX..XXXXXXX 100644
+       .writefn = tlbi_aa64_rvae1_write },
---- a/target/arm/translate-mve.c
+    { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64,
-+++ b/target/arm/translate-mve.c
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5,
-@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
+       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
- DO_2SHIFT(VSHRI_U, vshli_u, true)
++      .fgt = FGT_TLBIRVALE1,
- DO_2SHIFT(VRSHRI_S, vrshli_s, true)
+       .writefn = tlbi_aa64_rvae1_write },
- DO_2SHIFT(VRSHRI_U, vrshli_u, true)
+     { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64,
-+
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7,
-+#define DO_VSHLL(INSN, FN)                                      \
+       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
-+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
++      .fgt = FGT_TLBIRVAALE1,
-+    {                                                           \
+       .writefn = tlbi_aa64_rvae1_write },
-+        static MVEGenTwoOpShiftFn * const fns[] = {             \
+     { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
-+            gen_helper_mve_##FN##b,                             \
+       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
-+            gen_helper_mve_##FN##h,                             \
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
-+        };                                                      \
+     { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
-+        return do_2shift(s, a, fns[a->size], false);            \
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
-+    }
+       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
-+
++      .fgt = FGT_TLBIVMALLE1OS,
-+DO_VSHLL(VSHLL_BS, vshllbs)
+       .writefn = tlbi_aa64_vmalle1is_write },
-+DO_VSHLL(VSHLL_BU, vshllbu)
+     { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
-+DO_VSHLL(VSHLL_TS, vshllts)
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
-+DO_VSHLL(VSHLL_TU, vshlltu)
++      .fgt = FGT_TLBIVAE1OS,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIASIDE1OS,
        .writefn = tlbi_aa64_vmalle1is_write },
      { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIVAAE1OS,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIVALE1OS,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIVAALE1OS,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
 --
-.20.1
+.34.1

-[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
+[PULL 29/33] target/arm: Mark up sysregs for HFGITR bits 48..63
-Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
+Mark up the sysreg definitions for the system instructions
-and VQSHLU.
+trapped by HFGITR bits 48..63.
-The size-and-immediate encoding here is the same as Neon, and we
+Some of these bits are for trapping instructions which are
-handle it the same way neon-dp.decode does.
+not in the system instruction encoding (i.e. which are
 not handled by the ARMCPRegInfo mechanism):
  * ERET, ERETAA, ERETAB
  * SVC
 We will have to handle those separately and manually.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-20-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-20-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    | 16 +++++++++++
+ target/arm/cpregs.h | 4 ++++
- target/arm/mve.decode      | 23 +++++++++++++++
+ target/arm/helper.c | 9 +++++++++
- target/arm/mve_helper.c    | 57 ++++++++++++++++++++++++++++++++++++++
+files changed, 13 insertions(+)
  target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
 files changed, 147 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/cpregs.h
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
- DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
+     DO_BIT(HFGITR, TLBIVAAE1),
- DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
+     DO_BIT(HFGITR, TLBIVALE1),
- DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
+     DO_BIT(HFGITR, TLBIVAALE1),
-+
++    DO_BIT(HFGITR, CFPRCTX),
-+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, DVPRCTX),
-+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, CPPRCTX),
-+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
++    DO_BIT(HFGITR, DCCVAC),
-+
+ } FGTBit;
-+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ #undef DO_BIT
-+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 +
 +DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +
 +DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 +DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/mve.decode
+--- a/target/arm/helper.c
-+++ b/target/arm/mve.decode
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
- &2op qd qm qn size
+     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
- &2scalar qd qn rm size
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
- &1imm qd imm cmode op
+       .access = PL0_W, .type = ARM_CP_NOP,
-+&2shift qd qm shift size
++      .fgt = FGT_DCCVAC,
+       .accessfn = aa64_cacheop_poc_access },
- @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
+     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
- # Note that both Rn and Qd are 3 bits only (no D bit)
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
- @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
+     { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64,
- @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
+       .type = ARM_CP_NOP, .access = PL0_W,
-+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
++      .fgt = FGT_DCCVAC,
-+@2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+       .accessfn = aa64_cacheop_poc_access },
-+@2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
+     { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64,
-+
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
- # Vector loads and stores
+       .type = ARM_CP_NOP, .access = PL0_W,
++      .fgt = FGT_DCCVAC,
- # Widening loads and narrowing stores:
+       .accessfn = aa64_cacheop_poc_access },
-@@ -XXX,XX +XXX,XX @@ VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
+     { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
- # So we have a single decode line and check the cmode/op in the
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
- # trans function.
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
- Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
+ static const ARMCPRegInfo predinv_reginfo[] = {
-+
+     { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64,
-+# Shifts by immediate
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,
-+
++      .fgt = FGT_CFPRCTX,
-+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
+       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
-+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
+     { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64,
-+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,
-+
++      .fgt = FGT_DVPRCTX,
-+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
+       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
-+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
+     { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64,
-+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,
-+
++      .fgt = FGT_CPPRCTX,
-+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
+       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
-+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
+     /*
-+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
+      * Note the AArch32 opcodes have a different OPC1.
-+
+      */
-+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
+     { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32,
-+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
+       .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,
-+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
++      .fgt = FGT_CFPRCTX,
-diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
+       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
-index XXXXXXX..XXXXXXX 100644
+     { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32,
---- a/target/arm/mve_helper.c
+       .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,
-+++ b/target/arm/mve_helper.c
++      .fgt = FGT_DVPRCTX,
-@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
+       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
-     WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
+     { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
- #define DO_UQRSHL_OP(N, M, satp) \
+       .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
-     WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
++      .fgt = FGT_CPPRCTX,
-+#define DO_SUQSHL_OP(N, M, satp) \
+       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
-+    WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
+ };
  DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
  DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
  DO_VADDV(vaddvub, 1, uint8_t)
  DO_VADDV(vaddvuh, 2, uint16_t)
  DO_VADDV(vaddvuw, 4, uint32_t)
 +
 +/* Shifts by immediate */
 +#define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 +                                void *vm, uint32_t shift)       \
 +    {                                                           \
 +        TYPE *d = vd, *m = vm;                                  \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned e;                                             \
 +        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
 +            mergemask(&d[H##ESIZE(e)],                          \
 +                      FN(m[H##ESIZE(e)], shift), mask);         \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +    }
 +
 +#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN)                      \
 +    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
 +                                void *vm, uint32_t shift)       \
 +    {                                                           \
 +        TYPE *d = vd, *m = vm;                                  \
 +        uint16_t mask = mve_element_mask(env);                  \
 +        unsigned e;                                             \
 +        bool qc = false;                                        \
 +        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
 +            bool sat = false;                                   \
 +            mergemask(&d[H##ESIZE(e)],                          \
 +                      FN(m[H##ESIZE(e)], shift, &sat), mask);   \
 +            qc |= sat & mask & 1;                               \
 +        }                                                       \
 +        if (qc) {                                               \
 +            env->vfp.qc[0] = qc;                                \
 +        }                                                       \
 +        mve_advance_vpt(env);                                   \
 +    }
 +
 +/* provide unsigned 2-op shift helpers for all sizes */
 +#define DO_2SHIFT_U(OP, FN)                     \
 +    DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
 +    DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
 +    DO_2SHIFT(OP##w, 4, uint32_t, FN)
 +
 +#define DO_2SHIFT_SAT_U(OP, FN)                 \
 +    DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
 +    DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN)       \
 +    DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
 +#define DO_2SHIFT_SAT_S(OP, FN)                 \
 +    DO_2SHIFT_SAT(OP##b, 1, int8_t, FN)         \
 +    DO_2SHIFT_SAT(OP##h, 2, int16_t, FN)        \
 +    DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
 +
 +DO_2SHIFT_U(vshli_u, DO_VSHLU)
 +DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
 +DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
 +DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
 +typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
  typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
      }
      return do_1imm(s, a, fn);
  }
 +
 +static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
 +                      bool negateshift)
 +{
 +    TCGv_ptr qd, qm;
 +    int shift = a->shift;
 +
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !mve_check_qreg_bank(s, a->qd | a->qm) ||
 +        !fn) {
 +        return false;
 +    }
 +    if (!mve_eci_check(s) || !vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    /*
 +     * When we handle a right shift insn using a left-shift helper
 +     * which permits a negative shift count to indicate a right-shift,
 +     * we must negate the shift count.
 +     */
 +    if (negateshift) {
 +        shift = -shift;
 +    }
 +
 +    qd = mve_qreg_ptr(a->qd);
 +    qm = mve_qreg_ptr(a->qm);
 +    fn(cpu_env, qd, qm, tcg_constant_i32(shift));
 +    tcg_temp_free_ptr(qd);
 +    tcg_temp_free_ptr(qm);
 +    mve_update_eci(s);
 +    return true;
 +}
 +
 +#define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
 +    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
 +    {                                                           \
 +        static MVEGenTwoOpShiftFn * const fns[] = {             \
 +            gen_helper_mve_##FN##b,                             \
 +            gen_helper_mve_##FN##h,                             \
 +            gen_helper_mve_##FN##w,                             \
 +            NULL,                                               \
 +        };                                                      \
 +        return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
 +    }
 +
 +DO_2SHIFT(VSHLI, vshli_u, false)
 +DO_2SHIFT(VQSHLI_S, vqshli_s, false)
 +DO_2SHIFT(VQSHLI_U, vqshli_u, false)
 +DO_2SHIFT(VQSHLUI, vqshlui_s, false)
 --
-.20.1
+.34.1

-[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
+[PULL 30/33] target/arm: Implement the HFGITR_EL2.ERET trap
-Use dup_const() instead of bitfield_replicate() in
+Implement the HFGITR_EL2.ERET fine-grained trap.  This traps
-disas_simd_mod_imm().
+execution from AArch64 EL1 of ERET, ERETAA and ERETAB.  The trap is
 reported with a syndrome value of 0x1a.
-(We can't replace the other use of bitfield_replicate() in this file,
+The trap must take precedence over a possible pointer-authentication
-in logic_imm_decode_wmask(), because that location needs to handle 2
+trap for ERETAA and ERETAB.
 and 4 bit elements, which dup_const() cannot.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-21-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-21-peter.maydell@linaro.org
 ---
- target/arm/translate-a64.c | 2 +-
+ target/arm/cpu.h           |  1 +
-file changed, 1 insertion(+), 1 deletion(-)
+ target/arm/syndrome.h      | 10 ++++++++++
  target/arm/translate.h     |  2 ++
  target/arm/helper.c        |  3 +++
  target/arm/translate-a64.c | 10 ++++++++++
 files changed, 26 insertions(+)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
+ FIELD(TBFLAG_A64, SVL, 24, 4)
+ /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
+ FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
++FIELD(TBFLAG_A64, FGT_ERET, 29, 1)
+ /*
+  * Helpers for using the above.
+diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/syndrome.h
++++ b/target/arm/syndrome.h
+@@ -XXX,XX +XXX,XX @@ enum arm_exception_class {
+     EC_AA64_SMC               = 0x17,
+     EC_SYSTEMREGISTERTRAP     = 0x18,
+     EC_SVEACCESSTRAP          = 0x19,
++    EC_ERETTRAP               = 0x1a,
+     EC_SMETRAP                = 0x1d,
+     EC_INSNABORT              = 0x20,
+     EC_INSNABORT_SAME_EL      = 0x21,
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_sve_access_trap(void)
+     return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT;
+ }
++/*
++ * eret_op is bits [1:0] of the ERET instruction, so:
++ * 0 for ERET, 2 for ERETAA, 3 for ERETAB.
++ */
++static inline uint32_t syn_erettrap(int eret_op)
++{
++    return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op;
++}
++
+ static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit)
+ {
+     return (EC_SMETRAP << ARM_EL_EC_SHIFT)
+diff --git a/target/arm/translate.h b/target/arm/translate.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.h
++++ b/target/arm/translate.h
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+     bool mve_no_pred;
+     /* True if fine-grained traps are active */
+     bool fgt_active;
++    /* True if fine-grained trap on ERET is enabled */
++    bool fgt_eret;
+     /*
+      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
+      *  < 0, set by the current instruction.
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
+     if (arm_fgt_active(env, el)) {
+         DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
++        if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
++            DP_TBFLAG_A64(flags, FGT_ERET, 1);
++        }
+     }
+     if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
-         /* FMOV (vector, immediate) - half-precision */
+             if (op4 != 0) {
-         imm = vfp_expand_imm(MO_16, abcdefgh);
+                 goto do_unallocated;
-         /* now duplicate across the lanes */
+             }
--        imm = bitfield_replicate(imm, 16);
++            if (s->fgt_eret) {
-+        imm = dup_const(MO_16, imm);
++                gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2);
-     } else {
++                return;
-         imm = asimd_imm_const(abcdefgh, cmode, is_neg);
++            }
-     }
+             dst = tcg_temp_new_i64();
              tcg_gen_ld_i64(dst, cpu_env,
                             offsetof(CPUARMState, elr_el[s->current_el]));
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
              if (rn != 0x1f || op4 != 0x1f) {
                  goto do_unallocated;
              }
 +            /* The FGT trap takes precedence over an auth trap. */
 +            if (s->fgt_eret) {
 +                gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2);
 +                return;
 +            }
              dst = tcg_temp_new_i64();
              tcg_gen_ld_i64(dst, cpu_env,
                             offsetof(CPUARMState, elr_el[s->current_el]));
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
      dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
      dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
      dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
 +    dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET);
      dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
      dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
      dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;
 --
-.20.1
+.34.1

-[PULL 21/24] target/arm: Implement MVE long shifts by immediate
+[PULL 31/33] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
-The MVE extension to v8.1M includes some new shift instructions which
+Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps.
-sit entirely within the non-coprocessor part of the encoding space
+These trap execution of the SVC instruction from AArch32 and AArch64.
-and which operate only on general-purpose registers.  They take up
+(As usual, AArch32 can only trap from EL0, as fine grained traps are
-the space which was previously UNPREDICTABLE MOVS and ORRS encodings
+disabled with an AArch32 EL1.)
 with Rm == 13 or 15.
 Implement the long shifts by immediate, which perform shifts on a
 pair of general-purpose registers treated as a 64-bit quantity, with
 an immediate shift count between 1 and 32.
 Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
 the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
 cases where v8.1M now requires that.  (Trying to change MOVS and ORRS
 is too difficult, because the functions that generate the code are
 shared between a dozen different kinds of arithmetic or logical
 instruction for all A32, T16 and T32 encodings, and for some insns
 and some encodings Rm==13,15 are valid.)
 We make the helper functions we need for UQSHLL and SQSHLL take
 a 32-bit value which the helper casts to int8_t because we'll need
 these helpers also for the shift-by-register insns, where the shift
 count might be < 0 or > 32.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-22-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-22-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h |  3 ++
+ target/arm/cpu.h           |  1 +
- target/arm/translate.h  |  1 +
+ target/arm/translate.h     |  2 ++
- target/arm/t32.decode   | 28 +++++++++++++
+ target/arm/helper.c        | 20 ++++++++++++++++++++
- target/arm/mve_helper.c | 10 +++++
+ target/arm/translate-a64.c |  9 ++++++++-
- target/arm/translate.c  | 90 +++++++++++++++++++++++++++++++++++++++++
+ target/arm/translate.c     | 12 +++++++++---
-files changed, 132 insertions(+)
+files changed, 40 insertions(+), 4 deletions(-)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/cpu.h
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
- DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+ FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
+ FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
- DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
+ FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
-+
++FIELD(TBFLAG_ANY, FGT_SVC, 13, 1)
-+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
-+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+ /*
   * Bit usage when in AArch32 state, both A- and M-profile.
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
- typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
+     bool fgt_active;
- typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
+     /* True if fine-grained trap on ERET is enabled */
- typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
+     bool fgt_eret;
-+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
++    /* True if fine-grained trap on SVC is enabled */
++    bool fgt_svc;
- /**
+     /*
-  * arm_tbflags_from_tb:
+      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
-diff --git a/target/arm/t32.decode b/target/arm/t32.decode
+      *  < 0, set by the current instruction.
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/t32.decode
+--- a/target/arm/helper.c
-+++ b/target/arm/t32.decode
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
- &mcr             !extern cp opc1 crn crm opc2 rt
+     return arm_mmu_idx_el(env, arm_current_el(env));
  &mcrr            !extern cp opc1 crm rt rt2
 +&mve_shl_ri      rdalo rdahi shim
 +
 +# rdahi: bits [3:1] from insn, bit 0 is 1
 +# rdalo: bits [3:1] from insn, bit 0 is 0
 +%rdahi_9 9:3 !function=times_2_plus_1
 +%rdalo_17 17:3 !function=times_2
 +
  # Data-processing (register)
  %imm5_12_6       12:3 6:2
@@ -XXX,XX +XXX,XX @@
  @S_xrr_shi       ....... .... .   rn:4 .... .... .. shty:2 rm:4 \
                   &s_rrr_shi shim=%imm5_12_6 s=1 rd=0
 +@mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
 +                 &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
 +
  {
    TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
    AND_rrri       1110101 0000 . .... 0 ... .... .... ....     @s_rrr_shi
  }
- BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
- {
++static inline bool fgt_svc(CPUARMState *env, int el)
 +  # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
 +  # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
 +  # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
 +  # they explicitly call unallocated_encoding() for cases that must UNDEF
 +  # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
 +  # the rest fall through (where ORR_rrri and MOV_rxri will end up
 +  # handling them as r13 and r15 accesses with the same semantics as A32).
 +  [
 +    LSLL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +    LSRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +    ASRL_ri      1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +
 +    UQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111  @mve_shl_ri
 +    URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
 +    SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
 +    SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
 +  ]
 +
    MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
    ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
  }
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
      mve_advance_vpt(env);
      return rdm;
  }
 +
 +uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 +{
-+    return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
++    /*
 +     * Assuming fine-grained-traps are active, return true if we
 +     * should be trapping on SVC instructions. Only AArch64 can
 +     * trap on an SVC at EL1, but we don't need to special-case this
 +     * because if this is AArch32 EL1 then arm_fgt_active() is false.
 +     * We also know el is 0 or 1.
 +     */
 +    return el == 0 ?
 +        FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
 +        FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
 +}
 +
-+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
+ static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
-+{
+                                            ARMMMUIdx mmu_idx,
-+    return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
+                                            CPUARMTBFlags flags)
-+}
+@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
      if (arm_fgt_active(env, el)) {
          DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
 +        if (fgt_svc(env, el)) {
 +            DP_TBFLAG_ANY(flags, FGT_SVC, 1);
 +        }
      }
      if (env->uncached_cpsr & CPSR_IL) {
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
          if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
              DP_TBFLAG_A64(flags, FGT_ERET, 1);
          }
 +        if (fgt_svc(env, el)) {
 +            DP_TBFLAG_ANY(flags, FGT_SVC, 1);
 +        }
      }
      if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
      int opc = extract32(insn, 21, 3);
      int op2_ll = extract32(insn, 0, 5);
      int imm16 = extract32(insn, 5, 16);
 +    uint32_t syndrome;
      switch (opc) {
      case 0:
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
           */
          switch (op2_ll) {
          case 1:                                                     /* SVC */
 +            syndrome = syn_aa64_svc(imm16);
 +            if (s->fgt_svc) {
 +                gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
 +                break;
 +            }
              gen_ss_advance(s);
 -            gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16));
 +            gen_exception_insn(s, 4, EXCP_SWI, syndrome);
              break;
          case 2:                                                     /* HVC */
              if (s->current_el == 0) {
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
      dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
      dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
      dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
 +    dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC);
      dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET);
      dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
      dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
+@@ -XXX,XX +XXX,XX @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
          (a->imm == semihost_imm)) {
          gen_exception_internal_insn(s, EXCP_SEMIHOST);
      } else {
 -        gen_update_pc(s, curr_insn_len(s));
 -        s->svc_imm = a->imm;
 -        s->base.is_jmp = DISAS_SWI;
 +        if (s->fgt_svc) {
 +            uint32_t syndrome = syn_aa32_svc(a->imm, s->thumb);
 +            gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
 +        } else {
 +            gen_update_pc(s, curr_insn_len(s));
 +            s->svc_imm = a->imm;
 +            s->base.is_jmp = DISAS_SWI;
 +        }
      }
      return true;
  }
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-+/*
+     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
-+ * v8.1M MVE wide-shifts
+     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
-+ */
+     dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
-+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
++    dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC);
-+                          WideShiftImmFn *fn)
-+{
+     if (arm_feature(env, ARM_FEATURE_M)) {
-+    TCGv_i64 rda;
+         dc->vfp_enabled = 1;
 +    TCGv_i32 rdalo, rdahi;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 +        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
 +        return false;
 +    }
 +    if (a->rdahi == 15) {
 +        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
 +        return false;
 +    }
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
 +        a->rdahi == 13) {
 +        /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
 +    if (a->shim == 0) {
 +        a->shim = 32;
 +    }
 +
 +    rda = tcg_temp_new_i64();
 +    rdalo = load_reg(s, a->rdalo);
 +    rdahi = load_reg(s, a->rdahi);
 +    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
 +
 +    fn(rda, rda, a->shim);
 +
 +    tcg_gen_extrl_i64_i32(rdalo, rda);
 +    tcg_gen_extrh_i64_i32(rdahi, rda);
 +    store_reg(s, a->rdalo, rdalo);
 +    store_reg(s, a->rdahi, rdahi);
 +    tcg_temp_free_i64(rda);
 +
 +    return true;
 +}
 +
 +static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
 +}
 +
 +static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
 +}
 +
 +static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
 +}
 +
 +static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
 +{
 +    gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_mve_sqshll);
 +}
 +
 +static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
 +{
 +    gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
 +}
 +
 +static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_mve_uqshll);
 +}
 +
 +static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_srshr64_i64);
 +}
 +
 +static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
 +{
 +    return do_mve_shl_ri(s, a, gen_urshr64_i64);
 +}
 +
  /*
   * Multiply and multiply accumulate
   */
 --
-.20.1
+.34.1

-[PULL 12/24] target/arm: Implement MVE logical immediate insns
+[PULL 32/33] target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
-Implement the MVE logical-immediate insns (VMOV, VMVN,
+FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and
-VORR and VBIC). These have essentially the same encoding
+MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug
-as their Neon equivalents, and we implement the decode
+Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0,
-in the same way.
+MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their
 AArch32 equivalents).  This trapping is independent of whether
 fine-grained traps are enabled or not.
 Implement these extra traps.  (We don't implement DBGDTR_EL0,
 DBGDTRRX_EL0 and DBGDTRTX_EL0.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-23-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-23-peter.maydell@linaro.org
 ---
- target/arm/helper-mve.h    |  4 +++
+ target/arm/debug_helper.c | 35 +++++++++++++++++++++++++++++++----
- target/arm/mve.decode      | 17 +++++++++++++
+file changed, 31 insertions(+), 4 deletions(-)
  target/arm/mve_helper.c    | 24 ++++++++++++++++++
  target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
 files changed, 95 insertions(+)
-diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
+diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-mve.h
+--- a/target/arm/debug_helper.c
-+++ b/target/arm/helper-mve.h
++++ b/target/arm/debug_helper.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
- DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
+     return CP_ACCESS_OK;
- DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
+ }
- DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
 +/*
 + * Check for traps to Debug Comms Channel registers. If FEAT_FGT
 + * is implemented then these are controlled by MDCR_EL2.TDCC for
 + * EL2 and MDCR_EL3.TDCC for EL3. They are also controlled by
 + * the general debug access trap bits MDCR_EL2.TDA and MDCR_EL3.TDA.
 + */
 +static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri,
 +                                  bool isread)
 +{
 +    int el = arm_current_el(env);
 +    uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
 +    bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) ||
 +        (arm_hcr_el2_eff(env) & HCR_TGE);
 +    bool mdcr_el2_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
 +                                          (mdcr_el2 & MDCR_TDCC);
 +    bool mdcr_el3_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
 +                                          (env->cp15.mdcr_el3 & MDCR_TDCC);
 +
-+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
++    if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) {
-+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
++        return CP_ACCESS_TRAP_EL2;
 +DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
 diff --git a/target/arm/mve.decode b/target/arm/mve.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve.decode
 +++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
  # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
  %size_28 28:1 !function=plus_1
 +# 1imm format immediate
 +%imm_28_16_0 28:1 16:3 0:4
 +
  &vldr_vstr rn qd imm p a w size l u
  &1op qd qm size
  &2op qd qm qn size
  &2scalar qd qn rm size
 +&1imm qd imm cmode op
  @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
  # Note that both Rn and Qd are 3 bits only (no D bit)
@@ -XXX,XX +XXX,XX @@
  @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
  @2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
       size=%size_28
 +@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
  # The _rev suffix indicates that Vn and Vm are reversed. This is
  # the case for shifts. In the Arm ARM these insns are documented
@@ -XXX,XX +XXX,XX @@ VADDV            111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
  # Predicate operations
  %mask_22_13      22:1 13:3
  VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
 +
 +# Logical immediate operations (1 reg and modified-immediate)
 +
 +# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
 +# not in a way we can conveniently represent in decodetree without
 +# a lot of repetition:
 +# VORR: op=0, (cmode & 1) && cmode < 12
 +# VBIC: op=1, (cmode & 1) && cmode < 12
 +# VMOV: everything else
 +# So we have a single decode line and check the cmode/op in the
 +# trans function.
 +Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/mve_helper.c
 +++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
  DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
  DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
 +/*
 + * 1 operand immediates: Vda is destination and possibly also one source.
 + * All these insns work at 64-bit widths.
 + */
 +#define DO_1OP_IMM(OP, FN)                                              \
 +    void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm)    \
 +    {                                                                   \
 +        uint64_t *da = vda;                                             \
 +        uint16_t mask = mve_element_mask(env);                          \
 +        unsigned e;                                                     \
 +        for (e = 0; e < 16 / 8; e++, mask >>= 8) {                      \
 +            mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask);            \
 +        }                                                               \
 +        mve_advance_vpt(env);                                           \
 +    }
-+
++    if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) {
-+#define DO_MOVI(N, I) (I)
++        return CP_ACCESS_TRAP_EL3;
 +#define DO_ANDI(N, I) ((N) & (I))
 +#define DO_ORRI(N, I) ((N) | (I))
 +
 +DO_1OP_IMM(vmovi, DO_MOVI)
 +DO_1OP_IMM(vandi, DO_ANDI)
 +DO_1OP_IMM(vorri, DO_ORRI)
 +
  #define DO_2OP(OP, ESIZE, TYPE, FN)                                     \
      void HELPER(glue(mve_, OP))(CPUARMState *env,                       \
                                  void *vd, void *vn, void *vm)           \
 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-mve.c
 +++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
  typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
  typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
  typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
 +typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
  /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
  static inline long mve_qreg_offset(unsigned reg)
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
      mve_update_eci(s);
      return true;
  }
 +
 +static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
 +{
 +    TCGv_ptr qd;
 +    uint64_t imm;
 +
 +    if (!dc_isar_feature(aa32_mve, s) ||
 +        !mve_check_qreg_bank(s, a->qd) ||
 +        !fn) {
 +        return false;
 +    }
-+    if (!mve_eci_check(s) || !vfp_access_check(s)) {
++    return CP_ACCESS_OK;
 +        return true;
 +    }
 +
 +    imm = asimd_imm_const(a->imm, a->cmode, a->op);
 +
 +    qd = mve_qreg_ptr(a->qd);
 +    fn(cpu_env, qd, tcg_constant_i64(imm));
 +    tcg_temp_free_ptr(qd);
 +    mve_update_eci(s);
 +    return true;
 +}
 +
-+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
+ static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
-+{
+                         uint64_t value)
-+    /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
+ {
-+    MVEGenOneOpImmFn *fn;
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
-+
+      */
-+    if ((a->cmode & 1) && a->cmode < 12) {
+     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
-+        if (a->op) {
+       .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
-+            /*
+-      .access = PL0_R, .accessfn = access_tda,
-+             * For op=1, the immediate will be inverted by asimd_imm_const(),
++      .access = PL0_R, .accessfn = access_tdcc,
-+             * so the VBIC becomes a logical AND operation.
+       .type = ARM_CP_CONST, .resetvalue = 0 },
-+             */
+     /*
-+            fn = gen_helper_mve_vandi;
+      * OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_EL0.
-+        } else {
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
-+            fn = gen_helper_mve_vorri;
+      */
-+        }
+     { .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
-+    } else {
+       .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
-+        /* There is one unallocated cmode/op combination in this space */
+-      .access = PL1_RW, .accessfn = access_tda,
-+        if (a->cmode == 15 && a->op == 1) {
++      .access = PL1_RW, .accessfn = access_tdcc,
-+            return false;
+       .type = ARM_CP_CONST, .resetvalue = 0 },
-+        }
+     { .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
-+        /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
+       .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
-+        fn = gen_helper_mve_vmovi;
+-      .access = PL1_RW, .accessfn = access_tda,
-+    }
++      .access = PL1_RW, .accessfn = access_tdcc,
-+    return do_1imm(s, a, fn);
+       .type = ARM_CP_CONST, .resetvalue = 0 },
-+}
+     /*
       * OSECCR_EL1 provides a mechanism for an operating system
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
       */
      { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
        .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
 -      .access = PL1_RW, .accessfn = access_tda,
 +      .access = PL1_RW, .accessfn = access_tdcc,
        .type = ARM_CP_NOP },
      /*
       * Dummy DBGCLAIM registers.
 --
-.20.1
+.34.1

-[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
+[PULL 33/33] target/arm: Enable FEAT_FGT on '-cpu max'
-In do_ldst(), the calculation of the offset needs to be based on the
+Update the ID registers for TCG's '-cpu max' to report the
-size of the memory access, not the size of the elements in the
+presence of FEAT_FGT Fine-Grained Traps support.
 vector.  This meant we were getting it wrong for the widening and
 narrowing variants of the various VLDR and VSTR insns.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-24-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-24-peter.maydell@linaro.org
 ---
- target/arm/translate-mve.c | 17 +++++++++--------
+ docs/system/arm/emulation.rst | 1 +
-file changed, 9 insertions(+), 8 deletions(-)
+ target/arm/cpu64.c            | 1 +
 files changed, 2 insertions(+)
-diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-mve.c
+--- a/docs/system/arm/emulation.rst
-+++ b/target/arm/translate-mve.c
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
-     }
+ - FEAT_ETS (Enhanced Translation Synchronization)
- }
+ - FEAT_EVT (Enhanced Virtualization Traps)
+ - FEAT_FCMA (Floating-point complex number instructions)
--static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
++- FEAT_FGT (Fine-Grained Traps)
-+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
+ - FEAT_FHM (Floating-point half-precision multiplication instructions)
-+                    unsigned msize)
+ - FEAT_FP16 (Half-precision floating-point data processing)
- {
+ - FEAT_FRINTTS (Floating-point to integer instructions)
-     TCGv_i32 addr;
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-     uint32_t offset;
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
+--- a/target/arm/cpu64.c
-         return true;
++++ b/target/arm/cpu64.c
-     }
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
--    offset = a->imm << a->size;
+     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
-+    offset = a->imm << msize;
+     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2);  /*  4k stage2 supported */
-     if (!a->a) {
++    t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1);       /* FEAT_FGT */
-         offset = -offset;
+     cpu->isar.id_aa64mmfr0 = t;
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
+     t = cpu->isar.id_aa64mmfr1;
          { gen_helper_mve_vstrw, gen_helper_mve_vldrw },
          { NULL, NULL }
      };
 -    return do_ldst(s, a, ldstfns[a->size][a->l]);
 +    return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
  }
 -#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST)                  \
 +#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE)           \
      static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
      {                                                           \
          static MVEGenLdStFn * const ldstfns[2][2] = {           \
              { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
              { NULL, gen_helper_mve_##ULD },                     \
          };                                                      \
 -        return do_ldst(s, a, ldstfns[a->u][a->l]);              \
 +        return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE);       \
      }
 -DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
 -DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
 -DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
 +DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
 +DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
 +DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
  static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
  {
 --
-.20.1
+.34.1

The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:

Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702

for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:

target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)

----------------------------------------------------------------
target-arm queue:
 * more MVE instructions
 * hw/gpio/gpio_pwr: use shutdown function for reboot
 * target/arm: Check NaN mode before silencing NaN
 * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
 * hw/arm: Add basic power management to raspi.
 * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc

----------------------------------------------------------------
Joe Komlodi (1):
      target/arm: Check NaN mode before silencing NaN

Maxim Uvarov (1):
      hw/gpio/gpio_pwr: use shutdown function for reboot

Nolan Leake (1):
      hw/arm: Add basic power management to raspi.

Patrick Venture (2):
      docs/system/arm: Add quanta-q7l1-bmc reference
      docs/system/arm: Add quanta-gbs-bmc reference

Peter Maydell (18):
      target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
      target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
      target/arm: Make asimd_imm_const() public
      target/arm: Use asimd_imm_const for A64 decode
      target/arm: Use dup_const() instead of bitfield_replicate()
      target/arm: Implement MVE logical immediate insns
      target/arm: Implement MVE vector shift left by immediate insns
      target/arm: Implement MVE vector shift right by immediate insns
      target/arm: Implement MVE VSHLL
      target/arm: Implement MVE VSRI, VSLI
      target/arm: Implement MVE VSHRN, VRSHRN
      target/arm: Implement MVE saturating narrowing shifts
      target/arm: Implement MVE VSHLC
      target/arm: Implement MVE VADDLV
      target/arm: Implement MVE long shifts by immediate
      target/arm: Implement MVE long shifts by register
      target/arm: Implement MVE shifts by immediate
      target/arm: Implement MVE shifts by register

Philippe Mathieu-Daudé (1):
      tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine

docs/system/arm/aspeed.rst             |   1 +
 docs/system/arm/nuvoton.rst            |   5 +-
 include/hw/arm/bcm2835_peripherals.h   |   3 +-
 include/hw/misc/bcm2835_powermgt.h     |  29 ++
 target/arm/helper-mve.h                | 108 +++++++
 target/arm/translate.h                 |  41 +++
 target/arm/mve.decode                  | 177 ++++++++++-
 target/arm/t32.decode                  |  71 ++++-
 hw/arm/bcm2835_peripherals.c           |  13 +-
 hw/gpio/gpio_pwr.c                     |   2 +-
 hw/misc/bcm2835_powermgt.c             | 160 ++++++++++
 target/arm/helper-a64.c                |  12 +-
 target/arm/mve_helper.c                | 524 +++++++++++++++++++++++++++++++--
 target/arm/translate-a64.c             |  86 +-----
 target/arm/translate-mve.c             | 261 +++++++++++++++-
 target/arm/translate-neon.c            |  81 -----
 target/arm/translate.c                 | 327 +++++++++++++++++++-
 target/arm/vfp_helper.c                |  24 +-
 hw/misc/meson.build                    |   1 +
 tests/acceptance/boot_linux_console.py |  43 +++
 20 files changed, 1760 insertions(+), 209 deletions(-)
 create mode 100644 include/hw/misc/bcm2835_powermgt.h
 create mode 100644 hw/misc/bcm2835_powermgt.c

From: Patrick Venture <venture@google.com>

Add line item reference to quanta-gbs-bmc machine.

Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20210615192848.1065297-3-venture@google.com
[PMM: fixed underline Sphinx warning]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
-=====================================================
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
+================================================================
 
 The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
 designed to be used as Baseboard Management Controllers (BMCs) in various
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
 Hyperscale applications. The following machines are based on this chip :
 
+- ``quanta-gbs-bmc``    Quanta GBS server BMC
 - ``quanta-gsj``        Quanta GSJ server BMC
 
 There are also two more SoCs, NPCM710 and NPCM705, which are single-core
-- 
2.20.1

From: Nolan Leake <nolan@sigbus.net>

This is just enough to make reboot and poweroff work. Works for
linux, u-boot, and the arm trusted firmware. Not tested, but should
work for plan9, and bare-metal/hobby OSes, since they seem to generally
do what linux does for reset.

The watchdog timer functionality is not yet implemented.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
Signed-off-by: Nolan Leake <nolan@sigbus.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
[PMM: tweaked commit title; fixed region size to 0x200;
 moved header file to include/]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bcm2835_peripherals.h |   3 +-
 include/hw/misc/bcm2835_powermgt.h   |  29 +++++
 hw/arm/bcm2835_peripherals.c         |  13 ++-
 hw/misc/bcm2835_powermgt.c           | 160 +++++++++++++++++++++++++++
 hw/misc/meson.build                  |   1 +
 5 files changed, 204 insertions(+), 2 deletions(-)
 create mode 100644 include/hw/misc/bcm2835_powermgt.h
 create mode 100644 hw/misc/bcm2835_powermgt.c

diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2835_peripherals.h
+++ b/include/hw/arm/bcm2835_peripherals.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/bcm2835_mphi.h"
 #include "hw/misc/bcm2835_thermal.h"
 #include "hw/misc/bcm2835_cprman.h"
+#include "hw/misc/bcm2835_powermgt.h"
 #include "hw/sd/sdhci.h"
 #include "hw/sd/bcm2835_sdhost.h"
 #include "hw/gpio/bcm2835_gpio.h"
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
     BCM2835MphiState mphi;
     UnimplementedDeviceState txp;
     UnimplementedDeviceState armtmr;
-    UnimplementedDeviceState powermgt;
+    BCM2835PowerMgtState powermgt;
     BCM2835CprmanState cprman;
     PL011State uart0;
     BCM2835AuxState aux;
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/bcm2835_powermgt.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 Power Management emulation
+ *
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef BCM2835_POWERMGT_H
+#define BCM2835_POWERMGT_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
+
+struct BCM2835PowerMgtState {
+    SysBusDevice busdev;
+    MemoryRegion iomem;
+
+    uint32_t rstc;
+    uint32_t rsts;
+    uint32_t wdog;
+};
+
+#endif
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
 
     object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
                                    OBJECT(&s->gpu_bus_mr));
+
+    /* Power Management */
+    object_initialize_child(obj, "powermgt", &s->powermgt,
+                            TYPE_BCM2835_POWERMGT);
 }
 
 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
         qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
                                INTERRUPT_USB));
 
+    /* Power Management */
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
+        return;
+    }
+
+    memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
+                sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
+
     create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
-    create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
     create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
     create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
     create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/bcm2835_powermgt.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * BCM2835 Power Management emulation
+ *
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/bcm2835_powermgt.h"
+#include "migration/vmstate.h"
+#include "sysemu/runstate.h"
+
+#define PASSWORD 0x5a000000
+#define PASSWORD_MASK 0xff000000
+
+#define R_RSTC 0x1c
+#define V_RSTC_RESET 0x20
+#define R_RSTS 0x20
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
+#define R_WDOG 0x24
+
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
+                                      unsigned size)
+{
+    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
+    uint32_t res = 0;
+
+    switch (offset) {
+    case R_RSTC:
+        res = s->rstc;
+        break;
+    case R_RSTS:
+        res = s->rsts;
+        break;
+    case R_WDOG:
+        res = s->wdog;
+        break;
+
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
+                      "\n", offset);
+        res = 0;
+        break;
+    }
+
+    return res;
+}
+
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
+                                   uint64_t value, unsigned size)
+{
+    BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
+
+    if ((value & PASSWORD_MASK) != PASSWORD) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "bcm2835_powermgt_write: Bad password 0x%"PRIx64
+                      " at offset 0x%08"HWADDR_PRIx"\n",
+                      value, offset);
+        return;
+    }
+
+    value = value & ~PASSWORD_MASK;
+
+    switch (offset) {
+    case R_RSTC:
+        s->rstc = value;
+        if (value & V_RSTC_RESET) {
+            if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
+                qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+            } else {
+                qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+            }
+        }
+        break;
+    case R_RSTS:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: RSTS\n");
+        s->rsts = value;
+        break;
+    case R_WDOG:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: WDOG\n");
+        s->wdog = value;
+        break;
+
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
+                      "\n", offset);
+        break;
+    }
+}
+
+static const MemoryRegionOps bcm2835_powermgt_ops = {
+    .read = bcm2835_powermgt_read,
+    .write = bcm2835_powermgt_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+};
+
+static const VMStateDescription vmstate_bcm2835_powermgt = {
+    .name = TYPE_BCM2835_POWERMGT,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
+        VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
+        VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void bcm2835_powermgt_init(Object *obj)
+{
+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
+
+    memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
+                          TYPE_BCM2835_POWERMGT, 0x200);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static void bcm2835_powermgt_reset(DeviceState *dev)
+{
+    BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
+
+    /* https://elinux.org/BCM2835_registers#PM */
+    s->rstc = 0x00000102;
+    s->rsts = 0x00001000;
+    s->wdog = 0x00000000;
+}
+
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = bcm2835_powermgt_reset;
+    dc->vmsd = &vmstate_bcm2835_powermgt;
+}
+
+static TypeInfo bcm2835_powermgt_info = {
+    .name          = TYPE_BCM2835_POWERMGT,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(BCM2835PowerMgtState),
+    .class_init    = bcm2835_powermgt_class_init,
+    .instance_init = bcm2835_powermgt_init,
+};
+
+static void bcm2835_powermgt_register_types(void)
+{
+    type_register_static(&bcm2835_powermgt_info);
+}
+
+type_init(bcm2835_powermgt_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
   'bcm2835_rng.c',
   'bcm2835_thermal.c',
   'bcm2835_cprman.c',
+  'bcm2835_powermgt.c',
 ))
 softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
 softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Add a test booting and quickly shutdown a raspi2 machine,
to test the power management model:

(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
  console: [    0.000000] Booting Linux on physical CPU 0xf00
  console: [    0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
  console: [    0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
  console: [    0.000000] CPU: div instructions available: patching division code
  console: [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
  console: [    0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
  ...
  console: Boot successful.
  console: cat /proc/cpuinfo
  console: / # cat /proc/cpuinfo
  ...
  console: processor      : 3
  console: model name     : ARMv7 Processor rev 5 (v7l)
  console: BogoMIPS       : 125.00
  console: Features       : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
  console: CPU implementer        : 0x41
  console: CPU architecture: 7
  console: CPU variant    : 0x0
  console: CPU part       : 0xc07
  console: CPU revision   : 5
  console: Hardware       : BCM2835
  console: Revision       : 0000
  console: Serial         : 0000000000000000
  console: cat /proc/iomem
  console: / # cat /proc/iomem
  console: 00000000-3bffffff : System RAM
  console: 00008000-00afffff : Kernel code
  console: 00c00000-00d468ef : Kernel data
  console: 3f006000-3f006fff : dwc_otg
  console: 3f007000-3f007eff : /soc/dma@7e007000
  console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
  console: 3f100000-3f100027 : /soc/watchdog@7e100000
  console: 3f101000-3f102fff : /soc/cprman@7e101000
  console: 3f200000-3f2000b3 : /soc/gpio@7e200000
  PASS (24.59 s)
  RESULTS    : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
  JOB TIME   : 25.02 s

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@
 from avocado import skip
 from avocado import skipUnless
 from avocado_qemu import Test
+from avocado_qemu import exec_command
 from avocado_qemu import exec_command_and_wait_for_pattern
 from avocado_qemu import interrupt_interactive_console_until_pattern
 from avocado_qemu import wait_for_console_pattern
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
         """
         self.do_test_arm_raspi2(0)
 
+    def test_arm_raspi2_initrd(self):
+        """
+        :avocado: tags=arch:arm
+        :avocado: tags=machine:raspi2
+        """
+        deb_url = ('http://archive.raspberrypi.org/debian/'
+                   'pool/main/r/raspberrypi-firmware/'
+                   'raspberrypi-kernel_1.20190215-1_armhf.deb')
+        deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
+        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+        kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
+        dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
+
+        initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
+                      '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
+                      'arm/rootfs-armv7a.cpio.gz')
+        initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
+        initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
+        initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
+        archive.gzip_uncompress(initrd_path_gz, initrd_path)
+
+        self.vm.set_console()
+        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+                               'earlycon=pl011,0x3f201000 console=ttyAMA0 '
+                               'panic=-1 noreboot ' +
+                               'dwc_otg.fiq_fsm_enable=0')
+        self.vm.add_args('-kernel', kernel_path,
+                         '-dtb', dtb_path,
+                         '-initrd', initrd_path,
+                         '-append', kernel_command_line,
+                         '-no-reboot')
+        self.vm.launch()
+        self.wait_for_console_pattern('Boot successful.')
+
+        exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+                                                'BCM2835')
+        exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
+                                                '/soc/cprman@7e101000')
+        exec_command(self, 'halt')
+        # Wait for VM to shut down gracefully
+        self.vm.wait()
+
     def test_arm_exynos4210_initrd(self):
         """
         :avocado: tags=arch:arm
-- 
2.20.1

From: Joe Komlodi <joe.komlodi@xilinx.com>

If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
assert due to fpst->default_nan_mode being set.

To avoid this, we check to see what NaN mode we're running in before we call
floatxx_silence_nan().

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper-a64.c | 12 +++++++++---
 target/arm/vfp_helper.c | 24 ++++++++++++++++++------
 2 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
         float16 nan = a;
         if (float16_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float16_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float16_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
         float32 nan = a;
         if (float32_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float32_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float32_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
         float64 nan = a;
         if (float64_is_signaling_nan(a, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float64_silence_nan(a, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float64_silence_nan(a, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan = float64_default_nan(fpst);
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
         float16 nan = f16;
         if (float16_is_signaling_nan(f16, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float16_silence_nan(f16, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float16_silence_nan(f16, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float16_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
         float32 nan = f32;
         if (float32_is_signaling_nan(f32, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float32_silence_nan(f32, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float32_silence_nan(f32, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float32_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
         float64 nan = f64;
         if (float64_is_signaling_nan(f64, fpst)) {
             float_raise(float_flag_invalid, fpst);
-            nan = float64_silence_nan(f64, fpst);
+            if (!fpst->default_nan_mode) {
+                nan = float64_silence_nan(f64, fpst);
+            }
         }
         if (fpst->default_nan_mode) {
             nan =  float64_default_nan(fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
         float16 nan = f16;
         if (float16_is_signaling_nan(f16, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float16_silence_nan(f16, s);
+            if (!s->default_nan_mode) {
+                nan = float16_silence_nan(f16, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float16_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
         float32 nan = f32;
         if (float32_is_signaling_nan(f32, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float32_silence_nan(f32, s);
+            if (!s->default_nan_mode) {
+                nan = float32_silence_nan(f32, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float32_default_nan(s);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
         float64 nan = f64;
         if (float64_is_signaling_nan(f64, s)) {
             float_raise(float_flag_invalid, s);
-            nan = float64_silence_nan(f64, s);
+            if (!s->default_nan_mode) {
+                nan = float64_silence_nan(f64, fpstp);
+            }
         }
         if (s->default_nan_mode) {
             nan =  float64_default_nan(s);
-- 
2.20.1

From: Maxim Uvarov <maxim.uvarov@linaro.org>

qemu has 2 type of functions: shutdown and reboot. Shutdown
function has to be used for machine shutdown. Otherwise we cause
a reset with a bogus "cause" value, when we intended a shutdown.

Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/gpio/gpio_pwr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/gpio_pwr.c
+++ b/hw/gpio/gpio_pwr.c
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
 static void gpio_pwr_shutdown(void *opaque, int n, int level)
 {
     if (level) {
-        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
     }
 }
 
-- 
2.20.1

In do_ldst(), the calculation of the offset needs to be based on the
size of the memory access, not the size of the elements in the
vector.  This meant we were getting it wrong for the widening and
narrowing variants of the various VLDR and VSTR insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
---
 target/arm/translate-mve.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
     }
 }
 
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
+                    unsigned msize)
 {
     TCGv_i32 addr;
     uint32_t offset;
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
         return true;
     }
 
-    offset = a->imm << a->size;
+    offset = a->imm << msize;
     if (!a->a) {
         offset = -offset;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
         { gen_helper_mve_vstrw, gen_helper_mve_vldrw },
         { NULL, NULL }
     };
-    return do_ldst(s, a, ldstfns[a->size][a->l]);
+    return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
 }
 
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST)                  \
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE)           \
     static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a)   \
     {                                                           \
         static MVEGenLdStFn * const ldstfns[2][2] = {           \
             { gen_helper_mve_##ST, gen_helper_mve_##SLD },      \
             { NULL, gen_helper_mve_##ULD },                     \
         };                                                      \
-        return do_ldst(s, a, ldstfns[a->u][a->l]);              \
+        return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE);       \
     }
 
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
 
 static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
 {
-- 
2.20.1

The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
insns had some bugs:
 * the 32x32 multiply of elements was being done as 32x32->32,
   not 32x32->64
 * we were incorrectly maintaining the accumulator in its full
   72-bit form across all 4 beats of the insn; in the pseudocode
   it is squashed back into the 64 bits of the RdaHi:RdaLo
   registers after each beat

In particular, fixing the second of these allows us to recast
the implementation to avoid 128-bit arithmetic entirely.

Since the element size here is always 4, we can also drop the
parameterization of ESIZE to make the code a little more readable.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
---
 target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
 1 file changed, 21 insertions(+), 17 deletions(-)

diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu/int128.h"
 #include "cpu.h"
 #include "internals.h"
 #include "vec_internal.h"
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
 
 /*
- * Rounding multiply add long dual accumulate high: we must keep
- * a 72-bit internal accumulator value and return the top 64 bits.
+ * Rounding multiply add long dual accumulate high. In the pseudocode
+ * this is implemented with a 72-bit internal accumulator value of which
+ * the top 64 bits are returned. We optimize this to avoid having to
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
+ * is squashed back into 64-bits after each beat.
  */
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128)         \
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB)                            \
     uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn,         \
                                     void *vm, uint64_t a)               \
     {                                                                   \
         uint16_t mask = mve_element_mask(env);                          \
         unsigned e;                                                     \
         TYPE *n = vn, *m = vm;                                          \
-        Int128 acc = int128_lshift(TO128(a), 8);                        \
-        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {              \
+        for (e = 0; e < 16 / 4; e++, mask >>= 4) {                      \
             if (mask & 1) {                                             \
+                LTYPE mul;                                              \
                 if (e & 1) {                                            \
-                    acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
-                                            m[H##ESIZE(e)]));           \
+                    mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)];        \
+                    if (SUB) {                                          \
+                        mul = -mul;                                     \
+                    }                                                   \
                 } else {                                                \
-                    acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
-                                             m[H##ESIZE(e)]));          \
+                    mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)];        \
                 }                                                       \
-                acc = int128_add(acc, int128_make64(1 << 7));           \
+                mul = (mul >> 8) + ((mul >> 7) & 1);                    \
+                a += mul;                                               \
             }                                                           \
         }                                                               \
         mve_advance_vpt(env);                                           \
-        return int128_getlo(int128_rshift(acc, 8));                     \
+        return a;                                                       \
     }
 
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
 
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
 
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
 
 /* Vector add across vector */
 #define DO_VADDV(OP, ESIZE, TYPE)                               \
-- 
2.20.1

The function asimd_imm_const() in translate-neon.c is an
implementation of the pseudocode AdvSIMDExpandImm(), which we will
also want for MVE.  Move the implementation to translate.c, with a
prototype in translate.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
---
 target/arm/translate.h      | 16 ++++++++++
 target/arm/translate-neon.c | 63 -------------------------------------
 target/arm/translate.c      | 57 +++++++++++++++++++++++++++++++++
 3 files changed, 73 insertions(+), 63 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
     return opc | s->be_data;
 }
 
+/**
+ * asimd_imm_const: Expand an encoded SIMD constant value
+ *
+ * Expand a SIMD constant value. This is essentially the pseudocode
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
+ * VMVN and VBIC (when cmode < 14 && op == 1).
+ *
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
+ * callers must catch this.
+ *
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
+ * we produce an immediate constant value of 0 in these cases.
+ */
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
+
 #endif /* TARGET_ARM_TRANSLATE_H */
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c
+++ b/target/arm/translate-neon.c
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
 DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
 DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
 
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
-{
-    /*
-     * Expand the encoded constant.
-     * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
-     * We choose to not special-case this and will behave as if a
-     * valid constant encoding of 0 had been given.
-     * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
-     */
-    switch (cmode) {
-    case 0: case 1:
-        /* no-op */
-        break;
-    case 2: case 3:
-        imm <<= 8;
-        break;
-    case 4: case 5:
-        imm <<= 16;
-        break;
-    case 6: case 7:
-        imm <<= 24;
-        break;
-    case 8: case 9:
-        imm |= imm << 16;
-        break;
-    case 10: case 11:
-        imm = (imm << 8) | (imm << 24);
-        break;
-    case 12:
-        imm = (imm << 8) | 0xff;
-        break;
-    case 13:
-        imm = (imm << 16) | 0xffff;
-        break;
-    case 14:
-        if (op) {
-            /*
-             * This is the only case where the top and bottom 32 bits
-             * of the encoded constant differ.
-             */
-            uint64_t imm64 = 0;
-            int n;
-
-            for (n = 0; n < 8; n++) {
-                if (imm & (1 << n)) {
-                    imm64 |= (0xffULL << (n * 8));
-                }
-            }
-            return imm64;
-        }
-        imm |= (imm << 8) | (imm << 16) | (imm << 24);
-        break;
-    case 15:
-        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
-            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
-        break;
-    }
-    if (op) {
-        imm = ~imm;
-    }
-    return dup_const(MO_32, imm);
-}
-
 static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
                         GVecGen2iFn *fn)
 {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
     a64_translate_init();
 }
 
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
+{
+    /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
+    switch (cmode) {
+    case 0: case 1:
+        /* no-op */
+        break;
+    case 2: case 3:
+        imm <<= 8;
+        break;
+    case 4: case 5:
+        imm <<= 16;
+        break;
+    case 6: case 7:
+        imm <<= 24;
+        break;
+    case 8: case 9:
+        imm |= imm << 16;
+        break;
+    case 10: case 11:
+        imm = (imm << 8) | (imm << 24);
+        break;
+    case 12:
+        imm = (imm << 8) | 0xff;
+        break;
+    case 13:
+        imm = (imm << 16) | 0xffff;
+        break;
+    case 14:
+        if (op) {
+            /*
+             * This is the only case where the top and bottom 32 bits
+             * of the encoded constant differ.
+             */
+            uint64_t imm64 = 0;
+            int n;
+
+            for (n = 0; n < 8; n++) {
+                if (imm & (1 << n)) {
+                    imm64 |= (0xffULL << (n * 8));
+                }
+            }
+            return imm64;
+        }
+        imm |= (imm << 8) | (imm << 16) | (imm << 24);
+        break;
+    case 15:
+        imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
+            | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
+        break;
+    }
+    if (op) {
+        imm = ~imm;
+    }
+    return dup_const(MO_32, imm);
+}
+
 /* Generate a label used for skipping this instruction */
 void arm_gen_condlabel(DisasContext *s)
 {
-- 
2.20.1

The A64 AdvSIMD modified-immediate grouping uses almost the same
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
which we add the AArch64-specific case for cmode 15 op 1) instead of
reimplementing it all.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
---
 target/arm/translate.h     |  3 +-
 target/arm/translate-a64.c | 86 ++++----------------------------------
 target/arm/translate.c     | 17 +++++++-
 3 files changed, 24 insertions(+), 82 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
  * VMVN and VBIC (when cmode < 14 && op == 1).
  *
  * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
- * callers must catch this.
+ * callers must catch this; we return the 64-bit constant value defined
+ * for AArch64.
  *
  * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
  * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
 {
     int rd = extract32(insn, 0, 5);
     int cmode = extract32(insn, 12, 4);
-    int cmode_3_1 = extract32(cmode, 1, 3);
-    int cmode_0 = extract32(cmode, 0, 1);
     int o2 = extract32(insn, 11, 1);
     uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
     bool is_neg = extract32(insn, 29, 1);
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
         return;
     }
 
-    /* See AdvSIMDExpandImm() in ARM ARM */
-    switch (cmode_3_1) {
-    case 0: /* Replicate(Zeros(24):imm8, 2) */
-    case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
-    case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
-    case 3: /* Replicate(imm8:Zeros(24), 2) */
-    {
-        int shift = cmode_3_1 * 8;
-        imm = bitfield_replicate(abcdefgh << shift, 32);
-        break;
-    }
-    case 4: /* Replicate(Zeros(8):imm8, 4) */
-    case 5: /* Replicate(imm8:Zeros(8), 4) */
-    {
-        int shift = (cmode_3_1 & 0x1) * 8;
-        imm = bitfield_replicate(abcdefgh << shift, 16);
-        break;
-    }
-    case 6:
-        if (cmode_0) {
-            /* Replicate(Zeros(8):imm8:Ones(16), 2) */
-            imm = (abcdefgh << 16) | 0xffff;
-        } else {
-            /* Replicate(Zeros(16):imm8:Ones(8), 2) */
-            imm = (abcdefgh << 8) | 0xff;
-        }
-        imm = bitfield_replicate(imm, 32);
-        break;
-    case 7:
-        if (!cmode_0 && !is_neg) {
-            imm = bitfield_replicate(abcdefgh, 8);
-        } else if (!cmode_0 && is_neg) {
-            int i;
-            imm = 0;
-            for (i = 0; i < 8; i++) {
-                if ((abcdefgh) & (1 << i)) {
-                    imm |= 0xffULL << (i * 8);
-                }
-            }
-        } else if (cmode_0) {
-            if (is_neg) {
-                imm = (abcdefgh & 0x3f) << 48;
-                if (abcdefgh & 0x80) {
-                    imm |= 0x8000000000000000ULL;
-                }
-                if (abcdefgh & 0x40) {
-                    imm |= 0x3fc0000000000000ULL;
-                } else {
-                    imm |= 0x4000000000000000ULL;
-                }
-            } else {
-                if (o2) {
-                    /* FMOV (vector, immediate) - half-precision */
-                    imm = vfp_expand_imm(MO_16, abcdefgh);
-                    /* now duplicate across the lanes */
-                    imm = bitfield_replicate(imm, 16);
-                } else {
-                    imm = (abcdefgh & 0x3f) << 19;
-                    if (abcdefgh & 0x80) {
-                        imm |= 0x80000000;
-                    }
-                    if (abcdefgh & 0x40) {
-                        imm |= 0x3e000000;
-                    } else {
-                        imm |= 0x40000000;
-                    }
-                    imm |= (imm << 32);
-                }
-            }
-        }
-        break;
-    default:
-        g_assert_not_reached();
-    }
-
-    if (cmode_3_1 != 7 && is_neg) {
-        imm = ~imm;
+    if (cmode == 15 && o2 && !is_neg) {
+        /* FMOV (vector, immediate) - half-precision */
+        imm = vfp_expand_imm(MO_16, abcdefgh);
+        /* now duplicate across the lanes */
+        imm = bitfield_replicate(imm, 16);
+    } else {
+        imm = asimd_imm_const(abcdefgh, cmode, is_neg);
     }
 
     if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
     case 14:
         if (op) {
             /*
-             * This is the only case where the top and bottom 32 bits
-             * of the encoded constant differ.
+             * This and cmode == 15 op == 1 are the only cases where
+             * the top and bottom 32 bits of the encoded constant differ.
              */
             uint64_t imm64 = 0;
             int n;
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
         imm |= (imm << 8) | (imm << 16) | (imm << 24);
         break;
     case 15:
+        if (op) {
+            /* Reserved encoding for AArch32; valid for AArch64 */
+            uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
+            if (imm & 0x80) {
+                imm64 |= 0x8000000000000000ULL;
+            }
+            if (imm & 0x40) {
+                imm64 |= 0x3fc0000000000000ULL;
+            } else {
+                imm64 |= 0x4000000000000000ULL;
+            }
+            return imm64;
+        }
         imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
             | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
         break;
-- 
2.20.1

Use dup_const() instead of bitfield_replicate() in
disas_simd_mod_imm().

(We can't replace the other use of bitfield_replicate() in this file,
in logic_imm_decode_wmask(), because that location needs to handle 2
and 4 bit elements, which dup_const() cannot.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
---
 target/arm/translate-a64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
         /* FMOV (vector, immediate) - half-precision */
         imm = vfp_expand_imm(MO_16, abcdefgh);
         /* now duplicate across the lanes */
-        imm = bitfield_replicate(imm, 16);
+        imm = dup_const(MO_16, imm);
     } else {
         imm = asimd_imm_const(abcdefgh, cmode, is_neg);
     }
-- 
2.20.1

Implement the MVE logical-immediate insns (VMOV, VMVN,
VORR and VBIC). These have essentially the same encoding
as their Neon equivalents, and we implement the decode
in the same way.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  4 +++
 target/arm/mve.decode      | 17 +++++++++++++
 target/arm/mve_helper.c    | 24 ++++++++++++++++++
 target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 95 insertions(+)

Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
and VQSHLU.

The size-and-immediate encoding here is the same as Neon, and we
handle it the same way neon-dp.decode does.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    | 16 +++++++++++
 target/arm/mve.decode      | 23 +++++++++++++++
 target/arm/mve_helper.c    | 57 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
 4 files changed, 147 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
 DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
 DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
 DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
+
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
 &2op qd qm qn size
 &2scalar qd qn rm size
 &1imm qd imm cmode op
+&2shift qd qm shift size
 
 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
 # Note that both Rn and Qd are 3 bits only (no D bit)
@@ -XXX,XX +XXX,XX @@
 @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
 
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
+@2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+@2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
+
 # Vector loads and stores
 
 # Widening loads and narrowing stores:
@@ -XXX,XX +XXX,XX @@ VPST             1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
 # So we have a single decode line and check the cmode/op in the
 # trans function.
 Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
+
+# Shifts by immediate
+
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
+VSHLI             111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
+VQSHLI_S          111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
+VQSHLI_U          111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
+
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
+VQSHLUI           111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
     WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
 #define DO_UQRSHL_OP(N, M, satp) \
     WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
+#define DO_SUQSHL_OP(N, M, satp) \
+    WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
 
 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
 DO_VADDV(vaddvub, 1, uint8_t)
 DO_VADDV(vaddvuh, 2, uint16_t)
 DO_VADDV(vaddvuw, 4, uint32_t)
+
+/* Shifts by immediate */
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN)                          \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        TYPE *d = vd, *m = vm;                                  \
+        uint16_t mask = mve_element_mask(env);                  \
+        unsigned e;                                             \
+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
+            mergemask(&d[H##ESIZE(e)],                          \
+                      FN(m[H##ESIZE(e)], shift), mask);         \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN)                      \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        TYPE *d = vd, *m = vm;                                  \
+        uint16_t mask = mve_element_mask(env);                  \
+        unsigned e;                                             \
+        bool qc = false;                                        \
+        for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) {      \
+            bool sat = false;                                   \
+            mergemask(&d[H##ESIZE(e)],                          \
+                      FN(m[H##ESIZE(e)], shift, &sat), mask);   \
+            qc |= sat & mask & 1;                               \
+        }                                                       \
+        if (qc) {                                               \
+            env->vfp.qc[0] = qc;                                \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+/* provide unsigned 2-op shift helpers for all sizes */
+#define DO_2SHIFT_U(OP, FN)                     \
+    DO_2SHIFT(OP##b, 1, uint8_t, FN)            \
+    DO_2SHIFT(OP##h, 2, uint16_t, FN)           \
+    DO_2SHIFT(OP##w, 4, uint32_t, FN)
+
+#define DO_2SHIFT_SAT_U(OP, FN)                 \
+    DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN)        \
+    DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN)       \
+    DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
+#define DO_2SHIFT_SAT_S(OP, FN)                 \
+    DO_2SHIFT_SAT(OP##b, 1, int8_t, FN)         \
+    DO_2SHIFT_SAT(OP##h, 2, int16_t, FN)        \
+    DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
+
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
 typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
     }
     return do_1imm(s, a, fn);
 }
+
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
+                      bool negateshift)
+{
+    TCGv_ptr qd, qm;
+    int shift = a->shift;
+
+    if (!dc_isar_feature(aa32_mve, s) ||
+        !mve_check_qreg_bank(s, a->qd | a->qm) ||
+        !fn) {
+        return false;
+    }
+    if (!mve_eci_check(s) || !vfp_access_check(s)) {
+        return true;
+    }
+
+    /*
+     * When we handle a right shift insn using a left-shift helper
+     * which permits a negative shift count to indicate a right-shift,
+     * we must negate the shift count.
+     */
+    if (negateshift) {
+        shift = -shift;
+    }
+
+    qd = mve_qreg_ptr(a->qd);
+    qm = mve_qreg_ptr(a->qm);
+    fn(cpu_env, qd, qm, tcg_constant_i32(shift));
+    tcg_temp_free_ptr(qd);
+    tcg_temp_free_ptr(qm);
+    mve_update_eci(s);
+    return true;
+}
+
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT)                         \
+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+    {                                                           \
+        static MVEGenTwoOpShiftFn * const fns[] = {             \
+            gen_helper_mve_##FN##b,                             \
+            gen_helper_mve_##FN##h,                             \
+            gen_helper_mve_##FN##w,                             \
+            NULL,                                               \
+        };                                                      \
+        return do_2shift(s, a, fns[a->size], NEGATESHIFT);      \
+    }
+
+DO_2SHIFT(VSHLI, vshli_u, false)
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
-- 
2.20.1

Implement the MVE vector shift right by immediate insns VSHRI and
VRSHRI.  As with Neon, we implement these by using helper functions
which perform left shifts but allow negative shift counts to indicate
right shifts.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
---
 target/arm/helper-mve.h     | 12 ++++++++++++
 target/arm/translate.h      | 20 ++++++++++++++++++++
 target/arm/mve.decode       | 28 ++++++++++++++++++++++++++++
 target/arm/mve_helper.c     |  7 +++++++
 target/arm/translate-mve.c  |  5 +++++
 target/arm/translate-neon.c | 18 ------------------
 6 files changed, 72 insertions(+), 18 deletions(-)

Implement the MVE VHLL (vector shift left long) insn.  This has two
encodings: the T1 encoding is the usual shift-by-immediate format,
and the T2 encoding is a special case where the shift count is always
equal to the element size.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  9 +++++++
 target/arm/mve.decode      | 53 +++++++++++++++++++++++++++++++++++---
 target/arm/mve_helper.c    | 32 +++++++++++++++++++++++
 target/arm/translate-mve.c | 15 +++++++++++
 4 files changed, 105 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@
 @2_shl_h .... .... .. 01  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
 @2_shl_w .... .... .. 1   shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
 
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
+@2_shll_h .... .... ... 1  shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
+# VSHLL encoding T2 where shift == esize
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
+                qd=%qd qm=%qm size=0 shift=8
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
+                qd=%qd qm=%qm size=1 shift=16
+
 # Right shifts are encoded as N - shift, where N is the element size in bits.
 %rshift_i5  16:5 !function=rsub_32
 %rshift_i4  16:4 !function=rsub_16
@@ -XXX,XX +XXX,XX @@ VADD             1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
 VSUB             1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
 VMUL             1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
 
-VMULH_S          111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
-VMULH_U          111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
+# overlaps what would be size=0b11 VMULH/VRMULH
+{
+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_BS       111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
 
-VRMULH_S         111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
-VRMULH_U         111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+  VMULH_S        111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_BU       111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VMULH_U        111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_TS       111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VRMULH_S       111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+}
+
+{
+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
+  VSHLL_TU       111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
+
+  VRMULH_U       111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
+}
 
 VMAX_S           111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
 VMAX_U           111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
@@ -XXX,XX +XXX,XX @@ VRSHRI_S          111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
 VRSHRI_U          111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
+
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_BS          111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_BU          111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_TS          111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
+
+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
+VSHLL_TU          111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
 DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
 DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
+
+/*
+ * Long shifts taking half-sized inputs from top or bottom of the input
+ * vector and producing a double-width result. ESIZE, TYPE are for
+ * the input, and LESIZE, LTYPE for the output.
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
+ * because the long shift is strictly left-only.
+ */
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE)                   \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,             \
+                                void *vm, uint32_t shift)               \
+    {                                                                   \
+        LTYPE *d = vd;                                                  \
+        TYPE *m = vm;                                                   \
+        uint16_t mask = mve_element_mask(env);                          \
+        unsigned le;                                                    \
+        assert(shift <= 16);                                            \
+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) {         \
+            LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift;        \
+            mergemask(&d[H##LESIZE(le)], r, mask);                      \
+        }                                                               \
+        mve_advance_vpt(env);                                           \
+    }
+
+#define DO_VSHLL_ALL(OP, TOP)                                \
+    DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t)             \
+    DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t)           \
+    DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t)            \
+    DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t)          \
+
+DO_VSHLL_ALL(vshllb, false)
+DO_VSHLL_ALL(vshllt, true)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
 DO_2SHIFT(VSHRI_U, vshli_u, true)
 DO_2SHIFT(VRSHRI_S, vrshli_s, true)
 DO_2SHIFT(VRSHRI_U, vrshli_u, true)
+
+#define DO_VSHLL(INSN, FN)                                      \
+    static bool trans_##INSN(DisasContext *s, arg_2shift *a)    \
+    {                                                           \
+        static MVEGenTwoOpShiftFn * const fns[] = {             \
+            gen_helper_mve_##FN##b,                             \
+            gen_helper_mve_##FN##h,                             \
+        };                                                      \
+        return do_2shift(s, a, fns[a->size], false);            \
+    }
+
+DO_VSHLL(VSHLL_BS, vshllbs)
+DO_VSHLL(VSHLL_BU, vshllbu)
+DO_VSHLL(VSHLL_TS, vshllts)
+DO_VSHLL(VSHLL_TU, vshlltu)
-- 
2.20.1

Implement the MVE VSRI and VSLI insns, which perform a
shift-and-insert operation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  8 ++++++++
 target/arm/mve.decode      |  9 ++++++++
 target/arm/mve_helper.c    | 42 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  3 +++
 4 files changed, 62 insertions(+)

Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.

do_urshr() is borrowed from sve_helper.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    | 10 ++++++++++
 target/arm/mve.decode      | 11 +++++++++++
 target/arm/mve_helper.c    | 40 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 15 ++++++++++++++
 4 files changed, 76 insertions(+)

Implement the MVE saturating shift-right-and-narrow insns
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.

do_srshr() is borrowed from sve_helper.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  30 +++++++++++
 target/arm/mve.decode      |  28 ++++++++++
 target/arm/mve_helper.c    | 104 +++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c |  12 +++++
 4 files changed, 174 insertions(+)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -XXX,XX +XXX,XX @@ VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
 VRSHRNB           111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
 VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
 VRSHRNT           111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
+
+VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNB_S         111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNT_S         111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNB_U         111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
+VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
+VQSHRNT_U         111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
+
+VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+VQSHRUNB          111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+VQSHRUNT          111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
+
+VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNB_S        111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNT_S        111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNB_U        111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
+VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
+VQRSHRNT_U        111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
+
+VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
+VQRSHRUNB         111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
+VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
+VQRSHRUNT         111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
     }
 }
 
+static inline int64_t do_srshr(int64_t x, unsigned sh)
+{
+    if (likely(sh < 64)) {
+        return (x >> sh) + ((x >> (sh - 1)) & 1);
+    } else {
+        /* Rounding the sign bit always produces 0. */
+        return 0;
+    }
+}
+
 DO_VSHRN_ALL(vshrn, DO_SHR)
 DO_VSHRN_ALL(vrshrn, do_urshr)
+
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
+                                 bool *satp)
+{
+    if (val > max) {
+        *satp = true;
+        return max;
+    } else if (val < min) {
+        *satp = true;
+        return min;
+    } else {
+        return val;
+    }
+}
+
+/* Saturating narrowing right shifts */
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN)   \
+    void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd,     \
+                                void *vm, uint32_t shift)       \
+    {                                                           \
+        LTYPE *m = vm;                                          \
+        TYPE *d = vd;                                           \
+        uint16_t mask = mve_element_mask(env);                  \
+        bool qc = false;                                        \
+        unsigned le;                                            \
+        for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
+            bool sat = false;                                   \
+            TYPE r = FN(m[H##LESIZE(le)], shift, &sat);         \
+            mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask);     \
+            qc |= sat && (mask & 1 << (TOP * ESIZE));           \
+        }                                                       \
+        if (qc) {                                               \
+            env->vfp.qc[0] = qc;                                \
+        }                                                       \
+        mve_advance_vpt(env);                                   \
+    }
+
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN)       \
+    DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
+
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN)      \
+    DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
+
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN)         \
+    DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
+
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN)                           \
+    DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN)        \
+    DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
+
+#define DO_SHRN_SB(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
+#define DO_SHRN_UB(N, M, SATP)                                  \
+    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
+#define DO_SHRUN_B(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
+
+#define DO_SHRN_SH(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
+#define DO_SHRN_UH(N, M, SATP)                                  \
+    do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
+#define DO_SHRUN_H(N, M, SATP)                                  \
+    do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
+
+#define DO_RSHRN_SB(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
+#define DO_RSHRN_UB(N, M, SATP)                                 \
+    do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
+#define DO_RSHRUN_B(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
+
+#define DO_RSHRN_SH(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
+#define DO_RSHRN_UH(N, M, SATP)                                 \
+    do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
+#define DO_RSHRUN_H(N, M, SATP)                                 \
+    do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
+
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
+
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
 DO_2SHIFT_N(VSHRNT, vshrnt)
 DO_2SHIFT_N(VRSHRNB, vrshrnb)
 DO_2SHIFT_N(VRSHRNT, vrshrnt)
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
-- 
2.20.1

Implement the MVE VSHLC insn, which performs a shift left of the
entire vector with carry in bits provided from a general purpose
register and carry out bits written back to that register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  2 ++
 target/arm/mve.decode      |  2 ++
 target/arm/mve_helper.c    | 38 ++++++++++++++++++++++++++++++++++++++
 target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
 4 files changed, 72 insertions(+)

Implement the MVE VADDLV insn; this is similar to VADDV, except
that it accumulates 32-bit elements into a 64-bit accumulator
stored in a pair of general-purpose registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
---
 target/arm/helper-mve.h    |  3 ++
 target/arm/mve.decode      |  6 +++-
 target/arm/mve_helper.c    | 19 ++++++++++++
 target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 90 insertions(+), 1 deletion(-)

The MVE extension to v8.1M includes some new shift instructions which
sit entirely within the non-coprocessor part of the encoding space
and which operate only on general-purpose registers.  They take up
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
with Rm == 13 or 15.

Implement the long shifts by immediate, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
an immediate shift count between 1 and 32.

Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
cases where v8.1M now requires that.  (Trying to change MOVS and ORRS
is too difficult, because the functions that generate the code are
shared between a dozen different kinds of arithmetic or logical
instruction for all A32, T16 and T32 encodings, and for some insns
and some encodings Rm==13,15 are valid.)

We make the helper functions we need for UQSHLL and SQSHLL take
a 32-bit value which the helper casts to int8_t because we'll need
these helpers also for the shift-by-register insns, where the shift
count might be < 0 or > 32.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  3 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 28 +++++++++++++
 target/arm/mve_helper.c | 10 +++++
 target/arm/translate.c  | 90 +++++++++++++++++++++++++++++++++++++++++
 5 files changed, 132 insertions(+)

Implement the MVE long shifts by register, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
the shift count in another general-purpose register, which might be
either positive or negative.

Like the long-shifts-by-immediate, these encodings sit in the space
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
we have to move the CSEL pattern into the same decodetree group.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  6 +++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 16 +++++--
 target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
 target/arm/translate.c  | 69 ++++++++++++++++++++++++++++++
 5 files changed, 182 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
 
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
 DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
 typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
 
 /**
  * arm_tbflags_from_tb:
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@
 &mcrr            !extern cp opc1 crm rt rt2
 
 &mve_shl_ri      rdalo rdahi shim
+&mve_shl_rr      rdalo rdahi rm
 
 # rdahi: bits [3:1] from insn, bit 0 is 1
 # rdalo: bits [3:1] from insn, bit 0 is 0
@@ -XXX,XX +XXX,XX @@
 
 @mve_shl_ri      ....... .... . ... . . ... ... . .. .. .... \
                  &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
+@mve_shl_rr      ....... .... . ... . rm:4  ... . .. .. .... \
+                 &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
 
 {
   TST_xrri       1110101 0000 1 .... 0 ... 1111 .... ....     @S_xrr_shi
@@ -XXX,XX +XXX,XX @@ BIC_rrri         1110101 0001 . .... 0 ... .... .... ....     @s_rrr_shi
     URSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111  @mve_shl_ri
     SRSHRL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111  @mve_shl_ri
     SQSHLL_ri    1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111  @mve_shl_ri
+
+    LSLL_rr      1110101 0010 1 ... 0 ....  ... 1  0000 1101  @mve_shl_rr
+    ASRL_rr      1110101 0010 1 ... 0 ....  ... 1  0010 1101  @mve_shl_rr
+    UQRSHLL64_rr 1110101 0010 1 ... 1 ....  ... 1  0000 1101  @mve_shl_rr
+    SQRSHRL64_rr 1110101 0010 1 ... 1 ....  ... 1  0010 1101  @mve_shl_rr
+    UQRSHLL48_rr 1110101 0010 1 ... 1 ....  ... 1  1000 1101  @mve_shl_rr
+    SQRSHRL48_rr 1110101 0010 1 ... 1 ....  ... 1  1010 1101  @mve_shl_rr
   ]
 
   MOV_rxri       1110101 0010 . 1111 0 ... .... .... ....     @s_rxr_shi
   ORR_rrri       1110101 0010 . .... 0 ... .... .... ....     @s_rrr_shi
+
+  # v8.1M CSEL and friends
+  CSEL           1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
 }
 {
   MVN_rxri       1110101 0011 . 1111 0 ... .... .... ....     @s_rxr_shi
@@ -XXX,XX +XXX,XX @@ SBC_rrri         1110101 1011 . .... 0 ... .... .... ....     @s_rrr_shi
 }
 RSB_rrri         1110101 1110 . .... 0 ... .... .... ....     @s_rrr_shi
 
-# v8.1M CSEL and friends
-CSEL             1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
-
 # Data-processing (register-shifted register)
 
 MOV_rxrr         1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
     return rdm;
 }
 
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
+}
+
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl_d(n, (int8_t)shift, false, NULL);
+}
+
 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 {
     return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
 {
     return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
 }
+
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
+}
+
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
+}
+
+/* Operate on 64-bit values, but saturate at 48 bits */
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
+                                    bool round, uint32_t *sat)
+{
+    if (shift <= -48) {
+        /* Rounding the sign bit always produces 0. */
+        if (round) {
+            return 0;
+        }
+        return src >> 63;
+    } else if (shift < 0) {
+        if (round) {
+            src >>= -shift - 1;
+            return (src >> 1) + (src & 1);
+        }
+        return src >> -shift;
+    } else if (shift < 48) {
+        int64_t val = src << shift;
+        int64_t extval = sextract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (!sat || src == 0) {
+        return 0;
+    }
+
+    *sat = 1;
+    return (1ULL << 47) - (src >= 0);
+}
+
+/* Operate on 64-bit values, but saturate at 48 bits */
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
+                                     bool round, uint32_t *sat)
+{
+    uint64_t val, extval;
+
+    if (shift <= -(48 + round)) {
+        return 0;
+    } else if (shift < 0) {
+        if (round) {
+            val = src >> (-shift - 1);
+            val = (val >> 1) + (val & 1);
+        } else {
+            val = src >> -shift;
+        }
+        extval = extract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (shift < 48) {
+        uint64_t val = src << shift;
+        uint64_t extval = extract64(val, 0, 48);
+        if (!sat || val == extval) {
+            return extval;
+        }
+    } else if (!sat || src == 0) {
+        return 0;
+    }
+
+    *sat = 1;
+    return MAKE_64BIT_MASK(0, 48);
+}
+
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
+}
+
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
+{
+    return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
     return do_mve_shl_ri(s, a, gen_urshr64_i64);
 }
 
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
+{
+    TCGv_i64 rda;
+    TCGv_i32 rdalo, rdahi;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+        /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
+        return false;
+    }
+    if (a->rdahi == 15) {
+        /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
+        return false;
+    }
+    if (!dc_isar_feature(aa32_mve, s) ||
+        !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
+        a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
+        a->rm == a->rdahi || a->rm == a->rdalo) {
+        /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
+        unallocated_encoding(s);
+        return true;
+    }
+
+    rda = tcg_temp_new_i64();
+    rdalo = load_reg(s, a->rdalo);
+    rdahi = load_reg(s, a->rdahi);
+    tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
+
+    /* The helper takes care of the sign-extension of the low 8 bits of Rm */
+    fn(rda, cpu_env, rda, cpu_R[a->rm]);
+
+    tcg_gen_extrl_i64_i32(rdalo, rda);
+    tcg_gen_extrh_i64_i32(rdahi, rda);
+    store_reg(s, a->rdalo, rdalo);
+    store_reg(s, a->rdahi, rdahi);
+    tcg_temp_free_i64(rda);
+
+    return true;
+}
+
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
+}
+
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
+}
+
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
+}
+
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
+}
+
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
+}
+
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
+{
+    return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
+}
+
 /*
  * Multiply and multiply accumulate
  */
-- 
2.20.1

Implement the MVE shifts by immediate, which perform shifts
on a single general-purpose register.

These patterns overlap with the long-shift-by-immediates,
so we have to rearrange the grouping a little here.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  3 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 31 ++++++++++++++-----
 target/arm/mve_helper.c | 10 ++++++
 target/arm/translate.c  | 68 +++++++++++++++++++++++++++++++++++++++--
 5 files changed, 104 insertions(+), 9 deletions(-)

Implement the MVE shifts by register, which perform
shifts on a single general-purpose register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
---
 target/arm/helper-mve.h |  2 ++
 target/arm/translate.h  |  1 +
 target/arm/t32.decode   | 18 ++++++++++++++----
 target/arm/mve_helper.c | 10 ++++++++++
 target/arm/translate.c  | 30 ++++++++++++++++++++++++++++++
 5 files changed, 57 insertions(+), 4 deletions(-)

The following changes since commit bf4460a8d9a86f6cfe05d7a7f470c48e3a93d8b2:

Merge tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu into staging (2023-02-03 09:30:45 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230203

for you to fetch changes up to bb18151d8bd9bedc497ee9d4e8d81b39a4e5bbf6:

target/arm: Enable FEAT_FGT on '-cpu max' (2023-02-03 12:59:24 +0000)

----------------------------------------------------------------
target-arm queue:
 * Fix physical address resolution for Stage2
 * pl011: refactoring, implement reset method
 * Support GICv3 with hvf acceleration
 * sbsa-ref: remove cortex-a76 from list of supported cpus
 * Correct syndrome for ATS12NSO* traps at Secure EL1
 * Fix priority of HSTR_EL2 traps vs UNDEFs
 * Implement FEAT_FGT for '-cpu max'

----------------------------------------------------------------
Alexander Graf (3):
      hvf: arm: Add support for GICv3
      hw/arm/virt: Consolidate GIC finalize logic
      hw/arm/virt: Make accels in GIC finalize logic explicit

Evgeny Iakovlev (4):
      hw/char/pl011: refactor FIFO depth handling code
      hw/char/pl011: add post_load hook for backwards-compatibility
      hw/char/pl011: implement a reset method
      hw/char/pl011: better handling of FIFO flags on LCR reset

Marcin Juszkiewicz (1):
      sbsa-ref: remove cortex-a76 from list of supported cpus

Peter Maydell (23):
      target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly
      target/arm: Correct syndrome for ATS12NSO* at Secure EL1
      target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}
      target/arm: Move do_coproc_insn() syndrome calculation earlier
      target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
      target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
      target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
      target/arm: Define the FEAT_FGT registers
      target/arm: Implement FGT trapping infrastructure
      target/arm: Mark up sysregs for HFGRTR bits 0..11
      target/arm: Mark up sysregs for HFGRTR bits 12..23
      target/arm: Mark up sysregs for HFGRTR bits 24..35
      target/arm: Mark up sysregs for HFGRTR bits 36..63
      target/arm: Mark up sysregs for HDFGRTR bits 0..11
      target/arm: Mark up sysregs for HDFGRTR bits 12..63
      target/arm: Mark up sysregs for HFGITR bits 0..11
      target/arm: Mark up sysregs for HFGITR bits 12..17
      target/arm: Mark up sysregs for HFGITR bits 18..47
      target/arm: Mark up sysregs for HFGITR bits 48..63
      target/arm: Implement the HFGITR_EL2.ERET trap
      target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
      target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
      target/arm: Enable FEAT_FGT on '-cpu max'

Richard Henderson (2):
      hw/arm: Use TYPE_ARM_SMMUV3
      target/arm: Fix physical address resolution for Stage2

From: Richard Henderson <richard.henderson@linaro.org>

Use the macro instead of two explicit string literals.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230124232059.4017615-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/sbsa-ref.c | 3 ++-
 hw/arm/virt.c     | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/hwaddr.h"
 #include "kvm_arm.h"
 #include "hw/arm/boot.h"
+#include "hw/arm/smmuv3.h"
 #include "hw/block/flash.h"
 #include "hw/boards.h"
 #include "hw/ide/internal.h"
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
     DeviceState *dev;
     int i;
 
-    dev = qdev_new("arm-smmuv3");
+    dev = qdev_new(TYPE_ARM_SMMUV3);
 
     object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
                              &error_abort);
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
         return;
     }
 
-    dev = qdev_new("arm-smmuv3");
+    dev = qdev_new(TYPE_ARM_SMMUV3);
 
     object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
                              &error_abort);
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Conversion to probe_access_full missed applying the page offset.

Cc: qemu-stable@nongnu.org
Reported-by: Sid Manning <sidneym@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230126233134.103193-1-richard.henderson@linaro.org
Fixes: f3639a64f602 ("target/arm: Use softmmu tlbs for page table walking")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
         if (unlikely(flags & TLB_INVALID_MASK)) {
             goto fail;
         }
-        ptw->out_phys = full->phys_addr;
+        ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK);
         ptw->out_rw = full->prot & PAGE_WRITE;
         pte_attrs = full->pte_attrs;
         pte_secure = full->attrs.secure;
-- 
2.34.1

From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>

PL011 can be in either of 2 modes depending guest config: FIFO and
single register. The last mode could be viewed as a 1-element-deep FIFO.

Current code open-codes a bunch of depth-dependent logic. Refactor FIFO
depth handling code to isolate calculating current FIFO depth.

One functional (albeit guest-invisible) side-effect of this change is
that previously we would always increment s->read_pos in UARTDR read
handler even if FIFO was disabled, now we are limiting read_pos to not
exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO).

Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230123162304.26254-2-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/char/pl011.h |  5 ++++-
 hw/char/pl011.c         | 30 ++++++++++++++++++------------
 2 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/pl011.h
+++ b/include/hw/char/pl011.h
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011)
 /* This shares the same struct (and cast macro) as the base pl011 device */
 #define TYPE_PL011_LUMINARY "pl011_luminary"
 
+/* Depth of UART FIFO in bytes, when FIFO mode is enabled (else depth == 1) */
+#define PL011_FIFO_DEPTH 16
+
 struct PL011State {
     SysBusDevice parent_obj;
 
@@ -XXX,XX +XXX,XX @@ struct PL011State {
     uint32_t dmacr;
     uint32_t int_enabled;
     uint32_t int_level;
-    uint32_t read_fifo[16];
+    uint32_t read_fifo[PL011_FIFO_DEPTH];
     uint32_t ilpr;
     uint32_t ibrd;
     uint32_t fbrd;
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -XXX,XX +XXX,XX @@ static void pl011_update(PL011State *s)
     }
 }
 
+static bool pl011_is_fifo_enabled(PL011State *s)
+{
+    return (s->lcr & 0x10) != 0;
+}
+
+static inline unsigned pl011_get_fifo_depth(PL011State *s)
+{
+    /* Note: FIFO depth is expected to be power-of-2 */
+    return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
+}
+
 static uint64_t pl011_read(void *opaque, hwaddr offset,
                            unsigned size)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
         c = s->read_fifo[s->read_pos];
         if (s->read_count > 0) {
             s->read_count--;
-            if (++s->read_pos == 16)
-                s->read_pos = 0;
+            s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1);
         }
         if (s->read_count == 0) {
             s->flags |= PL011_FLAG_RXFE;
@@ -XXX,XX +XXX,XX @@ static int pl011_can_receive(void *opaque)
     PL011State *s = (PL011State *)opaque;
     int r;
 
-    if (s->lcr & 0x10) {
-        r = s->read_count < 16;
-    } else {
-        r = s->read_count < 1;
-    }
+    r = s->read_count < pl011_get_fifo_depth(s);
     trace_pl011_can_receive(s->lcr, s->read_count, r);
     return r;
 }
@@ -XXX,XX +XXX,XX @@ static void pl011_put_fifo(void *opaque, uint32_t value)
 {
     PL011State *s = (PL011State *)opaque;
     int slot;
+    unsigned pipe_depth;
 
-    slot = s->read_pos + s->read_count;
-    if (slot >= 16)
-        slot -= 16;
+    pipe_depth = pl011_get_fifo_depth(s);
+    slot = (s->read_pos + s->read_count) & (pipe_depth - 1);
     s->read_fifo[slot] = value;
     s->read_count++;
     s->flags &= ~PL011_FLAG_RXFE;
     trace_pl011_put_fifo(value, s->read_count);
-    if (!(s->lcr & 0x10) || s->read_count == 16) {
+    if (s->read_count == pipe_depth) {
         trace_pl011_put_fifo_full();
         s->flags |= PL011_FLAG_RXFF;
     }
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011 = {
         VMSTATE_UINT32(dmacr, PL011State),
         VMSTATE_UINT32(int_enabled, PL011State),
         VMSTATE_UINT32(int_level, PL011State),
-        VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16),
+        VMSTATE_UINT32_ARRAY(read_fifo, PL011State, PL011_FIFO_DEPTH),
         VMSTATE_UINT32(ilpr, PL011State),
         VMSTATE_UINT32(ibrd, PL011State),
         VMSTATE_UINT32(fbrd, PL011State),
-- 
2.34.1

From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>

Previous change slightly modified the way we handle data writes when
FIFO is disabled. Previously we kept incrementing read_pos and were
storing data at that position, although we only have a
single-register-deep FIFO now. Then we changed it to always store data
at pos 0.

If guest disables FIFO and the proceeds to read data, it will work out
fine, because we still read from current read_pos before setting it to
0.

However, to make code less fragile, introduce a post_load hook for
PL011State and move fixup read FIFO state when FIFO is disabled. Since
we are introducing a post_load hook, also do some sanity checking on
untrusted incoming input state.

Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Message-id: 20230123162304.26254-3-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/pl011.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011_clock = {
     }
 };
 
+static int pl011_post_load(void *opaque, int version_id)
+{
+    PL011State* s = opaque;
+
+    /* Sanity-check input state */
+    if (s->read_pos >= ARRAY_SIZE(s->read_fifo) ||
+        s->read_count > ARRAY_SIZE(s->read_fifo)) {
+        return -1;
+    }
+
+    if (!pl011_is_fifo_enabled(s) && s->read_count > 0 && s->read_pos > 0) {
+        /*
+         * Older versions of PL011 didn't ensure that the single
+         * character in the FIFO in FIFO-disabled mode is in
+         * element 0 of the array; convert to follow the current
+         * code's assumptions.
+         */
+        s->read_fifo[0] = s->read_fifo[s->read_pos];
+        s->read_pos = 0;
+    }
+
+    return 0;
+}
+
 static const VMStateDescription vmstate_pl011 = {
     .name = "pl011",
     .version_id = 2,
     .minimum_version_id = 2,
+    .post_load = pl011_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(readbuff, PL011State),
         VMSTATE_UINT32(flags, PL011State),
-- 
2.34.1

From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>

PL011 currently lacks a reset method. Implement it.

Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230123162304.26254-4-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/pl011.c | 26 +++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -XXX,XX +XXX,XX @@ static void pl011_init(Object *obj)
     s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s,
                                 ClockUpdate);
 
-    s->read_trigger = 1;
-    s->ifl = 0x12;
-    s->cr = 0x300;
-    s->flags = 0x90;
-
     s->id = pl011_id_arm;
 }
 
@@ -XXX,XX +XXX,XX @@ static void pl011_realize(DeviceState *dev, Error **errp)
                              pl011_event, NULL, s, NULL, true);
 }
 
+static void pl011_reset(DeviceState *dev)
+{
+    PL011State *s = PL011(dev);
+
+    s->lcr = 0;
+    s->rsr = 0;
+    s->dmacr = 0;
+    s->int_enabled = 0;
+    s->int_level = 0;
+    s->ilpr = 0;
+    s->ibrd = 0;
+    s->fbrd = 0;
+    s->read_pos = 0;
+    s->read_count = 0;
+    s->read_trigger = 1;
+    s->ifl = 0x12;
+    s->cr = 0x300;
+    s->flags = 0x90;
+}
+
 static void pl011_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
     dc->realize = pl011_realize;
+    dc->reset = pl011_reset;
     dc->vmsd = &vmstate_pl011;
     device_class_set_props(dc, pl011_properties);
 }
-- 
2.34.1

From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>

Current FIFO handling code does not reset RXFE/RXFF flags when guest
resets FIFO by writing to UARTLCR register, although internal FIFO state
is reset to 0 read count. Actual guest-visible flag update will happen
only on next data read or write attempt. As a result of that any guest
that expects RXFE flag to be set (and RXFF to be cleared) after resetting
FIFO will never see that happen.

Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230123162304.26254-5-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/pl011.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -XXX,XX +XXX,XX @@ static inline unsigned pl011_get_fifo_depth(PL011State *s)
     return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
 }
 
+static inline void pl011_reset_fifo(PL011State *s)
+{
+    s->read_count = 0;
+    s->read_pos = 0;
+
+    /* Reset FIFO flags */
+    s->flags &= ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF);
+    s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE;
+}
+
 static uint64_t pl011_read(void *opaque, hwaddr offset,
                            unsigned size)
 {
@@ -XXX,XX +XXX,XX @@ static void pl011_write(void *opaque, hwaddr offset,
     case 11: /* UARTLCR_H */
         /* Reset the FIFO state on FIFO enable or disable */
         if ((s->lcr ^ value) & 0x10) {
-            s->read_count = 0;
-            s->read_pos = 0;
+            pl011_reset_fifo(s);
         }
         if ((s->lcr ^ value) & 0x1) {
             int break_enable = value & 0x1;
@@ -XXX,XX +XXX,XX @@ static void pl011_reset(DeviceState *dev)
     s->ilpr = 0;
     s->ibrd = 0;
     s->fbrd = 0;
-    s->read_pos = 0;
-    s->read_count = 0;
     s->read_trigger = 1;
     s->ifl = 0x12;
     s->cr = 0x300;
-    s->flags = 0x90;
+    s->flags = 0;
+    pl011_reset_fifo(s);
 }
 
 static void pl011_class_init(ObjectClass *oc, void *data)
-- 
2.34.1

From: Alexander Graf <agraf@csgraf.de>

We currently only support GICv2 emulation. To also support GICv3, we will
need to pass a few system registers into their respective handler functions.

This patch adds support for HVF to call into the TCG callbacks for GICv3
system register handlers. This is safe because the GICv3 TCG code is generic
as long as we limit ourselves to EL0 and EL1 - which are the only modes
supported by HVF.

To make sure nobody trips over that, we also annotate callbacks that don't
work in HVF mode, such as EL state change hooks.

With GICv3 support in place, we can run with more than 8 vCPUs.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Message-id: 20230128224459.70676-1-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c   |  16 +++-
 target/arm/hvf/hvf.c        | 151 ++++++++++++++++++++++++++++++++++++
 target/arm/hvf/trace-events |   2 +
 3 files changed, 168 insertions(+), 1 deletion(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/irq.h"
 #include "cpu.h"
 #include "target/arm/cpregs.h"
+#include "sysemu/tcg.h"
+#include "sysemu/qtest.h"
 
 /*
  * Special case return value from hppvi_index(); must be larger than
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
          * which case we'd get the wrong value.
          * So instead we define the regs with no ri->opaque info, and
          * get back to the GICv3CPUState from the CPUARMState.
+         *
+         * These CP regs callbacks can be called from either TCG or HVF code.
          */
         define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
 
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
                 define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo);
             }
         }
-        arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs);
+        if (tcg_enabled() || qtest_enabled()) {
+            /*
+             * We can only trap EL changes with TCG. However the GIC interrupt
+             * state only changes on EL changes involving EL2 or EL3, so for
+             * the non-TCG case this is OK, as EL2 and EL3 can't exist.
+             */
+            arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs);
+        } else {
+            assert(!arm_feature(&cpu->env, ARM_FEATURE_EL2));
+            assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3));
+        }
     }
 }
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@
 #define SYSREG_PMCCNTR_EL0    SYSREG(3, 3, 9, 13, 0)
 #define SYSREG_PMCCFILTR_EL0  SYSREG(3, 3, 14, 15, 7)
 
+#define SYSREG_ICC_AP0R0_EL1     SYSREG(3, 0, 12, 8, 4)
+#define SYSREG_ICC_AP0R1_EL1     SYSREG(3, 0, 12, 8, 5)
+#define SYSREG_ICC_AP0R2_EL1     SYSREG(3, 0, 12, 8, 6)
+#define SYSREG_ICC_AP0R3_EL1     SYSREG(3, 0, 12, 8, 7)
+#define SYSREG_ICC_AP1R0_EL1     SYSREG(3, 0, 12, 9, 0)
+#define SYSREG_ICC_AP1R1_EL1     SYSREG(3, 0, 12, 9, 1)
+#define SYSREG_ICC_AP1R2_EL1     SYSREG(3, 0, 12, 9, 2)
+#define SYSREG_ICC_AP1R3_EL1     SYSREG(3, 0, 12, 9, 3)
+#define SYSREG_ICC_ASGI1R_EL1    SYSREG(3, 0, 12, 11, 6)
+#define SYSREG_ICC_BPR0_EL1      SYSREG(3, 0, 12, 8, 3)
+#define SYSREG_ICC_BPR1_EL1      SYSREG(3, 0, 12, 12, 3)
+#define SYSREG_ICC_CTLR_EL1      SYSREG(3, 0, 12, 12, 4)
+#define SYSREG_ICC_DIR_EL1       SYSREG(3, 0, 12, 11, 1)
+#define SYSREG_ICC_EOIR0_EL1     SYSREG(3, 0, 12, 8, 1)
+#define SYSREG_ICC_EOIR1_EL1     SYSREG(3, 0, 12, 12, 1)
+#define SYSREG_ICC_HPPIR0_EL1    SYSREG(3, 0, 12, 8, 2)
+#define SYSREG_ICC_HPPIR1_EL1    SYSREG(3, 0, 12, 12, 2)
+#define SYSREG_ICC_IAR0_EL1      SYSREG(3, 0, 12, 8, 0)
+#define SYSREG_ICC_IAR1_EL1      SYSREG(3, 0, 12, 12, 0)
+#define SYSREG_ICC_IGRPEN0_EL1   SYSREG(3, 0, 12, 12, 6)
+#define SYSREG_ICC_IGRPEN1_EL1   SYSREG(3, 0, 12, 12, 7)
+#define SYSREG_ICC_PMR_EL1       SYSREG(3, 0, 4, 6, 0)
+#define SYSREG_ICC_RPR_EL1       SYSREG(3, 0, 12, 11, 3)
+#define SYSREG_ICC_SGI0R_EL1     SYSREG(3, 0, 12, 11, 7)
+#define SYSREG_ICC_SGI1R_EL1     SYSREG(3, 0, 12, 11, 5)
+#define SYSREG_ICC_SRE_EL1       SYSREG(3, 0, 12, 12, 5)
+
 #define WFX_IS_WFE (1 << 0)
 
 #define TMR_CTL_ENABLE  (1 << 0)
@@ -XXX,XX +XXX,XX @@ static bool is_id_sysreg(uint32_t reg)
            SYSREG_CRM(reg) < 8;
 }
 
+static uint32_t hvf_reg2cp_reg(uint32_t reg)
+{
+    return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
+                              (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
+                              (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK,
+                              (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK,
+                              (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK,
+                              (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK);
+}
+
+static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    CPUARMState *env = &arm_cpu->env;
+    const ARMCPRegInfo *ri;
+
+    ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
+    if (ri) {
+        if (ri->accessfn) {
+            if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) {
+                return false;
+            }
+        }
+        if (ri->type & ARM_CP_CONST) {
+            *val = ri->resetvalue;
+        } else if (ri->readfn) {
+            *val = ri->readfn(env, ri);
+        } else {
+            *val = CPREG_FIELD64(env, ri);
+        }
+        trace_hvf_vgic_read(ri->name, *val);
+        return true;
+    }
+
+    return false;
+}
+
 static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
 {
     ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
     case SYSREG_OSDLR_EL1:
         /* Dummy register */
         break;
+    case SYSREG_ICC_AP0R0_EL1:
+    case SYSREG_ICC_AP0R1_EL1:
+    case SYSREG_ICC_AP0R2_EL1:
+    case SYSREG_ICC_AP0R3_EL1:
+    case SYSREG_ICC_AP1R0_EL1:
+    case SYSREG_ICC_AP1R1_EL1:
+    case SYSREG_ICC_AP1R2_EL1:
+    case SYSREG_ICC_AP1R3_EL1:
+    case SYSREG_ICC_ASGI1R_EL1:
+    case SYSREG_ICC_BPR0_EL1:
+    case SYSREG_ICC_BPR1_EL1:
+    case SYSREG_ICC_DIR_EL1:
+    case SYSREG_ICC_EOIR0_EL1:
+    case SYSREG_ICC_EOIR1_EL1:
+    case SYSREG_ICC_HPPIR0_EL1:
+    case SYSREG_ICC_HPPIR1_EL1:
+    case SYSREG_ICC_IAR0_EL1:
+    case SYSREG_ICC_IAR1_EL1:
+    case SYSREG_ICC_IGRPEN0_EL1:
+    case SYSREG_ICC_IGRPEN1_EL1:
+    case SYSREG_ICC_PMR_EL1:
+    case SYSREG_ICC_SGI0R_EL1:
+    case SYSREG_ICC_SGI1R_EL1:
+    case SYSREG_ICC_SRE_EL1:
+    case SYSREG_ICC_CTLR_EL1:
+        /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
+        if (!hvf_sysreg_read_cp(cpu, reg, &val)) {
+            hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
+        }
+        break;
     default:
         if (is_id_sysreg(reg)) {
             /* ID system registers read as RES0 */
@@ -XXX,XX +XXX,XX @@ static void pmswinc_write(CPUARMState *env, uint64_t value)
     }
 }
 
+static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    CPUARMState *env = &arm_cpu->env;
+    const ARMCPRegInfo *ri;
+
+    ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
+
+    if (ri) {
+        if (ri->accessfn) {
+            if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) {
+                return false;
+            }
+        }
+        if (ri->writefn) {
+            ri->writefn(env, ri, val);
+        } else {
+            CPREG_FIELD64(env, ri) = val;
+        }
+
+        trace_hvf_vgic_write(ri->name, val);
+        return true;
+    }
+
+    return false;
+}
+
 static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
 {
     ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
     case SYSREG_OSDLR_EL1:
         /* Dummy register */
         break;
+    case SYSREG_ICC_AP0R0_EL1:
+    case SYSREG_ICC_AP0R1_EL1:
+    case SYSREG_ICC_AP0R2_EL1:
+    case SYSREG_ICC_AP0R3_EL1:
+    case SYSREG_ICC_AP1R0_EL1:
+    case SYSREG_ICC_AP1R1_EL1:
+    case SYSREG_ICC_AP1R2_EL1:
+    case SYSREG_ICC_AP1R3_EL1:
+    case SYSREG_ICC_ASGI1R_EL1:
+    case SYSREG_ICC_BPR0_EL1:
+    case SYSREG_ICC_BPR1_EL1:
+    case SYSREG_ICC_CTLR_EL1:
+    case SYSREG_ICC_DIR_EL1:
+    case SYSREG_ICC_EOIR0_EL1:
+    case SYSREG_ICC_EOIR1_EL1:
+    case SYSREG_ICC_HPPIR0_EL1:
+    case SYSREG_ICC_HPPIR1_EL1:
+    case SYSREG_ICC_IAR0_EL1:
+    case SYSREG_ICC_IAR1_EL1:
+    case SYSREG_ICC_IGRPEN0_EL1:
+    case SYSREG_ICC_IGRPEN1_EL1:
+    case SYSREG_ICC_PMR_EL1:
+    case SYSREG_ICC_SGI0R_EL1:
+    case SYSREG_ICC_SGI1R_EL1:
+    case SYSREG_ICC_SRE_EL1:
+        /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
+        if (!hvf_sysreg_write_cp(cpu, reg, val)) {
+            hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
+        }
+        break;
     default:
         cpu_synchronize_state(cpu);
         trace_hvf_unhandled_sysreg_write(env->pc, reg,
diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/hvf/trace-events
+++ b/target/arm/hvf/trace-events
@@ -XXX,XX +XXX,XX @@ hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64
 hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64
 hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]"
 hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpu=0x%x"
+hvf_vgic_write(const char *name, uint64_t val) "vgic write to %s [val=0x%016"PRIx64"]"
+hvf_vgic_read(const char *name, uint64_t val) "vgic read from %s [val=0x%016"PRIx64"]"
-- 
2.34.1

From: Alexander Graf <agraf@csgraf.de>

Up to now, the finalize_gic_version() code open coded what is essentially
a support bitmap match between host/emulation environment and desired
target GIC type.

This open coding leads to undesirable side effects. For example, a VM with
KVM and -smp 10 will automatically choose GICv3 while the same command
line with TCG will stay on GICv2 and fail the launch.

This patch combines the TCG and KVM matching code paths by making
everything a 2 pass process. First, we determine which GIC versions the
current environment is able to support, then we go through a single
state machine to determine which target GIC mode that means for us.

After this patch, the only user noticable changes should be consolidated
error messages as well as TCG -M virt supporting -smp > 8 automatically.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Message-id: 20221223090107.98888-2-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h |  15 ++--
 hw/arm/virt.c         | 198 ++++++++++++++++++++++--------------------
 2 files changed, 112 insertions(+), 101 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@ typedef enum VirtMSIControllerType {
 } VirtMSIControllerType;
 
 typedef enum VirtGICType {
-    VIRT_GIC_VERSION_MAX,
-    VIRT_GIC_VERSION_HOST,
-    VIRT_GIC_VERSION_2,
-    VIRT_GIC_VERSION_3,
-    VIRT_GIC_VERSION_4,
+    VIRT_GIC_VERSION_MAX = 0,
+    VIRT_GIC_VERSION_HOST = 1,
+    /* The concrete GIC values have to match the GIC version number */
+    VIRT_GIC_VERSION_2 = 2,
+    VIRT_GIC_VERSION_3 = 3,
+    VIRT_GIC_VERSION_4 = 4,
     VIRT_GIC_VERSION_NOSEL,
 } VirtGICType;
 
+#define VIRT_GIC_VERSION_2_MASK BIT(VIRT_GIC_VERSION_2)
+#define VIRT_GIC_VERSION_3_MASK BIT(VIRT_GIC_VERSION_3)
+#define VIRT_GIC_VERSION_4_MASK BIT(VIRT_GIC_VERSION_4)
+
 struct VirtMachineClass {
     MachineClass parent;
     bool disallow_affinity_adjustment;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
     }
 }
 
+static VirtGICType finalize_gic_version_do(const char *accel_name,
+                                           VirtGICType gic_version,
+                                           int gics_supported,
+                                           unsigned int max_cpus)
+{
+    /* Convert host/max/nosel to GIC version number */
+    switch (gic_version) {
+    case VIRT_GIC_VERSION_HOST:
+        if (!kvm_enabled()) {
+            error_report("gic-version=host requires KVM");
+            exit(1);
+        }
+
+        /* For KVM, gic-version=host means gic-version=max */
+        return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
+                                       gics_supported, max_cpus);
+    case VIRT_GIC_VERSION_MAX:
+        if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
+            gic_version = VIRT_GIC_VERSION_4;
+        } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
+            gic_version = VIRT_GIC_VERSION_3;
+        } else {
+            gic_version = VIRT_GIC_VERSION_2;
+        }
+        break;
+    case VIRT_GIC_VERSION_NOSEL:
+        if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
+            max_cpus <= GIC_NCPU) {
+            gic_version = VIRT_GIC_VERSION_2;
+        } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
+            /*
+             * in case the host does not support v2 emulation or
+             * the end-user requested more than 8 VCPUs we now default
+             * to v3. In any case defaulting to v2 would be broken.
+             */
+            gic_version = VIRT_GIC_VERSION_3;
+        } else if (max_cpus > GIC_NCPU) {
+            error_report("%s only supports GICv2 emulation but more than 8 "
+                         "vcpus are requested", accel_name);
+            exit(1);
+        }
+        break;
+    case VIRT_GIC_VERSION_2:
+    case VIRT_GIC_VERSION_3:
+    case VIRT_GIC_VERSION_4:
+        break;
+    }
+
+    /* Check chosen version is effectively supported */
+    switch (gic_version) {
+    case VIRT_GIC_VERSION_2:
+        if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
+            error_report("%s does not support GICv2 emulation", accel_name);
+            exit(1);
+        }
+        break;
+    case VIRT_GIC_VERSION_3:
+        if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
+            error_report("%s does not support GICv3 emulation", accel_name);
+            exit(1);
+        }
+        break;
+    case VIRT_GIC_VERSION_4:
+        if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
+            error_report("%s does not support GICv4 emulation, is virtualization=on?",
+                         accel_name);
+            exit(1);
+        }
+        break;
+    default:
+        error_report("logic error in finalize_gic_version");
+        exit(1);
+        break;
+    }
+
+    return gic_version;
+}
+
 /*
  * finalize_gic_version - Determines the final gic_version
  * according to the gic-version property
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
  */
 static void finalize_gic_version(VirtMachineState *vms)
 {
+    const char *accel_name = current_accel_name();
     unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
+    int gics_supported = 0;
 
-    if (kvm_enabled()) {
-        int probe_bitmap;
+    /* Determine which GIC versions the current environment supports */
+    if (kvm_enabled() && kvm_irqchip_in_kernel()) {
+        int probe_bitmap = kvm_arm_vgic_probe();
 
-        if (!kvm_irqchip_in_kernel()) {
-            switch (vms->gic_version) {
-            case VIRT_GIC_VERSION_HOST:
-                warn_report(
-                    "gic-version=host not relevant with kernel-irqchip=off "
-                     "as only userspace GICv2 is supported. Using v2 ...");
-                return;
-            case VIRT_GIC_VERSION_MAX:
-            case VIRT_GIC_VERSION_NOSEL:
-                vms->gic_version = VIRT_GIC_VERSION_2;
-                return;
-            case VIRT_GIC_VERSION_2:
-                return;
-            case VIRT_GIC_VERSION_3:
-                error_report(
-                    "gic-version=3 is not supported with kernel-irqchip=off");
-                exit(1);
-            case VIRT_GIC_VERSION_4:
-                error_report(
-                    "gic-version=4 is not supported with kernel-irqchip=off");
-                exit(1);
-            }
-        }
-
-        probe_bitmap = kvm_arm_vgic_probe();
         if (!probe_bitmap) {
             error_report("Unable to determine GIC version supported by host");
             exit(1);
         }
 
-        switch (vms->gic_version) {
-        case VIRT_GIC_VERSION_HOST:
-        case VIRT_GIC_VERSION_MAX:
-            if (probe_bitmap & KVM_ARM_VGIC_V3) {
-                vms->gic_version = VIRT_GIC_VERSION_3;
-            } else {
-                vms->gic_version = VIRT_GIC_VERSION_2;
-            }
-            return;
-        case VIRT_GIC_VERSION_NOSEL:
-            if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
-                vms->gic_version = VIRT_GIC_VERSION_2;
-            } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
-                /*
-                 * in case the host does not support v2 in-kernel emulation or
-                 * the end-user requested more than 8 VCPUs we now default
-                 * to v3. In any case defaulting to v2 would be broken.
-                 */
-                vms->gic_version = VIRT_GIC_VERSION_3;
-            } else if (max_cpus > GIC_NCPU) {
-                error_report("host only supports in-kernel GICv2 emulation "
-                             "but more than 8 vcpus are requested");
-                exit(1);
-            }
-            break;
-        case VIRT_GIC_VERSION_2:
-        case VIRT_GIC_VERSION_3:
-            break;
-        case VIRT_GIC_VERSION_4:
-            error_report("gic-version=4 is not supported with KVM");
-            exit(1);
+        if (probe_bitmap & KVM_ARM_VGIC_V2) {
+            gics_supported |= VIRT_GIC_VERSION_2_MASK;
         }
-
-        /* Check chosen version is effectively supported by the host */
-        if (vms->gic_version == VIRT_GIC_VERSION_2 &&
-            !(probe_bitmap & KVM_ARM_VGIC_V2)) {
-            error_report("host does not support in-kernel GICv2 emulation");
-            exit(1);
-        } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
-                   !(probe_bitmap & KVM_ARM_VGIC_V3)) {
-            error_report("host does not support in-kernel GICv3 emulation");
-            exit(1);
+        if (probe_bitmap & KVM_ARM_VGIC_V3) {
+            gics_supported |= VIRT_GIC_VERSION_3_MASK;
         }
-        return;
-    }
-
-    /* TCG mode */
-    switch (vms->gic_version) {
-    case VIRT_GIC_VERSION_NOSEL:
-        vms->gic_version = VIRT_GIC_VERSION_2;
-        break;
-    case VIRT_GIC_VERSION_MAX:
+    } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
+        /* KVM w/o kernel irqchip can only deal with GICv2 */
+        gics_supported |= VIRT_GIC_VERSION_2_MASK;
+        accel_name = "KVM with kernel-irqchip=off";
+    } else {
+        gics_supported |= VIRT_GIC_VERSION_2_MASK;
         if (module_object_class_by_name("arm-gicv3")) {
-            /* CONFIG_ARM_GICV3_TCG was set */
+            gics_supported |= VIRT_GIC_VERSION_3_MASK;
             if (vms->virt) {
                 /* GICv4 only makes sense if CPU has EL2 */
-                vms->gic_version = VIRT_GIC_VERSION_4;
-            } else {
-                vms->gic_version = VIRT_GIC_VERSION_3;
+                gics_supported |= VIRT_GIC_VERSION_4_MASK;
             }
-        } else {
-            vms->gic_version = VIRT_GIC_VERSION_2;
         }
-        break;
-    case VIRT_GIC_VERSION_HOST:
-        error_report("gic-version=host requires KVM");
-        exit(1);
-    case VIRT_GIC_VERSION_4:
-        if (!vms->virt) {
-            error_report("gic-version=4 requires virtualization enabled");
-            exit(1);
-        }
-        break;
-    case VIRT_GIC_VERSION_2:
-    case VIRT_GIC_VERSION_3:
-        break;
     }
+
+    /*
+     * Then convert helpers like host/max to concrete GIC versions and ensure
+     * the desired version is supported
+     */
+    vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
+                                               gics_supported, max_cpus);
 }
 
 /*
-- 
2.34.1

From: Alexander Graf <agraf@csgraf.de>

Let's explicitly list out all accelerators that we support when trying to
determine the supported set of GIC versions. KVM was already separate, so
the only missing one is HVF which simply reuses all of TCG's emulation
code and thus has the same compatibility matrix.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221223090107.98888-3-agraf@csgraf.de
[PMM: Added qtest to the list of accelerators]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/numa.h"
 #include "sysemu/runstate.h"
 #include "sysemu/tpm.h"
+#include "sysemu/tcg.h"
 #include "sysemu/kvm.h"
 #include "sysemu/hvf.h"
+#include "sysemu/qtest.h"
 #include "hw/loader.h"
 #include "qapi/error.h"
 #include "qemu/bitops.h"
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
         /* KVM w/o kernel irqchip can only deal with GICv2 */
         gics_supported |= VIRT_GIC_VERSION_2_MASK;
         accel_name = "KVM with kernel-irqchip=off";
-    } else {
+    } else if (tcg_enabled() || hvf_enabled() || qtest_enabled())  {
         gics_supported |= VIRT_GIC_VERSION_2_MASK;
         if (module_object_class_by_name("arm-gicv3")) {
             gics_supported |= VIRT_GIC_VERSION_3_MASK;
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
                 gics_supported |= VIRT_GIC_VERSION_4_MASK;
             }
         }
+    } else {
+        error_report("Unsupported accelerator, can not determine GIC support");
+        exit(1);
     }
 
     /*
-- 
2.34.1

The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT
S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name
them AT S1E1R and AT S1E1W (which are entirely different
instructions).  Fix the names.

(This has no guest-visible effect as the names are for debug purposes
only.)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
 
 #ifndef CONFIG_USER_ONLY
 static const ARMCPRegInfo ats1e1_reginfo[] = {
-    { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
+    { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
       .writefn = ats_write64 },
-    { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
+    { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
       .writefn = ats_write64 },
-- 
2.34.1

The AArch32 ATS12NSO* address translation operations are supposed to
trap to either EL2 or EL3 if they're executed at Secure EL1 (which
can only happen if EL3 is AArch64).  We implement this, but we got
the syndrome value wrong: like other traps to EL2 or EL3 on an
AArch32 cpreg access, they should report the 0x3 syndrome, not the
0x0 'uncategorized' syndrome.  This is clear in the access pseudocode
for these instructions.

Fix the syndrome value for these operations by correcting the
returned value from the ats_access() function.

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
         if (arm_current_el(env) == 1) {
             if (arm_is_secure_below_el3(env)) {
                 if (env->cp15.scr_el3 & SCR_EEL2) {
-                    return CP_ACCESS_TRAP_UNCATEGORIZED_EL2;
+                    return CP_ACCESS_TRAP_EL2;
                 }
-                return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
+                return CP_ACCESS_TRAP_EL3;
             }
             return CP_ACCESS_TRAP_UNCATEGORIZED;
         }
-- 
2.34.1

We added the CPAccessResult values CP_ACCESS_TRAP_UNCATEGORIZED_EL2
and CP_ACCESS_TRAP_UNCATEGORIZED_EL3 purely in order to use them in
the ats_access() function, but doing so was incorrect (a bug fixed in
a previous commit).  There aren't any cases where we want an access
function to be able to request a trap to EL2 or EL3 with a zero
syndrome value, so remove these enum values.

As well as cleaning up dead code, the motivation here is that
we'd like to implement fine-grained-trap handling in
helper_access_check_cp_reg(). Although the fine-grained traps
to EL2 are always lower priority than trap-to-same-EL and
higher priority than trap-to-EL3, they are in the middle of
various other kinds of trap-to-EL2. Knowing that a trap-to-EL2
must always for us have the same syndrome (ie that an access
function will return CP_ACCESS_TRAP_EL2 and there is no other
kind of trap-to-EL2 enum value) means we don't have to try
to choose which of the two syndrome values to report if the
access would trap to EL2 both for the fine-grained-trap and
because the access function requires it.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum CPAccessResult {
      * Access fails and results in an exception syndrome 0x0 ("uncategorized").
      * Note that this is not a catch-all case -- the set of cases which may
      * result in this failure is specifically defined by the architecture.
+     * This trap is always to the usual target EL, never directly to a
+     * specified target EL.
      */
     CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
 } CPAccessResult;
 
 typedef struct ARMCPRegInfo ARMCPRegInfo;
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
     case CP_ACCESS_TRAP:
         break;
     case CP_ACCESS_TRAP_UNCATEGORIZED:
+        /* Only CP_ACCESS_TRAP traps are direct to a specified EL */
+        assert((res & CP_ACCESS_EL_MASK) == 0);
         if (cpu_isar_feature(aa64_ids, cpu) && isread &&
             arm_cpreg_in_idspace(ri)) {
             /*
-- 
2.34.1

Rearrange the code in do_coproc_insn() so that we calculate the
syndrome value for a potential trap early; we're about to add a
second check that wants this value earlier than where it is currently
determined.

(Specifically, a trap to EL2 because of HSTR_EL2 should take
priority over an UNDEF to EL1, even when the UNDEF is because
the register does not exist at all or because its ri->access
bits non-configurably fail the access. So the check we put in
for HSTR_EL2 trapping at EL1 (which needs the syndrome) is
going to have to be done before the check "is the ARMCPRegInfo
pointer NULL".)

This commit is just code motion; the change to HSTR_EL2
handling that will use the 'syndrome' variable is in a
subsequent commit.

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
     const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key);
     TCGv_ptr tcg_ri = NULL;
     bool need_exit_tb;
+    uint32_t syndrome;
+
+    /*
+     * Note that since we are an implementation which takes an
+     * exception on a trapped conditional instruction only if the
+     * instruction passes its condition code check, we can take
+     * advantage of the clause in the ARM ARM that allows us to set
+     * the COND field in the instruction to 0xE in all cases.
+     * We could fish the actual condition out of the insn (ARM)
+     * or the condexec bits (Thumb) but it isn't necessary.
+     */
+    switch (cpnum) {
+    case 14:
+        if (is64) {
+            syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
+                                         isread, false);
+        } else {
+            syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
+                                        rt, isread, false);
+        }
+        break;
+    case 15:
+        if (is64) {
+            syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
+                                         isread, false);
+        } else {
+            syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
+                                        rt, isread, false);
+        }
+        break;
+    default:
+        /*
+         * ARMv8 defines that only coprocessors 14 and 15 exist,
+         * so this can only happen if this is an ARMv7 or earlier CPU,
+         * in which case the syndrome information won't actually be
+         * guest visible.
+         */
+        assert(!arm_dc_feature(s, ARM_FEATURE_V8));
+        syndrome = syn_uncategorized();
+        break;
+    }
 
     if (!ri) {
         /*
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
          * Note that on XScale all cp0..c13 registers do an access check
          * call in order to handle c15_cpar.
          */
-        uint32_t syndrome;
-
-        /*
-         * Note that since we are an implementation which takes an
-         * exception on a trapped conditional instruction only if the
-         * instruction passes its condition code check, we can take
-         * advantage of the clause in the ARM ARM that allows us to set
-         * the COND field in the instruction to 0xE in all cases.
-         * We could fish the actual condition out of the insn (ARM)
-         * or the condexec bits (Thumb) but it isn't necessary.
-         */
-        switch (cpnum) {
-        case 14:
-            if (is64) {
-                syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
-                                             isread, false);
-            } else {
-                syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
-                                            rt, isread, false);
-            }
-            break;
-        case 15:
-            if (is64) {
-                syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
-                                             isread, false);
-            } else {
-                syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
-                                            rt, isread, false);
-            }
-            break;
-        default:
-            /*
-             * ARMv8 defines that only coprocessors 14 and 15 exist,
-             * so this can only happen if this is an ARMv7 or earlier CPU,
-             * in which case the syndrome information won't actually be
-             * guest visible.
-             */
-            assert(!arm_dc_feature(s, ARM_FEATURE_V8));
-            syndrome = syn_uncategorized();
-            break;
-        }
-
         gen_set_condexec(s);
         gen_update_pc(s, 0);
         tcg_ri = tcg_temp_new_ptr();
-- 
2.34.1

The HSTR_EL2 register has a collection of trap bits which allow
trapping to EL2 for AArch32 EL0 or EL1 accesses to coprocessor
registers.  The specification of these bits is that when the bit is
set we should trap
 * EL1 accesses
 * EL0 accesses, if the access is not UNDEFINED when the
   trap bit is 0

In other words, all UNDEF traps from EL0 to EL1 take precedence over
the HSTR_EL2 trap to EL2.  (Since this is all AArch32, the only kind
of trap-to-EL1 is the UNDEF.)

Our implementation doesn't quite get this right -- we check for traps
in the order:
 * no such register
 * ARMCPRegInfo::access bits
 * HSTR_EL2 trap bits
 * ARMCPRegInfo::accessfn

So UNDEFs that happen because of the access bits or because the
register doesn't exist at all correctly take priority over the
HSTR_EL2 trap, but where a register can UNDEF at EL0 because of the
accessfn we are incorrectly always taking the HSTR_EL2 trap.  There
aren't many of these, but one example is the PMCR; if you look at the
access pseudocode for this register you can see that UNDEFs taken
because of the value of PMUSERENR.EN are checked before the HSTR_EL2
bit.

Rearrange helper_access_check_cp_reg() so that we always call the
accessfn, and use its return value if it indicates that the access
traps to EL0 rather than continuing to do the HSTR_EL2 check.

The semantics of HSTR_EL2 require that it traps cpreg accesses
to EL2 for:
 * EL1 accesses
 * EL0 accesses, if the access is not UNDEFINED when the
   trap bit is 0

(You can see this in the I_ZFGJP priority ordering, where HSTR_EL2
traps from EL1 to EL2 are priority 12, UNDEFs are priority 13, and
HSTR_EL2 traps from EL0 are priority 15.)

However, we don't get this right for EL1 accesses which UNDEF because
the register doesn't exist at all or because its ri->access bits
non-configurably forbid the access.  At EL1, check for the HSTR_EL2
trap early, before either of these UNDEF reasons.

We have to retain the HSTR_EL2 check in access_check_cp_reg(),
because at EL0 any kind of UNDEF-to-EL1 (including "no such
register", "bad ri->access" and "ri->accessfn returns 'trap to EL1'")
takes precedence over the trap to EL2.  But we only need to do that
check for EL0 now.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230130182459.3309057-7-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-7-peter.maydell@linaro.org
---
 target/arm/op_helper.c |  6 +++++-
 target/arm/translate.c | 28 +++++++++++++++++++++++++++-
 2 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
         goto fail;
     }
 
-    if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 &&
+    /*
+     * HSTR_EL2 traps from EL1 are checked earlier, in generated code;
+     * we only need to check here for traps from EL0.
+     */
+    if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
         (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
         uint32_t mask = 1 << ri->crn;
 
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
         break;
     }
 
+    if (s->hstr_active && cpnum == 15 && s->current_el == 1) {
+        /*
+         * At EL1, check for a HSTR_EL2 trap, which must take precedence
+         * over the UNDEF for "no such register" or the UNDEF for "access
+         * permissions forbid this EL1 access". HSTR_EL2 traps from EL0
+         * only happen if the cpreg doesn't UNDEF at EL0, so we do those in
+         * access_check_cp_reg(), after the checks for whether the access
+         * configurably trapped to EL1.
+         */
+        uint32_t maskbit = is64 ? crm : crn;
+
+        if (maskbit != 4 && maskbit != 14) {
+            /* T4 and T14 are RES0 so never cause traps */
+            TCGv_i32 t;
+            DisasLabel over = gen_disas_label(s);
+
+            t = load_cpu_offset(offsetoflow32(CPUARMState, cp15.hstr_el2));
+            tcg_gen_andi_i32(t, t, 1u << maskbit);
+            tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label);
+            tcg_temp_free_i32(t);
+
+            gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
+            set_disas_label(s, over);
+        }
+    }
+
     if (!ri) {
         /*
          * Unknown register; this might be a guest error or a QEMU
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
         return;
     }
 
-    if (s->hstr_active || ri->accessfn ||
+    if ((s->hstr_active && s->current_el == 0) || ri->accessfn ||
         (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
         /*
          * Emit code to perform further access permissions checks at
-- 
2.34.1

The HSTR_EL2 register is not supposed to have an effect unless EL2 is
enabled in the current security state.  We weren't checking for this,
which meant that if the guest set up the HSTR_EL2 register we would
incorrectly trap even for accesses from Secure EL0 and EL1.

Add the missing checks. (Other places where we look at HSTR_EL2
for the not-in-v8A bits TTEE and TJDBX are already checking that
we are in NS EL0 or EL1, so there we alredy know EL2 is enabled.)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
         DP_TBFLAG_A32(flags, VFPEN, 1);
     }
 
-    if (el < 2 && env->cp15.hstr_el2 &&
+    if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
         (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
         DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
     }
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
      * we only need to check here for traps from EL0.
      */
     if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
+        arm_is_el2_enabled(env) &&
         (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
         uint32_t mask = 1 << ri->crn;
 
-- 
2.34.1

Define the system registers which are provided by the
FEAT_FGT fine-grained trap architectural feature:
 HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2

All these registers are a set of bit fields, where each bit is set
for a trap and clear to not trap on a particular system register
access.  The R and W register pairs are for system registers,
allowing trapping to be done separately for reads and writes; the I
register is for system instructions where trapping is on instruction
execution.

The data storage in the CPU state struct is arranged as a set of
arrays rather than separate fields so that when we're looking up the
bits for a system register access we can just index into the array
rather than having to use a switch to select a named struct member.
The later FEAT_FGT2 will add extra elements to these arrays.

The field definitions for the new registers are in cpregs.h because
in practice the code that needs them is code that also needs
the cpregs information; cpu.h is included in a lot more files.
We're also going to add some FGT-specific definitions to cpregs.h
in the next commit.

We do not implement HAFGRTR_EL2, because we don't implement
FEAT_AMUv1.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum CPAccessResult {
     CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
 } CPAccessResult;
 
+/* Indexes into fgt_read[] */
+#define FGTREG_HFGRTR 0
+#define FGTREG_HDFGRTR 1
+/* Indexes into fgt_write[] */
+#define FGTREG_HFGWTR 0
+#define FGTREG_HDFGWTR 1
+/* Indexes into fgt_exec[] */
+#define FGTREG_HFGITR 0
+
+FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1)
+FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1)
+FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1)
+FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1)
+FIELD(HFGRTR_EL2, APDAKEY, 4, 1)
+FIELD(HFGRTR_EL2, APDBKEY, 5, 1)
+FIELD(HFGRTR_EL2, APGAKEY, 6, 1)
+FIELD(HFGRTR_EL2, APIAKEY, 7, 1)
+FIELD(HFGRTR_EL2, APIBKEY, 8, 1)
+FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1)
+FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1)
+FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1)
+FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1)
+FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1)
+FIELD(HFGRTR_EL2, CTR_EL0, 14, 1)
+FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1)
+FIELD(HFGRTR_EL2, ESR_EL1, 16, 1)
+FIELD(HFGRTR_EL2, FAR_EL1, 17, 1)
+FIELD(HFGRTR_EL2, ISR_EL1, 18, 1)
+FIELD(HFGRTR_EL2, LORC_EL1, 19, 1)
+FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1)
+FIELD(HFGRTR_EL2, LORID_EL1, 21, 1)
+FIELD(HFGRTR_EL2, LORN_EL1, 22, 1)
+FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1)
+FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1)
+FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1)
+FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1)
+FIELD(HFGRTR_EL2, PAR_EL1, 27, 1)
+FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1)
+FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1)
+FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1)
+FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1)
+FIELD(HFGRTR_EL2, TCR_EL1, 32, 1)
+FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1)
+FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1)
+FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1)
+FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1)
+FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1)
+FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1)
+FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1)
+FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1)
+FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1)
+FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1)
+FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1)
+FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1)
+FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1)
+FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1)
+FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1)
+FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1)
+FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1)
+FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1)
+/* 51-53: RES0 */
+FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1)
+FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1)
+/* 56-63: RES0 */
+
+/* These match HFGRTR but bits for RO registers are RES0 */
+FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1)
+FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1)
+FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1)
+FIELD(HFGWTR_EL2, APDAKEY, 4, 1)
+FIELD(HFGWTR_EL2, APDBKEY, 5, 1)
+FIELD(HFGWTR_EL2, APGAKEY, 6, 1)
+FIELD(HFGWTR_EL2, APIAKEY, 7, 1)
+FIELD(HFGWTR_EL2, APIBKEY, 8, 1)
+FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1)
+FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1)
+FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1)
+FIELD(HFGWTR_EL2, ESR_EL1, 16, 1)
+FIELD(HFGWTR_EL2, FAR_EL1, 17, 1)
+FIELD(HFGWTR_EL2, LORC_EL1, 19, 1)
+FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1)
+FIELD(HFGWTR_EL2, LORN_EL1, 22, 1)
+FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1)
+FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1)
+FIELD(HFGWTR_EL2, PAR_EL1, 27, 1)
+FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1)
+FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1)
+FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1)
+FIELD(HFGWTR_EL2, TCR_EL1, 32, 1)
+FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1)
+FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1)
+FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1)
+FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1)
+FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1)
+FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1)
+FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1)
+FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1)
+FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1)
+FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1)
+FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1)
+FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1)
+FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1)
+FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1)
+FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1)
+FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1)
+FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1)
+
+FIELD(HFGITR_EL2, ICIALLUIS, 0, 1)
+FIELD(HFGITR_EL2, ICIALLU, 1, 1)
+FIELD(HFGITR_EL2, ICIVAU, 2, 1)
+FIELD(HFGITR_EL2, DCIVAC, 3, 1)
+FIELD(HFGITR_EL2, DCISW, 4, 1)
+FIELD(HFGITR_EL2, DCCSW, 5, 1)
+FIELD(HFGITR_EL2, DCCISW, 6, 1)
+FIELD(HFGITR_EL2, DCCVAU, 7, 1)
+FIELD(HFGITR_EL2, DCCVAP, 8, 1)
+FIELD(HFGITR_EL2, DCCVADP, 9, 1)
+FIELD(HFGITR_EL2, DCCIVAC, 10, 1)
+FIELD(HFGITR_EL2, DCZVA, 11, 1)
+FIELD(HFGITR_EL2, ATS1E1R, 12, 1)
+FIELD(HFGITR_EL2, ATS1E1W, 13, 1)
+FIELD(HFGITR_EL2, ATS1E0R, 14, 1)
+FIELD(HFGITR_EL2, ATS1E0W, 15, 1)
+FIELD(HFGITR_EL2, ATS1E1RP, 16, 1)
+FIELD(HFGITR_EL2, ATS1E1WP, 17, 1)
+FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1)
+FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1)
+FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1)
+FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1)
+FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1)
+FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1)
+FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1)
+FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1)
+FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1)
+FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1)
+FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1)
+FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1)
+FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1)
+FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1)
+FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1)
+FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1)
+FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1)
+FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1)
+FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1)
+FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1)
+FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1)
+FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1)
+FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1)
+FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1)
+FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1)
+FIELD(HFGITR_EL2, TLBIVAE1, 43, 1)
+FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1)
+FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1)
+FIELD(HFGITR_EL2, TLBIVALE1, 46, 1)
+FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1)
+FIELD(HFGITR_EL2, CFPRCTX, 48, 1)
+FIELD(HFGITR_EL2, DVPRCTX, 49, 1)
+FIELD(HFGITR_EL2, CPPRCTX, 50, 1)
+FIELD(HFGITR_EL2, ERET, 51, 1)
+FIELD(HFGITR_EL2, SVC_EL0, 52, 1)
+FIELD(HFGITR_EL2, SVC_EL1, 53, 1)
+FIELD(HFGITR_EL2, DCCVAC, 54, 1)
+FIELD(HFGITR_EL2, NBRBINJ, 55, 1)
+FIELD(HFGITR_EL2, NBRBIALL, 56, 1)
+
+FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1)
+FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1)
+FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1)
+FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1)
+FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1)
+FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1)
+FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1)
+FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1)
+/* 8: RES0: OSLAR_EL1 is WO */
+FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1)
+FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1)
+FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1)
+FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1)
+FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1)
+FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1)
+FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1)
+FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1)
+FIELD(HDFGRTR_EL2, PMINTEN, 17, 1)
+FIELD(HDFGRTR_EL2, PMOVS, 18, 1)
+FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1)
+/* 20: RES0: PMSWINC_EL0 is WO */
+/* 21: RES0: PMCR_EL0 is WO */
+FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1)
+FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1)
+FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1)
+FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1)
+FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1)
+FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1)
+FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1)
+FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1)
+FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1)
+FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1)
+FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1)
+FIELD(HDFGRTR_EL2, TRC, 33, 1)
+FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1)
+FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1)
+FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1)
+FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1)
+/* 38, 39: RES0 */
+FIELD(HDFGRTR_EL2, TRCID, 40, 1)
+FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1)
+/* 42: RES0: TRCOSLAR is WO */
+FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1)
+FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1)
+FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1)
+FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1)
+FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1)
+FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1)
+/* 49: RES0: TRFCR_EL1 is WO */
+FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1)
+FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1)
+FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1)
+FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1)
+FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1)
+FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1)
+FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1)
+FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1)
+FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1)
+FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1)
+FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1)
+FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1)
+FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1)
+FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1)
+
+/*
+ * These match HDFGRTR_EL2, but bits for RO registers are RES0.
+ * A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0.
+ */
+FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1)
+FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1)
+FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1)
+FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1)
+FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1)
+FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1)
+FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1)
+FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1)
+FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1)
+FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1)
+FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1)
+FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1)
+FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1)
+FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1)
+FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1)
+FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1)
+FIELD(HDFGWTR_EL2, PMINTEN, 17, 1)
+FIELD(HDFGWTR_EL2, PMOVS, 18, 1)
+FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1)
+FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1)
+FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1)
+FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1)
+FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1)
+FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1)
+FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1)
+FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1)
+FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1)
+FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1)
+FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1)
+FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1)
+FIELD(HDFGWTR_EL2, TRC, 33, 1)
+FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1)
+FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1)
+FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1)
+FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1)
+FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1)
+FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1)
+FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1)
+FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1)
+FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1)
+FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1)
+FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1)
+FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1)
+FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1)
+FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1)
+FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1)
+FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1)
+FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1)
+FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
+FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
+FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
+
 typedef struct ARMCPRegInfo ARMCPRegInfo;
 
 /*
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
         uint64_t disr_el1;
         uint64_t vdisr_el2;
         uint64_t vsesr_el2;
+
+        /*
+         * Fine-Grained Trap registers. We store these as arrays so the
+         * access checking code doesn't have to manually select
+         * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test.
+         * FEAT_FGT2 will add more elements to these arrays.
+         */
+        uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
+        uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */
+        uint64_t fgt_exec[1]; /* HFGITR */
     } cp15;
 
     struct {
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
     return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
 }
 
+static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
+}
+
 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         if (cpu_isar_feature(aa64_hcx, cpu)) {
             valid_mask |= SCR_HXEN;
         }
+        if (cpu_isar_feature(aa64_fgt, cpu)) {
+            valid_mask |= SCR_FGTEN;
+        }
     } else {
         valid_mask &= ~(SCR_RW | SCR_ST);
         if (cpu_isar_feature(aa32_ras, cpu)) {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
       .access = PL3_RW,
       .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
 };
+
+static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri,
+                                 bool isread)
+{
+    if (arm_current_el(env) == 2 &&
+        arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_FGTEN)) {
+        return CP_ACCESS_TRAP_EL3;
+    }
+    return CP_ACCESS_OK;
+}
+
+static const ARMCPRegInfo fgt_reginfo[] = {
+    { .name = "HFGRTR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
+      .access = PL2_RW, .accessfn = access_fgt,
+      .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR]) },
+    { .name = "HFGWTR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 5,
+      .access = PL2_RW, .accessfn = access_fgt,
+      .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]) },
+    { .name = "HDFGRTR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 4,
+      .access = PL2_RW, .accessfn = access_fgt,
+      .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]) },
+    { .name = "HDFGWTR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 5,
+      .access = PL2_RW, .accessfn = access_fgt,
+      .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR]) },
+    { .name = "HFGITR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 6,
+      .access = PL2_RW, .accessfn = access_fgt,
+      .fieldoffset = offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR]) },
+};
 #endif /* TARGET_AARCH64 */
 
 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     if (cpu_isar_feature(aa64_scxtnum, cpu)) {
         define_arm_cp_regs(cpu, scxtnum_reginfo);
     }
+
+    if (cpu_isar_feature(aa64_fgt, cpu)) {
+        define_arm_cp_regs(cpu, fgt_reginfo);
+    }
 #endif
 
     if (cpu_isar_feature(any_predinv, cpu)) {
-- 
2.34.1

Implement the machinery for fine-grained traps on normal sysregs.
Any sysreg with a fine-grained trap will set the new field to
indicate which FGT register bit it should trap on.

FGT traps only happen when an AArch64 EL2 enables them for
an AArch64 EL1. They therefore are only relevant for AArch32
cpregs when the cpreg can be accessed from EL0. The logic
in access_check_cp_reg() will check this, so it is safe to
add a .fgt marking to an ARM_CP_STATE_BOTH ARMCPRegInfo.

The DO_BIT and DO_REV_BIT macros define enum constants FGT_##bitname
which can be used to specify the FGT bit, eg
   .fgt = FGT_AFSR0_EL1
(We assume that there is no bit name duplication across the FGT
registers, for brevity's sake.)

Subsequent commits will add the .fgt fields to the relevant register
definitions and define the FGT_nnn values for them.

Note that some of the FGT traps are for instructions that we don't
handle via the cpregs mechanisms (mostly these are instruction traps).
Those we will have to handle separately.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-10-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-10-peter.maydell@linaro.org
---
 target/arm/cpregs.h        | 72 ++++++++++++++++++++++++++++++++++++++
 target/arm/cpu.h           |  1 +
 target/arm/internals.h     | 20 +++++++++++
 target/arm/translate.h     |  2 ++
 target/arm/helper.c        |  9 +++++
 target/arm/op_helper.c     | 30 ++++++++++++++++
 target/arm/translate-a64.c |  3 +-
 target/arm/translate.c     |  2 ++
 8 files changed, 138 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
 FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
 FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
 
+/* Which fine-grained trap bit register to check, if any */
+FIELD(FGT, TYPE, 10, 3)
+FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */
+FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */
+FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */
+
+/*
+ * Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::fgt
+ * fields. We assume for brevity's sake that there are no duplicated
+ * bit names across the various FGT registers.
+ */
+#define DO_BIT(REG, BITNAME)                                    \
+    FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT
+
+/* Some bits have reversed sense, so 0 means trap and 1 means not */
+#define DO_REV_BIT(REG, BITNAME)                                        \
+    FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT
+
+typedef enum FGTBit {
+    /*
+     * These bits tell us which register arrays to use:
+     * if FGT_R is set then reads are checked against fgt_read[];
+     * if FGT_W is set then writes are checked against fgt_write[];
+     * if FGT_EXEC is set then all accesses are checked against fgt_exec[].
+     *
+     * For almost all bits in the R/W register pairs, the bit exists in
+     * both registers for a RW register, in HFGRTR/HDFGRTR for a RO register
+     * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa
+     * for a WO register. There are unfortunately a couple of exceptions
+     * (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but
+     * the FGT system only allows trapping of writes, not reads.
+     *
+     * Note that we arrange these bits so that a 0 FGTBit means "no trap".
+     */
+    FGT_R = 1 << R_FGT_TYPE_SHIFT,
+    FGT_W = 2 << R_FGT_TYPE_SHIFT,
+    FGT_EXEC = 4 << R_FGT_TYPE_SHIFT,
+    FGT_RW = FGT_R | FGT_W,
+    /* Bit to identify whether trap bit is reversed sense */
+    FGT_REV = R_FGT_REV_MASK,
+
+    /*
+     * If a bit exists in HFGRTR/HDFGRTR then either the register being
+     * trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either
+     * want to trap for both reads and writes or else it's harmless to mark
+     * it as trap-on-writes.
+     * If a bit exists only in HFGWTR/HDFGWTR then either the register being
+     * trapped is WO, or else it is one of the two oddball special cases
+     * which are RW but have only a write trap. We mark these as only
+     * FGT_W so we get the right behaviour for those special cases.
+     * (If a bit was added in future that provided only a read trap for an
+     * RW register we'd need to do something special to get the FGT_R bit
+     * only. But this seems unlikely to happen.)
+     *
+     * So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if
+     * the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGWTR.
+     */
+    FGT_HFGRTR = FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT),
+    FGT_HFGWTR = FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT),
+    FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
+    FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
+    FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
+} FGTBit;
+
+#undef DO_BIT
+#undef DO_REV_BIT
+
 typedef struct ARMCPRegInfo ARMCPRegInfo;
 
 /*
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
     CPAccessRights access;
     /* Security state: ARM_CP_SECSTATE_* bits/values */
     CPSecureState secure;
+    /*
+     * Which fine-grained trap register bit to check, if any. This
+     * value encodes both the trap register and bit within it.
+     */
+    FGTBit fgt;
     /*
      * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
      * this register was defined: can be used to hand data through to the
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
+FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
 
 /*
  * Bit usage when in AArch32 state, both A- and M-profile.
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
     ((1 << (1 - 1)) | (1 << (2 - 1)) |                  \
      (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1)))
 
+/*
+ * Return true if it is possible to take a fine-grained-trap to EL2.
+ */
+static inline bool arm_fgt_active(CPUARMState *env, int el)
+{
+    /*
+     * The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps
+     * that can affect EL0, but it is harmless to do the test also for
+     * traps on registers that are only accessible at EL1 because if the test
+     * returns true then we can't be executing at EL1 anyway.
+     * FGT traps only happen when EL2 is enabled and EL1 is AArch64;
+     * traps from AArch32 only happen for the EL0 is AArch32 case.
+     */
+    return cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
+        el < 2 && arm_is_el2_enabled(env) &&
+        arm_el_is_aa64(env, 1) &&
+        (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE) &&
+        (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN));
+}
+
 #endif
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     bool is_nonstreaming;
     /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
     bool mve_no_pred;
+    /* True if fine-grained traps are active */
+    bool fgt_active;
     /*
      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
      *  < 0, set by the current instruction.
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
     if (arm_singlestep_active(env)) {
         DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
     }
+
     return flags;
 }
 
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
         DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
     }
 
+    if (arm_fgt_active(env, el)) {
+        DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
+    }
+
     if (env->uncached_cpsr & CPSR_IL) {
         DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
     }
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
         DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
     }
 
+    if (arm_fgt_active(env, el)) {
+        DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
+    }
+
     if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
         /*
          * Set MTE_ACTIVE if any access may be Checked, and leave clear
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
         }
     }
 
+    /*
+     * Fine-grained traps also are lower priority than undef-to-EL1,
+     * higher priority than trap-to-EL3, and we don't care about priority
+     * order with other EL2 traps because the syndrome value is the same.
+     */
+    if (arm_fgt_active(env, arm_current_el(env))) {
+        uint64_t trapword = 0;
+        unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX);
+        unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS);
+        bool rev = FIELD_EX32(ri->fgt, FGT, REV);
+        bool trapbit;
+
+        if (ri->fgt & FGT_EXEC) {
+            assert(idx < ARRAY_SIZE(env->cp15.fgt_exec));
+            trapword = env->cp15.fgt_exec[idx];
+        } else if (isread && (ri->fgt & FGT_R)) {
+            assert(idx < ARRAY_SIZE(env->cp15.fgt_read));
+            trapword = env->cp15.fgt_read[idx];
+        } else if (!isread && (ri->fgt & FGT_W)) {
+            assert(idx < ARRAY_SIZE(env->cp15.fgt_write));
+            trapword = env->cp15.fgt_write[idx];
+        }
+
+        trapbit = extract64(trapword, bitpos, 1);
+        if (trapbit != rev) {
+            res = CP_ACCESS_TRAP_EL2;
+            goto fail;
+        }
+    }
+
     if (likely(res == CP_ACCESS_OK)) {
         return ri;
     }
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
         return;
     }
 
-    if (ri->accessfn) {
+    if (ri->accessfn || (ri->fgt && s->fgt_active)) {
         /* Emit code to perform further access permissions checks at
          * runtime; this may result in an exception.
          */
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
+    dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
     dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
     dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
     dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
     }
 
     if ((s->hstr_active && s->current_el == 0) || ri->accessfn ||
+        (ri->fgt && s->fgt_active) ||
         (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
         /*
          * Emit code to perform further access permissions checks at
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
+    dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
 
     if (arm_feature(env, ARM_FEATURE_M)) {
         dc->vfp_enabled = 1;
-- 
2.34.1

Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 0..11.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
     FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
     FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
+
+    /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */
+    DO_BIT(HFGRTR, AFSR0_EL1),
+    DO_BIT(HFGRTR, AFSR1_EL1),
+    DO_BIT(HFGRTR, AIDR_EL1),
+    DO_BIT(HFGRTR, AMAIR_EL1),
+    DO_BIT(HFGRTR, APDAKEY),
+    DO_BIT(HFGRTR, APDBKEY),
+    DO_BIT(HFGRTR, APGAKEY),
+    DO_BIT(HFGRTR, APIAKEY),
+    DO_BIT(HFGRTR, APIBKEY),
+    DO_BIT(HFGRTR, CCSIDR_EL1),
+    DO_BIT(HFGRTR, CLIDR_EL1),
+    DO_BIT(HFGRTR, CONTEXTIDR_EL1),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_CONTEXTIDR_EL1,
       .secure = ARM_CP_SECSTATE_NS,
       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
       .access = PL1_R,
       .accessfn = access_tid4,
+      .fgt = FGT_CCSIDR_EL1,
       .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
       .access = PL1_R, .type = ARM_CP_CONST,
       .accessfn = access_aa64_tid1,
+      .fgt = FGT_AIDR_EL1,
       .resetvalue = 0 },
     /*
      * Auxiliary fault status registers: these also are IMPDEF, and we
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_AFSR0_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_AFSR1_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     /*
      * MAIR can just read-as-written because we don't implement caches
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_AMAIR_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
     { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APDAKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apda.lo) },
     { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APDAKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apda.hi) },
     { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APDBKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) },
     { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APDBKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) },
     { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APGAKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apga.lo) },
     { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APGAKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apga.hi) },
     { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APIAKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apia.lo) },
     { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APIAKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apia.hi) },
     { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APIBKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apib.lo) },
     { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APIBKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
 };
 
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
             .access = PL1_R, .type = ARM_CP_CONST,
             .accessfn = access_tid4,
+            .fgt = FGT_CLIDR_EL1,
             .resetvalue = cpu->clidr
         };
         define_one_arm_cp_reg(cpu, &clidr);
-- 
2.34.1

Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 12..23.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HFGRTR, CCSIDR_EL1),
     DO_BIT(HFGRTR, CLIDR_EL1),
     DO_BIT(HFGRTR, CONTEXTIDR_EL1),
+    DO_BIT(HFGRTR, CPACR_EL1),
+    DO_BIT(HFGRTR, CSSELR_EL1),
+    DO_BIT(HFGRTR, CTR_EL0),
+    DO_BIT(HFGRTR, DCZID_EL0),
+    DO_BIT(HFGRTR, ESR_EL1),
+    DO_BIT(HFGRTR, FAR_EL1),
+    DO_BIT(HFGRTR, ISR_EL1),
+    DO_BIT(HFGRTR, LORC_EL1),
+    DO_BIT(HFGRTR, LOREA_EL1),
+    DO_BIT(HFGRTR, LORID_EL1),
+    DO_BIT(HFGRTR, LORN_EL1),
+    DO_BIT(HFGRTR, LORSA_EL1),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
+      .fgt = FGT_CPACR_EL1,
       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
       .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
 };
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
       .access = PL1_RW,
       .accessfn = access_tid4,
+      .fgt = FGT_CSSELR_EL1,
       .writefn = csselr_write, .resetvalue = 0,
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
                              offsetof(CPUARMState, cp15.csselr_ns) } },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .resetfn = arm_cp_reset_ignore },
     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
+      .fgt = FGT_ISR_EL1,
       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
     /* 32 bit ITLB invalidates */
     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_FAR_EL1,
       .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
       .resetvalue = 0, },
 };
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_ESR_EL1,
       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
       .access = PL0_R, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_DCZID_EL0,
       .readfn = aa64_dczid_read },
     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
     { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_lor_other,
+      .fgt = FGT_LORSA_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_lor_other,
+      .fgt = FGT_LOREA_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_lor_other,
+      .fgt = FGT_LORN_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
       .access = PL1_RW, .accessfn = access_lor_other,
+      .fgt = FGT_LORC_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
       .access = PL1_R, .accessfn = access_lor_ns,
+      .fgt = FGT_LORID_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
 };
 
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
               .access = PL0_R, .accessfn = ctr_el0_access,
+              .fgt = FGT_CTR_EL0,
               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
             { .name = "TCMTR",
-- 
2.34.1

Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 24..35.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HFGRTR, LORID_EL1),
     DO_BIT(HFGRTR, LORN_EL1),
     DO_BIT(HFGRTR, LORSA_EL1),
+    DO_BIT(HFGRTR, MAIR_EL1),
+    DO_BIT(HFGRTR, MIDR_EL1),
+    DO_BIT(HFGRTR, MPIDR_EL1),
+    DO_BIT(HFGRTR, PAR_EL1),
+    DO_BIT(HFGRTR, REVIDR_EL1),
+    DO_BIT(HFGRTR, SCTLR_EL1),
+    DO_BIT(HFGRTR, SCXTNUM_EL1),
+    DO_BIT(HFGRTR, SCXTNUM_EL0),
+    DO_BIT(HFGRTR, TCR_EL1),
+    DO_BIT(HFGRTR, TPIDR_EL1),
+    DO_BIT(HFGRTR, TPIDRRO_EL0),
+    DO_BIT(HFGRTR, TPIDR_EL0),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_MAIR_EL1,
       .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
       .resetvalue = 0 },
     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
       .access = PL0_RW,
+      .fgt = FGT_TPIDR_EL0,
       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
       .access = PL0_RW,
+      .fgt = FGT_TPIDR_EL0,
       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
       .resetfn = arm_cp_reset_ignore },
     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
       .access = PL0_R | PL1_W,
+      .fgt = FGT_TPIDRRO_EL0,
       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
       .resetvalue = 0},
     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
       .access = PL0_R | PL1_W,
+      .fgt = FGT_TPIDRRO_EL0,
       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
       .resetfn = arm_cp_reset_ignore },
     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
       .access = PL1_RW,
+      .fgt = FGT_TPIDR_EL1,
       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
       .access = PL1_RW,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_TCR_EL1,
       .writefn = vmsa_tcr_el12_write,
       .raw_writefn = raw_write,
       .resetvalue = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .type = ARM_CP_ALIAS,
       .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
       .access = PL1_RW, .resetvalue = 0,
+      .fgt = FGT_PAR_EL1,
       .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
       .writefn = par_write },
 #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
     { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
       .access = PL0_RW, .accessfn = access_scxtnum,
+      .fgt = FGT_SCXTNUM_EL0,
       .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
     { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
       .access = PL1_RW, .accessfn = access_scxtnum,
+      .fgt = FGT_SCXTNUM_EL1,
       .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
     { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
+              .fgt = FGT_MIDR_EL1,
               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
               .readfn = midr_read },
             /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
               .access = PL1_R,
               .accessfn = access_aa64_tid1,
+              .fgt = FGT_REVIDR_EL1,
               .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
         };
         ARMCPRegInfo id_v8_midr_alias_cp_reginfo = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         ARMCPRegInfo mpidr_cp_reginfo[] = {
             { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
+              .fgt = FGT_MPIDR_EL1,
               .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
         };
 #ifdef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
             .access = PL1_RW, .accessfn = access_tvm_trvm,
+            .fgt = FGT_SCTLR_EL1,
             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
                                    offsetof(CPUARMState, cp15.sctlr_ns) },
             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
-- 
2.34.1

Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 36..63.

Of these, some correspond to RAS registers which we implement as
always-UNDEF: these don't need any extra handling for FGT because the
UNDEF-to-EL1 always takes priority over any theoretical
FGT-trap-to-EL2.

Bit 50 (NACCDATA_EL1) is for the ACCDATA_EL1 register which is part
of the FEAT_LS64_ACCDATA feature which we don't yet implement.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HFGRTR, TPIDR_EL1),
     DO_BIT(HFGRTR, TPIDRRO_EL0),
     DO_BIT(HFGRTR, TPIDR_EL0),
+    DO_BIT(HFGRTR, TTBR0_EL1),
+    DO_BIT(HFGRTR, TTBR1_EL1),
+    DO_BIT(HFGRTR, VBAR_EL1),
+    DO_BIT(HFGRTR, ICC_IGRPENN_EL1),
+    DO_BIT(HFGRTR, ERRIDR_EL1),
+    DO_REV_BIT(HFGRTR, NSMPRI_EL1),
+    DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 6,
       .type = ARM_CP_IO | ARM_CP_NO_RAW,
       .access = PL1_RW, .accessfn = gicv3_fiq_access,
+      .fgt = FGT_ICC_IGRPENN_EL1,
       .readfn = icc_igrpen_read,
       .writefn = icc_igrpen_write,
     },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7,
       .type = ARM_CP_IO | ARM_CP_NO_RAW,
       .access = PL1_RW, .accessfn = gicv3_irq_access,
+      .fgt = FGT_ICC_IGRPENN_EL1,
       .readfn = icc_igrpen_read,
       .writefn = icc_igrpen_write,
     },
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_TTBR0_EL1,
       .writefn = vmsa_ttbr_write, .resetvalue = 0,
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_TTBR1_EL1,
       .writefn = vmsa_ttbr_write, .resetvalue = 0,
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
@@ -XXX,XX +XXX,XX @@ static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
  *   ERRSELR_EL1
  * may generate UNDEFINED, which is the effect we get by not
  * listing them at all.
+ *
+ * These registers have fine-grained trap bits, but UNDEF-to-EL1
+ * is higher priority than FGT-to-EL2 so we do not need to list them
+ * in order to check for an FGT.
  */
 static const ARMCPRegInfo minimal_ras_reginfo[] = {
     { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo minimal_ras_reginfo[] = {
     { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
       .access = PL1_R, .accessfn = access_terr,
+      .fgt = FGT_ERRIDR_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {
     { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5,
       .access = PL0_RW, .accessfn = access_tpidr2,
+      .fgt = FGT_NTPIDR2_EL0,
       .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) },
     { .name = "SVCR", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {
     { .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4,
       .access = PL1_RW, .accessfn = access_esm,
+      .fgt = FGT_NSMPRI_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
               .access = PL1_RW, .writefn = vbar_write,
+              .fgt = FGT_VBAR_EL1,
               .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
                                      offsetof(CPUARMState, cp15.vbar_ns) },
               .resetvalue = 0 },
-- 
2.34.1

Mark up the sysreg definitons for the registers trapped
by HDFGRTR/HDFGWTR bits 0..11. These cover various debug
related registers.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HFGRTR, ERRIDR_EL1),
     DO_REV_BIT(HFGRTR, NSMPRI_EL1),
     DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
+
+    /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */
+    DO_BIT(HDFGRTR, DBGBCRN_EL1),
+    DO_BIT(HDFGRTR, DBGBVRN_EL1),
+    DO_BIT(HDFGRTR, DBGWCRN_EL1),
+    DO_BIT(HDFGRTR, DBGWVRN_EL1),
+    DO_BIT(HDFGRTR, MDSCR_EL1),
+    DO_BIT(HDFGRTR, DBGCLAIM),
+    DO_BIT(HDFGWTR, OSLAR_EL1),
+    DO_BIT(HDFGRTR, OSLSR_EL1),
+    DO_BIT(HDFGRTR, OSECCR_EL1),
+    DO_BIT(HDFGRTR, OSDLR_EL1),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_tda,
+      .fgt = FGT_MDSCR_EL1,
       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
       .resetvalue = 0 },
     /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
     { .name = "OSECCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
       .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_tda,
+      .fgt = FGT_OSECCR_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     /*
      * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2].  Map all bits as
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
       .access = PL1_W, .type = ARM_CP_NO_RAW,
       .accessfn = access_tdosa,
+      .fgt = FGT_OSLAR_EL1,
       .writefn = oslar_write },
     { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
       .access = PL1_R, .resetvalue = 10,
       .accessfn = access_tdosa,
+      .fgt = FGT_OSLSR_EL1,
       .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
       .access = PL1_RW, .accessfn = access_tdosa,
+      .fgt = FGT_OSDLR_EL1,
       .writefn = osdlr_write,
       .fieldoffset = offsetof(CPUARMState, cp15.osdlr_el1) },
     /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
       .type = ARM_CP_ALIAS,
       .access = PL1_RW, .accessfn = access_tda,
+      .fgt = FGT_DBGCLAIM,
       .writefn = dbgclaimset_write, .readfn = dbgclaimset_read },
     { .name = "DBGCLAIMCLR_EL1", .state = ARM_CP_STATE_BOTH,
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 6,
       .access = PL1_RW, .accessfn = access_tda,
+      .fgt = FGT_DBGCLAIM,
       .writefn = dbgclaimclr_write, .raw_writefn = raw_write,
       .fieldoffset = offsetof(CPUARMState, cp15.dbgclaim) },
 };
@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
             { .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH,
               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
               .access = PL1_RW, .accessfn = access_tda,
+              .fgt = FGT_DBGBVRN_EL1,
               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
               .writefn = dbgbvr_write, .raw_writefn = raw_write
             },
             { .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH,
               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
               .access = PL1_RW, .accessfn = access_tda,
+              .fgt = FGT_DBGBCRN_EL1,
               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
               .writefn = dbgbcr_write, .raw_writefn = raw_write
             },
@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
             { .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH,
               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
               .access = PL1_RW, .accessfn = access_tda,
+              .fgt = FGT_DBGWVRN_EL1,
               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
               .writefn = dbgwvr_write, .raw_writefn = raw_write
             },
             { .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH,
               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
               .access = PL1_RW, .accessfn = access_tda,
+              .fgt = FGT_DBGWCRN_EL1,
               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
               .writefn = dbgwcr_write, .raw_writefn = raw_write
             },
-- 
2.34.1

Mark up the sysreg definitions for the registers trapped
by HDFGRTR/HDFGWTR bits 12..x.

Bits 12..22 and bit 58 are for PMU registers.

The remaining bits in HDFGRTR/HDFGWTR are for traps on
registers that are part of features we don't implement:

Bits 23..32 and 63 : FEAT_SPE
Bits 33..48 : FEAT_ETE
Bits 50..56 : FEAT_TRBE
Bits 59..61 : FEAT_BRBE
Bit 62 : FEAT_SPEv1p2.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HDFGRTR, OSLSR_EL1),
     DO_BIT(HDFGRTR, OSECCR_EL1),
     DO_BIT(HDFGRTR, OSDLR_EL1),
+    DO_BIT(HDFGRTR, PMEVCNTRN_EL0),
+    DO_BIT(HDFGRTR, PMEVTYPERN_EL0),
+    DO_BIT(HDFGRTR, PMCCFILTR_EL0),
+    DO_BIT(HDFGRTR, PMCCNTR_EL0),
+    DO_BIT(HDFGRTR, PMCNTEN),
+    DO_BIT(HDFGRTR, PMINTEN),
+    DO_BIT(HDFGRTR, PMOVS),
+    DO_BIT(HDFGRTR, PMSELR_EL0),
+    DO_BIT(HDFGWTR, PMSWINC_EL0),
+    DO_BIT(HDFGWTR, PMCR_EL0),
+    DO_BIT(HDFGRTR, PMMIR_EL1),
+    DO_BIT(HDFGRTR, PMCEIDN_EL0),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
       .writefn = pmcntenset_write,
       .accessfn = pmreg_access,
+      .fgt = FGT_PMCNTEN,
       .raw_writefn = raw_write },
     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
       .access = PL0_RW, .accessfn = pmreg_access,
+      .fgt = FGT_PMCNTEN,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
       .writefn = pmcntenset_write, .raw_writefn = raw_write },
     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
       .access = PL0_RW,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
       .accessfn = pmreg_access,
+      .fgt = FGT_PMCNTEN,
       .writefn = pmcntenclr_write,
       .type = ARM_CP_ALIAS | ARM_CP_IO },
     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
       .access = PL0_RW, .accessfn = pmreg_access,
+      .fgt = FGT_PMCNTEN,
       .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
       .writefn = pmcntenclr_write },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .access = PL0_RW, .type = ARM_CP_IO,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
       .accessfn = pmreg_access,
+      .fgt = FGT_PMOVS,
       .writefn = pmovsr_write,
       .raw_writefn = raw_write },
     { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
       .access = PL0_RW, .accessfn = pmreg_access,
+      .fgt = FGT_PMOVS,
       .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
       .writefn = pmovsr_write,
       .raw_writefn = raw_write },
     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
       .access = PL0_W, .accessfn = pmreg_access_swinc,
+      .fgt = FGT_PMSWINC_EL0,
       .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .writefn = pmswinc_write },
     { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4,
       .access = PL0_W, .accessfn = pmreg_access_swinc,
+      .fgt = FGT_PMSWINC_EL0,
       .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .writefn = pmswinc_write },
     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
       .access = PL0_RW, .type = ARM_CP_ALIAS,
+      .fgt = FGT_PMSELR_EL0,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
       .accessfn = pmreg_access_selr, .writefn = pmselr_write,
       .raw_writefn = raw_write},
     { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
       .access = PL0_RW, .accessfn = pmreg_access_selr,
+      .fgt = FGT_PMSELR_EL0,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
       .writefn = pmselr_write, .raw_writefn = raw_write, },
     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
+      .fgt = FGT_PMCCNTR_EL0,
       .readfn = pmccntr_read, .writefn = pmccntr_write32,
       .accessfn = pmreg_access_ccntr },
     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
       .access = PL0_RW, .accessfn = pmreg_access_ccntr,
+      .fgt = FGT_PMCCNTR_EL0,
       .type = ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
       .readfn = pmccntr_read, .writefn = pmccntr_write,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7,
       .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
       .access = PL0_RW, .accessfn = pmreg_access,
+      .fgt = FGT_PMCCFILTR_EL0,
       .type = ARM_CP_ALIAS | ARM_CP_IO,
       .resetvalue = 0, },
     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
       .writefn = pmccfiltr_write, .raw_writefn = raw_write,
       .access = PL0_RW, .accessfn = pmreg_access,
+      .fgt = FGT_PMCCFILTR_EL0,
       .type = ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
       .resetvalue = 0, },
     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
       .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .accessfn = pmreg_access,
+      .fgt = FGT_PMEVTYPERN_EL0,
       .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
     { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
       .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .accessfn = pmreg_access,
+      .fgt = FGT_PMEVTYPERN_EL0,
       .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
       .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .accessfn = pmreg_access_xevcntr,
+      .fgt = FGT_PMEVCNTRN_EL0,
       .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
     { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2,
       .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .accessfn = pmreg_access_xevcntr,
+      .fgt = FGT_PMEVCNTRN_EL0,
       .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
       .access = PL0_R | PL1_RW, .accessfn = access_tpm,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .writefn = pmuserenr_write, .raw_writefn = raw_write },
     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_tpm,
+      .fgt = FGT_PMINTEN,
       .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
       .resetvalue = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_tpm,
+      .fgt = FGT_PMINTEN,
       .type = ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
       .writefn = pmintenset_write, .raw_writefn = raw_write,
       .resetvalue = 0x0 },
     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_tpm,
+      .fgt = FGT_PMINTEN,
       .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
       .writefn = pmintenclr_write, },
     { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_tpm,
+      .fgt = FGT_PMINTEN,
       .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
       .writefn = pmintenclr_write },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
     /* PMOVSSET is not implemented in v7 before v7ve */
     { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
       .access = PL0_RW, .accessfn = pmreg_access,
+      .fgt = FGT_PMOVS,
       .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
       .writefn = pmovsset_write,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
     { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
       .access = PL0_RW, .accessfn = pmreg_access,
+      .fgt = FGT_PMOVS,
       .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
       .writefn = pmovsset_write,
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
     ARMCPRegInfo pmcr = {
         .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
         .access = PL0_RW,
+        .fgt = FGT_PMCR_EL0,
         .type = ARM_CP_IO | ARM_CP_ALIAS,
         .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
         .accessfn = pmreg_access, .writefn = pmcr_write,
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
         .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
         .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
         .access = PL0_RW, .accessfn = pmreg_access,
+        .fgt = FGT_PMCR_EL0,
         .type = ARM_CP_IO,
         .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
         .resetvalue = cpu->isar.reset_pmcr_el0,
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
             { .name = pmevcntr_name, .cp = 15, .crn = 14,
               .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
               .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
+              .fgt = FGT_PMEVCNTRN_EL0,
               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
               .accessfn = pmreg_access_xevcntr },
             { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
               .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr,
               .type = ARM_CP_IO,
+              .fgt = FGT_PMEVCNTRN_EL0,
               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
               .raw_readfn = pmevcntr_rawread,
               .raw_writefn = pmevcntr_rawwrite },
             { .name = pmevtyper_name, .cp = 15, .crn = 14,
               .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
               .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
+              .fgt = FGT_PMEVTYPERN_EL0,
               .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
               .accessfn = pmreg_access },
             { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
               .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
+              .fgt = FGT_PMEVTYPERN_EL0,
               .type = ARM_CP_IO,
               .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
               .raw_writefn = pmevtyper_rawwrite },
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
             { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+              .fgt = FGT_PMCEIDN_EL0,
               .resetvalue = extract64(cpu->pmceid0, 32, 32) },
             { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+              .fgt = FGT_PMCEIDN_EL0,
               .resetvalue = extract64(cpu->pmceid1, 32, 32) },
         };
         define_arm_cp_regs(cpu, v81_pmu_regs);
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
             .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH,
             .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6,
             .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+            .fgt = FGT_PMMIR_EL1,
             .resetvalue = 0
         };
         define_one_arm_cp_reg(cpu, &v84_pmmir);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+              .fgt = FGT_PMCEIDN_EL0,
               .resetvalue = extract64(cpu->pmceid0, 0, 32) },
             { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+              .fgt = FGT_PMCEIDN_EL0,
               .resetvalue = cpu->pmceid0 },
             { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+              .fgt = FGT_PMCEIDN_EL0,
               .resetvalue = extract64(cpu->pmceid1, 0, 32) },
             { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+              .fgt = FGT_PMCEIDN_EL0,
               .resetvalue = cpu->pmceid1 },
         };
 #ifdef CONFIG_USER_ONLY
-- 
2.34.1

Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 0..11. These bits cover various
cache maintenance operations.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HDFGWTR, PMCR_EL0),
     DO_BIT(HDFGRTR, PMMIR_EL1),
     DO_BIT(HDFGRTR, PMCEIDN_EL0),
+
+    /* Trap bits in HFGITR_EL2, starting from bit 0 */
+    DO_BIT(HFGITR, ICIALLUIS),
+    DO_BIT(HFGITR, ICIALLU),
+    DO_BIT(HFGITR, ICIVAU),
+    DO_BIT(HFGITR, DCIVAC),
+    DO_BIT(HFGITR, DCISW),
+    DO_BIT(HFGITR, DCCSW),
+    DO_BIT(HFGITR, DCCISW),
+    DO_BIT(HFGITR, DCCVAU),
+    DO_BIT(HFGITR, DCCVAP),
+    DO_BIT(HFGITR, DCCVADP),
+    DO_BIT(HFGITR, DCCIVAC),
+    DO_BIT(HFGITR, DCZVA),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
 #ifndef CONFIG_USER_ONLY
       /* Avoid overhead of an access check that always passes in user-mode */
       .accessfn = aa64_zva_access,
+      .fgt = FGT_DCZVA,
 #endif
     },
     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NOP,
+      .fgt = FGT_ICIALLUIS,
       .accessfn = access_ticab },
     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NOP,
+      .fgt = FGT_ICIALLU,
       .accessfn = access_tocu },
     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NOP,
+      .fgt = FGT_ICIVAU,
       .accessfn = access_tocu },
     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
       .access = PL1_W, .accessfn = aa64_cacheop_poc_access,
+      .fgt = FGT_DCIVAC,
       .type = ARM_CP_NOP },
     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
+      .fgt = FGT_DCISW,
       .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
+      .fgt = FGT_DCCSW,
       .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NOP,
+      .fgt = FGT_DCCVAU,
       .accessfn = access_tocu },
     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NOP,
+      .fgt = FGT_DCCIVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
+      .fgt = FGT_DCCISW,
       .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
     /* TLBI operations */
     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = {
     { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
+      .fgt = FGT_DCCVAP,
       .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
 };
 
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = {
     { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
+      .fgt = FGT_DCCVADP,
       .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
 };
 #endif /*CONFIG_USER_ONLY*/
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
     { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
       .type = ARM_CP_NOP, .access = PL1_W,
+      .fgt = FGT_DCIVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4,
+      .fgt = FGT_DCISW,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
     { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5,
       .type = ARM_CP_NOP, .access = PL1_W,
+      .fgt = FGT_DCIVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6,
+      .fgt = FGT_DCISW,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
     { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4,
+      .fgt = FGT_DCCSW,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
     { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6,
+      .fgt = FGT_DCCSW,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
     { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4,
+      .fgt = FGT_DCCISW,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
     { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
+      .fgt = FGT_DCCISW,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
 };
 
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
     { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCVAP,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCVAP,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCVADP,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCVADP,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCIVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCIVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_GVA", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
 #ifndef CONFIG_USER_ONLY
       /* Avoid overhead of an access check that always passes in user-mode */
       .accessfn = aa64_zva_access,
+      .fgt = FGT_DCZVA,
 #endif
     },
     { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
 #ifndef CONFIG_USER_ONLY
       /* Avoid overhead of an access check that always passes in user-mode */
       .accessfn = aa64_zva_access,
+      .fgt = FGT_DCZVA,
 #endif
     },
 };
-- 
2.34.1

Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 12..17. These bits cover AT address
translation instructions.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HFGITR, DCCVADP),
     DO_BIT(HFGITR, DCCIVAC),
     DO_BIT(HFGITR, DCZVA),
+    DO_BIT(HFGITR, ATS1E1R),
+    DO_BIT(HFGITR, ATS1E1W),
+    DO_BIT(HFGITR, ATS1E0R),
+    DO_BIT(HFGITR, ATS1E0W),
+    DO_BIT(HFGITR, ATS1E1RP),
+    DO_BIT(HFGITR, ATS1E1WP),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+      .fgt = FGT_ATS1E1R,
       .writefn = ats_write64 },
     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+      .fgt = FGT_ATS1E1W,
       .writefn = ats_write64 },
     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+      .fgt = FGT_ATS1E0R,
       .writefn = ats_write64 },
     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+      .fgt = FGT_ATS1E0W,
       .writefn = ats_write64 },
     { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
     { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+      .fgt = FGT_ATS1E1RP,
       .writefn = ats_write64 },
     { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+      .fgt = FGT_ATS1E1WP,
       .writefn = ats_write64 },
 };
 
-- 
2.34.1

Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 18..47. These bits cover TLBI
TLB maintenance instructions.

(If we implemented FEAT_XS we would need to trap some of the
instructions added by that feature using these bits; but we don't
yet, so will need to add the .fgt markup when we do.)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HFGITR, ATS1E0W),
     DO_BIT(HFGITR, ATS1E1RP),
     DO_BIT(HFGITR, ATS1E1WP),
+    DO_BIT(HFGITR, TLBIVMALLE1OS),
+    DO_BIT(HFGITR, TLBIVAE1OS),
+    DO_BIT(HFGITR, TLBIASIDE1OS),
+    DO_BIT(HFGITR, TLBIVAAE1OS),
+    DO_BIT(HFGITR, TLBIVALE1OS),
+    DO_BIT(HFGITR, TLBIVAALE1OS),
+    DO_BIT(HFGITR, TLBIRVAE1OS),
+    DO_BIT(HFGITR, TLBIRVAAE1OS),
+    DO_BIT(HFGITR, TLBIRVALE1OS),
+    DO_BIT(HFGITR, TLBIRVAALE1OS),
+    DO_BIT(HFGITR, TLBIVMALLE1IS),
+    DO_BIT(HFGITR, TLBIVAE1IS),
+    DO_BIT(HFGITR, TLBIASIDE1IS),
+    DO_BIT(HFGITR, TLBIVAAE1IS),
+    DO_BIT(HFGITR, TLBIVALE1IS),
+    DO_BIT(HFGITR, TLBIVAALE1IS),
+    DO_BIT(HFGITR, TLBIRVAE1IS),
+    DO_BIT(HFGITR, TLBIRVAAE1IS),
+    DO_BIT(HFGITR, TLBIRVALE1IS),
+    DO_BIT(HFGITR, TLBIRVAALE1IS),
+    DO_BIT(HFGITR, TLBIRVAE1),
+    DO_BIT(HFGITR, TLBIRVAAE1),
+    DO_BIT(HFGITR, TLBIRVALE1),
+    DO_BIT(HFGITR, TLBIRVAALE1),
+    DO_BIT(HFGITR, TLBIVMALLE1),
+    DO_BIT(HFGITR, TLBIVAE1),
+    DO_BIT(HFGITR, TLBIASIDE1),
+    DO_BIT(HFGITR, TLBIVAAE1),
+    DO_BIT(HFGITR, TLBIVALE1),
+    DO_BIT(HFGITR, TLBIVAALE1),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVMALLE1IS,
       .writefn = tlbi_aa64_vmalle1is_write },
     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAE1IS,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIASIDE1IS,
       .writefn = tlbi_aa64_vmalle1is_write },
     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAAE1IS,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVALE1IS,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAALE1IS,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVMALLE1,
       .writefn = tlbi_aa64_vmalle1_write },
     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAE1,
       .writefn = tlbi_aa64_vae1_write },
     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIASIDE1,
       .writefn = tlbi_aa64_vmalle1_write },
     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAAE1,
       .writefn = tlbi_aa64_vae1_write },
     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVALE1,
       .writefn = tlbi_aa64_vae1_write },
     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAALE1,
       .writefn = tlbi_aa64_vae1_write },
     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
     { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAE1IS,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAAE1IS,
       .writefn = tlbi_aa64_rvae1is_write },
    { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVALE1IS,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAALE1IS,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAE1OS,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAAE1OS,
       .writefn = tlbi_aa64_rvae1is_write },
    { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVALE1OS,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAALE1OS,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAE1,
       .writefn = tlbi_aa64_rvae1_write },
     { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAAE1,
       .writefn = tlbi_aa64_rvae1_write },
    { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVALE1,
       .writefn = tlbi_aa64_rvae1_write },
     { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAALE1,
       .writefn = tlbi_aa64_rvae1_write },
     { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
     { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVMALLE1OS,
       .writefn = tlbi_aa64_vmalle1is_write },
     { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
+      .fgt = FGT_TLBIVAE1OS,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIASIDE1OS,
       .writefn = tlbi_aa64_vmalle1is_write },
     { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAAE1OS,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVALE1OS,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAALE1OS,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
-- 
2.34.1

Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 48..63.

Some of these bits are for trapping instructions which are
not in the system instruction encoding (i.e. which are
not handled by the ARMCPRegInfo mechanism):
 * ERET, ERETAA, ERETAB
 * SVC

We will have to handle those separately and manually.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HFGITR, TLBIVAAE1),
     DO_BIT(HFGITR, TLBIVALE1),
     DO_BIT(HFGITR, TLBIVAALE1),
+    DO_BIT(HFGITR, CFPRCTX),
+    DO_BIT(HFGITR, DVPRCTX),
+    DO_BIT(HFGITR, CPPRCTX),
+    DO_BIT(HFGITR, DCCVAC),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NOP,
+      .fgt = FGT_DCCVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
     { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
 static const ARMCPRegInfo predinv_reginfo[] = {
     { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,
+      .fgt = FGT_CFPRCTX,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
     { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,
+      .fgt = FGT_DVPRCTX,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
     { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,
+      .fgt = FGT_CPPRCTX,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
     /*
      * Note the AArch32 opcodes have a different OPC1.
      */
     { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32,
       .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,
+      .fgt = FGT_CFPRCTX,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
     { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32,
       .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,
+      .fgt = FGT_DVPRCTX,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
     { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
       .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
+      .fgt = FGT_CPPRCTX,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
 };
 
-- 
2.34.1

Implement the HFGITR_EL2.ERET fine-grained trap.  This traps
execution from AArch64 EL1 of ERET, ERETAA and ERETAB.  The trap is
reported with a syndrome value of 0x1a.

The trap must take precedence over a possible pointer-authentication
trap for ERETAA and ERETAB.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-21-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-21-peter.maydell@linaro.org
---
 target/arm/cpu.h           |  1 +
 target/arm/syndrome.h      | 10 ++++++++++
 target/arm/translate.h     |  2 ++
 target/arm/helper.c        |  3 +++
 target/arm/translate-a64.c | 10 ++++++++++
 5 files changed, 26 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
 FIELD(TBFLAG_A64, SVL, 24, 4)
 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
+FIELD(TBFLAG_A64, FGT_ERET, 29, 1)
 
 /*
  * Helpers for using the above.
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -XXX,XX +XXX,XX @@ enum arm_exception_class {
     EC_AA64_SMC               = 0x17,
     EC_SYSTEMREGISTERTRAP     = 0x18,
     EC_SVEACCESSTRAP          = 0x19,
+    EC_ERETTRAP               = 0x1a,
     EC_SMETRAP                = 0x1d,
     EC_INSNABORT              = 0x20,
     EC_INSNABORT_SAME_EL      = 0x21,
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_sve_access_trap(void)
     return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT;
 }
 
+/*
+ * eret_op is bits [1:0] of the ERET instruction, so:
+ * 0 for ERET, 2 for ERETAA, 3 for ERETAB.
+ */
+static inline uint32_t syn_erettrap(int eret_op)
+{
+    return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op;
+}
+
 static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit)
 {
     return (EC_SMETRAP << ARM_EL_EC_SHIFT)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     bool mve_no_pred;
     /* True if fine-grained traps are active */
     bool fgt_active;
+    /* True if fine-grained trap on ERET is enabled */
+    bool fgt_eret;
     /*
      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
      *  < 0, set by the current instruction.
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
 
     if (arm_fgt_active(env, el)) {
         DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
+        if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
+            DP_TBFLAG_A64(flags, FGT_ERET, 1);
+        }
     }
 
     if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
             if (op4 != 0) {
                 goto do_unallocated;
             }
+            if (s->fgt_eret) {
+                gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2);
+                return;
+            }
             dst = tcg_temp_new_i64();
             tcg_gen_ld_i64(dst, cpu_env,
                            offsetof(CPUARMState, elr_el[s->current_el]));
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
             if (rn != 0x1f || op4 != 0x1f) {
                 goto do_unallocated;
             }
+            /* The FGT trap takes precedence over an auth trap. */
+            if (s->fgt_eret) {
+                gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2);
+                return;
+            }
             dst = tcg_temp_new_i64();
             tcg_gen_ld_i64(dst, cpu_env,
                            offsetof(CPUARMState, elr_el[s->current_el]));
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
     dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
+    dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET);
     dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
     dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
     dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;
-- 
2.34.1

Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps.
These trap execution of the SVC instruction from AArch32 and AArch64.
(As usual, AArch32 can only trap from EL0, as fine grained traps are
disabled with an AArch32 EL1.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-22-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-22-peter.maydell@linaro.org
---
 target/arm/cpu.h           |  1 +
 target/arm/translate.h     |  2 ++
 target/arm/helper.c        | 20 ++++++++++++++++++++
 target/arm/translate-a64.c |  9 ++++++++-
 target/arm/translate.c     | 12 +++++++++---
 5 files changed, 40 insertions(+), 4 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
+FIELD(TBFLAG_ANY, FGT_SVC, 13, 1)
 
 /*
  * Bit usage when in AArch32 state, both A- and M-profile.
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     bool fgt_active;
     /* True if fine-grained trap on ERET is enabled */
     bool fgt_eret;
+    /* True if fine-grained trap on SVC is enabled */
+    bool fgt_svc;
     /*
      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
      *  < 0, set by the current instruction.
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
     return arm_mmu_idx_el(env, arm_current_el(env));
 }
 
+static inline bool fgt_svc(CPUARMState *env, int el)
+{
+    /*
+     * Assuming fine-grained-traps are active, return true if we
+     * should be trapping on SVC instructions. Only AArch64 can
+     * trap on an SVC at EL1, but we don't need to special-case this
+     * because if this is AArch32 EL1 then arm_fgt_active() is false.
+     * We also know el is 0 or 1.
+     */
+    return el == 0 ?
+        FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
+        FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
+}
+
 static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
                                            ARMMMUIdx mmu_idx,
                                            CPUARMTBFlags flags)
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
 
     if (arm_fgt_active(env, el)) {
         DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
+        if (fgt_svc(env, el)) {
+            DP_TBFLAG_ANY(flags, FGT_SVC, 1);
+        }
     }
 
     if (env->uncached_cpsr & CPSR_IL) {
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
         if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
             DP_TBFLAG_A64(flags, FGT_ERET, 1);
         }
+        if (fgt_svc(env, el)) {
+            DP_TBFLAG_ANY(flags, FGT_SVC, 1);
+        }
     }
 
     if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
     int opc = extract32(insn, 21, 3);
     int op2_ll = extract32(insn, 0, 5);
     int imm16 = extract32(insn, 5, 16);
+    uint32_t syndrome;
 
     switch (opc) {
     case 0:
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
          */
         switch (op2_ll) {
         case 1:                                                     /* SVC */
+            syndrome = syn_aa64_svc(imm16);
+            if (s->fgt_svc) {
+                gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
+                break;
+            }
             gen_ss_advance(s);
-            gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16));
+            gen_exception_insn(s, 4, EXCP_SWI, syndrome);
             break;
         case 2:                                                     /* HVC */
             if (s->current_el == 0) {
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
     dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
+    dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC);
     dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET);
     dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
     dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
         (a->imm == semihost_imm)) {
         gen_exception_internal_insn(s, EXCP_SEMIHOST);
     } else {
-        gen_update_pc(s, curr_insn_len(s));
-        s->svc_imm = a->imm;
-        s->base.is_jmp = DISAS_SWI;
+        if (s->fgt_svc) {
+            uint32_t syndrome = syn_aa32_svc(a->imm, s->thumb);
+            gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
+        } else {
+            gen_update_pc(s, curr_insn_len(s));
+            s->svc_imm = a->imm;
+            s->base.is_jmp = DISAS_SWI;
+        }
     }
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
     dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
+    dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC);
 
     if (arm_feature(env, ARM_FEATURE_M)) {
         dc->vfp_enabled = 1;
-- 
2.34.1

FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and
MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug
Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0,
MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their
AArch32 equivalents).  This trapping is independent of whether
fine-grained traps are enabled or not.

Implement these extra traps.  (We don't implement DBGDTR_EL0,
DBGDTRRX_EL0 and DBGDTRTX_EL0.)

diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
     return CP_ACCESS_OK;
 }
 
+/*
+ * Check for traps to Debug Comms Channel registers. If FEAT_FGT
+ * is implemented then these are controlled by MDCR_EL2.TDCC for
+ * EL2 and MDCR_EL3.TDCC for EL3. They are also controlled by
+ * the general debug access trap bits MDCR_EL2.TDA and MDCR_EL3.TDA.
+ */
+static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  bool isread)
+{
+    int el = arm_current_el(env);
+    uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
+    bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) ||
+        (arm_hcr_el2_eff(env) & HCR_TGE);
+    bool mdcr_el2_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
+                                          (mdcr_el2 & MDCR_TDCC);
+    bool mdcr_el3_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
+                                          (env->cp15.mdcr_el3 & MDCR_TDCC);
+
+    if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) {
+        return CP_ACCESS_TRAP_EL3;
+    }
+    return CP_ACCESS_OK;
+}
+
 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
                         uint64_t value)
 {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
      */
     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
-      .access = PL0_R, .accessfn = access_tda,
+      .access = PL0_R, .accessfn = access_tdcc,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     /*
      * OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_EL0.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
      */
     { .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
       .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
-      .access = PL1_RW, .accessfn = access_tda,
+      .access = PL1_RW, .accessfn = access_tdcc,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
       .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
-      .access = PL1_RW, .accessfn = access_tda,
+      .access = PL1_RW, .accessfn = access_tdcc,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     /*
      * OSECCR_EL1 provides a mechanism for an operating system
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
      */
     { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
-      .access = PL1_RW, .accessfn = access_tda,
+      .access = PL1_RW, .accessfn = access_tdcc,
       .type = ARM_CP_NOP },
     /*
      * Dummy DBGCLAIM registers.
-- 
2.34.1

Update the ID registers for TCG's '-cpu max' to report the
presence of FEAT_FGT Fine-Grained Traps support.

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_ETS (Enhanced Translation Synchronization)
 - FEAT_EVT (Enhanced Virtualization Traps)
 - FEAT_FCMA (Floating-point complex number instructions)
+- FEAT_FGT (Fine-Grained Traps)
 - FEAT_FHM (Floating-point half-precision multiplication instructions)
 - FEAT_FP16 (Half-precision floating-point data processing)
 - FEAT_FRINTTS (Floating-point to integer instructions)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2);  /*  4k stage2 supported */
+    t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1);       /* FEAT_FGT */
     cpu->isar.id_aa64mmfr0 = t;
 
     t = cpu->isar.id_aa64mmfr1;
-- 
2.34.1