| 1 | The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df: | 1 | My OS Lock/DoubleLock patches, plus a small selection of other |
|---|---|---|---|
| 2 | bug fixes and minor things. | ||
| 2 | 3 | ||
| 3 | Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100) | 4 | thanks |
| 5 | -- PMM | ||
| 6 | |||
| 7 | The following changes since commit 8e9398e3b1a860b8c29c670c1b6c36afe8d87849: | ||
| 8 | |||
| 9 | Merge tag 'pull-ppc-20220706' of https://gitlab.com/danielhb/qemu into staging (2022-07-07 06:21:05 +0530) | ||
| 4 | 10 | ||
| 5 | are available in the Git repository at: | 11 | are available in the Git repository at: |
| 6 | 12 | ||
| 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702 | 13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220707 |
| 8 | 14 | ||
| 9 | for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8: | 15 | for you to fetch changes up to c2360eaa0262a816faf8032b7762d0c73df2cc62: |
| 10 | 16 | ||
| 11 | target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100) | 17 | target/arm: Fix qemu-system-arm handling of LPAE block descriptors for highmem (2022-07-07 11:41:04 +0100) |
| 12 | 18 | ||
| 13 | ---------------------------------------------------------------- | 19 | ---------------------------------------------------------------- |
| 14 | target-arm queue: | 20 | target-arm queue: |
| 15 | * more MVE instructions | 21 | * hw/arm/virt: dt: add rng-seed property |
| 16 | * hw/gpio/gpio_pwr: use shutdown function for reboot | 22 | * Fix MTE check in sve_ldnfff1_r |
| 17 | * target/arm: Check NaN mode before silencing NaN | 23 | * Record tagged bit for user-only in sve_probe_page |
| 18 | * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine | 24 | * Correctly implement OS Lock and OS DoubleLock |
| 19 | * hw/arm: Add basic power management to raspi. | 25 | * Implement DBGDEVID, DBGDEVID1, DBGDEVID2 registers |
| 20 | * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc | 26 | * Fix qemu-system-arm handling of LPAE block descriptors for highmem |
| 21 | 27 | ||
| 22 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
| 23 | Joe Komlodi (1): | 29 | Jason A. Donenfeld (1): |
| 24 | target/arm: Check NaN mode before silencing NaN | 30 | hw/arm/virt: dt: add rng-seed property |
| 25 | 31 | ||
| 26 | Maxim Uvarov (1): | 32 | Peter Maydell (6): |
| 27 | hw/gpio/gpio_pwr: use shutdown function for reboot | 33 | target/arm: Fix code style issues in debug helper functions |
| 34 | target/arm: Move define_debug_regs() to debug_helper.c | ||
| 35 | target/arm: Suppress debug exceptions when OS Lock set | ||
| 36 | target/arm: Implement AArch32 DBGDEVID, DBGDEVID1, DBGDEVID2 | ||
| 37 | target/arm: Correctly implement Feat_DoubleLock | ||
| 38 | target/arm: Fix qemu-system-arm handling of LPAE block descriptors for highmem | ||
| 28 | 39 | ||
| 29 | Nolan Leake (1): | 40 | Richard Henderson (2): |
| 30 | hw/arm: Add basic power management to raspi. | 41 | target/arm: Fix MTE check in sve_ldnfff1_r |
| 42 | target/arm: Record tagged bit for user-only in sve_probe_page | ||
| 31 | 43 | ||
| 32 | Patrick Venture (2): | 44 | docs/about/deprecated.rst | 8 + |
| 33 | docs/system/arm: Add quanta-q7l1-bmc reference | 45 | docs/system/arm/virt.rst | 17 +- |
| 34 | docs/system/arm: Add quanta-gbs-bmc reference | 46 | include/hw/arm/virt.h | 2 +- |
| 35 | 47 | target/arm/cpregs.h | 3 + | |
| 36 | Peter Maydell (18): | 48 | target/arm/cpu.h | 27 +++ |
| 37 | target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation | 49 | target/arm/internals.h | 9 + |
| 38 | target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH | 50 | hw/arm/virt.c | 44 ++-- |
| 39 | target/arm: Make asimd_imm_const() public | 51 | target/arm/cpu64.c | 6 + |
| 40 | target/arm: Use asimd_imm_const for A64 decode | 52 | target/arm/cpu_tcg.c | 6 + |
| 41 | target/arm: Use dup_const() instead of bitfield_replicate() | 53 | target/arm/debug_helper.c | 580 ++++++++++++++++++++++++++++++++++++++++++++++ |
| 42 | target/arm: Implement MVE logical immediate insns | 54 | target/arm/helper.c | 513 +--------------------------------------- |
| 43 | target/arm: Implement MVE vector shift left by immediate insns | 55 | target/arm/ptw.c | 2 +- |
| 44 | target/arm: Implement MVE vector shift right by immediate insns | 56 | target/arm/sve_helper.c | 5 +- |
| 45 | target/arm: Implement MVE VSHLL | 57 | 13 files changed, 684 insertions(+), 538 deletions(-) |
| 46 | target/arm: Implement MVE VSRI, VSLI | ||
| 47 | target/arm: Implement MVE VSHRN, VRSHRN | ||
| 48 | target/arm: Implement MVE saturating narrowing shifts | ||
| 49 | target/arm: Implement MVE VSHLC | ||
| 50 | target/arm: Implement MVE VADDLV | ||
| 51 | target/arm: Implement MVE long shifts by immediate | ||
| 52 | target/arm: Implement MVE long shifts by register | ||
| 53 | target/arm: Implement MVE shifts by immediate | ||
| 54 | target/arm: Implement MVE shifts by register | ||
| 55 | |||
| 56 | Philippe Mathieu-Daudé (1): | ||
| 57 | tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine | ||
| 58 | |||
| 59 | docs/system/arm/aspeed.rst | 1 + | ||
| 60 | docs/system/arm/nuvoton.rst | 5 +- | ||
| 61 | include/hw/arm/bcm2835_peripherals.h | 3 +- | ||
| 62 | include/hw/misc/bcm2835_powermgt.h | 29 ++ | ||
| 63 | target/arm/helper-mve.h | 108 +++++++ | ||
| 64 | target/arm/translate.h | 41 +++ | ||
| 65 | target/arm/mve.decode | 177 ++++++++++- | ||
| 66 | target/arm/t32.decode | 71 ++++- | ||
| 67 | hw/arm/bcm2835_peripherals.c | 13 +- | ||
| 68 | hw/gpio/gpio_pwr.c | 2 +- | ||
| 69 | hw/misc/bcm2835_powermgt.c | 160 ++++++++++ | ||
| 70 | target/arm/helper-a64.c | 12 +- | ||
| 71 | target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++-- | ||
| 72 | target/arm/translate-a64.c | 86 +----- | ||
| 73 | target/arm/translate-mve.c | 261 +++++++++++++++- | ||
| 74 | target/arm/translate-neon.c | 81 ----- | ||
| 75 | target/arm/translate.c | 327 +++++++++++++++++++- | ||
| 76 | target/arm/vfp_helper.c | 24 +- | ||
| 77 | hw/misc/meson.build | 1 + | ||
| 78 | tests/acceptance/boot_linux_console.py | 43 +++ | ||
| 79 | 20 files changed, 1760 insertions(+), 209 deletions(-) | ||
| 80 | create mode 100644 include/hw/misc/bcm2835_powermgt.h | ||
| 81 | create mode 100644 hw/misc/bcm2835_powermgt.c | ||
| 82 | diff view generated by jsdifflib |
| 1 | From: Patrick Venture <venture@google.com> | 1 | From: "Jason A. Donenfeld" <Jason@zx2c4.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Adds a line-item reference to the supported quanta-q71l-bmc aspeed | 3 | In 60592cfed2 ("hw/arm/virt: dt: add kaslr-seed property"), the |
| 4 | entry. | 4 | kaslr-seed property was added, but the equally as important rng-seed |
| 5 | property was forgotten about, which has identical semantics for a | ||
| 6 | similar purpose. This commit implements it in exactly the same way as | ||
| 7 | kaslr-seed. It then changes the name of the disabling option to reflect | ||
| 8 | that this has more to do with randomness vs determinism, rather than | ||
| 9 | something particular about kaslr. | ||
| 5 | 10 | ||
| 6 | Signed-off-by: Patrick Venture <venture@google.com> | 11 | Cc: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 12 | Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> |
| 8 | Message-id: 20210615192848.1065297-2-venture@google.com | 13 | [PMM: added deprecated.rst section for the deprecation] |
| 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | --- | 16 | --- |
| 11 | docs/system/arm/aspeed.rst | 1 + | 17 | docs/about/deprecated.rst | 8 +++++++ |
| 12 | 1 file changed, 1 insertion(+) | 18 | docs/system/arm/virt.rst | 17 +++++++++------ |
| 19 | include/hw/arm/virt.h | 2 +- | ||
| 20 | hw/arm/virt.c | 44 ++++++++++++++++++++++++--------------- | ||
| 21 | 4 files changed, 47 insertions(+), 24 deletions(-) | ||
| 13 | 22 | ||
| 14 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst | 23 | diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst |
| 15 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/docs/system/arm/aspeed.rst | 25 | --- a/docs/about/deprecated.rst |
| 17 | +++ b/docs/system/arm/aspeed.rst | 26 | +++ b/docs/about/deprecated.rst |
| 18 | @@ -XXX,XX +XXX,XX @@ etc. | 27 | @@ -XXX,XX +XXX,XX @@ Use the more generic event ``DEVICE_UNPLUG_GUEST_ERROR`` instead. |
| 19 | AST2400 SoC based machines : | 28 | System emulator machines |
| 20 | 29 | ------------------------ | |
| 21 | - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC | 30 | |
| 22 | +- ``quanta-q71l-bmc`` OpenBMC Quanta BMC | 31 | +Arm ``virt`` machine ``dtb-kaslr-seed`` property |
| 23 | 32 | +'''''''''''''''''''''''''''''''''''''''''''''''' | |
| 24 | AST2500 SoC based machines : | 33 | + |
| 34 | +The ``dtb-kaslr-seed`` property on the ``virt`` board has been | ||
| 35 | +deprecated; use the new name ``dtb-randomness`` instead. The new name | ||
| 36 | +better reflects the way this property affects all random data within | ||
| 37 | +the device tree blob, not just the ``kaslr-seed`` node. | ||
| 38 | + | ||
| 39 | PPC 405 ``taihu`` machine (since 7.0) | ||
| 40 | ''''''''''''''''''''''''''''''''''''' | ||
| 41 | |||
| 42 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | ||
| 43 | index XXXXXXX..XXXXXXX 100644 | ||
| 44 | --- a/docs/system/arm/virt.rst | ||
| 45 | +++ b/docs/system/arm/virt.rst | ||
| 46 | @@ -XXX,XX +XXX,XX @@ ras | ||
| 47 | Set ``on``/``off`` to enable/disable reporting host memory errors to a guest | ||
| 48 | using ACPI and guest external abort exceptions. The default is off. | ||
| 49 | |||
| 50 | +dtb-randomness | ||
| 51 | + Set ``on``/``off`` to pass random seeds via the guest DTB | ||
| 52 | + rng-seed and kaslr-seed nodes (in both "/chosen" and | ||
| 53 | + "/secure-chosen") to use for features like the random number | ||
| 54 | + generator and address space randomisation. The default is | ||
| 55 | + ``on``. You will want to disable it if your trusted boot chain | ||
| 56 | + will verify the DTB it is passed, since this option causes the | ||
| 57 | + DTB to be non-deterministic. It would be the responsibility of | ||
| 58 | + the firmware to come up with a seed and pass it on if it wants to. | ||
| 59 | + | ||
| 60 | dtb-kaslr-seed | ||
| 61 | - Set ``on``/``off`` to pass a random seed via the guest dtb | ||
| 62 | - kaslr-seed node (in both "/chosen" and /secure-chosen) to use | ||
| 63 | - for features like address space randomisation. The default is | ||
| 64 | - ``on``. You will want to disable it if your trusted boot chain will | ||
| 65 | - verify the DTB it is passed. It would be the responsibility of the | ||
| 66 | - firmware to come up with a seed and pass it on if it wants to. | ||
| 67 | + A deprecated synonym for dtb-randomness. | ||
| 68 | |||
| 69 | Linux guest kernel configuration | ||
| 70 | """""""""""""""""""""""""""""""" | ||
| 71 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | ||
| 72 | index XXXXXXX..XXXXXXX 100644 | ||
| 73 | --- a/include/hw/arm/virt.h | ||
| 74 | +++ b/include/hw/arm/virt.h | ||
| 75 | @@ -XXX,XX +XXX,XX @@ struct VirtMachineState { | ||
| 76 | bool virt; | ||
| 77 | bool ras; | ||
| 78 | bool mte; | ||
| 79 | - bool dtb_kaslr_seed; | ||
| 80 | + bool dtb_randomness; | ||
| 81 | OnOffAuto acpi; | ||
| 82 | VirtGICType gic_version; | ||
| 83 | VirtIOMMUType iommu; | ||
| 84 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
| 85 | index XXXXXXX..XXXXXXX 100644 | ||
| 86 | --- a/hw/arm/virt.c | ||
| 87 | +++ b/hw/arm/virt.c | ||
| 88 | @@ -XXX,XX +XXX,XX @@ static bool cpu_type_valid(const char *cpu) | ||
| 89 | return false; | ||
| 90 | } | ||
| 91 | |||
| 92 | -static void create_kaslr_seed(MachineState *ms, const char *node) | ||
| 93 | +static void create_randomness(MachineState *ms, const char *node) | ||
| 94 | { | ||
| 95 | - uint64_t seed; | ||
| 96 | + struct { | ||
| 97 | + uint64_t kaslr; | ||
| 98 | + uint8_t rng[32]; | ||
| 99 | + } seed; | ||
| 100 | |||
| 101 | if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) { | ||
| 102 | return; | ||
| 103 | } | ||
| 104 | - qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed); | ||
| 105 | + qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); | ||
| 106 | + qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); | ||
| 107 | } | ||
| 108 | |||
| 109 | static void create_fdt(VirtMachineState *vms) | ||
| 110 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms) | ||
| 111 | |||
| 112 | /* /chosen must exist for load_dtb to fill in necessary properties later */ | ||
| 113 | qemu_fdt_add_subnode(fdt, "/chosen"); | ||
| 114 | - if (vms->dtb_kaslr_seed) { | ||
| 115 | - create_kaslr_seed(ms, "/chosen"); | ||
| 116 | + if (vms->dtb_randomness) { | ||
| 117 | + create_randomness(ms, "/chosen"); | ||
| 118 | } | ||
| 119 | |||
| 120 | if (vms->secure) { | ||
| 121 | qemu_fdt_add_subnode(fdt, "/secure-chosen"); | ||
| 122 | - if (vms->dtb_kaslr_seed) { | ||
| 123 | - create_kaslr_seed(ms, "/secure-chosen"); | ||
| 124 | + if (vms->dtb_randomness) { | ||
| 125 | + create_randomness(ms, "/secure-chosen"); | ||
| 126 | } | ||
| 127 | } | ||
| 128 | |||
| 129 | @@ -XXX,XX +XXX,XX @@ static void virt_set_its(Object *obj, bool value, Error **errp) | ||
| 130 | vms->its = value; | ||
| 131 | } | ||
| 132 | |||
| 133 | -static bool virt_get_dtb_kaslr_seed(Object *obj, Error **errp) | ||
| 134 | +static bool virt_get_dtb_randomness(Object *obj, Error **errp) | ||
| 135 | { | ||
| 136 | VirtMachineState *vms = VIRT_MACHINE(obj); | ||
| 137 | |||
| 138 | - return vms->dtb_kaslr_seed; | ||
| 139 | + return vms->dtb_randomness; | ||
| 140 | } | ||
| 141 | |||
| 142 | -static void virt_set_dtb_kaslr_seed(Object *obj, bool value, Error **errp) | ||
| 143 | +static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp) | ||
| 144 | { | ||
| 145 | VirtMachineState *vms = VIRT_MACHINE(obj); | ||
| 146 | |||
| 147 | - vms->dtb_kaslr_seed = value; | ||
| 148 | + vms->dtb_randomness = value; | ||
| 149 | } | ||
| 150 | |||
| 151 | static char *virt_get_oem_id(Object *obj, Error **errp) | ||
| 152 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) | ||
| 153 | "Set on/off to enable/disable " | ||
| 154 | "ITS instantiation"); | ||
| 155 | |||
| 156 | + object_class_property_add_bool(oc, "dtb-randomness", | ||
| 157 | + virt_get_dtb_randomness, | ||
| 158 | + virt_set_dtb_randomness); | ||
| 159 | + object_class_property_set_description(oc, "dtb-randomness", | ||
| 160 | + "Set off to disable passing random or " | ||
| 161 | + "non-deterministic dtb nodes to guest"); | ||
| 162 | + | ||
| 163 | object_class_property_add_bool(oc, "dtb-kaslr-seed", | ||
| 164 | - virt_get_dtb_kaslr_seed, | ||
| 165 | - virt_set_dtb_kaslr_seed); | ||
| 166 | + virt_get_dtb_randomness, | ||
| 167 | + virt_set_dtb_randomness); | ||
| 168 | object_class_property_set_description(oc, "dtb-kaslr-seed", | ||
| 169 | - "Set off to disable passing of kaslr-seed " | ||
| 170 | - "dtb node to guest"); | ||
| 171 | + "Deprecated synonym of dtb-randomness"); | ||
| 172 | |||
| 173 | object_class_property_add_str(oc, "x-oem-id", | ||
| 174 | virt_get_oem_id, | ||
| 175 | @@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj) | ||
| 176 | /* MTE is disabled by default. */ | ||
| 177 | vms->mte = false; | ||
| 178 | |||
| 179 | - /* Supply a kaslr-seed by default */ | ||
| 180 | - vms->dtb_kaslr_seed = true; | ||
| 181 | + /* Supply kaslr-seed and rng-seed by default */ | ||
| 182 | + vms->dtb_randomness = true; | ||
| 183 | |||
| 184 | vms->irqmap = a15irqmap; | ||
| 25 | 185 | ||
| 26 | -- | 186 | -- |
| 27 | 2.20.1 | 187 | 2.25.1 |
| 28 | |||
| 29 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Patrick Venture <venture@google.com> | ||
| 2 | 1 | ||
| 3 | Add line item reference to quanta-gbs-bmc machine. | ||
| 4 | |||
| 5 | Signed-off-by: Patrick Venture <venture@google.com> | ||
| 6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
| 7 | Message-id: 20210615192848.1065297-3-venture@google.com | ||
| 8 | [PMM: fixed underline Sphinx warning] | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | docs/system/arm/nuvoton.rst | 5 +++-- | ||
| 12 | 1 file changed, 3 insertions(+), 2 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/docs/system/arm/nuvoton.rst | ||
| 17 | +++ b/docs/system/arm/nuvoton.rst | ||
| 18 | @@ -XXX,XX +XXX,XX @@ | ||
| 19 | -Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``) | ||
| 20 | -===================================================== | ||
| 21 | +Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``) | ||
| 22 | +================================================================ | ||
| 23 | |||
| 24 | The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are | ||
| 25 | designed to be used as Baseboard Management Controllers (BMCs) in various | ||
| 26 | @@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip : | ||
| 27 | The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and | ||
| 28 | Hyperscale applications. The following machines are based on this chip : | ||
| 29 | |||
| 30 | +- ``quanta-gbs-bmc`` Quanta GBS server BMC | ||
| 31 | - ``quanta-gsj`` Quanta GSJ server BMC | ||
| 32 | |||
| 33 | There are also two more SoCs, NPCM710 and NPCM705, which are single-core | ||
| 34 | -- | ||
| 35 | 2.20.1 | ||
| 36 | |||
| 37 | diff view generated by jsdifflib |
| 1 | From: Maxim Uvarov <maxim.uvarov@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | qemu has 2 type of functions: shutdown and reboot. Shutdown | 3 | The comment was correct, but the test was not: |
| 4 | function has to be used for machine shutdown. Otherwise we cause | 4 | disable mte if tagged is *not* set. |
| 5 | a reset with a bogus "cause" value, when we intended a shutdown. | ||
| 6 | 5 | ||
| 7 | Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 9 | Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org | ||
| 10 | [PMM: tweaked commit message] | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 12 | --- | 9 | --- |
| 13 | hw/gpio/gpio_pwr.c | 2 +- | 10 | target/arm/sve_helper.c | 2 +- |
| 14 | 1 file changed, 1 insertion(+), 1 deletion(-) | 11 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 15 | 12 | ||
| 16 | diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c | 13 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c |
| 17 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/hw/gpio/gpio_pwr.c | 15 | --- a/target/arm/sve_helper.c |
| 19 | +++ b/hw/gpio/gpio_pwr.c | 16 | +++ b/target/arm/sve_helper.c |
| 20 | @@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level) | 17 | @@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const target_ulong addr, |
| 21 | static void gpio_pwr_shutdown(void *opaque, int n, int level) | 18 | * Disable MTE checking if the Tagged bit is not set. Since TBI must |
| 22 | { | 19 | * be set within MTEDESC for MTE, !mtedesc => !mte_active. |
| 23 | if (level) { | 20 | */ |
| 24 | - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | 21 | - if (arm_tlb_mte_tagged(&info.page[0].attrs)) { |
| 25 | + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | 22 | + if (!arm_tlb_mte_tagged(&info.page[0].attrs)) { |
| 23 | mtedesc = 0; | ||
| 26 | } | 24 | } |
| 27 | } | ||
| 28 | 25 | ||
| 29 | -- | 26 | -- |
| 30 | 2.20.1 | 27 | 2.25.1 |
| 31 | |||
| 32 | diff view generated by jsdifflib |
| 1 | From: Joe Komlodi <joe.komlodi@xilinx.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute | 3 | Fixes a bug in that we were not honoring MTE from user-only |
| 4 | FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will | 4 | SVE. Copy the user-only MTE logic from allocation_tag_mem |
| 5 | assert due to fpst->default_nan_mode being set. | 5 | into sve_probe_page. |
| 6 | 6 | ||
| 7 | To avoid this, we check to see what NaN mode we're running in before we call | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | floatxx_silence_nan(). | ||
| 9 | |||
| 10 | Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com> | ||
| 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 12 | Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com | ||
| 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 15 | --- | 10 | --- |
| 16 | target/arm/helper-a64.c | 12 +++++++++--- | 11 | target/arm/sve_helper.c | 3 +++ |
| 17 | target/arm/vfp_helper.c | 24 ++++++++++++++++++------ | 12 | 1 file changed, 3 insertions(+) |
| 18 | 2 files changed, 27 insertions(+), 9 deletions(-) | ||
| 19 | 13 | ||
| 20 | diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c | 14 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c |
| 21 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 22 | --- a/target/arm/helper-a64.c | 16 | --- a/target/arm/sve_helper.c |
| 23 | +++ b/target/arm/helper-a64.c | 17 | +++ b/target/arm/sve_helper.c |
| 24 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp) | 18 | @@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, |
| 25 | float16 nan = a; | 19 | |
| 26 | if (float16_is_signaling_nan(a, fpst)) { | 20 | #ifdef CONFIG_USER_ONLY |
| 27 | float_raise(float_flag_invalid, fpst); | 21 | memset(&info->attrs, 0, sizeof(info->attrs)); |
| 28 | - nan = float16_silence_nan(a, fpst); | 22 | + /* Require both MAP_ANON and PROT_MTE -- see allocation_tag_mem. */ |
| 29 | + if (!fpst->default_nan_mode) { | 23 | + arm_tlb_mte_tagged(&info->attrs) = |
| 30 | + nan = float16_silence_nan(a, fpst); | 24 | + (flags & PAGE_ANON) && (flags & PAGE_MTE); |
| 31 | + } | 25 | #else |
| 32 | } | 26 | /* |
| 33 | if (fpst->default_nan_mode) { | 27 | * Find the iotlbentry for addr and return the transaction attributes. |
| 34 | nan = float16_default_nan(fpst); | ||
| 35 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp) | ||
| 36 | float32 nan = a; | ||
| 37 | if (float32_is_signaling_nan(a, fpst)) { | ||
| 38 | float_raise(float_flag_invalid, fpst); | ||
| 39 | - nan = float32_silence_nan(a, fpst); | ||
| 40 | + if (!fpst->default_nan_mode) { | ||
| 41 | + nan = float32_silence_nan(a, fpst); | ||
| 42 | + } | ||
| 43 | } | ||
| 44 | if (fpst->default_nan_mode) { | ||
| 45 | nan = float32_default_nan(fpst); | ||
| 46 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp) | ||
| 47 | float64 nan = a; | ||
| 48 | if (float64_is_signaling_nan(a, fpst)) { | ||
| 49 | float_raise(float_flag_invalid, fpst); | ||
| 50 | - nan = float64_silence_nan(a, fpst); | ||
| 51 | + if (!fpst->default_nan_mode) { | ||
| 52 | + nan = float64_silence_nan(a, fpst); | ||
| 53 | + } | ||
| 54 | } | ||
| 55 | if (fpst->default_nan_mode) { | ||
| 56 | nan = float64_default_nan(fpst); | ||
| 57 | diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c | ||
| 58 | index XXXXXXX..XXXXXXX 100644 | ||
| 59 | --- a/target/arm/vfp_helper.c | ||
| 60 | +++ b/target/arm/vfp_helper.c | ||
| 61 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp) | ||
| 62 | float16 nan = f16; | ||
| 63 | if (float16_is_signaling_nan(f16, fpst)) { | ||
| 64 | float_raise(float_flag_invalid, fpst); | ||
| 65 | - nan = float16_silence_nan(f16, fpst); | ||
| 66 | + if (!fpst->default_nan_mode) { | ||
| 67 | + nan = float16_silence_nan(f16, fpst); | ||
| 68 | + } | ||
| 69 | } | ||
| 70 | if (fpst->default_nan_mode) { | ||
| 71 | nan = float16_default_nan(fpst); | ||
| 72 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp) | ||
| 73 | float32 nan = f32; | ||
| 74 | if (float32_is_signaling_nan(f32, fpst)) { | ||
| 75 | float_raise(float_flag_invalid, fpst); | ||
| 76 | - nan = float32_silence_nan(f32, fpst); | ||
| 77 | + if (!fpst->default_nan_mode) { | ||
| 78 | + nan = float32_silence_nan(f32, fpst); | ||
| 79 | + } | ||
| 80 | } | ||
| 81 | if (fpst->default_nan_mode) { | ||
| 82 | nan = float32_default_nan(fpst); | ||
| 83 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp) | ||
| 84 | float64 nan = f64; | ||
| 85 | if (float64_is_signaling_nan(f64, fpst)) { | ||
| 86 | float_raise(float_flag_invalid, fpst); | ||
| 87 | - nan = float64_silence_nan(f64, fpst); | ||
| 88 | + if (!fpst->default_nan_mode) { | ||
| 89 | + nan = float64_silence_nan(f64, fpst); | ||
| 90 | + } | ||
| 91 | } | ||
| 92 | if (fpst->default_nan_mode) { | ||
| 93 | nan = float64_default_nan(fpst); | ||
| 94 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp) | ||
| 95 | float16 nan = f16; | ||
| 96 | if (float16_is_signaling_nan(f16, s)) { | ||
| 97 | float_raise(float_flag_invalid, s); | ||
| 98 | - nan = float16_silence_nan(f16, s); | ||
| 99 | + if (!s->default_nan_mode) { | ||
| 100 | + nan = float16_silence_nan(f16, fpstp); | ||
| 101 | + } | ||
| 102 | } | ||
| 103 | if (s->default_nan_mode) { | ||
| 104 | nan = float16_default_nan(s); | ||
| 105 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) | ||
| 106 | float32 nan = f32; | ||
| 107 | if (float32_is_signaling_nan(f32, s)) { | ||
| 108 | float_raise(float_flag_invalid, s); | ||
| 109 | - nan = float32_silence_nan(f32, s); | ||
| 110 | + if (!s->default_nan_mode) { | ||
| 111 | + nan = float32_silence_nan(f32, fpstp); | ||
| 112 | + } | ||
| 113 | } | ||
| 114 | if (s->default_nan_mode) { | ||
| 115 | nan = float32_default_nan(s); | ||
| 116 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) | ||
| 117 | float64 nan = f64; | ||
| 118 | if (float64_is_signaling_nan(f64, s)) { | ||
| 119 | float_raise(float_flag_invalid, s); | ||
| 120 | - nan = float64_silence_nan(f64, s); | ||
| 121 | + if (!s->default_nan_mode) { | ||
| 122 | + nan = float64_silence_nan(f64, fpstp); | ||
| 123 | + } | ||
| 124 | } | ||
| 125 | if (s->default_nan_mode) { | ||
| 126 | nan = float64_default_nan(s); | ||
| 127 | -- | 28 | -- |
| 128 | 2.20.1 | 29 | 2.25.1 |
| 129 | |||
| 130 | diff view generated by jsdifflib |
| 1 | Implement the MVE shifts by register, which perform | 1 | Before moving debug system register helper functions to a |
|---|---|---|---|
| 2 | shifts on a single general-purpose register. | 2 | different file, fix the code style issues (mostly block |
| 3 | comment syntax) so checkpatch doesn't complain about the | ||
| 4 | code-motion patch. | ||
| 3 | 5 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 6 | Message-id: 20210628135835.6690-19-peter.maydell@linaro.org | 8 | Message-id: 20220630194116.3438513-2-peter.maydell@linaro.org |
| 7 | --- | 9 | --- |
| 8 | target/arm/helper-mve.h | 2 ++ | 10 | target/arm/helper.c | 58 +++++++++++++++++++++++++++++---------------- |
| 9 | target/arm/translate.h | 1 + | 11 | 1 file changed, 38 insertions(+), 20 deletions(-) |
| 10 | target/arm/t32.decode | 18 ++++++++++++++---- | ||
| 11 | target/arm/mve_helper.c | 10 ++++++++++ | ||
| 12 | target/arm/translate.c | 30 ++++++++++++++++++++++++++++++ | ||
| 13 | 5 files changed, 57 insertions(+), 4 deletions(-) | ||
| 14 | 12 | ||
| 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | 13 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/target/arm/helper-mve.h | 15 | --- a/target/arm/helper.c |
| 18 | +++ b/target/arm/helper-mve.h | 16 | +++ b/target/arm/helper.c |
| 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) | 17 | @@ -XXX,XX +XXX,XX @@ static uint64_t arm_mdcr_el2_eff(CPUARMState *env) |
| 20 | 18 | return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; | |
| 21 | DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | 19 | } |
| 22 | DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | 20 | |
| 23 | +DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | 21 | -/* Check for traps to "powerdown debug" registers, which are controlled |
| 24 | +DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32) | 22 | +/* |
| 25 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 23 | + * Check for traps to "powerdown debug" registers, which are controlled |
| 26 | index XXXXXXX..XXXXXXX 100644 | 24 | * by MDCR.TDOSA |
| 27 | --- a/target/arm/translate.h | 25 | */ |
| 28 | +++ b/target/arm/translate.h | 26 | static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, |
| 29 | @@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | 27 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, |
| 30 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | 28 | return CP_ACCESS_OK; |
| 31 | typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); | 29 | } |
| 32 | typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); | 30 | |
| 33 | +typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); | 31 | -/* Check for traps to "debug ROM" registers, which are controlled |
| 34 | 32 | +/* | |
| 35 | /** | 33 | + * Check for traps to "debug ROM" registers, which are controlled |
| 36 | * arm_tbflags_from_tb: | 34 | * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. |
| 37 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | 35 | */ |
| 38 | index XXXXXXX..XXXXXXX 100644 | 36 | static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, |
| 39 | --- a/target/arm/t32.decode | 37 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, |
| 40 | +++ b/target/arm/t32.decode | 38 | return CP_ACCESS_OK; |
| 41 | @@ -XXX,XX +XXX,XX @@ | 39 | } |
| 42 | &mve_shl_ri rdalo rdahi shim | 40 | |
| 43 | &mve_shl_rr rdalo rdahi rm | 41 | -/* Check for traps to general debug registers, which are controlled |
| 44 | &mve_sh_ri rda shim | 42 | +/* |
| 45 | +&mve_sh_rr rda rm | 43 | + * Check for traps to general debug registers, which are controlled |
| 46 | 44 | * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. | |
| 47 | # rdahi: bits [3:1] from insn, bit 0 is 1 | 45 | */ |
| 48 | # rdalo: bits [3:1] from insn, bit 0 is 0 | 46 | static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, |
| 49 | @@ -XXX,XX +XXX,XX @@ | 47 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, |
| 50 | &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 | 48 | static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 51 | @mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \ | 49 | uint64_t value) |
| 52 | &mve_sh_ri shim=%imm5_12_6 | ||
| 53 | +@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr | ||
| 54 | |||
| 55 | { | 50 | { |
| 56 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | 51 | - /* Writes to OSLAR_EL1 may update the OS lock status, which can be |
| 57 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | 52 | + /* |
| 58 | SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | 53 | + * Writes to OSLAR_EL1 may update the OS lock status, which can be |
| 54 | * read via a bit in OSLSR_EL1. | ||
| 55 | */ | ||
| 56 | int oslock; | ||
| 57 | @@ -XXX,XX +XXX,XX @@ static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 58 | } | ||
| 59 | |||
| 60 | static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
| 61 | - /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped | ||
| 62 | + /* | ||
| 63 | + * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped | ||
| 64 | * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; | ||
| 65 | * unlike DBGDRAR it is never accessible from EL0. | ||
| 66 | * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | ||
| 67 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
| 68 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | ||
| 69 | .access = PL1_RW, .accessfn = access_tdosa, | ||
| 70 | .type = ARM_CP_NOP }, | ||
| 71 | - /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't | ||
| 72 | + /* | ||
| 73 | + * Dummy DBGVCR: Linux wants to clear this on startup, but we don't | ||
| 74 | * implement vector catch debug events yet. | ||
| 75 | */ | ||
| 76 | { .name = "DBGVCR", | ||
| 77 | .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | ||
| 78 | .access = PL1_RW, .accessfn = access_tda, | ||
| 79 | .type = ARM_CP_NOP }, | ||
| 80 | - /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor | ||
| 81 | + /* | ||
| 82 | + * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor | ||
| 83 | * to save and restore a 32-bit guest's DBGVCR) | ||
| 84 | */ | ||
| 85 | { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | ||
| 86 | .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | ||
| 87 | .access = PL2_RW, .accessfn = access_tda, | ||
| 88 | .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, | ||
| 89 | - /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications | ||
| 90 | + /* | ||
| 91 | + * Dummy MDCCINT_EL1, since we don't implement the Debug Communications | ||
| 92 | * Channel but Linux may try to access this register. The 32-bit | ||
| 93 | * alias is DBGDCCINT. | ||
| 94 | */ | ||
| 95 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
| 96 | static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | ||
| 97 | /* 64 bit access versions of the (dummy) debug registers */ | ||
| 98 | { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | ||
| 99 | - .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 100 | + .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 101 | { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | ||
| 102 | - .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 103 | + .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 104 | }; | ||
| 105 | |||
| 106 | /* | ||
| 107 | @@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
| 108 | break; | ||
| 59 | } | 109 | } |
| 60 | 110 | ||
| 61 | - LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | 111 | - /* Attempts to use both MASK and BAS fields simultaneously are |
| 62 | - ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | 112 | + /* |
| 63 | - UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr | 113 | + * Attempts to use both MASK and BAS fields simultaneously are |
| 64 | - SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr | 114 | * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, |
| 65 | + { | 115 | * thus generating a watchpoint for every byte in the masked region. |
| 66 | + UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr | 116 | */ |
| 67 | + LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | 117 | mask = FIELD_EX64(wcr, DBGWCR, MASK); |
| 68 | + UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr | 118 | if (mask == 1 || mask == 2) { |
| 69 | + } | 119 | - /* Reserved values of MASK; we must act as if the mask value was |
| 70 | + | 120 | + /* |
| 71 | + { | 121 | + * Reserved values of MASK; we must act as if the mask value was |
| 72 | + SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr | 122 | * some non-reserved value, or as if the watchpoint were disabled. |
| 73 | + ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | 123 | * We choose the latter. |
| 74 | + SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr | 124 | */ |
| 75 | + } | 125 | @@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n) |
| 76 | + | 126 | } else if (mask) { |
| 77 | UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr | 127 | /* Watchpoint covers an aligned area up to 2GB in size */ |
| 78 | SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr | 128 | len = 1ULL << mask; |
| 79 | ] | 129 | - /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE |
| 80 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | 130 | + /* |
| 81 | index XXXXXXX..XXXXXXX 100644 | 131 | + * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE |
| 82 | --- a/target/arm/mve_helper.c | 132 | * whether the watchpoint fires when the unmasked bits match; we opt |
| 83 | +++ b/target/arm/mve_helper.c | 133 | * to generate the exceptions. |
| 84 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) | 134 | */ |
| 135 | @@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
| 136 | int basstart; | ||
| 137 | |||
| 138 | if (extract64(wvr, 2, 1)) { | ||
| 139 | - /* Deprecated case of an only 4-aligned address. BAS[7:4] are | ||
| 140 | + /* | ||
| 141 | + * Deprecated case of an only 4-aligned address. BAS[7:4] are | ||
| 142 | * ignored, and BAS[3:0] define which bytes to watch. | ||
| 143 | */ | ||
| 144 | bas &= 0xf; | ||
| 145 | @@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
| 146 | return; | ||
| 147 | } | ||
| 148 | |||
| 149 | - /* The BAS bits are supposed to be programmed to indicate a contiguous | ||
| 150 | + /* | ||
| 151 | + * The BAS bits are supposed to be programmed to indicate a contiguous | ||
| 152 | * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | ||
| 153 | * we fire for each byte in the word/doubleword addressed by the WVR. | ||
| 154 | * We choose to ignore any non-zero bits after the first range of 1s. | ||
| 155 | @@ -XXX,XX +XXX,XX @@ void hw_watchpoint_update_all(ARMCPU *cpu) | ||
| 156 | int i; | ||
| 157 | CPUARMState *env = &cpu->env; | ||
| 158 | |||
| 159 | - /* Completely clear out existing QEMU watchpoints and our array, to | ||
| 160 | + /* | ||
| 161 | + * Completely clear out existing QEMU watchpoints and our array, to | ||
| 162 | * avoid possible stale entries following migration load. | ||
| 163 | */ | ||
| 164 | cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | ||
| 165 | @@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update(ARMCPU *cpu, int n) | ||
| 166 | case 11: /* linked context ID and VMID match (reserved if no EL2) */ | ||
| 167 | case 3: /* linked context ID match */ | ||
| 168 | default: | ||
| 169 | - /* We must generate no events for Linked context matches (unless | ||
| 170 | + /* | ||
| 171 | + * We must generate no events for Linked context matches (unless | ||
| 172 | * they are linked to by some other bp/wp, which is handled in | ||
| 173 | * updates for the linking bp/wp). We choose to also generate no events | ||
| 174 | * for reserved values. | ||
| 175 | @@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update_all(ARMCPU *cpu) | ||
| 176 | int i; | ||
| 177 | CPUARMState *env = &cpu->env; | ||
| 178 | |||
| 179 | - /* Completely clear out existing QEMU breakpoints and our array, to | ||
| 180 | + /* | ||
| 181 | + * Completely clear out existing QEMU breakpoints and our array, to | ||
| 182 | * avoid possible stale entries following migration load. | ||
| 183 | */ | ||
| 184 | cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | ||
| 185 | @@ -XXX,XX +XXX,XX @@ static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 186 | ARMCPU *cpu = env_archcpu(env); | ||
| 187 | int i = ri->crm; | ||
| 188 | |||
| 189 | - /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | ||
| 190 | + /* | ||
| 191 | + * BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | ||
| 192 | * copy of BAS[0]. | ||
| 193 | */ | ||
| 194 | value = deposit64(value, 6, 1, extract64(value, 5, 1)); | ||
| 195 | @@ -XXX,XX +XXX,XX @@ static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 196 | |||
| 197 | static void define_debug_regs(ARMCPU *cpu) | ||
| 85 | { | 198 | { |
| 86 | return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); | 199 | - /* Define v7 and v8 architectural debug registers. |
| 87 | } | 200 | + /* |
| 88 | + | 201 | + * Define v7 and v8 architectural debug registers. |
| 89 | +uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) | 202 | * These are just dummy implementations for now. |
| 90 | +{ | 203 | */ |
| 91 | + return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); | 204 | int i; |
| 92 | +} | ||
| 93 | + | ||
| 94 | +uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
| 95 | +{ | ||
| 96 | + return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); | ||
| 97 | +} | ||
| 98 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 99 | index XXXXXXX..XXXXXXX 100644 | ||
| 100 | --- a/target/arm/translate.c | ||
| 101 | +++ b/target/arm/translate.c | ||
| 102 | @@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
| 103 | return do_mve_sh_ri(s, a, gen_mve_uqshl); | ||
| 104 | } | ||
| 105 | |||
| 106 | +static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn) | ||
| 107 | +{ | ||
| 108 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
| 109 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | ||
| 110 | + return false; | ||
| 111 | + } | ||
| 112 | + if (!dc_isar_feature(aa32_mve, s) || | ||
| 113 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | ||
| 114 | + a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 || | ||
| 115 | + a->rm == a->rda) { | ||
| 116 | + /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */ | ||
| 117 | + unallocated_encoding(s); | ||
| 118 | + return true; | ||
| 119 | + } | ||
| 120 | + | ||
| 121 | + /* The helper takes care of the sign-extension of the low 8 bits of Rm */ | ||
| 122 | + fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]); | ||
| 123 | + return true; | ||
| 124 | +} | ||
| 125 | + | ||
| 126 | +static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a) | ||
| 127 | +{ | ||
| 128 | + return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr); | ||
| 129 | +} | ||
| 130 | + | ||
| 131 | +static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a) | ||
| 132 | +{ | ||
| 133 | + return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl); | ||
| 134 | +} | ||
| 135 | + | ||
| 136 | /* | ||
| 137 | * Multiply and multiply accumulate | ||
| 138 | */ | ||
| 139 | -- | 205 | -- |
| 140 | 2.20.1 | 206 | 2.25.1 |
| 141 | |||
| 142 | diff view generated by jsdifflib |
| 1 | In do_ldst(), the calculation of the offset needs to be based on the | 1 | The target/arm/helper.c file is very long and is a grabbag of all |
|---|---|---|---|
| 2 | size of the memory access, not the size of the elements in the | 2 | kinds of functionality. We have already a debug_helper.c which has |
| 3 | vector. This meant we were getting it wrong for the widening and | 3 | code for implementing architectural debug. Move the code which |
| 4 | narrowing variants of the various VLDR and VSTR insns. | 4 | defines the debug-related system registers out to this file also. |
| 5 | This affects the define_debug_regs() function and the various | ||
| 6 | functions and arrays which are used only by it. | ||
| 7 | |||
| 8 | The functions raw_write() and arm_mdcr_el2_eff() and | ||
| 9 | define_debug_regs() now need to be global rather than local to | ||
| 10 | helper.c; everything else is pure code movement. | ||
| 5 | 11 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20210628135835.6690-2-peter.maydell@linaro.org | 14 | Message-id: 20220630194116.3438513-3-peter.maydell@linaro.org |
| 9 | --- | 15 | --- |
| 10 | target/arm/translate-mve.c | 17 +++++++++-------- | 16 | target/arm/cpregs.h | 3 + |
| 11 | 1 file changed, 9 insertions(+), 8 deletions(-) | 17 | target/arm/internals.h | 9 + |
| 18 | target/arm/debug_helper.c | 525 +++++++++++++++++++++++++++++++++++++ | ||
| 19 | target/arm/helper.c | 531 +------------------------------------- | ||
| 20 | 4 files changed, 538 insertions(+), 530 deletions(-) | ||
| 12 | 21 | ||
| 13 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | 22 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
| 14 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/target/arm/translate-mve.c | 24 | --- a/target/arm/cpregs.h |
| 16 | +++ b/target/arm/translate-mve.c | 25 | +++ b/target/arm/cpregs.h |
| 17 | @@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s) | 26 | @@ -XXX,XX +XXX,XX @@ void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
| 27 | /* CPReadFn that can be used for read-as-zero behaviour */ | ||
| 28 | uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); | ||
| 29 | |||
| 30 | +/* CPWriteFn that just writes the value to ri->fieldoffset */ | ||
| 31 | +void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); | ||
| 32 | + | ||
| 33 | /* | ||
| 34 | * CPResetFn that does nothing, for use if no reset is required even | ||
| 35 | * if fieldoffset is non zero. | ||
| 36 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
| 37 | index XXXXXXX..XXXXXXX 100644 | ||
| 38 | --- a/target/arm/internals.h | ||
| 39 | +++ b/target/arm/internals.h | ||
| 40 | @@ -XXX,XX +XXX,XX @@ int exception_target_el(CPUARMState *env); | ||
| 41 | bool arm_singlestep_active(CPUARMState *env); | ||
| 42 | bool arm_generate_debug_exceptions(CPUARMState *env); | ||
| 43 | |||
| 44 | +/* Add the cpreg definitions for debug related system registers */ | ||
| 45 | +void define_debug_regs(ARMCPU *cpu); | ||
| 46 | + | ||
| 47 | +/* Effective value of MDCR_EL2 */ | ||
| 48 | +static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) | ||
| 49 | +{ | ||
| 50 | + return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; | ||
| 51 | +} | ||
| 52 | + | ||
| 53 | /* Powers of 2 for sve_vq_map et al. */ | ||
| 54 | #define SVE_VQ_POW2_MAP \ | ||
| 55 | ((1 << (1 - 1)) | (1 << (2 - 1)) | \ | ||
| 56 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | ||
| 57 | index XXXXXXX..XXXXXXX 100644 | ||
| 58 | --- a/target/arm/debug_helper.c | ||
| 59 | +++ b/target/arm/debug_helper.c | ||
| 60 | @@ -XXX,XX +XXX,XX @@ | ||
| 61 | * SPDX-License-Identifier: GPL-2.0-or-later | ||
| 62 | */ | ||
| 63 | #include "qemu/osdep.h" | ||
| 64 | +#include "qemu/log.h" | ||
| 65 | #include "cpu.h" | ||
| 66 | #include "internals.h" | ||
| 67 | +#include "cpregs.h" | ||
| 68 | #include "exec/exec-all.h" | ||
| 69 | #include "exec/helper-proto.h" | ||
| 70 | |||
| 71 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) | ||
| 72 | raise_exception_debug(env, EXCP_UDEF, syndrome); | ||
| 73 | } | ||
| 74 | |||
| 75 | +/* | ||
| 76 | + * Check for traps to "powerdown debug" registers, which are controlled | ||
| 77 | + * by MDCR.TDOSA | ||
| 78 | + */ | ||
| 79 | +static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 80 | + bool isread) | ||
| 81 | +{ | ||
| 82 | + int el = arm_current_el(env); | ||
| 83 | + uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); | ||
| 84 | + bool mdcr_el2_tdosa = (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TDE) || | ||
| 85 | + (arm_hcr_el2_eff(env) & HCR_TGE); | ||
| 86 | + | ||
| 87 | + if (el < 2 && mdcr_el2_tdosa) { | ||
| 88 | + return CP_ACCESS_TRAP_EL2; | ||
| 89 | + } | ||
| 90 | + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { | ||
| 91 | + return CP_ACCESS_TRAP_EL3; | ||
| 92 | + } | ||
| 93 | + return CP_ACCESS_OK; | ||
| 94 | +} | ||
| 95 | + | ||
| 96 | +/* | ||
| 97 | + * Check for traps to "debug ROM" registers, which are controlled | ||
| 98 | + * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. | ||
| 99 | + */ | ||
| 100 | +static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 101 | + bool isread) | ||
| 102 | +{ | ||
| 103 | + int el = arm_current_el(env); | ||
| 104 | + uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); | ||
| 105 | + bool mdcr_el2_tdra = (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE) || | ||
| 106 | + (arm_hcr_el2_eff(env) & HCR_TGE); | ||
| 107 | + | ||
| 108 | + if (el < 2 && mdcr_el2_tdra) { | ||
| 109 | + return CP_ACCESS_TRAP_EL2; | ||
| 110 | + } | ||
| 111 | + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | ||
| 112 | + return CP_ACCESS_TRAP_EL3; | ||
| 113 | + } | ||
| 114 | + return CP_ACCESS_OK; | ||
| 115 | +} | ||
| 116 | + | ||
| 117 | +/* | ||
| 118 | + * Check for traps to general debug registers, which are controlled | ||
| 119 | + * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. | ||
| 120 | + */ | ||
| 121 | +static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 122 | + bool isread) | ||
| 123 | +{ | ||
| 124 | + int el = arm_current_el(env); | ||
| 125 | + uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); | ||
| 126 | + bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || | ||
| 127 | + (arm_hcr_el2_eff(env) & HCR_TGE); | ||
| 128 | + | ||
| 129 | + if (el < 2 && mdcr_el2_tda) { | ||
| 130 | + return CP_ACCESS_TRAP_EL2; | ||
| 131 | + } | ||
| 132 | + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | ||
| 133 | + return CP_ACCESS_TRAP_EL3; | ||
| 134 | + } | ||
| 135 | + return CP_ACCESS_OK; | ||
| 136 | +} | ||
| 137 | + | ||
| 138 | +static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 139 | + uint64_t value) | ||
| 140 | +{ | ||
| 141 | + /* | ||
| 142 | + * Writes to OSLAR_EL1 may update the OS lock status, which can be | ||
| 143 | + * read via a bit in OSLSR_EL1. | ||
| 144 | + */ | ||
| 145 | + int oslock; | ||
| 146 | + | ||
| 147 | + if (ri->state == ARM_CP_STATE_AA32) { | ||
| 148 | + oslock = (value == 0xC5ACCE55); | ||
| 149 | + } else { | ||
| 150 | + oslock = value & 1; | ||
| 151 | + } | ||
| 152 | + | ||
| 153 | + env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); | ||
| 154 | +} | ||
| 155 | + | ||
| 156 | +static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
| 157 | + /* | ||
| 158 | + * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped | ||
| 159 | + * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; | ||
| 160 | + * unlike DBGDRAR it is never accessible from EL0. | ||
| 161 | + * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | ||
| 162 | + * accessor. | ||
| 163 | + */ | ||
| 164 | + { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | ||
| 165 | + .access = PL0_R, .accessfn = access_tdra, | ||
| 166 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 167 | + { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, | ||
| 168 | + .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | ||
| 169 | + .access = PL1_R, .accessfn = access_tdra, | ||
| 170 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 171 | + { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, | ||
| 172 | + .access = PL0_R, .accessfn = access_tdra, | ||
| 173 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 174 | + /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ | ||
| 175 | + { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, | ||
| 176 | + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | ||
| 177 | + .access = PL1_RW, .accessfn = access_tda, | ||
| 178 | + .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), | ||
| 179 | + .resetvalue = 0 }, | ||
| 180 | + /* | ||
| 181 | + * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external | ||
| 182 | + * Debug Communication Channel is not implemented. | ||
| 183 | + */ | ||
| 184 | + { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64, | ||
| 185 | + .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0, | ||
| 186 | + .access = PL0_R, .accessfn = access_tda, | ||
| 187 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 188 | + /* | ||
| 189 | + * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as | ||
| 190 | + * it is unlikely a guest will care. | ||
| 191 | + * We don't implement the configurable EL0 access. | ||
| 192 | + */ | ||
| 193 | + { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32, | ||
| 194 | + .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | ||
| 195 | + .type = ARM_CP_ALIAS, | ||
| 196 | + .access = PL1_R, .accessfn = access_tda, | ||
| 197 | + .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, | ||
| 198 | + { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, | ||
| 199 | + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | ||
| 200 | + .access = PL1_W, .type = ARM_CP_NO_RAW, | ||
| 201 | + .accessfn = access_tdosa, | ||
| 202 | + .writefn = oslar_write }, | ||
| 203 | + { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, | ||
| 204 | + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, | ||
| 205 | + .access = PL1_R, .resetvalue = 10, | ||
| 206 | + .accessfn = access_tdosa, | ||
| 207 | + .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, | ||
| 208 | + /* Dummy OSDLR_EL1: 32-bit Linux will read this */ | ||
| 209 | + { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | ||
| 210 | + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | ||
| 211 | + .access = PL1_RW, .accessfn = access_tdosa, | ||
| 212 | + .type = ARM_CP_NOP }, | ||
| 213 | + /* | ||
| 214 | + * Dummy DBGVCR: Linux wants to clear this on startup, but we don't | ||
| 215 | + * implement vector catch debug events yet. | ||
| 216 | + */ | ||
| 217 | + { .name = "DBGVCR", | ||
| 218 | + .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | ||
| 219 | + .access = PL1_RW, .accessfn = access_tda, | ||
| 220 | + .type = ARM_CP_NOP }, | ||
| 221 | + /* | ||
| 222 | + * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor | ||
| 223 | + * to save and restore a 32-bit guest's DBGVCR) | ||
| 224 | + */ | ||
| 225 | + { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | ||
| 226 | + .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | ||
| 227 | + .access = PL2_RW, .accessfn = access_tda, | ||
| 228 | + .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, | ||
| 229 | + /* | ||
| 230 | + * Dummy MDCCINT_EL1, since we don't implement the Debug Communications | ||
| 231 | + * Channel but Linux may try to access this register. The 32-bit | ||
| 232 | + * alias is DBGDCCINT. | ||
| 233 | + */ | ||
| 234 | + { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, | ||
| 235 | + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | ||
| 236 | + .access = PL1_RW, .accessfn = access_tda, | ||
| 237 | + .type = ARM_CP_NOP }, | ||
| 238 | +}; | ||
| 239 | + | ||
| 240 | +static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | ||
| 241 | + /* 64 bit access versions of the (dummy) debug registers */ | ||
| 242 | + { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | ||
| 243 | + .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 244 | + { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | ||
| 245 | + .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 246 | +}; | ||
| 247 | + | ||
| 248 | +void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
| 249 | +{ | ||
| 250 | + CPUARMState *env = &cpu->env; | ||
| 251 | + vaddr len = 0; | ||
| 252 | + vaddr wvr = env->cp15.dbgwvr[n]; | ||
| 253 | + uint64_t wcr = env->cp15.dbgwcr[n]; | ||
| 254 | + int mask; | ||
| 255 | + int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | ||
| 256 | + | ||
| 257 | + if (env->cpu_watchpoint[n]) { | ||
| 258 | + cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | ||
| 259 | + env->cpu_watchpoint[n] = NULL; | ||
| 260 | + } | ||
| 261 | + | ||
| 262 | + if (!FIELD_EX64(wcr, DBGWCR, E)) { | ||
| 263 | + /* E bit clear : watchpoint disabled */ | ||
| 264 | + return; | ||
| 265 | + } | ||
| 266 | + | ||
| 267 | + switch (FIELD_EX64(wcr, DBGWCR, LSC)) { | ||
| 268 | + case 0: | ||
| 269 | + /* LSC 00 is reserved and must behave as if the wp is disabled */ | ||
| 270 | + return; | ||
| 271 | + case 1: | ||
| 272 | + flags |= BP_MEM_READ; | ||
| 273 | + break; | ||
| 274 | + case 2: | ||
| 275 | + flags |= BP_MEM_WRITE; | ||
| 276 | + break; | ||
| 277 | + case 3: | ||
| 278 | + flags |= BP_MEM_ACCESS; | ||
| 279 | + break; | ||
| 280 | + } | ||
| 281 | + | ||
| 282 | + /* | ||
| 283 | + * Attempts to use both MASK and BAS fields simultaneously are | ||
| 284 | + * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | ||
| 285 | + * thus generating a watchpoint for every byte in the masked region. | ||
| 286 | + */ | ||
| 287 | + mask = FIELD_EX64(wcr, DBGWCR, MASK); | ||
| 288 | + if (mask == 1 || mask == 2) { | ||
| 289 | + /* | ||
| 290 | + * Reserved values of MASK; we must act as if the mask value was | ||
| 291 | + * some non-reserved value, or as if the watchpoint were disabled. | ||
| 292 | + * We choose the latter. | ||
| 293 | + */ | ||
| 294 | + return; | ||
| 295 | + } else if (mask) { | ||
| 296 | + /* Watchpoint covers an aligned area up to 2GB in size */ | ||
| 297 | + len = 1ULL << mask; | ||
| 298 | + /* | ||
| 299 | + * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | ||
| 300 | + * whether the watchpoint fires when the unmasked bits match; we opt | ||
| 301 | + * to generate the exceptions. | ||
| 302 | + */ | ||
| 303 | + wvr &= ~(len - 1); | ||
| 304 | + } else { | ||
| 305 | + /* Watchpoint covers bytes defined by the byte address select bits */ | ||
| 306 | + int bas = FIELD_EX64(wcr, DBGWCR, BAS); | ||
| 307 | + int basstart; | ||
| 308 | + | ||
| 309 | + if (extract64(wvr, 2, 1)) { | ||
| 310 | + /* | ||
| 311 | + * Deprecated case of an only 4-aligned address. BAS[7:4] are | ||
| 312 | + * ignored, and BAS[3:0] define which bytes to watch. | ||
| 313 | + */ | ||
| 314 | + bas &= 0xf; | ||
| 315 | + } | ||
| 316 | + | ||
| 317 | + if (bas == 0) { | ||
| 318 | + /* This must act as if the watchpoint is disabled */ | ||
| 319 | + return; | ||
| 320 | + } | ||
| 321 | + | ||
| 322 | + /* | ||
| 323 | + * The BAS bits are supposed to be programmed to indicate a contiguous | ||
| 324 | + * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | ||
| 325 | + * we fire for each byte in the word/doubleword addressed by the WVR. | ||
| 326 | + * We choose to ignore any non-zero bits after the first range of 1s. | ||
| 327 | + */ | ||
| 328 | + basstart = ctz32(bas); | ||
| 329 | + len = cto32(bas >> basstart); | ||
| 330 | + wvr += basstart; | ||
| 331 | + } | ||
| 332 | + | ||
| 333 | + cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | ||
| 334 | + &env->cpu_watchpoint[n]); | ||
| 335 | +} | ||
| 336 | + | ||
| 337 | +void hw_watchpoint_update_all(ARMCPU *cpu) | ||
| 338 | +{ | ||
| 339 | + int i; | ||
| 340 | + CPUARMState *env = &cpu->env; | ||
| 341 | + | ||
| 342 | + /* | ||
| 343 | + * Completely clear out existing QEMU watchpoints and our array, to | ||
| 344 | + * avoid possible stale entries following migration load. | ||
| 345 | + */ | ||
| 346 | + cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | ||
| 347 | + memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | ||
| 348 | + | ||
| 349 | + for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | ||
| 350 | + hw_watchpoint_update(cpu, i); | ||
| 351 | + } | ||
| 352 | +} | ||
| 353 | + | ||
| 354 | +static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 355 | + uint64_t value) | ||
| 356 | +{ | ||
| 357 | + ARMCPU *cpu = env_archcpu(env); | ||
| 358 | + int i = ri->crm; | ||
| 359 | + | ||
| 360 | + /* | ||
| 361 | + * Bits [1:0] are RES0. | ||
| 362 | + * | ||
| 363 | + * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA) | ||
| 364 | + * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if | ||
| 365 | + * they contain the value written. It is CONSTRAINED UNPREDICTABLE | ||
| 366 | + * whether the RESS bits are ignored when comparing an address. | ||
| 367 | + * | ||
| 368 | + * Therefore we are allowed to compare the entire register, which lets | ||
| 369 | + * us avoid considering whether or not FEAT_LVA is actually enabled. | ||
| 370 | + */ | ||
| 371 | + value &= ~3ULL; | ||
| 372 | + | ||
| 373 | + raw_write(env, ri, value); | ||
| 374 | + hw_watchpoint_update(cpu, i); | ||
| 375 | +} | ||
| 376 | + | ||
| 377 | +static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 378 | + uint64_t value) | ||
| 379 | +{ | ||
| 380 | + ARMCPU *cpu = env_archcpu(env); | ||
| 381 | + int i = ri->crm; | ||
| 382 | + | ||
| 383 | + raw_write(env, ri, value); | ||
| 384 | + hw_watchpoint_update(cpu, i); | ||
| 385 | +} | ||
| 386 | + | ||
| 387 | +void hw_breakpoint_update(ARMCPU *cpu, int n) | ||
| 388 | +{ | ||
| 389 | + CPUARMState *env = &cpu->env; | ||
| 390 | + uint64_t bvr = env->cp15.dbgbvr[n]; | ||
| 391 | + uint64_t bcr = env->cp15.dbgbcr[n]; | ||
| 392 | + vaddr addr; | ||
| 393 | + int bt; | ||
| 394 | + int flags = BP_CPU; | ||
| 395 | + | ||
| 396 | + if (env->cpu_breakpoint[n]) { | ||
| 397 | + cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | ||
| 398 | + env->cpu_breakpoint[n] = NULL; | ||
| 399 | + } | ||
| 400 | + | ||
| 401 | + if (!extract64(bcr, 0, 1)) { | ||
| 402 | + /* E bit clear : watchpoint disabled */ | ||
| 403 | + return; | ||
| 404 | + } | ||
| 405 | + | ||
| 406 | + bt = extract64(bcr, 20, 4); | ||
| 407 | + | ||
| 408 | + switch (bt) { | ||
| 409 | + case 4: /* unlinked address mismatch (reserved if AArch64) */ | ||
| 410 | + case 5: /* linked address mismatch (reserved if AArch64) */ | ||
| 411 | + qemu_log_mask(LOG_UNIMP, | ||
| 412 | + "arm: address mismatch breakpoint types not implemented\n"); | ||
| 413 | + return; | ||
| 414 | + case 0: /* unlinked address match */ | ||
| 415 | + case 1: /* linked address match */ | ||
| 416 | + { | ||
| 417 | + /* | ||
| 418 | + * Bits [1:0] are RES0. | ||
| 419 | + * | ||
| 420 | + * It is IMPLEMENTATION DEFINED whether bits [63:49] | ||
| 421 | + * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit | ||
| 422 | + * of the VA field ([48] or [52] for FEAT_LVA), or whether the | ||
| 423 | + * value is read as written. It is CONSTRAINED UNPREDICTABLE | ||
| 424 | + * whether the RESS bits are ignored when comparing an address. | ||
| 425 | + * Therefore we are allowed to compare the entire register, which | ||
| 426 | + * lets us avoid considering whether FEAT_LVA is actually enabled. | ||
| 427 | + * | ||
| 428 | + * The BAS field is used to allow setting breakpoints on 16-bit | ||
| 429 | + * wide instructions; it is CONSTRAINED UNPREDICTABLE whether | ||
| 430 | + * a bp will fire if the addresses covered by the bp and the addresses | ||
| 431 | + * covered by the insn overlap but the insn doesn't start at the | ||
| 432 | + * start of the bp address range. We choose to require the insn and | ||
| 433 | + * the bp to have the same address. The constraints on writing to | ||
| 434 | + * BAS enforced in dbgbcr_write mean we have only four cases: | ||
| 435 | + * 0b0000 => no breakpoint | ||
| 436 | + * 0b0011 => breakpoint on addr | ||
| 437 | + * 0b1100 => breakpoint on addr + 2 | ||
| 438 | + * 0b1111 => breakpoint on addr | ||
| 439 | + * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | ||
| 440 | + */ | ||
| 441 | + int bas = extract64(bcr, 5, 4); | ||
| 442 | + addr = bvr & ~3ULL; | ||
| 443 | + if (bas == 0) { | ||
| 444 | + return; | ||
| 445 | + } | ||
| 446 | + if (bas == 0xc) { | ||
| 447 | + addr += 2; | ||
| 448 | + } | ||
| 449 | + break; | ||
| 450 | + } | ||
| 451 | + case 2: /* unlinked context ID match */ | ||
| 452 | + case 8: /* unlinked VMID match (reserved if no EL2) */ | ||
| 453 | + case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | ||
| 454 | + qemu_log_mask(LOG_UNIMP, | ||
| 455 | + "arm: unlinked context breakpoint types not implemented\n"); | ||
| 456 | + return; | ||
| 457 | + case 9: /* linked VMID match (reserved if no EL2) */ | ||
| 458 | + case 11: /* linked context ID and VMID match (reserved if no EL2) */ | ||
| 459 | + case 3: /* linked context ID match */ | ||
| 460 | + default: | ||
| 461 | + /* | ||
| 462 | + * We must generate no events for Linked context matches (unless | ||
| 463 | + * they are linked to by some other bp/wp, which is handled in | ||
| 464 | + * updates for the linking bp/wp). We choose to also generate no events | ||
| 465 | + * for reserved values. | ||
| 466 | + */ | ||
| 467 | + return; | ||
| 468 | + } | ||
| 469 | + | ||
| 470 | + cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | ||
| 471 | +} | ||
| 472 | + | ||
| 473 | +void hw_breakpoint_update_all(ARMCPU *cpu) | ||
| 474 | +{ | ||
| 475 | + int i; | ||
| 476 | + CPUARMState *env = &cpu->env; | ||
| 477 | + | ||
| 478 | + /* | ||
| 479 | + * Completely clear out existing QEMU breakpoints and our array, to | ||
| 480 | + * avoid possible stale entries following migration load. | ||
| 481 | + */ | ||
| 482 | + cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | ||
| 483 | + memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | ||
| 484 | + | ||
| 485 | + for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | ||
| 486 | + hw_breakpoint_update(cpu, i); | ||
| 487 | + } | ||
| 488 | +} | ||
| 489 | + | ||
| 490 | +static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 491 | + uint64_t value) | ||
| 492 | +{ | ||
| 493 | + ARMCPU *cpu = env_archcpu(env); | ||
| 494 | + int i = ri->crm; | ||
| 495 | + | ||
| 496 | + raw_write(env, ri, value); | ||
| 497 | + hw_breakpoint_update(cpu, i); | ||
| 498 | +} | ||
| 499 | + | ||
| 500 | +static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 501 | + uint64_t value) | ||
| 502 | +{ | ||
| 503 | + ARMCPU *cpu = env_archcpu(env); | ||
| 504 | + int i = ri->crm; | ||
| 505 | + | ||
| 506 | + /* | ||
| 507 | + * BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | ||
| 508 | + * copy of BAS[0]. | ||
| 509 | + */ | ||
| 510 | + value = deposit64(value, 6, 1, extract64(value, 5, 1)); | ||
| 511 | + value = deposit64(value, 8, 1, extract64(value, 7, 1)); | ||
| 512 | + | ||
| 513 | + raw_write(env, ri, value); | ||
| 514 | + hw_breakpoint_update(cpu, i); | ||
| 515 | +} | ||
| 516 | + | ||
| 517 | +void define_debug_regs(ARMCPU *cpu) | ||
| 518 | +{ | ||
| 519 | + /* | ||
| 520 | + * Define v7 and v8 architectural debug registers. | ||
| 521 | + * These are just dummy implementations for now. | ||
| 522 | + */ | ||
| 523 | + int i; | ||
| 524 | + int wrps, brps, ctx_cmps; | ||
| 525 | + | ||
| 526 | + /* | ||
| 527 | + * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot | ||
| 528 | + * use AArch32. Given that bit 15 is RES1, if the value is 0 then | ||
| 529 | + * the register must not exist for this cpu. | ||
| 530 | + */ | ||
| 531 | + if (cpu->isar.dbgdidr != 0) { | ||
| 532 | + ARMCPRegInfo dbgdidr = { | ||
| 533 | + .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, | ||
| 534 | + .opc1 = 0, .opc2 = 0, | ||
| 535 | + .access = PL0_R, .accessfn = access_tda, | ||
| 536 | + .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr, | ||
| 537 | + }; | ||
| 538 | + define_one_arm_cp_reg(cpu, &dbgdidr); | ||
| 539 | + } | ||
| 540 | + | ||
| 541 | + brps = arm_num_brps(cpu); | ||
| 542 | + wrps = arm_num_wrps(cpu); | ||
| 543 | + ctx_cmps = arm_num_ctx_cmps(cpu); | ||
| 544 | + | ||
| 545 | + assert(ctx_cmps <= brps); | ||
| 546 | + | ||
| 547 | + define_arm_cp_regs(cpu, debug_cp_reginfo); | ||
| 548 | + | ||
| 549 | + if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | ||
| 550 | + define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | ||
| 551 | + } | ||
| 552 | + | ||
| 553 | + for (i = 0; i < brps; i++) { | ||
| 554 | + char *dbgbvr_el1_name = g_strdup_printf("DBGBVR%d_EL1", i); | ||
| 555 | + char *dbgbcr_el1_name = g_strdup_printf("DBGBCR%d_EL1", i); | ||
| 556 | + ARMCPRegInfo dbgregs[] = { | ||
| 557 | + { .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH, | ||
| 558 | + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | ||
| 559 | + .access = PL1_RW, .accessfn = access_tda, | ||
| 560 | + .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), | ||
| 561 | + .writefn = dbgbvr_write, .raw_writefn = raw_write | ||
| 562 | + }, | ||
| 563 | + { .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH, | ||
| 564 | + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | ||
| 565 | + .access = PL1_RW, .accessfn = access_tda, | ||
| 566 | + .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), | ||
| 567 | + .writefn = dbgbcr_write, .raw_writefn = raw_write | ||
| 568 | + }, | ||
| 569 | + }; | ||
| 570 | + define_arm_cp_regs(cpu, dbgregs); | ||
| 571 | + g_free(dbgbvr_el1_name); | ||
| 572 | + g_free(dbgbcr_el1_name); | ||
| 573 | + } | ||
| 574 | + | ||
| 575 | + for (i = 0; i < wrps; i++) { | ||
| 576 | + char *dbgwvr_el1_name = g_strdup_printf("DBGWVR%d_EL1", i); | ||
| 577 | + char *dbgwcr_el1_name = g_strdup_printf("DBGWCR%d_EL1", i); | ||
| 578 | + ARMCPRegInfo dbgregs[] = { | ||
| 579 | + { .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH, | ||
| 580 | + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | ||
| 581 | + .access = PL1_RW, .accessfn = access_tda, | ||
| 582 | + .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), | ||
| 583 | + .writefn = dbgwvr_write, .raw_writefn = raw_write | ||
| 584 | + }, | ||
| 585 | + { .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH, | ||
| 586 | + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | ||
| 587 | + .access = PL1_RW, .accessfn = access_tda, | ||
| 588 | + .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), | ||
| 589 | + .writefn = dbgwcr_write, .raw_writefn = raw_write | ||
| 590 | + }, | ||
| 591 | + }; | ||
| 592 | + define_arm_cp_regs(cpu, dbgregs); | ||
| 593 | + g_free(dbgwvr_el1_name); | ||
| 594 | + g_free(dbgwcr_el1_name); | ||
| 595 | + } | ||
| 596 | +} | ||
| 597 | + | ||
| 598 | #if !defined(CONFIG_USER_ONLY) | ||
| 599 | |||
| 600 | vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) | ||
| 601 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 602 | index XXXXXXX..XXXXXXX 100644 | ||
| 603 | --- a/target/arm/helper.c | ||
| 604 | +++ b/target/arm/helper.c | ||
| 605 | @@ -XXX,XX +XXX,XX @@ static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
| 18 | } | 606 | } |
| 19 | } | 607 | } |
| 20 | 608 | ||
| 21 | -static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) | 609 | -static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 22 | +static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn, | 610 | - uint64_t value) |
| 23 | + unsigned msize) | 611 | +void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
| 24 | { | 612 | { |
| 25 | TCGv_i32 addr; | 613 | assert(ri->fieldoffset); |
| 26 | uint32_t offset; | 614 | if (cpreg_field_is_64bit(ri)) { |
| 27 | @@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) | 615 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, |
| 28 | return true; | 616 | return CP_ACCESS_TRAP_UNCATEGORIZED; |
| 29 | } | ||
| 30 | |||
| 31 | - offset = a->imm << a->size; | ||
| 32 | + offset = a->imm << msize; | ||
| 33 | if (!a->a) { | ||
| 34 | offset = -offset; | ||
| 35 | } | ||
| 36 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) | ||
| 37 | { gen_helper_mve_vstrw, gen_helper_mve_vldrw }, | ||
| 38 | { NULL, NULL } | ||
| 39 | }; | ||
| 40 | - return do_ldst(s, a, ldstfns[a->size][a->l]); | ||
| 41 | + return do_ldst(s, a, ldstfns[a->size][a->l], a->size); | ||
| 42 | } | 617 | } |
| 43 | 618 | ||
| 44 | -#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \ | 619 | -static uint64_t arm_mdcr_el2_eff(CPUARMState *env) |
| 45 | +#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \ | 620 | -{ |
| 46 | static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \ | 621 | - return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; |
| 47 | { \ | 622 | -} |
| 48 | static MVEGenLdStFn * const ldstfns[2][2] = { \ | 623 | - |
| 49 | { gen_helper_mve_##ST, gen_helper_mve_##SLD }, \ | 624 | -/* |
| 50 | { NULL, gen_helper_mve_##ULD }, \ | 625 | - * Check for traps to "powerdown debug" registers, which are controlled |
| 51 | }; \ | 626 | - * by MDCR.TDOSA |
| 52 | - return do_ldst(s, a, ldstfns[a->u][a->l]); \ | 627 | - */ |
| 53 | + return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \ | 628 | -static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, |
| 54 | } | 629 | - bool isread) |
| 55 | 630 | -{ | |
| 56 | -DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h) | 631 | - int el = arm_current_el(env); |
| 57 | -DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w) | 632 | - uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
| 58 | -DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w) | 633 | - bool mdcr_el2_tdosa = (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TDE) || |
| 59 | +DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8) | 634 | - (arm_hcr_el2_eff(env) & HCR_TGE); |
| 60 | +DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8) | 635 | - |
| 61 | +DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16) | 636 | - if (el < 2 && mdcr_el2_tdosa) { |
| 62 | 637 | - return CP_ACCESS_TRAP_EL2; | |
| 63 | static bool trans_VDUP(DisasContext *s, arg_VDUP *a) | 638 | - } |
| 639 | - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { | ||
| 640 | - return CP_ACCESS_TRAP_EL3; | ||
| 641 | - } | ||
| 642 | - return CP_ACCESS_OK; | ||
| 643 | -} | ||
| 644 | - | ||
| 645 | -/* | ||
| 646 | - * Check for traps to "debug ROM" registers, which are controlled | ||
| 647 | - * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. | ||
| 648 | - */ | ||
| 649 | -static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 650 | - bool isread) | ||
| 651 | -{ | ||
| 652 | - int el = arm_current_el(env); | ||
| 653 | - uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); | ||
| 654 | - bool mdcr_el2_tdra = (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE) || | ||
| 655 | - (arm_hcr_el2_eff(env) & HCR_TGE); | ||
| 656 | - | ||
| 657 | - if (el < 2 && mdcr_el2_tdra) { | ||
| 658 | - return CP_ACCESS_TRAP_EL2; | ||
| 659 | - } | ||
| 660 | - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | ||
| 661 | - return CP_ACCESS_TRAP_EL3; | ||
| 662 | - } | ||
| 663 | - return CP_ACCESS_OK; | ||
| 664 | -} | ||
| 665 | - | ||
| 666 | -/* | ||
| 667 | - * Check for traps to general debug registers, which are controlled | ||
| 668 | - * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. | ||
| 669 | - */ | ||
| 670 | -static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 671 | - bool isread) | ||
| 672 | -{ | ||
| 673 | - int el = arm_current_el(env); | ||
| 674 | - uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); | ||
| 675 | - bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || | ||
| 676 | - (arm_hcr_el2_eff(env) & HCR_TGE); | ||
| 677 | - | ||
| 678 | - if (el < 2 && mdcr_el2_tda) { | ||
| 679 | - return CP_ACCESS_TRAP_EL2; | ||
| 680 | - } | ||
| 681 | - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { | ||
| 682 | - return CP_ACCESS_TRAP_EL3; | ||
| 683 | - } | ||
| 684 | - return CP_ACCESS_OK; | ||
| 685 | -} | ||
| 686 | - | ||
| 687 | /* Check for traps to performance monitor registers, which are controlled | ||
| 688 | * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. | ||
| 689 | */ | ||
| 690 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 691 | return CP_ACCESS_OK; | ||
| 692 | } | ||
| 693 | |||
| 694 | -static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 695 | - uint64_t value) | ||
| 696 | -{ | ||
| 697 | - /* | ||
| 698 | - * Writes to OSLAR_EL1 may update the OS lock status, which can be | ||
| 699 | - * read via a bit in OSLSR_EL1. | ||
| 700 | - */ | ||
| 701 | - int oslock; | ||
| 702 | - | ||
| 703 | - if (ri->state == ARM_CP_STATE_AA32) { | ||
| 704 | - oslock = (value == 0xC5ACCE55); | ||
| 705 | - } else { | ||
| 706 | - oslock = value & 1; | ||
| 707 | - } | ||
| 708 | - | ||
| 709 | - env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); | ||
| 710 | -} | ||
| 711 | - | ||
| 712 | -static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
| 713 | - /* | ||
| 714 | - * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped | ||
| 715 | - * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; | ||
| 716 | - * unlike DBGDRAR it is never accessible from EL0. | ||
| 717 | - * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64 | ||
| 718 | - * accessor. | ||
| 719 | - */ | ||
| 720 | - { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, | ||
| 721 | - .access = PL0_R, .accessfn = access_tdra, | ||
| 722 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 723 | - { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, | ||
| 724 | - .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | ||
| 725 | - .access = PL1_R, .accessfn = access_tdra, | ||
| 726 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 727 | - { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, | ||
| 728 | - .access = PL0_R, .accessfn = access_tdra, | ||
| 729 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 730 | - /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ | ||
| 731 | - { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, | ||
| 732 | - .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | ||
| 733 | - .access = PL1_RW, .accessfn = access_tda, | ||
| 734 | - .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), | ||
| 735 | - .resetvalue = 0 }, | ||
| 736 | - /* | ||
| 737 | - * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external | ||
| 738 | - * Debug Communication Channel is not implemented. | ||
| 739 | - */ | ||
| 740 | - { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64, | ||
| 741 | - .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0, | ||
| 742 | - .access = PL0_R, .accessfn = access_tda, | ||
| 743 | - .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
| 744 | - /* | ||
| 745 | - * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as | ||
| 746 | - * it is unlikely a guest will care. | ||
| 747 | - * We don't implement the configurable EL0 access. | ||
| 748 | - */ | ||
| 749 | - { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32, | ||
| 750 | - .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | ||
| 751 | - .type = ARM_CP_ALIAS, | ||
| 752 | - .access = PL1_R, .accessfn = access_tda, | ||
| 753 | - .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), }, | ||
| 754 | - { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH, | ||
| 755 | - .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | ||
| 756 | - .access = PL1_W, .type = ARM_CP_NO_RAW, | ||
| 757 | - .accessfn = access_tdosa, | ||
| 758 | - .writefn = oslar_write }, | ||
| 759 | - { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, | ||
| 760 | - .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, | ||
| 761 | - .access = PL1_R, .resetvalue = 10, | ||
| 762 | - .accessfn = access_tdosa, | ||
| 763 | - .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, | ||
| 764 | - /* Dummy OSDLR_EL1: 32-bit Linux will read this */ | ||
| 765 | - { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | ||
| 766 | - .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | ||
| 767 | - .access = PL1_RW, .accessfn = access_tdosa, | ||
| 768 | - .type = ARM_CP_NOP }, | ||
| 769 | - /* | ||
| 770 | - * Dummy DBGVCR: Linux wants to clear this on startup, but we don't | ||
| 771 | - * implement vector catch debug events yet. | ||
| 772 | - */ | ||
| 773 | - { .name = "DBGVCR", | ||
| 774 | - .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | ||
| 775 | - .access = PL1_RW, .accessfn = access_tda, | ||
| 776 | - .type = ARM_CP_NOP }, | ||
| 777 | - /* | ||
| 778 | - * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor | ||
| 779 | - * to save and restore a 32-bit guest's DBGVCR) | ||
| 780 | - */ | ||
| 781 | - { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64, | ||
| 782 | - .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0, | ||
| 783 | - .access = PL2_RW, .accessfn = access_tda, | ||
| 784 | - .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, | ||
| 785 | - /* | ||
| 786 | - * Dummy MDCCINT_EL1, since we don't implement the Debug Communications | ||
| 787 | - * Channel but Linux may try to access this register. The 32-bit | ||
| 788 | - * alias is DBGDCCINT. | ||
| 789 | - */ | ||
| 790 | - { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, | ||
| 791 | - .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | ||
| 792 | - .access = PL1_RW, .accessfn = access_tda, | ||
| 793 | - .type = ARM_CP_NOP }, | ||
| 794 | -}; | ||
| 795 | - | ||
| 796 | -static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | ||
| 797 | - /* 64 bit access versions of the (dummy) debug registers */ | ||
| 798 | - { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0, | ||
| 799 | - .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 800 | - { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0, | ||
| 801 | - .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 802 | -}; | ||
| 803 | - | ||
| 804 | /* | ||
| 805 | * Check for traps to RAS registers, which are controlled | ||
| 806 | * by HCR_EL2.TERR and SCR_EL3.TERR. | ||
| 807 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = { | ||
| 808 | }; | ||
| 809 | #endif /* TARGET_AARCH64 */ | ||
| 810 | |||
| 811 | -void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
| 812 | -{ | ||
| 813 | - CPUARMState *env = &cpu->env; | ||
| 814 | - vaddr len = 0; | ||
| 815 | - vaddr wvr = env->cp15.dbgwvr[n]; | ||
| 816 | - uint64_t wcr = env->cp15.dbgwcr[n]; | ||
| 817 | - int mask; | ||
| 818 | - int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | ||
| 819 | - | ||
| 820 | - if (env->cpu_watchpoint[n]) { | ||
| 821 | - cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | ||
| 822 | - env->cpu_watchpoint[n] = NULL; | ||
| 823 | - } | ||
| 824 | - | ||
| 825 | - if (!FIELD_EX64(wcr, DBGWCR, E)) { | ||
| 826 | - /* E bit clear : watchpoint disabled */ | ||
| 827 | - return; | ||
| 828 | - } | ||
| 829 | - | ||
| 830 | - switch (FIELD_EX64(wcr, DBGWCR, LSC)) { | ||
| 831 | - case 0: | ||
| 832 | - /* LSC 00 is reserved and must behave as if the wp is disabled */ | ||
| 833 | - return; | ||
| 834 | - case 1: | ||
| 835 | - flags |= BP_MEM_READ; | ||
| 836 | - break; | ||
| 837 | - case 2: | ||
| 838 | - flags |= BP_MEM_WRITE; | ||
| 839 | - break; | ||
| 840 | - case 3: | ||
| 841 | - flags |= BP_MEM_ACCESS; | ||
| 842 | - break; | ||
| 843 | - } | ||
| 844 | - | ||
| 845 | - /* | ||
| 846 | - * Attempts to use both MASK and BAS fields simultaneously are | ||
| 847 | - * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | ||
| 848 | - * thus generating a watchpoint for every byte in the masked region. | ||
| 849 | - */ | ||
| 850 | - mask = FIELD_EX64(wcr, DBGWCR, MASK); | ||
| 851 | - if (mask == 1 || mask == 2) { | ||
| 852 | - /* | ||
| 853 | - * Reserved values of MASK; we must act as if the mask value was | ||
| 854 | - * some non-reserved value, or as if the watchpoint were disabled. | ||
| 855 | - * We choose the latter. | ||
| 856 | - */ | ||
| 857 | - return; | ||
| 858 | - } else if (mask) { | ||
| 859 | - /* Watchpoint covers an aligned area up to 2GB in size */ | ||
| 860 | - len = 1ULL << mask; | ||
| 861 | - /* | ||
| 862 | - * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | ||
| 863 | - * whether the watchpoint fires when the unmasked bits match; we opt | ||
| 864 | - * to generate the exceptions. | ||
| 865 | - */ | ||
| 866 | - wvr &= ~(len - 1); | ||
| 867 | - } else { | ||
| 868 | - /* Watchpoint covers bytes defined by the byte address select bits */ | ||
| 869 | - int bas = FIELD_EX64(wcr, DBGWCR, BAS); | ||
| 870 | - int basstart; | ||
| 871 | - | ||
| 872 | - if (extract64(wvr, 2, 1)) { | ||
| 873 | - /* | ||
| 874 | - * Deprecated case of an only 4-aligned address. BAS[7:4] are | ||
| 875 | - * ignored, and BAS[3:0] define which bytes to watch. | ||
| 876 | - */ | ||
| 877 | - bas &= 0xf; | ||
| 878 | - } | ||
| 879 | - | ||
| 880 | - if (bas == 0) { | ||
| 881 | - /* This must act as if the watchpoint is disabled */ | ||
| 882 | - return; | ||
| 883 | - } | ||
| 884 | - | ||
| 885 | - /* | ||
| 886 | - * The BAS bits are supposed to be programmed to indicate a contiguous | ||
| 887 | - * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | ||
| 888 | - * we fire for each byte in the word/doubleword addressed by the WVR. | ||
| 889 | - * We choose to ignore any non-zero bits after the first range of 1s. | ||
| 890 | - */ | ||
| 891 | - basstart = ctz32(bas); | ||
| 892 | - len = cto32(bas >> basstart); | ||
| 893 | - wvr += basstart; | ||
| 894 | - } | ||
| 895 | - | ||
| 896 | - cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | ||
| 897 | - &env->cpu_watchpoint[n]); | ||
| 898 | -} | ||
| 899 | - | ||
| 900 | -void hw_watchpoint_update_all(ARMCPU *cpu) | ||
| 901 | -{ | ||
| 902 | - int i; | ||
| 903 | - CPUARMState *env = &cpu->env; | ||
| 904 | - | ||
| 905 | - /* | ||
| 906 | - * Completely clear out existing QEMU watchpoints and our array, to | ||
| 907 | - * avoid possible stale entries following migration load. | ||
| 908 | - */ | ||
| 909 | - cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | ||
| 910 | - memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | ||
| 911 | - | ||
| 912 | - for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | ||
| 913 | - hw_watchpoint_update(cpu, i); | ||
| 914 | - } | ||
| 915 | -} | ||
| 916 | - | ||
| 917 | -static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 918 | - uint64_t value) | ||
| 919 | -{ | ||
| 920 | - ARMCPU *cpu = env_archcpu(env); | ||
| 921 | - int i = ri->crm; | ||
| 922 | - | ||
| 923 | - /* | ||
| 924 | - * Bits [1:0] are RES0. | ||
| 925 | - * | ||
| 926 | - * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA) | ||
| 927 | - * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if | ||
| 928 | - * they contain the value written. It is CONSTRAINED UNPREDICTABLE | ||
| 929 | - * whether the RESS bits are ignored when comparing an address. | ||
| 930 | - * | ||
| 931 | - * Therefore we are allowed to compare the entire register, which lets | ||
| 932 | - * us avoid considering whether or not FEAT_LVA is actually enabled. | ||
| 933 | - */ | ||
| 934 | - value &= ~3ULL; | ||
| 935 | - | ||
| 936 | - raw_write(env, ri, value); | ||
| 937 | - hw_watchpoint_update(cpu, i); | ||
| 938 | -} | ||
| 939 | - | ||
| 940 | -static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 941 | - uint64_t value) | ||
| 942 | -{ | ||
| 943 | - ARMCPU *cpu = env_archcpu(env); | ||
| 944 | - int i = ri->crm; | ||
| 945 | - | ||
| 946 | - raw_write(env, ri, value); | ||
| 947 | - hw_watchpoint_update(cpu, i); | ||
| 948 | -} | ||
| 949 | - | ||
| 950 | -void hw_breakpoint_update(ARMCPU *cpu, int n) | ||
| 951 | -{ | ||
| 952 | - CPUARMState *env = &cpu->env; | ||
| 953 | - uint64_t bvr = env->cp15.dbgbvr[n]; | ||
| 954 | - uint64_t bcr = env->cp15.dbgbcr[n]; | ||
| 955 | - vaddr addr; | ||
| 956 | - int bt; | ||
| 957 | - int flags = BP_CPU; | ||
| 958 | - | ||
| 959 | - if (env->cpu_breakpoint[n]) { | ||
| 960 | - cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | ||
| 961 | - env->cpu_breakpoint[n] = NULL; | ||
| 962 | - } | ||
| 963 | - | ||
| 964 | - if (!extract64(bcr, 0, 1)) { | ||
| 965 | - /* E bit clear : watchpoint disabled */ | ||
| 966 | - return; | ||
| 967 | - } | ||
| 968 | - | ||
| 969 | - bt = extract64(bcr, 20, 4); | ||
| 970 | - | ||
| 971 | - switch (bt) { | ||
| 972 | - case 4: /* unlinked address mismatch (reserved if AArch64) */ | ||
| 973 | - case 5: /* linked address mismatch (reserved if AArch64) */ | ||
| 974 | - qemu_log_mask(LOG_UNIMP, | ||
| 975 | - "arm: address mismatch breakpoint types not implemented\n"); | ||
| 976 | - return; | ||
| 977 | - case 0: /* unlinked address match */ | ||
| 978 | - case 1: /* linked address match */ | ||
| 979 | - { | ||
| 980 | - /* | ||
| 981 | - * Bits [1:0] are RES0. | ||
| 982 | - * | ||
| 983 | - * It is IMPLEMENTATION DEFINED whether bits [63:49] | ||
| 984 | - * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit | ||
| 985 | - * of the VA field ([48] or [52] for FEAT_LVA), or whether the | ||
| 986 | - * value is read as written. It is CONSTRAINED UNPREDICTABLE | ||
| 987 | - * whether the RESS bits are ignored when comparing an address. | ||
| 988 | - * Therefore we are allowed to compare the entire register, which | ||
| 989 | - * lets us avoid considering whether FEAT_LVA is actually enabled. | ||
| 990 | - * | ||
| 991 | - * The BAS field is used to allow setting breakpoints on 16-bit | ||
| 992 | - * wide instructions; it is CONSTRAINED UNPREDICTABLE whether | ||
| 993 | - * a bp will fire if the addresses covered by the bp and the addresses | ||
| 994 | - * covered by the insn overlap but the insn doesn't start at the | ||
| 995 | - * start of the bp address range. We choose to require the insn and | ||
| 996 | - * the bp to have the same address. The constraints on writing to | ||
| 997 | - * BAS enforced in dbgbcr_write mean we have only four cases: | ||
| 998 | - * 0b0000 => no breakpoint | ||
| 999 | - * 0b0011 => breakpoint on addr | ||
| 1000 | - * 0b1100 => breakpoint on addr + 2 | ||
| 1001 | - * 0b1111 => breakpoint on addr | ||
| 1002 | - * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | ||
| 1003 | - */ | ||
| 1004 | - int bas = extract64(bcr, 5, 4); | ||
| 1005 | - addr = bvr & ~3ULL; | ||
| 1006 | - if (bas == 0) { | ||
| 1007 | - return; | ||
| 1008 | - } | ||
| 1009 | - if (bas == 0xc) { | ||
| 1010 | - addr += 2; | ||
| 1011 | - } | ||
| 1012 | - break; | ||
| 1013 | - } | ||
| 1014 | - case 2: /* unlinked context ID match */ | ||
| 1015 | - case 8: /* unlinked VMID match (reserved if no EL2) */ | ||
| 1016 | - case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | ||
| 1017 | - qemu_log_mask(LOG_UNIMP, | ||
| 1018 | - "arm: unlinked context breakpoint types not implemented\n"); | ||
| 1019 | - return; | ||
| 1020 | - case 9: /* linked VMID match (reserved if no EL2) */ | ||
| 1021 | - case 11: /* linked context ID and VMID match (reserved if no EL2) */ | ||
| 1022 | - case 3: /* linked context ID match */ | ||
| 1023 | - default: | ||
| 1024 | - /* | ||
| 1025 | - * We must generate no events for Linked context matches (unless | ||
| 1026 | - * they are linked to by some other bp/wp, which is handled in | ||
| 1027 | - * updates for the linking bp/wp). We choose to also generate no events | ||
| 1028 | - * for reserved values. | ||
| 1029 | - */ | ||
| 1030 | - return; | ||
| 1031 | - } | ||
| 1032 | - | ||
| 1033 | - cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | ||
| 1034 | -} | ||
| 1035 | - | ||
| 1036 | -void hw_breakpoint_update_all(ARMCPU *cpu) | ||
| 1037 | -{ | ||
| 1038 | - int i; | ||
| 1039 | - CPUARMState *env = &cpu->env; | ||
| 1040 | - | ||
| 1041 | - /* | ||
| 1042 | - * Completely clear out existing QEMU breakpoints and our array, to | ||
| 1043 | - * avoid possible stale entries following migration load. | ||
| 1044 | - */ | ||
| 1045 | - cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | ||
| 1046 | - memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | ||
| 1047 | - | ||
| 1048 | - for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | ||
| 1049 | - hw_breakpoint_update(cpu, i); | ||
| 1050 | - } | ||
| 1051 | -} | ||
| 1052 | - | ||
| 1053 | -static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 1054 | - uint64_t value) | ||
| 1055 | -{ | ||
| 1056 | - ARMCPU *cpu = env_archcpu(env); | ||
| 1057 | - int i = ri->crm; | ||
| 1058 | - | ||
| 1059 | - raw_write(env, ri, value); | ||
| 1060 | - hw_breakpoint_update(cpu, i); | ||
| 1061 | -} | ||
| 1062 | - | ||
| 1063 | -static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 1064 | - uint64_t value) | ||
| 1065 | -{ | ||
| 1066 | - ARMCPU *cpu = env_archcpu(env); | ||
| 1067 | - int i = ri->crm; | ||
| 1068 | - | ||
| 1069 | - /* | ||
| 1070 | - * BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only | ||
| 1071 | - * copy of BAS[0]. | ||
| 1072 | - */ | ||
| 1073 | - value = deposit64(value, 6, 1, extract64(value, 5, 1)); | ||
| 1074 | - value = deposit64(value, 8, 1, extract64(value, 7, 1)); | ||
| 1075 | - | ||
| 1076 | - raw_write(env, ri, value); | ||
| 1077 | - hw_breakpoint_update(cpu, i); | ||
| 1078 | -} | ||
| 1079 | - | ||
| 1080 | -static void define_debug_regs(ARMCPU *cpu) | ||
| 1081 | -{ | ||
| 1082 | - /* | ||
| 1083 | - * Define v7 and v8 architectural debug registers. | ||
| 1084 | - * These are just dummy implementations for now. | ||
| 1085 | - */ | ||
| 1086 | - int i; | ||
| 1087 | - int wrps, brps, ctx_cmps; | ||
| 1088 | - | ||
| 1089 | - /* | ||
| 1090 | - * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot | ||
| 1091 | - * use AArch32. Given that bit 15 is RES1, if the value is 0 then | ||
| 1092 | - * the register must not exist for this cpu. | ||
| 1093 | - */ | ||
| 1094 | - if (cpu->isar.dbgdidr != 0) { | ||
| 1095 | - ARMCPRegInfo dbgdidr = { | ||
| 1096 | - .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, | ||
| 1097 | - .opc1 = 0, .opc2 = 0, | ||
| 1098 | - .access = PL0_R, .accessfn = access_tda, | ||
| 1099 | - .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr, | ||
| 1100 | - }; | ||
| 1101 | - define_one_arm_cp_reg(cpu, &dbgdidr); | ||
| 1102 | - } | ||
| 1103 | - | ||
| 1104 | - brps = arm_num_brps(cpu); | ||
| 1105 | - wrps = arm_num_wrps(cpu); | ||
| 1106 | - ctx_cmps = arm_num_ctx_cmps(cpu); | ||
| 1107 | - | ||
| 1108 | - assert(ctx_cmps <= brps); | ||
| 1109 | - | ||
| 1110 | - define_arm_cp_regs(cpu, debug_cp_reginfo); | ||
| 1111 | - | ||
| 1112 | - if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { | ||
| 1113 | - define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); | ||
| 1114 | - } | ||
| 1115 | - | ||
| 1116 | - for (i = 0; i < brps; i++) { | ||
| 1117 | - char *dbgbvr_el1_name = g_strdup_printf("DBGBVR%d_EL1", i); | ||
| 1118 | - char *dbgbcr_el1_name = g_strdup_printf("DBGBCR%d_EL1", i); | ||
| 1119 | - ARMCPRegInfo dbgregs[] = { | ||
| 1120 | - { .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH, | ||
| 1121 | - .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | ||
| 1122 | - .access = PL1_RW, .accessfn = access_tda, | ||
| 1123 | - .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), | ||
| 1124 | - .writefn = dbgbvr_write, .raw_writefn = raw_write | ||
| 1125 | - }, | ||
| 1126 | - { .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH, | ||
| 1127 | - .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | ||
| 1128 | - .access = PL1_RW, .accessfn = access_tda, | ||
| 1129 | - .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), | ||
| 1130 | - .writefn = dbgbcr_write, .raw_writefn = raw_write | ||
| 1131 | - }, | ||
| 1132 | - }; | ||
| 1133 | - define_arm_cp_regs(cpu, dbgregs); | ||
| 1134 | - g_free(dbgbvr_el1_name); | ||
| 1135 | - g_free(dbgbcr_el1_name); | ||
| 1136 | - } | ||
| 1137 | - | ||
| 1138 | - for (i = 0; i < wrps; i++) { | ||
| 1139 | - char *dbgwvr_el1_name = g_strdup_printf("DBGWVR%d_EL1", i); | ||
| 1140 | - char *dbgwcr_el1_name = g_strdup_printf("DBGWCR%d_EL1", i); | ||
| 1141 | - ARMCPRegInfo dbgregs[] = { | ||
| 1142 | - { .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH, | ||
| 1143 | - .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | ||
| 1144 | - .access = PL1_RW, .accessfn = access_tda, | ||
| 1145 | - .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), | ||
| 1146 | - .writefn = dbgwvr_write, .raw_writefn = raw_write | ||
| 1147 | - }, | ||
| 1148 | - { .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH, | ||
| 1149 | - .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | ||
| 1150 | - .access = PL1_RW, .accessfn = access_tda, | ||
| 1151 | - .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), | ||
| 1152 | - .writefn = dbgwcr_write, .raw_writefn = raw_write | ||
| 1153 | - }, | ||
| 1154 | - }; | ||
| 1155 | - define_arm_cp_regs(cpu, dbgregs); | ||
| 1156 | - g_free(dbgwvr_el1_name); | ||
| 1157 | - g_free(dbgwcr_el1_name); | ||
| 1158 | - } | ||
| 1159 | -} | ||
| 1160 | - | ||
| 1161 | static void define_pmu_regs(ARMCPU *cpu) | ||
| 64 | { | 1162 | { |
| 1163 | /* | ||
| 65 | -- | 1164 | -- |
| 66 | 2.20.1 | 1165 | 2.25.1 |
| 67 | |||
| 68 | diff view generated by jsdifflib |
| 1 | Implement the MVE shifts by immediate, which perform shifts | 1 | The "OS Lock" in the Arm debug architecture is a way for software |
|---|---|---|---|
| 2 | on a single general-purpose register. | 2 | to suppress debug exceptions while it is trying to power down |
| 3 | a CPU and save the state of the breakpoint and watchpoint | ||
| 4 | registers. In QEMU we implemented the support for writing | ||
| 5 | the OS Lock bit via OSLAR_EL1 and reading it via OSLSR_EL1, | ||
| 6 | but didn't implement the actual behaviour. | ||
| 3 | 7 | ||
| 4 | These patterns overlap with the long-shift-by-immediates, | 8 | The required behaviour with the OS Lock set is: |
| 5 | so we have to rearrange the grouping a little here. | 9 | * debug exceptions (apart from BKPT insns) are suppressed |
| 10 | * some MDSCR_EL1 bits allow write access to the corresponding | ||
| 11 | EDSCR external debug status register that they shadow | ||
| 12 | (we can ignore this because we don't implement external debug) | ||
| 13 | * similarly with the OSECCR_EL1 which shadows the EDECCR | ||
| 14 | (but we don't implement OSECCR_EL1 anyway) | ||
| 15 | |||
| 16 | Implement the missing behaviour of suppressing debug | ||
| 17 | exceptions. | ||
| 6 | 18 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 9 | Message-id: 20210628135835.6690-18-peter.maydell@linaro.org | 21 | Message-id: 20220630194116.3438513-4-peter.maydell@linaro.org |
| 10 | --- | 22 | --- |
| 11 | target/arm/helper-mve.h | 3 ++ | 23 | target/arm/debug_helper.c | 3 +++ |
| 12 | target/arm/translate.h | 1 + | 24 | 1 file changed, 3 insertions(+) |
| 13 | target/arm/t32.decode | 31 ++++++++++++++----- | ||
| 14 | target/arm/mve_helper.c | 10 ++++++ | ||
| 15 | target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++-- | ||
| 16 | 5 files changed, 104 insertions(+), 9 deletions(-) | ||
| 17 | 25 | ||
| 18 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | 26 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
| 19 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
| 20 | --- a/target/arm/helper-mve.h | 28 | --- a/target/arm/debug_helper.c |
| 21 | +++ b/target/arm/helper-mve.h | 29 | +++ b/target/arm/debug_helper.c |
| 22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) | 30 | @@ -XXX,XX +XXX,XX @@ static bool aa32_generate_debug_exceptions(CPUARMState *env) |
| 23 | DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | 31 | */ |
| 24 | DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32) | 32 | bool arm_generate_debug_exceptions(CPUARMState *env) |
| 25 | DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
| 26 | + | ||
| 27 | +DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | ||
| 28 | +DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | ||
| 29 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
| 30 | index XXXXXXX..XXXXXXX 100644 | ||
| 31 | --- a/target/arm/translate.h | ||
| 32 | +++ b/target/arm/translate.h | ||
| 33 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
| 34 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
| 35 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | ||
| 36 | typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); | ||
| 37 | +typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); | ||
| 38 | |||
| 39 | /** | ||
| 40 | * arm_tbflags_from_tb: | ||
| 41 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
| 42 | index XXXXXXX..XXXXXXX 100644 | ||
| 43 | --- a/target/arm/t32.decode | ||
| 44 | +++ b/target/arm/t32.decode | ||
| 45 | @@ -XXX,XX +XXX,XX @@ | ||
| 46 | |||
| 47 | &mve_shl_ri rdalo rdahi shim | ||
| 48 | &mve_shl_rr rdalo rdahi rm | ||
| 49 | +&mve_sh_ri rda shim | ||
| 50 | |||
| 51 | # rdahi: bits [3:1] from insn, bit 0 is 1 | ||
| 52 | # rdalo: bits [3:1] from insn, bit 0 is 0 | ||
| 53 | @@ -XXX,XX +XXX,XX @@ | ||
| 54 | &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
| 55 | @mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \ | ||
| 56 | &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
| 57 | +@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \ | ||
| 58 | + &mve_sh_ri shim=%imm5_12_6 | ||
| 59 | |||
| 60 | { | 33 | { |
| 61 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | 34 | + if (env->cp15.oslsr_el1 & 1) { |
| 62 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
| 63 | # the rest fall through (where ORR_rrri and MOV_rxri will end up | ||
| 64 | # handling them as r13 and r15 accesses with the same semantics as A32). | ||
| 65 | [ | ||
| 66 | - LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
| 67 | - LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
| 68 | - ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
| 69 | + { | ||
| 70 | + UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri | ||
| 71 | + LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
| 72 | + UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
| 73 | + } | ||
| 74 | |||
| 75 | - UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
| 76 | - URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
| 77 | - SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
| 78 | - SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
| 79 | + { | ||
| 80 | + URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri | ||
| 81 | + LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
| 82 | + URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
| 83 | + } | ||
| 84 | + | ||
| 85 | + { | ||
| 86 | + SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri | ||
| 87 | + ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
| 88 | + SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
| 89 | + } | ||
| 90 | + | ||
| 91 | + { | ||
| 92 | + SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri | ||
| 93 | + SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
| 94 | + } | ||
| 95 | |||
| 96 | LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | ||
| 97 | ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | ||
| 98 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
| 99 | index XXXXXXX..XXXXXXX 100644 | ||
| 100 | --- a/target/arm/mve_helper.c | ||
| 101 | +++ b/target/arm/mve_helper.c | ||
| 102 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
| 103 | { | ||
| 104 | return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); | ||
| 105 | } | ||
| 106 | + | ||
| 107 | +uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
| 108 | +{ | ||
| 109 | + return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); | ||
| 110 | +} | ||
| 111 | + | ||
| 112 | +uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
| 113 | +{ | ||
| 114 | + return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); | ||
| 115 | +} | ||
| 116 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 117 | index XXXXXXX..XXXXXXX 100644 | ||
| 118 | --- a/target/arm/translate.c | ||
| 119 | +++ b/target/arm/translate.c | ||
| 120 | @@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) | ||
| 121 | |||
| 122 | static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh) | ||
| 123 | { | ||
| 124 | - TCGv_i32 t = tcg_temp_new_i32(); | ||
| 125 | + TCGv_i32 t; | ||
| 126 | |||
| 127 | + /* Handle shift by the input size for the benefit of trans_SRSHR_ri */ | ||
| 128 | + if (sh == 32) { | ||
| 129 | + tcg_gen_movi_i32(d, 0); | ||
| 130 | + return; | ||
| 131 | + } | ||
| 132 | + t = tcg_temp_new_i32(); | ||
| 133 | tcg_gen_extract_i32(t, a, sh - 1, 1); | ||
| 134 | tcg_gen_sari_i32(d, a, sh); | ||
| 135 | tcg_gen_add_i32(d, d, t); | ||
| 136 | @@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) | ||
| 137 | |||
| 138 | static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh) | ||
| 139 | { | ||
| 140 | - TCGv_i32 t = tcg_temp_new_i32(); | ||
| 141 | + TCGv_i32 t; | ||
| 142 | |||
| 143 | + /* Handle shift by the input size for the benefit of trans_URSHR_ri */ | ||
| 144 | + if (sh == 32) { | ||
| 145 | + tcg_gen_extract_i32(d, a, sh - 1, 1); | ||
| 146 | + return; | ||
| 147 | + } | ||
| 148 | + t = tcg_temp_new_i32(); | ||
| 149 | tcg_gen_extract_i32(t, a, sh - 1, 1); | ||
| 150 | tcg_gen_shri_i32(d, a, sh); | ||
| 151 | tcg_gen_add_i32(d, d, t); | ||
| 152 | @@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
| 153 | return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48); | ||
| 154 | } | ||
| 155 | |||
| 156 | +static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn) | ||
| 157 | +{ | ||
| 158 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
| 159 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | ||
| 160 | + return false; | 35 | + return false; |
| 161 | + } | 36 | + } |
| 162 | + if (!dc_isar_feature(aa32_mve, s) || | 37 | if (is_a64(env)) { |
| 163 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | 38 | return aa64_generate_debug_exceptions(env); |
| 164 | + a->rda == 13 || a->rda == 15) { | 39 | } else { |
| 165 | + /* These rda cases are UNPREDICTABLE; we choose to UNDEF */ | ||
| 166 | + unallocated_encoding(s); | ||
| 167 | + return true; | ||
| 168 | + } | ||
| 169 | + | ||
| 170 | + if (a->shim == 0) { | ||
| 171 | + a->shim = 32; | ||
| 172 | + } | ||
| 173 | + fn(cpu_R[a->rda], cpu_R[a->rda], a->shim); | ||
| 174 | + | ||
| 175 | + return true; | ||
| 176 | +} | ||
| 177 | + | ||
| 178 | +static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
| 179 | +{ | ||
| 180 | + return do_mve_sh_ri(s, a, gen_urshr32_i32); | ||
| 181 | +} | ||
| 182 | + | ||
| 183 | +static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
| 184 | +{ | ||
| 185 | + return do_mve_sh_ri(s, a, gen_srshr32_i32); | ||
| 186 | +} | ||
| 187 | + | ||
| 188 | +static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) | ||
| 189 | +{ | ||
| 190 | + gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift)); | ||
| 191 | +} | ||
| 192 | + | ||
| 193 | +static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
| 194 | +{ | ||
| 195 | + return do_mve_sh_ri(s, a, gen_mve_sqshl); | ||
| 196 | +} | ||
| 197 | + | ||
| 198 | +static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) | ||
| 199 | +{ | ||
| 200 | + gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift)); | ||
| 201 | +} | ||
| 202 | + | ||
| 203 | +static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
| 204 | +{ | ||
| 205 | + return do_mve_sh_ri(s, a, gen_mve_uqshl); | ||
| 206 | +} | ||
| 207 | + | ||
| 208 | /* | ||
| 209 | * Multiply and multiply accumulate | ||
| 210 | */ | ||
| 211 | -- | 40 | -- |
| 212 | 2.20.1 | 41 | 2.25.1 |
| 213 | |||
| 214 | diff view generated by jsdifflib |
| 1 | Implement the MVE saturating shift-right-and-narrow insns | 1 | Starting with v7 of the debug architecture, there are three extra |
|---|---|---|---|
| 2 | VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN. | 2 | ID registers that add information on top of that provided in |
| 3 | DBGDIDR. These are DBGDEVID, DBGDEVID1 and DBGDEVID2. In the | ||
| 4 | v7 debug architecture, DBGDEVID is optional, present only of | ||
| 5 | DBGDIDR.DEVID_imp is set. In v7.1 all three must be present. | ||
| 3 | 6 | ||
| 4 | do_srshr() is borrowed from sve_helper.c. | 7 | Implement the missing registers. Note that we only need to set the |
| 8 | values in the ARMISARegisters struct for the CPUs Cortex-A7, A15, | ||
| 9 | A53, A57 and A72 (plus the 32-bit 'max' which uses the Cortex-A53 | ||
| 10 | values): earlier CPUs didn't implement v7 of the architecture, and | ||
| 11 | our other 64-bit CPUs (Cortex-A76, Neoverse-N1 and A64fx) don't have | ||
| 12 | AArch32 support at EL1. | ||
| 5 | 13 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20210628135835.6690-13-peter.maydell@linaro.org | 16 | Message-id: 20220630194116.3438513-5-peter.maydell@linaro.org |
| 9 | --- | 17 | --- |
| 10 | target/arm/helper-mve.h | 30 +++++++++++ | 18 | target/arm/cpu.h | 7 +++++++ |
| 11 | target/arm/mve.decode | 28 ++++++++++ | 19 | target/arm/cpu64.c | 6 ++++++ |
| 12 | target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++ | 20 | target/arm/cpu_tcg.c | 6 ++++++ |
| 13 | target/arm/translate-mve.c | 12 +++++ | 21 | target/arm/debug_helper.c | 36 ++++++++++++++++++++++++++++++++++++ |
| 14 | 4 files changed, 174 insertions(+) | 22 | 4 files changed, 55 insertions(+) |
| 15 | 23 | ||
| 16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | 24 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
| 17 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/target/arm/helper-mve.h | 26 | --- a/target/arm/cpu.h |
| 19 | +++ b/target/arm/helper-mve.h | 27 | +++ b/target/arm/cpu.h |
| 20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 28 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { |
| 21 | DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 29 | uint32_t mvfr2; |
| 22 | DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 30 | uint32_t id_dfr0; |
| 23 | DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 31 | uint32_t dbgdidr; |
| 24 | + | 32 | + uint32_t dbgdevid; |
| 25 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 33 | + uint32_t dbgdevid1; |
| 26 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 34 | uint64_t id_aa64isar0; |
| 27 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 35 | uint64_t id_aa64isar1; |
| 28 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 36 | uint64_t id_aa64pfr0; |
| 29 | + | 37 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) |
| 30 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 38 | return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; |
| 31 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 32 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 33 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 34 | + | ||
| 35 | +DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 36 | +DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 37 | +DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 38 | +DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 39 | + | ||
| 40 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 41 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 42 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 43 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 44 | + | ||
| 45 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 46 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 47 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 48 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 49 | + | ||
| 50 | +DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 51 | +DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 52 | +DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 53 | +DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 54 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
| 55 | index XXXXXXX..XXXXXXX 100644 | ||
| 56 | --- a/target/arm/mve.decode | ||
| 57 | +++ b/target/arm/mve.decode | ||
| 58 | @@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b | ||
| 59 | VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h | ||
| 60 | VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b | ||
| 61 | VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h | ||
| 62 | + | ||
| 63 | +VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b | ||
| 64 | +VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h | ||
| 65 | +VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b | ||
| 66 | +VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h | ||
| 67 | +VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b | ||
| 68 | +VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h | ||
| 69 | +VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b | ||
| 70 | +VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h | ||
| 71 | + | ||
| 72 | +VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b | ||
| 73 | +VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h | ||
| 74 | +VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b | ||
| 75 | +VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h | ||
| 76 | + | ||
| 77 | +VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b | ||
| 78 | +VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h | ||
| 79 | +VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b | ||
| 80 | +VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h | ||
| 81 | +VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b | ||
| 82 | +VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h | ||
| 83 | +VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b | ||
| 84 | +VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h | ||
| 85 | + | ||
| 86 | +VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b | ||
| 87 | +VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h | ||
| 88 | +VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b | ||
| 89 | +VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h | ||
| 90 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
| 91 | index XXXXXXX..XXXXXXX 100644 | ||
| 92 | --- a/target/arm/mve_helper.c | ||
| 93 | +++ b/target/arm/mve_helper.c | ||
| 94 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh) | ||
| 95 | } | ||
| 96 | } | 39 | } |
| 97 | 40 | ||
| 98 | +static inline int64_t do_srshr(int64_t x, unsigned sh) | 41 | +static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) |
| 99 | +{ | 42 | +{ |
| 100 | + if (likely(sh < 64)) { | 43 | + return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5; |
| 101 | + return (x >> sh) + ((x >> (sh - 1)) & 1); | ||
| 102 | + } else { | ||
| 103 | + /* Rounding the sign bit always produces 0. */ | ||
| 104 | + return 0; | ||
| 105 | + } | ||
| 106 | +} | 44 | +} |
| 107 | + | 45 | + |
| 108 | DO_VSHRN_ALL(vshrn, DO_SHR) | 46 | static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) |
| 109 | DO_VSHRN_ALL(vrshrn, do_urshr) | 47 | { |
| 110 | + | 48 | return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; |
| 111 | +static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, | 49 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
| 112 | + bool *satp) | 50 | index XXXXXXX..XXXXXXX 100644 |
| 113 | +{ | 51 | --- a/target/arm/cpu64.c |
| 114 | + if (val > max) { | 52 | +++ b/target/arm/cpu64.c |
| 115 | + *satp = true; | 53 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj) |
| 116 | + return max; | 54 | cpu->isar.id_aa64isar0 = 0x00011120; |
| 117 | + } else if (val < min) { | 55 | cpu->isar.id_aa64mmfr0 = 0x00001124; |
| 118 | + *satp = true; | 56 | cpu->isar.dbgdidr = 0x3516d000; |
| 119 | + return min; | 57 | + cpu->isar.dbgdevid = 0x01110f13; |
| 120 | + } else { | 58 | + cpu->isar.dbgdevid1 = 0x2; |
| 121 | + return val; | 59 | cpu->isar.reset_pmcr_el0 = 0x41013000; |
| 60 | cpu->clidr = 0x0a200023; | ||
| 61 | cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | ||
| 62 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj) | ||
| 63 | cpu->isar.id_aa64isar0 = 0x00011120; | ||
| 64 | cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ | ||
| 65 | cpu->isar.dbgdidr = 0x3516d000; | ||
| 66 | + cpu->isar.dbgdevid = 0x00110f13; | ||
| 67 | + cpu->isar.dbgdevid1 = 0x1; | ||
| 68 | cpu->isar.reset_pmcr_el0 = 0x41033000; | ||
| 69 | cpu->clidr = 0x0a200023; | ||
| 70 | cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ | ||
| 71 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | ||
| 72 | cpu->isar.id_aa64isar0 = 0x00011120; | ||
| 73 | cpu->isar.id_aa64mmfr0 = 0x00001124; | ||
| 74 | cpu->isar.dbgdidr = 0x3516d000; | ||
| 75 | + cpu->isar.dbgdevid = 0x01110f13; | ||
| 76 | + cpu->isar.dbgdevid1 = 0x2; | ||
| 77 | cpu->isar.reset_pmcr_el0 = 0x41023000; | ||
| 78 | cpu->clidr = 0x0a200023; | ||
| 79 | cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | ||
| 80 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
| 81 | index XXXXXXX..XXXXXXX 100644 | ||
| 82 | --- a/target/arm/cpu_tcg.c | ||
| 83 | +++ b/target/arm/cpu_tcg.c | ||
| 84 | @@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj) | ||
| 85 | cpu->isar.id_isar3 = 0x11112131; | ||
| 86 | cpu->isar.id_isar4 = 0x10011142; | ||
| 87 | cpu->isar.dbgdidr = 0x3515f005; | ||
| 88 | + cpu->isar.dbgdevid = 0x01110f13; | ||
| 89 | + cpu->isar.dbgdevid1 = 0x1; | ||
| 90 | cpu->clidr = 0x0a200023; | ||
| 91 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | ||
| 92 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | ||
| 93 | @@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj) | ||
| 94 | cpu->isar.id_isar3 = 0x11112131; | ||
| 95 | cpu->isar.id_isar4 = 0x10011142; | ||
| 96 | cpu->isar.dbgdidr = 0x3515f021; | ||
| 97 | + cpu->isar.dbgdevid = 0x01110f13; | ||
| 98 | + cpu->isar.dbgdevid1 = 0x0; | ||
| 99 | cpu->clidr = 0x0a200023; | ||
| 100 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | ||
| 101 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | ||
| 102 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | ||
| 103 | cpu->isar.id_isar5 = 0x00011121; | ||
| 104 | cpu->isar.id_isar6 = 0; | ||
| 105 | cpu->isar.dbgdidr = 0x3516d000; | ||
| 106 | + cpu->isar.dbgdevid = 0x00110f13; | ||
| 107 | + cpu->isar.dbgdevid1 = 0x2; | ||
| 108 | cpu->isar.reset_pmcr_el0 = 0x41013000; | ||
| 109 | cpu->clidr = 0x0a200023; | ||
| 110 | cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | ||
| 111 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | ||
| 112 | index XXXXXXX..XXXXXXX 100644 | ||
| 113 | --- a/target/arm/debug_helper.c | ||
| 114 | +++ b/target/arm/debug_helper.c | ||
| 115 | @@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu) | ||
| 116 | define_one_arm_cp_reg(cpu, &dbgdidr); | ||
| 117 | } | ||
| 118 | |||
| 119 | + /* | ||
| 120 | + * DBGDEVID is present in the v7 debug architecture if | ||
| 121 | + * DBGDIDR.DEVID_imp is 1 (bit 15); from v7.1 and on it is | ||
| 122 | + * mandatory (and bit 15 is RES1). DBGDEVID1 and DBGDEVID2 exist | ||
| 123 | + * from v7.1 of the debug architecture. Because no fields have yet | ||
| 124 | + * been defined in DBGDEVID2 (and quite possibly none will ever | ||
| 125 | + * be) we don't define an ARMISARegisters field for it. | ||
| 126 | + * These registers exist only if EL1 can use AArch32, but that | ||
| 127 | + * happens naturally because they are only PL1 accessible anyway. | ||
| 128 | + */ | ||
| 129 | + if (extract32(cpu->isar.dbgdidr, 15, 1)) { | ||
| 130 | + ARMCPRegInfo dbgdevid = { | ||
| 131 | + .name = "DBGDEVID", | ||
| 132 | + .cp = 14, .opc1 = 0, .crn = 7, .opc2 = 2, .crn = 7, | ||
| 133 | + .access = PL1_R, .accessfn = access_tda, | ||
| 134 | + .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdevid, | ||
| 135 | + }; | ||
| 136 | + define_one_arm_cp_reg(cpu, &dbgdevid); | ||
| 122 | + } | 137 | + } |
| 123 | +} | 138 | + if (cpu_isar_feature(aa32_debugv7p1, cpu)) { |
| 124 | + | 139 | + ARMCPRegInfo dbgdevid12[] = { |
| 125 | +/* Saturating narrowing right shifts */ | 140 | + { |
| 126 | +#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ | 141 | + .name = "DBGDEVID1", |
| 127 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | 142 | + .cp = 14, .opc1 = 0, .crn = 7, .opc2 = 1, .crn = 7, |
| 128 | + void *vm, uint32_t shift) \ | 143 | + .access = PL1_R, .accessfn = access_tda, |
| 129 | + { \ | 144 | + .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdevid1, |
| 130 | + LTYPE *m = vm; \ | 145 | + }, { |
| 131 | + TYPE *d = vd; \ | 146 | + .name = "DBGDEVID2", |
| 132 | + uint16_t mask = mve_element_mask(env); \ | 147 | + .cp = 14, .opc1 = 0, .crn = 7, .opc2 = 0, .crn = 7, |
| 133 | + bool qc = false; \ | 148 | + .access = PL1_R, .accessfn = access_tda, |
| 134 | + unsigned le; \ | 149 | + .type = ARM_CP_CONST, .resetvalue = 0, |
| 135 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | 150 | + }, |
| 136 | + bool sat = false; \ | 151 | + }; |
| 137 | + TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ | 152 | + define_arm_cp_regs(cpu, dbgdevid12); |
| 138 | + mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ | ||
| 139 | + qc |= sat && (mask & 1 << (TOP * ESIZE)); \ | ||
| 140 | + } \ | ||
| 141 | + if (qc) { \ | ||
| 142 | + env->vfp.qc[0] = qc; \ | ||
| 143 | + } \ | ||
| 144 | + mve_advance_vpt(env); \ | ||
| 145 | + } | 153 | + } |
| 146 | + | 154 | + |
| 147 | +#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ | 155 | brps = arm_num_brps(cpu); |
| 148 | + DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ | 156 | wrps = arm_num_wrps(cpu); |
| 149 | + DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) | 157 | ctx_cmps = arm_num_ctx_cmps(cpu); |
| 150 | + | ||
| 151 | +#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ | ||
| 152 | + DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ | ||
| 153 | + DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) | ||
| 154 | + | ||
| 155 | +#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ | ||
| 156 | + DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ | ||
| 157 | + DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) | ||
| 158 | + | ||
| 159 | +#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ | ||
| 160 | + DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ | ||
| 161 | + DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) | ||
| 162 | + | ||
| 163 | +#define DO_SHRN_SB(N, M, SATP) \ | ||
| 164 | + do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) | ||
| 165 | +#define DO_SHRN_UB(N, M, SATP) \ | ||
| 166 | + do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) | ||
| 167 | +#define DO_SHRUN_B(N, M, SATP) \ | ||
| 168 | + do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) | ||
| 169 | + | ||
| 170 | +#define DO_SHRN_SH(N, M, SATP) \ | ||
| 171 | + do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) | ||
| 172 | +#define DO_SHRN_UH(N, M, SATP) \ | ||
| 173 | + do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) | ||
| 174 | +#define DO_SHRUN_H(N, M, SATP) \ | ||
| 175 | + do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) | ||
| 176 | + | ||
| 177 | +#define DO_RSHRN_SB(N, M, SATP) \ | ||
| 178 | + do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) | ||
| 179 | +#define DO_RSHRN_UB(N, M, SATP) \ | ||
| 180 | + do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) | ||
| 181 | +#define DO_RSHRUN_B(N, M, SATP) \ | ||
| 182 | + do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) | ||
| 183 | + | ||
| 184 | +#define DO_RSHRN_SH(N, M, SATP) \ | ||
| 185 | + do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) | ||
| 186 | +#define DO_RSHRN_UH(N, M, SATP) \ | ||
| 187 | + do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) | ||
| 188 | +#define DO_RSHRUN_H(N, M, SATP) \ | ||
| 189 | + do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) | ||
| 190 | + | ||
| 191 | +DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) | ||
| 192 | +DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) | ||
| 193 | +DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) | ||
| 194 | +DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) | ||
| 195 | +DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) | ||
| 196 | +DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) | ||
| 197 | + | ||
| 198 | +DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) | ||
| 199 | +DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) | ||
| 200 | +DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) | ||
| 201 | +DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) | ||
| 202 | +DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) | ||
| 203 | +DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) | ||
| 204 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
| 205 | index XXXXXXX..XXXXXXX 100644 | ||
| 206 | --- a/target/arm/translate-mve.c | ||
| 207 | +++ b/target/arm/translate-mve.c | ||
| 208 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb) | ||
| 209 | DO_2SHIFT_N(VSHRNT, vshrnt) | ||
| 210 | DO_2SHIFT_N(VRSHRNB, vrshrnb) | ||
| 211 | DO_2SHIFT_N(VRSHRNT, vrshrnt) | ||
| 212 | +DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s) | ||
| 213 | +DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s) | ||
| 214 | +DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u) | ||
| 215 | +DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u) | ||
| 216 | +DO_2SHIFT_N(VQSHRUNB, vqshrunb) | ||
| 217 | +DO_2SHIFT_N(VQSHRUNT, vqshrunt) | ||
| 218 | +DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s) | ||
| 219 | +DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s) | ||
| 220 | +DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u) | ||
| 221 | +DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u) | ||
| 222 | +DO_2SHIFT_N(VQRSHRUNB, vqrshrunb) | ||
| 223 | +DO_2SHIFT_N(VQRSHRUNT, vqrshrunt) | ||
| 224 | -- | 158 | -- |
| 225 | 2.20.1 | 159 | 2.25.1 |
| 226 | |||
| 227 | diff view generated by jsdifflib |
| 1 | From: Nolan Leake <nolan@sigbus.net> | 1 | The architecture defines the OS DoubleLock as a register which |
|---|---|---|---|
| 2 | (similarly to the OS Lock) suppresses debug events for use in CPU | ||
| 3 | powerdown sequences. This functionality is required in Arm v7 and | ||
| 4 | v8.0; from v8.2 it becomes optional and in v9 it must not be | ||
| 5 | implemented. | ||
| 2 | 6 | ||
| 3 | This is just enough to make reboot and poweroff work. Works for | 7 | Currently in QEMU we implement the OSDLR_EL1 register as a NOP. This |
| 4 | linux, u-boot, and the arm trusted firmware. Not tested, but should | 8 | is wrong both for the "feature implemented" and the "feature not |
| 5 | work for plan9, and bare-metal/hobby OSes, since they seem to generally | 9 | implemented" cases: if the feature is implemented then the DLK bit |
| 6 | do what linux does for reset. | 10 | should read as written and cause suppression of debug exceptions, and |
| 11 | if it is not implemented then the bit must be RAZ/WI. | ||
| 7 | 12 | ||
| 8 | The watchdog timer functionality is not yet implemented. | 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 9 | |||
| 10 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64 | ||
| 11 | Signed-off-by: Nolan Leake <nolan@sigbus.net> | ||
| 12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 13 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 14 | Message-id: 20210625210209.1870217-1-nolan@sigbus.net | ||
| 15 | [PMM: tweaked commit title; fixed region size to 0x200; | ||
| 16 | moved header file to include/] | ||
| 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 18 | --- | 15 | --- |
| 19 | include/hw/arm/bcm2835_peripherals.h | 3 +- | 16 | target/arm/cpu.h | 20 ++++++++++++++++++++ |
| 20 | include/hw/misc/bcm2835_powermgt.h | 29 +++++ | 17 | target/arm/debug_helper.c | 20 ++++++++++++++++++-- |
| 21 | hw/arm/bcm2835_peripherals.c | 13 ++- | 18 | 2 files changed, 38 insertions(+), 2 deletions(-) |
| 22 | hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++ | ||
| 23 | hw/misc/meson.build | 1 + | ||
| 24 | 5 files changed, 204 insertions(+), 2 deletions(-) | ||
| 25 | create mode 100644 include/hw/misc/bcm2835_powermgt.h | ||
| 26 | create mode 100644 hw/misc/bcm2835_powermgt.c | ||
| 27 | 19 | ||
| 28 | diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h | 20 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
| 29 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
| 30 | --- a/include/hw/arm/bcm2835_peripherals.h | 22 | --- a/target/arm/cpu.h |
| 31 | +++ b/include/hw/arm/bcm2835_peripherals.h | 23 | +++ b/target/arm/cpu.h |
| 32 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
| 33 | #include "hw/misc/bcm2835_mphi.h" | 25 | uint64_t dbgwcr[16]; /* watchpoint control registers */ |
| 34 | #include "hw/misc/bcm2835_thermal.h" | 26 | uint64_t mdscr_el1; |
| 35 | #include "hw/misc/bcm2835_cprman.h" | 27 | uint64_t oslsr_el1; /* OS Lock Status */ |
| 36 | +#include "hw/misc/bcm2835_powermgt.h" | 28 | + uint64_t osdlr_el1; /* OS DoubleLock status */ |
| 37 | #include "hw/sd/sdhci.h" | 29 | uint64_t mdcr_el2; |
| 38 | #include "hw/sd/bcm2835_sdhost.h" | 30 | uint64_t mdcr_el3; |
| 39 | #include "hw/gpio/bcm2835_gpio.h" | 31 | /* Stores the architectural value of the counter *the last time it was |
| 40 | @@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState { | 32 | @@ -XXX,XX +XXX,XX @@ FIELD(DBGDIDR, CTX_CMPS, 20, 4) |
| 41 | BCM2835MphiState mphi; | 33 | FIELD(DBGDIDR, BRPS, 24, 4) |
| 42 | UnimplementedDeviceState txp; | 34 | FIELD(DBGDIDR, WRPS, 28, 4) |
| 43 | UnimplementedDeviceState armtmr; | 35 | |
| 44 | - UnimplementedDeviceState powermgt; | 36 | +FIELD(DBGDEVID, PCSAMPLE, 0, 4) |
| 45 | + BCM2835PowerMgtState powermgt; | 37 | +FIELD(DBGDEVID, WPADDRMASK, 4, 4) |
| 46 | BCM2835CprmanState cprman; | 38 | +FIELD(DBGDEVID, BPADDRMASK, 8, 4) |
| 47 | PL011State uart0; | 39 | +FIELD(DBGDEVID, VECTORCATCH, 12, 4) |
| 48 | BCM2835AuxState aux; | 40 | +FIELD(DBGDEVID, VIRTEXTNS, 16, 4) |
| 49 | diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h | 41 | +FIELD(DBGDEVID, DOUBLELOCK, 20, 4) |
| 50 | new file mode 100644 | 42 | +FIELD(DBGDEVID, AUXREGS, 24, 4) |
| 51 | index XXXXXXX..XXXXXXX | 43 | +FIELD(DBGDEVID, CIDMASK, 28, 4) |
| 52 | --- /dev/null | ||
| 53 | +++ b/include/hw/misc/bcm2835_powermgt.h | ||
| 54 | @@ -XXX,XX +XXX,XX @@ | ||
| 55 | +/* | ||
| 56 | + * BCM2835 Power Management emulation | ||
| 57 | + * | ||
| 58 | + * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com> | ||
| 59 | + * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net> | ||
| 60 | + * | ||
| 61 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 62 | + * See the COPYING file in the top-level directory. | ||
| 63 | + */ | ||
| 64 | + | 44 | + |
| 65 | +#ifndef BCM2835_POWERMGT_H | 45 | FIELD(MVFR0, SIMDREG, 0, 4) |
| 66 | +#define BCM2835_POWERMGT_H | 46 | FIELD(MVFR0, FPSP, 4, 4) |
| 67 | + | 47 | FIELD(MVFR0, FPDP, 8, 4) |
| 68 | +#include "hw/sysbus.h" | 48 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) |
| 69 | +#include "qom/object.h" | 49 | return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; |
| 70 | + | ||
| 71 | +#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt" | ||
| 72 | +OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT) | ||
| 73 | + | ||
| 74 | +struct BCM2835PowerMgtState { | ||
| 75 | + SysBusDevice busdev; | ||
| 76 | + MemoryRegion iomem; | ||
| 77 | + | ||
| 78 | + uint32_t rstc; | ||
| 79 | + uint32_t rsts; | ||
| 80 | + uint32_t wdog; | ||
| 81 | +}; | ||
| 82 | + | ||
| 83 | +#endif | ||
| 84 | diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c | ||
| 85 | index XXXXXXX..XXXXXXX 100644 | ||
| 86 | --- a/hw/arm/bcm2835_peripherals.c | ||
| 87 | +++ b/hw/arm/bcm2835_peripherals.c | ||
| 88 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj) | ||
| 89 | |||
| 90 | object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr", | ||
| 91 | OBJECT(&s->gpu_bus_mr)); | ||
| 92 | + | ||
| 93 | + /* Power Management */ | ||
| 94 | + object_initialize_child(obj, "powermgt", &s->powermgt, | ||
| 95 | + TYPE_BCM2835_POWERMGT); | ||
| 96 | } | 50 | } |
| 97 | 51 | ||
| 98 | static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | 52 | +static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) |
| 99 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | ||
| 100 | qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, | ||
| 101 | INTERRUPT_USB)); | ||
| 102 | |||
| 103 | + /* Power Management */ | ||
| 104 | + if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) { | ||
| 105 | + return; | ||
| 106 | + } | ||
| 107 | + | ||
| 108 | + memory_region_add_subregion(&s->peri_mr, PM_OFFSET, | ||
| 109 | + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0)); | ||
| 110 | + | ||
| 111 | create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000); | ||
| 112 | create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); | ||
| 113 | - create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114); | ||
| 114 | create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); | ||
| 115 | create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100); | ||
| 116 | create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20); | ||
| 117 | diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c | ||
| 118 | new file mode 100644 | ||
| 119 | index XXXXXXX..XXXXXXX | ||
| 120 | --- /dev/null | ||
| 121 | +++ b/hw/misc/bcm2835_powermgt.c | ||
| 122 | @@ -XXX,XX +XXX,XX @@ | ||
| 123 | +/* | ||
| 124 | + * BCM2835 Power Management emulation | ||
| 125 | + * | ||
| 126 | + * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com> | ||
| 127 | + * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net> | ||
| 128 | + * | ||
| 129 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
| 130 | + * See the COPYING file in the top-level directory. | ||
| 131 | + */ | ||
| 132 | + | ||
| 133 | +#include "qemu/osdep.h" | ||
| 134 | +#include "qemu/log.h" | ||
| 135 | +#include "qemu/module.h" | ||
| 136 | +#include "hw/misc/bcm2835_powermgt.h" | ||
| 137 | +#include "migration/vmstate.h" | ||
| 138 | +#include "sysemu/runstate.h" | ||
| 139 | + | ||
| 140 | +#define PASSWORD 0x5a000000 | ||
| 141 | +#define PASSWORD_MASK 0xff000000 | ||
| 142 | + | ||
| 143 | +#define R_RSTC 0x1c | ||
| 144 | +#define V_RSTC_RESET 0x20 | ||
| 145 | +#define R_RSTS 0x20 | ||
| 146 | +#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */ | ||
| 147 | +#define R_WDOG 0x24 | ||
| 148 | + | ||
| 149 | +static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset, | ||
| 150 | + unsigned size) | ||
| 151 | +{ | 53 | +{ |
| 152 | + BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque; | 54 | + return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0; |
| 153 | + uint32_t res = 0; | ||
| 154 | + | ||
| 155 | + switch (offset) { | ||
| 156 | + case R_RSTC: | ||
| 157 | + res = s->rstc; | ||
| 158 | + break; | ||
| 159 | + case R_RSTS: | ||
| 160 | + res = s->rsts; | ||
| 161 | + break; | ||
| 162 | + case R_WDOG: | ||
| 163 | + res = s->wdog; | ||
| 164 | + break; | ||
| 165 | + | ||
| 166 | + default: | ||
| 167 | + qemu_log_mask(LOG_UNIMP, | ||
| 168 | + "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx | ||
| 169 | + "\n", offset); | ||
| 170 | + res = 0; | ||
| 171 | + break; | ||
| 172 | + } | ||
| 173 | + | ||
| 174 | + return res; | ||
| 175 | +} | 55 | +} |
| 176 | + | 56 | + |
| 177 | +static void bcm2835_powermgt_write(void *opaque, hwaddr offset, | 57 | /* |
| 178 | + uint64_t value, unsigned size) | 58 | * 64-bit feature tests via id registers. |
| 59 | */ | ||
| 60 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) | ||
| 61 | return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); | ||
| 62 | } | ||
| 63 | |||
| 64 | +static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) | ||
| 179 | +{ | 65 | +{ |
| 180 | + BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque; | 66 | + return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; |
| 67 | +} | ||
| 181 | + | 68 | + |
| 182 | + if ((value & PASSWORD_MASK) != PASSWORD) { | 69 | /* |
| 183 | + qemu_log_mask(LOG_GUEST_ERROR, | 70 | * Feature tests for "does this exist in either 32-bit or 64-bit?" |
| 184 | + "bcm2835_powermgt_write: Bad password 0x%"PRIx64 | 71 | */ |
| 185 | + " at offset 0x%08"HWADDR_PRIx"\n", | 72 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
| 186 | + value, offset); | 73 | index XXXXXXX..XXXXXXX 100644 |
| 187 | + return; | 74 | --- a/target/arm/debug_helper.c |
| 188 | + } | 75 | +++ b/target/arm/debug_helper.c |
| 189 | + | 76 | @@ -XXX,XX +XXX,XX @@ static bool aa32_generate_debug_exceptions(CPUARMState *env) |
| 190 | + value = value & ~PASSWORD_MASK; | 77 | */ |
| 191 | + | 78 | bool arm_generate_debug_exceptions(CPUARMState *env) |
| 192 | + switch (offset) { | 79 | { |
| 193 | + case R_RSTC: | 80 | - if (env->cp15.oslsr_el1 & 1) { |
| 194 | + s->rstc = value; | 81 | + if ((env->cp15.oslsr_el1 & 1) || (env->cp15.osdlr_el1 & 1)) { |
| 195 | + if (value & V_RSTC_RESET) { | 82 | return false; |
| 196 | + if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) { | 83 | } |
| 197 | + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | 84 | if (is_a64(env)) { |
| 198 | + } else { | 85 | @@ -XXX,XX +XXX,XX @@ static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 199 | + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | 86 | env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock); |
| 200 | + } | 87 | } |
| 201 | + } | 88 | |
| 202 | + break; | 89 | +static void osdlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 203 | + case R_RSTS: | 90 | + uint64_t value) |
| 204 | + qemu_log_mask(LOG_UNIMP, | 91 | +{ |
| 205 | + "bcm2835_powermgt_write: RSTS\n"); | 92 | + ARMCPU *cpu = env_archcpu(env); |
| 206 | + s->rsts = value; | 93 | + /* |
| 207 | + break; | 94 | + * Only defined bit is bit 0 (DLK); if Feat_DoubleLock is not |
| 208 | + case R_WDOG: | 95 | + * implemented this is RAZ/WI. |
| 209 | + qemu_log_mask(LOG_UNIMP, | 96 | + */ |
| 210 | + "bcm2835_powermgt_write: WDOG\n"); | 97 | + if(arm_feature(env, ARM_FEATURE_AARCH64) |
| 211 | + s->wdog = value; | 98 | + ? cpu_isar_feature(aa64_doublelock, cpu) |
| 212 | + break; | 99 | + : cpu_isar_feature(aa32_doublelock, cpu)) { |
| 213 | + | 100 | + env->cp15.osdlr_el1 = value & 1; |
| 214 | + default: | ||
| 215 | + qemu_log_mask(LOG_UNIMP, | ||
| 216 | + "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx | ||
| 217 | + "\n", offset); | ||
| 218 | + break; | ||
| 219 | + } | 101 | + } |
| 220 | +} | 102 | +} |
| 221 | + | 103 | + |
| 222 | +static const MemoryRegionOps bcm2835_powermgt_ops = { | 104 | static const ARMCPRegInfo debug_cp_reginfo[] = { |
| 223 | + .read = bcm2835_powermgt_read, | 105 | /* |
| 224 | + .write = bcm2835_powermgt_write, | 106 | * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped |
| 225 | + .endianness = DEVICE_NATIVE_ENDIAN, | 107 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { |
| 226 | + .impl.min_access_size = 4, | 108 | { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, |
| 227 | + .impl.max_access_size = 4, | 109 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, |
| 228 | +}; | 110 | .access = PL1_RW, .accessfn = access_tdosa, |
| 229 | + | 111 | - .type = ARM_CP_NOP }, |
| 230 | +static const VMStateDescription vmstate_bcm2835_powermgt = { | 112 | + .writefn = osdlr_write, |
| 231 | + .name = TYPE_BCM2835_POWERMGT, | 113 | + .fieldoffset = offsetof(CPUARMState, cp15.osdlr_el1) }, |
| 232 | + .version_id = 1, | 114 | /* |
| 233 | + .minimum_version_id = 1, | 115 | * Dummy DBGVCR: Linux wants to clear this on startup, but we don't |
| 234 | + .fields = (VMStateField[]) { | 116 | * implement vector catch debug events yet. |
| 235 | + VMSTATE_UINT32(rstc, BCM2835PowerMgtState), | ||
| 236 | + VMSTATE_UINT32(rsts, BCM2835PowerMgtState), | ||
| 237 | + VMSTATE_UINT32(wdog, BCM2835PowerMgtState), | ||
| 238 | + VMSTATE_END_OF_LIST() | ||
| 239 | + } | ||
| 240 | +}; | ||
| 241 | + | ||
| 242 | +static void bcm2835_powermgt_init(Object *obj) | ||
| 243 | +{ | ||
| 244 | + BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj); | ||
| 245 | + | ||
| 246 | + memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s, | ||
| 247 | + TYPE_BCM2835_POWERMGT, 0x200); | ||
| 248 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); | ||
| 249 | +} | ||
| 250 | + | ||
| 251 | +static void bcm2835_powermgt_reset(DeviceState *dev) | ||
| 252 | +{ | ||
| 253 | + BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev); | ||
| 254 | + | ||
| 255 | + /* https://elinux.org/BCM2835_registers#PM */ | ||
| 256 | + s->rstc = 0x00000102; | ||
| 257 | + s->rsts = 0x00001000; | ||
| 258 | + s->wdog = 0x00000000; | ||
| 259 | +} | ||
| 260 | + | ||
| 261 | +static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data) | ||
| 262 | +{ | ||
| 263 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
| 264 | + | ||
| 265 | + dc->reset = bcm2835_powermgt_reset; | ||
| 266 | + dc->vmsd = &vmstate_bcm2835_powermgt; | ||
| 267 | +} | ||
| 268 | + | ||
| 269 | +static TypeInfo bcm2835_powermgt_info = { | ||
| 270 | + .name = TYPE_BCM2835_POWERMGT, | ||
| 271 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
| 272 | + .instance_size = sizeof(BCM2835PowerMgtState), | ||
| 273 | + .class_init = bcm2835_powermgt_class_init, | ||
| 274 | + .instance_init = bcm2835_powermgt_init, | ||
| 275 | +}; | ||
| 276 | + | ||
| 277 | +static void bcm2835_powermgt_register_types(void) | ||
| 278 | +{ | ||
| 279 | + type_register_static(&bcm2835_powermgt_info); | ||
| 280 | +} | ||
| 281 | + | ||
| 282 | +type_init(bcm2835_powermgt_register_types) | ||
| 283 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
| 284 | index XXXXXXX..XXXXXXX 100644 | ||
| 285 | --- a/hw/misc/meson.build | ||
| 286 | +++ b/hw/misc/meson.build | ||
| 287 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( | ||
| 288 | 'bcm2835_rng.c', | ||
| 289 | 'bcm2835_thermal.c', | ||
| 290 | 'bcm2835_cprman.c', | ||
| 291 | + 'bcm2835_powermgt.c', | ||
| 292 | )) | ||
| 293 | softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) | ||
| 294 | softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c')) | ||
| 295 | -- | 117 | -- |
| 296 | 2.20.1 | 118 | 2.25.1 |
| 297 | |||
| 298 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 2 | 1 | ||
| 3 | Add a test booting and quickly shutdown a raspi2 machine, | ||
| 4 | to test the power management model: | ||
| 5 | |||
| 6 | (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd: | ||
| 7 | console: [ 0.000000] Booting Linux on physical CPU 0xf00 | ||
| 8 | console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019 | ||
| 9 | console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d | ||
| 10 | console: [ 0.000000] CPU: div instructions available: patching division code | ||
| 11 | console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache | ||
| 12 | console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B | ||
| 13 | ... | ||
| 14 | console: Boot successful. | ||
| 15 | console: cat /proc/cpuinfo | ||
| 16 | console: / # cat /proc/cpuinfo | ||
| 17 | ... | ||
| 18 | console: processor : 3 | ||
| 19 | console: model name : ARMv7 Processor rev 5 (v7l) | ||
| 20 | console: BogoMIPS : 125.00 | ||
| 21 | console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm | ||
| 22 | console: CPU implementer : 0x41 | ||
| 23 | console: CPU architecture: 7 | ||
| 24 | console: CPU variant : 0x0 | ||
| 25 | console: CPU part : 0xc07 | ||
| 26 | console: CPU revision : 5 | ||
| 27 | console: Hardware : BCM2835 | ||
| 28 | console: Revision : 0000 | ||
| 29 | console: Serial : 0000000000000000 | ||
| 30 | console: cat /proc/iomem | ||
| 31 | console: / # cat /proc/iomem | ||
| 32 | console: 00000000-3bffffff : System RAM | ||
| 33 | console: 00008000-00afffff : Kernel code | ||
| 34 | console: 00c00000-00d468ef : Kernel data | ||
| 35 | console: 3f006000-3f006fff : dwc_otg | ||
| 36 | console: 3f007000-3f007eff : /soc/dma@7e007000 | ||
| 37 | console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880 | ||
| 38 | console: 3f100000-3f100027 : /soc/watchdog@7e100000 | ||
| 39 | console: 3f101000-3f102fff : /soc/cprman@7e101000 | ||
| 40 | console: 3f200000-3f2000b3 : /soc/gpio@7e200000 | ||
| 41 | PASS (24.59 s) | ||
| 42 | RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 | ||
| 43 | JOB TIME : 25.02 s | ||
| 44 | |||
| 45 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 46 | Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> | ||
| 47 | Message-id: 20210531113837.1689775-1-f4bug@amsat.org | ||
| 48 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 49 | --- | ||
| 50 | tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++ | ||
| 51 | 1 file changed, 43 insertions(+) | ||
| 52 | |||
| 53 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py | ||
| 54 | index XXXXXXX..XXXXXXX 100644 | ||
| 55 | --- a/tests/acceptance/boot_linux_console.py | ||
| 56 | +++ b/tests/acceptance/boot_linux_console.py | ||
| 57 | @@ -XXX,XX +XXX,XX @@ | ||
| 58 | from avocado import skip | ||
| 59 | from avocado import skipUnless | ||
| 60 | from avocado_qemu import Test | ||
| 61 | +from avocado_qemu import exec_command | ||
| 62 | from avocado_qemu import exec_command_and_wait_for_pattern | ||
| 63 | from avocado_qemu import interrupt_interactive_console_until_pattern | ||
| 64 | from avocado_qemu import wait_for_console_pattern | ||
| 65 | @@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self): | ||
| 66 | """ | ||
| 67 | self.do_test_arm_raspi2(0) | ||
| 68 | |||
| 69 | + def test_arm_raspi2_initrd(self): | ||
| 70 | + """ | ||
| 71 | + :avocado: tags=arch:arm | ||
| 72 | + :avocado: tags=machine:raspi2 | ||
| 73 | + """ | ||
| 74 | + deb_url = ('http://archive.raspberrypi.org/debian/' | ||
| 75 | + 'pool/main/r/raspberrypi-firmware/' | ||
| 76 | + 'raspberrypi-kernel_1.20190215-1_armhf.deb') | ||
| 77 | + deb_hash = 'cd284220b32128c5084037553db3c482426f3972' | ||
| 78 | + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | ||
| 79 | + kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img') | ||
| 80 | + dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb') | ||
| 81 | + | ||
| 82 | + initrd_url = ('https://github.com/groeck/linux-build-test/raw/' | ||
| 83 | + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' | ||
| 84 | + 'arm/rootfs-armv7a.cpio.gz') | ||
| 85 | + initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c' | ||
| 86 | + initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash) | ||
| 87 | + initrd_path = os.path.join(self.workdir, 'rootfs.cpio') | ||
| 88 | + archive.gzip_uncompress(initrd_path_gz, initrd_path) | ||
| 89 | + | ||
| 90 | + self.vm.set_console() | ||
| 91 | + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + | ||
| 92 | + 'earlycon=pl011,0x3f201000 console=ttyAMA0 ' | ||
| 93 | + 'panic=-1 noreboot ' + | ||
| 94 | + 'dwc_otg.fiq_fsm_enable=0') | ||
| 95 | + self.vm.add_args('-kernel', kernel_path, | ||
| 96 | + '-dtb', dtb_path, | ||
| 97 | + '-initrd', initrd_path, | ||
| 98 | + '-append', kernel_command_line, | ||
| 99 | + '-no-reboot') | ||
| 100 | + self.vm.launch() | ||
| 101 | + self.wait_for_console_pattern('Boot successful.') | ||
| 102 | + | ||
| 103 | + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', | ||
| 104 | + 'BCM2835') | ||
| 105 | + exec_command_and_wait_for_pattern(self, 'cat /proc/iomem', | ||
| 106 | + '/soc/cprman@7e101000') | ||
| 107 | + exec_command(self, 'halt') | ||
| 108 | + # Wait for VM to shut down gracefully | ||
| 109 | + self.vm.wait() | ||
| 110 | + | ||
| 111 | def test_arm_exynos4210_initrd(self): | ||
| 112 | """ | ||
| 113 | :avocado: tags=arch:arm | ||
| 114 | -- | ||
| 115 | 2.20.1 | ||
| 116 | |||
| 117 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH | ||
| 2 | insns had some bugs: | ||
| 3 | * the 32x32 multiply of elements was being done as 32x32->32, | ||
| 4 | not 32x32->64 | ||
| 5 | * we were incorrectly maintaining the accumulator in its full | ||
| 6 | 72-bit form across all 4 beats of the insn; in the pseudocode | ||
| 7 | it is squashed back into the 64 bits of the RdaHi:RdaLo | ||
| 8 | registers after each beat | ||
| 9 | 1 | ||
| 10 | In particular, fixing the second of these allows us to recast | ||
| 11 | the implementation to avoid 128-bit arithmetic entirely. | ||
| 12 | |||
| 13 | Since the element size here is always 4, we can also drop the | ||
| 14 | parameterization of ESIZE to make the code a little more readable. | ||
| 15 | |||
| 16 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 19 | Message-id: 20210628135835.6690-3-peter.maydell@linaro.org | ||
| 20 | --- | ||
| 21 | target/arm/mve_helper.c | 38 +++++++++++++++++++++----------------- | ||
| 22 | 1 file changed, 21 insertions(+), 17 deletions(-) | ||
| 23 | |||
| 24 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | ||
| 26 | --- a/target/arm/mve_helper.c | ||
| 27 | +++ b/target/arm/mve_helper.c | ||
| 28 | @@ -XXX,XX +XXX,XX @@ | ||
| 29 | */ | ||
| 30 | |||
| 31 | #include "qemu/osdep.h" | ||
| 32 | -#include "qemu/int128.h" | ||
| 33 | #include "cpu.h" | ||
| 34 | #include "internals.h" | ||
| 35 | #include "vec_internal.h" | ||
| 36 | @@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) | ||
| 37 | DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) | ||
| 38 | |||
| 39 | /* | ||
| 40 | - * Rounding multiply add long dual accumulate high: we must keep | ||
| 41 | - * a 72-bit internal accumulator value and return the top 64 bits. | ||
| 42 | + * Rounding multiply add long dual accumulate high. In the pseudocode | ||
| 43 | + * this is implemented with a 72-bit internal accumulator value of which | ||
| 44 | + * the top 64 bits are returned. We optimize this to avoid having to | ||
| 45 | + * use 128-bit arithmetic -- we can do this because the 74-bit accumulator | ||
| 46 | + * is squashed back into 64-bits after each beat. | ||
| 47 | */ | ||
| 48 | -#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \ | ||
| 49 | +#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ | ||
| 50 | uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ | ||
| 51 | void *vm, uint64_t a) \ | ||
| 52 | { \ | ||
| 53 | uint16_t mask = mve_element_mask(env); \ | ||
| 54 | unsigned e; \ | ||
| 55 | TYPE *n = vn, *m = vm; \ | ||
| 56 | - Int128 acc = int128_lshift(TO128(a), 8); \ | ||
| 57 | - for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
| 58 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ | ||
| 59 | if (mask & 1) { \ | ||
| 60 | + LTYPE mul; \ | ||
| 61 | if (e & 1) { \ | ||
| 62 | - acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \ | ||
| 63 | - m[H##ESIZE(e)])); \ | ||
| 64 | + mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ | ||
| 65 | + if (SUB) { \ | ||
| 66 | + mul = -mul; \ | ||
| 67 | + } \ | ||
| 68 | } else { \ | ||
| 69 | - acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \ | ||
| 70 | - m[H##ESIZE(e)])); \ | ||
| 71 | + mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ | ||
| 72 | } \ | ||
| 73 | - acc = int128_add(acc, int128_make64(1 << 7)); \ | ||
| 74 | + mul = (mul >> 8) + ((mul >> 7) & 1); \ | ||
| 75 | + a += mul; \ | ||
| 76 | } \ | ||
| 77 | } \ | ||
| 78 | mve_advance_vpt(env); \ | ||
| 79 | - return int128_getlo(int128_rshift(acc, 8)); \ | ||
| 80 | + return a; \ | ||
| 81 | } | ||
| 82 | |||
| 83 | -DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64) | ||
| 84 | -DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64) | ||
| 85 | +DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) | ||
| 86 | +DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) | ||
| 87 | |||
| 88 | -DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64) | ||
| 89 | +DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) | ||
| 90 | |||
| 91 | -DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64) | ||
| 92 | -DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64) | ||
| 93 | +DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) | ||
| 94 | +DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) | ||
| 95 | |||
| 96 | /* Vector add across vector */ | ||
| 97 | #define DO_VADDV(OP, ESIZE, TYPE) \ | ||
| 98 | -- | ||
| 99 | 2.20.1 | ||
| 100 | |||
| 101 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | The function asimd_imm_const() in translate-neon.c is an | ||
| 2 | implementation of the pseudocode AdvSIMDExpandImm(), which we will | ||
| 3 | also want for MVE. Move the implementation to translate.c, with a | ||
| 4 | prototype in translate.h. | ||
| 5 | 1 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20210628135835.6690-4-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | target/arm/translate.h | 16 ++++++++++ | ||
| 11 | target/arm/translate-neon.c | 63 ------------------------------------- | ||
| 12 | target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++ | ||
| 13 | 3 files changed, 73 insertions(+), 63 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/arm/translate.h | ||
| 18 | +++ b/target/arm/translate.h | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc) | ||
| 20 | return opc | s->be_data; | ||
| 21 | } | ||
| 22 | |||
| 23 | +/** | ||
| 24 | + * asimd_imm_const: Expand an encoded SIMD constant value | ||
| 25 | + * | ||
| 26 | + * Expand a SIMD constant value. This is essentially the pseudocode | ||
| 27 | + * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for | ||
| 28 | + * VMVN and VBIC (when cmode < 14 && op == 1). | ||
| 29 | + * | ||
| 30 | + * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; | ||
| 31 | + * callers must catch this. | ||
| 32 | + * | ||
| 33 | + * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but | ||
| 34 | + * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; | ||
| 35 | + * we produce an immediate constant value of 0 in these cases. | ||
| 36 | + */ | ||
| 37 | +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op); | ||
| 38 | + | ||
| 39 | #endif /* TARGET_ARM_TRANSLATE_H */ | ||
| 40 | diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c | ||
| 41 | index XXXXXXX..XXXXXXX 100644 | ||
| 42 | --- a/target/arm/translate-neon.c | ||
| 43 | +++ b/target/arm/translate-neon.c | ||
| 44 | @@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh) | ||
| 45 | DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs) | ||
| 46 | DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu) | ||
| 47 | |||
| 48 | -static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) | ||
| 49 | -{ | ||
| 50 | - /* | ||
| 51 | - * Expand the encoded constant. | ||
| 52 | - * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE. | ||
| 53 | - * We choose to not special-case this and will behave as if a | ||
| 54 | - * valid constant encoding of 0 had been given. | ||
| 55 | - * cmode = 15 op = 1 must UNDEF; we assume decode has handled that. | ||
| 56 | - */ | ||
| 57 | - switch (cmode) { | ||
| 58 | - case 0: case 1: | ||
| 59 | - /* no-op */ | ||
| 60 | - break; | ||
| 61 | - case 2: case 3: | ||
| 62 | - imm <<= 8; | ||
| 63 | - break; | ||
| 64 | - case 4: case 5: | ||
| 65 | - imm <<= 16; | ||
| 66 | - break; | ||
| 67 | - case 6: case 7: | ||
| 68 | - imm <<= 24; | ||
| 69 | - break; | ||
| 70 | - case 8: case 9: | ||
| 71 | - imm |= imm << 16; | ||
| 72 | - break; | ||
| 73 | - case 10: case 11: | ||
| 74 | - imm = (imm << 8) | (imm << 24); | ||
| 75 | - break; | ||
| 76 | - case 12: | ||
| 77 | - imm = (imm << 8) | 0xff; | ||
| 78 | - break; | ||
| 79 | - case 13: | ||
| 80 | - imm = (imm << 16) | 0xffff; | ||
| 81 | - break; | ||
| 82 | - case 14: | ||
| 83 | - if (op) { | ||
| 84 | - /* | ||
| 85 | - * This is the only case where the top and bottom 32 bits | ||
| 86 | - * of the encoded constant differ. | ||
| 87 | - */ | ||
| 88 | - uint64_t imm64 = 0; | ||
| 89 | - int n; | ||
| 90 | - | ||
| 91 | - for (n = 0; n < 8; n++) { | ||
| 92 | - if (imm & (1 << n)) { | ||
| 93 | - imm64 |= (0xffULL << (n * 8)); | ||
| 94 | - } | ||
| 95 | - } | ||
| 96 | - return imm64; | ||
| 97 | - } | ||
| 98 | - imm |= (imm << 8) | (imm << 16) | (imm << 24); | ||
| 99 | - break; | ||
| 100 | - case 15: | ||
| 101 | - imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | ||
| 102 | - | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | ||
| 103 | - break; | ||
| 104 | - } | ||
| 105 | - if (op) { | ||
| 106 | - imm = ~imm; | ||
| 107 | - } | ||
| 108 | - return dup_const(MO_32, imm); | ||
| 109 | -} | ||
| 110 | - | ||
| 111 | static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, | ||
| 112 | GVecGen2iFn *fn) | ||
| 113 | { | ||
| 114 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 115 | index XXXXXXX..XXXXXXX 100644 | ||
| 116 | --- a/target/arm/translate.c | ||
| 117 | +++ b/target/arm/translate.c | ||
| 118 | @@ -XXX,XX +XXX,XX @@ void arm_translate_init(void) | ||
| 119 | a64_translate_init(); | ||
| 120 | } | ||
| 121 | |||
| 122 | +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) | ||
| 123 | +{ | ||
| 124 | + /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */ | ||
| 125 | + switch (cmode) { | ||
| 126 | + case 0: case 1: | ||
| 127 | + /* no-op */ | ||
| 128 | + break; | ||
| 129 | + case 2: case 3: | ||
| 130 | + imm <<= 8; | ||
| 131 | + break; | ||
| 132 | + case 4: case 5: | ||
| 133 | + imm <<= 16; | ||
| 134 | + break; | ||
| 135 | + case 6: case 7: | ||
| 136 | + imm <<= 24; | ||
| 137 | + break; | ||
| 138 | + case 8: case 9: | ||
| 139 | + imm |= imm << 16; | ||
| 140 | + break; | ||
| 141 | + case 10: case 11: | ||
| 142 | + imm = (imm << 8) | (imm << 24); | ||
| 143 | + break; | ||
| 144 | + case 12: | ||
| 145 | + imm = (imm << 8) | 0xff; | ||
| 146 | + break; | ||
| 147 | + case 13: | ||
| 148 | + imm = (imm << 16) | 0xffff; | ||
| 149 | + break; | ||
| 150 | + case 14: | ||
| 151 | + if (op) { | ||
| 152 | + /* | ||
| 153 | + * This is the only case where the top and bottom 32 bits | ||
| 154 | + * of the encoded constant differ. | ||
| 155 | + */ | ||
| 156 | + uint64_t imm64 = 0; | ||
| 157 | + int n; | ||
| 158 | + | ||
| 159 | + for (n = 0; n < 8; n++) { | ||
| 160 | + if (imm & (1 << n)) { | ||
| 161 | + imm64 |= (0xffULL << (n * 8)); | ||
| 162 | + } | ||
| 163 | + } | ||
| 164 | + return imm64; | ||
| 165 | + } | ||
| 166 | + imm |= (imm << 8) | (imm << 16) | (imm << 24); | ||
| 167 | + break; | ||
| 168 | + case 15: | ||
| 169 | + imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | ||
| 170 | + | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | ||
| 171 | + break; | ||
| 172 | + } | ||
| 173 | + if (op) { | ||
| 174 | + imm = ~imm; | ||
| 175 | + } | ||
| 176 | + return dup_const(MO_32, imm); | ||
| 177 | +} | ||
| 178 | + | ||
| 179 | /* Generate a label used for skipping this instruction */ | ||
| 180 | void arm_gen_condlabel(DisasContext *s) | ||
| 181 | { | ||
| 182 | -- | ||
| 183 | 2.20.1 | ||
| 184 | |||
| 185 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | The A64 AdvSIMD modified-immediate grouping uses almost the same | ||
| 2 | constant encoding that A32 Neon does; reuse asimd_imm_const() (to | ||
| 3 | which we add the AArch64-specific case for cmode 15 op 1) instead of | ||
| 4 | reimplementing it all. | ||
| 5 | 1 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20210628135835.6690-5-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | target/arm/translate.h | 3 +- | ||
| 11 | target/arm/translate-a64.c | 86 ++++---------------------------------- | ||
| 12 | target/arm/translate.c | 17 +++++++- | ||
| 13 | 3 files changed, 24 insertions(+), 82 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/arm/translate.h | ||
| 18 | +++ b/target/arm/translate.h | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc) | ||
| 20 | * VMVN and VBIC (when cmode < 14 && op == 1). | ||
| 21 | * | ||
| 22 | * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; | ||
| 23 | - * callers must catch this. | ||
| 24 | + * callers must catch this; we return the 64-bit constant value defined | ||
| 25 | + * for AArch64. | ||
| 26 | * | ||
| 27 | * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but | ||
| 28 | * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; | ||
| 29 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 30 | index XXXXXXX..XXXXXXX 100644 | ||
| 31 | --- a/target/arm/translate-a64.c | ||
| 32 | +++ b/target/arm/translate-a64.c | ||
| 33 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | ||
| 34 | { | ||
| 35 | int rd = extract32(insn, 0, 5); | ||
| 36 | int cmode = extract32(insn, 12, 4); | ||
| 37 | - int cmode_3_1 = extract32(cmode, 1, 3); | ||
| 38 | - int cmode_0 = extract32(cmode, 0, 1); | ||
| 39 | int o2 = extract32(insn, 11, 1); | ||
| 40 | uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); | ||
| 41 | bool is_neg = extract32(insn, 29, 1); | ||
| 42 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | ||
| 43 | return; | ||
| 44 | } | ||
| 45 | |||
| 46 | - /* See AdvSIMDExpandImm() in ARM ARM */ | ||
| 47 | - switch (cmode_3_1) { | ||
| 48 | - case 0: /* Replicate(Zeros(24):imm8, 2) */ | ||
| 49 | - case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ | ||
| 50 | - case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ | ||
| 51 | - case 3: /* Replicate(imm8:Zeros(24), 2) */ | ||
| 52 | - { | ||
| 53 | - int shift = cmode_3_1 * 8; | ||
| 54 | - imm = bitfield_replicate(abcdefgh << shift, 32); | ||
| 55 | - break; | ||
| 56 | - } | ||
| 57 | - case 4: /* Replicate(Zeros(8):imm8, 4) */ | ||
| 58 | - case 5: /* Replicate(imm8:Zeros(8), 4) */ | ||
| 59 | - { | ||
| 60 | - int shift = (cmode_3_1 & 0x1) * 8; | ||
| 61 | - imm = bitfield_replicate(abcdefgh << shift, 16); | ||
| 62 | - break; | ||
| 63 | - } | ||
| 64 | - case 6: | ||
| 65 | - if (cmode_0) { | ||
| 66 | - /* Replicate(Zeros(8):imm8:Ones(16), 2) */ | ||
| 67 | - imm = (abcdefgh << 16) | 0xffff; | ||
| 68 | - } else { | ||
| 69 | - /* Replicate(Zeros(16):imm8:Ones(8), 2) */ | ||
| 70 | - imm = (abcdefgh << 8) | 0xff; | ||
| 71 | - } | ||
| 72 | - imm = bitfield_replicate(imm, 32); | ||
| 73 | - break; | ||
| 74 | - case 7: | ||
| 75 | - if (!cmode_0 && !is_neg) { | ||
| 76 | - imm = bitfield_replicate(abcdefgh, 8); | ||
| 77 | - } else if (!cmode_0 && is_neg) { | ||
| 78 | - int i; | ||
| 79 | - imm = 0; | ||
| 80 | - for (i = 0; i < 8; i++) { | ||
| 81 | - if ((abcdefgh) & (1 << i)) { | ||
| 82 | - imm |= 0xffULL << (i * 8); | ||
| 83 | - } | ||
| 84 | - } | ||
| 85 | - } else if (cmode_0) { | ||
| 86 | - if (is_neg) { | ||
| 87 | - imm = (abcdefgh & 0x3f) << 48; | ||
| 88 | - if (abcdefgh & 0x80) { | ||
| 89 | - imm |= 0x8000000000000000ULL; | ||
| 90 | - } | ||
| 91 | - if (abcdefgh & 0x40) { | ||
| 92 | - imm |= 0x3fc0000000000000ULL; | ||
| 93 | - } else { | ||
| 94 | - imm |= 0x4000000000000000ULL; | ||
| 95 | - } | ||
| 96 | - } else { | ||
| 97 | - if (o2) { | ||
| 98 | - /* FMOV (vector, immediate) - half-precision */ | ||
| 99 | - imm = vfp_expand_imm(MO_16, abcdefgh); | ||
| 100 | - /* now duplicate across the lanes */ | ||
| 101 | - imm = bitfield_replicate(imm, 16); | ||
| 102 | - } else { | ||
| 103 | - imm = (abcdefgh & 0x3f) << 19; | ||
| 104 | - if (abcdefgh & 0x80) { | ||
| 105 | - imm |= 0x80000000; | ||
| 106 | - } | ||
| 107 | - if (abcdefgh & 0x40) { | ||
| 108 | - imm |= 0x3e000000; | ||
| 109 | - } else { | ||
| 110 | - imm |= 0x40000000; | ||
| 111 | - } | ||
| 112 | - imm |= (imm << 32); | ||
| 113 | - } | ||
| 114 | - } | ||
| 115 | - } | ||
| 116 | - break; | ||
| 117 | - default: | ||
| 118 | - g_assert_not_reached(); | ||
| 119 | - } | ||
| 120 | - | ||
| 121 | - if (cmode_3_1 != 7 && is_neg) { | ||
| 122 | - imm = ~imm; | ||
| 123 | + if (cmode == 15 && o2 && !is_neg) { | ||
| 124 | + /* FMOV (vector, immediate) - half-precision */ | ||
| 125 | + imm = vfp_expand_imm(MO_16, abcdefgh); | ||
| 126 | + /* now duplicate across the lanes */ | ||
| 127 | + imm = bitfield_replicate(imm, 16); | ||
| 128 | + } else { | ||
| 129 | + imm = asimd_imm_const(abcdefgh, cmode, is_neg); | ||
| 130 | } | ||
| 131 | |||
| 132 | if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) { | ||
| 133 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 134 | index XXXXXXX..XXXXXXX 100644 | ||
| 135 | --- a/target/arm/translate.c | ||
| 136 | +++ b/target/arm/translate.c | ||
| 137 | @@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) | ||
| 138 | case 14: | ||
| 139 | if (op) { | ||
| 140 | /* | ||
| 141 | - * This is the only case where the top and bottom 32 bits | ||
| 142 | - * of the encoded constant differ. | ||
| 143 | + * This and cmode == 15 op == 1 are the only cases where | ||
| 144 | + * the top and bottom 32 bits of the encoded constant differ. | ||
| 145 | */ | ||
| 146 | uint64_t imm64 = 0; | ||
| 147 | int n; | ||
| 148 | @@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) | ||
| 149 | imm |= (imm << 8) | (imm << 16) | (imm << 24); | ||
| 150 | break; | ||
| 151 | case 15: | ||
| 152 | + if (op) { | ||
| 153 | + /* Reserved encoding for AArch32; valid for AArch64 */ | ||
| 154 | + uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48; | ||
| 155 | + if (imm & 0x80) { | ||
| 156 | + imm64 |= 0x8000000000000000ULL; | ||
| 157 | + } | ||
| 158 | + if (imm & 0x40) { | ||
| 159 | + imm64 |= 0x3fc0000000000000ULL; | ||
| 160 | + } else { | ||
| 161 | + imm64 |= 0x4000000000000000ULL; | ||
| 162 | + } | ||
| 163 | + return imm64; | ||
| 164 | + } | ||
| 165 | imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | ||
| 166 | | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | ||
| 167 | break; | ||
| 168 | -- | ||
| 169 | 2.20.1 | ||
| 170 | |||
| 171 | diff view generated by jsdifflib |
| 1 | Use dup_const() instead of bitfield_replicate() in | 1 | In commit 39a1fd25287f5d we fixed a bug in the handling of LPAE block |
|---|---|---|---|
| 2 | disas_simd_mod_imm(). | 2 | descriptors where we weren't correctly zeroing out some RES0 bits. |
| 3 | However this fix has a bug because the calculation of the mask is | ||
| 4 | done at the wrong width: in | ||
| 5 | descaddr &= ~(page_size - 1); | ||
| 6 | page_size is a target_ulong, so in the 'qemu-system-arm' binary it is | ||
| 7 | only 32 bits, and the effect is that we always zero out the top 32 | ||
| 8 | bits of the calculated address. Fix the calculation by forcing the | ||
| 9 | mask to be calculated with the same type as descaddr. | ||
| 3 | 10 | ||
| 4 | (We can't replace the other use of bitfield_replicate() in this file, | 11 | This only affects 32-bit CPUs which support LPAE (e.g. cortex-a15) |
| 5 | in logic_imm_decode_wmask(), because that location needs to handle 2 | 12 | when used on board models which put RAM or devices above the 4GB |
| 6 | and 4 bit elements, which dup_const() cannot.) | 13 | mark and when the 'qemu-system-arm' executable is being used. |
| 14 | It was also masked in 7.0 by the main bug reported in | ||
| 15 | https://gitlab.com/qemu-project/qemu/-/issues/1078 where the | ||
| 16 | virt board incorrectly does not enable 'highmem' for 32-bit CPUs. | ||
| 7 | 17 | ||
| 18 | The workaround is to use 'qemu-system-aarch64' with the same | ||
| 19 | command line. | ||
| 20 | |||
| 21 | Reported-by: He Zhe <zhe.he@windriver.com> | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 23 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 10 | Message-id: 20210628135835.6690-6-peter.maydell@linaro.org | 24 | Message-id: 20220627134620.3190252-1-peter.maydell@linaro.org |
| 25 | Fixes: 39a1fd25287f5de ("target/arm: Fix handling of LPAE block descriptors") | ||
| 26 | Cc: qemu-stable@nongnu.org | ||
| 27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | 28 | --- |
| 12 | target/arm/translate-a64.c | 2 +- | 29 | target/arm/ptw.c | 2 +- |
| 13 | 1 file changed, 1 insertion(+), 1 deletion(-) | 30 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 14 | 31 | ||
| 15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 32 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/target/arm/translate-a64.c | 34 | --- a/target/arm/ptw.c |
| 18 | +++ b/target/arm/translate-a64.c | 35 | +++ b/target/arm/ptw.c |
| 19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | 36 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, |
| 20 | /* FMOV (vector, immediate) - half-precision */ | 37 | * clear the lower bits here before ORing in the low vaddr bits. |
| 21 | imm = vfp_expand_imm(MO_16, abcdefgh); | 38 | */ |
| 22 | /* now duplicate across the lanes */ | 39 | page_size = (1ULL << ((stride * (4 - level)) + 3)); |
| 23 | - imm = bitfield_replicate(imm, 16); | 40 | - descaddr &= ~(page_size - 1); |
| 24 | + imm = dup_const(MO_16, imm); | 41 | + descaddr &= ~(hwaddr)(page_size - 1); |
| 25 | } else { | 42 | descaddr |= (address & (page_size - 1)); |
| 26 | imm = asimd_imm_const(abcdefgh, cmode, is_neg); | 43 | /* Extract attributes from the descriptor */ |
| 27 | } | 44 | attrs = extract64(descriptor, 2, 10) |
| 28 | -- | 45 | -- |
| 29 | 2.20.1 | 46 | 2.25.1 |
| 30 | |||
| 31 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Implement the MVE logical-immediate insns (VMOV, VMVN, | ||
| 2 | VORR and VBIC). These have essentially the same encoding | ||
| 3 | as their Neon equivalents, and we implement the decode | ||
| 4 | in the same way. | ||
| 5 | 1 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20210628135835.6690-7-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | target/arm/helper-mve.h | 4 +++ | ||
| 11 | target/arm/mve.decode | 17 +++++++++++++ | ||
| 12 | target/arm/mve_helper.c | 24 ++++++++++++++++++ | ||
| 13 | target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++ | ||
| 14 | 4 files changed, 95 insertions(+) | ||
| 15 | |||
| 16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/arm/helper-mve.h | ||
| 19 | +++ b/target/arm/helper-mve.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
| 21 | DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
| 22 | DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
| 23 | DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
| 24 | + | ||
| 25 | +DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
| 26 | +DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
| 27 | +DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
| 28 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/target/arm/mve.decode | ||
| 31 | +++ b/target/arm/mve.decode | ||
| 32 | @@ -XXX,XX +XXX,XX @@ | ||
| 33 | # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit | ||
| 34 | %size_28 28:1 !function=plus_1 | ||
| 35 | |||
| 36 | +# 1imm format immediate | ||
| 37 | +%imm_28_16_0 28:1 16:3 0:4 | ||
| 38 | + | ||
| 39 | &vldr_vstr rn qd imm p a w size l u | ||
| 40 | &1op qd qm size | ||
| 41 | &2op qd qm qn size | ||
| 42 | &2scalar qd qn rm size | ||
| 43 | +&1imm qd imm cmode op | ||
| 44 | |||
| 45 | @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 | ||
| 46 | # Note that both Rn and Qd are 3 bits only (no D bit) | ||
| 47 | @@ -XXX,XX +XXX,XX @@ | ||
| 48 | @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0 | ||
| 49 | @2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \ | ||
| 50 | size=%size_28 | ||
| 51 | +@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0 | ||
| 52 | |||
| 53 | # The _rev suffix indicates that Vn and Vm are reversed. This is | ||
| 54 | # the case for shifts. In the Arm ARM these insns are documented | ||
| 55 | @@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd | ||
| 56 | # Predicate operations | ||
| 57 | %mask_22_13 22:1 13:3 | ||
| 58 | VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 | ||
| 59 | + | ||
| 60 | +# Logical immediate operations (1 reg and modified-immediate) | ||
| 61 | + | ||
| 62 | +# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but | ||
| 63 | +# not in a way we can conveniently represent in decodetree without | ||
| 64 | +# a lot of repetition: | ||
| 65 | +# VORR: op=0, (cmode & 1) && cmode < 12 | ||
| 66 | +# VBIC: op=1, (cmode & 1) && cmode < 12 | ||
| 67 | +# VMOV: everything else | ||
| 68 | +# So we have a single decode line and check the cmode/op in the | ||
| 69 | +# trans function. | ||
| 70 | +Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm | ||
| 71 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
| 72 | index XXXXXXX..XXXXXXX 100644 | ||
| 73 | --- a/target/arm/mve_helper.c | ||
| 74 | +++ b/target/arm/mve_helper.c | ||
| 75 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG) | ||
| 76 | DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) | ||
| 77 | DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) | ||
| 78 | |||
| 79 | +/* | ||
| 80 | + * 1 operand immediates: Vda is destination and possibly also one source. | ||
| 81 | + * All these insns work at 64-bit widths. | ||
| 82 | + */ | ||
| 83 | +#define DO_1OP_IMM(OP, FN) \ | ||
| 84 | + void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ | ||
| 85 | + { \ | ||
| 86 | + uint64_t *da = vda; \ | ||
| 87 | + uint16_t mask = mve_element_mask(env); \ | ||
| 88 | + unsigned e; \ | ||
| 89 | + for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ | ||
| 90 | + mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ | ||
| 91 | + } \ | ||
| 92 | + mve_advance_vpt(env); \ | ||
| 93 | + } | ||
| 94 | + | ||
| 95 | +#define DO_MOVI(N, I) (I) | ||
| 96 | +#define DO_ANDI(N, I) ((N) & (I)) | ||
| 97 | +#define DO_ORRI(N, I) ((N) | (I)) | ||
| 98 | + | ||
| 99 | +DO_1OP_IMM(vmovi, DO_MOVI) | ||
| 100 | +DO_1OP_IMM(vandi, DO_ANDI) | ||
| 101 | +DO_1OP_IMM(vorri, DO_ORRI) | ||
| 102 | + | ||
| 103 | #define DO_2OP(OP, ESIZE, TYPE, FN) \ | ||
| 104 | void HELPER(glue(mve_, OP))(CPUARMState *env, \ | ||
| 105 | void *vd, void *vn, void *vm) \ | ||
| 106 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
| 107 | index XXXXXXX..XXXXXXX 100644 | ||
| 108 | --- a/target/arm/translate-mve.c | ||
| 109 | +++ b/target/arm/translate-mve.c | ||
| 110 | @@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
| 111 | typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
| 112 | typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
| 113 | typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
| 114 | +typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
| 115 | |||
| 116 | /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ | ||
| 117 | static inline long mve_qreg_offset(unsigned reg) | ||
| 118 | @@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a) | ||
| 119 | mve_update_eci(s); | ||
| 120 | return true; | ||
| 121 | } | ||
| 122 | + | ||
| 123 | +static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) | ||
| 124 | +{ | ||
| 125 | + TCGv_ptr qd; | ||
| 126 | + uint64_t imm; | ||
| 127 | + | ||
| 128 | + if (!dc_isar_feature(aa32_mve, s) || | ||
| 129 | + !mve_check_qreg_bank(s, a->qd) || | ||
| 130 | + !fn) { | ||
| 131 | + return false; | ||
| 132 | + } | ||
| 133 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
| 134 | + return true; | ||
| 135 | + } | ||
| 136 | + | ||
| 137 | + imm = asimd_imm_const(a->imm, a->cmode, a->op); | ||
| 138 | + | ||
| 139 | + qd = mve_qreg_ptr(a->qd); | ||
| 140 | + fn(cpu_env, qd, tcg_constant_i64(imm)); | ||
| 141 | + tcg_temp_free_ptr(qd); | ||
| 142 | + mve_update_eci(s); | ||
| 143 | + return true; | ||
| 144 | +} | ||
| 145 | + | ||
| 146 | +static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) | ||
| 147 | +{ | ||
| 148 | + /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ | ||
| 149 | + MVEGenOneOpImmFn *fn; | ||
| 150 | + | ||
| 151 | + if ((a->cmode & 1) && a->cmode < 12) { | ||
| 152 | + if (a->op) { | ||
| 153 | + /* | ||
| 154 | + * For op=1, the immediate will be inverted by asimd_imm_const(), | ||
| 155 | + * so the VBIC becomes a logical AND operation. | ||
| 156 | + */ | ||
| 157 | + fn = gen_helper_mve_vandi; | ||
| 158 | + } else { | ||
| 159 | + fn = gen_helper_mve_vorri; | ||
| 160 | + } | ||
| 161 | + } else { | ||
| 162 | + /* There is one unallocated cmode/op combination in this space */ | ||
| 163 | + if (a->cmode == 15 && a->op == 1) { | ||
| 164 | + return false; | ||
| 165 | + } | ||
| 166 | + /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */ | ||
| 167 | + fn = gen_helper_mve_vmovi; | ||
| 168 | + } | ||
| 169 | + return do_1imm(s, a, fn); | ||
| 170 | +} | ||
| 171 | -- | ||
| 172 | 2.20.1 | ||
| 173 | |||
| 174 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL | ||
| 2 | and VQSHLU. | ||
| 3 | 1 | ||
| 4 | The size-and-immediate encoding here is the same as Neon, and we | ||
| 5 | handle it the same way neon-dp.decode does. | ||
| 6 | |||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20210628135835.6690-8-peter.maydell@linaro.org | ||
| 10 | --- | ||
| 11 | target/arm/helper-mve.h | 16 +++++++++++ | ||
| 12 | target/arm/mve.decode | 23 +++++++++++++++ | ||
| 13 | target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++ | ||
| 14 | target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++ | ||
| 15 | 4 files changed, 147 insertions(+) | ||
| 16 | |||
| 17 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | ||
| 19 | --- a/target/arm/helper-mve.h | ||
| 20 | +++ b/target/arm/helper-mve.h | ||
| 21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
| 22 | DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
| 23 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
| 24 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
| 25 | + | ||
| 26 | +DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 27 | +DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 28 | +DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 29 | + | ||
| 30 | +DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 31 | +DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 32 | +DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 33 | + | ||
| 34 | +DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 35 | +DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 36 | +DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 37 | + | ||
| 38 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 39 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 40 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 41 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
| 42 | index XXXXXXX..XXXXXXX 100644 | ||
| 43 | --- a/target/arm/mve.decode | ||
| 44 | +++ b/target/arm/mve.decode | ||
| 45 | @@ -XXX,XX +XXX,XX @@ | ||
| 46 | &2op qd qm qn size | ||
| 47 | &2scalar qd qn rm size | ||
| 48 | &1imm qd imm cmode op | ||
| 49 | +&2shift qd qm shift size | ||
| 50 | |||
| 51 | @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 | ||
| 52 | # Note that both Rn and Qd are 3 bits only (no D bit) | ||
| 53 | @@ -XXX,XX +XXX,XX @@ | ||
| 54 | @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn | ||
| 55 | @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn | ||
| 56 | |||
| 57 | +@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0 | ||
| 58 | +@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 | ||
| 59 | +@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 | ||
| 60 | + | ||
| 61 | # Vector loads and stores | ||
| 62 | |||
| 63 | # Widening loads and narrowing stores: | ||
| 64 | @@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 | ||
| 65 | # So we have a single decode line and check the cmode/op in the | ||
| 66 | # trans function. | ||
| 67 | Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm | ||
| 68 | + | ||
| 69 | +# Shifts by immediate | ||
| 70 | + | ||
| 71 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b | ||
| 72 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h | ||
| 73 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w | ||
| 74 | + | ||
| 75 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b | ||
| 76 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h | ||
| 77 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
| 78 | + | ||
| 79 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b | ||
| 80 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h | ||
| 81 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
| 82 | + | ||
| 83 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b | ||
| 84 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h | ||
| 85 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w | ||
| 86 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
| 87 | index XXXXXXX..XXXXXXX 100644 | ||
| 88 | --- a/target/arm/mve_helper.c | ||
| 89 | +++ b/target/arm/mve_helper.c | ||
| 90 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) | ||
| 91 | WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) | ||
| 92 | #define DO_UQRSHL_OP(N, M, satp) \ | ||
| 93 | WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) | ||
| 94 | +#define DO_SUQSHL_OP(N, M, satp) \ | ||
| 95 | + WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) | ||
| 96 | |||
| 97 | DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) | ||
| 98 | DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) | ||
| 99 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t) | ||
| 100 | DO_VADDV(vaddvub, 1, uint8_t) | ||
| 101 | DO_VADDV(vaddvuh, 2, uint16_t) | ||
| 102 | DO_VADDV(vaddvuw, 4, uint32_t) | ||
| 103 | + | ||
| 104 | +/* Shifts by immediate */ | ||
| 105 | +#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ | ||
| 106 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
| 107 | + void *vm, uint32_t shift) \ | ||
| 108 | + { \ | ||
| 109 | + TYPE *d = vd, *m = vm; \ | ||
| 110 | + uint16_t mask = mve_element_mask(env); \ | ||
| 111 | + unsigned e; \ | ||
| 112 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
| 113 | + mergemask(&d[H##ESIZE(e)], \ | ||
| 114 | + FN(m[H##ESIZE(e)], shift), mask); \ | ||
| 115 | + } \ | ||
| 116 | + mve_advance_vpt(env); \ | ||
| 117 | + } | ||
| 118 | + | ||
| 119 | +#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ | ||
| 120 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
| 121 | + void *vm, uint32_t shift) \ | ||
| 122 | + { \ | ||
| 123 | + TYPE *d = vd, *m = vm; \ | ||
| 124 | + uint16_t mask = mve_element_mask(env); \ | ||
| 125 | + unsigned e; \ | ||
| 126 | + bool qc = false; \ | ||
| 127 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
| 128 | + bool sat = false; \ | ||
| 129 | + mergemask(&d[H##ESIZE(e)], \ | ||
| 130 | + FN(m[H##ESIZE(e)], shift, &sat), mask); \ | ||
| 131 | + qc |= sat & mask & 1; \ | ||
| 132 | + } \ | ||
| 133 | + if (qc) { \ | ||
| 134 | + env->vfp.qc[0] = qc; \ | ||
| 135 | + } \ | ||
| 136 | + mve_advance_vpt(env); \ | ||
| 137 | + } | ||
| 138 | + | ||
| 139 | +/* provide unsigned 2-op shift helpers for all sizes */ | ||
| 140 | +#define DO_2SHIFT_U(OP, FN) \ | ||
| 141 | + DO_2SHIFT(OP##b, 1, uint8_t, FN) \ | ||
| 142 | + DO_2SHIFT(OP##h, 2, uint16_t, FN) \ | ||
| 143 | + DO_2SHIFT(OP##w, 4, uint32_t, FN) | ||
| 144 | + | ||
| 145 | +#define DO_2SHIFT_SAT_U(OP, FN) \ | ||
| 146 | + DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ | ||
| 147 | + DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ | ||
| 148 | + DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) | ||
| 149 | +#define DO_2SHIFT_SAT_S(OP, FN) \ | ||
| 150 | + DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ | ||
| 151 | + DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ | ||
| 152 | + DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) | ||
| 153 | + | ||
| 154 | +DO_2SHIFT_U(vshli_u, DO_VSHLU) | ||
| 155 | +DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) | ||
| 156 | +DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) | ||
| 157 | +DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
| 158 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
| 159 | index XXXXXXX..XXXXXXX 100644 | ||
| 160 | --- a/target/arm/translate-mve.c | ||
| 161 | +++ b/target/arm/translate-mve.c | ||
| 162 | @@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
| 163 | typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
| 164 | typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
| 165 | typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
| 166 | +typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
| 167 | typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
| 168 | typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
| 169 | typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
| 170 | @@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) | ||
| 171 | } | ||
| 172 | return do_1imm(s, a, fn); | ||
| 173 | } | ||
| 174 | + | ||
| 175 | +static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, | ||
| 176 | + bool negateshift) | ||
| 177 | +{ | ||
| 178 | + TCGv_ptr qd, qm; | ||
| 179 | + int shift = a->shift; | ||
| 180 | + | ||
| 181 | + if (!dc_isar_feature(aa32_mve, s) || | ||
| 182 | + !mve_check_qreg_bank(s, a->qd | a->qm) || | ||
| 183 | + !fn) { | ||
| 184 | + return false; | ||
| 185 | + } | ||
| 186 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
| 187 | + return true; | ||
| 188 | + } | ||
| 189 | + | ||
| 190 | + /* | ||
| 191 | + * When we handle a right shift insn using a left-shift helper | ||
| 192 | + * which permits a negative shift count to indicate a right-shift, | ||
| 193 | + * we must negate the shift count. | ||
| 194 | + */ | ||
| 195 | + if (negateshift) { | ||
| 196 | + shift = -shift; | ||
| 197 | + } | ||
| 198 | + | ||
| 199 | + qd = mve_qreg_ptr(a->qd); | ||
| 200 | + qm = mve_qreg_ptr(a->qm); | ||
| 201 | + fn(cpu_env, qd, qm, tcg_constant_i32(shift)); | ||
| 202 | + tcg_temp_free_ptr(qd); | ||
| 203 | + tcg_temp_free_ptr(qm); | ||
| 204 | + mve_update_eci(s); | ||
| 205 | + return true; | ||
| 206 | +} | ||
| 207 | + | ||
| 208 | +#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \ | ||
| 209 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | ||
| 210 | + { \ | ||
| 211 | + static MVEGenTwoOpShiftFn * const fns[] = { \ | ||
| 212 | + gen_helper_mve_##FN##b, \ | ||
| 213 | + gen_helper_mve_##FN##h, \ | ||
| 214 | + gen_helper_mve_##FN##w, \ | ||
| 215 | + NULL, \ | ||
| 216 | + }; \ | ||
| 217 | + return do_2shift(s, a, fns[a->size], NEGATESHIFT); \ | ||
| 218 | + } | ||
| 219 | + | ||
| 220 | +DO_2SHIFT(VSHLI, vshli_u, false) | ||
| 221 | +DO_2SHIFT(VQSHLI_S, vqshli_s, false) | ||
| 222 | +DO_2SHIFT(VQSHLI_U, vqshli_u, false) | ||
| 223 | +DO_2SHIFT(VQSHLUI, vqshlui_s, false) | ||
| 224 | -- | ||
| 225 | 2.20.1 | ||
| 226 | |||
| 227 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Implement the MVE vector shift right by immediate insns VSHRI and | ||
| 2 | VRSHRI. As with Neon, we implement these by using helper functions | ||
| 3 | which perform left shifts but allow negative shift counts to indicate | ||
| 4 | right shifts. | ||
| 5 | 1 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20210628135835.6690-9-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | target/arm/helper-mve.h | 12 ++++++++++++ | ||
| 11 | target/arm/translate.h | 20 ++++++++++++++++++++ | ||
| 12 | target/arm/mve.decode | 28 ++++++++++++++++++++++++++++ | ||
| 13 | target/arm/mve_helper.c | 7 +++++++ | ||
| 14 | target/arm/translate-mve.c | 5 +++++ | ||
| 15 | target/arm/translate-neon.c | 18 ------------------ | ||
| 16 | 6 files changed, 72 insertions(+), 18 deletions(-) | ||
| 17 | |||
| 18 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/target/arm/helper-mve.h | ||
| 21 | +++ b/target/arm/helper-mve.h | ||
| 22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
| 23 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
| 24 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
| 25 | |||
| 26 | +DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 27 | +DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 28 | +DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 29 | + | ||
| 30 | DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 31 | DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 32 | DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 33 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 34 | DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 35 | DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 36 | DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 37 | + | ||
| 38 | +DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 39 | +DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 40 | +DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 41 | + | ||
| 42 | +DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 43 | +DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 44 | +DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 45 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
| 46 | index XXXXXXX..XXXXXXX 100644 | ||
| 47 | --- a/target/arm/translate.h | ||
| 48 | +++ b/target/arm/translate.h | ||
| 49 | @@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x) | ||
| 50 | return x * 2 + 1; | ||
| 51 | } | ||
| 52 | |||
| 53 | +static inline int rsub_64(DisasContext *s, int x) | ||
| 54 | +{ | ||
| 55 | + return 64 - x; | ||
| 56 | +} | ||
| 57 | + | ||
| 58 | +static inline int rsub_32(DisasContext *s, int x) | ||
| 59 | +{ | ||
| 60 | + return 32 - x; | ||
| 61 | +} | ||
| 62 | + | ||
| 63 | +static inline int rsub_16(DisasContext *s, int x) | ||
| 64 | +{ | ||
| 65 | + return 16 - x; | ||
| 66 | +} | ||
| 67 | + | ||
| 68 | +static inline int rsub_8(DisasContext *s, int x) | ||
| 69 | +{ | ||
| 70 | + return 8 - x; | ||
| 71 | +} | ||
| 72 | + | ||
| 73 | static inline int arm_dc_feature(DisasContext *dc, int feature) | ||
| 74 | { | ||
| 75 | return (dc->features & (1ULL << feature)) != 0; | ||
| 76 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
| 77 | index XXXXXXX..XXXXXXX 100644 | ||
| 78 | --- a/target/arm/mve.decode | ||
| 79 | +++ b/target/arm/mve.decode | ||
| 80 | @@ -XXX,XX +XXX,XX @@ | ||
| 81 | @2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 | ||
| 82 | @2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 | ||
| 83 | |||
| 84 | +# Right shifts are encoded as N - shift, where N is the element size in bits. | ||
| 85 | +%rshift_i5 16:5 !function=rsub_32 | ||
| 86 | +%rshift_i4 16:4 !function=rsub_16 | ||
| 87 | +%rshift_i3 16:3 !function=rsub_8 | ||
| 88 | + | ||
| 89 | +@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
| 90 | + size=0 shift=%rshift_i3 | ||
| 91 | +@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
| 92 | + size=1 shift=%rshift_i4 | ||
| 93 | +@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
| 94 | + size=2 shift=%rshift_i5 | ||
| 95 | + | ||
| 96 | # Vector loads and stores | ||
| 97 | |||
| 98 | # Widening loads and narrowing stores: | ||
| 99 | @@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
| 100 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b | ||
| 101 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h | ||
| 102 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w | ||
| 103 | + | ||
| 104 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b | ||
| 105 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h | ||
| 106 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w | ||
| 107 | + | ||
| 108 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b | ||
| 109 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h | ||
| 110 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w | ||
| 111 | + | ||
| 112 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | ||
| 113 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | ||
| 114 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
| 115 | + | ||
| 116 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | ||
| 117 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | ||
| 118 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
| 119 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
| 120 | index XXXXXXX..XXXXXXX 100644 | ||
| 121 | --- a/target/arm/mve_helper.c | ||
| 122 | +++ b/target/arm/mve_helper.c | ||
| 123 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t) | ||
| 124 | DO_2SHIFT(OP##b, 1, uint8_t, FN) \ | ||
| 125 | DO_2SHIFT(OP##h, 2, uint16_t, FN) \ | ||
| 126 | DO_2SHIFT(OP##w, 4, uint32_t, FN) | ||
| 127 | +#define DO_2SHIFT_S(OP, FN) \ | ||
| 128 | + DO_2SHIFT(OP##b, 1, int8_t, FN) \ | ||
| 129 | + DO_2SHIFT(OP##h, 2, int16_t, FN) \ | ||
| 130 | + DO_2SHIFT(OP##w, 4, int32_t, FN) | ||
| 131 | |||
| 132 | #define DO_2SHIFT_SAT_U(OP, FN) \ | ||
| 133 | DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ | ||
| 134 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t) | ||
| 135 | DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) | ||
| 136 | |||
| 137 | DO_2SHIFT_U(vshli_u, DO_VSHLU) | ||
| 138 | +DO_2SHIFT_S(vshli_s, DO_VSHLS) | ||
| 139 | DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) | ||
| 140 | DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) | ||
| 141 | DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
| 142 | +DO_2SHIFT_U(vrshli_u, DO_VRSHLU) | ||
| 143 | +DO_2SHIFT_S(vrshli_s, DO_VRSHLS) | ||
| 144 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
| 145 | index XXXXXXX..XXXXXXX 100644 | ||
| 146 | --- a/target/arm/translate-mve.c | ||
| 147 | +++ b/target/arm/translate-mve.c | ||
| 148 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false) | ||
| 149 | DO_2SHIFT(VQSHLI_S, vqshli_s, false) | ||
| 150 | DO_2SHIFT(VQSHLI_U, vqshli_u, false) | ||
| 151 | DO_2SHIFT(VQSHLUI, vqshlui_s, false) | ||
| 152 | +/* These right shifts use a left-shift helper with negated shift count */ | ||
| 153 | +DO_2SHIFT(VSHRI_S, vshli_s, true) | ||
| 154 | +DO_2SHIFT(VSHRI_U, vshli_u, true) | ||
| 155 | +DO_2SHIFT(VRSHRI_S, vrshli_s, true) | ||
| 156 | +DO_2SHIFT(VRSHRI_U, vrshli_u, true) | ||
| 157 | diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c | ||
| 158 | index XXXXXXX..XXXXXXX 100644 | ||
| 159 | --- a/target/arm/translate-neon.c | ||
| 160 | +++ b/target/arm/translate-neon.c | ||
| 161 | @@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x) | ||
| 162 | return x + 1; | ||
| 163 | } | ||
| 164 | |||
| 165 | -static inline int rsub_64(DisasContext *s, int x) | ||
| 166 | -{ | ||
| 167 | - return 64 - x; | ||
| 168 | -} | ||
| 169 | - | ||
| 170 | -static inline int rsub_32(DisasContext *s, int x) | ||
| 171 | -{ | ||
| 172 | - return 32 - x; | ||
| 173 | -} | ||
| 174 | -static inline int rsub_16(DisasContext *s, int x) | ||
| 175 | -{ | ||
| 176 | - return 16 - x; | ||
| 177 | -} | ||
| 178 | -static inline int rsub_8(DisasContext *s, int x) | ||
| 179 | -{ | ||
| 180 | - return 8 - x; | ||
| 181 | -} | ||
| 182 | - | ||
| 183 | static inline int neon_3same_fp_size(DisasContext *s, int x) | ||
| 184 | { | ||
| 185 | /* Convert 0==fp32, 1==fp16 into a MO_* value */ | ||
| 186 | -- | ||
| 187 | 2.20.1 | ||
| 188 | |||
| 189 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Implement the MVE VHLL (vector shift left long) insn. This has two | ||
| 2 | encodings: the T1 encoding is the usual shift-by-immediate format, | ||
| 3 | and the T2 encoding is a special case where the shift count is always | ||
| 4 | equal to the element size. | ||
| 5 | 1 | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20210628135835.6690-10-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | target/arm/helper-mve.h | 9 +++++++ | ||
| 11 | target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++--- | ||
| 12 | target/arm/mve_helper.c | 32 +++++++++++++++++++++++ | ||
| 13 | target/arm/translate-mve.c | 15 +++++++++++ | ||
| 14 | 4 files changed, 105 insertions(+), 4 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/arm/helper-mve.h | ||
| 19 | +++ b/target/arm/helper-mve.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 21 | DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 22 | DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 23 | DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 24 | + | ||
| 25 | +DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 26 | +DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 27 | +DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 28 | +DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 29 | +DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 30 | +DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 31 | +DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 32 | +DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
| 34 | index XXXXXXX..XXXXXXX 100644 | ||
| 35 | --- a/target/arm/mve.decode | ||
| 36 | +++ b/target/arm/mve.decode | ||
| 37 | @@ -XXX,XX +XXX,XX @@ | ||
| 38 | @2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 | ||
| 39 | @2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 | ||
| 40 | |||
| 41 | +@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0 | ||
| 42 | +@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 | ||
| 43 | +# VSHLL encoding T2 where shift == esize | ||
| 44 | +@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \ | ||
| 45 | + qd=%qd qm=%qm size=0 shift=8 | ||
| 46 | +@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \ | ||
| 47 | + qd=%qd qm=%qm size=1 shift=16 | ||
| 48 | + | ||
| 49 | # Right shifts are encoded as N - shift, where N is the element size in bits. | ||
| 50 | %rshift_i5 16:5 !function=rsub_32 | ||
| 51 | %rshift_i4 16:4 !function=rsub_16 | ||
| 52 | @@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op | ||
| 53 | VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op | ||
| 54 | VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op | ||
| 55 | |||
| 56 | -VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
| 57 | -VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
| 58 | +# The VSHLL T2 encoding is not a @2op pattern, but is here because it | ||
| 59 | +# overlaps what would be size=0b11 VMULH/VRMULH | ||
| 60 | +{ | ||
| 61 | + VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b | ||
| 62 | + VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h | ||
| 63 | |||
| 64 | -VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | ||
| 65 | -VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | ||
| 66 | + VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
| 67 | +} | ||
| 68 | + | ||
| 69 | +{ | ||
| 70 | + VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b | ||
| 71 | + VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h | ||
| 72 | + | ||
| 73 | + VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
| 74 | +} | ||
| 75 | + | ||
| 76 | +{ | ||
| 77 | + VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b | ||
| 78 | + VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h | ||
| 79 | + | ||
| 80 | + VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | ||
| 81 | +} | ||
| 82 | + | ||
| 83 | +{ | ||
| 84 | + VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b | ||
| 85 | + VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h | ||
| 86 | + | ||
| 87 | + VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | ||
| 88 | +} | ||
| 89 | |||
| 90 | VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op | ||
| 91 | VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op | ||
| 92 | @@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
| 93 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | ||
| 94 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | ||
| 95 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
| 96 | + | ||
| 97 | +# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file | ||
| 98 | +VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b | ||
| 99 | +VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h | ||
| 100 | + | ||
| 101 | +VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b | ||
| 102 | +VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h | ||
| 103 | + | ||
| 104 | +VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b | ||
| 105 | +VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h | ||
| 106 | + | ||
| 107 | +VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b | ||
| 108 | +VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h | ||
| 109 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
| 110 | index XXXXXXX..XXXXXXX 100644 | ||
| 111 | --- a/target/arm/mve_helper.c | ||
| 112 | +++ b/target/arm/mve_helper.c | ||
| 113 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) | ||
| 114 | DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
| 115 | DO_2SHIFT_U(vrshli_u, DO_VRSHLU) | ||
| 116 | DO_2SHIFT_S(vrshli_s, DO_VRSHLS) | ||
| 117 | + | ||
| 118 | +/* | ||
| 119 | + * Long shifts taking half-sized inputs from top or bottom of the input | ||
| 120 | + * vector and producing a double-width result. ESIZE, TYPE are for | ||
| 121 | + * the input, and LESIZE, LTYPE for the output. | ||
| 122 | + * Unlike the normal shift helpers, we do not handle negative shift counts, | ||
| 123 | + * because the long shift is strictly left-only. | ||
| 124 | + */ | ||
| 125 | +#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ | ||
| 126 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
| 127 | + void *vm, uint32_t shift) \ | ||
| 128 | + { \ | ||
| 129 | + LTYPE *d = vd; \ | ||
| 130 | + TYPE *m = vm; \ | ||
| 131 | + uint16_t mask = mve_element_mask(env); \ | ||
| 132 | + unsigned le; \ | ||
| 133 | + assert(shift <= 16); \ | ||
| 134 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | ||
| 135 | + LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ | ||
| 136 | + mergemask(&d[H##LESIZE(le)], r, mask); \ | ||
| 137 | + } \ | ||
| 138 | + mve_advance_vpt(env); \ | ||
| 139 | + } | ||
| 140 | + | ||
| 141 | +#define DO_VSHLL_ALL(OP, TOP) \ | ||
| 142 | + DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ | ||
| 143 | + DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ | ||
| 144 | + DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ | ||
| 145 | + DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ | ||
| 146 | + | ||
| 147 | +DO_VSHLL_ALL(vshllb, false) | ||
| 148 | +DO_VSHLL_ALL(vshllt, true) | ||
| 149 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
| 150 | index XXXXXXX..XXXXXXX 100644 | ||
| 151 | --- a/target/arm/translate-mve.c | ||
| 152 | +++ b/target/arm/translate-mve.c | ||
| 153 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true) | ||
| 154 | DO_2SHIFT(VSHRI_U, vshli_u, true) | ||
| 155 | DO_2SHIFT(VRSHRI_S, vrshli_s, true) | ||
| 156 | DO_2SHIFT(VRSHRI_U, vrshli_u, true) | ||
| 157 | + | ||
| 158 | +#define DO_VSHLL(INSN, FN) \ | ||
| 159 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | ||
| 160 | + { \ | ||
| 161 | + static MVEGenTwoOpShiftFn * const fns[] = { \ | ||
| 162 | + gen_helper_mve_##FN##b, \ | ||
| 163 | + gen_helper_mve_##FN##h, \ | ||
| 164 | + }; \ | ||
| 165 | + return do_2shift(s, a, fns[a->size], false); \ | ||
| 166 | + } | ||
| 167 | + | ||
| 168 | +DO_VSHLL(VSHLL_BS, vshllbs) | ||
| 169 | +DO_VSHLL(VSHLL_BU, vshllbu) | ||
| 170 | +DO_VSHLL(VSHLL_TS, vshllts) | ||
| 171 | +DO_VSHLL(VSHLL_TU, vshlltu) | ||
| 172 | -- | ||
| 173 | 2.20.1 | ||
| 174 | |||
| 175 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Implement the MVE VSRI and VSLI insns, which perform a | ||
| 2 | shift-and-insert operation. | ||
| 3 | 1 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20210628135835.6690-11-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/arm/helper-mve.h | 8 ++++++++ | ||
| 9 | target/arm/mve.decode | 9 ++++++++ | ||
| 10 | target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++ | ||
| 11 | target/arm/translate-mve.c | 3 +++ | ||
| 12 | 4 files changed, 62 insertions(+) | ||
| 13 | |||
| 14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/helper-mve.h | ||
| 17 | +++ b/target/arm/helper-mve.h | ||
| 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 19 | DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 20 | DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 21 | DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 22 | + | ||
| 23 | +DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 24 | +DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 25 | +DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 26 | + | ||
| 27 | +DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 28 | +DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 29 | +DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 30 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
| 31 | index XXXXXXX..XXXXXXX 100644 | ||
| 32 | --- a/target/arm/mve.decode | ||
| 33 | +++ b/target/arm/mve.decode | ||
| 34 | @@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h | ||
| 35 | |||
| 36 | VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b | ||
| 37 | VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h | ||
| 38 | + | ||
| 39 | +# Shift-and-insert | ||
| 40 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b | ||
| 41 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h | ||
| 42 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w | ||
| 43 | + | ||
| 44 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b | ||
| 45 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h | ||
| 46 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w | ||
| 47 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
| 48 | index XXXXXXX..XXXXXXX 100644 | ||
| 49 | --- a/target/arm/mve_helper.c | ||
| 50 | +++ b/target/arm/mve_helper.c | ||
| 51 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
| 52 | DO_2SHIFT_U(vrshli_u, DO_VRSHLU) | ||
| 53 | DO_2SHIFT_S(vrshli_s, DO_VRSHLS) | ||
| 54 | |||
| 55 | +/* Shift-and-insert; we always work with 64 bits at a time */ | ||
| 56 | +#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ | ||
| 57 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
| 58 | + void *vm, uint32_t shift) \ | ||
| 59 | + { \ | ||
| 60 | + uint64_t *d = vd, *m = vm; \ | ||
| 61 | + uint16_t mask; \ | ||
| 62 | + uint64_t shiftmask; \ | ||
| 63 | + unsigned e; \ | ||
| 64 | + if (shift == 0 || shift == ESIZE * 8) { \ | ||
| 65 | + /* \ | ||
| 66 | + * Only VSLI can shift by 0; only VSRI can shift by <dt>. \ | ||
| 67 | + * The generic logic would give the right answer for 0 but \ | ||
| 68 | + * fails for <dt>. \ | ||
| 69 | + */ \ | ||
| 70 | + goto done; \ | ||
| 71 | + } \ | ||
| 72 | + assert(shift < ESIZE * 8); \ | ||
| 73 | + mask = mve_element_mask(env); \ | ||
| 74 | + /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ | ||
| 75 | + shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ | ||
| 76 | + for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ | ||
| 77 | + uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ | ||
| 78 | + (d[H8(e)] & ~shiftmask); \ | ||
| 79 | + mergemask(&d[H8(e)], r, mask); \ | ||
| 80 | + } \ | ||
| 81 | +done: \ | ||
| 82 | + mve_advance_vpt(env); \ | ||
| 83 | + } | ||
| 84 | + | ||
| 85 | +#define DO_SHL(N, SHIFT) ((N) << (SHIFT)) | ||
| 86 | +#define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) | ||
| 87 | +#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) | ||
| 88 | +#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) | ||
| 89 | + | ||
| 90 | +DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) | ||
| 91 | +DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) | ||
| 92 | +DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) | ||
| 93 | +DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) | ||
| 94 | +DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) | ||
| 95 | +DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) | ||
| 96 | + | ||
| 97 | /* | ||
| 98 | * Long shifts taking half-sized inputs from top or bottom of the input | ||
| 99 | * vector and producing a double-width result. ESIZE, TYPE are for | ||
| 100 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
| 101 | index XXXXXXX..XXXXXXX 100644 | ||
| 102 | --- a/target/arm/translate-mve.c | ||
| 103 | +++ b/target/arm/translate-mve.c | ||
| 104 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true) | ||
| 105 | DO_2SHIFT(VRSHRI_S, vrshli_s, true) | ||
| 106 | DO_2SHIFT(VRSHRI_U, vrshli_u, true) | ||
| 107 | |||
| 108 | +DO_2SHIFT(VSRI, vsri, false) | ||
| 109 | +DO_2SHIFT(VSLI, vsli, false) | ||
| 110 | + | ||
| 111 | #define DO_VSHLL(INSN, FN) \ | ||
| 112 | static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | ||
| 113 | { \ | ||
| 114 | -- | ||
| 115 | 2.20.1 | ||
| 116 | |||
| 117 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN. | ||
| 2 | 1 | ||
| 3 | do_urshr() is borrowed from sve_helper.c. | ||
| 4 | |||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20210628135835.6690-12-peter.maydell@linaro.org | ||
| 8 | --- | ||
| 9 | target/arm/helper-mve.h | 10 ++++++++++ | ||
| 10 | target/arm/mve.decode | 11 +++++++++++ | ||
| 11 | target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++ | ||
| 12 | target/arm/translate-mve.c | 15 ++++++++++++++ | ||
| 13 | 4 files changed, 76 insertions(+) | ||
| 14 | |||
| 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/arm/helper-mve.h | ||
| 18 | +++ b/target/arm/helper-mve.h | ||
| 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 20 | DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 21 | DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 22 | DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 23 | + | ||
| 24 | +DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 25 | +DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 26 | +DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 27 | +DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 28 | + | ||
| 29 | +DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 30 | +DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 31 | +DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 32 | +DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
| 34 | index XXXXXXX..XXXXXXX 100644 | ||
| 35 | --- a/target/arm/mve.decode | ||
| 36 | +++ b/target/arm/mve.decode | ||
| 37 | @@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w | ||
| 38 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b | ||
| 39 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h | ||
| 40 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w | ||
| 41 | + | ||
| 42 | +# Narrowing shifts (which only support b and h sizes) | ||
| 43 | +VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b | ||
| 44 | +VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h | ||
| 45 | +VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b | ||
| 46 | +VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h | ||
| 47 | + | ||
| 48 | +VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b | ||
| 49 | +VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h | ||
| 50 | +VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b | ||
| 51 | +VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h | ||
| 52 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
| 53 | index XXXXXXX..XXXXXXX 100644 | ||
| 54 | --- a/target/arm/mve_helper.c | ||
| 55 | +++ b/target/arm/mve_helper.c | ||
| 56 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) | ||
| 57 | |||
| 58 | DO_VSHLL_ALL(vshllb, false) | ||
| 59 | DO_VSHLL_ALL(vshllt, true) | ||
| 60 | + | ||
| 61 | +/* | ||
| 62 | + * Narrowing right shifts, taking a double sized input, shifting it | ||
| 63 | + * and putting the result in either the top or bottom half of the output. | ||
| 64 | + * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. | ||
| 65 | + */ | ||
| 66 | +#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ | ||
| 67 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
| 68 | + void *vm, uint32_t shift) \ | ||
| 69 | + { \ | ||
| 70 | + LTYPE *m = vm; \ | ||
| 71 | + TYPE *d = vd; \ | ||
| 72 | + uint16_t mask = mve_element_mask(env); \ | ||
| 73 | + unsigned le; \ | ||
| 74 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | ||
| 75 | + TYPE r = FN(m[H##LESIZE(le)], shift); \ | ||
| 76 | + mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ | ||
| 77 | + } \ | ||
| 78 | + mve_advance_vpt(env); \ | ||
| 79 | + } | ||
| 80 | + | ||
| 81 | +#define DO_VSHRN_ALL(OP, FN) \ | ||
| 82 | + DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ | ||
| 83 | + DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ | ||
| 84 | + DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ | ||
| 85 | + DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) | ||
| 86 | + | ||
| 87 | +static inline uint64_t do_urshr(uint64_t x, unsigned sh) | ||
| 88 | +{ | ||
| 89 | + if (likely(sh < 64)) { | ||
| 90 | + return (x >> sh) + ((x >> (sh - 1)) & 1); | ||
| 91 | + } else if (sh == 64) { | ||
| 92 | + return x >> 63; | ||
| 93 | + } else { | ||
| 94 | + return 0; | ||
| 95 | + } | ||
| 96 | +} | ||
| 97 | + | ||
| 98 | +DO_VSHRN_ALL(vshrn, DO_SHR) | ||
| 99 | +DO_VSHRN_ALL(vrshrn, do_urshr) | ||
| 100 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
| 101 | index XXXXXXX..XXXXXXX 100644 | ||
| 102 | --- a/target/arm/translate-mve.c | ||
| 103 | +++ b/target/arm/translate-mve.c | ||
| 104 | @@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs) | ||
| 105 | DO_VSHLL(VSHLL_BU, vshllbu) | ||
| 106 | DO_VSHLL(VSHLL_TS, vshllts) | ||
| 107 | DO_VSHLL(VSHLL_TU, vshlltu) | ||
| 108 | + | ||
| 109 | +#define DO_2SHIFT_N(INSN, FN) \ | ||
| 110 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | ||
| 111 | + { \ | ||
| 112 | + static MVEGenTwoOpShiftFn * const fns[] = { \ | ||
| 113 | + gen_helper_mve_##FN##b, \ | ||
| 114 | + gen_helper_mve_##FN##h, \ | ||
| 115 | + }; \ | ||
| 116 | + return do_2shift(s, a, fns[a->size], false); \ | ||
| 117 | + } | ||
| 118 | + | ||
| 119 | +DO_2SHIFT_N(VSHRNB, vshrnb) | ||
| 120 | +DO_2SHIFT_N(VSHRNT, vshrnt) | ||
| 121 | +DO_2SHIFT_N(VRSHRNB, vrshrnb) | ||
| 122 | +DO_2SHIFT_N(VRSHRNT, vrshrnt) | ||
| 123 | -- | ||
| 124 | 2.20.1 | ||
| 125 | |||
| 126 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Implement the MVE VSHLC insn, which performs a shift left of the | ||
| 2 | entire vector with carry in bits provided from a general purpose | ||
| 3 | register and carry out bits written back to that register. | ||
| 4 | 1 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20210628135835.6690-14-peter.maydell@linaro.org | ||
| 8 | --- | ||
| 9 | target/arm/helper-mve.h | 2 ++ | ||
| 10 | target/arm/mve.decode | 2 ++ | ||
| 11 | target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++ | ||
| 12 | target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++ | ||
| 13 | 4 files changed, 72 insertions(+) | ||
| 14 | |||
| 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/arm/helper-mve.h | ||
| 18 | +++ b/target/arm/helper-mve.h | ||
| 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 20 | DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 21 | DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 22 | DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 23 | + | ||
| 24 | +DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) | ||
| 25 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/target/arm/mve.decode | ||
| 28 | +++ b/target/arm/mve.decode | ||
| 29 | @@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b | ||
| 30 | VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h | ||
| 31 | VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b | ||
| 32 | VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h | ||
| 33 | + | ||
| 34 | +VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd | ||
| 35 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
| 36 | index XXXXXXX..XXXXXXX 100644 | ||
| 37 | --- a/target/arm/mve_helper.c | ||
| 38 | +++ b/target/arm/mve_helper.c | ||
| 39 | @@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) | ||
| 40 | DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) | ||
| 41 | DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) | ||
| 42 | DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) | ||
| 43 | + | ||
| 44 | +uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, | ||
| 45 | + uint32_t shift) | ||
| 46 | +{ | ||
| 47 | + uint32_t *d = vd; | ||
| 48 | + uint16_t mask = mve_element_mask(env); | ||
| 49 | + unsigned e; | ||
| 50 | + uint32_t r; | ||
| 51 | + | ||
| 52 | + /* | ||
| 53 | + * For each 32-bit element, we shift it left, bringing in the | ||
| 54 | + * low 'shift' bits of rdm at the bottom. Bits shifted out at | ||
| 55 | + * the top become the new rdm, if the predicate mask permits. | ||
| 56 | + * The final rdm value is returned to update the register. | ||
| 57 | + * shift == 0 here means "shift by 32 bits". | ||
| 58 | + */ | ||
| 59 | + if (shift == 0) { | ||
| 60 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { | ||
| 61 | + r = rdm; | ||
| 62 | + if (mask & 1) { | ||
| 63 | + rdm = d[H4(e)]; | ||
| 64 | + } | ||
| 65 | + mergemask(&d[H4(e)], r, mask); | ||
| 66 | + } | ||
| 67 | + } else { | ||
| 68 | + uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); | ||
| 69 | + | ||
| 70 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { | ||
| 71 | + r = (d[H4(e)] << shift) | (rdm & shiftmask); | ||
| 72 | + if (mask & 1) { | ||
| 73 | + rdm = d[H4(e)] >> (32 - shift); | ||
| 74 | + } | ||
| 75 | + mergemask(&d[H4(e)], r, mask); | ||
| 76 | + } | ||
| 77 | + } | ||
| 78 | + mve_advance_vpt(env); | ||
| 79 | + return rdm; | ||
| 80 | +} | ||
| 81 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
| 82 | index XXXXXXX..XXXXXXX 100644 | ||
| 83 | --- a/target/arm/translate-mve.c | ||
| 84 | +++ b/target/arm/translate-mve.c | ||
| 85 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u) | ||
| 86 | DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u) | ||
| 87 | DO_2SHIFT_N(VQRSHRUNB, vqrshrunb) | ||
| 88 | DO_2SHIFT_N(VQRSHRUNT, vqrshrunt) | ||
| 89 | + | ||
| 90 | +static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a) | ||
| 91 | +{ | ||
| 92 | + /* | ||
| 93 | + * Whole Vector Left Shift with Carry. The carry is taken | ||
| 94 | + * from a general purpose register and written back there. | ||
| 95 | + * An imm of 0 means "shift by 32". | ||
| 96 | + */ | ||
| 97 | + TCGv_ptr qd; | ||
| 98 | + TCGv_i32 rdm; | ||
| 99 | + | ||
| 100 | + if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { | ||
| 101 | + return false; | ||
| 102 | + } | ||
| 103 | + if (a->rdm == 13 || a->rdm == 15) { | ||
| 104 | + /* CONSTRAINED UNPREDICTABLE: we UNDEF */ | ||
| 105 | + return false; | ||
| 106 | + } | ||
| 107 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
| 108 | + return true; | ||
| 109 | + } | ||
| 110 | + | ||
| 111 | + qd = mve_qreg_ptr(a->qd); | ||
| 112 | + rdm = load_reg(s, a->rdm); | ||
| 113 | + gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm)); | ||
| 114 | + store_reg(s, a->rdm, rdm); | ||
| 115 | + tcg_temp_free_ptr(qd); | ||
| 116 | + mve_update_eci(s); | ||
| 117 | + return true; | ||
| 118 | +} | ||
| 119 | -- | ||
| 120 | 2.20.1 | ||
| 121 | |||
| 122 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Implement the MVE VADDLV insn; this is similar to VADDV, except | ||
| 2 | that it accumulates 32-bit elements into a 64-bit accumulator | ||
| 3 | stored in a pair of general-purpose registers. | ||
| 4 | 1 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20210628135835.6690-15-peter.maydell@linaro.org | ||
| 8 | --- | ||
| 9 | target/arm/helper-mve.h | 3 ++ | ||
| 10 | target/arm/mve.decode | 6 +++- | ||
| 11 | target/arm/mve_helper.c | 19 ++++++++++++ | ||
| 12 | target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++ | ||
| 13 | 4 files changed, 90 insertions(+), 1 deletion(-) | ||
| 14 | |||
| 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/arm/helper-mve.h | ||
| 18 | +++ b/target/arm/helper-mve.h | ||
| 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
| 20 | DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
| 21 | DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
| 22 | |||
| 23 | +DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64) | ||
| 24 | +DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64) | ||
| 25 | + | ||
| 26 | DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
| 27 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
| 28 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
| 29 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
| 30 | index XXXXXXX..XXXXXXX 100644 | ||
| 31 | --- a/target/arm/mve.decode | ||
| 32 | +++ b/target/arm/mve.decode | ||
| 33 | @@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar | ||
| 34 | VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar | ||
| 35 | |||
| 36 | # Vector add across vector | ||
| 37 | -VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo | ||
| 38 | +{ | ||
| 39 | + VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo | ||
| 40 | + VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \ | ||
| 41 | + rdahi=%rdahi rdalo=%rdalo | ||
| 42 | +} | ||
| 43 | |||
| 44 | # Predicate operations | ||
| 45 | %mask_22_13 22:1 13:3 | ||
| 46 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
| 47 | index XXXXXXX..XXXXXXX 100644 | ||
| 48 | --- a/target/arm/mve_helper.c | ||
| 49 | +++ b/target/arm/mve_helper.c | ||
| 50 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t) | ||
| 51 | DO_VADDV(vaddvuh, 2, uint16_t) | ||
| 52 | DO_VADDV(vaddvuw, 4, uint32_t) | ||
| 53 | |||
| 54 | +#define DO_VADDLV(OP, TYPE, LTYPE) \ | ||
| 55 | + uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ | ||
| 56 | + uint64_t ra) \ | ||
| 57 | + { \ | ||
| 58 | + uint16_t mask = mve_element_mask(env); \ | ||
| 59 | + unsigned e; \ | ||
| 60 | + TYPE *m = vm; \ | ||
| 61 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ | ||
| 62 | + if (mask & 1) { \ | ||
| 63 | + ra += (LTYPE)m[H4(e)]; \ | ||
| 64 | + } \ | ||
| 65 | + } \ | ||
| 66 | + mve_advance_vpt(env); \ | ||
| 67 | + return ra; \ | ||
| 68 | + } \ | ||
| 69 | + | ||
| 70 | +DO_VADDLV(vaddlv_s, int32_t, int64_t) | ||
| 71 | +DO_VADDLV(vaddlv_u, uint32_t, uint64_t) | ||
| 72 | + | ||
| 73 | /* Shifts by immediate */ | ||
| 74 | #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ | ||
| 75 | void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
| 76 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
| 77 | index XXXXXXX..XXXXXXX 100644 | ||
| 78 | --- a/target/arm/translate-mve.c | ||
| 79 | +++ b/target/arm/translate-mve.c | ||
| 80 | @@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a) | ||
| 81 | return true; | ||
| 82 | } | ||
| 83 | |||
| 84 | +static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a) | ||
| 85 | +{ | ||
| 86 | + /* | ||
| 87 | + * Vector Add Long Across Vector: accumulate the 32-bit | ||
| 88 | + * elements of the vector into a 64-bit result stored in | ||
| 89 | + * a pair of general-purpose registers. | ||
| 90 | + * No need to check Qm's bank: it is only 3 bits in decode. | ||
| 91 | + */ | ||
| 92 | + TCGv_ptr qm; | ||
| 93 | + TCGv_i64 rda; | ||
| 94 | + TCGv_i32 rdalo, rdahi; | ||
| 95 | + | ||
| 96 | + if (!dc_isar_feature(aa32_mve, s)) { | ||
| 97 | + return false; | ||
| 98 | + } | ||
| 99 | + /* | ||
| 100 | + * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related | ||
| 101 | + * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. | ||
| 102 | + */ | ||
| 103 | + if (a->rdahi == 13 || a->rdahi == 15) { | ||
| 104 | + return false; | ||
| 105 | + } | ||
| 106 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
| 107 | + return true; | ||
| 108 | + } | ||
| 109 | + | ||
| 110 | + /* | ||
| 111 | + * This insn is subject to beat-wise execution. Partial execution | ||
| 112 | + * of an A=0 (no-accumulate) insn which does not execute the first | ||
| 113 | + * beat must start with the current value of RdaHi:RdaLo, not zero. | ||
| 114 | + */ | ||
| 115 | + if (a->a || mve_skip_first_beat(s)) { | ||
| 116 | + /* Accumulate input from RdaHi:RdaLo */ | ||
| 117 | + rda = tcg_temp_new_i64(); | ||
| 118 | + rdalo = load_reg(s, a->rdalo); | ||
| 119 | + rdahi = load_reg(s, a->rdahi); | ||
| 120 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); | ||
| 121 | + tcg_temp_free_i32(rdalo); | ||
| 122 | + tcg_temp_free_i32(rdahi); | ||
| 123 | + } else { | ||
| 124 | + /* Accumulate starting at zero */ | ||
| 125 | + rda = tcg_const_i64(0); | ||
| 126 | + } | ||
| 127 | + | ||
| 128 | + qm = mve_qreg_ptr(a->qm); | ||
| 129 | + if (a->u) { | ||
| 130 | + gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda); | ||
| 131 | + } else { | ||
| 132 | + gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda); | ||
| 133 | + } | ||
| 134 | + tcg_temp_free_ptr(qm); | ||
| 135 | + | ||
| 136 | + rdalo = tcg_temp_new_i32(); | ||
| 137 | + rdahi = tcg_temp_new_i32(); | ||
| 138 | + tcg_gen_extrl_i64_i32(rdalo, rda); | ||
| 139 | + tcg_gen_extrh_i64_i32(rdahi, rda); | ||
| 140 | + store_reg(s, a->rdalo, rdalo); | ||
| 141 | + store_reg(s, a->rdahi, rdahi); | ||
| 142 | + tcg_temp_free_i64(rda); | ||
| 143 | + mve_update_eci(s); | ||
| 144 | + return true; | ||
| 145 | +} | ||
| 146 | + | ||
| 147 | static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) | ||
| 148 | { | ||
| 149 | TCGv_ptr qd; | ||
| 150 | -- | ||
| 151 | 2.20.1 | ||
| 152 | |||
| 153 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | The MVE extension to v8.1M includes some new shift instructions which | ||
| 2 | sit entirely within the non-coprocessor part of the encoding space | ||
| 3 | and which operate only on general-purpose registers. They take up | ||
| 4 | the space which was previously UNPREDICTABLE MOVS and ORRS encodings | ||
| 5 | with Rm == 13 or 15. | ||
| 6 | 1 | ||
| 7 | Implement the long shifts by immediate, which perform shifts on a | ||
| 8 | pair of general-purpose registers treated as a 64-bit quantity, with | ||
| 9 | an immediate shift count between 1 and 32. | ||
| 10 | |||
| 11 | Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for | ||
| 12 | the Rm==13,15 case, we need to explicitly emit code to UNDEF for the | ||
| 13 | cases where v8.1M now requires that. (Trying to change MOVS and ORRS | ||
| 14 | is too difficult, because the functions that generate the code are | ||
| 15 | shared between a dozen different kinds of arithmetic or logical | ||
| 16 | instruction for all A32, T16 and T32 encodings, and for some insns | ||
| 17 | and some encodings Rm==13,15 are valid.) | ||
| 18 | |||
| 19 | We make the helper functions we need for UQSHLL and SQSHLL take | ||
| 20 | a 32-bit value which the helper casts to int8_t because we'll need | ||
| 21 | these helpers also for the shift-by-register insns, where the shift | ||
| 22 | count might be < 0 or > 32. | ||
| 23 | |||
| 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 25 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 26 | Message-id: 20210628135835.6690-16-peter.maydell@linaro.org | ||
| 27 | --- | ||
| 28 | target/arm/helper-mve.h | 3 ++ | ||
| 29 | target/arm/translate.h | 1 + | ||
| 30 | target/arm/t32.decode | 28 +++++++++++++ | ||
| 31 | target/arm/mve_helper.c | 10 +++++ | ||
| 32 | target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++ | ||
| 33 | 5 files changed, 132 insertions(+) | ||
| 34 | |||
| 35 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
| 36 | index XXXXXXX..XXXXXXX 100644 | ||
| 37 | --- a/target/arm/helper-mve.h | ||
| 38 | +++ b/target/arm/helper-mve.h | ||
| 39 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 40 | DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 41 | |||
| 42 | DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) | ||
| 43 | + | ||
| 44 | +DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
| 45 | +DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
| 46 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
| 47 | index XXXXXXX..XXXXXXX 100644 | ||
| 48 | --- a/target/arm/translate.h | ||
| 49 | +++ b/target/arm/translate.h | ||
| 50 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); | ||
| 51 | typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
| 52 | typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
| 53 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
| 54 | +typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | ||
| 55 | |||
| 56 | /** | ||
| 57 | * arm_tbflags_from_tb: | ||
| 58 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
| 59 | index XXXXXXX..XXXXXXX 100644 | ||
| 60 | --- a/target/arm/t32.decode | ||
| 61 | +++ b/target/arm/t32.decode | ||
| 62 | @@ -XXX,XX +XXX,XX @@ | ||
| 63 | &mcr !extern cp opc1 crn crm opc2 rt | ||
| 64 | &mcrr !extern cp opc1 crm rt rt2 | ||
| 65 | |||
| 66 | +&mve_shl_ri rdalo rdahi shim | ||
| 67 | + | ||
| 68 | +# rdahi: bits [3:1] from insn, bit 0 is 1 | ||
| 69 | +# rdalo: bits [3:1] from insn, bit 0 is 0 | ||
| 70 | +%rdahi_9 9:3 !function=times_2_plus_1 | ||
| 71 | +%rdalo_17 17:3 !function=times_2 | ||
| 72 | + | ||
| 73 | # Data-processing (register) | ||
| 74 | |||
| 75 | %imm5_12_6 12:3 6:2 | ||
| 76 | @@ -XXX,XX +XXX,XX @@ | ||
| 77 | @S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \ | ||
| 78 | &s_rrr_shi shim=%imm5_12_6 s=1 rd=0 | ||
| 79 | |||
| 80 | +@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \ | ||
| 81 | + &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
| 82 | + | ||
| 83 | { | ||
| 84 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | ||
| 85 | AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi | ||
| 86 | } | ||
| 87 | BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
| 88 | { | ||
| 89 | + # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS | ||
| 90 | + # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE | ||
| 91 | + # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that | ||
| 92 | + # they explicitly call unallocated_encoding() for cases that must UNDEF | ||
| 93 | + # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting | ||
| 94 | + # the rest fall through (where ORR_rrri and MOV_rxri will end up | ||
| 95 | + # handling them as r13 and r15 accesses with the same semantics as A32). | ||
| 96 | + [ | ||
| 97 | + LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
| 98 | + LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
| 99 | + ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
| 100 | + | ||
| 101 | + UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
| 102 | + URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
| 103 | + SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
| 104 | + SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
| 105 | + ] | ||
| 106 | + | ||
| 107 | MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi | ||
| 108 | ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi | ||
| 109 | } | ||
| 110 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
| 111 | index XXXXXXX..XXXXXXX 100644 | ||
| 112 | --- a/target/arm/mve_helper.c | ||
| 113 | +++ b/target/arm/mve_helper.c | ||
| 114 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, | ||
| 115 | mve_advance_vpt(env); | ||
| 116 | return rdm; | ||
| 117 | } | ||
| 118 | + | ||
| 119 | +uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
| 120 | +{ | ||
| 121 | + return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); | ||
| 122 | +} | ||
| 123 | + | ||
| 124 | +uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
| 125 | +{ | ||
| 126 | + return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); | ||
| 127 | +} | ||
| 128 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 129 | index XXXXXXX..XXXXXXX 100644 | ||
| 130 | --- a/target/arm/translate.c | ||
| 131 | +++ b/target/arm/translate.c | ||
| 132 | @@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a) | ||
| 133 | return true; | ||
| 134 | } | ||
| 135 | |||
| 136 | +/* | ||
| 137 | + * v8.1M MVE wide-shifts | ||
| 138 | + */ | ||
| 139 | +static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a, | ||
| 140 | + WideShiftImmFn *fn) | ||
| 141 | +{ | ||
| 142 | + TCGv_i64 rda; | ||
| 143 | + TCGv_i32 rdalo, rdahi; | ||
| 144 | + | ||
| 145 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
| 146 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | ||
| 147 | + return false; | ||
| 148 | + } | ||
| 149 | + if (a->rdahi == 15) { | ||
| 150 | + /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */ | ||
| 151 | + return false; | ||
| 152 | + } | ||
| 153 | + if (!dc_isar_feature(aa32_mve, s) || | ||
| 154 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | ||
| 155 | + a->rdahi == 13) { | ||
| 156 | + /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */ | ||
| 157 | + unallocated_encoding(s); | ||
| 158 | + return true; | ||
| 159 | + } | ||
| 160 | + | ||
| 161 | + if (a->shim == 0) { | ||
| 162 | + a->shim = 32; | ||
| 163 | + } | ||
| 164 | + | ||
| 165 | + rda = tcg_temp_new_i64(); | ||
| 166 | + rdalo = load_reg(s, a->rdalo); | ||
| 167 | + rdahi = load_reg(s, a->rdahi); | ||
| 168 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); | ||
| 169 | + | ||
| 170 | + fn(rda, rda, a->shim); | ||
| 171 | + | ||
| 172 | + tcg_gen_extrl_i64_i32(rdalo, rda); | ||
| 173 | + tcg_gen_extrh_i64_i32(rdahi, rda); | ||
| 174 | + store_reg(s, a->rdalo, rdalo); | ||
| 175 | + store_reg(s, a->rdahi, rdahi); | ||
| 176 | + tcg_temp_free_i64(rda); | ||
| 177 | + | ||
| 178 | + return true; | ||
| 179 | +} | ||
| 180 | + | ||
| 181 | +static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
| 182 | +{ | ||
| 183 | + return do_mve_shl_ri(s, a, tcg_gen_sari_i64); | ||
| 184 | +} | ||
| 185 | + | ||
| 186 | +static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
| 187 | +{ | ||
| 188 | + return do_mve_shl_ri(s, a, tcg_gen_shli_i64); | ||
| 189 | +} | ||
| 190 | + | ||
| 191 | +static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
| 192 | +{ | ||
| 193 | + return do_mve_shl_ri(s, a, tcg_gen_shri_i64); | ||
| 194 | +} | ||
| 195 | + | ||
| 196 | +static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) | ||
| 197 | +{ | ||
| 198 | + gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift)); | ||
| 199 | +} | ||
| 200 | + | ||
| 201 | +static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
| 202 | +{ | ||
| 203 | + return do_mve_shl_ri(s, a, gen_mve_sqshll); | ||
| 204 | +} | ||
| 205 | + | ||
| 206 | +static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) | ||
| 207 | +{ | ||
| 208 | + gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift)); | ||
| 209 | +} | ||
| 210 | + | ||
| 211 | +static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
| 212 | +{ | ||
| 213 | + return do_mve_shl_ri(s, a, gen_mve_uqshll); | ||
| 214 | +} | ||
| 215 | + | ||
| 216 | +static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
| 217 | +{ | ||
| 218 | + return do_mve_shl_ri(s, a, gen_srshr64_i64); | ||
| 219 | +} | ||
| 220 | + | ||
| 221 | +static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
| 222 | +{ | ||
| 223 | + return do_mve_shl_ri(s, a, gen_urshr64_i64); | ||
| 224 | +} | ||
| 225 | + | ||
| 226 | /* | ||
| 227 | * Multiply and multiply accumulate | ||
| 228 | */ | ||
| 229 | -- | ||
| 230 | 2.20.1 | ||
| 231 | |||
| 232 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Implement the MVE long shifts by register, which perform shifts on a | ||
| 2 | pair of general-purpose registers treated as a 64-bit quantity, with | ||
| 3 | the shift count in another general-purpose register, which might be | ||
| 4 | either positive or negative. | ||
| 5 | 1 | ||
| 6 | Like the long-shifts-by-immediate, these encodings sit in the space | ||
| 7 | that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15. | ||
| 8 | Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and | ||
| 9 | also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases), | ||
| 10 | we have to move the CSEL pattern into the same decodetree group. | ||
| 11 | |||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Message-id: 20210628135835.6690-17-peter.maydell@linaro.org | ||
| 15 | --- | ||
| 16 | target/arm/helper-mve.h | 6 +++ | ||
| 17 | target/arm/translate.h | 1 + | ||
| 18 | target/arm/t32.decode | 16 +++++-- | ||
| 19 | target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++ | ||
| 20 | target/arm/translate.c | 69 ++++++++++++++++++++++++++++++ | ||
| 21 | 5 files changed, 182 insertions(+), 3 deletions(-) | ||
| 22 | |||
| 23 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
| 24 | index XXXXXXX..XXXXXXX 100644 | ||
| 25 | --- a/target/arm/helper-mve.h | ||
| 26 | +++ b/target/arm/helper-mve.h | ||
| 27 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
| 28 | |||
| 29 | DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) | ||
| 30 | |||
| 31 | +DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
| 32 | +DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
| 33 | DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
| 34 | DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
| 35 | +DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
| 36 | +DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
| 37 | +DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
| 38 | +DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
| 39 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
| 40 | index XXXXXXX..XXXXXXX 100644 | ||
| 41 | --- a/target/arm/translate.h | ||
| 42 | +++ b/target/arm/translate.h | ||
| 43 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
| 44 | typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
| 45 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
| 46 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | ||
| 47 | +typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); | ||
| 48 | |||
| 49 | /** | ||
| 50 | * arm_tbflags_from_tb: | ||
| 51 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
| 52 | index XXXXXXX..XXXXXXX 100644 | ||
| 53 | --- a/target/arm/t32.decode | ||
| 54 | +++ b/target/arm/t32.decode | ||
| 55 | @@ -XXX,XX +XXX,XX @@ | ||
| 56 | &mcrr !extern cp opc1 crm rt rt2 | ||
| 57 | |||
| 58 | &mve_shl_ri rdalo rdahi shim | ||
| 59 | +&mve_shl_rr rdalo rdahi rm | ||
| 60 | |||
| 61 | # rdahi: bits [3:1] from insn, bit 0 is 1 | ||
| 62 | # rdalo: bits [3:1] from insn, bit 0 is 0 | ||
| 63 | @@ -XXX,XX +XXX,XX @@ | ||
| 64 | |||
| 65 | @mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \ | ||
| 66 | &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
| 67 | +@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \ | ||
| 68 | + &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
| 69 | |||
| 70 | { | ||
| 71 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | ||
| 72 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
| 73 | URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
| 74 | SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
| 75 | SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
| 76 | + | ||
| 77 | + LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | ||
| 78 | + ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | ||
| 79 | + UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr | ||
| 80 | + SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr | ||
| 81 | + UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr | ||
| 82 | + SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr | ||
| 83 | ] | ||
| 84 | |||
| 85 | MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi | ||
| 86 | ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi | ||
| 87 | + | ||
| 88 | + # v8.1M CSEL and friends | ||
| 89 | + CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4 | ||
| 90 | } | ||
| 91 | { | ||
| 92 | MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi | ||
| 93 | @@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi | ||
| 94 | } | ||
| 95 | RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi | ||
| 96 | |||
| 97 | -# v8.1M CSEL and friends | ||
| 98 | -CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4 | ||
| 99 | - | ||
| 100 | # Data-processing (register-shifted register) | ||
| 101 | |||
| 102 | MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ | ||
| 103 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
| 104 | index XXXXXXX..XXXXXXX 100644 | ||
| 105 | --- a/target/arm/mve_helper.c | ||
| 106 | +++ b/target/arm/mve_helper.c | ||
| 107 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, | ||
| 108 | return rdm; | ||
| 109 | } | ||
| 110 | |||
| 111 | +uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
| 112 | +{ | ||
| 113 | + return do_sqrshl_d(n, -(int8_t)shift, false, NULL); | ||
| 114 | +} | ||
| 115 | + | ||
| 116 | +uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
| 117 | +{ | ||
| 118 | + return do_uqrshl_d(n, (int8_t)shift, false, NULL); | ||
| 119 | +} | ||
| 120 | + | ||
| 121 | uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
| 122 | { | ||
| 123 | return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); | ||
| 124 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
| 125 | { | ||
| 126 | return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); | ||
| 127 | } | ||
| 128 | + | ||
| 129 | +uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
| 130 | +{ | ||
| 131 | + return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); | ||
| 132 | +} | ||
| 133 | + | ||
| 134 | +uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
| 135 | +{ | ||
| 136 | + return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); | ||
| 137 | +} | ||
| 138 | + | ||
| 139 | +/* Operate on 64-bit values, but saturate at 48 bits */ | ||
| 140 | +static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, | ||
| 141 | + bool round, uint32_t *sat) | ||
| 142 | +{ | ||
| 143 | + if (shift <= -48) { | ||
| 144 | + /* Rounding the sign bit always produces 0. */ | ||
| 145 | + if (round) { | ||
| 146 | + return 0; | ||
| 147 | + } | ||
| 148 | + return src >> 63; | ||
| 149 | + } else if (shift < 0) { | ||
| 150 | + if (round) { | ||
| 151 | + src >>= -shift - 1; | ||
| 152 | + return (src >> 1) + (src & 1); | ||
| 153 | + } | ||
| 154 | + return src >> -shift; | ||
| 155 | + } else if (shift < 48) { | ||
| 156 | + int64_t val = src << shift; | ||
| 157 | + int64_t extval = sextract64(val, 0, 48); | ||
| 158 | + if (!sat || val == extval) { | ||
| 159 | + return extval; | ||
| 160 | + } | ||
| 161 | + } else if (!sat || src == 0) { | ||
| 162 | + return 0; | ||
| 163 | + } | ||
| 164 | + | ||
| 165 | + *sat = 1; | ||
| 166 | + return (1ULL << 47) - (src >= 0); | ||
| 167 | +} | ||
| 168 | + | ||
| 169 | +/* Operate on 64-bit values, but saturate at 48 bits */ | ||
| 170 | +static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, | ||
| 171 | + bool round, uint32_t *sat) | ||
| 172 | +{ | ||
| 173 | + uint64_t val, extval; | ||
| 174 | + | ||
| 175 | + if (shift <= -(48 + round)) { | ||
| 176 | + return 0; | ||
| 177 | + } else if (shift < 0) { | ||
| 178 | + if (round) { | ||
| 179 | + val = src >> (-shift - 1); | ||
| 180 | + val = (val >> 1) + (val & 1); | ||
| 181 | + } else { | ||
| 182 | + val = src >> -shift; | ||
| 183 | + } | ||
| 184 | + extval = extract64(val, 0, 48); | ||
| 185 | + if (!sat || val == extval) { | ||
| 186 | + return extval; | ||
| 187 | + } | ||
| 188 | + } else if (shift < 48) { | ||
| 189 | + uint64_t val = src << shift; | ||
| 190 | + uint64_t extval = extract64(val, 0, 48); | ||
| 191 | + if (!sat || val == extval) { | ||
| 192 | + return extval; | ||
| 193 | + } | ||
| 194 | + } else if (!sat || src == 0) { | ||
| 195 | + return 0; | ||
| 196 | + } | ||
| 197 | + | ||
| 198 | + *sat = 1; | ||
| 199 | + return MAKE_64BIT_MASK(0, 48); | ||
| 200 | +} | ||
| 201 | + | ||
| 202 | +uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
| 203 | +{ | ||
| 204 | + return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); | ||
| 205 | +} | ||
| 206 | + | ||
| 207 | +uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
| 208 | +{ | ||
| 209 | + return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); | ||
| 210 | +} | ||
| 211 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 212 | index XXXXXXX..XXXXXXX 100644 | ||
| 213 | --- a/target/arm/translate.c | ||
| 214 | +++ b/target/arm/translate.c | ||
| 215 | @@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
| 216 | return do_mve_shl_ri(s, a, gen_urshr64_i64); | ||
| 217 | } | ||
| 218 | |||
| 219 | +static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn) | ||
| 220 | +{ | ||
| 221 | + TCGv_i64 rda; | ||
| 222 | + TCGv_i32 rdalo, rdahi; | ||
| 223 | + | ||
| 224 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
| 225 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | ||
| 226 | + return false; | ||
| 227 | + } | ||
| 228 | + if (a->rdahi == 15) { | ||
| 229 | + /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */ | ||
| 230 | + return false; | ||
| 231 | + } | ||
| 232 | + if (!dc_isar_feature(aa32_mve, s) || | ||
| 233 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | ||
| 234 | + a->rdahi == 13 || a->rm == 13 || a->rm == 15 || | ||
| 235 | + a->rm == a->rdahi || a->rm == a->rdalo) { | ||
| 236 | + /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */ | ||
| 237 | + unallocated_encoding(s); | ||
| 238 | + return true; | ||
| 239 | + } | ||
| 240 | + | ||
| 241 | + rda = tcg_temp_new_i64(); | ||
| 242 | + rdalo = load_reg(s, a->rdalo); | ||
| 243 | + rdahi = load_reg(s, a->rdahi); | ||
| 244 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); | ||
| 245 | + | ||
| 246 | + /* The helper takes care of the sign-extension of the low 8 bits of Rm */ | ||
| 247 | + fn(rda, cpu_env, rda, cpu_R[a->rm]); | ||
| 248 | + | ||
| 249 | + tcg_gen_extrl_i64_i32(rdalo, rda); | ||
| 250 | + tcg_gen_extrh_i64_i32(rdahi, rda); | ||
| 251 | + store_reg(s, a->rdalo, rdalo); | ||
| 252 | + store_reg(s, a->rdahi, rdahi); | ||
| 253 | + tcg_temp_free_i64(rda); | ||
| 254 | + | ||
| 255 | + return true; | ||
| 256 | +} | ||
| 257 | + | ||
| 258 | +static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
| 259 | +{ | ||
| 260 | + return do_mve_shl_rr(s, a, gen_helper_mve_ushll); | ||
| 261 | +} | ||
| 262 | + | ||
| 263 | +static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
| 264 | +{ | ||
| 265 | + return do_mve_shl_rr(s, a, gen_helper_mve_sshrl); | ||
| 266 | +} | ||
| 267 | + | ||
| 268 | +static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
| 269 | +{ | ||
| 270 | + return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll); | ||
| 271 | +} | ||
| 272 | + | ||
| 273 | +static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
| 274 | +{ | ||
| 275 | + return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl); | ||
| 276 | +} | ||
| 277 | + | ||
| 278 | +static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
| 279 | +{ | ||
| 280 | + return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48); | ||
| 281 | +} | ||
| 282 | + | ||
| 283 | +static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
| 284 | +{ | ||
| 285 | + return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48); | ||
| 286 | +} | ||
| 287 | + | ||
| 288 | /* | ||
| 289 | * Multiply and multiply accumulate | ||
| 290 | */ | ||
| 291 | -- | ||
| 292 | 2.20.1 | ||
| 293 | |||
| 294 | diff view generated by jsdifflib |