1 | The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df: | 1 | Nothing too exciting in this lot :-) |
---|---|---|---|
2 | 2 | ||
3 | Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100) | 3 | The following changes since commit ba0fa56bc06e563de68d2a2bf3ddb0cfea1be4f9: |
4 | |||
5 | Merge remote-tracking branch 'remotes/vivier/tags/q800-for-6.2-pull-request' into staging (2021-09-29 21:20:49 +0100) | ||
4 | 6 | ||
5 | are available in the Git repository at: | 7 | are available in the Git repository at: |
6 | 8 | ||
7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702 | 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210930 |
8 | 10 | ||
9 | for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8: | 11 | for you to fetch changes up to 1f4b2ec701b9d73d3fa7bb90c8b4376bc7d3c42b: |
10 | 12 | ||
11 | target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100) | 13 | hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19 (2021-09-30 13:44:13 +0100) |
12 | 14 | ||
13 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
14 | target-arm queue: | 16 | target-arm queue: |
15 | * more MVE instructions | 17 | * allwinner-h3: Switch to SMC as PSCI conduit |
16 | * hw/gpio/gpio_pwr: use shutdown function for reboot | 18 | * arm: tcg: Adhere to SMCCC 1.3 section 5.2 |
17 | * target/arm: Check NaN mode before silencing NaN | 19 | * xlnx-zcu102, xlnx-versal-virt: Support BBRAM and eFUSE devices |
18 | * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine | 20 | * gdbstub related code cleanups |
19 | * hw/arm: Add basic power management to raspi. | 21 | * Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML |
20 | * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc | 22 | * Use _init vs _new convention in bus creation function names |
23 | * sabrelite: Connect SPI flash CS line to GPIO3_19 | ||
21 | 24 | ||
22 | ---------------------------------------------------------------- | 25 | ---------------------------------------------------------------- |
23 | Joe Komlodi (1): | 26 | Alexander Graf (2): |
24 | target/arm: Check NaN mode before silencing NaN | 27 | allwinner-h3: Switch to SMC as PSCI conduit |
28 | arm: tcg: Adhere to SMCCC 1.3 section 5.2 | ||
25 | 29 | ||
26 | Maxim Uvarov (1): | 30 | Peter Maydell (10): |
27 | hw/gpio/gpio_pwr: use shutdown function for reboot | 31 | configs: Don't include 32-bit-only GDB XML in aarch64 linux configs |
32 | target/arm: Fix coding style issues in gdbstub code in helper.c | ||
33 | target/arm: Move gdbstub related code out of helper.c | ||
34 | target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML | ||
35 | scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named() | ||
36 | ipack: Rename ipack_bus_new_inplace() to ipack_bus_init() | ||
37 | pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init() | ||
38 | qbus: Rename qbus_create_inplace() to qbus_init() | ||
39 | qbus: Rename qbus_create() to qbus_new() | ||
40 | ide: Rename ide_bus_new() to ide_bus_init() | ||
28 | 41 | ||
29 | Nolan Leake (1): | 42 | Tong Ho (9): |
30 | hw/arm: Add basic power management to raspi. | 43 | hw/nvram: Introduce Xilinx eFuse QOM |
44 | hw/nvram: Introduce Xilinx Versal eFuse device | ||
45 | hw/nvram: Introduce Xilinx ZynqMP eFuse device | ||
46 | hw/nvram: Introduce Xilinx battery-backed ram | ||
47 | hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device | ||
48 | hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device | ||
49 | hw/arm: xlnx-zcu102: Add Xilinx BBRAM device | ||
50 | hw/arm: xlnx-zcu102: Add Xilinx eFUSE device | ||
51 | docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage | ||
31 | 52 | ||
32 | Patrick Venture (2): | 53 | Xuzhou Cheng (1): |
33 | docs/system/arm: Add quanta-q7l1-bmc reference | 54 | hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19 |
34 | docs/system/arm: Add quanta-gbs-bmc reference | ||
35 | 55 | ||
36 | Peter Maydell (18): | 56 | docs/system/arm/xlnx-versal-virt.rst | 49 ++ |
37 | target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation | 57 | configs/targets/aarch64-linux-user.mak | 2 +- |
38 | target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH | 58 | configs/targets/aarch64-softmmu.mak | 2 +- |
39 | target/arm: Make asimd_imm_const() public | 59 | configs/targets/aarch64_be-linux-user.mak | 2 +- |
40 | target/arm: Use asimd_imm_const for A64 decode | 60 | configs/targets/arm-linux-user.mak | 2 +- |
41 | target/arm: Use dup_const() instead of bitfield_replicate() | 61 | configs/targets/arm-softmmu.mak | 2 +- |
42 | target/arm: Implement MVE logical immediate insns | 62 | configs/targets/armeb-linux-user.mak | 2 +- |
43 | target/arm: Implement MVE vector shift left by immediate insns | 63 | include/hw/arm/xlnx-versal.h | 15 + |
44 | target/arm: Implement MVE vector shift right by immediate insns | 64 | include/hw/arm/xlnx-zynqmp.h | 5 + |
45 | target/arm: Implement MVE VSHLL | 65 | include/hw/ide/internal.h | 4 +- |
46 | target/arm: Implement MVE VSRI, VSLI | 66 | include/hw/ipack/ipack.h | 8 +- |
47 | target/arm: Implement MVE VSHRN, VRSHRN | 67 | include/hw/nvram/xlnx-bbram.h | 54 ++ |
48 | target/arm: Implement MVE saturating narrowing shifts | 68 | include/hw/nvram/xlnx-efuse.h | 132 +++++ |
49 | target/arm: Implement MVE VSHLC | 69 | include/hw/nvram/xlnx-versal-efuse.h | 68 +++ |
50 | target/arm: Implement MVE VADDLV | 70 | include/hw/nvram/xlnx-zynqmp-efuse.h | 44 ++ |
51 | target/arm: Implement MVE long shifts by immediate | 71 | include/hw/pci/pci.h | 10 +- |
52 | target/arm: Implement MVE long shifts by register | 72 | include/hw/qdev-core.h | 6 +- |
53 | target/arm: Implement MVE shifts by immediate | 73 | include/hw/scsi/scsi.h | 30 +- |
54 | target/arm: Implement MVE shifts by register | 74 | target/arm/internals.h | 7 + |
75 | hw/arm/allwinner-h3.c | 2 +- | ||
76 | hw/arm/sabrelite.c | 2 +- | ||
77 | hw/arm/xlnx-versal-virt.c | 88 +++ | ||
78 | hw/arm/xlnx-versal.c | 57 ++ | ||
79 | hw/arm/xlnx-zcu102.c | 30 ++ | ||
80 | hw/arm/xlnx-zynqmp.c | 49 ++ | ||
81 | hw/audio/intel-hda.c | 2 +- | ||
82 | hw/block/fdc.c | 2 +- | ||
83 | hw/block/swim.c | 3 +- | ||
84 | hw/char/virtio-serial-bus.c | 4 +- | ||
85 | hw/core/bus.c | 13 +- | ||
86 | hw/core/sysbus.c | 10 +- | ||
87 | hw/gpio/bcm2835_gpio.c | 3 +- | ||
88 | hw/hyperv/vmbus.c | 2 +- | ||
89 | hw/i2c/core.c | 2 +- | ||
90 | hw/ide/ahci.c | 2 +- | ||
91 | hw/ide/cmd646.c | 2 +- | ||
92 | hw/ide/isa.c | 2 +- | ||
93 | hw/ide/macio.c | 2 +- | ||
94 | hw/ide/microdrive.c | 2 +- | ||
95 | hw/ide/mmio.c | 2 +- | ||
96 | hw/ide/piix.c | 2 +- | ||
97 | hw/ide/qdev.c | 4 +- | ||
98 | hw/ide/sii3112.c | 2 +- | ||
99 | hw/ide/via.c | 2 +- | ||
100 | hw/ipack/ipack.c | 10 +- | ||
101 | hw/ipack/tpci200.c | 4 +- | ||
102 | hw/isa/isa-bus.c | 2 +- | ||
103 | hw/misc/auxbus.c | 2 +- | ||
104 | hw/misc/mac_via.c | 4 +- | ||
105 | hw/misc/macio/cuda.c | 4 +- | ||
106 | hw/misc/macio/macio.c | 4 +- | ||
107 | hw/misc/macio/pmu.c | 4 +- | ||
108 | hw/nubus/nubus-bridge.c | 2 +- | ||
109 | hw/nvme/ctrl.c | 4 +- | ||
110 | hw/nvme/subsys.c | 3 +- | ||
111 | hw/nvram/xlnx-bbram.c | 545 +++++++++++++++++++ | ||
112 | hw/nvram/xlnx-efuse-crc.c | 119 +++++ | ||
113 | hw/nvram/xlnx-efuse.c | 280 ++++++++++ | ||
114 | hw/nvram/xlnx-versal-efuse-cache.c | 114 ++++ | ||
115 | hw/nvram/xlnx-versal-efuse-ctrl.c | 783 +++++++++++++++++++++++++++ | ||
116 | hw/nvram/xlnx-zynqmp-efuse.c | 855 ++++++++++++++++++++++++++++++ | ||
117 | hw/pci-host/raven.c | 4 +- | ||
118 | hw/pci-host/versatile.c | 6 +- | ||
119 | hw/pci/pci.c | 30 +- | ||
120 | hw/pci/pci_bridge.c | 4 +- | ||
121 | hw/ppc/spapr_vio.c | 2 +- | ||
122 | hw/s390x/ap-bridge.c | 2 +- | ||
123 | hw/s390x/css-bridge.c | 2 +- | ||
124 | hw/s390x/event-facility.c | 4 +- | ||
125 | hw/s390x/s390-pci-bus.c | 2 +- | ||
126 | hw/s390x/virtio-ccw.c | 3 +- | ||
127 | hw/scsi/esp-pci.c | 2 +- | ||
128 | hw/scsi/esp.c | 2 +- | ||
129 | hw/scsi/lsi53c895a.c | 2 +- | ||
130 | hw/scsi/megasas.c | 3 +- | ||
131 | hw/scsi/mptsas.c | 2 +- | ||
132 | hw/scsi/scsi-bus.c | 6 +- | ||
133 | hw/scsi/spapr_vscsi.c | 3 +- | ||
134 | hw/scsi/virtio-scsi.c | 4 +- | ||
135 | hw/scsi/vmw_pvscsi.c | 3 +- | ||
136 | hw/sd/allwinner-sdhost.c | 4 +- | ||
137 | hw/sd/bcm2835_sdhost.c | 4 +- | ||
138 | hw/sd/pl181.c | 3 +- | ||
139 | hw/sd/pxa2xx_mmci.c | 4 +- | ||
140 | hw/sd/sdhci.c | 3 +- | ||
141 | hw/sd/ssi-sd.c | 3 +- | ||
142 | hw/ssi/ssi.c | 2 +- | ||
143 | hw/usb/bus.c | 2 +- | ||
144 | hw/usb/dev-smartcard-reader.c | 3 +- | ||
145 | hw/usb/dev-storage-bot.c | 3 +- | ||
146 | hw/usb/dev-storage-classic.c | 4 +- | ||
147 | hw/usb/dev-uas.c | 3 +- | ||
148 | hw/virtio/virtio-mmio.c | 3 +- | ||
149 | hw/virtio/virtio-pci.c | 3 +- | ||
150 | hw/xen/xen-bus.c | 2 +- | ||
151 | hw/xen/xen-legacy-backend.c | 2 +- | ||
152 | target/arm/gdbstub.c | 154 ++++++ | ||
153 | target/arm/gdbstub64.c | 140 +++++ | ||
154 | target/arm/helper.c | 262 --------- | ||
155 | target/arm/psci.c | 35 +- | ||
156 | gdb-xml/arm-neon.xml | 2 - | ||
157 | gdb-xml/arm-vfp-sysregs.xml | 17 + | ||
158 | gdb-xml/arm-vfp.xml | 2 - | ||
159 | gdb-xml/arm-vfp3.xml | 2 - | ||
160 | hw/Kconfig | 2 + | ||
161 | hw/arm/Kconfig | 2 + | ||
162 | hw/nvram/Kconfig | 19 + | ||
163 | hw/nvram/meson.build | 8 + | ||
164 | 108 files changed, 3806 insertions(+), 447 deletions(-) | ||
165 | create mode 100644 include/hw/nvram/xlnx-bbram.h | ||
166 | create mode 100644 include/hw/nvram/xlnx-efuse.h | ||
167 | create mode 100644 include/hw/nvram/xlnx-versal-efuse.h | ||
168 | create mode 100644 include/hw/nvram/xlnx-zynqmp-efuse.h | ||
169 | create mode 100644 hw/nvram/xlnx-bbram.c | ||
170 | create mode 100644 hw/nvram/xlnx-efuse-crc.c | ||
171 | create mode 100644 hw/nvram/xlnx-efuse.c | ||
172 | create mode 100644 hw/nvram/xlnx-versal-efuse-cache.c | ||
173 | create mode 100644 hw/nvram/xlnx-versal-efuse-ctrl.c | ||
174 | create mode 100644 hw/nvram/xlnx-zynqmp-efuse.c | ||
175 | create mode 100644 gdb-xml/arm-vfp-sysregs.xml | ||
55 | 176 | ||
56 | Philippe Mathieu-Daudé (1): | ||
57 | tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine | ||
58 | |||
59 | docs/system/arm/aspeed.rst | 1 + | ||
60 | docs/system/arm/nuvoton.rst | 5 +- | ||
61 | include/hw/arm/bcm2835_peripherals.h | 3 +- | ||
62 | include/hw/misc/bcm2835_powermgt.h | 29 ++ | ||
63 | target/arm/helper-mve.h | 108 +++++++ | ||
64 | target/arm/translate.h | 41 +++ | ||
65 | target/arm/mve.decode | 177 ++++++++++- | ||
66 | target/arm/t32.decode | 71 ++++- | ||
67 | hw/arm/bcm2835_peripherals.c | 13 +- | ||
68 | hw/gpio/gpio_pwr.c | 2 +- | ||
69 | hw/misc/bcm2835_powermgt.c | 160 ++++++++++ | ||
70 | target/arm/helper-a64.c | 12 +- | ||
71 | target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++-- | ||
72 | target/arm/translate-a64.c | 86 +----- | ||
73 | target/arm/translate-mve.c | 261 +++++++++++++++- | ||
74 | target/arm/translate-neon.c | 81 ----- | ||
75 | target/arm/translate.c | 327 +++++++++++++++++++- | ||
76 | target/arm/vfp_helper.c | 24 +- | ||
77 | hw/misc/meson.build | 1 + | ||
78 | tests/acceptance/boot_linux_console.py | 43 +++ | ||
79 | 20 files changed, 1760 insertions(+), 209 deletions(-) | ||
80 | create mode 100644 include/hw/misc/bcm2835_powermgt.h | ||
81 | create mode 100644 hw/misc/bcm2835_powermgt.c | ||
82 | diff view generated by jsdifflib |
1 | Implement the MVE shifts by immediate, which perform shifts | 1 | From: Alexander Graf <agraf@csgraf.de> |
---|---|---|---|
2 | on a single general-purpose register. | ||
3 | 2 | ||
4 | These patterns overlap with the long-shift-by-immediates, | 3 | The Allwinner H3 SoC uses Cortex-A7 cores which support virtualization. |
5 | so we have to rearrange the grouping a little here. | 4 | However, today we are configuring QEMU to use HVC as PSCI conduit. |
6 | 5 | ||
6 | That means HVC calls get trapped into QEMU instead of the guest's own | ||
7 | emulated CPU and thus break the guest's ability to execute virtualization. | ||
8 | |||
9 | Fix this by moving to SMC as conduit, freeing up HYP completely to the VM. | ||
10 | |||
11 | Signed-off-by: Alexander Graf <agraf@csgraf.de> | ||
12 | Message-id: 20210920203931.66527-1-agraf@csgraf.de | ||
13 | Fixes: 740dafc0ba0 ("hw/arm: add Allwinner H3 System-on-Chip") | ||
14 | Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
15 | Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20210628135835.6690-18-peter.maydell@linaro.org | ||
10 | --- | 19 | --- |
11 | target/arm/helper-mve.h | 3 ++ | 20 | hw/arm/allwinner-h3.c | 2 +- |
12 | target/arm/translate.h | 1 + | 21 | 1 file changed, 1 insertion(+), 1 deletion(-) |
13 | target/arm/t32.decode | 31 ++++++++++++++----- | ||
14 | target/arm/mve_helper.c | 10 ++++++ | ||
15 | target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++-- | ||
16 | 5 files changed, 104 insertions(+), 9 deletions(-) | ||
17 | 22 | ||
18 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | 23 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c |
19 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/helper-mve.h | 25 | --- a/hw/arm/allwinner-h3.c |
21 | +++ b/target/arm/helper-mve.h | 26 | +++ b/hw/arm/allwinner-h3.c |
22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) | 27 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) |
23 | DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | 28 | |
24 | DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32) | 29 | /* Provide Power State Coordination Interface */ |
25 | DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) | 30 | qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit", |
26 | + | 31 | - QEMU_PSCI_CONDUIT_HVC); |
27 | +DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | 32 | + QEMU_PSCI_CONDUIT_SMC); |
28 | +DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | 33 | |
29 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 34 | /* Disable secondary CPUs */ |
30 | index XXXXXXX..XXXXXXX 100644 | 35 | qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off", |
31 | --- a/target/arm/translate.h | ||
32 | +++ b/target/arm/translate.h | ||
33 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
34 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
35 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | ||
36 | typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); | ||
37 | +typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); | ||
38 | |||
39 | /** | ||
40 | * arm_tbflags_from_tb: | ||
41 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/t32.decode | ||
44 | +++ b/target/arm/t32.decode | ||
45 | @@ -XXX,XX +XXX,XX @@ | ||
46 | |||
47 | &mve_shl_ri rdalo rdahi shim | ||
48 | &mve_shl_rr rdalo rdahi rm | ||
49 | +&mve_sh_ri rda shim | ||
50 | |||
51 | # rdahi: bits [3:1] from insn, bit 0 is 1 | ||
52 | # rdalo: bits [3:1] from insn, bit 0 is 0 | ||
53 | @@ -XXX,XX +XXX,XX @@ | ||
54 | &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
55 | @mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \ | ||
56 | &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
57 | +@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \ | ||
58 | + &mve_sh_ri shim=%imm5_12_6 | ||
59 | |||
60 | { | ||
61 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | ||
62 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
63 | # the rest fall through (where ORR_rrri and MOV_rxri will end up | ||
64 | # handling them as r13 and r15 accesses with the same semantics as A32). | ||
65 | [ | ||
66 | - LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
67 | - LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
68 | - ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
69 | + { | ||
70 | + UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri | ||
71 | + LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
72 | + UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
73 | + } | ||
74 | |||
75 | - UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
76 | - URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
77 | - SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
78 | - SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
79 | + { | ||
80 | + URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri | ||
81 | + LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
82 | + URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
83 | + } | ||
84 | + | ||
85 | + { | ||
86 | + SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri | ||
87 | + ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
88 | + SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
89 | + } | ||
90 | + | ||
91 | + { | ||
92 | + SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri | ||
93 | + SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
94 | + } | ||
95 | |||
96 | LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | ||
97 | ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | ||
98 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
99 | index XXXXXXX..XXXXXXX 100644 | ||
100 | --- a/target/arm/mve_helper.c | ||
101 | +++ b/target/arm/mve_helper.c | ||
102 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
103 | { | ||
104 | return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); | ||
105 | } | ||
106 | + | ||
107 | +uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
108 | +{ | ||
109 | + return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); | ||
110 | +} | ||
111 | + | ||
112 | +uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
113 | +{ | ||
114 | + return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); | ||
115 | +} | ||
116 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
117 | index XXXXXXX..XXXXXXX 100644 | ||
118 | --- a/target/arm/translate.c | ||
119 | +++ b/target/arm/translate.c | ||
120 | @@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) | ||
121 | |||
122 | static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh) | ||
123 | { | ||
124 | - TCGv_i32 t = tcg_temp_new_i32(); | ||
125 | + TCGv_i32 t; | ||
126 | |||
127 | + /* Handle shift by the input size for the benefit of trans_SRSHR_ri */ | ||
128 | + if (sh == 32) { | ||
129 | + tcg_gen_movi_i32(d, 0); | ||
130 | + return; | ||
131 | + } | ||
132 | + t = tcg_temp_new_i32(); | ||
133 | tcg_gen_extract_i32(t, a, sh - 1, 1); | ||
134 | tcg_gen_sari_i32(d, a, sh); | ||
135 | tcg_gen_add_i32(d, d, t); | ||
136 | @@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) | ||
137 | |||
138 | static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh) | ||
139 | { | ||
140 | - TCGv_i32 t = tcg_temp_new_i32(); | ||
141 | + TCGv_i32 t; | ||
142 | |||
143 | + /* Handle shift by the input size for the benefit of trans_URSHR_ri */ | ||
144 | + if (sh == 32) { | ||
145 | + tcg_gen_extract_i32(d, a, sh - 1, 1); | ||
146 | + return; | ||
147 | + } | ||
148 | + t = tcg_temp_new_i32(); | ||
149 | tcg_gen_extract_i32(t, a, sh - 1, 1); | ||
150 | tcg_gen_shri_i32(d, a, sh); | ||
151 | tcg_gen_add_i32(d, d, t); | ||
152 | @@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
153 | return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48); | ||
154 | } | ||
155 | |||
156 | +static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn) | ||
157 | +{ | ||
158 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
159 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | ||
160 | + return false; | ||
161 | + } | ||
162 | + if (!dc_isar_feature(aa32_mve, s) || | ||
163 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | ||
164 | + a->rda == 13 || a->rda == 15) { | ||
165 | + /* These rda cases are UNPREDICTABLE; we choose to UNDEF */ | ||
166 | + unallocated_encoding(s); | ||
167 | + return true; | ||
168 | + } | ||
169 | + | ||
170 | + if (a->shim == 0) { | ||
171 | + a->shim = 32; | ||
172 | + } | ||
173 | + fn(cpu_R[a->rda], cpu_R[a->rda], a->shim); | ||
174 | + | ||
175 | + return true; | ||
176 | +} | ||
177 | + | ||
178 | +static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
179 | +{ | ||
180 | + return do_mve_sh_ri(s, a, gen_urshr32_i32); | ||
181 | +} | ||
182 | + | ||
183 | +static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
184 | +{ | ||
185 | + return do_mve_sh_ri(s, a, gen_srshr32_i32); | ||
186 | +} | ||
187 | + | ||
188 | +static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) | ||
189 | +{ | ||
190 | + gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift)); | ||
191 | +} | ||
192 | + | ||
193 | +static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
194 | +{ | ||
195 | + return do_mve_sh_ri(s, a, gen_mve_sqshl); | ||
196 | +} | ||
197 | + | ||
198 | +static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) | ||
199 | +{ | ||
200 | + gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift)); | ||
201 | +} | ||
202 | + | ||
203 | +static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
204 | +{ | ||
205 | + return do_mve_sh_ri(s, a, gen_mve_uqshl); | ||
206 | +} | ||
207 | + | ||
208 | /* | ||
209 | * Multiply and multiply accumulate | ||
210 | */ | ||
211 | -- | 36 | -- |
212 | 2.20.1 | 37 | 2.20.1 |
213 | 38 | ||
214 | 39 | diff view generated by jsdifflib |
1 | The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH | 1 | From: Alexander Graf <agraf@csgraf.de> |
---|---|---|---|
2 | insns had some bugs: | ||
3 | * the 32x32 multiply of elements was being done as 32x32->32, | ||
4 | not 32x32->64 | ||
5 | * we were incorrectly maintaining the accumulator in its full | ||
6 | 72-bit form across all 4 beats of the insn; in the pseudocode | ||
7 | it is squashed back into the 64 bits of the RdaHi:RdaLo | ||
8 | registers after each beat | ||
9 | 2 | ||
10 | In particular, fixing the second of these allows us to recast | 3 | The SMCCC 1.3 spec section 5.2 says |
11 | the implementation to avoid 128-bit arithmetic entirely. | ||
12 | 4 | ||
13 | Since the element size here is always 4, we can also drop the | 5 | The Unknown SMC Function Identifier is a sign-extended value of (-1) |
14 | parameterization of ESIZE to make the code a little more readable. | 6 | that is returned in the R0, W0 or X0 registers. An implementation must |
7 | return this error code when it receives: | ||
15 | 8 | ||
16 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | 9 | * An SMC or HVC call with an unknown Function Identifier |
10 | * An SMC or HVC call for a removed Function Identifier | ||
11 | * An SMC64/HVC64 call from AArch32 state | ||
12 | |||
13 | To comply with these statements, let's always return -1 when we encounter | ||
14 | an unknown HVC or SMC call. | ||
15 | |||
16 | Signed-off-by: Alexander Graf <agraf@csgraf.de> | ||
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
19 | Message-id: 20210628135835.6690-3-peter.maydell@linaro.org | ||
20 | --- | 19 | --- |
21 | target/arm/mve_helper.c | 38 +++++++++++++++++++++----------------- | 20 | target/arm/psci.c | 35 ++++++----------------------------- |
22 | 1 file changed, 21 insertions(+), 17 deletions(-) | 21 | 1 file changed, 6 insertions(+), 29 deletions(-) |
23 | 22 | ||
24 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | 23 | diff --git a/target/arm/psci.c b/target/arm/psci.c |
25 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/mve_helper.c | 25 | --- a/target/arm/psci.c |
27 | +++ b/target/arm/mve_helper.c | 26 | +++ b/target/arm/psci.c |
28 | @@ -XXX,XX +XXX,XX @@ | 27 | @@ -XXX,XX +XXX,XX @@ |
29 | */ | 28 | |
30 | 29 | bool arm_is_psci_call(ARMCPU *cpu, int excp_type) | |
31 | #include "qemu/osdep.h" | 30 | { |
32 | -#include "qemu/int128.h" | 31 | - /* Return true if the r0/x0 value indicates a PSCI call and |
33 | #include "cpu.h" | 32 | - * the exception type matches the configured PSCI conduit. This is |
34 | #include "internals.h" | 33 | - * called before the SMC/HVC instruction is executed, to decide whether |
35 | #include "vec_internal.h" | 34 | - * we should treat it as a PSCI call or with the architecturally |
36 | @@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) | 35 | + /* |
37 | DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) | 36 | + * Return true if the exception type matches the configured PSCI conduit. |
38 | 37 | + * This is called before the SMC/HVC instruction is executed, to decide | |
39 | /* | 38 | + * whether we should treat it as a PSCI call or with the architecturally |
40 | - * Rounding multiply add long dual accumulate high: we must keep | 39 | * defined behaviour for an SMC or HVC (which might be UNDEF or trap |
41 | - * a 72-bit internal accumulator value and return the top 64 bits. | 40 | * to EL2 or to EL3). |
42 | + * Rounding multiply add long dual accumulate high. In the pseudocode | 41 | */ |
43 | + * this is implemented with a 72-bit internal accumulator value of which | 42 | - CPUARMState *env = &cpu->env; |
44 | + * the top 64 bits are returned. We optimize this to avoid having to | 43 | - uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0]; |
45 | + * use 128-bit arithmetic -- we can do this because the 74-bit accumulator | 44 | |
46 | + * is squashed back into 64-bits after each beat. | 45 | switch (excp_type) { |
47 | */ | 46 | case EXCP_HVC: |
48 | -#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \ | 47 | @@ -XXX,XX +XXX,XX @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type) |
49 | +#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ | 48 | return false; |
50 | uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ | ||
51 | void *vm, uint64_t a) \ | ||
52 | { \ | ||
53 | uint16_t mask = mve_element_mask(env); \ | ||
54 | unsigned e; \ | ||
55 | TYPE *n = vn, *m = vm; \ | ||
56 | - Int128 acc = int128_lshift(TO128(a), 8); \ | ||
57 | - for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
58 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ | ||
59 | if (mask & 1) { \ | ||
60 | + LTYPE mul; \ | ||
61 | if (e & 1) { \ | ||
62 | - acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \ | ||
63 | - m[H##ESIZE(e)])); \ | ||
64 | + mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ | ||
65 | + if (SUB) { \ | ||
66 | + mul = -mul; \ | ||
67 | + } \ | ||
68 | } else { \ | ||
69 | - acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \ | ||
70 | - m[H##ESIZE(e)])); \ | ||
71 | + mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ | ||
72 | } \ | ||
73 | - acc = int128_add(acc, int128_make64(1 << 7)); \ | ||
74 | + mul = (mul >> 8) + ((mul >> 7) & 1); \ | ||
75 | + a += mul; \ | ||
76 | } \ | ||
77 | } \ | ||
78 | mve_advance_vpt(env); \ | ||
79 | - return int128_getlo(int128_rshift(acc, 8)); \ | ||
80 | + return a; \ | ||
81 | } | 49 | } |
82 | 50 | ||
83 | -DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64) | 51 | - switch (param) { |
84 | -DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64) | 52 | - case QEMU_PSCI_0_2_FN_PSCI_VERSION: |
85 | +DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) | 53 | - case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: |
86 | +DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) | 54 | - case QEMU_PSCI_0_2_FN_AFFINITY_INFO: |
87 | 55 | - case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: | |
88 | -DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64) | 56 | - case QEMU_PSCI_0_2_FN_SYSTEM_RESET: |
89 | +DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) | 57 | - case QEMU_PSCI_0_2_FN_SYSTEM_OFF: |
90 | 58 | - case QEMU_PSCI_0_1_FN_CPU_ON: | |
91 | -DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64) | 59 | - case QEMU_PSCI_0_2_FN_CPU_ON: |
92 | -DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64) | 60 | - case QEMU_PSCI_0_2_FN64_CPU_ON: |
93 | +DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) | 61 | - case QEMU_PSCI_0_1_FN_CPU_OFF: |
94 | +DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) | 62 | - case QEMU_PSCI_0_2_FN_CPU_OFF: |
95 | 63 | - case QEMU_PSCI_0_1_FN_CPU_SUSPEND: | |
96 | /* Vector add across vector */ | 64 | - case QEMU_PSCI_0_2_FN_CPU_SUSPEND: |
97 | #define DO_VADDV(OP, ESIZE, TYPE) \ | 65 | - case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: |
66 | - case QEMU_PSCI_0_1_FN_MIGRATE: | ||
67 | - case QEMU_PSCI_0_2_FN_MIGRATE: | ||
68 | - return true; | ||
69 | - default: | ||
70 | - return false; | ||
71 | - } | ||
72 | + return true; | ||
73 | } | ||
74 | |||
75 | void arm_handle_psci_call(ARMCPU *cpu) | ||
76 | @@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu) | ||
77 | break; | ||
78 | case QEMU_PSCI_0_1_FN_MIGRATE: | ||
79 | case QEMU_PSCI_0_2_FN_MIGRATE: | ||
80 | + default: | ||
81 | ret = QEMU_PSCI_RET_NOT_SUPPORTED; | ||
82 | break; | ||
83 | - default: | ||
84 | - g_assert_not_reached(); | ||
85 | } | ||
86 | |||
87 | err: | ||
98 | -- | 88 | -- |
99 | 2.20.1 | 89 | 2.20.1 |
100 | 90 | ||
101 | 91 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Tong Ho <tong.ho@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | Add a test booting and quickly shutdown a raspi2 machine, | 3 | This introduces the QOM for Xilinx eFuse, an one-time |
4 | to test the power management model: | 4 | field-programmable storage bit array. |
5 | 5 | ||
6 | (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd: | 6 | The actual mmio interface to the array varies by device |
7 | console: [ 0.000000] Booting Linux on physical CPU 0xf00 | 7 | families and will be provided in different change-sets. |
8 | console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019 | ||
9 | console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d | ||
10 | console: [ 0.000000] CPU: div instructions available: patching division code | ||
11 | console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache | ||
12 | console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B | ||
13 | ... | ||
14 | console: Boot successful. | ||
15 | console: cat /proc/cpuinfo | ||
16 | console: / # cat /proc/cpuinfo | ||
17 | ... | ||
18 | console: processor : 3 | ||
19 | console: model name : ARMv7 Processor rev 5 (v7l) | ||
20 | console: BogoMIPS : 125.00 | ||
21 | console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm | ||
22 | console: CPU implementer : 0x41 | ||
23 | console: CPU architecture: 7 | ||
24 | console: CPU variant : 0x0 | ||
25 | console: CPU part : 0xc07 | ||
26 | console: CPU revision : 5 | ||
27 | console: Hardware : BCM2835 | ||
28 | console: Revision : 0000 | ||
29 | console: Serial : 0000000000000000 | ||
30 | console: cat /proc/iomem | ||
31 | console: / # cat /proc/iomem | ||
32 | console: 00000000-3bffffff : System RAM | ||
33 | console: 00008000-00afffff : Kernel code | ||
34 | console: 00c00000-00d468ef : Kernel data | ||
35 | console: 3f006000-3f006fff : dwc_otg | ||
36 | console: 3f007000-3f007eff : /soc/dma@7e007000 | ||
37 | console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880 | ||
38 | console: 3f100000-3f100027 : /soc/watchdog@7e100000 | ||
39 | console: 3f101000-3f102fff : /soc/cprman@7e101000 | ||
40 | console: 3f200000-3f2000b3 : /soc/gpio@7e200000 | ||
41 | PASS (24.59 s) | ||
42 | RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 | ||
43 | JOB TIME : 25.02 s | ||
44 | 8 | ||
45 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 9 | Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
46 | Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> | 10 | Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> |
47 | Message-id: 20210531113837.1689775-1-f4bug@amsat.org | 11 | |
12 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
13 | Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | ||
14 | Signed-off-by: Tong Ho <tong.ho@xilinx.com> | ||
15 | Message-id: 20210917052400.1249094-2-tong.ho@xilinx.com | ||
16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
48 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
49 | --- | 18 | --- |
50 | tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++ | 19 | include/hw/nvram/xlnx-efuse.h | 132 ++++++++++++++++ |
51 | 1 file changed, 43 insertions(+) | 20 | hw/nvram/xlnx-efuse-crc.c | 119 +++++++++++++++ |
21 | hw/nvram/xlnx-efuse.c | 280 ++++++++++++++++++++++++++++++++++ | ||
22 | hw/nvram/Kconfig | 7 + | ||
23 | hw/nvram/meson.build | 2 + | ||
24 | 5 files changed, 540 insertions(+) | ||
25 | create mode 100644 include/hw/nvram/xlnx-efuse.h | ||
26 | create mode 100644 hw/nvram/xlnx-efuse-crc.c | ||
27 | create mode 100644 hw/nvram/xlnx-efuse.c | ||
52 | 28 | ||
53 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py | 29 | diff --git a/include/hw/nvram/xlnx-efuse.h b/include/hw/nvram/xlnx-efuse.h |
30 | new file mode 100644 | ||
31 | index XXXXXXX..XXXXXXX | ||
32 | --- /dev/null | ||
33 | +++ b/include/hw/nvram/xlnx-efuse.h | ||
34 | @@ -XXX,XX +XXX,XX @@ | ||
35 | +/* | ||
36 | + * QEMU model of the Xilinx eFuse core | ||
37 | + * | ||
38 | + * Copyright (c) 2015 Xilinx Inc. | ||
39 | + * | ||
40 | + * Written by Edgar E. Iglesias <edgari@xilinx.com> | ||
41 | + * | ||
42 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
43 | + * of this software and associated documentation files (the "Software"), to deal | ||
44 | + * in the Software without restriction, including without limitation the rights | ||
45 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
46 | + * copies of the Software, and to permit persons to whom the Software is | ||
47 | + * furnished to do so, subject to the following conditions: | ||
48 | + * | ||
49 | + * The above copyright notice and this permission notice shall be included in | ||
50 | + * all copies or substantial portions of the Software. | ||
51 | + * | ||
52 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
53 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
54 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
55 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
56 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
57 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
58 | + * THE SOFTWARE. | ||
59 | + */ | ||
60 | + | ||
61 | +#ifndef XLNX_EFUSE_H | ||
62 | +#define XLNX_EFUSE_H | ||
63 | + | ||
64 | +#include "sysemu/block-backend.h" | ||
65 | +#include "hw/qdev-core.h" | ||
66 | + | ||
67 | +#define TYPE_XLNX_EFUSE "xlnx,efuse" | ||
68 | +OBJECT_DECLARE_SIMPLE_TYPE(XlnxEFuse, XLNX_EFUSE); | ||
69 | + | ||
70 | +struct XlnxEFuse { | ||
71 | + DeviceState parent_obj; | ||
72 | + BlockBackend *blk; | ||
73 | + bool blk_ro; | ||
74 | + uint32_t *fuse32; | ||
75 | + | ||
76 | + DeviceState *dev; | ||
77 | + | ||
78 | + bool init_tbits; | ||
79 | + | ||
80 | + uint8_t efuse_nr; | ||
81 | + uint32_t efuse_size; | ||
82 | + | ||
83 | + uint32_t *ro_bits; | ||
84 | + uint32_t ro_bits_cnt; | ||
85 | +}; | ||
86 | + | ||
87 | +/** | ||
88 | + * xlnx_efuse_calc_crc: | ||
89 | + * @data: an array of 32-bit words for which the CRC should be computed | ||
90 | + * @u32_cnt: the array size in number of 32-bit words | ||
91 | + * @zpads: the number of 32-bit zeros prepended to @data before computation | ||
92 | + * | ||
93 | + * This function is used to compute the CRC for an array of 32-bit words, | ||
94 | + * using a Xilinx-specific data padding. | ||
95 | + * | ||
96 | + * Returns: the computed 32-bit CRC | ||
97 | + */ | ||
98 | +uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt, | ||
99 | + unsigned zpads); | ||
100 | + | ||
101 | +/** | ||
102 | + * xlnx_efuse_get_bit: | ||
103 | + * @s: the efuse object | ||
104 | + * @bit: the efuse bit-address to read the data | ||
105 | + * | ||
106 | + * Returns: the bit, 0 or 1, at @bit of object @s | ||
107 | + */ | ||
108 | +bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit); | ||
109 | + | ||
110 | +/** | ||
111 | + * xlnx_efuse_set_bit: | ||
112 | + * @s: the efuse object | ||
113 | + * @bit: the efuse bit-address to be written a value of 1 | ||
114 | + * | ||
115 | + * Returns: true on success, false on failure | ||
116 | + */ | ||
117 | +bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit); | ||
118 | + | ||
119 | +/** | ||
120 | + * xlnx_efuse_k256_check: | ||
121 | + * @s: the efuse object | ||
122 | + * @crc: the 32-bit CRC to be compared with | ||
123 | + * @start: the efuse bit-address (which must be multiple of 32) of the | ||
124 | + * start of a 256-bit array | ||
125 | + * | ||
126 | + * This function computes the CRC of a 256-bit array starting at @start | ||
127 | + * then compares to the given @crc | ||
128 | + * | ||
129 | + * Returns: true of @crc == computed, false otherwise | ||
130 | + */ | ||
131 | +bool xlnx_efuse_k256_check(XlnxEFuse *s, uint32_t crc, unsigned start); | ||
132 | + | ||
133 | +/** | ||
134 | + * xlnx_efuse_tbits_check: | ||
135 | + * @s: the efuse object | ||
136 | + * | ||
137 | + * This function inspects a number of efuse bits at specific addresses | ||
138 | + * to see if they match a validation pattern. Each pattern is a group | ||
139 | + * of 4 bits, and there are 3 groups. | ||
140 | + * | ||
141 | + * Returns: a 3-bit mask, where a bit of '1' means the corresponding | ||
142 | + * group has a valid pattern. | ||
143 | + */ | ||
144 | +uint32_t xlnx_efuse_tbits_check(XlnxEFuse *s); | ||
145 | + | ||
146 | +/** | ||
147 | + * xlnx_efuse_get_row: | ||
148 | + * @s: the efuse object | ||
149 | + * @bit: the efuse bit address for which a 32-bit value is read | ||
150 | + * | ||
151 | + * Returns: the entire 32 bits of the efuse, starting at a bit | ||
152 | + * address that is multiple of 32 and contains the bit at @bit | ||
153 | + */ | ||
154 | +static inline uint32_t xlnx_efuse_get_row(XlnxEFuse *s, unsigned int bit) | ||
155 | +{ | ||
156 | + if (!(s->fuse32)) { | ||
157 | + return 0; | ||
158 | + } else { | ||
159 | + unsigned int row_idx = bit / 32; | ||
160 | + | ||
161 | + assert(row_idx < (s->efuse_size * s->efuse_nr / 32)); | ||
162 | + return s->fuse32[row_idx]; | ||
163 | + } | ||
164 | +} | ||
165 | + | ||
166 | +#endif | ||
167 | diff --git a/hw/nvram/xlnx-efuse-crc.c b/hw/nvram/xlnx-efuse-crc.c | ||
168 | new file mode 100644 | ||
169 | index XXXXXXX..XXXXXXX | ||
170 | --- /dev/null | ||
171 | +++ b/hw/nvram/xlnx-efuse-crc.c | ||
172 | @@ -XXX,XX +XXX,XX @@ | ||
173 | +/* | ||
174 | + * Xilinx eFuse/bbram CRC calculator | ||
175 | + * | ||
176 | + * Copyright (c) 2021 Xilinx Inc. | ||
177 | + * | ||
178 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
179 | + * of this software and associated documentation files (the "Software"), to deal | ||
180 | + * in the Software without restriction, including without limitation the rights | ||
181 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
182 | + * copies of the Software, and to permit persons to whom the Software is | ||
183 | + * furnished to do so, subject to the following conditions: | ||
184 | + * | ||
185 | + * The above copyright notice and this permission notice shall be included in | ||
186 | + * all copies or substantial portions of the Software. | ||
187 | + * | ||
188 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
189 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
190 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
191 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
192 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
193 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
194 | + * THE SOFTWARE. | ||
195 | + */ | ||
196 | +#include "qemu/osdep.h" | ||
197 | +#include "hw/nvram/xlnx-efuse.h" | ||
198 | + | ||
199 | +static uint32_t xlnx_efuse_u37_crc(uint32_t prev_crc, uint32_t data, | ||
200 | + uint32_t addr) | ||
201 | +{ | ||
202 | + /* A table for 7-bit slicing */ | ||
203 | + static const uint32_t crc_tab[128] = { | ||
204 | + 0x00000000, 0xe13b70f7, 0xc79a971f, 0x26a1e7e8, | ||
205 | + 0x8ad958cf, 0x6be22838, 0x4d43cfd0, 0xac78bf27, | ||
206 | + 0x105ec76f, 0xf165b798, 0xd7c45070, 0x36ff2087, | ||
207 | + 0x9a879fa0, 0x7bbcef57, 0x5d1d08bf, 0xbc267848, | ||
208 | + 0x20bd8ede, 0xc186fe29, 0xe72719c1, 0x061c6936, | ||
209 | + 0xaa64d611, 0x4b5fa6e6, 0x6dfe410e, 0x8cc531f9, | ||
210 | + 0x30e349b1, 0xd1d83946, 0xf779deae, 0x1642ae59, | ||
211 | + 0xba3a117e, 0x5b016189, 0x7da08661, 0x9c9bf696, | ||
212 | + 0x417b1dbc, 0xa0406d4b, 0x86e18aa3, 0x67dafa54, | ||
213 | + 0xcba24573, 0x2a993584, 0x0c38d26c, 0xed03a29b, | ||
214 | + 0x5125dad3, 0xb01eaa24, 0x96bf4dcc, 0x77843d3b, | ||
215 | + 0xdbfc821c, 0x3ac7f2eb, 0x1c661503, 0xfd5d65f4, | ||
216 | + 0x61c69362, 0x80fde395, 0xa65c047d, 0x4767748a, | ||
217 | + 0xeb1fcbad, 0x0a24bb5a, 0x2c855cb2, 0xcdbe2c45, | ||
218 | + 0x7198540d, 0x90a324fa, 0xb602c312, 0x5739b3e5, | ||
219 | + 0xfb410cc2, 0x1a7a7c35, 0x3cdb9bdd, 0xdde0eb2a, | ||
220 | + 0x82f63b78, 0x63cd4b8f, 0x456cac67, 0xa457dc90, | ||
221 | + 0x082f63b7, 0xe9141340, 0xcfb5f4a8, 0x2e8e845f, | ||
222 | + 0x92a8fc17, 0x73938ce0, 0x55326b08, 0xb4091bff, | ||
223 | + 0x1871a4d8, 0xf94ad42f, 0xdfeb33c7, 0x3ed04330, | ||
224 | + 0xa24bb5a6, 0x4370c551, 0x65d122b9, 0x84ea524e, | ||
225 | + 0x2892ed69, 0xc9a99d9e, 0xef087a76, 0x0e330a81, | ||
226 | + 0xb21572c9, 0x532e023e, 0x758fe5d6, 0x94b49521, | ||
227 | + 0x38cc2a06, 0xd9f75af1, 0xff56bd19, 0x1e6dcdee, | ||
228 | + 0xc38d26c4, 0x22b65633, 0x0417b1db, 0xe52cc12c, | ||
229 | + 0x49547e0b, 0xa86f0efc, 0x8ecee914, 0x6ff599e3, | ||
230 | + 0xd3d3e1ab, 0x32e8915c, 0x144976b4, 0xf5720643, | ||
231 | + 0x590ab964, 0xb831c993, 0x9e902e7b, 0x7fab5e8c, | ||
232 | + 0xe330a81a, 0x020bd8ed, 0x24aa3f05, 0xc5914ff2, | ||
233 | + 0x69e9f0d5, 0x88d28022, 0xae7367ca, 0x4f48173d, | ||
234 | + 0xf36e6f75, 0x12551f82, 0x34f4f86a, 0xd5cf889d, | ||
235 | + 0x79b737ba, 0x988c474d, 0xbe2da0a5, 0x5f16d052 | ||
236 | + }; | ||
237 | + | ||
238 | + /* | ||
239 | + * eFuse calculation is shown here: | ||
240 | + * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1496 | ||
241 | + * | ||
242 | + * Each u32 word is appended a 5-bit value, for a total of 37 bits; see: | ||
243 | + * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_utils.c#L1356 | ||
244 | + */ | ||
245 | + uint32_t crc = prev_crc; | ||
246 | + const unsigned rshf = 7; | ||
247 | + const uint32_t im = (1 << rshf) - 1; | ||
248 | + const uint32_t rm = (1 << (32 - rshf)) - 1; | ||
249 | + const uint32_t i2 = (1 << 2) - 1; | ||
250 | + const uint32_t r2 = (1 << 30) - 1; | ||
251 | + | ||
252 | + unsigned j; | ||
253 | + uint32_t i, r; | ||
254 | + uint64_t w; | ||
255 | + | ||
256 | + w = (uint64_t)(addr) << 32; | ||
257 | + w |= data; | ||
258 | + | ||
259 | + /* Feed 35 bits, in 5 rounds, each a slice of 7 bits */ | ||
260 | + for (j = 0; j < 5; j++) { | ||
261 | + r = rm & (crc >> rshf); | ||
262 | + i = im & (crc ^ w); | ||
263 | + crc = crc_tab[i] ^ r; | ||
264 | + | ||
265 | + w >>= rshf; | ||
266 | + } | ||
267 | + | ||
268 | + /* Feed the remaining 2 bits */ | ||
269 | + r = r2 & (crc >> 2); | ||
270 | + i = i2 & (crc ^ w); | ||
271 | + crc = crc_tab[i << (rshf - 2)] ^ r; | ||
272 | + | ||
273 | + return crc; | ||
274 | +} | ||
275 | + | ||
276 | +uint32_t xlnx_efuse_calc_crc(const uint32_t *data, unsigned u32_cnt, | ||
277 | + unsigned zpads) | ||
278 | +{ | ||
279 | + uint32_t crc = 0; | ||
280 | + unsigned index; | ||
281 | + | ||
282 | + for (index = zpads; index; index--) { | ||
283 | + crc = xlnx_efuse_u37_crc(crc, 0, (index + u32_cnt)); | ||
284 | + } | ||
285 | + | ||
286 | + for (index = u32_cnt; index; index--) { | ||
287 | + crc = xlnx_efuse_u37_crc(crc, data[index - 1], index); | ||
288 | + } | ||
289 | + | ||
290 | + return crc; | ||
291 | +} | ||
292 | diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c | ||
293 | new file mode 100644 | ||
294 | index XXXXXXX..XXXXXXX | ||
295 | --- /dev/null | ||
296 | +++ b/hw/nvram/xlnx-efuse.c | ||
297 | @@ -XXX,XX +XXX,XX @@ | ||
298 | +/* | ||
299 | + * QEMU model of the EFUSE eFuse | ||
300 | + * | ||
301 | + * Copyright (c) 2015 Xilinx Inc. | ||
302 | + * | ||
303 | + * Written by Edgar E. Iglesias <edgari@xilinx.com> | ||
304 | + * | ||
305 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
306 | + * of this software and associated documentation files (the "Software"), to deal | ||
307 | + * in the Software without restriction, including without limitation the rights | ||
308 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
309 | + * copies of the Software, and to permit persons to whom the Software is | ||
310 | + * furnished to do so, subject to the following conditions: | ||
311 | + * | ||
312 | + * The above copyright notice and this permission notice shall be included in | ||
313 | + * all copies or substantial portions of the Software. | ||
314 | + * | ||
315 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
316 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
317 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
318 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
319 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
320 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
321 | + * THE SOFTWARE. | ||
322 | + */ | ||
323 | + | ||
324 | +#include "qemu/osdep.h" | ||
325 | +#include "hw/nvram/xlnx-efuse.h" | ||
326 | + | ||
327 | +#include "qemu/error-report.h" | ||
328 | +#include "qemu/log.h" | ||
329 | +#include "qapi/error.h" | ||
330 | +#include "sysemu/blockdev.h" | ||
331 | +#include "hw/qdev-properties.h" | ||
332 | +#include "hw/qdev-properties-system.h" | ||
333 | + | ||
334 | +#define TBIT0_OFFSET 28 | ||
335 | +#define TBIT1_OFFSET 29 | ||
336 | +#define TBIT2_OFFSET 30 | ||
337 | +#define TBIT3_OFFSET 31 | ||
338 | +#define TBITS_PATTERN (0x0AU << TBIT0_OFFSET) | ||
339 | +#define TBITS_MASK (0x0FU << TBIT0_OFFSET) | ||
340 | + | ||
341 | +bool xlnx_efuse_get_bit(XlnxEFuse *s, unsigned int bit) | ||
342 | +{ | ||
343 | + bool b = s->fuse32[bit / 32] & (1 << (bit % 32)); | ||
344 | + return b; | ||
345 | +} | ||
346 | + | ||
347 | +static int efuse_bytes(XlnxEFuse *s) | ||
348 | +{ | ||
349 | + return ROUND_UP((s->efuse_nr * s->efuse_size) / 8, 4); | ||
350 | +} | ||
351 | + | ||
352 | +static int efuse_bdrv_read(XlnxEFuse *s, Error **errp) | ||
353 | +{ | ||
354 | + uint32_t *ram = s->fuse32; | ||
355 | + int nr = efuse_bytes(s); | ||
356 | + | ||
357 | + if (!s->blk) { | ||
358 | + return 0; | ||
359 | + } | ||
360 | + | ||
361 | + s->blk_ro = !blk_supports_write_perm(s->blk); | ||
362 | + if (!s->blk_ro) { | ||
363 | + int rc; | ||
364 | + | ||
365 | + rc = blk_set_perm(s->blk, | ||
366 | + (BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE), | ||
367 | + BLK_PERM_ALL, NULL); | ||
368 | + if (rc) { | ||
369 | + s->blk_ro = true; | ||
370 | + } | ||
371 | + } | ||
372 | + if (s->blk_ro) { | ||
373 | + warn_report("%s: Skip saving updates to read-only eFUSE backstore.", | ||
374 | + blk_name(s->blk)); | ||
375 | + } | ||
376 | + | ||
377 | + if (blk_pread(s->blk, 0, ram, nr) < 0) { | ||
378 | + error_setg(errp, "%s: Failed to read %u bytes from eFUSE backstore.", | ||
379 | + blk_name(s->blk), nr); | ||
380 | + return -1; | ||
381 | + } | ||
382 | + | ||
383 | + /* Convert from little-endian backstore for each 32-bit row */ | ||
384 | + nr /= 4; | ||
385 | + while (nr--) { | ||
386 | + ram[nr] = le32_to_cpu(ram[nr]); | ||
387 | + } | ||
388 | + | ||
389 | + return 0; | ||
390 | +} | ||
391 | + | ||
392 | +static void efuse_bdrv_sync(XlnxEFuse *s, unsigned int bit) | ||
393 | +{ | ||
394 | + unsigned int row_offset; | ||
395 | + uint32_t le32; | ||
396 | + | ||
397 | + if (!s->blk || s->blk_ro) { | ||
398 | + return; /* Silent on read-only backend to avoid message flood */ | ||
399 | + } | ||
400 | + | ||
401 | + /* Backstore is always in little-endian */ | ||
402 | + le32 = cpu_to_le32(xlnx_efuse_get_row(s, bit)); | ||
403 | + | ||
404 | + row_offset = (bit / 32) * 4; | ||
405 | + if (blk_pwrite(s->blk, row_offset, &le32, 4, 0) < 0) { | ||
406 | + error_report("%s: Failed to write offset %u of eFUSE backstore.", | ||
407 | + blk_name(s->blk), row_offset); | ||
408 | + } | ||
409 | +} | ||
410 | + | ||
411 | +static int efuse_ro_bits_cmp(const void *a, const void *b) | ||
412 | +{ | ||
413 | + uint32_t i = *(const uint32_t *)a; | ||
414 | + uint32_t j = *(const uint32_t *)b; | ||
415 | + | ||
416 | + return (i > j) - (i < j); | ||
417 | +} | ||
418 | + | ||
419 | +static void efuse_ro_bits_sort(XlnxEFuse *s) | ||
420 | +{ | ||
421 | + uint32_t *ary = s->ro_bits; | ||
422 | + const uint32_t cnt = s->ro_bits_cnt; | ||
423 | + | ||
424 | + if (ary && cnt > 1) { | ||
425 | + qsort(ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp); | ||
426 | + } | ||
427 | +} | ||
428 | + | ||
429 | +static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k) | ||
430 | +{ | ||
431 | + const uint32_t *ary = s->ro_bits; | ||
432 | + const uint32_t cnt = s->ro_bits_cnt; | ||
433 | + | ||
434 | + if (!ary || !cnt) { | ||
435 | + return false; | ||
436 | + } | ||
437 | + | ||
438 | + return bsearch(&k, ary, cnt, sizeof(ary[0]), efuse_ro_bits_cmp) != NULL; | ||
439 | +} | ||
440 | + | ||
441 | +bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit) | ||
442 | +{ | ||
443 | + if (efuse_ro_bits_find(s, bit)) { | ||
444 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: WARN: " | ||
445 | + "Ignored setting of readonly efuse bit<%u,%u>!\n", | ||
446 | + object_get_canonical_path(OBJECT(s)), | ||
447 | + (bit / 32), (bit % 32)); | ||
448 | + return false; | ||
449 | + } | ||
450 | + | ||
451 | + s->fuse32[bit / 32] |= 1 << (bit % 32); | ||
452 | + efuse_bdrv_sync(s, bit); | ||
453 | + return true; | ||
454 | +} | ||
455 | + | ||
456 | +bool xlnx_efuse_k256_check(XlnxEFuse *s, uint32_t crc, unsigned start) | ||
457 | +{ | ||
458 | + uint32_t calc; | ||
459 | + | ||
460 | + /* A key always occupies multiple of whole rows */ | ||
461 | + assert((start % 32) == 0); | ||
462 | + | ||
463 | + calc = xlnx_efuse_calc_crc(&s->fuse32[start / 32], (256 / 32), 0); | ||
464 | + return calc == crc; | ||
465 | +} | ||
466 | + | ||
467 | +uint32_t xlnx_efuse_tbits_check(XlnxEFuse *s) | ||
468 | +{ | ||
469 | + int nr; | ||
470 | + uint32_t check = 0; | ||
471 | + | ||
472 | + for (nr = s->efuse_nr; nr-- > 0; ) { | ||
473 | + int efuse_start_row_num = (s->efuse_size * nr) / 32; | ||
474 | + uint32_t data = s->fuse32[efuse_start_row_num]; | ||
475 | + | ||
476 | + /* | ||
477 | + * If the option is on, auto-init blank T-bits. | ||
478 | + * (non-blank will still be reported as '0' in the check, e.g., | ||
479 | + * for error-injection tests) | ||
480 | + */ | ||
481 | + if ((data & TBITS_MASK) == 0 && s->init_tbits) { | ||
482 | + data |= TBITS_PATTERN; | ||
483 | + | ||
484 | + s->fuse32[efuse_start_row_num] = data; | ||
485 | + efuse_bdrv_sync(s, (efuse_start_row_num * 32 + TBIT0_OFFSET)); | ||
486 | + } | ||
487 | + | ||
488 | + check = (check << 1) | ((data & TBITS_MASK) == TBITS_PATTERN); | ||
489 | + } | ||
490 | + | ||
491 | + return check; | ||
492 | +} | ||
493 | + | ||
494 | +static void efuse_realize(DeviceState *dev, Error **errp) | ||
495 | +{ | ||
496 | + XlnxEFuse *s = XLNX_EFUSE(dev); | ||
497 | + | ||
498 | + /* Sort readonly-list for bsearch lookup */ | ||
499 | + efuse_ro_bits_sort(s); | ||
500 | + | ||
501 | + if ((s->efuse_size % 32) != 0) { | ||
502 | + error_setg(errp, | ||
503 | + "%s.efuse-size: %u: property value not multiple of 32.", | ||
504 | + object_get_canonical_path(OBJECT(dev)), s->efuse_size); | ||
505 | + return; | ||
506 | + } | ||
507 | + | ||
508 | + s->fuse32 = g_malloc0(efuse_bytes(s)); | ||
509 | + if (efuse_bdrv_read(s, errp)) { | ||
510 | + g_free(s->fuse32); | ||
511 | + } | ||
512 | +} | ||
513 | + | ||
514 | +static void efuse_prop_set_drive(Object *obj, Visitor *v, const char *name, | ||
515 | + void *opaque, Error **errp) | ||
516 | +{ | ||
517 | + DeviceState *dev = DEVICE(obj); | ||
518 | + | ||
519 | + qdev_prop_drive.set(obj, v, name, opaque, errp); | ||
520 | + | ||
521 | + /* Fill initial data if backend is attached after realized */ | ||
522 | + if (dev->realized) { | ||
523 | + efuse_bdrv_read(XLNX_EFUSE(obj), errp); | ||
524 | + } | ||
525 | +} | ||
526 | + | ||
527 | +static void efuse_prop_get_drive(Object *obj, Visitor *v, const char *name, | ||
528 | + void *opaque, Error **errp) | ||
529 | +{ | ||
530 | + qdev_prop_drive.get(obj, v, name, opaque, errp); | ||
531 | +} | ||
532 | + | ||
533 | +static void efuse_prop_release_drive(Object *obj, const char *name, | ||
534 | + void *opaque) | ||
535 | +{ | ||
536 | + qdev_prop_drive.release(obj, name, opaque); | ||
537 | +} | ||
538 | + | ||
539 | +static const PropertyInfo efuse_prop_drive = { | ||
540 | + .name = "str", | ||
541 | + .description = "Node name or ID of a block device to use as eFUSE backend", | ||
542 | + .realized_set_allowed = true, | ||
543 | + .get = efuse_prop_get_drive, | ||
544 | + .set = efuse_prop_set_drive, | ||
545 | + .release = efuse_prop_release_drive, | ||
546 | +}; | ||
547 | + | ||
548 | +static Property efuse_properties[] = { | ||
549 | + DEFINE_PROP("drive", XlnxEFuse, blk, efuse_prop_drive, BlockBackend *), | ||
550 | + DEFINE_PROP_UINT8("efuse-nr", XlnxEFuse, efuse_nr, 3), | ||
551 | + DEFINE_PROP_UINT32("efuse-size", XlnxEFuse, efuse_size, 64 * 32), | ||
552 | + DEFINE_PROP_BOOL("init-factory-tbits", XlnxEFuse, init_tbits, true), | ||
553 | + DEFINE_PROP_ARRAY("read-only", XlnxEFuse, ro_bits_cnt, ro_bits, | ||
554 | + qdev_prop_uint32, uint32_t), | ||
555 | + DEFINE_PROP_END_OF_LIST(), | ||
556 | +}; | ||
557 | + | ||
558 | +static void efuse_class_init(ObjectClass *klass, void *data) | ||
559 | +{ | ||
560 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
561 | + | ||
562 | + dc->realize = efuse_realize; | ||
563 | + device_class_set_props(dc, efuse_properties); | ||
564 | +} | ||
565 | + | ||
566 | +static const TypeInfo efuse_info = { | ||
567 | + .name = TYPE_XLNX_EFUSE, | ||
568 | + .parent = TYPE_DEVICE, | ||
569 | + .instance_size = sizeof(XlnxEFuse), | ||
570 | + .class_init = efuse_class_init, | ||
571 | +}; | ||
572 | + | ||
573 | +static void efuse_register_types(void) | ||
574 | +{ | ||
575 | + type_register_static(&efuse_info); | ||
576 | +} | ||
577 | +type_init(efuse_register_types) | ||
578 | diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig | ||
54 | index XXXXXXX..XXXXXXX 100644 | 579 | index XXXXXXX..XXXXXXX 100644 |
55 | --- a/tests/acceptance/boot_linux_console.py | 580 | --- a/hw/nvram/Kconfig |
56 | +++ b/tests/acceptance/boot_linux_console.py | 581 | +++ b/hw/nvram/Kconfig |
57 | @@ -XXX,XX +XXX,XX @@ | 582 | @@ -XXX,XX +XXX,XX @@ config NMC93XX_EEPROM |
58 | from avocado import skip | 583 | |
59 | from avocado import skipUnless | 584 | config CHRP_NVRAM |
60 | from avocado_qemu import Test | 585 | bool |
61 | +from avocado_qemu import exec_command | 586 | + |
62 | from avocado_qemu import exec_command_and_wait_for_pattern | 587 | +config XLNX_EFUSE_CRC |
63 | from avocado_qemu import interrupt_interactive_console_until_pattern | 588 | + bool |
64 | from avocado_qemu import wait_for_console_pattern | 589 | + |
65 | @@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self): | 590 | +config XLNX_EFUSE |
66 | """ | 591 | + bool |
67 | self.do_test_arm_raspi2(0) | 592 | + select XLNX_EFUSE_CRC |
68 | 593 | diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build | |
69 | + def test_arm_raspi2_initrd(self): | 594 | index XXXXXXX..XXXXXXX 100644 |
70 | + """ | 595 | --- a/hw/nvram/meson.build |
71 | + :avocado: tags=arch:arm | 596 | +++ b/hw/nvram/meson.build |
72 | + :avocado: tags=machine:raspi2 | 597 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_AT24C', if_true: files('eeprom_at24c.c')) |
73 | + """ | 598 | softmmu_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c')) |
74 | + deb_url = ('http://archive.raspberrypi.org/debian/' | 599 | softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c')) |
75 | + 'pool/main/r/raspberrypi-firmware/' | 600 | softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c')) |
76 | + 'raspberrypi-kernel_1.20190215-1_armhf.deb') | 601 | +softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c')) |
77 | + deb_hash = 'cd284220b32128c5084037553db3c482426f3972' | 602 | +softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c')) |
78 | + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | 603 | |
79 | + kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img') | 604 | specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c')) |
80 | + dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb') | ||
81 | + | ||
82 | + initrd_url = ('https://github.com/groeck/linux-build-test/raw/' | ||
83 | + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' | ||
84 | + 'arm/rootfs-armv7a.cpio.gz') | ||
85 | + initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c' | ||
86 | + initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash) | ||
87 | + initrd_path = os.path.join(self.workdir, 'rootfs.cpio') | ||
88 | + archive.gzip_uncompress(initrd_path_gz, initrd_path) | ||
89 | + | ||
90 | + self.vm.set_console() | ||
91 | + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + | ||
92 | + 'earlycon=pl011,0x3f201000 console=ttyAMA0 ' | ||
93 | + 'panic=-1 noreboot ' + | ||
94 | + 'dwc_otg.fiq_fsm_enable=0') | ||
95 | + self.vm.add_args('-kernel', kernel_path, | ||
96 | + '-dtb', dtb_path, | ||
97 | + '-initrd', initrd_path, | ||
98 | + '-append', kernel_command_line, | ||
99 | + '-no-reboot') | ||
100 | + self.vm.launch() | ||
101 | + self.wait_for_console_pattern('Boot successful.') | ||
102 | + | ||
103 | + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', | ||
104 | + 'BCM2835') | ||
105 | + exec_command_and_wait_for_pattern(self, 'cat /proc/iomem', | ||
106 | + '/soc/cprman@7e101000') | ||
107 | + exec_command(self, 'halt') | ||
108 | + # Wait for VM to shut down gracefully | ||
109 | + self.vm.wait() | ||
110 | + | ||
111 | def test_arm_exynos4210_initrd(self): | ||
112 | """ | ||
113 | :avocado: tags=arch:arm | ||
114 | -- | 605 | -- |
115 | 2.20.1 | 606 | 2.20.1 |
116 | 607 | ||
117 | 608 | diff view generated by jsdifflib |
1 | From: Nolan Leake <nolan@sigbus.net> | 1 | From: Tong Ho <tong.ho@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | This is just enough to make reboot and poweroff work. Works for | 3 | This implements the Xilinx Versal eFuse, an one-time |
4 | linux, u-boot, and the arm trusted firmware. Not tested, but should | 4 | field-programmable non-volatile storage device. There is |
5 | work for plan9, and bare-metal/hobby OSes, since they seem to generally | 5 | only one such device in the Xilinx Versal product family. |
6 | do what linux does for reset. | ||
7 | 6 | ||
8 | The watchdog timer functionality is not yet implemented. | 7 | This device has two separate mmio interfaces, a controller |
8 | and a flatten readback. | ||
9 | 9 | ||
10 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64 | 10 | The controller provides interfaces for field-programming, |
11 | Signed-off-by: Nolan Leake <nolan@sigbus.net> | 11 | configuration, control, and status. |
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 12 | |
13 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 13 | The flatten readback is a cache to provide a byte-accessible |
14 | Message-id: 20210625210209.1870217-1-nolan@sigbus.net | 14 | read-only interface to efficiently read efuse array. |
15 | [PMM: tweaked commit title; fixed region size to 0x200; | 15 | |
16 | moved header file to include/] | 16 | Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
17 | Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | ||
18 | |||
19 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
20 | Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | ||
21 | Signed-off-by: Tong Ho <tong.ho@xilinx.com> | ||
22 | Message-id: 20210917052400.1249094-3-tong.ho@xilinx.com | ||
23 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | --- | 25 | --- |
19 | include/hw/arm/bcm2835_peripherals.h | 3 +- | 26 | include/hw/nvram/xlnx-versal-efuse.h | 68 +++ |
20 | include/hw/misc/bcm2835_powermgt.h | 29 +++++ | 27 | hw/nvram/xlnx-versal-efuse-cache.c | 114 ++++ |
21 | hw/arm/bcm2835_peripherals.c | 13 ++- | 28 | hw/nvram/xlnx-versal-efuse-ctrl.c | 783 +++++++++++++++++++++++++++ |
22 | hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++ | 29 | hw/nvram/Kconfig | 4 + |
23 | hw/misc/meson.build | 1 + | 30 | hw/nvram/meson.build | 3 + |
24 | 5 files changed, 204 insertions(+), 2 deletions(-) | 31 | 5 files changed, 972 insertions(+) |
25 | create mode 100644 include/hw/misc/bcm2835_powermgt.h | 32 | create mode 100644 include/hw/nvram/xlnx-versal-efuse.h |
26 | create mode 100644 hw/misc/bcm2835_powermgt.c | 33 | create mode 100644 hw/nvram/xlnx-versal-efuse-cache.c |
34 | create mode 100644 hw/nvram/xlnx-versal-efuse-ctrl.c | ||
27 | 35 | ||
28 | diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h | 36 | diff --git a/include/hw/nvram/xlnx-versal-efuse.h b/include/hw/nvram/xlnx-versal-efuse.h |
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/include/hw/arm/bcm2835_peripherals.h | ||
31 | +++ b/include/hw/arm/bcm2835_peripherals.h | ||
32 | @@ -XXX,XX +XXX,XX @@ | ||
33 | #include "hw/misc/bcm2835_mphi.h" | ||
34 | #include "hw/misc/bcm2835_thermal.h" | ||
35 | #include "hw/misc/bcm2835_cprman.h" | ||
36 | +#include "hw/misc/bcm2835_powermgt.h" | ||
37 | #include "hw/sd/sdhci.h" | ||
38 | #include "hw/sd/bcm2835_sdhost.h" | ||
39 | #include "hw/gpio/bcm2835_gpio.h" | ||
40 | @@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState { | ||
41 | BCM2835MphiState mphi; | ||
42 | UnimplementedDeviceState txp; | ||
43 | UnimplementedDeviceState armtmr; | ||
44 | - UnimplementedDeviceState powermgt; | ||
45 | + BCM2835PowerMgtState powermgt; | ||
46 | BCM2835CprmanState cprman; | ||
47 | PL011State uart0; | ||
48 | BCM2835AuxState aux; | ||
49 | diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h | ||
50 | new file mode 100644 | 37 | new file mode 100644 |
51 | index XXXXXXX..XXXXXXX | 38 | index XXXXXXX..XXXXXXX |
52 | --- /dev/null | 39 | --- /dev/null |
53 | +++ b/include/hw/misc/bcm2835_powermgt.h | 40 | +++ b/include/hw/nvram/xlnx-versal-efuse.h |
54 | @@ -XXX,XX +XXX,XX @@ | 41 | @@ -XXX,XX +XXX,XX @@ |
55 | +/* | 42 | +/* |
56 | + * BCM2835 Power Management emulation | 43 | + * Copyright (c) 2020 Xilinx Inc. |
57 | + * | 44 | + * |
58 | + * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com> | 45 | + * Permission is hereby granted, free of charge, to any person obtaining a copy |
59 | + * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net> | 46 | + * of this software and associated documentation files (the "Software"), to deal |
60 | + * | 47 | + * in the Software without restriction, including without limitation the rights |
61 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | 48 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
62 | + * See the COPYING file in the top-level directory. | 49 | + * copies of the Software, and to permit persons to whom the Software is |
50 | + * furnished to do so, subject to the following conditions: | ||
51 | + * | ||
52 | + * The above copyright notice and this permission notice shall be included in | ||
53 | + * all copies or substantial portions of the Software. | ||
54 | + * | ||
55 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
56 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
57 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
58 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
59 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
60 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
61 | + * THE SOFTWARE. | ||
63 | + */ | 62 | + */ |
64 | + | 63 | +#ifndef XLNX_VERSAL_EFUSE_H |
65 | +#ifndef BCM2835_POWERMGT_H | 64 | +#define XLNX_VERSAL_EFUSE_H |
66 | +#define BCM2835_POWERMGT_H | 65 | + |
67 | + | 66 | +#include "hw/irq.h" |
68 | +#include "hw/sysbus.h" | 67 | +#include "hw/sysbus.h" |
69 | +#include "qom/object.h" | 68 | +#include "hw/register.h" |
70 | + | 69 | +#include "hw/nvram/xlnx-efuse.h" |
71 | +#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt" | 70 | + |
72 | +OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT) | 71 | +#define XLNX_VERSAL_EFUSE_CTRL_R_MAX ((0x100 / 4) + 1) |
73 | + | 72 | + |
74 | +struct BCM2835PowerMgtState { | 73 | +#define TYPE_XLNX_VERSAL_EFUSE_CTRL "xlnx,versal-efuse" |
75 | + SysBusDevice busdev; | 74 | +#define TYPE_XLNX_VERSAL_EFUSE_CACHE "xlnx,pmc-efuse-cache" |
75 | + | ||
76 | +OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCtrl, XLNX_VERSAL_EFUSE_CTRL); | ||
77 | +OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalEFuseCache, XLNX_VERSAL_EFUSE_CACHE); | ||
78 | + | ||
79 | +struct XlnxVersalEFuseCtrl { | ||
80 | + SysBusDevice parent_obj; | ||
81 | + qemu_irq irq_efuse_imr; | ||
82 | + | ||
83 | + XlnxEFuse *efuse; | ||
84 | + | ||
85 | + void *extra_pg0_lock_spec; /* Opaque property */ | ||
86 | + uint32_t extra_pg0_lock_n16; | ||
87 | + | ||
88 | + uint32_t regs[XLNX_VERSAL_EFUSE_CTRL_R_MAX]; | ||
89 | + RegisterInfo regs_info[XLNX_VERSAL_EFUSE_CTRL_R_MAX]; | ||
90 | +}; | ||
91 | + | ||
92 | +struct XlnxVersalEFuseCache { | ||
93 | + SysBusDevice parent_obj; | ||
76 | + MemoryRegion iomem; | 94 | + MemoryRegion iomem; |
77 | + | 95 | + |
78 | + uint32_t rstc; | 96 | + XlnxEFuse *efuse; |
79 | + uint32_t rsts; | ||
80 | + uint32_t wdog; | ||
81 | +}; | 97 | +}; |
82 | + | 98 | + |
99 | +/** | ||
100 | + * xlnx_versal_efuse_read_row: | ||
101 | + * @s: the efuse object | ||
102 | + * @bit: the bit-address within the 32-bit row to be read | ||
103 | + * @denied: if non-NULL, to receive true if the row is write-only | ||
104 | + * | ||
105 | + * Returns: the 32-bit word containing address @bit; 0 if @denies is true | ||
106 | + */ | ||
107 | +uint32_t xlnx_versal_efuse_read_row(XlnxEFuse *s, uint32_t bit, bool *denied); | ||
108 | + | ||
83 | +#endif | 109 | +#endif |
84 | diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c | 110 | diff --git a/hw/nvram/xlnx-versal-efuse-cache.c b/hw/nvram/xlnx-versal-efuse-cache.c |
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/hw/arm/bcm2835_peripherals.c | ||
87 | +++ b/hw/arm/bcm2835_peripherals.c | ||
88 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj) | ||
89 | |||
90 | object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr", | ||
91 | OBJECT(&s->gpu_bus_mr)); | ||
92 | + | ||
93 | + /* Power Management */ | ||
94 | + object_initialize_child(obj, "powermgt", &s->powermgt, | ||
95 | + TYPE_BCM2835_POWERMGT); | ||
96 | } | ||
97 | |||
98 | static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | ||
99 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | ||
100 | qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, | ||
101 | INTERRUPT_USB)); | ||
102 | |||
103 | + /* Power Management */ | ||
104 | + if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) { | ||
105 | + return; | ||
106 | + } | ||
107 | + | ||
108 | + memory_region_add_subregion(&s->peri_mr, PM_OFFSET, | ||
109 | + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0)); | ||
110 | + | ||
111 | create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000); | ||
112 | create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); | ||
113 | - create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114); | ||
114 | create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); | ||
115 | create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100); | ||
116 | create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20); | ||
117 | diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c | ||
118 | new file mode 100644 | 111 | new file mode 100644 |
119 | index XXXXXXX..XXXXXXX | 112 | index XXXXXXX..XXXXXXX |
120 | --- /dev/null | 113 | --- /dev/null |
121 | +++ b/hw/misc/bcm2835_powermgt.c | 114 | +++ b/hw/nvram/xlnx-versal-efuse-cache.c |
122 | @@ -XXX,XX +XXX,XX @@ | 115 | @@ -XXX,XX +XXX,XX @@ |
123 | +/* | 116 | +/* |
124 | + * BCM2835 Power Management emulation | 117 | + * QEMU model of the EFuse_Cache |
125 | + * | 118 | + * |
126 | + * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com> | 119 | + * Copyright (c) 2017 Xilinx Inc. |
127 | + * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net> | 120 | + * |
128 | + * | 121 | + * Permission is hereby granted, free of charge, to any person obtaining a copy |
129 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | 122 | + * of this software and associated documentation files (the "Software"), to deal |
130 | + * See the COPYING file in the top-level directory. | 123 | + * in the Software without restriction, including without limitation the rights |
124 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
125 | + * copies of the Software, and to permit persons to whom the Software is | ||
126 | + * furnished to do so, subject to the following conditions: | ||
127 | + * | ||
128 | + * The above copyright notice and this permission notice shall be included in | ||
129 | + * all copies or substantial portions of the Software. | ||
130 | + * | ||
131 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
132 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
133 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
134 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
135 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
136 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
137 | + * THE SOFTWARE. | ||
131 | + */ | 138 | + */ |
132 | + | 139 | + |
133 | +#include "qemu/osdep.h" | 140 | +#include "qemu/osdep.h" |
141 | +#include "hw/nvram/xlnx-versal-efuse.h" | ||
142 | + | ||
134 | +#include "qemu/log.h" | 143 | +#include "qemu/log.h" |
135 | +#include "qemu/module.h" | 144 | +#include "hw/qdev-properties.h" |
136 | +#include "hw/misc/bcm2835_powermgt.h" | 145 | + |
146 | +#define MR_SIZE 0xC00 | ||
147 | + | ||
148 | +static uint64_t efuse_cache_read(void *opaque, hwaddr addr, unsigned size) | ||
149 | +{ | ||
150 | + XlnxVersalEFuseCache *s = XLNX_VERSAL_EFUSE_CACHE(opaque); | ||
151 | + unsigned int w0 = QEMU_ALIGN_DOWN(addr * 8, 32); | ||
152 | + unsigned int w1 = QEMU_ALIGN_DOWN((addr + size - 1) * 8, 32); | ||
153 | + | ||
154 | + uint64_t ret; | ||
155 | + | ||
156 | + assert(w0 == w1 || (w0 + 32) == w1); | ||
157 | + | ||
158 | + ret = xlnx_versal_efuse_read_row(s->efuse, w1, NULL); | ||
159 | + if (w0 < w1) { | ||
160 | + ret <<= 32; | ||
161 | + ret |= xlnx_versal_efuse_read_row(s->efuse, w0, NULL); | ||
162 | + } | ||
163 | + | ||
164 | + /* If 'addr' unaligned, the guest is always assumed to be little-endian. */ | ||
165 | + addr &= 3; | ||
166 | + if (addr) { | ||
167 | + ret >>= 8 * addr; | ||
168 | + } | ||
169 | + | ||
170 | + return ret; | ||
171 | +} | ||
172 | + | ||
173 | +static void efuse_cache_write(void *opaque, hwaddr addr, uint64_t value, | ||
174 | + unsigned size) | ||
175 | +{ | ||
176 | + /* No Register Writes allowed */ | ||
177 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: efuse cache registers are read-only", | ||
178 | + __func__); | ||
179 | +} | ||
180 | + | ||
181 | +static const MemoryRegionOps efuse_cache_ops = { | ||
182 | + .read = efuse_cache_read, | ||
183 | + .write = efuse_cache_write, | ||
184 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
185 | + .valid = { | ||
186 | + .min_access_size = 1, | ||
187 | + .max_access_size = 4, | ||
188 | + }, | ||
189 | +}; | ||
190 | + | ||
191 | +static void efuse_cache_init(Object *obj) | ||
192 | +{ | ||
193 | + XlnxVersalEFuseCache *s = XLNX_VERSAL_EFUSE_CACHE(obj); | ||
194 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
195 | + | ||
196 | + memory_region_init_io(&s->iomem, obj, &efuse_cache_ops, s, | ||
197 | + TYPE_XLNX_VERSAL_EFUSE_CACHE, MR_SIZE); | ||
198 | + sysbus_init_mmio(sbd, &s->iomem); | ||
199 | +} | ||
200 | + | ||
201 | +static Property efuse_cache_props[] = { | ||
202 | + DEFINE_PROP_LINK("efuse", | ||
203 | + XlnxVersalEFuseCache, efuse, | ||
204 | + TYPE_XLNX_EFUSE, XlnxEFuse *), | ||
205 | + | ||
206 | + DEFINE_PROP_END_OF_LIST(), | ||
207 | +}; | ||
208 | + | ||
209 | +static void efuse_cache_class_init(ObjectClass *klass, void *data) | ||
210 | +{ | ||
211 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
212 | + | ||
213 | + device_class_set_props(dc, efuse_cache_props); | ||
214 | +} | ||
215 | + | ||
216 | +static const TypeInfo efuse_cache_info = { | ||
217 | + .name = TYPE_XLNX_VERSAL_EFUSE_CACHE, | ||
218 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
219 | + .instance_size = sizeof(XlnxVersalEFuseCache), | ||
220 | + .class_init = efuse_cache_class_init, | ||
221 | + .instance_init = efuse_cache_init, | ||
222 | +}; | ||
223 | + | ||
224 | +static void efuse_cache_register_types(void) | ||
225 | +{ | ||
226 | + type_register_static(&efuse_cache_info); | ||
227 | +} | ||
228 | + | ||
229 | +type_init(efuse_cache_register_types) | ||
230 | diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c | ||
231 | new file mode 100644 | ||
232 | index XXXXXXX..XXXXXXX | ||
233 | --- /dev/null | ||
234 | +++ b/hw/nvram/xlnx-versal-efuse-ctrl.c | ||
235 | @@ -XXX,XX +XXX,XX @@ | ||
236 | +/* | ||
237 | + * QEMU model of the Versal eFuse controller | ||
238 | + * | ||
239 | + * Copyright (c) 2020 Xilinx Inc. | ||
240 | + * | ||
241 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
242 | + * of this software and associated documentation files (the "Software"), to deal | ||
243 | + * in the Software without restriction, including without limitation the rights | ||
244 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
245 | + * copies of the Software, and to permit persons to whom the Software is | ||
246 | + * furnished to do so, subject to the following conditions: | ||
247 | + * | ||
248 | + * The above copyright notice and this permission notice shall be included in | ||
249 | + * all copies or substantial portions of the Software. | ||
250 | + * | ||
251 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
252 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
253 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
254 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
255 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
256 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
257 | + * THE SOFTWARE. | ||
258 | + */ | ||
259 | + | ||
260 | +#include "qemu/osdep.h" | ||
261 | +#include "hw/nvram/xlnx-versal-efuse.h" | ||
262 | + | ||
263 | +#include "qemu/log.h" | ||
264 | +#include "qapi/error.h" | ||
137 | +#include "migration/vmstate.h" | 265 | +#include "migration/vmstate.h" |
138 | +#include "sysemu/runstate.h" | 266 | +#include "hw/qdev-properties.h" |
139 | + | 267 | + |
140 | +#define PASSWORD 0x5a000000 | 268 | +#ifndef XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG |
141 | +#define PASSWORD_MASK 0xff000000 | 269 | +#define XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG 0 |
142 | + | 270 | +#endif |
143 | +#define R_RSTC 0x1c | 271 | + |
144 | +#define V_RSTC_RESET 0x20 | 272 | +REG32(WR_LOCK, 0x0) |
145 | +#define R_RSTS 0x20 | 273 | + FIELD(WR_LOCK, LOCK, 0, 16) |
146 | +#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */ | 274 | +REG32(CFG, 0x4) |
147 | +#define R_WDOG 0x24 | 275 | + FIELD(CFG, SLVERR_ENABLE, 5, 1) |
148 | + | 276 | + FIELD(CFG, MARGIN_RD, 2, 1) |
149 | +static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset, | 277 | + FIELD(CFG, PGM_EN, 1, 1) |
150 | + unsigned size) | 278 | +REG32(STATUS, 0x8) |
151 | +{ | 279 | + FIELD(STATUS, AES_USER_KEY_1_CRC_PASS, 11, 1) |
152 | + BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque; | 280 | + FIELD(STATUS, AES_USER_KEY_1_CRC_DONE, 10, 1) |
153 | + uint32_t res = 0; | 281 | + FIELD(STATUS, AES_USER_KEY_0_CRC_PASS, 9, 1) |
154 | + | 282 | + FIELD(STATUS, AES_USER_KEY_0_CRC_DONE, 8, 1) |
155 | + switch (offset) { | 283 | + FIELD(STATUS, AES_CRC_PASS, 7, 1) |
156 | + case R_RSTC: | 284 | + FIELD(STATUS, AES_CRC_DONE, 6, 1) |
157 | + res = s->rstc; | 285 | + FIELD(STATUS, CACHE_DONE, 5, 1) |
286 | + FIELD(STATUS, CACHE_LOAD, 4, 1) | ||
287 | + FIELD(STATUS, EFUSE_2_TBIT, 2, 1) | ||
288 | + FIELD(STATUS, EFUSE_1_TBIT, 1, 1) | ||
289 | + FIELD(STATUS, EFUSE_0_TBIT, 0, 1) | ||
290 | +REG32(EFUSE_PGM_ADDR, 0xc) | ||
291 | + FIELD(EFUSE_PGM_ADDR, PAGE, 13, 4) | ||
292 | + FIELD(EFUSE_PGM_ADDR, ROW, 5, 8) | ||
293 | + FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5) | ||
294 | +REG32(EFUSE_RD_ADDR, 0x10) | ||
295 | + FIELD(EFUSE_RD_ADDR, PAGE, 13, 4) | ||
296 | + FIELD(EFUSE_RD_ADDR, ROW, 5, 8) | ||
297 | +REG32(EFUSE_RD_DATA, 0x14) | ||
298 | +REG32(TPGM, 0x18) | ||
299 | + FIELD(TPGM, VALUE, 0, 16) | ||
300 | +REG32(TRD, 0x1c) | ||
301 | + FIELD(TRD, VALUE, 0, 8) | ||
302 | +REG32(TSU_H_PS, 0x20) | ||
303 | + FIELD(TSU_H_PS, VALUE, 0, 8) | ||
304 | +REG32(TSU_H_PS_CS, 0x24) | ||
305 | + FIELD(TSU_H_PS_CS, VALUE, 0, 8) | ||
306 | +REG32(TRDM, 0x28) | ||
307 | + FIELD(TRDM, VALUE, 0, 8) | ||
308 | +REG32(TSU_H_CS, 0x2c) | ||
309 | + FIELD(TSU_H_CS, VALUE, 0, 8) | ||
310 | +REG32(EFUSE_ISR, 0x30) | ||
311 | + FIELD(EFUSE_ISR, APB_SLVERR, 31, 1) | ||
312 | + FIELD(EFUSE_ISR, CACHE_PARITY_E2, 14, 1) | ||
313 | + FIELD(EFUSE_ISR, CACHE_PARITY_E1, 13, 1) | ||
314 | + FIELD(EFUSE_ISR, CACHE_PARITY_E0S, 12, 1) | ||
315 | + FIELD(EFUSE_ISR, CACHE_PARITY_E0R, 11, 1) | ||
316 | + FIELD(EFUSE_ISR, CACHE_APB_SLVERR, 10, 1) | ||
317 | + FIELD(EFUSE_ISR, CACHE_REQ_ERROR, 9, 1) | ||
318 | + FIELD(EFUSE_ISR, MAIN_REQ_ERROR, 8, 1) | ||
319 | + FIELD(EFUSE_ISR, READ_ON_CACHE_LD, 7, 1) | ||
320 | + FIELD(EFUSE_ISR, CACHE_FSM_ERROR, 6, 1) | ||
321 | + FIELD(EFUSE_ISR, MAIN_FSM_ERROR, 5, 1) | ||
322 | + FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1) | ||
323 | + FIELD(EFUSE_ISR, RD_ERROR, 3, 1) | ||
324 | + FIELD(EFUSE_ISR, RD_DONE, 2, 1) | ||
325 | + FIELD(EFUSE_ISR, PGM_ERROR, 1, 1) | ||
326 | + FIELD(EFUSE_ISR, PGM_DONE, 0, 1) | ||
327 | +REG32(EFUSE_IMR, 0x34) | ||
328 | + FIELD(EFUSE_IMR, APB_SLVERR, 31, 1) | ||
329 | + FIELD(EFUSE_IMR, CACHE_PARITY_E2, 14, 1) | ||
330 | + FIELD(EFUSE_IMR, CACHE_PARITY_E1, 13, 1) | ||
331 | + FIELD(EFUSE_IMR, CACHE_PARITY_E0S, 12, 1) | ||
332 | + FIELD(EFUSE_IMR, CACHE_PARITY_E0R, 11, 1) | ||
333 | + FIELD(EFUSE_IMR, CACHE_APB_SLVERR, 10, 1) | ||
334 | + FIELD(EFUSE_IMR, CACHE_REQ_ERROR, 9, 1) | ||
335 | + FIELD(EFUSE_IMR, MAIN_REQ_ERROR, 8, 1) | ||
336 | + FIELD(EFUSE_IMR, READ_ON_CACHE_LD, 7, 1) | ||
337 | + FIELD(EFUSE_IMR, CACHE_FSM_ERROR, 6, 1) | ||
338 | + FIELD(EFUSE_IMR, MAIN_FSM_ERROR, 5, 1) | ||
339 | + FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1) | ||
340 | + FIELD(EFUSE_IMR, RD_ERROR, 3, 1) | ||
341 | + FIELD(EFUSE_IMR, RD_DONE, 2, 1) | ||
342 | + FIELD(EFUSE_IMR, PGM_ERROR, 1, 1) | ||
343 | + FIELD(EFUSE_IMR, PGM_DONE, 0, 1) | ||
344 | +REG32(EFUSE_IER, 0x38) | ||
345 | + FIELD(EFUSE_IER, APB_SLVERR, 31, 1) | ||
346 | + FIELD(EFUSE_IER, CACHE_PARITY_E2, 14, 1) | ||
347 | + FIELD(EFUSE_IER, CACHE_PARITY_E1, 13, 1) | ||
348 | + FIELD(EFUSE_IER, CACHE_PARITY_E0S, 12, 1) | ||
349 | + FIELD(EFUSE_IER, CACHE_PARITY_E0R, 11, 1) | ||
350 | + FIELD(EFUSE_IER, CACHE_APB_SLVERR, 10, 1) | ||
351 | + FIELD(EFUSE_IER, CACHE_REQ_ERROR, 9, 1) | ||
352 | + FIELD(EFUSE_IER, MAIN_REQ_ERROR, 8, 1) | ||
353 | + FIELD(EFUSE_IER, READ_ON_CACHE_LD, 7, 1) | ||
354 | + FIELD(EFUSE_IER, CACHE_FSM_ERROR, 6, 1) | ||
355 | + FIELD(EFUSE_IER, MAIN_FSM_ERROR, 5, 1) | ||
356 | + FIELD(EFUSE_IER, CACHE_ERROR, 4, 1) | ||
357 | + FIELD(EFUSE_IER, RD_ERROR, 3, 1) | ||
358 | + FIELD(EFUSE_IER, RD_DONE, 2, 1) | ||
359 | + FIELD(EFUSE_IER, PGM_ERROR, 1, 1) | ||
360 | + FIELD(EFUSE_IER, PGM_DONE, 0, 1) | ||
361 | +REG32(EFUSE_IDR, 0x3c) | ||
362 | + FIELD(EFUSE_IDR, APB_SLVERR, 31, 1) | ||
363 | + FIELD(EFUSE_IDR, CACHE_PARITY_E2, 14, 1) | ||
364 | + FIELD(EFUSE_IDR, CACHE_PARITY_E1, 13, 1) | ||
365 | + FIELD(EFUSE_IDR, CACHE_PARITY_E0S, 12, 1) | ||
366 | + FIELD(EFUSE_IDR, CACHE_PARITY_E0R, 11, 1) | ||
367 | + FIELD(EFUSE_IDR, CACHE_APB_SLVERR, 10, 1) | ||
368 | + FIELD(EFUSE_IDR, CACHE_REQ_ERROR, 9, 1) | ||
369 | + FIELD(EFUSE_IDR, MAIN_REQ_ERROR, 8, 1) | ||
370 | + FIELD(EFUSE_IDR, READ_ON_CACHE_LD, 7, 1) | ||
371 | + FIELD(EFUSE_IDR, CACHE_FSM_ERROR, 6, 1) | ||
372 | + FIELD(EFUSE_IDR, MAIN_FSM_ERROR, 5, 1) | ||
373 | + FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1) | ||
374 | + FIELD(EFUSE_IDR, RD_ERROR, 3, 1) | ||
375 | + FIELD(EFUSE_IDR, RD_DONE, 2, 1) | ||
376 | + FIELD(EFUSE_IDR, PGM_ERROR, 1, 1) | ||
377 | + FIELD(EFUSE_IDR, PGM_DONE, 0, 1) | ||
378 | +REG32(EFUSE_CACHE_LOAD, 0x40) | ||
379 | + FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1) | ||
380 | +REG32(EFUSE_PGM_LOCK, 0x44) | ||
381 | + FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1) | ||
382 | +REG32(EFUSE_AES_CRC, 0x48) | ||
383 | +REG32(EFUSE_AES_USR_KEY0_CRC, 0x4c) | ||
384 | +REG32(EFUSE_AES_USR_KEY1_CRC, 0x50) | ||
385 | +REG32(EFUSE_PD, 0x54) | ||
386 | +REG32(EFUSE_ANLG_OSC_SW_1LP, 0x60) | ||
387 | +REG32(EFUSE_TEST_CTRL, 0x100) | ||
388 | + | ||
389 | +#define R_MAX (R_EFUSE_TEST_CTRL + 1) | ||
390 | + | ||
391 | +#define R_WR_LOCK_UNLOCK_PASSCODE (0xDF0D) | ||
392 | + | ||
393 | +/* | ||
394 | + * eFuse layout references: | ||
395 | + * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilnvm/src/xnvm_efuse_hw.h | ||
396 | + */ | ||
397 | +#define BIT_POS_OF(A_) \ | ||
398 | + ((uint32_t)((A_) & (R_EFUSE_PGM_ADDR_ROW_MASK | \ | ||
399 | + R_EFUSE_PGM_ADDR_COLUMN_MASK))) | ||
400 | + | ||
401 | +#define BIT_POS(R_, C_) \ | ||
402 | + ((uint32_t)((R_EFUSE_PGM_ADDR_ROW_MASK \ | ||
403 | + & ((R_) << R_EFUSE_PGM_ADDR_ROW_SHIFT)) \ | ||
404 | + | \ | ||
405 | + (R_EFUSE_PGM_ADDR_COLUMN_MASK \ | ||
406 | + & ((C_) << R_EFUSE_PGM_ADDR_COLUMN_SHIFT)))) | ||
407 | + | ||
408 | +#define EFUSE_TBIT_POS(A_) (BIT_POS_OF(A_) >= BIT_POS(0, 28)) | ||
409 | + | ||
410 | +#define EFUSE_ANCHOR_ROW (0) | ||
411 | +#define EFUSE_ANCHOR_3_COL (27) | ||
412 | +#define EFUSE_ANCHOR_1_COL (1) | ||
413 | + | ||
414 | +#define EFUSE_AES_KEY_START BIT_POS(12, 0) | ||
415 | +#define EFUSE_AES_KEY_END BIT_POS(19, 31) | ||
416 | +#define EFUSE_USER_KEY_0_START BIT_POS(20, 0) | ||
417 | +#define EFUSE_USER_KEY_0_END BIT_POS(27, 31) | ||
418 | +#define EFUSE_USER_KEY_1_START BIT_POS(28, 0) | ||
419 | +#define EFUSE_USER_KEY_1_END BIT_POS(35, 31) | ||
420 | + | ||
421 | +#define EFUSE_RD_BLOCKED_START EFUSE_AES_KEY_START | ||
422 | +#define EFUSE_RD_BLOCKED_END EFUSE_USER_KEY_1_END | ||
423 | + | ||
424 | +#define EFUSE_GLITCH_DET_WR_LK BIT_POS(4, 31) | ||
425 | +#define EFUSE_PPK0_WR_LK BIT_POS(43, 6) | ||
426 | +#define EFUSE_PPK1_WR_LK BIT_POS(43, 7) | ||
427 | +#define EFUSE_PPK2_WR_LK BIT_POS(43, 8) | ||
428 | +#define EFUSE_AES_WR_LK BIT_POS(43, 11) | ||
429 | +#define EFUSE_USER_KEY_0_WR_LK BIT_POS(43, 13) | ||
430 | +#define EFUSE_USER_KEY_1_WR_LK BIT_POS(43, 15) | ||
431 | +#define EFUSE_PUF_SYN_LK BIT_POS(43, 16) | ||
432 | +#define EFUSE_DNA_WR_LK BIT_POS(43, 27) | ||
433 | +#define EFUSE_BOOT_ENV_WR_LK BIT_POS(43, 28) | ||
434 | + | ||
435 | +#define EFUSE_PGM_LOCKED_START BIT_POS(44, 0) | ||
436 | +#define EFUSE_PGM_LOCKED_END BIT_POS(51, 31) | ||
437 | + | ||
438 | +#define EFUSE_PUF_PAGE (2) | ||
439 | +#define EFUSE_PUF_SYN_START BIT_POS(129, 0) | ||
440 | +#define EFUSE_PUF_SYN_END BIT_POS(255, 27) | ||
441 | + | ||
442 | +#define EFUSE_KEY_CRC_LK_ROW (43) | ||
443 | +#define EFUSE_AES_KEY_CRC_LK_MASK ((1U << 9) | (1U << 10)) | ||
444 | +#define EFUSE_USER_KEY_0_CRC_LK_MASK (1U << 12) | ||
445 | +#define EFUSE_USER_KEY_1_CRC_LK_MASK (1U << 14) | ||
446 | + | ||
447 | +/* | ||
448 | + * A handy macro to return value of an array element, | ||
449 | + * or a specific default if given index is out of bound. | ||
450 | + */ | ||
451 | +#define ARRAY_GET(A_, I_, D_) \ | ||
452 | + ((unsigned int)(I_) < ARRAY_SIZE(A_) ? (A_)[I_] : (D_)) | ||
453 | + | ||
454 | +QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxVersalEFuseCtrl *)0)->regs)); | ||
455 | + | ||
456 | +typedef struct XlnxEFuseLkSpec { | ||
457 | + uint16_t row; | ||
458 | + uint16_t lk_bit; | ||
459 | +} XlnxEFuseLkSpec; | ||
460 | + | ||
461 | +static void efuse_imr_update_irq(XlnxVersalEFuseCtrl *s) | ||
462 | +{ | ||
463 | + bool pending = s->regs[R_EFUSE_ISR] & ~s->regs[R_EFUSE_IMR]; | ||
464 | + qemu_set_irq(s->irq_efuse_imr, pending); | ||
465 | +} | ||
466 | + | ||
467 | +static void efuse_isr_postw(RegisterInfo *reg, uint64_t val64) | ||
468 | +{ | ||
469 | + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); | ||
470 | + efuse_imr_update_irq(s); | ||
471 | +} | ||
472 | + | ||
473 | +static uint64_t efuse_ier_prew(RegisterInfo *reg, uint64_t val64) | ||
474 | +{ | ||
475 | + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); | ||
476 | + uint32_t val = val64; | ||
477 | + | ||
478 | + s->regs[R_EFUSE_IMR] &= ~val; | ||
479 | + efuse_imr_update_irq(s); | ||
480 | + return 0; | ||
481 | +} | ||
482 | + | ||
483 | +static uint64_t efuse_idr_prew(RegisterInfo *reg, uint64_t val64) | ||
484 | +{ | ||
485 | + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); | ||
486 | + uint32_t val = val64; | ||
487 | + | ||
488 | + s->regs[R_EFUSE_IMR] |= val; | ||
489 | + efuse_imr_update_irq(s); | ||
490 | + return 0; | ||
491 | +} | ||
492 | + | ||
493 | +static void efuse_status_tbits_sync(XlnxVersalEFuseCtrl *s) | ||
494 | +{ | ||
495 | + uint32_t check = xlnx_efuse_tbits_check(s->efuse); | ||
496 | + uint32_t val = s->regs[R_STATUS]; | ||
497 | + | ||
498 | + val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0))); | ||
499 | + val = FIELD_DP32(val, STATUS, EFUSE_1_TBIT, !!(check & (1 << 1))); | ||
500 | + val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 2))); | ||
501 | + | ||
502 | + s->regs[R_STATUS] = val; | ||
503 | +} | ||
504 | + | ||
505 | +static void efuse_anchor_bits_check(XlnxVersalEFuseCtrl *s) | ||
506 | +{ | ||
507 | + unsigned page; | ||
508 | + | ||
509 | + if (!s->efuse || !s->efuse->init_tbits) { | ||
510 | + return; | ||
511 | + } | ||
512 | + | ||
513 | + for (page = 0; page < s->efuse->efuse_nr; page++) { | ||
514 | + uint32_t row = 0, bit; | ||
515 | + | ||
516 | + row = FIELD_DP32(row, EFUSE_PGM_ADDR, PAGE, page); | ||
517 | + row = FIELD_DP32(row, EFUSE_PGM_ADDR, ROW, EFUSE_ANCHOR_ROW); | ||
518 | + | ||
519 | + bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_3_COL); | ||
520 | + if (!xlnx_efuse_get_bit(s->efuse, bit)) { | ||
521 | + xlnx_efuse_set_bit(s->efuse, bit); | ||
522 | + } | ||
523 | + | ||
524 | + bit = FIELD_DP32(row, EFUSE_PGM_ADDR, COLUMN, EFUSE_ANCHOR_1_COL); | ||
525 | + if (!xlnx_efuse_get_bit(s->efuse, bit)) { | ||
526 | + xlnx_efuse_set_bit(s->efuse, bit); | ||
527 | + } | ||
528 | + } | ||
529 | +} | ||
530 | + | ||
531 | +static void efuse_key_crc_check(RegisterInfo *reg, uint32_t crc, | ||
532 | + uint32_t pass_mask, uint32_t done_mask, | ||
533 | + unsigned first, uint32_t lk_mask) | ||
534 | +{ | ||
535 | + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); | ||
536 | + uint32_t r, lk_bits; | ||
537 | + | ||
538 | + /* | ||
539 | + * To start, assume both DONE and PASS, and clear PASS by xor | ||
540 | + * if CRC-check fails or CRC-check disabled by lock fuse. | ||
541 | + */ | ||
542 | + r = s->regs[R_STATUS] | done_mask | pass_mask; | ||
543 | + | ||
544 | + lk_bits = xlnx_efuse_get_row(s->efuse, EFUSE_KEY_CRC_LK_ROW) & lk_mask; | ||
545 | + if (lk_bits == 0 && xlnx_efuse_k256_check(s->efuse, crc, first)) { | ||
546 | + pass_mask = 0; | ||
547 | + } | ||
548 | + | ||
549 | + s->regs[R_STATUS] = r ^ pass_mask; | ||
550 | +} | ||
551 | + | ||
552 | +static void efuse_data_sync(XlnxVersalEFuseCtrl *s) | ||
553 | +{ | ||
554 | + efuse_status_tbits_sync(s); | ||
555 | +} | ||
556 | + | ||
557 | +static int efuse_lk_spec_cmp(const void *a, const void *b) | ||
558 | +{ | ||
559 | + uint16_t r1 = ((const XlnxEFuseLkSpec *)a)->row; | ||
560 | + uint16_t r2 = ((const XlnxEFuseLkSpec *)b)->row; | ||
561 | + | ||
562 | + return (r1 > r2) - (r1 < r2); | ||
563 | +} | ||
564 | + | ||
565 | +static void efuse_lk_spec_sort(XlnxVersalEFuseCtrl *s) | ||
566 | +{ | ||
567 | + XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec; | ||
568 | + const uint32_t n8 = s->extra_pg0_lock_n16 * 2; | ||
569 | + const uint32_t sz = sizeof(ary[0]); | ||
570 | + const uint32_t cnt = n8 / sz; | ||
571 | + | ||
572 | + if (ary && cnt) { | ||
573 | + qsort(ary, cnt, sz, efuse_lk_spec_cmp); | ||
574 | + } | ||
575 | +} | ||
576 | + | ||
577 | +static uint32_t efuse_lk_spec_find(XlnxVersalEFuseCtrl *s, uint32_t row) | ||
578 | +{ | ||
579 | + const XlnxEFuseLkSpec *ary = s->extra_pg0_lock_spec; | ||
580 | + const uint32_t n8 = s->extra_pg0_lock_n16 * 2; | ||
581 | + const uint32_t sz = sizeof(ary[0]); | ||
582 | + const uint32_t cnt = n8 / sz; | ||
583 | + const XlnxEFuseLkSpec *item = NULL; | ||
584 | + | ||
585 | + if (ary && cnt) { | ||
586 | + XlnxEFuseLkSpec k = { .row = row, }; | ||
587 | + | ||
588 | + item = bsearch(&k, ary, cnt, sz, efuse_lk_spec_cmp); | ||
589 | + } | ||
590 | + | ||
591 | + return item ? item->lk_bit : 0; | ||
592 | +} | ||
593 | + | ||
594 | +static uint32_t efuse_bit_locked(XlnxVersalEFuseCtrl *s, uint32_t bit) | ||
595 | +{ | ||
596 | + /* Hard-coded locks */ | ||
597 | + static const uint16_t pg0_hard_lock[] = { | ||
598 | + [4] = EFUSE_GLITCH_DET_WR_LK, | ||
599 | + [37] = EFUSE_BOOT_ENV_WR_LK, | ||
600 | + | ||
601 | + [8 ... 11] = EFUSE_DNA_WR_LK, | ||
602 | + [12 ... 19] = EFUSE_AES_WR_LK, | ||
603 | + [20 ... 27] = EFUSE_USER_KEY_0_WR_LK, | ||
604 | + [28 ... 35] = EFUSE_USER_KEY_1_WR_LK, | ||
605 | + [64 ... 71] = EFUSE_PPK0_WR_LK, | ||
606 | + [72 ... 79] = EFUSE_PPK1_WR_LK, | ||
607 | + [80 ... 87] = EFUSE_PPK2_WR_LK, | ||
608 | + }; | ||
609 | + | ||
610 | + uint32_t row = FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW); | ||
611 | + uint32_t lk_bit = ARRAY_GET(pg0_hard_lock, row, 0); | ||
612 | + | ||
613 | + return lk_bit ? lk_bit : efuse_lk_spec_find(s, row); | ||
614 | +} | ||
615 | + | ||
616 | +static bool efuse_pgm_locked(XlnxVersalEFuseCtrl *s, unsigned int bit) | ||
617 | +{ | ||
618 | + | ||
619 | + unsigned int lock = 1; | ||
620 | + | ||
621 | + /* Global lock */ | ||
622 | + if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) { | ||
623 | + goto ret_lock; | ||
624 | + } | ||
625 | + | ||
626 | + /* Row lock */ | ||
627 | + switch (FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE)) { | ||
628 | + case 0: | ||
629 | + if (ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK) && | ||
630 | + bit >= EFUSE_PGM_LOCKED_START && bit <= EFUSE_PGM_LOCKED_END) { | ||
631 | + goto ret_lock; | ||
632 | + } | ||
633 | + | ||
634 | + lock = efuse_bit_locked(s, bit); | ||
158 | + break; | 635 | + break; |
159 | + case R_RSTS: | 636 | + case EFUSE_PUF_PAGE: |
160 | + res = s->rsts; | 637 | + if (bit < EFUSE_PUF_SYN_START || bit > EFUSE_PUF_SYN_END) { |
638 | + lock = 0; | ||
639 | + goto ret_lock; | ||
640 | + } | ||
641 | + | ||
642 | + lock = EFUSE_PUF_SYN_LK; | ||
161 | + break; | 643 | + break; |
162 | + case R_WDOG: | ||
163 | + res = s->wdog; | ||
164 | + break; | ||
165 | + | ||
166 | + default: | 644 | + default: |
167 | + qemu_log_mask(LOG_UNIMP, | 645 | + lock = 0; |
168 | + "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx | 646 | + goto ret_lock; |
169 | + "\n", offset); | 647 | + } |
170 | + res = 0; | 648 | + |
171 | + break; | 649 | + /* Row lock by an efuse bit */ |
172 | + } | 650 | + if (lock) { |
173 | + | 651 | + lock = xlnx_efuse_get_bit(s->efuse, lock); |
174 | + return res; | 652 | + } |
175 | +} | 653 | + |
176 | + | 654 | + ret_lock: |
177 | +static void bcm2835_powermgt_write(void *opaque, hwaddr offset, | 655 | + return lock != 0; |
178 | + uint64_t value, unsigned size) | 656 | +} |
179 | +{ | 657 | + |
180 | + BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque; | 658 | +static void efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64) |
181 | + | 659 | +{ |
182 | + if ((value & PASSWORD_MASK) != PASSWORD) { | 660 | + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); |
661 | + unsigned bit = val64; | ||
662 | + bool ok = false; | ||
663 | + | ||
664 | + /* Always zero out PGM_ADDR because it is write-only */ | ||
665 | + s->regs[R_EFUSE_PGM_ADDR] = 0; | ||
666 | + | ||
667 | + /* | ||
668 | + * Indicate error if bit is write-protected (or read-only | ||
669 | + * as guarded by efuse_set_bit()). | ||
670 | + * | ||
671 | + * Keep it simple by not modeling program timing. | ||
672 | + * | ||
673 | + * Note: model must NEVER clear the PGM_ERROR bit; it is | ||
674 | + * up to guest to do so (or by reset). | ||
675 | + */ | ||
676 | + if (efuse_pgm_locked(s, bit)) { | ||
183 | + qemu_log_mask(LOG_GUEST_ERROR, | 677 | + qemu_log_mask(LOG_GUEST_ERROR, |
184 | + "bcm2835_powermgt_write: Bad password 0x%"PRIx64 | 678 | + "%s: Denied setting of efuse<%u, %u, %u>\n", |
185 | + " at offset 0x%08"HWADDR_PRIx"\n", | 679 | + object_get_canonical_path(OBJECT(s)), |
186 | + value, offset); | 680 | + FIELD_EX32(bit, EFUSE_PGM_ADDR, PAGE), |
681 | + FIELD_EX32(bit, EFUSE_PGM_ADDR, ROW), | ||
682 | + FIELD_EX32(bit, EFUSE_PGM_ADDR, COLUMN)); | ||
683 | + } else if (xlnx_efuse_set_bit(s->efuse, bit)) { | ||
684 | + ok = true; | ||
685 | + if (EFUSE_TBIT_POS(bit)) { | ||
686 | + efuse_status_tbits_sync(s); | ||
687 | + } | ||
688 | + } | ||
689 | + | ||
690 | + if (!ok) { | ||
691 | + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1); | ||
692 | + } | ||
693 | + | ||
694 | + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1); | ||
695 | + efuse_imr_update_irq(s); | ||
696 | +} | ||
697 | + | ||
698 | +static void efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64) | ||
699 | +{ | ||
700 | + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); | ||
701 | + unsigned bit = val64; | ||
702 | + bool denied; | ||
703 | + | ||
704 | + /* Always zero out RD_ADDR because it is write-only */ | ||
705 | + s->regs[R_EFUSE_RD_ADDR] = 0; | ||
706 | + | ||
707 | + /* | ||
708 | + * Indicate error if row is read-blocked. | ||
709 | + * | ||
710 | + * Note: model must NEVER clear the RD_ERROR bit; it is | ||
711 | + * up to guest to do so (or by reset). | ||
712 | + */ | ||
713 | + s->regs[R_EFUSE_RD_DATA] = xlnx_versal_efuse_read_row(s->efuse, | ||
714 | + bit, &denied); | ||
715 | + if (denied) { | ||
716 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
717 | + "%s: Denied reading of efuse<%u, %u>\n", | ||
718 | + object_get_canonical_path(OBJECT(s)), | ||
719 | + FIELD_EX32(bit, EFUSE_RD_ADDR, PAGE), | ||
720 | + FIELD_EX32(bit, EFUSE_RD_ADDR, ROW)); | ||
721 | + | ||
722 | + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1); | ||
723 | + } | ||
724 | + | ||
725 | + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1); | ||
726 | + efuse_imr_update_irq(s); | ||
727 | + return; | ||
728 | +} | ||
729 | + | ||
730 | +static uint64_t efuse_cache_load_prew(RegisterInfo *reg, uint64_t val64) | ||
731 | +{ | ||
732 | + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); | ||
733 | + | ||
734 | + if (val64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) { | ||
735 | + efuse_data_sync(s); | ||
736 | + | ||
737 | + ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1); | ||
738 | + efuse_imr_update_irq(s); | ||
739 | + } | ||
740 | + | ||
741 | + return 0; | ||
742 | +} | ||
743 | + | ||
744 | +static uint64_t efuse_pgm_lock_prew(RegisterInfo *reg, uint64_t val64) | ||
745 | +{ | ||
746 | + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(reg->opaque); | ||
747 | + | ||
748 | + /* Ignore all other bits */ | ||
749 | + val64 = FIELD_EX32(val64, EFUSE_PGM_LOCK, SPK_ID_LOCK); | ||
750 | + | ||
751 | + /* Once the bit is written 1, only reset will clear it to 0 */ | ||
752 | + val64 |= ARRAY_FIELD_EX32(s->regs, EFUSE_PGM_LOCK, SPK_ID_LOCK); | ||
753 | + | ||
754 | + return val64; | ||
755 | +} | ||
756 | + | ||
757 | +static void efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64) | ||
758 | +{ | ||
759 | + efuse_key_crc_check(reg, val64, | ||
760 | + R_STATUS_AES_CRC_PASS_MASK, | ||
761 | + R_STATUS_AES_CRC_DONE_MASK, | ||
762 | + EFUSE_AES_KEY_START, | ||
763 | + EFUSE_AES_KEY_CRC_LK_MASK); | ||
764 | +} | ||
765 | + | ||
766 | +static void efuse_aes_u0_crc_postw(RegisterInfo *reg, uint64_t val64) | ||
767 | +{ | ||
768 | + efuse_key_crc_check(reg, val64, | ||
769 | + R_STATUS_AES_USER_KEY_0_CRC_PASS_MASK, | ||
770 | + R_STATUS_AES_USER_KEY_0_CRC_DONE_MASK, | ||
771 | + EFUSE_USER_KEY_0_START, | ||
772 | + EFUSE_USER_KEY_0_CRC_LK_MASK); | ||
773 | +} | ||
774 | + | ||
775 | +static void efuse_aes_u1_crc_postw(RegisterInfo *reg, uint64_t val64) | ||
776 | +{ | ||
777 | + efuse_key_crc_check(reg, val64, | ||
778 | + R_STATUS_AES_USER_KEY_1_CRC_PASS_MASK, | ||
779 | + R_STATUS_AES_USER_KEY_1_CRC_DONE_MASK, | ||
780 | + EFUSE_USER_KEY_1_START, | ||
781 | + EFUSE_USER_KEY_1_CRC_LK_MASK); | ||
782 | +} | ||
783 | + | ||
784 | +static uint64_t efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val) | ||
785 | +{ | ||
786 | + return val != R_WR_LOCK_UNLOCK_PASSCODE; | ||
787 | +} | ||
788 | + | ||
789 | +static const RegisterAccessInfo efuse_ctrl_regs_info[] = { | ||
790 | + { .name = "WR_LOCK", .addr = A_WR_LOCK, | ||
791 | + .reset = 0x1, | ||
792 | + .pre_write = efuse_wr_lock_prew, | ||
793 | + },{ .name = "CFG", .addr = A_CFG, | ||
794 | + .rsvd = 0x9, | ||
795 | + },{ .name = "STATUS", .addr = A_STATUS, | ||
796 | + .rsvd = 0x8, | ||
797 | + .ro = 0xfff, | ||
798 | + },{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR, | ||
799 | + .post_write = efuse_pgm_addr_postw, | ||
800 | + },{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR, | ||
801 | + .rsvd = 0x1f, | ||
802 | + .post_write = efuse_rd_addr_postw, | ||
803 | + },{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA, | ||
804 | + .ro = 0xffffffff, | ||
805 | + },{ .name = "TPGM", .addr = A_TPGM, | ||
806 | + },{ .name = "TRD", .addr = A_TRD, | ||
807 | + .reset = 0x19, | ||
808 | + },{ .name = "TSU_H_PS", .addr = A_TSU_H_PS, | ||
809 | + .reset = 0xff, | ||
810 | + },{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS, | ||
811 | + .reset = 0x11, | ||
812 | + },{ .name = "TRDM", .addr = A_TRDM, | ||
813 | + .reset = 0x3a, | ||
814 | + },{ .name = "TSU_H_CS", .addr = A_TSU_H_CS, | ||
815 | + .reset = 0x16, | ||
816 | + },{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR, | ||
817 | + .rsvd = 0x7fff8000, | ||
818 | + .w1c = 0x80007fff, | ||
819 | + .post_write = efuse_isr_postw, | ||
820 | + },{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR, | ||
821 | + .reset = 0x80007fff, | ||
822 | + .rsvd = 0x7fff8000, | ||
823 | + .ro = 0xffffffff, | ||
824 | + },{ .name = "EFUSE_IER", .addr = A_EFUSE_IER, | ||
825 | + .rsvd = 0x7fff8000, | ||
826 | + .pre_write = efuse_ier_prew, | ||
827 | + },{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR, | ||
828 | + .rsvd = 0x7fff8000, | ||
829 | + .pre_write = efuse_idr_prew, | ||
830 | + },{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD, | ||
831 | + .pre_write = efuse_cache_load_prew, | ||
832 | + },{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK, | ||
833 | + .pre_write = efuse_pgm_lock_prew, | ||
834 | + },{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC, | ||
835 | + .post_write = efuse_aes_crc_postw, | ||
836 | + },{ .name = "EFUSE_AES_USR_KEY0_CRC", .addr = A_EFUSE_AES_USR_KEY0_CRC, | ||
837 | + .post_write = efuse_aes_u0_crc_postw, | ||
838 | + },{ .name = "EFUSE_AES_USR_KEY1_CRC", .addr = A_EFUSE_AES_USR_KEY1_CRC, | ||
839 | + .post_write = efuse_aes_u1_crc_postw, | ||
840 | + },{ .name = "EFUSE_PD", .addr = A_EFUSE_PD, | ||
841 | + .ro = 0xfffffffe, | ||
842 | + },{ .name = "EFUSE_ANLG_OSC_SW_1LP", .addr = A_EFUSE_ANLG_OSC_SW_1LP, | ||
843 | + },{ .name = "EFUSE_TEST_CTRL", .addr = A_EFUSE_TEST_CTRL, | ||
844 | + .reset = 0x8, | ||
845 | + } | ||
846 | +}; | ||
847 | + | ||
848 | +static void efuse_ctrl_reg_write(void *opaque, hwaddr addr, | ||
849 | + uint64_t data, unsigned size) | ||
850 | +{ | ||
851 | + RegisterInfoArray *reg_array = opaque; | ||
852 | + XlnxVersalEFuseCtrl *s; | ||
853 | + Object *dev; | ||
854 | + | ||
855 | + assert(reg_array != NULL); | ||
856 | + | ||
857 | + dev = reg_array->mem.owner; | ||
858 | + assert(dev); | ||
859 | + | ||
860 | + s = XLNX_VERSAL_EFUSE_CTRL(dev); | ||
861 | + | ||
862 | + if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) { | ||
863 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
864 | + "%s[reg_0x%02lx]: Attempt to write locked register.\n", | ||
865 | + object_get_canonical_path(OBJECT(s)), (long)addr); | ||
866 | + } else { | ||
867 | + register_write_memory(opaque, addr, data, size); | ||
868 | + } | ||
869 | +} | ||
870 | + | ||
871 | +static void efuse_ctrl_register_reset(RegisterInfo *reg) | ||
872 | +{ | ||
873 | + if (!reg->data || !reg->access) { | ||
187 | + return; | 874 | + return; |
188 | + } | 875 | + } |
189 | + | 876 | + |
190 | + value = value & ~PASSWORD_MASK; | 877 | + /* Reset must not trigger some registers' writers */ |
191 | + | 878 | + switch (reg->access->addr) { |
192 | + switch (offset) { | 879 | + case A_EFUSE_AES_CRC: |
193 | + case R_RSTC: | 880 | + case A_EFUSE_AES_USR_KEY0_CRC: |
194 | + s->rstc = value; | 881 | + case A_EFUSE_AES_USR_KEY1_CRC: |
195 | + if (value & V_RSTC_RESET) { | 882 | + *(uint32_t *)reg->data = reg->access->reset; |
196 | + if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) { | 883 | + return; |
197 | + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | 884 | + } |
198 | + } else { | 885 | + |
199 | + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | 886 | + register_reset(reg); |
200 | + } | 887 | +} |
201 | + } | 888 | + |
202 | + break; | 889 | +static void efuse_ctrl_reset(DeviceState *dev) |
203 | + case R_RSTS: | 890 | +{ |
204 | + qemu_log_mask(LOG_UNIMP, | 891 | + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev); |
205 | + "bcm2835_powermgt_write: RSTS\n"); | 892 | + unsigned int i; |
206 | + s->rsts = value; | 893 | + |
207 | + break; | 894 | + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { |
208 | + case R_WDOG: | 895 | + efuse_ctrl_register_reset(&s->regs_info[i]); |
209 | + qemu_log_mask(LOG_UNIMP, | 896 | + } |
210 | + "bcm2835_powermgt_write: WDOG\n"); | 897 | + |
211 | + s->wdog = value; | 898 | + efuse_anchor_bits_check(s); |
212 | + break; | 899 | + efuse_data_sync(s); |
213 | + | 900 | + efuse_imr_update_irq(s); |
214 | + default: | 901 | +} |
215 | + qemu_log_mask(LOG_UNIMP, | 902 | + |
216 | + "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx | 903 | +static const MemoryRegionOps efuse_ctrl_ops = { |
217 | + "\n", offset); | 904 | + .read = register_read_memory, |
218 | + break; | 905 | + .write = efuse_ctrl_reg_write, |
219 | + } | 906 | + .endianness = DEVICE_LITTLE_ENDIAN, |
220 | +} | 907 | + .valid = { |
221 | + | 908 | + .min_access_size = 4, |
222 | +static const MemoryRegionOps bcm2835_powermgt_ops = { | 909 | + .max_access_size = 4, |
223 | + .read = bcm2835_powermgt_read, | 910 | + }, |
224 | + .write = bcm2835_powermgt_write, | ||
225 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
226 | + .impl.min_access_size = 4, | ||
227 | + .impl.max_access_size = 4, | ||
228 | +}; | 911 | +}; |
229 | + | 912 | + |
230 | +static const VMStateDescription vmstate_bcm2835_powermgt = { | 913 | +static void efuse_ctrl_realize(DeviceState *dev, Error **errp) |
231 | + .name = TYPE_BCM2835_POWERMGT, | 914 | +{ |
915 | + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(dev); | ||
916 | + const uint32_t lks_sz = sizeof(XlnxEFuseLkSpec) / 2; | ||
917 | + | ||
918 | + if (!s->efuse) { | ||
919 | + error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE", | ||
920 | + object_get_canonical_path(OBJECT(dev))); | ||
921 | + return; | ||
922 | + } | ||
923 | + | ||
924 | + /* Sort property-defined pgm-locks for bsearch lookup */ | ||
925 | + if ((s->extra_pg0_lock_n16 % lks_sz) != 0) { | ||
926 | + error_setg(errp, | ||
927 | + "%s.pg0-lock: array property item-count not multiple of %u", | ||
928 | + object_get_canonical_path(OBJECT(dev)), lks_sz); | ||
929 | + return; | ||
930 | + } | ||
931 | + | ||
932 | + efuse_lk_spec_sort(s); | ||
933 | +} | ||
934 | + | ||
935 | +static void efuse_ctrl_init(Object *obj) | ||
936 | +{ | ||
937 | + XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj); | ||
938 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
939 | + RegisterInfoArray *reg_array; | ||
940 | + | ||
941 | + reg_array = | ||
942 | + register_init_block32(DEVICE(obj), efuse_ctrl_regs_info, | ||
943 | + ARRAY_SIZE(efuse_ctrl_regs_info), | ||
944 | + s->regs_info, s->regs, | ||
945 | + &efuse_ctrl_ops, | ||
946 | + XLNX_VERSAL_EFUSE_CTRL_ERR_DEBUG, | ||
947 | + R_MAX * 4); | ||
948 | + | ||
949 | + sysbus_init_mmio(sbd, ®_array->mem); | ||
950 | + sysbus_init_irq(sbd, &s->irq_efuse_imr); | ||
951 | +} | ||
952 | + | ||
953 | +static const VMStateDescription vmstate_efuse_ctrl = { | ||
954 | + .name = TYPE_XLNX_VERSAL_EFUSE_CTRL, | ||
232 | + .version_id = 1, | 955 | + .version_id = 1, |
233 | + .minimum_version_id = 1, | 956 | + .minimum_version_id = 1, |
234 | + .fields = (VMStateField[]) { | 957 | + .fields = (VMStateField[]) { |
235 | + VMSTATE_UINT32(rstc, BCM2835PowerMgtState), | 958 | + VMSTATE_UINT32_ARRAY(regs, XlnxVersalEFuseCtrl, R_MAX), |
236 | + VMSTATE_UINT32(rsts, BCM2835PowerMgtState), | 959 | + VMSTATE_END_OF_LIST(), |
237 | + VMSTATE_UINT32(wdog, BCM2835PowerMgtState), | ||
238 | + VMSTATE_END_OF_LIST() | ||
239 | + } | 960 | + } |
240 | +}; | 961 | +}; |
241 | + | 962 | + |
242 | +static void bcm2835_powermgt_init(Object *obj) | 963 | +static Property efuse_ctrl_props[] = { |
243 | +{ | 964 | + DEFINE_PROP_LINK("efuse", |
244 | + BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj); | 965 | + XlnxVersalEFuseCtrl, efuse, |
245 | + | 966 | + TYPE_XLNX_EFUSE, XlnxEFuse *), |
246 | + memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s, | 967 | + DEFINE_PROP_ARRAY("pg0-lock", |
247 | + TYPE_BCM2835_POWERMGT, 0x200); | 968 | + XlnxVersalEFuseCtrl, extra_pg0_lock_n16, |
248 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); | 969 | + extra_pg0_lock_spec, qdev_prop_uint16, uint16_t), |
249 | +} | 970 | + |
250 | + | 971 | + DEFINE_PROP_END_OF_LIST(), |
251 | +static void bcm2835_powermgt_reset(DeviceState *dev) | 972 | +}; |
252 | +{ | 973 | + |
253 | + BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev); | 974 | +static void efuse_ctrl_class_init(ObjectClass *klass, void *data) |
254 | + | ||
255 | + /* https://elinux.org/BCM2835_registers#PM */ | ||
256 | + s->rstc = 0x00000102; | ||
257 | + s->rsts = 0x00001000; | ||
258 | + s->wdog = 0x00000000; | ||
259 | +} | ||
260 | + | ||
261 | +static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data) | ||
262 | +{ | 975 | +{ |
263 | + DeviceClass *dc = DEVICE_CLASS(klass); | 976 | + DeviceClass *dc = DEVICE_CLASS(klass); |
264 | + | 977 | + |
265 | + dc->reset = bcm2835_powermgt_reset; | 978 | + dc->reset = efuse_ctrl_reset; |
266 | + dc->vmsd = &vmstate_bcm2835_powermgt; | 979 | + dc->realize = efuse_ctrl_realize; |
267 | +} | 980 | + dc->vmsd = &vmstate_efuse_ctrl; |
268 | + | 981 | + device_class_set_props(dc, efuse_ctrl_props); |
269 | +static TypeInfo bcm2835_powermgt_info = { | 982 | +} |
270 | + .name = TYPE_BCM2835_POWERMGT, | 983 | + |
984 | +static const TypeInfo efuse_ctrl_info = { | ||
985 | + .name = TYPE_XLNX_VERSAL_EFUSE_CTRL, | ||
271 | + .parent = TYPE_SYS_BUS_DEVICE, | 986 | + .parent = TYPE_SYS_BUS_DEVICE, |
272 | + .instance_size = sizeof(BCM2835PowerMgtState), | 987 | + .instance_size = sizeof(XlnxVersalEFuseCtrl), |
273 | + .class_init = bcm2835_powermgt_class_init, | 988 | + .class_init = efuse_ctrl_class_init, |
274 | + .instance_init = bcm2835_powermgt_init, | 989 | + .instance_init = efuse_ctrl_init, |
275 | +}; | 990 | +}; |
276 | + | 991 | + |
277 | +static void bcm2835_powermgt_register_types(void) | 992 | +static void efuse_ctrl_register_types(void) |
278 | +{ | 993 | +{ |
279 | + type_register_static(&bcm2835_powermgt_info); | 994 | + type_register_static(&efuse_ctrl_info); |
280 | +} | 995 | +} |
281 | + | 996 | + |
282 | +type_init(bcm2835_powermgt_register_types) | 997 | +type_init(efuse_ctrl_register_types) |
283 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | 998 | + |
999 | +/* | ||
1000 | + * Retrieve a row, with unreadable bits returned as 0. | ||
1001 | + */ | ||
1002 | +uint32_t xlnx_versal_efuse_read_row(XlnxEFuse *efuse, | ||
1003 | + uint32_t bit, bool *denied) | ||
1004 | +{ | ||
1005 | + bool dummy; | ||
1006 | + | ||
1007 | + if (!denied) { | ||
1008 | + denied = &dummy; | ||
1009 | + } | ||
1010 | + | ||
1011 | + if (bit >= EFUSE_RD_BLOCKED_START && bit <= EFUSE_RD_BLOCKED_END) { | ||
1012 | + *denied = true; | ||
1013 | + return 0; | ||
1014 | + } | ||
1015 | + | ||
1016 | + *denied = false; | ||
1017 | + return xlnx_efuse_get_row(efuse, bit); | ||
1018 | +} | ||
1019 | diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig | ||
284 | index XXXXXXX..XXXXXXX 100644 | 1020 | index XXXXXXX..XXXXXXX 100644 |
285 | --- a/hw/misc/meson.build | 1021 | --- a/hw/nvram/Kconfig |
286 | +++ b/hw/misc/meson.build | 1022 | +++ b/hw/nvram/Kconfig |
287 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( | 1023 | @@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE_CRC |
288 | 'bcm2835_rng.c', | 1024 | config XLNX_EFUSE |
289 | 'bcm2835_thermal.c', | 1025 | bool |
290 | 'bcm2835_cprman.c', | 1026 | select XLNX_EFUSE_CRC |
291 | + 'bcm2835_powermgt.c', | 1027 | + |
292 | )) | 1028 | +config XLNX_EFUSE_VERSAL |
293 | softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) | 1029 | + bool |
294 | softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c')) | 1030 | + select XLNX_EFUSE |
1031 | diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build | ||
1032 | index XXXXXXX..XXXXXXX 100644 | ||
1033 | --- a/hw/nvram/meson.build | ||
1034 | +++ b/hw/nvram/meson.build | ||
1035 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c')) | ||
1036 | softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c')) | ||
1037 | softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_CRC', if_true: files('xlnx-efuse-crc.c')) | ||
1038 | softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c')) | ||
1039 | +softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files( | ||
1040 | + 'xlnx-versal-efuse-cache.c', | ||
1041 | + 'xlnx-versal-efuse-ctrl.c')) | ||
1042 | |||
1043 | specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c')) | ||
295 | -- | 1044 | -- |
296 | 2.20.1 | 1045 | 2.20.1 |
297 | 1046 | ||
298 | 1047 | diff view generated by jsdifflib |
1 | From: Patrick Venture <venture@google.com> | 1 | From: Tong Ho <tong.ho@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | Add line item reference to quanta-gbs-bmc machine. | 3 | This implements the Xilinx ZynqMP eFuse, an one-time |
4 | field-programmable non-volatile storage device. There is | ||
5 | only one such device in the Xilinx ZynqMP product family. | ||
4 | 6 | ||
5 | Signed-off-by: Patrick Venture <venture@google.com> | 7 | Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 8 | Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> |
7 | Message-id: 20210615192848.1065297-3-venture@google.com | 9 | |
8 | [PMM: fixed underline Sphinx warning] | 10 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
11 | Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | ||
12 | Signed-off-by: Tong Ho <tong.ho@xilinx.com> | ||
13 | Message-id: 20210917052400.1249094-4-tong.ho@xilinx.com | ||
14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 16 | --- |
11 | docs/system/arm/nuvoton.rst | 5 +++-- | 17 | include/hw/nvram/xlnx-zynqmp-efuse.h | 44 ++ |
12 | 1 file changed, 3 insertions(+), 2 deletions(-) | 18 | hw/nvram/xlnx-zynqmp-efuse.c | 855 +++++++++++++++++++++++++++ |
19 | hw/nvram/Kconfig | 4 + | ||
20 | hw/nvram/meson.build | 2 + | ||
21 | 4 files changed, 905 insertions(+) | ||
22 | create mode 100644 include/hw/nvram/xlnx-zynqmp-efuse.h | ||
23 | create mode 100644 hw/nvram/xlnx-zynqmp-efuse.c | ||
13 | 24 | ||
14 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst | 25 | diff --git a/include/hw/nvram/xlnx-zynqmp-efuse.h b/include/hw/nvram/xlnx-zynqmp-efuse.h |
26 | new file mode 100644 | ||
27 | index XXXXXXX..XXXXXXX | ||
28 | --- /dev/null | ||
29 | +++ b/include/hw/nvram/xlnx-zynqmp-efuse.h | ||
30 | @@ -XXX,XX +XXX,XX @@ | ||
31 | +/* | ||
32 | + * Copyright (c) 2021 Xilinx Inc. | ||
33 | + * | ||
34 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
35 | + * of this software and associated documentation files (the "Software"), to deal | ||
36 | + * in the Software without restriction, including without limitation the rights | ||
37 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
38 | + * copies of the Software, and to permit persons to whom the Software is | ||
39 | + * furnished to do so, subject to the following conditions: | ||
40 | + * | ||
41 | + * The above copyright notice and this permission notice shall be included in | ||
42 | + * all copies or substantial portions of the Software. | ||
43 | + * | ||
44 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
45 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
46 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
47 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
48 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
49 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
50 | + * THE SOFTWARE. | ||
51 | + */ | ||
52 | +#ifndef XLNX_ZYNQMP_EFUSE_H | ||
53 | +#define XLNX_ZYNQMP_EFUSE_H | ||
54 | + | ||
55 | +#include "hw/irq.h" | ||
56 | +#include "hw/sysbus.h" | ||
57 | +#include "hw/register.h" | ||
58 | +#include "hw/nvram/xlnx-efuse.h" | ||
59 | + | ||
60 | +#define XLNX_ZYNQMP_EFUSE_R_MAX ((0x10fc / 4) + 1) | ||
61 | + | ||
62 | +#define TYPE_XLNX_ZYNQMP_EFUSE "xlnx,zynqmp-efuse" | ||
63 | +OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPEFuse, XLNX_ZYNQMP_EFUSE); | ||
64 | + | ||
65 | +struct XlnxZynqMPEFuse { | ||
66 | + SysBusDevice parent_obj; | ||
67 | + qemu_irq irq; | ||
68 | + | ||
69 | + XlnxEFuse *efuse; | ||
70 | + uint32_t regs[XLNX_ZYNQMP_EFUSE_R_MAX]; | ||
71 | + RegisterInfo regs_info[XLNX_ZYNQMP_EFUSE_R_MAX]; | ||
72 | +}; | ||
73 | + | ||
74 | +#endif | ||
75 | diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c | ||
76 | new file mode 100644 | ||
77 | index XXXXXXX..XXXXXXX | ||
78 | --- /dev/null | ||
79 | +++ b/hw/nvram/xlnx-zynqmp-efuse.c | ||
80 | @@ -XXX,XX +XXX,XX @@ | ||
81 | +/* | ||
82 | + * QEMU model of the ZynqMP eFuse | ||
83 | + * | ||
84 | + * Copyright (c) 2015 Xilinx Inc. | ||
85 | + * | ||
86 | + * Written by Edgar E. Iglesias <edgari@xilinx.com> | ||
87 | + * | ||
88 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
89 | + * of this software and associated documentation files (the "Software"), to deal | ||
90 | + * in the Software without restriction, including without limitation the rights | ||
91 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
92 | + * copies of the Software, and to permit persons to whom the Software is | ||
93 | + * furnished to do so, subject to the following conditions: | ||
94 | + * | ||
95 | + * The above copyright notice and this permission notice shall be included in | ||
96 | + * all copies or substantial portions of the Software. | ||
97 | + * | ||
98 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
99 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
100 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
101 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
102 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
103 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
104 | + * THE SOFTWARE. | ||
105 | + */ | ||
106 | + | ||
107 | +#include "qemu/osdep.h" | ||
108 | +#include "hw/nvram/xlnx-zynqmp-efuse.h" | ||
109 | + | ||
110 | +#include "qemu/log.h" | ||
111 | +#include "qapi/error.h" | ||
112 | +#include "migration/vmstate.h" | ||
113 | +#include "hw/qdev-properties.h" | ||
114 | + | ||
115 | +#ifndef ZYNQMP_EFUSE_ERR_DEBUG | ||
116 | +#define ZYNQMP_EFUSE_ERR_DEBUG 0 | ||
117 | +#endif | ||
118 | + | ||
119 | +REG32(WR_LOCK, 0x0) | ||
120 | + FIELD(WR_LOCK, LOCK, 0, 16) | ||
121 | +REG32(CFG, 0x4) | ||
122 | + FIELD(CFG, SLVERR_ENABLE, 5, 1) | ||
123 | + FIELD(CFG, MARGIN_RD, 2, 2) | ||
124 | + FIELD(CFG, PGM_EN, 1, 1) | ||
125 | + FIELD(CFG, EFUSE_CLK_SEL, 0, 1) | ||
126 | +REG32(STATUS, 0x8) | ||
127 | + FIELD(STATUS, AES_CRC_PASS, 7, 1) | ||
128 | + FIELD(STATUS, AES_CRC_DONE, 6, 1) | ||
129 | + FIELD(STATUS, CACHE_DONE, 5, 1) | ||
130 | + FIELD(STATUS, CACHE_LOAD, 4, 1) | ||
131 | + FIELD(STATUS, EFUSE_3_TBIT, 2, 1) | ||
132 | + FIELD(STATUS, EFUSE_2_TBIT, 1, 1) | ||
133 | + FIELD(STATUS, EFUSE_0_TBIT, 0, 1) | ||
134 | +REG32(EFUSE_PGM_ADDR, 0xc) | ||
135 | + FIELD(EFUSE_PGM_ADDR, EFUSE, 11, 2) | ||
136 | + FIELD(EFUSE_PGM_ADDR, ROW, 5, 6) | ||
137 | + FIELD(EFUSE_PGM_ADDR, COLUMN, 0, 5) | ||
138 | +REG32(EFUSE_RD_ADDR, 0x10) | ||
139 | + FIELD(EFUSE_RD_ADDR, EFUSE, 11, 2) | ||
140 | + FIELD(EFUSE_RD_ADDR, ROW, 5, 6) | ||
141 | +REG32(EFUSE_RD_DATA, 0x14) | ||
142 | +REG32(TPGM, 0x18) | ||
143 | + FIELD(TPGM, VALUE, 0, 16) | ||
144 | +REG32(TRD, 0x1c) | ||
145 | + FIELD(TRD, VALUE, 0, 8) | ||
146 | +REG32(TSU_H_PS, 0x20) | ||
147 | + FIELD(TSU_H_PS, VALUE, 0, 8) | ||
148 | +REG32(TSU_H_PS_CS, 0x24) | ||
149 | + FIELD(TSU_H_PS_CS, VALUE, 0, 8) | ||
150 | +REG32(TSU_H_CS, 0x2c) | ||
151 | + FIELD(TSU_H_CS, VALUE, 0, 4) | ||
152 | +REG32(EFUSE_ISR, 0x30) | ||
153 | + FIELD(EFUSE_ISR, APB_SLVERR, 31, 1) | ||
154 | + FIELD(EFUSE_ISR, CACHE_ERROR, 4, 1) | ||
155 | + FIELD(EFUSE_ISR, RD_ERROR, 3, 1) | ||
156 | + FIELD(EFUSE_ISR, RD_DONE, 2, 1) | ||
157 | + FIELD(EFUSE_ISR, PGM_ERROR, 1, 1) | ||
158 | + FIELD(EFUSE_ISR, PGM_DONE, 0, 1) | ||
159 | +REG32(EFUSE_IMR, 0x34) | ||
160 | + FIELD(EFUSE_IMR, APB_SLVERR, 31, 1) | ||
161 | + FIELD(EFUSE_IMR, CACHE_ERROR, 4, 1) | ||
162 | + FIELD(EFUSE_IMR, RD_ERROR, 3, 1) | ||
163 | + FIELD(EFUSE_IMR, RD_DONE, 2, 1) | ||
164 | + FIELD(EFUSE_IMR, PGM_ERROR, 1, 1) | ||
165 | + FIELD(EFUSE_IMR, PGM_DONE, 0, 1) | ||
166 | +REG32(EFUSE_IER, 0x38) | ||
167 | + FIELD(EFUSE_IER, APB_SLVERR, 31, 1) | ||
168 | + FIELD(EFUSE_IER, CACHE_ERROR, 4, 1) | ||
169 | + FIELD(EFUSE_IER, RD_ERROR, 3, 1) | ||
170 | + FIELD(EFUSE_IER, RD_DONE, 2, 1) | ||
171 | + FIELD(EFUSE_IER, PGM_ERROR, 1, 1) | ||
172 | + FIELD(EFUSE_IER, PGM_DONE, 0, 1) | ||
173 | +REG32(EFUSE_IDR, 0x3c) | ||
174 | + FIELD(EFUSE_IDR, APB_SLVERR, 31, 1) | ||
175 | + FIELD(EFUSE_IDR, CACHE_ERROR, 4, 1) | ||
176 | + FIELD(EFUSE_IDR, RD_ERROR, 3, 1) | ||
177 | + FIELD(EFUSE_IDR, RD_DONE, 2, 1) | ||
178 | + FIELD(EFUSE_IDR, PGM_ERROR, 1, 1) | ||
179 | + FIELD(EFUSE_IDR, PGM_DONE, 0, 1) | ||
180 | +REG32(EFUSE_CACHE_LOAD, 0x40) | ||
181 | + FIELD(EFUSE_CACHE_LOAD, LOAD, 0, 1) | ||
182 | +REG32(EFUSE_PGM_LOCK, 0x44) | ||
183 | + FIELD(EFUSE_PGM_LOCK, SPK_ID_LOCK, 0, 1) | ||
184 | +REG32(EFUSE_AES_CRC, 0x48) | ||
185 | +REG32(EFUSE_TBITS_PRGRMG_EN, 0x100) | ||
186 | + FIELD(EFUSE_TBITS_PRGRMG_EN, TBITS_PRGRMG_EN, 3, 1) | ||
187 | +REG32(DNA_0, 0x100c) | ||
188 | +REG32(DNA_1, 0x1010) | ||
189 | +REG32(DNA_2, 0x1014) | ||
190 | +REG32(IPDISABLE, 0x1018) | ||
191 | + FIELD(IPDISABLE, VCU_DIS, 8, 1) | ||
192 | + FIELD(IPDISABLE, GPU_DIS, 5, 1) | ||
193 | + FIELD(IPDISABLE, APU3_DIS, 3, 1) | ||
194 | + FIELD(IPDISABLE, APU2_DIS, 2, 1) | ||
195 | + FIELD(IPDISABLE, APU1_DIS, 1, 1) | ||
196 | + FIELD(IPDISABLE, APU0_DIS, 0, 1) | ||
197 | +REG32(SYSOSC_CTRL, 0x101c) | ||
198 | + FIELD(SYSOSC_CTRL, SYSOSC_EN, 0, 1) | ||
199 | +REG32(USER_0, 0x1020) | ||
200 | +REG32(USER_1, 0x1024) | ||
201 | +REG32(USER_2, 0x1028) | ||
202 | +REG32(USER_3, 0x102c) | ||
203 | +REG32(USER_4, 0x1030) | ||
204 | +REG32(USER_5, 0x1034) | ||
205 | +REG32(USER_6, 0x1038) | ||
206 | +REG32(USER_7, 0x103c) | ||
207 | +REG32(MISC_USER_CTRL, 0x1040) | ||
208 | + FIELD(MISC_USER_CTRL, FPD_SC_EN_0, 14, 1) | ||
209 | + FIELD(MISC_USER_CTRL, LPD_SC_EN_0, 11, 1) | ||
210 | + FIELD(MISC_USER_CTRL, LBIST_EN, 10, 1) | ||
211 | + FIELD(MISC_USER_CTRL, USR_WRLK_7, 7, 1) | ||
212 | + FIELD(MISC_USER_CTRL, USR_WRLK_6, 6, 1) | ||
213 | + FIELD(MISC_USER_CTRL, USR_WRLK_5, 5, 1) | ||
214 | + FIELD(MISC_USER_CTRL, USR_WRLK_4, 4, 1) | ||
215 | + FIELD(MISC_USER_CTRL, USR_WRLK_3, 3, 1) | ||
216 | + FIELD(MISC_USER_CTRL, USR_WRLK_2, 2, 1) | ||
217 | + FIELD(MISC_USER_CTRL, USR_WRLK_1, 1, 1) | ||
218 | + FIELD(MISC_USER_CTRL, USR_WRLK_0, 0, 1) | ||
219 | +REG32(ROM_RSVD, 0x1044) | ||
220 | + FIELD(ROM_RSVD, PBR_BOOT_ERROR, 0, 3) | ||
221 | +REG32(PUF_CHASH, 0x1050) | ||
222 | +REG32(PUF_MISC, 0x1054) | ||
223 | + FIELD(PUF_MISC, REGISTER_DIS, 31, 1) | ||
224 | + FIELD(PUF_MISC, SYN_WRLK, 30, 1) | ||
225 | + FIELD(PUF_MISC, SYN_INVLD, 29, 1) | ||
226 | + FIELD(PUF_MISC, TEST2_DIS, 28, 1) | ||
227 | + FIELD(PUF_MISC, UNUSED27, 27, 1) | ||
228 | + FIELD(PUF_MISC, UNUSED26, 26, 1) | ||
229 | + FIELD(PUF_MISC, UNUSED25, 25, 1) | ||
230 | + FIELD(PUF_MISC, UNUSED24, 24, 1) | ||
231 | + FIELD(PUF_MISC, AUX, 0, 24) | ||
232 | +REG32(SEC_CTRL, 0x1058) | ||
233 | + FIELD(SEC_CTRL, PPK1_INVLD, 30, 2) | ||
234 | + FIELD(SEC_CTRL, PPK1_WRLK, 29, 1) | ||
235 | + FIELD(SEC_CTRL, PPK0_INVLD, 27, 2) | ||
236 | + FIELD(SEC_CTRL, PPK0_WRLK, 26, 1) | ||
237 | + FIELD(SEC_CTRL, RSA_EN, 11, 15) | ||
238 | + FIELD(SEC_CTRL, SEC_LOCK, 10, 1) | ||
239 | + FIELD(SEC_CTRL, PROG_GATE_2, 9, 1) | ||
240 | + FIELD(SEC_CTRL, PROG_GATE_1, 8, 1) | ||
241 | + FIELD(SEC_CTRL, PROG_GATE_0, 7, 1) | ||
242 | + FIELD(SEC_CTRL, DFT_DIS, 6, 1) | ||
243 | + FIELD(SEC_CTRL, JTAG_DIS, 5, 1) | ||
244 | + FIELD(SEC_CTRL, ERROR_DIS, 4, 1) | ||
245 | + FIELD(SEC_CTRL, BBRAM_DIS, 3, 1) | ||
246 | + FIELD(SEC_CTRL, ENC_ONLY, 2, 1) | ||
247 | + FIELD(SEC_CTRL, AES_WRLK, 1, 1) | ||
248 | + FIELD(SEC_CTRL, AES_RDLK, 0, 1) | ||
249 | +REG32(SPK_ID, 0x105c) | ||
250 | +REG32(PPK0_0, 0x10a0) | ||
251 | +REG32(PPK0_1, 0x10a4) | ||
252 | +REG32(PPK0_2, 0x10a8) | ||
253 | +REG32(PPK0_3, 0x10ac) | ||
254 | +REG32(PPK0_4, 0x10b0) | ||
255 | +REG32(PPK0_5, 0x10b4) | ||
256 | +REG32(PPK0_6, 0x10b8) | ||
257 | +REG32(PPK0_7, 0x10bc) | ||
258 | +REG32(PPK0_8, 0x10c0) | ||
259 | +REG32(PPK0_9, 0x10c4) | ||
260 | +REG32(PPK0_10, 0x10c8) | ||
261 | +REG32(PPK0_11, 0x10cc) | ||
262 | +REG32(PPK1_0, 0x10d0) | ||
263 | +REG32(PPK1_1, 0x10d4) | ||
264 | +REG32(PPK1_2, 0x10d8) | ||
265 | +REG32(PPK1_3, 0x10dc) | ||
266 | +REG32(PPK1_4, 0x10e0) | ||
267 | +REG32(PPK1_5, 0x10e4) | ||
268 | +REG32(PPK1_6, 0x10e8) | ||
269 | +REG32(PPK1_7, 0x10ec) | ||
270 | +REG32(PPK1_8, 0x10f0) | ||
271 | +REG32(PPK1_9, 0x10f4) | ||
272 | +REG32(PPK1_10, 0x10f8) | ||
273 | +REG32(PPK1_11, 0x10fc) | ||
274 | + | ||
275 | +#define BIT_POS(ROW, COLUMN) (ROW * 32 + COLUMN) | ||
276 | +#define R_MAX (R_PPK1_11 + 1) | ||
277 | + | ||
278 | +/* #define EFUSE_XOSC 26 */ | ||
279 | + | ||
280 | +/* | ||
281 | + * eFUSE layout references: | ||
282 | + * ZynqMP: UG1085 (v2.1) August 21, 2019, p.277, Table 12-13 | ||
283 | + */ | ||
284 | +#define EFUSE_AES_RDLK BIT_POS(22, 0) | ||
285 | +#define EFUSE_AES_WRLK BIT_POS(22, 1) | ||
286 | +#define EFUSE_ENC_ONLY BIT_POS(22, 2) | ||
287 | +#define EFUSE_BBRAM_DIS BIT_POS(22, 3) | ||
288 | +#define EFUSE_ERROR_DIS BIT_POS(22, 4) | ||
289 | +#define EFUSE_JTAG_DIS BIT_POS(22, 5) | ||
290 | +#define EFUSE_DFT_DIS BIT_POS(22, 6) | ||
291 | +#define EFUSE_PROG_GATE_0 BIT_POS(22, 7) | ||
292 | +#define EFUSE_PROG_GATE_1 BIT_POS(22, 7) | ||
293 | +#define EFUSE_PROG_GATE_2 BIT_POS(22, 9) | ||
294 | +#define EFUSE_SEC_LOCK BIT_POS(22, 10) | ||
295 | +#define EFUSE_RSA_EN BIT_POS(22, 11) | ||
296 | +#define EFUSE_RSA_EN14 BIT_POS(22, 25) | ||
297 | +#define EFUSE_PPK0_WRLK BIT_POS(22, 26) | ||
298 | +#define EFUSE_PPK0_INVLD BIT_POS(22, 27) | ||
299 | +#define EFUSE_PPK0_INVLD_1 BIT_POS(22, 28) | ||
300 | +#define EFUSE_PPK1_WRLK BIT_POS(22, 29) | ||
301 | +#define EFUSE_PPK1_INVLD BIT_POS(22, 30) | ||
302 | +#define EFUSE_PPK1_INVLD_1 BIT_POS(22, 31) | ||
303 | + | ||
304 | +/* Areas. */ | ||
305 | +#define EFUSE_TRIM_START BIT_POS(1, 0) | ||
306 | +#define EFUSE_TRIM_END BIT_POS(1, 30) | ||
307 | +#define EFUSE_DNA_START BIT_POS(3, 0) | ||
308 | +#define EFUSE_DNA_END BIT_POS(5, 31) | ||
309 | +#define EFUSE_AES_START BIT_POS(24, 0) | ||
310 | +#define EFUSE_AES_END BIT_POS(31, 31) | ||
311 | +#define EFUSE_ROM_START BIT_POS(17, 0) | ||
312 | +#define EFUSE_ROM_END BIT_POS(17, 31) | ||
313 | +#define EFUSE_IPDIS_START BIT_POS(6, 0) | ||
314 | +#define EFUSE_IPDIS_END BIT_POS(6, 31) | ||
315 | +#define EFUSE_USER_START BIT_POS(8, 0) | ||
316 | +#define EFUSE_USER_END BIT_POS(15, 31) | ||
317 | +#define EFUSE_BISR_START BIT_POS(32, 0) | ||
318 | +#define EFUSE_BISR_END BIT_POS(39, 31) | ||
319 | + | ||
320 | +#define EFUSE_USER_CTRL_START BIT_POS(16, 0) | ||
321 | +#define EFUSE_USER_CTRL_END BIT_POS(16, 16) | ||
322 | +#define EFUSE_USER_CTRL_MASK ((uint32_t)MAKE_64BIT_MASK(0, 17)) | ||
323 | + | ||
324 | +#define EFUSE_PUF_CHASH_START BIT_POS(20, 0) | ||
325 | +#define EFUSE_PUF_CHASH_END BIT_POS(20, 31) | ||
326 | +#define EFUSE_PUF_MISC_START BIT_POS(21, 0) | ||
327 | +#define EFUSE_PUF_MISC_END BIT_POS(21, 31) | ||
328 | +#define EFUSE_PUF_SYN_WRLK BIT_POS(21, 30) | ||
329 | + | ||
330 | +#define EFUSE_SPK_START BIT_POS(23, 0) | ||
331 | +#define EFUSE_SPK_END BIT_POS(23, 31) | ||
332 | + | ||
333 | +#define EFUSE_PPK0_START BIT_POS(40, 0) | ||
334 | +#define EFUSE_PPK0_END BIT_POS(51, 31) | ||
335 | +#define EFUSE_PPK1_START BIT_POS(52, 0) | ||
336 | +#define EFUSE_PPK1_END BIT_POS(63, 31) | ||
337 | + | ||
338 | +#define EFUSE_CACHE_FLD(s, reg, field) \ | ||
339 | + ARRAY_FIELD_DP32((s)->regs, reg, field, \ | ||
340 | + (xlnx_efuse_get_row((s->efuse), EFUSE_ ## field) \ | ||
341 | + >> (EFUSE_ ## field % 32))) | ||
342 | + | ||
343 | +#define EFUSE_CACHE_BIT(s, reg, field) \ | ||
344 | + ARRAY_FIELD_DP32((s)->regs, reg, field, xlnx_efuse_get_bit((s->efuse), \ | ||
345 | + EFUSE_ ## field)) | ||
346 | + | ||
347 | +#define FBIT_UNKNOWN (~0) | ||
348 | + | ||
349 | +QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxZynqMPEFuse *)0)->regs)); | ||
350 | + | ||
351 | +static void update_tbit_status(XlnxZynqMPEFuse *s) | ||
352 | +{ | ||
353 | + unsigned int check = xlnx_efuse_tbits_check(s->efuse); | ||
354 | + uint32_t val = s->regs[R_STATUS]; | ||
355 | + | ||
356 | + val = FIELD_DP32(val, STATUS, EFUSE_0_TBIT, !!(check & (1 << 0))); | ||
357 | + val = FIELD_DP32(val, STATUS, EFUSE_2_TBIT, !!(check & (1 << 1))); | ||
358 | + val = FIELD_DP32(val, STATUS, EFUSE_3_TBIT, !!(check & (1 << 2))); | ||
359 | + | ||
360 | + s->regs[R_STATUS] = val; | ||
361 | +} | ||
362 | + | ||
363 | +/* Update the u32 array from efuse bits. Slow but simple approach. */ | ||
364 | +static void cache_sync_u32(XlnxZynqMPEFuse *s, unsigned int r_start, | ||
365 | + unsigned int f_start, unsigned int f_end, | ||
366 | + unsigned int f_written) | ||
367 | +{ | ||
368 | + uint32_t *u32 = &s->regs[r_start]; | ||
369 | + unsigned int fbit, wbits = 0, u32_off = 0; | ||
370 | + | ||
371 | + /* Avoid working on bits that are not relevant. */ | ||
372 | + if (f_written != FBIT_UNKNOWN | ||
373 | + && (f_written < f_start || f_written > f_end)) { | ||
374 | + return; | ||
375 | + } | ||
376 | + | ||
377 | + for (fbit = f_start; fbit <= f_end; fbit++, wbits++) { | ||
378 | + if (wbits == 32) { | ||
379 | + /* Update the key offset. */ | ||
380 | + u32_off += 1; | ||
381 | + wbits = 0; | ||
382 | + } | ||
383 | + u32[u32_off] |= xlnx_efuse_get_bit(s->efuse, fbit) << wbits; | ||
384 | + } | ||
385 | +} | ||
386 | + | ||
387 | +/* | ||
388 | + * Keep the syncs in bit order so we can bail out for the | ||
389 | + * slower ones. | ||
390 | + */ | ||
391 | +static void zynqmp_efuse_sync_cache(XlnxZynqMPEFuse *s, unsigned int bit) | ||
392 | +{ | ||
393 | + EFUSE_CACHE_BIT(s, SEC_CTRL, AES_RDLK); | ||
394 | + EFUSE_CACHE_BIT(s, SEC_CTRL, AES_WRLK); | ||
395 | + EFUSE_CACHE_BIT(s, SEC_CTRL, ENC_ONLY); | ||
396 | + EFUSE_CACHE_BIT(s, SEC_CTRL, BBRAM_DIS); | ||
397 | + EFUSE_CACHE_BIT(s, SEC_CTRL, ERROR_DIS); | ||
398 | + EFUSE_CACHE_BIT(s, SEC_CTRL, JTAG_DIS); | ||
399 | + EFUSE_CACHE_BIT(s, SEC_CTRL, DFT_DIS); | ||
400 | + EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_0); | ||
401 | + EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_1); | ||
402 | + EFUSE_CACHE_BIT(s, SEC_CTRL, PROG_GATE_2); | ||
403 | + EFUSE_CACHE_BIT(s, SEC_CTRL, SEC_LOCK); | ||
404 | + EFUSE_CACHE_BIT(s, SEC_CTRL, PPK0_WRLK); | ||
405 | + EFUSE_CACHE_BIT(s, SEC_CTRL, PPK1_WRLK); | ||
406 | + | ||
407 | + EFUSE_CACHE_FLD(s, SEC_CTRL, RSA_EN); | ||
408 | + EFUSE_CACHE_FLD(s, SEC_CTRL, PPK0_INVLD); | ||
409 | + EFUSE_CACHE_FLD(s, SEC_CTRL, PPK1_INVLD); | ||
410 | + | ||
411 | + /* Update the tbits. */ | ||
412 | + update_tbit_status(s); | ||
413 | + | ||
414 | + /* Sync the various areas. */ | ||
415 | + s->regs[R_MISC_USER_CTRL] = xlnx_efuse_get_row(s->efuse, | ||
416 | + EFUSE_USER_CTRL_START) | ||
417 | + & EFUSE_USER_CTRL_MASK; | ||
418 | + s->regs[R_PUF_CHASH] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_CHASH_START); | ||
419 | + s->regs[R_PUF_MISC] = xlnx_efuse_get_row(s->efuse, EFUSE_PUF_MISC_START); | ||
420 | + | ||
421 | + cache_sync_u32(s, R_DNA_0, EFUSE_DNA_START, EFUSE_DNA_END, bit); | ||
422 | + | ||
423 | + if (bit < EFUSE_AES_START) { | ||
424 | + return; | ||
425 | + } | ||
426 | + | ||
427 | + cache_sync_u32(s, R_ROM_RSVD, EFUSE_ROM_START, EFUSE_ROM_END, bit); | ||
428 | + cache_sync_u32(s, R_IPDISABLE, EFUSE_IPDIS_START, EFUSE_IPDIS_END, bit); | ||
429 | + cache_sync_u32(s, R_USER_0, EFUSE_USER_START, EFUSE_USER_END, bit); | ||
430 | + cache_sync_u32(s, R_SPK_ID, EFUSE_SPK_START, EFUSE_SPK_END, bit); | ||
431 | + cache_sync_u32(s, R_PPK0_0, EFUSE_PPK0_START, EFUSE_PPK0_END, bit); | ||
432 | + cache_sync_u32(s, R_PPK1_0, EFUSE_PPK1_START, EFUSE_PPK1_END, bit); | ||
433 | +} | ||
434 | + | ||
435 | +static void zynqmp_efuse_update_irq(XlnxZynqMPEFuse *s) | ||
436 | +{ | ||
437 | + bool pending = s->regs[R_EFUSE_ISR] & s->regs[R_EFUSE_IMR]; | ||
438 | + qemu_set_irq(s->irq, pending); | ||
439 | +} | ||
440 | + | ||
441 | +static void zynqmp_efuse_isr_postw(RegisterInfo *reg, uint64_t val64) | ||
442 | +{ | ||
443 | + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); | ||
444 | + zynqmp_efuse_update_irq(s); | ||
445 | +} | ||
446 | + | ||
447 | +static uint64_t zynqmp_efuse_ier_prew(RegisterInfo *reg, uint64_t val64) | ||
448 | +{ | ||
449 | + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); | ||
450 | + uint32_t val = val64; | ||
451 | + | ||
452 | + s->regs[R_EFUSE_IMR] |= val; | ||
453 | + zynqmp_efuse_update_irq(s); | ||
454 | + return 0; | ||
455 | +} | ||
456 | + | ||
457 | +static uint64_t zynqmp_efuse_idr_prew(RegisterInfo *reg, uint64_t val64) | ||
458 | +{ | ||
459 | + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); | ||
460 | + uint32_t val = val64; | ||
461 | + | ||
462 | + s->regs[R_EFUSE_IMR] &= ~val; | ||
463 | + zynqmp_efuse_update_irq(s); | ||
464 | + return 0; | ||
465 | +} | ||
466 | + | ||
467 | +static void zynqmp_efuse_pgm_addr_postw(RegisterInfo *reg, uint64_t val64) | ||
468 | +{ | ||
469 | + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); | ||
470 | + unsigned bit = val64; | ||
471 | + unsigned page = FIELD_EX32(bit, EFUSE_PGM_ADDR, EFUSE); | ||
472 | + bool puf_prot = false; | ||
473 | + const char *errmsg = NULL; | ||
474 | + | ||
475 | + /* Allow only valid array, and adjust for skipped array 1 */ | ||
476 | + switch (page) { | ||
477 | + case 0: | ||
478 | + break; | ||
479 | + case 2 ... 3: | ||
480 | + bit = FIELD_DP32(bit, EFUSE_PGM_ADDR, EFUSE, page - 1); | ||
481 | + puf_prot = xlnx_efuse_get_bit(s->efuse, EFUSE_PUF_SYN_WRLK); | ||
482 | + break; | ||
483 | + default: | ||
484 | + errmsg = "Invalid address"; | ||
485 | + goto pgm_done; | ||
486 | + } | ||
487 | + | ||
488 | + if (ARRAY_FIELD_EX32(s->regs, WR_LOCK, LOCK)) { | ||
489 | + errmsg = "Array write-locked"; | ||
490 | + goto pgm_done; | ||
491 | + } | ||
492 | + | ||
493 | + if (!ARRAY_FIELD_EX32(s->regs, CFG, PGM_EN)) { | ||
494 | + errmsg = "Array pgm-disabled"; | ||
495 | + goto pgm_done; | ||
496 | + } | ||
497 | + | ||
498 | + if (puf_prot) { | ||
499 | + errmsg = "PUF_HD-store write-locked"; | ||
500 | + goto pgm_done; | ||
501 | + } | ||
502 | + | ||
503 | + if (ARRAY_FIELD_EX32(s->regs, SEC_CTRL, AES_WRLK) | ||
504 | + && bit >= EFUSE_AES_START && bit <= EFUSE_AES_END) { | ||
505 | + errmsg = "AES key-store Write-locked"; | ||
506 | + goto pgm_done; | ||
507 | + } | ||
508 | + | ||
509 | + if (!xlnx_efuse_set_bit(s->efuse, bit)) { | ||
510 | + errmsg = "Write failed"; | ||
511 | + } | ||
512 | + | ||
513 | + pgm_done: | ||
514 | + if (!errmsg) { | ||
515 | + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 0); | ||
516 | + } else { | ||
517 | + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_ERROR, 1); | ||
518 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
519 | + "%s - eFuse write error: %s; addr=0x%x\n", | ||
520 | + object_get_canonical_path(OBJECT(s)), | ||
521 | + errmsg, (unsigned)val64); | ||
522 | + } | ||
523 | + | ||
524 | + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, PGM_DONE, 1); | ||
525 | + zynqmp_efuse_update_irq(s); | ||
526 | +} | ||
527 | + | ||
528 | +static void zynqmp_efuse_rd_addr_postw(RegisterInfo *reg, uint64_t val64) | ||
529 | +{ | ||
530 | + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); | ||
531 | + | ||
532 | + /* | ||
533 | + * Grant reads only to allowed bits; reference sources: | ||
534 | + * 1/ XilSKey - XilSKey_ZynqMp_EfusePs_ReadRow() | ||
535 | + * 2/ UG1085, v2.0, table 12-13 | ||
536 | + * (note: enumerates the masks as <first, last> per described in | ||
537 | + * references to avoid mental translation). | ||
538 | + */ | ||
539 | +#define COL_MASK(L_, H_) \ | ||
540 | + ((uint32_t)MAKE_64BIT_MASK((L_), (1 + (H_) - (L_)))) | ||
541 | + | ||
542 | + static const uint32_t ary0_col_mask[] = { | ||
543 | + /* XilSKey - XSK_ZYNQMP_EFUSEPS_TBITS_ROW */ | ||
544 | + [0] = COL_MASK(28, 31), | ||
545 | + | ||
546 | + /* XilSKey - XSK_ZYNQMP_EFUSEPS_USR{0:7}_FUSE_ROW */ | ||
547 | + [8] = COL_MASK(0, 31), [9] = COL_MASK(0, 31), | ||
548 | + [10] = COL_MASK(0, 31), [11] = COL_MASK(0, 31), | ||
549 | + [12] = COL_MASK(0, 31), [13] = COL_MASK(0, 31), | ||
550 | + [14] = COL_MASK(0, 31), [15] = COL_MASK(0, 31), | ||
551 | + | ||
552 | + /* XilSKey - XSK_ZYNQMP_EFUSEPS_MISC_USR_CTRL_ROW */ | ||
553 | + [16] = COL_MASK(0, 7) | COL_MASK(10, 16), | ||
554 | + | ||
555 | + /* XilSKey - XSK_ZYNQMP_EFUSEPS_PBR_BOOT_ERR_ROW */ | ||
556 | + [17] = COL_MASK(0, 2), | ||
557 | + | ||
558 | + /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_CHASH_ROW */ | ||
559 | + [20] = COL_MASK(0, 31), | ||
560 | + | ||
561 | + /* XilSKey - XSK_ZYNQMP_EFUSEPS_PUF_AUX_ROW */ | ||
562 | + [21] = COL_MASK(0, 23) | COL_MASK(29, 31), | ||
563 | + | ||
564 | + /* XilSKey - XSK_ZYNQMP_EFUSEPS_SEC_CTRL_ROW */ | ||
565 | + [22] = COL_MASK(0, 31), | ||
566 | + | ||
567 | + /* XilSKey - XSK_ZYNQMP_EFUSEPS_SPK_ID_ROW */ | ||
568 | + [23] = COL_MASK(0, 31), | ||
569 | + | ||
570 | + /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK0_START_ROW */ | ||
571 | + [40] = COL_MASK(0, 31), [41] = COL_MASK(0, 31), | ||
572 | + [42] = COL_MASK(0, 31), [43] = COL_MASK(0, 31), | ||
573 | + [44] = COL_MASK(0, 31), [45] = COL_MASK(0, 31), | ||
574 | + [46] = COL_MASK(0, 31), [47] = COL_MASK(0, 31), | ||
575 | + [48] = COL_MASK(0, 31), [49] = COL_MASK(0, 31), | ||
576 | + [50] = COL_MASK(0, 31), [51] = COL_MASK(0, 31), | ||
577 | + | ||
578 | + /* XilSKey - XSK_ZYNQMP_EFUSEPS_PPK1_START_ROW */ | ||
579 | + [52] = COL_MASK(0, 31), [53] = COL_MASK(0, 31), | ||
580 | + [54] = COL_MASK(0, 31), [55] = COL_MASK(0, 31), | ||
581 | + [56] = COL_MASK(0, 31), [57] = COL_MASK(0, 31), | ||
582 | + [58] = COL_MASK(0, 31), [59] = COL_MASK(0, 31), | ||
583 | + [60] = COL_MASK(0, 31), [61] = COL_MASK(0, 31), | ||
584 | + [62] = COL_MASK(0, 31), [63] = COL_MASK(0, 31), | ||
585 | + }; | ||
586 | + | ||
587 | + uint32_t col_mask = COL_MASK(0, 31); | ||
588 | +#undef COL_MASK | ||
589 | + | ||
590 | + uint32_t efuse_idx = s->regs[R_EFUSE_RD_ADDR]; | ||
591 | + uint32_t efuse_ary = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, EFUSE); | ||
592 | + uint32_t efuse_row = FIELD_EX32(efuse_idx, EFUSE_RD_ADDR, ROW); | ||
593 | + | ||
594 | + switch (efuse_ary) { | ||
595 | + case 0: /* Various */ | ||
596 | + if (efuse_row >= ARRAY_SIZE(ary0_col_mask)) { | ||
597 | + goto denied; | ||
598 | + } | ||
599 | + | ||
600 | + col_mask = ary0_col_mask[efuse_row]; | ||
601 | + if (!col_mask) { | ||
602 | + goto denied; | ||
603 | + } | ||
604 | + break; | ||
605 | + case 2: /* PUF helper data, adjust for skipped array 1 */ | ||
606 | + case 3: | ||
607 | + val64 = FIELD_DP32(efuse_idx, EFUSE_RD_ADDR, EFUSE, efuse_ary - 1); | ||
608 | + break; | ||
609 | + default: | ||
610 | + goto denied; | ||
611 | + } | ||
612 | + | ||
613 | + s->regs[R_EFUSE_RD_DATA] = xlnx_efuse_get_row(s->efuse, val64) & col_mask; | ||
614 | + | ||
615 | + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 0); | ||
616 | + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 1); | ||
617 | + zynqmp_efuse_update_irq(s); | ||
618 | + return; | ||
619 | + | ||
620 | + denied: | ||
621 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
622 | + "%s: Denied efuse read from array %u, row %u\n", | ||
623 | + object_get_canonical_path(OBJECT(s)), | ||
624 | + efuse_ary, efuse_row); | ||
625 | + | ||
626 | + s->regs[R_EFUSE_RD_DATA] = 0; | ||
627 | + | ||
628 | + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_ERROR, 1); | ||
629 | + ARRAY_FIELD_DP32(s->regs, EFUSE_ISR, RD_DONE, 0); | ||
630 | + zynqmp_efuse_update_irq(s); | ||
631 | +} | ||
632 | + | ||
633 | +static void zynqmp_efuse_aes_crc_postw(RegisterInfo *reg, uint64_t val64) | ||
634 | +{ | ||
635 | + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); | ||
636 | + bool ok; | ||
637 | + | ||
638 | + ok = xlnx_efuse_k256_check(s->efuse, (uint32_t)val64, EFUSE_AES_START); | ||
639 | + | ||
640 | + ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_PASS, (ok ? 1 : 0)); | ||
641 | + ARRAY_FIELD_DP32(s->regs, STATUS, AES_CRC_DONE, 1); | ||
642 | + | ||
643 | + s->regs[R_EFUSE_AES_CRC] = 0; /* crc value is write-only */ | ||
644 | +} | ||
645 | + | ||
646 | +static uint64_t zynqmp_efuse_cache_load_prew(RegisterInfo *reg, | ||
647 | + uint64_t valu64) | ||
648 | +{ | ||
649 | + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(reg->opaque); | ||
650 | + | ||
651 | + if (valu64 & R_EFUSE_CACHE_LOAD_LOAD_MASK) { | ||
652 | + zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN); | ||
653 | + ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1); | ||
654 | + zynqmp_efuse_update_irq(s); | ||
655 | + } | ||
656 | + | ||
657 | + return 0; | ||
658 | +} | ||
659 | + | ||
660 | +static uint64_t zynqmp_efuse_wr_lock_prew(RegisterInfo *reg, uint64_t val) | ||
661 | +{ | ||
662 | + return val == 0xDF0D ? 0 : 1; | ||
663 | +} | ||
664 | + | ||
665 | +static RegisterAccessInfo zynqmp_efuse_regs_info[] = { | ||
666 | + { .name = "WR_LOCK", .addr = A_WR_LOCK, | ||
667 | + .reset = 0x1, | ||
668 | + .pre_write = zynqmp_efuse_wr_lock_prew, | ||
669 | + },{ .name = "CFG", .addr = A_CFG, | ||
670 | + },{ .name = "STATUS", .addr = A_STATUS, | ||
671 | + .rsvd = 0x8, | ||
672 | + .ro = 0xff, | ||
673 | + },{ .name = "EFUSE_PGM_ADDR", .addr = A_EFUSE_PGM_ADDR, | ||
674 | + .post_write = zynqmp_efuse_pgm_addr_postw | ||
675 | + },{ .name = "EFUSE_RD_ADDR", .addr = A_EFUSE_RD_ADDR, | ||
676 | + .rsvd = 0x1f, | ||
677 | + .post_write = zynqmp_efuse_rd_addr_postw, | ||
678 | + },{ .name = "EFUSE_RD_DATA", .addr = A_EFUSE_RD_DATA, | ||
679 | + .ro = 0xffffffff, | ||
680 | + },{ .name = "TPGM", .addr = A_TPGM, | ||
681 | + },{ .name = "TRD", .addr = A_TRD, | ||
682 | + .reset = 0x1b, | ||
683 | + },{ .name = "TSU_H_PS", .addr = A_TSU_H_PS, | ||
684 | + .reset = 0xff, | ||
685 | + },{ .name = "TSU_H_PS_CS", .addr = A_TSU_H_PS_CS, | ||
686 | + .reset = 0xb, | ||
687 | + },{ .name = "TSU_H_CS", .addr = A_TSU_H_CS, | ||
688 | + .reset = 0x7, | ||
689 | + },{ .name = "EFUSE_ISR", .addr = A_EFUSE_ISR, | ||
690 | + .rsvd = 0x7fffffe0, | ||
691 | + .w1c = 0x8000001f, | ||
692 | + .post_write = zynqmp_efuse_isr_postw, | ||
693 | + },{ .name = "EFUSE_IMR", .addr = A_EFUSE_IMR, | ||
694 | + .reset = 0x8000001f, | ||
695 | + .rsvd = 0x7fffffe0, | ||
696 | + .ro = 0xffffffff, | ||
697 | + },{ .name = "EFUSE_IER", .addr = A_EFUSE_IER, | ||
698 | + .rsvd = 0x7fffffe0, | ||
699 | + .pre_write = zynqmp_efuse_ier_prew, | ||
700 | + },{ .name = "EFUSE_IDR", .addr = A_EFUSE_IDR, | ||
701 | + .rsvd = 0x7fffffe0, | ||
702 | + .pre_write = zynqmp_efuse_idr_prew, | ||
703 | + },{ .name = "EFUSE_CACHE_LOAD", .addr = A_EFUSE_CACHE_LOAD, | ||
704 | + .pre_write = zynqmp_efuse_cache_load_prew, | ||
705 | + },{ .name = "EFUSE_PGM_LOCK", .addr = A_EFUSE_PGM_LOCK, | ||
706 | + },{ .name = "EFUSE_AES_CRC", .addr = A_EFUSE_AES_CRC, | ||
707 | + .post_write = zynqmp_efuse_aes_crc_postw, | ||
708 | + },{ .name = "EFUSE_TBITS_PRGRMG_EN", .addr = A_EFUSE_TBITS_PRGRMG_EN, | ||
709 | + .reset = R_EFUSE_TBITS_PRGRMG_EN_TBITS_PRGRMG_EN_MASK, | ||
710 | + },{ .name = "DNA_0", .addr = A_DNA_0, | ||
711 | + .ro = 0xffffffff, | ||
712 | + },{ .name = "DNA_1", .addr = A_DNA_1, | ||
713 | + .ro = 0xffffffff, | ||
714 | + },{ .name = "DNA_2", .addr = A_DNA_2, | ||
715 | + .ro = 0xffffffff, | ||
716 | + },{ .name = "IPDISABLE", .addr = A_IPDISABLE, | ||
717 | + .ro = 0xffffffff, | ||
718 | + },{ .name = "SYSOSC_CTRL", .addr = A_SYSOSC_CTRL, | ||
719 | + .ro = 0xffffffff, | ||
720 | + },{ .name = "USER_0", .addr = A_USER_0, | ||
721 | + .ro = 0xffffffff, | ||
722 | + },{ .name = "USER_1", .addr = A_USER_1, | ||
723 | + .ro = 0xffffffff, | ||
724 | + },{ .name = "USER_2", .addr = A_USER_2, | ||
725 | + .ro = 0xffffffff, | ||
726 | + },{ .name = "USER_3", .addr = A_USER_3, | ||
727 | + .ro = 0xffffffff, | ||
728 | + },{ .name = "USER_4", .addr = A_USER_4, | ||
729 | + .ro = 0xffffffff, | ||
730 | + },{ .name = "USER_5", .addr = A_USER_5, | ||
731 | + .ro = 0xffffffff, | ||
732 | + },{ .name = "USER_6", .addr = A_USER_6, | ||
733 | + .ro = 0xffffffff, | ||
734 | + },{ .name = "USER_7", .addr = A_USER_7, | ||
735 | + .ro = 0xffffffff, | ||
736 | + },{ .name = "MISC_USER_CTRL", .addr = A_MISC_USER_CTRL, | ||
737 | + .ro = 0xffffffff, | ||
738 | + },{ .name = "ROM_RSVD", .addr = A_ROM_RSVD, | ||
739 | + .ro = 0xffffffff, | ||
740 | + },{ .name = "PUF_CHASH", .addr = A_PUF_CHASH, | ||
741 | + .ro = 0xffffffff, | ||
742 | + },{ .name = "PUF_MISC", .addr = A_PUF_MISC, | ||
743 | + .ro = 0xffffffff, | ||
744 | + },{ .name = "SEC_CTRL", .addr = A_SEC_CTRL, | ||
745 | + .ro = 0xffffffff, | ||
746 | + },{ .name = "SPK_ID", .addr = A_SPK_ID, | ||
747 | + .ro = 0xffffffff, | ||
748 | + },{ .name = "PPK0_0", .addr = A_PPK0_0, | ||
749 | + .ro = 0xffffffff, | ||
750 | + },{ .name = "PPK0_1", .addr = A_PPK0_1, | ||
751 | + .ro = 0xffffffff, | ||
752 | + },{ .name = "PPK0_2", .addr = A_PPK0_2, | ||
753 | + .ro = 0xffffffff, | ||
754 | + },{ .name = "PPK0_3", .addr = A_PPK0_3, | ||
755 | + .ro = 0xffffffff, | ||
756 | + },{ .name = "PPK0_4", .addr = A_PPK0_4, | ||
757 | + .ro = 0xffffffff, | ||
758 | + },{ .name = "PPK0_5", .addr = A_PPK0_5, | ||
759 | + .ro = 0xffffffff, | ||
760 | + },{ .name = "PPK0_6", .addr = A_PPK0_6, | ||
761 | + .ro = 0xffffffff, | ||
762 | + },{ .name = "PPK0_7", .addr = A_PPK0_7, | ||
763 | + .ro = 0xffffffff, | ||
764 | + },{ .name = "PPK0_8", .addr = A_PPK0_8, | ||
765 | + .ro = 0xffffffff, | ||
766 | + },{ .name = "PPK0_9", .addr = A_PPK0_9, | ||
767 | + .ro = 0xffffffff, | ||
768 | + },{ .name = "PPK0_10", .addr = A_PPK0_10, | ||
769 | + .ro = 0xffffffff, | ||
770 | + },{ .name = "PPK0_11", .addr = A_PPK0_11, | ||
771 | + .ro = 0xffffffff, | ||
772 | + },{ .name = "PPK1_0", .addr = A_PPK1_0, | ||
773 | + .ro = 0xffffffff, | ||
774 | + },{ .name = "PPK1_1", .addr = A_PPK1_1, | ||
775 | + .ro = 0xffffffff, | ||
776 | + },{ .name = "PPK1_2", .addr = A_PPK1_2, | ||
777 | + .ro = 0xffffffff, | ||
778 | + },{ .name = "PPK1_3", .addr = A_PPK1_3, | ||
779 | + .ro = 0xffffffff, | ||
780 | + },{ .name = "PPK1_4", .addr = A_PPK1_4, | ||
781 | + .ro = 0xffffffff, | ||
782 | + },{ .name = "PPK1_5", .addr = A_PPK1_5, | ||
783 | + .ro = 0xffffffff, | ||
784 | + },{ .name = "PPK1_6", .addr = A_PPK1_6, | ||
785 | + .ro = 0xffffffff, | ||
786 | + },{ .name = "PPK1_7", .addr = A_PPK1_7, | ||
787 | + .ro = 0xffffffff, | ||
788 | + },{ .name = "PPK1_8", .addr = A_PPK1_8, | ||
789 | + .ro = 0xffffffff, | ||
790 | + },{ .name = "PPK1_9", .addr = A_PPK1_9, | ||
791 | + .ro = 0xffffffff, | ||
792 | + },{ .name = "PPK1_10", .addr = A_PPK1_10, | ||
793 | + .ro = 0xffffffff, | ||
794 | + },{ .name = "PPK1_11", .addr = A_PPK1_11, | ||
795 | + .ro = 0xffffffff, | ||
796 | + } | ||
797 | +}; | ||
798 | + | ||
799 | +static void zynqmp_efuse_reg_write(void *opaque, hwaddr addr, | ||
800 | + uint64_t data, unsigned size) | ||
801 | +{ | ||
802 | + RegisterInfoArray *reg_array = opaque; | ||
803 | + XlnxZynqMPEFuse *s; | ||
804 | + Object *dev; | ||
805 | + | ||
806 | + assert(reg_array != NULL); | ||
807 | + | ||
808 | + dev = reg_array->mem.owner; | ||
809 | + assert(dev); | ||
810 | + | ||
811 | + s = XLNX_ZYNQMP_EFUSE(dev); | ||
812 | + | ||
813 | + if (addr != A_WR_LOCK && s->regs[R_WR_LOCK]) { | ||
814 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
815 | + "%s[reg_0x%02lx]: Attempt to write locked register.\n", | ||
816 | + object_get_canonical_path(OBJECT(s)), (long)addr); | ||
817 | + } else { | ||
818 | + register_write_memory(opaque, addr, data, size); | ||
819 | + } | ||
820 | +} | ||
821 | + | ||
822 | +static const MemoryRegionOps zynqmp_efuse_ops = { | ||
823 | + .read = register_read_memory, | ||
824 | + .write = zynqmp_efuse_reg_write, | ||
825 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
826 | + .valid = { | ||
827 | + .min_access_size = 4, | ||
828 | + .max_access_size = 4, | ||
829 | + }, | ||
830 | +}; | ||
831 | + | ||
832 | +static void zynqmp_efuse_register_reset(RegisterInfo *reg) | ||
833 | +{ | ||
834 | + if (!reg->data || !reg->access) { | ||
835 | + return; | ||
836 | + } | ||
837 | + | ||
838 | + /* Reset must not trigger some registers' writers */ | ||
839 | + switch (reg->access->addr) { | ||
840 | + case A_EFUSE_AES_CRC: | ||
841 | + *(uint32_t *)reg->data = reg->access->reset; | ||
842 | + return; | ||
843 | + } | ||
844 | + | ||
845 | + register_reset(reg); | ||
846 | +} | ||
847 | + | ||
848 | +static void zynqmp_efuse_reset(DeviceState *dev) | ||
849 | +{ | ||
850 | + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev); | ||
851 | + unsigned int i; | ||
852 | + | ||
853 | + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { | ||
854 | + zynqmp_efuse_register_reset(&s->regs_info[i]); | ||
855 | + } | ||
856 | + | ||
857 | + zynqmp_efuse_sync_cache(s, FBIT_UNKNOWN); | ||
858 | + ARRAY_FIELD_DP32(s->regs, STATUS, CACHE_DONE, 1); | ||
859 | + zynqmp_efuse_update_irq(s); | ||
860 | +} | ||
861 | + | ||
862 | +static void zynqmp_efuse_realize(DeviceState *dev, Error **errp) | ||
863 | +{ | ||
864 | + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(dev); | ||
865 | + | ||
866 | + if (!s->efuse) { | ||
867 | + error_setg(errp, "%s.efuse: link property not connected to XLNX-EFUSE", | ||
868 | + object_get_canonical_path(OBJECT(dev))); | ||
869 | + return; | ||
870 | + } | ||
871 | + | ||
872 | + s->efuse->dev = dev; | ||
873 | +} | ||
874 | + | ||
875 | +static void zynqmp_efuse_init(Object *obj) | ||
876 | +{ | ||
877 | + XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj); | ||
878 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
879 | + RegisterInfoArray *reg_array; | ||
880 | + | ||
881 | + reg_array = | ||
882 | + register_init_block32(DEVICE(obj), zynqmp_efuse_regs_info, | ||
883 | + ARRAY_SIZE(zynqmp_efuse_regs_info), | ||
884 | + s->regs_info, s->regs, | ||
885 | + &zynqmp_efuse_ops, | ||
886 | + ZYNQMP_EFUSE_ERR_DEBUG, | ||
887 | + R_MAX * 4); | ||
888 | + | ||
889 | + sysbus_init_mmio(sbd, ®_array->mem); | ||
890 | + sysbus_init_irq(sbd, &s->irq); | ||
891 | +} | ||
892 | + | ||
893 | +static const VMStateDescription vmstate_efuse = { | ||
894 | + .name = TYPE_XLNX_ZYNQMP_EFUSE, | ||
895 | + .version_id = 1, | ||
896 | + .minimum_version_id = 1, | ||
897 | + .fields = (VMStateField[]) { | ||
898 | + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPEFuse, R_MAX), | ||
899 | + VMSTATE_END_OF_LIST(), | ||
900 | + } | ||
901 | +}; | ||
902 | + | ||
903 | +static Property zynqmp_efuse_props[] = { | ||
904 | + DEFINE_PROP_LINK("efuse", | ||
905 | + XlnxZynqMPEFuse, efuse, | ||
906 | + TYPE_XLNX_EFUSE, XlnxEFuse *), | ||
907 | + | ||
908 | + DEFINE_PROP_END_OF_LIST(), | ||
909 | +}; | ||
910 | + | ||
911 | +static void zynqmp_efuse_class_init(ObjectClass *klass, void *data) | ||
912 | +{ | ||
913 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
914 | + | ||
915 | + dc->reset = zynqmp_efuse_reset; | ||
916 | + dc->realize = zynqmp_efuse_realize; | ||
917 | + dc->vmsd = &vmstate_efuse; | ||
918 | + device_class_set_props(dc, zynqmp_efuse_props); | ||
919 | +} | ||
920 | + | ||
921 | + | ||
922 | +static const TypeInfo efuse_info = { | ||
923 | + .name = TYPE_XLNX_ZYNQMP_EFUSE, | ||
924 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
925 | + .instance_size = sizeof(XlnxZynqMPEFuse), | ||
926 | + .class_init = zynqmp_efuse_class_init, | ||
927 | + .instance_init = zynqmp_efuse_init, | ||
928 | +}; | ||
929 | + | ||
930 | +static void efuse_register_types(void) | ||
931 | +{ | ||
932 | + type_register_static(&efuse_info); | ||
933 | +} | ||
934 | + | ||
935 | +type_init(efuse_register_types) | ||
936 | diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig | ||
15 | index XXXXXXX..XXXXXXX 100644 | 937 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/docs/system/arm/nuvoton.rst | 938 | --- a/hw/nvram/Kconfig |
17 | +++ b/docs/system/arm/nuvoton.rst | 939 | +++ b/hw/nvram/Kconfig |
18 | @@ -XXX,XX +XXX,XX @@ | 940 | @@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE |
19 | -Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``) | 941 | config XLNX_EFUSE_VERSAL |
20 | -===================================================== | 942 | bool |
21 | +Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``) | 943 | select XLNX_EFUSE |
22 | +================================================================ | 944 | + |
23 | 945 | +config XLNX_EFUSE_ZYNQMP | |
24 | The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are | 946 | + bool |
25 | designed to be used as Baseboard Management Controllers (BMCs) in various | 947 | + select XLNX_EFUSE |
26 | @@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip : | 948 | diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build |
27 | The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and | 949 | index XXXXXXX..XXXXXXX 100644 |
28 | Hyperscale applications. The following machines are based on this chip : | 950 | --- a/hw/nvram/meson.build |
29 | 951 | +++ b/hw/nvram/meson.build | |
30 | +- ``quanta-gbs-bmc`` Quanta GBS server BMC | 952 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE', if_true: files('xlnx-efuse.c')) |
31 | - ``quanta-gsj`` Quanta GSJ server BMC | 953 | softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files( |
32 | 954 | 'xlnx-versal-efuse-cache.c', | |
33 | There are also two more SoCs, NPCM710 and NPCM705, which are single-core | 955 | 'xlnx-versal-efuse-ctrl.c')) |
956 | +softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files( | ||
957 | + 'xlnx-zynqmp-efuse.c')) | ||
958 | |||
959 | specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c')) | ||
34 | -- | 960 | -- |
35 | 2.20.1 | 961 | 2.20.1 |
36 | 962 | ||
37 | 963 | diff view generated by jsdifflib |
1 | From: Patrick Venture <venture@google.com> | 1 | From: Tong Ho <tong.ho@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | Adds a line-item reference to the supported quanta-q71l-bmc aspeed | 3 | This device is present in Versal and ZynqMP product |
4 | entry. | 4 | families to store a 256-bit encryption key. |
5 | 5 | ||
6 | Signed-off-by: Patrick Venture <venture@google.com> | 6 | Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 7 | Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> |
8 | Message-id: 20210615192848.1065297-2-venture@google.com | 8 | |
9 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
10 | Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | ||
11 | Signed-off-by: Tong Ho <tong.ho@xilinx.com> | ||
12 | Message-id: 20210917052400.1249094-5-tong.ho@xilinx.com | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 15 | --- |
11 | docs/system/arm/aspeed.rst | 1 + | 16 | include/hw/nvram/xlnx-bbram.h | 54 ++++ |
12 | 1 file changed, 1 insertion(+) | 17 | hw/nvram/xlnx-bbram.c | 545 ++++++++++++++++++++++++++++++++++ |
18 | hw/nvram/Kconfig | 4 + | ||
19 | hw/nvram/meson.build | 1 + | ||
20 | 4 files changed, 604 insertions(+) | ||
21 | create mode 100644 include/hw/nvram/xlnx-bbram.h | ||
22 | create mode 100644 hw/nvram/xlnx-bbram.c | ||
13 | 23 | ||
14 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst | 24 | diff --git a/include/hw/nvram/xlnx-bbram.h b/include/hw/nvram/xlnx-bbram.h |
25 | new file mode 100644 | ||
26 | index XXXXXXX..XXXXXXX | ||
27 | --- /dev/null | ||
28 | +++ b/include/hw/nvram/xlnx-bbram.h | ||
29 | @@ -XXX,XX +XXX,XX @@ | ||
30 | +/* | ||
31 | + * QEMU model of the Xilinx BBRAM Battery Backed RAM | ||
32 | + * | ||
33 | + * Copyright (c) 2015-2021 Xilinx Inc. | ||
34 | + * | ||
35 | + * Written by Edgar E. Iglesias <edgari@xilinx.com> | ||
36 | + * | ||
37 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
38 | + * of this software and associated documentation files (the "Software"), to deal | ||
39 | + * in the Software without restriction, including without limitation the rights | ||
40 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
41 | + * copies of the Software, and to permit persons to whom the Software is | ||
42 | + * furnished to do so, subject to the following conditions: | ||
43 | + * | ||
44 | + * The above copyright notice and this permission notice shall be included in | ||
45 | + * all copies or substantial portions of the Software. | ||
46 | + * | ||
47 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
48 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
49 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
50 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
51 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
52 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
53 | + * THE SOFTWARE. | ||
54 | + */ | ||
55 | +#ifndef XLNX_BBRAM_H | ||
56 | +#define XLNX_BBRAM_H | ||
57 | + | ||
58 | +#include "sysemu/block-backend.h" | ||
59 | +#include "hw/qdev-core.h" | ||
60 | +#include "hw/irq.h" | ||
61 | +#include "hw/sysbus.h" | ||
62 | +#include "hw/register.h" | ||
63 | + | ||
64 | +#define RMAX_XLNX_BBRAM ((0x4c / 4) + 1) | ||
65 | + | ||
66 | +#define TYPE_XLNX_BBRAM "xlnx,bbram-ctrl" | ||
67 | +OBJECT_DECLARE_SIMPLE_TYPE(XlnxBBRam, XLNX_BBRAM); | ||
68 | + | ||
69 | +struct XlnxBBRam { | ||
70 | + SysBusDevice parent_obj; | ||
71 | + qemu_irq irq_bbram; | ||
72 | + | ||
73 | + BlockBackend *blk; | ||
74 | + | ||
75 | + uint32_t crc_zpads; | ||
76 | + bool bbram8_wo; | ||
77 | + bool blk_ro; | ||
78 | + | ||
79 | + uint32_t regs[RMAX_XLNX_BBRAM]; | ||
80 | + RegisterInfo regs_info[RMAX_XLNX_BBRAM]; | ||
81 | +}; | ||
82 | + | ||
83 | +#endif | ||
84 | diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c | ||
85 | new file mode 100644 | ||
86 | index XXXXXXX..XXXXXXX | ||
87 | --- /dev/null | ||
88 | +++ b/hw/nvram/xlnx-bbram.c | ||
89 | @@ -XXX,XX +XXX,XX @@ | ||
90 | +/* | ||
91 | + * QEMU model of the Xilinx BBRAM Battery Backed RAM | ||
92 | + * | ||
93 | + * Copyright (c) 2014-2021 Xilinx Inc. | ||
94 | + * | ||
95 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
96 | + * of this software and associated documentation files (the "Software"), to deal | ||
97 | + * in the Software without restriction, including without limitation the rights | ||
98 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
99 | + * copies of the Software, and to permit persons to whom the Software is | ||
100 | + * furnished to do so, subject to the following conditions: | ||
101 | + * | ||
102 | + * The above copyright notice and this permission notice shall be included in | ||
103 | + * all copies or substantial portions of the Software. | ||
104 | + * | ||
105 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
106 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
107 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
108 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
109 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
110 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
111 | + * THE SOFTWARE. | ||
112 | + */ | ||
113 | + | ||
114 | +#include "qemu/osdep.h" | ||
115 | +#include "hw/nvram/xlnx-bbram.h" | ||
116 | + | ||
117 | +#include "qemu/error-report.h" | ||
118 | +#include "qemu/log.h" | ||
119 | +#include "qapi/error.h" | ||
120 | +#include "sysemu/blockdev.h" | ||
121 | +#include "migration/vmstate.h" | ||
122 | +#include "hw/qdev-properties.h" | ||
123 | +#include "hw/qdev-properties-system.h" | ||
124 | +#include "hw/nvram/xlnx-efuse.h" | ||
125 | + | ||
126 | +#ifndef XLNX_BBRAM_ERR_DEBUG | ||
127 | +#define XLNX_BBRAM_ERR_DEBUG 0 | ||
128 | +#endif | ||
129 | + | ||
130 | +REG32(BBRAM_STATUS, 0x0) | ||
131 | + FIELD(BBRAM_STATUS, AES_CRC_PASS, 9, 1) | ||
132 | + FIELD(BBRAM_STATUS, AES_CRC_DONE, 8, 1) | ||
133 | + FIELD(BBRAM_STATUS, BBRAM_ZEROIZED, 4, 1) | ||
134 | + FIELD(BBRAM_STATUS, PGM_MODE, 0, 1) | ||
135 | +REG32(BBRAM_CTRL, 0x4) | ||
136 | + FIELD(BBRAM_CTRL, ZEROIZE, 0, 1) | ||
137 | +REG32(PGM_MODE, 0x8) | ||
138 | +REG32(BBRAM_AES_CRC, 0xc) | ||
139 | +REG32(BBRAM_0, 0x10) | ||
140 | +REG32(BBRAM_1, 0x14) | ||
141 | +REG32(BBRAM_2, 0x18) | ||
142 | +REG32(BBRAM_3, 0x1c) | ||
143 | +REG32(BBRAM_4, 0x20) | ||
144 | +REG32(BBRAM_5, 0x24) | ||
145 | +REG32(BBRAM_6, 0x28) | ||
146 | +REG32(BBRAM_7, 0x2c) | ||
147 | +REG32(BBRAM_8, 0x30) | ||
148 | +REG32(BBRAM_SLVERR, 0x34) | ||
149 | + FIELD(BBRAM_SLVERR, ENABLE, 0, 1) | ||
150 | +REG32(BBRAM_ISR, 0x38) | ||
151 | + FIELD(BBRAM_ISR, APB_SLVERR, 0, 1) | ||
152 | +REG32(BBRAM_IMR, 0x3c) | ||
153 | + FIELD(BBRAM_IMR, APB_SLVERR, 0, 1) | ||
154 | +REG32(BBRAM_IER, 0x40) | ||
155 | + FIELD(BBRAM_IER, APB_SLVERR, 0, 1) | ||
156 | +REG32(BBRAM_IDR, 0x44) | ||
157 | + FIELD(BBRAM_IDR, APB_SLVERR, 0, 1) | ||
158 | +REG32(BBRAM_MSW_LOCK, 0x4c) | ||
159 | + FIELD(BBRAM_MSW_LOCK, VAL, 0, 1) | ||
160 | + | ||
161 | +#define R_MAX (R_BBRAM_MSW_LOCK + 1) | ||
162 | + | ||
163 | +#define RAM_MAX (A_BBRAM_8 + 4 - A_BBRAM_0) | ||
164 | + | ||
165 | +#define BBRAM_PGM_MAGIC 0x757bdf0d | ||
166 | + | ||
167 | +QEMU_BUILD_BUG_ON(R_MAX != ARRAY_SIZE(((XlnxBBRam *)0)->regs)); | ||
168 | + | ||
169 | +static bool bbram_msw_locked(XlnxBBRam *s) | ||
170 | +{ | ||
171 | + return ARRAY_FIELD_EX32(s->regs, BBRAM_MSW_LOCK, VAL) != 0; | ||
172 | +} | ||
173 | + | ||
174 | +static bool bbram_pgm_enabled(XlnxBBRam *s) | ||
175 | +{ | ||
176 | + return ARRAY_FIELD_EX32(s->regs, BBRAM_STATUS, PGM_MODE) != 0; | ||
177 | +} | ||
178 | + | ||
179 | +static void bbram_bdrv_error(XlnxBBRam *s, int rc, gchar *detail) | ||
180 | +{ | ||
181 | + Error *errp; | ||
182 | + | ||
183 | + error_setg_errno(&errp, -rc, "%s: BBRAM backstore %s failed.", | ||
184 | + blk_name(s->blk), detail); | ||
185 | + error_report("%s", error_get_pretty(errp)); | ||
186 | + error_free(errp); | ||
187 | + | ||
188 | + g_free(detail); | ||
189 | +} | ||
190 | + | ||
191 | +static void bbram_bdrv_read(XlnxBBRam *s, Error **errp) | ||
192 | +{ | ||
193 | + uint32_t *ram = &s->regs[R_BBRAM_0]; | ||
194 | + int nr = RAM_MAX; | ||
195 | + | ||
196 | + if (!s->blk) { | ||
197 | + return; | ||
198 | + } | ||
199 | + | ||
200 | + s->blk_ro = !blk_supports_write_perm(s->blk); | ||
201 | + if (!s->blk_ro) { | ||
202 | + int rc; | ||
203 | + | ||
204 | + rc = blk_set_perm(s->blk, | ||
205 | + (BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE), | ||
206 | + BLK_PERM_ALL, NULL); | ||
207 | + if (rc) { | ||
208 | + s->blk_ro = true; | ||
209 | + } | ||
210 | + } | ||
211 | + if (s->blk_ro) { | ||
212 | + warn_report("%s: Skip saving updates to read-only BBRAM backstore.", | ||
213 | + blk_name(s->blk)); | ||
214 | + } | ||
215 | + | ||
216 | + if (blk_pread(s->blk, 0, ram, nr) < 0) { | ||
217 | + error_setg(errp, | ||
218 | + "%s: Failed to read %u bytes from BBRAM backstore.", | ||
219 | + blk_name(s->blk), nr); | ||
220 | + return; | ||
221 | + } | ||
222 | + | ||
223 | + /* Convert from little-endian backstore for each 32-bit word */ | ||
224 | + nr /= 4; | ||
225 | + while (nr--) { | ||
226 | + ram[nr] = le32_to_cpu(ram[nr]); | ||
227 | + } | ||
228 | +} | ||
229 | + | ||
230 | +static void bbram_bdrv_sync(XlnxBBRam *s, uint64_t hwaddr) | ||
231 | +{ | ||
232 | + uint32_t le32; | ||
233 | + unsigned offset; | ||
234 | + int rc; | ||
235 | + | ||
236 | + assert(A_BBRAM_0 <= hwaddr && hwaddr <= A_BBRAM_8); | ||
237 | + | ||
238 | + /* Backstore is always in little-endian */ | ||
239 | + le32 = cpu_to_le32(s->regs[hwaddr / 4]); | ||
240 | + | ||
241 | + /* Update zeroized flag */ | ||
242 | + if (le32 && (hwaddr != A_BBRAM_8 || s->bbram8_wo)) { | ||
243 | + ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 0); | ||
244 | + } | ||
245 | + | ||
246 | + if (!s->blk || s->blk_ro) { | ||
247 | + return; | ||
248 | + } | ||
249 | + | ||
250 | + offset = hwaddr - A_BBRAM_0; | ||
251 | + rc = blk_pwrite(s->blk, offset, &le32, 4, 0); | ||
252 | + if (rc < 0) { | ||
253 | + bbram_bdrv_error(s, rc, g_strdup_printf("write to offset %u", offset)); | ||
254 | + } | ||
255 | +} | ||
256 | + | ||
257 | +static void bbram_bdrv_zero(XlnxBBRam *s) | ||
258 | +{ | ||
259 | + int rc; | ||
260 | + | ||
261 | + ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, BBRAM_ZEROIZED, 1); | ||
262 | + | ||
263 | + if (!s->blk || s->blk_ro) { | ||
264 | + return; | ||
265 | + } | ||
266 | + | ||
267 | + rc = blk_make_zero(s->blk, 0); | ||
268 | + if (rc < 0) { | ||
269 | + bbram_bdrv_error(s, rc, g_strdup("zeroizing")); | ||
270 | + } | ||
271 | + | ||
272 | + /* Restore bbram8 if it is non-zero */ | ||
273 | + if (s->regs[R_BBRAM_8]) { | ||
274 | + bbram_bdrv_sync(s, A_BBRAM_8); | ||
275 | + } | ||
276 | +} | ||
277 | + | ||
278 | +static void bbram_zeroize(XlnxBBRam *s) | ||
279 | +{ | ||
280 | + int nr = RAM_MAX - (s->bbram8_wo ? 0 : 4); /* only wo bbram8 is cleared */ | ||
281 | + | ||
282 | + memset(&s->regs[R_BBRAM_0], 0, nr); | ||
283 | + bbram_bdrv_zero(s); | ||
284 | +} | ||
285 | + | ||
286 | +static void bbram_update_irq(XlnxBBRam *s) | ||
287 | +{ | ||
288 | + bool pending = s->regs[R_BBRAM_ISR] & ~s->regs[R_BBRAM_IMR]; | ||
289 | + | ||
290 | + qemu_set_irq(s->irq_bbram, pending); | ||
291 | +} | ||
292 | + | ||
293 | +static void bbram_ctrl_postw(RegisterInfo *reg, uint64_t val64) | ||
294 | +{ | ||
295 | + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); | ||
296 | + uint32_t val = val64; | ||
297 | + | ||
298 | + if (val & R_BBRAM_CTRL_ZEROIZE_MASK) { | ||
299 | + bbram_zeroize(s); | ||
300 | + /* The bit is self clearing */ | ||
301 | + s->regs[R_BBRAM_CTRL] &= ~R_BBRAM_CTRL_ZEROIZE_MASK; | ||
302 | + } | ||
303 | +} | ||
304 | + | ||
305 | +static void bbram_pgm_mode_postw(RegisterInfo *reg, uint64_t val64) | ||
306 | +{ | ||
307 | + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); | ||
308 | + uint32_t val = val64; | ||
309 | + | ||
310 | + if (val == BBRAM_PGM_MAGIC) { | ||
311 | + bbram_zeroize(s); | ||
312 | + | ||
313 | + /* The status bit is cleared only by POR */ | ||
314 | + ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, PGM_MODE, 1); | ||
315 | + } | ||
316 | +} | ||
317 | + | ||
318 | +static void bbram_aes_crc_postw(RegisterInfo *reg, uint64_t val64) | ||
319 | +{ | ||
320 | + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); | ||
321 | + uint32_t calc_crc; | ||
322 | + | ||
323 | + if (!bbram_pgm_enabled(s)) { | ||
324 | + /* We are not in programming mode, don't do anything */ | ||
325 | + return; | ||
326 | + } | ||
327 | + | ||
328 | + /* Perform the AES integrity check */ | ||
329 | + s->regs[R_BBRAM_STATUS] |= R_BBRAM_STATUS_AES_CRC_DONE_MASK; | ||
330 | + | ||
331 | + /* | ||
332 | + * Set check status. | ||
333 | + * | ||
334 | + * ZynqMP BBRAM check has a zero-u32 prepended; see: | ||
335 | + * https://github.com/Xilinx/embeddedsw/blob/release-2019.2/lib/sw_services/xilskey/src/xilskey_bbramps_zynqmp.c#L311 | ||
336 | + */ | ||
337 | + calc_crc = xlnx_efuse_calc_crc(&s->regs[R_BBRAM_0], | ||
338 | + (R_BBRAM_8 - R_BBRAM_0), s->crc_zpads); | ||
339 | + | ||
340 | + ARRAY_FIELD_DP32(s->regs, BBRAM_STATUS, AES_CRC_PASS, | ||
341 | + (s->regs[R_BBRAM_AES_CRC] == calc_crc)); | ||
342 | +} | ||
343 | + | ||
344 | +static uint64_t bbram_key_prew(RegisterInfo *reg, uint64_t val64) | ||
345 | +{ | ||
346 | + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); | ||
347 | + uint32_t original_data = *(uint32_t *) reg->data; | ||
348 | + | ||
349 | + if (bbram_pgm_enabled(s)) { | ||
350 | + return val64; | ||
351 | + } else { | ||
352 | + /* We are not in programming mode, don't do anything */ | ||
353 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
354 | + "Not in programming mode, dropping the write\n"); | ||
355 | + return original_data; | ||
356 | + } | ||
357 | +} | ||
358 | + | ||
359 | +static void bbram_key_postw(RegisterInfo *reg, uint64_t val64) | ||
360 | +{ | ||
361 | + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); | ||
362 | + | ||
363 | + bbram_bdrv_sync(s, reg->access->addr); | ||
364 | +} | ||
365 | + | ||
366 | +static uint64_t bbram_wo_postr(RegisterInfo *reg, uint64_t val) | ||
367 | +{ | ||
368 | + return 0; | ||
369 | +} | ||
370 | + | ||
371 | +static uint64_t bbram_r8_postr(RegisterInfo *reg, uint64_t val) | ||
372 | +{ | ||
373 | + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); | ||
374 | + | ||
375 | + return s->bbram8_wo ? bbram_wo_postr(reg, val) : val; | ||
376 | +} | ||
377 | + | ||
378 | +static bool bbram_r8_readonly(XlnxBBRam *s) | ||
379 | +{ | ||
380 | + return !bbram_pgm_enabled(s) || bbram_msw_locked(s); | ||
381 | +} | ||
382 | + | ||
383 | +static uint64_t bbram_r8_prew(RegisterInfo *reg, uint64_t val64) | ||
384 | +{ | ||
385 | + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); | ||
386 | + | ||
387 | + if (bbram_r8_readonly(s)) { | ||
388 | + val64 = *(uint32_t *)reg->data; | ||
389 | + } | ||
390 | + | ||
391 | + return val64; | ||
392 | +} | ||
393 | + | ||
394 | +static void bbram_r8_postw(RegisterInfo *reg, uint64_t val64) | ||
395 | +{ | ||
396 | + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); | ||
397 | + | ||
398 | + if (!bbram_r8_readonly(s)) { | ||
399 | + bbram_bdrv_sync(s, A_BBRAM_8); | ||
400 | + } | ||
401 | +} | ||
402 | + | ||
403 | +static uint64_t bbram_msw_lock_prew(RegisterInfo *reg, uint64_t val64) | ||
404 | +{ | ||
405 | + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); | ||
406 | + | ||
407 | + /* Never lock if bbram8 is wo; and, only POR can clear the lock */ | ||
408 | + if (s->bbram8_wo) { | ||
409 | + val64 = 0; | ||
410 | + } else { | ||
411 | + val64 |= s->regs[R_BBRAM_MSW_LOCK]; | ||
412 | + } | ||
413 | + | ||
414 | + return val64; | ||
415 | +} | ||
416 | + | ||
417 | +static void bbram_isr_postw(RegisterInfo *reg, uint64_t val64) | ||
418 | +{ | ||
419 | + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); | ||
420 | + | ||
421 | + bbram_update_irq(s); | ||
422 | +} | ||
423 | + | ||
424 | +static uint64_t bbram_ier_prew(RegisterInfo *reg, uint64_t val64) | ||
425 | +{ | ||
426 | + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); | ||
427 | + uint32_t val = val64; | ||
428 | + | ||
429 | + s->regs[R_BBRAM_IMR] &= ~val; | ||
430 | + bbram_update_irq(s); | ||
431 | + return 0; | ||
432 | +} | ||
433 | + | ||
434 | +static uint64_t bbram_idr_prew(RegisterInfo *reg, uint64_t val64) | ||
435 | +{ | ||
436 | + XlnxBBRam *s = XLNX_BBRAM(reg->opaque); | ||
437 | + uint32_t val = val64; | ||
438 | + | ||
439 | + s->regs[R_BBRAM_IMR] |= val; | ||
440 | + bbram_update_irq(s); | ||
441 | + return 0; | ||
442 | +} | ||
443 | + | ||
444 | +static RegisterAccessInfo bbram_ctrl_regs_info[] = { | ||
445 | + { .name = "BBRAM_STATUS", .addr = A_BBRAM_STATUS, | ||
446 | + .rsvd = 0xee, | ||
447 | + .ro = 0x3ff, | ||
448 | + },{ .name = "BBRAM_CTRL", .addr = A_BBRAM_CTRL, | ||
449 | + .post_write = bbram_ctrl_postw, | ||
450 | + },{ .name = "PGM_MODE", .addr = A_PGM_MODE, | ||
451 | + .post_write = bbram_pgm_mode_postw, | ||
452 | + },{ .name = "BBRAM_AES_CRC", .addr = A_BBRAM_AES_CRC, | ||
453 | + .post_write = bbram_aes_crc_postw, | ||
454 | + .post_read = bbram_wo_postr, | ||
455 | + },{ .name = "BBRAM_0", .addr = A_BBRAM_0, | ||
456 | + .pre_write = bbram_key_prew, | ||
457 | + .post_write = bbram_key_postw, | ||
458 | + .post_read = bbram_wo_postr, | ||
459 | + },{ .name = "BBRAM_1", .addr = A_BBRAM_1, | ||
460 | + .pre_write = bbram_key_prew, | ||
461 | + .post_write = bbram_key_postw, | ||
462 | + .post_read = bbram_wo_postr, | ||
463 | + },{ .name = "BBRAM_2", .addr = A_BBRAM_2, | ||
464 | + .pre_write = bbram_key_prew, | ||
465 | + .post_write = bbram_key_postw, | ||
466 | + .post_read = bbram_wo_postr, | ||
467 | + },{ .name = "BBRAM_3", .addr = A_BBRAM_3, | ||
468 | + .pre_write = bbram_key_prew, | ||
469 | + .post_write = bbram_key_postw, | ||
470 | + .post_read = bbram_wo_postr, | ||
471 | + },{ .name = "BBRAM_4", .addr = A_BBRAM_4, | ||
472 | + .pre_write = bbram_key_prew, | ||
473 | + .post_write = bbram_key_postw, | ||
474 | + .post_read = bbram_wo_postr, | ||
475 | + },{ .name = "BBRAM_5", .addr = A_BBRAM_5, | ||
476 | + .pre_write = bbram_key_prew, | ||
477 | + .post_write = bbram_key_postw, | ||
478 | + .post_read = bbram_wo_postr, | ||
479 | + },{ .name = "BBRAM_6", .addr = A_BBRAM_6, | ||
480 | + .pre_write = bbram_key_prew, | ||
481 | + .post_write = bbram_key_postw, | ||
482 | + .post_read = bbram_wo_postr, | ||
483 | + },{ .name = "BBRAM_7", .addr = A_BBRAM_7, | ||
484 | + .pre_write = bbram_key_prew, | ||
485 | + .post_write = bbram_key_postw, | ||
486 | + .post_read = bbram_wo_postr, | ||
487 | + },{ .name = "BBRAM_8", .addr = A_BBRAM_8, | ||
488 | + .pre_write = bbram_r8_prew, | ||
489 | + .post_write = bbram_r8_postw, | ||
490 | + .post_read = bbram_r8_postr, | ||
491 | + },{ .name = "BBRAM_SLVERR", .addr = A_BBRAM_SLVERR, | ||
492 | + .rsvd = ~1, | ||
493 | + },{ .name = "BBRAM_ISR", .addr = A_BBRAM_ISR, | ||
494 | + .w1c = 0x1, | ||
495 | + .post_write = bbram_isr_postw, | ||
496 | + },{ .name = "BBRAM_IMR", .addr = A_BBRAM_IMR, | ||
497 | + .ro = 0x1, | ||
498 | + },{ .name = "BBRAM_IER", .addr = A_BBRAM_IER, | ||
499 | + .pre_write = bbram_ier_prew, | ||
500 | + },{ .name = "BBRAM_IDR", .addr = A_BBRAM_IDR, | ||
501 | + .pre_write = bbram_idr_prew, | ||
502 | + },{ .name = "BBRAM_MSW_LOCK", .addr = A_BBRAM_MSW_LOCK, | ||
503 | + .pre_write = bbram_msw_lock_prew, | ||
504 | + .ro = ~R_BBRAM_MSW_LOCK_VAL_MASK, | ||
505 | + } | ||
506 | +}; | ||
507 | + | ||
508 | +static void bbram_ctrl_reset(DeviceState *dev) | ||
509 | +{ | ||
510 | + XlnxBBRam *s = XLNX_BBRAM(dev); | ||
511 | + unsigned int i; | ||
512 | + | ||
513 | + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { | ||
514 | + if (i < R_BBRAM_0 || i > R_BBRAM_8) { | ||
515 | + register_reset(&s->regs_info[i]); | ||
516 | + } | ||
517 | + } | ||
518 | + | ||
519 | + bbram_update_irq(s); | ||
520 | +} | ||
521 | + | ||
522 | +static const MemoryRegionOps bbram_ctrl_ops = { | ||
523 | + .read = register_read_memory, | ||
524 | + .write = register_write_memory, | ||
525 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
526 | + .valid = { | ||
527 | + .min_access_size = 4, | ||
528 | + .max_access_size = 4, | ||
529 | + }, | ||
530 | +}; | ||
531 | + | ||
532 | +static void bbram_ctrl_realize(DeviceState *dev, Error **errp) | ||
533 | +{ | ||
534 | + XlnxBBRam *s = XLNX_BBRAM(dev); | ||
535 | + | ||
536 | + if (s->crc_zpads) { | ||
537 | + s->bbram8_wo = true; | ||
538 | + } | ||
539 | + | ||
540 | + bbram_bdrv_read(s, errp); | ||
541 | +} | ||
542 | + | ||
543 | +static void bbram_ctrl_init(Object *obj) | ||
544 | +{ | ||
545 | + XlnxBBRam *s = XLNX_BBRAM(obj); | ||
546 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
547 | + RegisterInfoArray *reg_array; | ||
548 | + | ||
549 | + reg_array = | ||
550 | + register_init_block32(DEVICE(obj), bbram_ctrl_regs_info, | ||
551 | + ARRAY_SIZE(bbram_ctrl_regs_info), | ||
552 | + s->regs_info, s->regs, | ||
553 | + &bbram_ctrl_ops, | ||
554 | + XLNX_BBRAM_ERR_DEBUG, | ||
555 | + R_MAX * 4); | ||
556 | + | ||
557 | + sysbus_init_mmio(sbd, ®_array->mem); | ||
558 | + sysbus_init_irq(sbd, &s->irq_bbram); | ||
559 | +} | ||
560 | + | ||
561 | +static void bbram_prop_set_drive(Object *obj, Visitor *v, const char *name, | ||
562 | + void *opaque, Error **errp) | ||
563 | +{ | ||
564 | + DeviceState *dev = DEVICE(obj); | ||
565 | + | ||
566 | + qdev_prop_drive.set(obj, v, name, opaque, errp); | ||
567 | + | ||
568 | + /* Fill initial data if backend is attached after realized */ | ||
569 | + if (dev->realized) { | ||
570 | + bbram_bdrv_read(XLNX_BBRAM(obj), errp); | ||
571 | + } | ||
572 | +} | ||
573 | + | ||
574 | +static void bbram_prop_get_drive(Object *obj, Visitor *v, const char *name, | ||
575 | + void *opaque, Error **errp) | ||
576 | +{ | ||
577 | + qdev_prop_drive.get(obj, v, name, opaque, errp); | ||
578 | +} | ||
579 | + | ||
580 | +static void bbram_prop_release_drive(Object *obj, const char *name, | ||
581 | + void *opaque) | ||
582 | +{ | ||
583 | + qdev_prop_drive.release(obj, name, opaque); | ||
584 | +} | ||
585 | + | ||
586 | +static const PropertyInfo bbram_prop_drive = { | ||
587 | + .name = "str", | ||
588 | + .description = "Node name or ID of a block device to use as BBRAM backend", | ||
589 | + .realized_set_allowed = true, | ||
590 | + .get = bbram_prop_get_drive, | ||
591 | + .set = bbram_prop_set_drive, | ||
592 | + .release = bbram_prop_release_drive, | ||
593 | +}; | ||
594 | + | ||
595 | +static const VMStateDescription vmstate_bbram_ctrl = { | ||
596 | + .name = TYPE_XLNX_BBRAM, | ||
597 | + .version_id = 1, | ||
598 | + .minimum_version_id = 1, | ||
599 | + .fields = (VMStateField[]) { | ||
600 | + VMSTATE_UINT32_ARRAY(regs, XlnxBBRam, R_MAX), | ||
601 | + VMSTATE_END_OF_LIST(), | ||
602 | + } | ||
603 | +}; | ||
604 | + | ||
605 | +static Property bbram_ctrl_props[] = { | ||
606 | + DEFINE_PROP("drive", XlnxBBRam, blk, bbram_prop_drive, BlockBackend *), | ||
607 | + DEFINE_PROP_UINT32("crc-zpads", XlnxBBRam, crc_zpads, 1), | ||
608 | + DEFINE_PROP_END_OF_LIST(), | ||
609 | +}; | ||
610 | + | ||
611 | +static void bbram_ctrl_class_init(ObjectClass *klass, void *data) | ||
612 | +{ | ||
613 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
614 | + | ||
615 | + dc->reset = bbram_ctrl_reset; | ||
616 | + dc->realize = bbram_ctrl_realize; | ||
617 | + dc->vmsd = &vmstate_bbram_ctrl; | ||
618 | + device_class_set_props(dc, bbram_ctrl_props); | ||
619 | +} | ||
620 | + | ||
621 | +static const TypeInfo bbram_ctrl_info = { | ||
622 | + .name = TYPE_XLNX_BBRAM, | ||
623 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
624 | + .instance_size = sizeof(XlnxBBRam), | ||
625 | + .class_init = bbram_ctrl_class_init, | ||
626 | + .instance_init = bbram_ctrl_init, | ||
627 | +}; | ||
628 | + | ||
629 | +static void bbram_ctrl_register_types(void) | ||
630 | +{ | ||
631 | + type_register_static(&bbram_ctrl_info); | ||
632 | +} | ||
633 | + | ||
634 | +type_init(bbram_ctrl_register_types) | ||
635 | diff --git a/hw/nvram/Kconfig b/hw/nvram/Kconfig | ||
15 | index XXXXXXX..XXXXXXX 100644 | 636 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/docs/system/arm/aspeed.rst | 637 | --- a/hw/nvram/Kconfig |
17 | +++ b/docs/system/arm/aspeed.rst | 638 | +++ b/hw/nvram/Kconfig |
18 | @@ -XXX,XX +XXX,XX @@ etc. | 639 | @@ -XXX,XX +XXX,XX @@ config XLNX_EFUSE_VERSAL |
19 | AST2400 SoC based machines : | 640 | config XLNX_EFUSE_ZYNQMP |
20 | 641 | bool | |
21 | - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC | 642 | select XLNX_EFUSE |
22 | +- ``quanta-q71l-bmc`` OpenBMC Quanta BMC | 643 | + |
23 | 644 | +config XLNX_BBRAM | |
24 | AST2500 SoC based machines : | 645 | + bool |
25 | 646 | + select XLNX_EFUSE_CRC | |
647 | diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build | ||
648 | index XXXXXXX..XXXXXXX 100644 | ||
649 | --- a/hw/nvram/meson.build | ||
650 | +++ b/hw/nvram/meson.build | ||
651 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_VERSAL', if_true: files( | ||
652 | 'xlnx-versal-efuse-ctrl.c')) | ||
653 | softmmu_ss.add(when: 'CONFIG_XLNX_EFUSE_ZYNQMP', if_true: files( | ||
654 | 'xlnx-zynqmp-efuse.c')) | ||
655 | +softmmu_ss.add(when: 'CONFIG_XLNX_BBRAM', if_true: files('xlnx-bbram.c')) | ||
656 | |||
657 | specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c')) | ||
26 | -- | 658 | -- |
27 | 2.20.1 | 659 | 2.20.1 |
28 | 660 | ||
29 | 661 | diff view generated by jsdifflib |
1 | Implement the MVE long shifts by register, which perform shifts on a | 1 | From: Tong Ho <tong.ho@xilinx.com> |
---|---|---|---|
2 | pair of general-purpose registers treated as a 64-bit quantity, with | ||
3 | the shift count in another general-purpose register, which might be | ||
4 | either positive or negative. | ||
5 | 2 | ||
6 | Like the long-shifts-by-immediate, these encodings sit in the space | 3 | Connect the support for Versal Battery-Backed RAM (BBRAM) |
7 | that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15. | ||
8 | Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and | ||
9 | also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases), | ||
10 | we have to move the CSEL pattern into the same decodetree group. | ||
11 | 4 | ||
5 | The command argument: | ||
6 | -drive if=pflash,index=0,... | ||
7 | Can be used to optionally connect the bbram to a backend | ||
8 | storage, such that field-programmed values in one | ||
9 | invocation can be made available to next invocation. | ||
10 | |||
11 | The backend storage must be a seekable binary file, and | ||
12 | its size must be 36 bytes or larger. A file with all | ||
13 | binary 0's is a 'blank'. | ||
14 | |||
15 | Signed-off-by: Tong Ho <tong.ho@xilinx.com> | ||
16 | Message-id: 20210917052400.1249094-6-tong.ho@xilinx.com | ||
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20210628135835.6690-17-peter.maydell@linaro.org | ||
15 | --- | 19 | --- |
16 | target/arm/helper-mve.h | 6 +++ | 20 | include/hw/arm/xlnx-versal.h | 5 +++++ |
17 | target/arm/translate.h | 1 + | 21 | hw/arm/xlnx-versal-virt.c | 36 ++++++++++++++++++++++++++++++++++++ |
18 | target/arm/t32.decode | 16 +++++-- | 22 | hw/arm/xlnx-versal.c | 18 ++++++++++++++++++ |
19 | target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++ | 23 | hw/arm/Kconfig | 1 + |
20 | target/arm/translate.c | 69 ++++++++++++++++++++++++++++++ | 24 | 4 files changed, 60 insertions(+) |
21 | 5 files changed, 182 insertions(+), 3 deletions(-) | ||
22 | 25 | ||
23 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | 26 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h |
24 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/target/arm/helper-mve.h | 28 | --- a/include/hw/arm/xlnx-versal.h |
26 | +++ b/target/arm/helper-mve.h | 29 | +++ b/include/hw/arm/xlnx-versal.h |
27 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 30 | @@ -XXX,XX +XXX,XX @@ |
28 | 31 | #include "qom/object.h" | |
29 | DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) | 32 | #include "hw/usb/xlnx-usb-subsystem.h" |
30 | 33 | #include "hw/misc/xlnx-versal-xramc.h" | |
31 | +DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) | 34 | +#include "hw/nvram/xlnx-bbram.h" |
32 | +DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32) | 35 | |
33 | DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | 36 | #define TYPE_XLNX_VERSAL "xlnx-versal" |
34 | DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | 37 | OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) |
35 | +DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) | 38 | @@ -XXX,XX +XXX,XX @@ struct Versal { |
36 | +DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | 39 | } iou; |
37 | +DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32) | 40 | |
38 | +DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) | 41 | XlnxZynqMPRTC rtc; |
39 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 42 | + XlnxBBRam bbram; |
43 | } pmc; | ||
44 | |||
45 | struct { | ||
46 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
47 | #define VERSAL_GEM1_WAKE_IRQ_0 59 | ||
48 | #define VERSAL_ADMA_IRQ_0 60 | ||
49 | #define VERSAL_XRAM_IRQ_0 79 | ||
50 | +#define VERSAL_BBRAM_APB_IRQ_0 121 | ||
51 | #define VERSAL_RTC_APB_ERR_IRQ 121 | ||
52 | #define VERSAL_SD0_IRQ_0 126 | ||
53 | #define VERSAL_RTC_ALARM_IRQ 142 | ||
54 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
55 | |||
56 | #define MM_PMC_SD0 0xf1040000U | ||
57 | #define MM_PMC_SD0_SIZE 0x10000 | ||
58 | +#define MM_PMC_BBRAM_CTRL 0xf11f0000 | ||
59 | +#define MM_PMC_BBRAM_CTRL_SIZE 0x00050 | ||
60 | #define MM_PMC_CRP 0xf1260000U | ||
61 | #define MM_PMC_CRP_SIZE 0x10000 | ||
62 | #define MM_PMC_RTC 0xf12a0000 | ||
63 | diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | 64 | index XXXXXXX..XXXXXXX 100644 |
41 | --- a/target/arm/translate.h | 65 | --- a/hw/arm/xlnx-versal-virt.c |
42 | +++ b/target/arm/translate.h | 66 | +++ b/hw/arm/xlnx-versal-virt.c |
43 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | 67 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_rtc_node(VersalVirt *s) |
44 | typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | 68 | g_free(name); |
45 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | 69 | } |
46 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | 70 | |
47 | +typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); | 71 | +static void fdt_add_bbram_node(VersalVirt *s) |
48 | 72 | +{ | |
49 | /** | 73 | + const char compat[] = TYPE_XLNX_BBRAM; |
50 | * arm_tbflags_from_tb: | 74 | + const char interrupt_names[] = "bbram-error"; |
51 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | 75 | + char *name = g_strdup_printf("/bbram@%x", MM_PMC_BBRAM_CTRL); |
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/target/arm/t32.decode | ||
54 | +++ b/target/arm/t32.decode | ||
55 | @@ -XXX,XX +XXX,XX @@ | ||
56 | &mcrr !extern cp opc1 crm rt rt2 | ||
57 | |||
58 | &mve_shl_ri rdalo rdahi shim | ||
59 | +&mve_shl_rr rdalo rdahi rm | ||
60 | |||
61 | # rdahi: bits [3:1] from insn, bit 0 is 1 | ||
62 | # rdalo: bits [3:1] from insn, bit 0 is 0 | ||
63 | @@ -XXX,XX +XXX,XX @@ | ||
64 | |||
65 | @mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \ | ||
66 | &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
67 | +@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \ | ||
68 | + &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
69 | |||
70 | { | ||
71 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | ||
72 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
73 | URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
74 | SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
75 | SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
76 | + | 76 | + |
77 | + LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | 77 | + qemu_fdt_add_subnode(s->fdt, name); |
78 | + ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | ||
79 | + UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr | ||
80 | + SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr | ||
81 | + UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr | ||
82 | + SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr | ||
83 | ] | ||
84 | |||
85 | MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi | ||
86 | ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi | ||
87 | + | 78 | + |
88 | + # v8.1M CSEL and friends | 79 | + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", |
89 | + CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4 | 80 | + GIC_FDT_IRQ_TYPE_SPI, VERSAL_BBRAM_APB_IRQ_0, |
90 | } | 81 | + GIC_FDT_IRQ_FLAGS_LEVEL_HI); |
91 | { | 82 | + qemu_fdt_setprop(s->fdt, name, "interrupt-names", |
92 | MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi | 83 | + interrupt_names, sizeof(interrupt_names)); |
93 | @@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi | 84 | + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", |
94 | } | 85 | + 2, MM_PMC_BBRAM_CTRL, |
95 | RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi | 86 | + 2, MM_PMC_BBRAM_CTRL_SIZE); |
96 | 87 | + qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); | |
97 | -# v8.1M CSEL and friends | 88 | + g_free(name); |
98 | -CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4 | ||
99 | - | ||
100 | # Data-processing (register-shifted register) | ||
101 | |||
102 | MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ | ||
103 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
104 | index XXXXXXX..XXXXXXX 100644 | ||
105 | --- a/target/arm/mve_helper.c | ||
106 | +++ b/target/arm/mve_helper.c | ||
107 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, | ||
108 | return rdm; | ||
109 | } | ||
110 | |||
111 | +uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
112 | +{ | ||
113 | + return do_sqrshl_d(n, -(int8_t)shift, false, NULL); | ||
114 | +} | 89 | +} |
115 | + | 90 | + |
116 | +uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) | 91 | static void fdt_nop_memory_nodes(void *fdt, Error **errp) |
92 | { | ||
93 | Error *err = NULL; | ||
94 | @@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s) | ||
95 | } | ||
96 | } | ||
97 | |||
98 | +static void bbram_attach_drive(XlnxBBRam *dev) | ||
117 | +{ | 99 | +{ |
118 | + return do_uqrshl_d(n, (int8_t)shift, false, NULL); | 100 | + DriveInfo *dinfo; |
101 | + BlockBackend *blk; | ||
102 | + | ||
103 | + dinfo = drive_get_by_index(IF_PFLASH, 0); | ||
104 | + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; | ||
105 | + if (blk) { | ||
106 | + qdev_prop_set_drive(DEVICE(dev), "drive", blk); | ||
107 | + } | ||
119 | +} | 108 | +} |
120 | + | 109 | + |
121 | uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | 110 | static void sd_plugin_card(SDHCIState *sd, DriveInfo *di) |
122 | { | 111 | { |
123 | return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); | 112 | BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; |
124 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | 113 | @@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine) |
125 | { | 114 | fdt_add_usb_xhci_nodes(s); |
126 | return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); | 115 | fdt_add_sd_nodes(s); |
116 | fdt_add_rtc_node(s); | ||
117 | + fdt_add_bbram_node(s); | ||
118 | fdt_add_cpu_nodes(s, psci_conduit); | ||
119 | fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); | ||
120 | fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); | ||
121 | @@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine) | ||
122 | memory_region_add_subregion_overlap(get_system_memory(), | ||
123 | 0, &s->soc.fpd.apu.mr, 0); | ||
124 | |||
125 | + /* Attach bbram backend, if given */ | ||
126 | + bbram_attach_drive(&s->soc.pmc.bbram); | ||
127 | + | ||
128 | /* Plugin SD cards. */ | ||
129 | for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) { | ||
130 | sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD)); | ||
131 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
132 | index XXXXXXX..XXXXXXX 100644 | ||
133 | --- a/hw/arm/xlnx-versal.c | ||
134 | +++ b/hw/arm/xlnx-versal.c | ||
135 | @@ -XXX,XX +XXX,XX @@ static void versal_create_xrams(Versal *s, qemu_irq *pic) | ||
136 | } | ||
127 | } | 137 | } |
138 | |||
139 | +static void versal_create_bbram(Versal *s, qemu_irq *pic) | ||
140 | +{ | ||
141 | + SysBusDevice *sbd; | ||
128 | + | 142 | + |
129 | +uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) | 143 | + object_initialize_child_with_props(OBJECT(s), "bbram", &s->pmc.bbram, |
130 | +{ | 144 | + sizeof(s->pmc.bbram), TYPE_XLNX_BBRAM, |
131 | + return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); | 145 | + &error_fatal, |
146 | + "crc-zpads", "0", | ||
147 | + NULL); | ||
148 | + sbd = SYS_BUS_DEVICE(&s->pmc.bbram); | ||
149 | + | ||
150 | + sysbus_realize(sbd, &error_fatal); | ||
151 | + memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL, | ||
152 | + sysbus_mmio_get_region(sbd, 0)); | ||
153 | + sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]); | ||
132 | +} | 154 | +} |
133 | + | 155 | + |
134 | +uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) | 156 | /* This takes the board allocated linear DDR memory and creates aliases |
135 | +{ | 157 | * for each split DDR range/aperture on the Versal address map. |
136 | + return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); | 158 | */ |
137 | +} | 159 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) |
138 | + | 160 | versal_create_sds(s, pic); |
139 | +/* Operate on 64-bit values, but saturate at 48 bits */ | 161 | versal_create_rtc(s, pic); |
140 | +static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, | 162 | versal_create_xrams(s, pic); |
141 | + bool round, uint32_t *sat) | 163 | + versal_create_bbram(s, pic); |
142 | +{ | 164 | versal_map_ddr(s); |
143 | + if (shift <= -48) { | 165 | versal_unimp(s); |
144 | + /* Rounding the sign bit always produces 0. */ | 166 | |
145 | + if (round) { | 167 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig |
146 | + return 0; | ||
147 | + } | ||
148 | + return src >> 63; | ||
149 | + } else if (shift < 0) { | ||
150 | + if (round) { | ||
151 | + src >>= -shift - 1; | ||
152 | + return (src >> 1) + (src & 1); | ||
153 | + } | ||
154 | + return src >> -shift; | ||
155 | + } else if (shift < 48) { | ||
156 | + int64_t val = src << shift; | ||
157 | + int64_t extval = sextract64(val, 0, 48); | ||
158 | + if (!sat || val == extval) { | ||
159 | + return extval; | ||
160 | + } | ||
161 | + } else if (!sat || src == 0) { | ||
162 | + return 0; | ||
163 | + } | ||
164 | + | ||
165 | + *sat = 1; | ||
166 | + return (1ULL << 47) - (src >= 0); | ||
167 | +} | ||
168 | + | ||
169 | +/* Operate on 64-bit values, but saturate at 48 bits */ | ||
170 | +static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, | ||
171 | + bool round, uint32_t *sat) | ||
172 | +{ | ||
173 | + uint64_t val, extval; | ||
174 | + | ||
175 | + if (shift <= -(48 + round)) { | ||
176 | + return 0; | ||
177 | + } else if (shift < 0) { | ||
178 | + if (round) { | ||
179 | + val = src >> (-shift - 1); | ||
180 | + val = (val >> 1) + (val & 1); | ||
181 | + } else { | ||
182 | + val = src >> -shift; | ||
183 | + } | ||
184 | + extval = extract64(val, 0, 48); | ||
185 | + if (!sat || val == extval) { | ||
186 | + return extval; | ||
187 | + } | ||
188 | + } else if (shift < 48) { | ||
189 | + uint64_t val = src << shift; | ||
190 | + uint64_t extval = extract64(val, 0, 48); | ||
191 | + if (!sat || val == extval) { | ||
192 | + return extval; | ||
193 | + } | ||
194 | + } else if (!sat || src == 0) { | ||
195 | + return 0; | ||
196 | + } | ||
197 | + | ||
198 | + *sat = 1; | ||
199 | + return MAKE_64BIT_MASK(0, 48); | ||
200 | +} | ||
201 | + | ||
202 | +uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
203 | +{ | ||
204 | + return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); | ||
205 | +} | ||
206 | + | ||
207 | +uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
208 | +{ | ||
209 | + return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); | ||
210 | +} | ||
211 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
212 | index XXXXXXX..XXXXXXX 100644 | 168 | index XXXXXXX..XXXXXXX 100644 |
213 | --- a/target/arm/translate.c | 169 | --- a/hw/arm/Kconfig |
214 | +++ b/target/arm/translate.c | 170 | +++ b/hw/arm/Kconfig |
215 | @@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) | 171 | @@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL |
216 | return do_mve_shl_ri(s, a, gen_urshr64_i64); | 172 | select XLNX_ZDMA |
217 | } | 173 | select XLNX_ZYNQMP |
218 | 174 | select OR_IRQ | |
219 | +static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn) | 175 | + select XLNX_BBRAM |
220 | +{ | 176 | |
221 | + TCGv_i64 rda; | 177 | config NPCM7XX |
222 | + TCGv_i32 rdalo, rdahi; | 178 | bool |
223 | + | ||
224 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
225 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | ||
226 | + return false; | ||
227 | + } | ||
228 | + if (a->rdahi == 15) { | ||
229 | + /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */ | ||
230 | + return false; | ||
231 | + } | ||
232 | + if (!dc_isar_feature(aa32_mve, s) || | ||
233 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | ||
234 | + a->rdahi == 13 || a->rm == 13 || a->rm == 15 || | ||
235 | + a->rm == a->rdahi || a->rm == a->rdalo) { | ||
236 | + /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */ | ||
237 | + unallocated_encoding(s); | ||
238 | + return true; | ||
239 | + } | ||
240 | + | ||
241 | + rda = tcg_temp_new_i64(); | ||
242 | + rdalo = load_reg(s, a->rdalo); | ||
243 | + rdahi = load_reg(s, a->rdahi); | ||
244 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); | ||
245 | + | ||
246 | + /* The helper takes care of the sign-extension of the low 8 bits of Rm */ | ||
247 | + fn(rda, cpu_env, rda, cpu_R[a->rm]); | ||
248 | + | ||
249 | + tcg_gen_extrl_i64_i32(rdalo, rda); | ||
250 | + tcg_gen_extrh_i64_i32(rdahi, rda); | ||
251 | + store_reg(s, a->rdalo, rdalo); | ||
252 | + store_reg(s, a->rdahi, rdahi); | ||
253 | + tcg_temp_free_i64(rda); | ||
254 | + | ||
255 | + return true; | ||
256 | +} | ||
257 | + | ||
258 | +static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
259 | +{ | ||
260 | + return do_mve_shl_rr(s, a, gen_helper_mve_ushll); | ||
261 | +} | ||
262 | + | ||
263 | +static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
264 | +{ | ||
265 | + return do_mve_shl_rr(s, a, gen_helper_mve_sshrl); | ||
266 | +} | ||
267 | + | ||
268 | +static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
269 | +{ | ||
270 | + return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll); | ||
271 | +} | ||
272 | + | ||
273 | +static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
274 | +{ | ||
275 | + return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl); | ||
276 | +} | ||
277 | + | ||
278 | +static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
279 | +{ | ||
280 | + return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48); | ||
281 | +} | ||
282 | + | ||
283 | +static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
284 | +{ | ||
285 | + return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48); | ||
286 | +} | ||
287 | + | ||
288 | /* | ||
289 | * Multiply and multiply accumulate | ||
290 | */ | ||
291 | -- | 179 | -- |
292 | 2.20.1 | 180 | 2.20.1 |
293 | 181 | ||
294 | 182 | diff view generated by jsdifflib |
1 | From: Maxim Uvarov <maxim.uvarov@linaro.org> | 1 | From: Tong Ho <tong.ho@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | qemu has 2 type of functions: shutdown and reboot. Shutdown | 3 | Connect the support for Versal eFUSE one-time field-programmable |
4 | function has to be used for machine shutdown. Otherwise we cause | 4 | bit array. |
5 | a reset with a bogus "cause" value, when we intended a shutdown. | 5 | |
6 | 6 | The command argument: | |
7 | Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org> | 7 | -drive if=pflash,index=1,... |
8 | Can be used to optionally connect the bit array to a | ||
9 | backend storage, such that field-programmed values | ||
10 | in one invocation can be made available to next | ||
11 | invocation. | ||
12 | |||
13 | The backend storage must be a seekable binary file, and | ||
14 | its size must be 3072 bytes or larger. A file with all | ||
15 | binary 0's is a 'blank'. | ||
16 | |||
17 | Signed-off-by: Tong Ho <tong.ho@xilinx.com> | ||
18 | Message-id: 20210917052400.1249094-7-tong.ho@xilinx.com | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org | ||
10 | [PMM: tweaked commit message] | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 21 | --- |
13 | hw/gpio/gpio_pwr.c | 2 +- | 22 | include/hw/arm/xlnx-versal.h | 10 +++++++ |
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | 23 | hw/arm/xlnx-versal-virt.c | 52 ++++++++++++++++++++++++++++++++++++ |
15 | 24 | hw/arm/xlnx-versal.c | 39 +++++++++++++++++++++++++++ | |
16 | diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c | 25 | hw/arm/Kconfig | 1 + |
17 | index XXXXXXX..XXXXXXX 100644 | 26 | 4 files changed, 102 insertions(+) |
18 | --- a/hw/gpio/gpio_pwr.c | 27 | |
19 | +++ b/hw/gpio/gpio_pwr.c | 28 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h |
20 | @@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level) | 29 | index XXXXXXX..XXXXXXX 100644 |
21 | static void gpio_pwr_shutdown(void *opaque, int n, int level) | 30 | --- a/include/hw/arm/xlnx-versal.h |
31 | +++ b/include/hw/arm/xlnx-versal.h | ||
32 | @@ -XXX,XX +XXX,XX @@ | ||
33 | #include "hw/usb/xlnx-usb-subsystem.h" | ||
34 | #include "hw/misc/xlnx-versal-xramc.h" | ||
35 | #include "hw/nvram/xlnx-bbram.h" | ||
36 | +#include "hw/nvram/xlnx-versal-efuse.h" | ||
37 | |||
38 | #define TYPE_XLNX_VERSAL "xlnx-versal" | ||
39 | OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) | ||
40 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
41 | |||
42 | XlnxZynqMPRTC rtc; | ||
43 | XlnxBBRam bbram; | ||
44 | + XlnxEFuse efuse; | ||
45 | + XlnxVersalEFuseCtrl efuse_ctrl; | ||
46 | + XlnxVersalEFuseCache efuse_cache; | ||
47 | } pmc; | ||
48 | |||
49 | struct { | ||
50 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
51 | #define VERSAL_BBRAM_APB_IRQ_0 121 | ||
52 | #define VERSAL_RTC_APB_ERR_IRQ 121 | ||
53 | #define VERSAL_SD0_IRQ_0 126 | ||
54 | +#define VERSAL_EFUSE_IRQ 139 | ||
55 | #define VERSAL_RTC_ALARM_IRQ 142 | ||
56 | #define VERSAL_RTC_SECONDS_IRQ 143 | ||
57 | |||
58 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
59 | #define MM_PMC_SD0_SIZE 0x10000 | ||
60 | #define MM_PMC_BBRAM_CTRL 0xf11f0000 | ||
61 | #define MM_PMC_BBRAM_CTRL_SIZE 0x00050 | ||
62 | +#define MM_PMC_EFUSE_CTRL 0xf1240000 | ||
63 | +#define MM_PMC_EFUSE_CTRL_SIZE 0x00104 | ||
64 | +#define MM_PMC_EFUSE_CACHE 0xf1250000 | ||
65 | +#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00 | ||
66 | + | ||
67 | #define MM_PMC_CRP 0xf1260000U | ||
68 | #define MM_PMC_CRP_SIZE 0x10000 | ||
69 | #define MM_PMC_RTC 0xf12a0000 | ||
70 | diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/hw/arm/xlnx-versal-virt.c | ||
73 | +++ b/hw/arm/xlnx-versal-virt.c | ||
74 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_bbram_node(VersalVirt *s) | ||
75 | g_free(name); | ||
76 | } | ||
77 | |||
78 | +static void fdt_add_efuse_ctrl_node(VersalVirt *s) | ||
79 | +{ | ||
80 | + const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CTRL; | ||
81 | + const char interrupt_names[] = "pmc_efuse"; | ||
82 | + char *name = g_strdup_printf("/pmc_efuse@%x", MM_PMC_EFUSE_CTRL); | ||
83 | + | ||
84 | + qemu_fdt_add_subnode(s->fdt, name); | ||
85 | + | ||
86 | + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", | ||
87 | + GIC_FDT_IRQ_TYPE_SPI, VERSAL_EFUSE_IRQ, | ||
88 | + GIC_FDT_IRQ_FLAGS_LEVEL_HI); | ||
89 | + qemu_fdt_setprop(s->fdt, name, "interrupt-names", | ||
90 | + interrupt_names, sizeof(interrupt_names)); | ||
91 | + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", | ||
92 | + 2, MM_PMC_EFUSE_CTRL, | ||
93 | + 2, MM_PMC_EFUSE_CTRL_SIZE); | ||
94 | + qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); | ||
95 | + g_free(name); | ||
96 | +} | ||
97 | + | ||
98 | +static void fdt_add_efuse_cache_node(VersalVirt *s) | ||
99 | +{ | ||
100 | + const char compat[] = TYPE_XLNX_VERSAL_EFUSE_CACHE; | ||
101 | + char *name = g_strdup_printf("/xlnx_pmc_efuse_cache@%x", | ||
102 | + MM_PMC_EFUSE_CACHE); | ||
103 | + | ||
104 | + qemu_fdt_add_subnode(s->fdt, name); | ||
105 | + | ||
106 | + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", | ||
107 | + 2, MM_PMC_EFUSE_CACHE, | ||
108 | + 2, MM_PMC_EFUSE_CACHE_SIZE); | ||
109 | + qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); | ||
110 | + g_free(name); | ||
111 | +} | ||
112 | + | ||
113 | static void fdt_nop_memory_nodes(void *fdt, Error **errp) | ||
22 | { | 114 | { |
23 | if (level) { | 115 | Error *err = NULL; |
24 | - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | 116 | @@ -XXX,XX +XXX,XX @@ static void bbram_attach_drive(XlnxBBRam *dev) |
25 | + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | ||
26 | } | 117 | } |
27 | } | 118 | } |
28 | 119 | ||
120 | +static void efuse_attach_drive(XlnxEFuse *dev) | ||
121 | +{ | ||
122 | + DriveInfo *dinfo; | ||
123 | + BlockBackend *blk; | ||
124 | + | ||
125 | + dinfo = drive_get_by_index(IF_PFLASH, 1); | ||
126 | + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; | ||
127 | + if (blk) { | ||
128 | + qdev_prop_set_drive(DEVICE(dev), "drive", blk); | ||
129 | + } | ||
130 | +} | ||
131 | + | ||
132 | static void sd_plugin_card(SDHCIState *sd, DriveInfo *di) | ||
133 | { | ||
134 | BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; | ||
135 | @@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine) | ||
136 | fdt_add_sd_nodes(s); | ||
137 | fdt_add_rtc_node(s); | ||
138 | fdt_add_bbram_node(s); | ||
139 | + fdt_add_efuse_ctrl_node(s); | ||
140 | + fdt_add_efuse_cache_node(s); | ||
141 | fdt_add_cpu_nodes(s, psci_conduit); | ||
142 | fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); | ||
143 | fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); | ||
144 | @@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine) | ||
145 | /* Attach bbram backend, if given */ | ||
146 | bbram_attach_drive(&s->soc.pmc.bbram); | ||
147 | |||
148 | + /* Attach efuse backend, if given */ | ||
149 | + efuse_attach_drive(&s->soc.pmc.efuse); | ||
150 | + | ||
151 | /* Plugin SD cards. */ | ||
152 | for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) { | ||
153 | sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD)); | ||
154 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
155 | index XXXXXXX..XXXXXXX 100644 | ||
156 | --- a/hw/arm/xlnx-versal.c | ||
157 | +++ b/hw/arm/xlnx-versal.c | ||
158 | @@ -XXX,XX +XXX,XX @@ static void versal_create_bbram(Versal *s, qemu_irq *pic) | ||
159 | sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]); | ||
160 | } | ||
161 | |||
162 | +static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base) | ||
163 | +{ | ||
164 | + SysBusDevice *part = SYS_BUS_DEVICE(dev); | ||
165 | + | ||
166 | + object_property_set_link(OBJECT(part), "efuse", | ||
167 | + OBJECT(&s->pmc.efuse), &error_abort); | ||
168 | + | ||
169 | + sysbus_realize(part, &error_abort); | ||
170 | + memory_region_add_subregion(&s->mr_ps, base, | ||
171 | + sysbus_mmio_get_region(part, 0)); | ||
172 | +} | ||
173 | + | ||
174 | +static void versal_create_efuse(Versal *s, qemu_irq *pic) | ||
175 | +{ | ||
176 | + Object *bits = OBJECT(&s->pmc.efuse); | ||
177 | + Object *ctrl = OBJECT(&s->pmc.efuse_ctrl); | ||
178 | + Object *cache = OBJECT(&s->pmc.efuse_cache); | ||
179 | + | ||
180 | + object_initialize_child(OBJECT(s), "efuse-ctrl", &s->pmc.efuse_ctrl, | ||
181 | + TYPE_XLNX_VERSAL_EFUSE_CTRL); | ||
182 | + | ||
183 | + object_initialize_child(OBJECT(s), "efuse-cache", &s->pmc.efuse_cache, | ||
184 | + TYPE_XLNX_VERSAL_EFUSE_CACHE); | ||
185 | + | ||
186 | + object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, | ||
187 | + sizeof(s->pmc.efuse), | ||
188 | + TYPE_XLNX_EFUSE, &error_abort, | ||
189 | + "efuse-nr", "3", | ||
190 | + "efuse-size", "8192", | ||
191 | + NULL); | ||
192 | + | ||
193 | + qdev_realize(DEVICE(bits), NULL, &error_abort); | ||
194 | + versal_realize_efuse_part(s, ctrl, MM_PMC_EFUSE_CTRL); | ||
195 | + versal_realize_efuse_part(s, cache, MM_PMC_EFUSE_CACHE); | ||
196 | + | ||
197 | + sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]); | ||
198 | +} | ||
199 | + | ||
200 | /* This takes the board allocated linear DDR memory and creates aliases | ||
201 | * for each split DDR range/aperture on the Versal address map. | ||
202 | */ | ||
203 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) | ||
204 | versal_create_rtc(s, pic); | ||
205 | versal_create_xrams(s, pic); | ||
206 | versal_create_bbram(s, pic); | ||
207 | + versal_create_efuse(s, pic); | ||
208 | versal_map_ddr(s); | ||
209 | versal_unimp(s); | ||
210 | |||
211 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
212 | index XXXXXXX..XXXXXXX 100644 | ||
213 | --- a/hw/arm/Kconfig | ||
214 | +++ b/hw/arm/Kconfig | ||
215 | @@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL | ||
216 | select XLNX_ZYNQMP | ||
217 | select OR_IRQ | ||
218 | select XLNX_BBRAM | ||
219 | + select XLNX_EFUSE_VERSAL | ||
220 | |||
221 | config NPCM7XX | ||
222 | bool | ||
29 | -- | 223 | -- |
30 | 2.20.1 | 224 | 2.20.1 |
31 | 225 | ||
32 | 226 | diff view generated by jsdifflib |
1 | The MVE extension to v8.1M includes some new shift instructions which | 1 | From: Tong Ho <tong.ho@xilinx.com> |
---|---|---|---|
2 | sit entirely within the non-coprocessor part of the encoding space | ||
3 | and which operate only on general-purpose registers. They take up | ||
4 | the space which was previously UNPREDICTABLE MOVS and ORRS encodings | ||
5 | with Rm == 13 or 15. | ||
6 | 2 | ||
7 | Implement the long shifts by immediate, which perform shifts on a | 3 | Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM) |
8 | pair of general-purpose registers treated as a 64-bit quantity, with | ||
9 | an immediate shift count between 1 and 32. | ||
10 | 4 | ||
11 | Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for | 5 | The command argument: |
12 | the Rm==13,15 case, we need to explicitly emit code to UNDEF for the | 6 | -drive if=pflash,index=2,... |
13 | cases where v8.1M now requires that. (Trying to change MOVS and ORRS | 7 | Can be used to optionally connect the bbram to a backend |
14 | is too difficult, because the functions that generate the code are | 8 | storage, such that field-programmed values in one |
15 | shared between a dozen different kinds of arithmetic or logical | 9 | invocation can be made available to next invocation. |
16 | instruction for all A32, T16 and T32 encodings, and for some insns | ||
17 | and some encodings Rm==13,15 are valid.) | ||
18 | 10 | ||
19 | We make the helper functions we need for UQSHLL and SQSHLL take | 11 | The backend storage must be a seekable binary file, and |
20 | a 32-bit value which the helper casts to int8_t because we'll need | 12 | its size must be 36 bytes or larger. A file with all |
21 | these helpers also for the shift-by-register insns, where the shift | 13 | binary 0's is a 'blank'. |
22 | count might be < 0 or > 32. | ||
23 | 14 | ||
15 | Signed-off-by: Tong Ho <tong.ho@xilinx.com> | ||
16 | Message-id: 20210917052400.1249094-8-tong.ho@xilinx.com | ||
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
25 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
26 | Message-id: 20210628135835.6690-16-peter.maydell@linaro.org | ||
27 | --- | 19 | --- |
28 | target/arm/helper-mve.h | 3 ++ | 20 | include/hw/arm/xlnx-zynqmp.h | 2 ++ |
29 | target/arm/translate.h | 1 + | 21 | hw/arm/xlnx-zcu102.c | 15 +++++++++++++++ |
30 | target/arm/t32.decode | 28 +++++++++++++ | 22 | hw/arm/xlnx-zynqmp.c | 20 ++++++++++++++++++++ |
31 | target/arm/mve_helper.c | 10 +++++ | 23 | hw/Kconfig | 1 + |
32 | target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++ | 24 | 4 files changed, 38 insertions(+) |
33 | 5 files changed, 132 insertions(+) | ||
34 | 25 | ||
35 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | 26 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h |
36 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/target/arm/helper-mve.h | 28 | --- a/include/hw/arm/xlnx-zynqmp.h |
38 | +++ b/target/arm/helper-mve.h | 29 | +++ b/include/hw/arm/xlnx-zynqmp.h |
39 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 30 | @@ -XXX,XX +XXX,XX @@ |
40 | DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 31 | #include "qom/object.h" |
41 | 32 | #include "net/can_emu.h" | |
42 | DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) | 33 | #include "hw/dma/xlnx_csu_dma.h" |
34 | +#include "hw/nvram/xlnx-bbram.h" | ||
35 | |||
36 | #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" | ||
37 | OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) | ||
38 | @@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState { | ||
39 | |||
40 | MemoryRegion *ddr_ram; | ||
41 | MemoryRegion ddr_ram_low, ddr_ram_high; | ||
42 | + XlnxBBRam bbram; | ||
43 | |||
44 | MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS]; | ||
45 | |||
46 | diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/hw/arm/xlnx-zcu102.c | ||
49 | +++ b/hw/arm/xlnx-zcu102.c | ||
50 | @@ -XXX,XX +XXX,XX @@ static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt) | ||
51 | } | ||
52 | } | ||
53 | |||
54 | +static void bbram_attach_drive(XlnxBBRam *dev) | ||
55 | +{ | ||
56 | + DriveInfo *dinfo; | ||
57 | + BlockBackend *blk; | ||
43 | + | 58 | + |
44 | +DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | 59 | + dinfo = drive_get_by_index(IF_PFLASH, 2); |
45 | +DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | 60 | + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; |
46 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 61 | + if (blk) { |
47 | index XXXXXXX..XXXXXXX 100644 | 62 | + qdev_prop_set_drive(DEVICE(dev), "drive", blk); |
48 | --- a/target/arm/translate.h | 63 | + } |
49 | +++ b/target/arm/translate.h | ||
50 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); | ||
51 | typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
52 | typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
53 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
54 | +typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | ||
55 | |||
56 | /** | ||
57 | * arm_tbflags_from_tb: | ||
58 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/t32.decode | ||
61 | +++ b/target/arm/t32.decode | ||
62 | @@ -XXX,XX +XXX,XX @@ | ||
63 | &mcr !extern cp opc1 crn crm opc2 rt | ||
64 | &mcrr !extern cp opc1 crm rt rt2 | ||
65 | |||
66 | +&mve_shl_ri rdalo rdahi shim | ||
67 | + | ||
68 | +# rdahi: bits [3:1] from insn, bit 0 is 1 | ||
69 | +# rdalo: bits [3:1] from insn, bit 0 is 0 | ||
70 | +%rdahi_9 9:3 !function=times_2_plus_1 | ||
71 | +%rdalo_17 17:3 !function=times_2 | ||
72 | + | ||
73 | # Data-processing (register) | ||
74 | |||
75 | %imm5_12_6 12:3 6:2 | ||
76 | @@ -XXX,XX +XXX,XX @@ | ||
77 | @S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \ | ||
78 | &s_rrr_shi shim=%imm5_12_6 s=1 rd=0 | ||
79 | |||
80 | +@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \ | ||
81 | + &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
82 | + | ||
83 | { | ||
84 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | ||
85 | AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi | ||
86 | } | ||
87 | BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
88 | { | ||
89 | + # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS | ||
90 | + # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE | ||
91 | + # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that | ||
92 | + # they explicitly call unallocated_encoding() for cases that must UNDEF | ||
93 | + # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting | ||
94 | + # the rest fall through (where ORR_rrri and MOV_rxri will end up | ||
95 | + # handling them as r13 and r15 accesses with the same semantics as A32). | ||
96 | + [ | ||
97 | + LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
98 | + LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
99 | + ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
100 | + | ||
101 | + UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
102 | + URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
103 | + SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
104 | + SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
105 | + ] | ||
106 | + | ||
107 | MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi | ||
108 | ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi | ||
109 | } | ||
110 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
111 | index XXXXXXX..XXXXXXX 100644 | ||
112 | --- a/target/arm/mve_helper.c | ||
113 | +++ b/target/arm/mve_helper.c | ||
114 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, | ||
115 | mve_advance_vpt(env); | ||
116 | return rdm; | ||
117 | } | ||
118 | + | ||
119 | +uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
120 | +{ | ||
121 | + return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); | ||
122 | +} | 64 | +} |
123 | + | 65 | + |
124 | +uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | 66 | static void xlnx_zcu102_init(MachineState *machine) |
67 | { | ||
68 | XlnxZCU102 *s = ZCU102_MACHINE(machine); | ||
69 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine) | ||
70 | |||
71 | qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); | ||
72 | |||
73 | + /* Attach bbram backend, if given */ | ||
74 | + bbram_attach_drive(&s->soc.bbram); | ||
75 | + | ||
76 | /* Create and plug in the SD cards */ | ||
77 | for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { | ||
78 | BusState *bus; | ||
79 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | ||
80 | index XXXXXXX..XXXXXXX 100644 | ||
81 | --- a/hw/arm/xlnx-zynqmp.c | ||
82 | +++ b/hw/arm/xlnx-zynqmp.c | ||
83 | @@ -XXX,XX +XXX,XX @@ | ||
84 | #define RTC_ADDR 0xffa60000 | ||
85 | #define RTC_IRQ 26 | ||
86 | |||
87 | +#define BBRAM_ADDR 0xffcd0000 | ||
88 | +#define BBRAM_IRQ 11 | ||
89 | + | ||
90 | #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ | ||
91 | |||
92 | static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { | ||
93 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s, | ||
94 | qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal); | ||
95 | } | ||
96 | |||
97 | +static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic) | ||
125 | +{ | 98 | +{ |
126 | + return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); | 99 | + SysBusDevice *sbd; |
127 | +} | ||
128 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
129 | index XXXXXXX..XXXXXXX 100644 | ||
130 | --- a/target/arm/translate.c | ||
131 | +++ b/target/arm/translate.c | ||
132 | @@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a) | ||
133 | return true; | ||
134 | } | ||
135 | |||
136 | +/* | ||
137 | + * v8.1M MVE wide-shifts | ||
138 | + */ | ||
139 | +static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a, | ||
140 | + WideShiftImmFn *fn) | ||
141 | +{ | ||
142 | + TCGv_i64 rda; | ||
143 | + TCGv_i32 rdalo, rdahi; | ||
144 | + | 100 | + |
145 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | 101 | + object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram, |
146 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | 102 | + sizeof(s->bbram), TYPE_XLNX_BBRAM, |
147 | + return false; | 103 | + &error_fatal, |
148 | + } | 104 | + "crc-zpads", "1", |
149 | + if (a->rdahi == 15) { | 105 | + NULL); |
150 | + /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */ | 106 | + sbd = SYS_BUS_DEVICE(&s->bbram); |
151 | + return false; | ||
152 | + } | ||
153 | + if (!dc_isar_feature(aa32_mve, s) || | ||
154 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | ||
155 | + a->rdahi == 13) { | ||
156 | + /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */ | ||
157 | + unallocated_encoding(s); | ||
158 | + return true; | ||
159 | + } | ||
160 | + | 107 | + |
161 | + if (a->shim == 0) { | 108 | + sysbus_realize(sbd, &error_fatal); |
162 | + a->shim = 32; | 109 | + sysbus_mmio_map(sbd, 0, BBRAM_ADDR); |
163 | + } | 110 | + sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]); |
164 | + | ||
165 | + rda = tcg_temp_new_i64(); | ||
166 | + rdalo = load_reg(s, a->rdalo); | ||
167 | + rdahi = load_reg(s, a->rdahi); | ||
168 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); | ||
169 | + | ||
170 | + fn(rda, rda, a->shim); | ||
171 | + | ||
172 | + tcg_gen_extrl_i64_i32(rdalo, rda); | ||
173 | + tcg_gen_extrh_i64_i32(rdahi, rda); | ||
174 | + store_reg(s, a->rdalo, rdalo); | ||
175 | + store_reg(s, a->rdahi, rdahi); | ||
176 | + tcg_temp_free_i64(rda); | ||
177 | + | ||
178 | + return true; | ||
179 | +} | 111 | +} |
180 | + | 112 | + |
181 | +static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a) | 113 | static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) |
182 | +{ | 114 | { |
183 | + return do_mve_shl_ri(s, a, tcg_gen_sari_i64); | 115 | static const struct UnimpInfo { |
184 | +} | 116 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) |
185 | + | 117 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR); |
186 | +static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a) | 118 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); |
187 | +{ | 119 | |
188 | + return do_mve_shl_ri(s, a, tcg_gen_shli_i64); | 120 | + xlnx_zynqmp_create_bbram(s, gic_spi); |
189 | +} | 121 | xlnx_zynqmp_create_unimp_mmio(s); |
190 | + | 122 | |
191 | +static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a) | 123 | for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { |
192 | +{ | 124 | diff --git a/hw/Kconfig b/hw/Kconfig |
193 | + return do_mve_shl_ri(s, a, tcg_gen_shri_i64); | 125 | index XXXXXXX..XXXXXXX 100644 |
194 | +} | 126 | --- a/hw/Kconfig |
195 | + | 127 | +++ b/hw/Kconfig |
196 | +static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) | 128 | @@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP |
197 | +{ | 129 | select REGISTER |
198 | + gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift)); | 130 | select CAN_BUS |
199 | +} | 131 | select PTIMER |
200 | + | 132 | + select XLNX_BBRAM |
201 | +static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
202 | +{ | ||
203 | + return do_mve_shl_ri(s, a, gen_mve_sqshll); | ||
204 | +} | ||
205 | + | ||
206 | +static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) | ||
207 | +{ | ||
208 | + gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift)); | ||
209 | +} | ||
210 | + | ||
211 | +static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
212 | +{ | ||
213 | + return do_mve_shl_ri(s, a, gen_mve_uqshll); | ||
214 | +} | ||
215 | + | ||
216 | +static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
217 | +{ | ||
218 | + return do_mve_shl_ri(s, a, gen_srshr64_i64); | ||
219 | +} | ||
220 | + | ||
221 | +static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
222 | +{ | ||
223 | + return do_mve_shl_ri(s, a, gen_urshr64_i64); | ||
224 | +} | ||
225 | + | ||
226 | /* | ||
227 | * Multiply and multiply accumulate | ||
228 | */ | ||
229 | -- | 133 | -- |
230 | 2.20.1 | 134 | 2.20.1 |
231 | 135 | ||
232 | 136 | diff view generated by jsdifflib |
1 | Implement the MVE saturating shift-right-and-narrow insns | 1 | From: Tong Ho <tong.ho@xilinx.com> |
---|---|---|---|
2 | VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN. | ||
3 | 2 | ||
4 | do_srshr() is borrowed from sve_helper.c. | 3 | Connect the support for ZynqMP eFUSE one-time field-programmable |
4 | bit array. | ||
5 | 5 | ||
6 | The command argument: | ||
7 | -drive if=pflash,index=3,... | ||
8 | Can be used to optionally connect the bit array to a | ||
9 | backend storage, such that field-programmed values | ||
10 | in one invocation can be made available to next | ||
11 | invocation. | ||
12 | |||
13 | The backend storage must be a seekable binary file, and | ||
14 | its size must be 768 bytes or larger. A file with all | ||
15 | binary 0's is a 'blank'. | ||
16 | |||
17 | Signed-off-by: Tong Ho <tong.ho@xilinx.com> | ||
18 | Message-id: 20210917052400.1249094-9-tong.ho@xilinx.com | ||
19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20210628135835.6690-13-peter.maydell@linaro.org | ||
9 | --- | 21 | --- |
10 | target/arm/helper-mve.h | 30 +++++++++++ | 22 | include/hw/arm/xlnx-zynqmp.h | 3 +++ |
11 | target/arm/mve.decode | 28 ++++++++++ | 23 | hw/arm/xlnx-zcu102.c | 15 +++++++++++++++ |
12 | target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++ | 24 | hw/arm/xlnx-zynqmp.c | 29 +++++++++++++++++++++++++++++ |
13 | target/arm/translate-mve.c | 12 +++++ | 25 | hw/Kconfig | 1 + |
14 | 4 files changed, 174 insertions(+) | 26 | 4 files changed, 48 insertions(+) |
15 | 27 | ||
16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | 28 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h |
17 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/helper-mve.h | 30 | --- a/include/hw/arm/xlnx-zynqmp.h |
19 | +++ b/target/arm/helper-mve.h | 31 | +++ b/include/hw/arm/xlnx-zynqmp.h |
20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 32 | @@ -XXX,XX +XXX,XX @@ |
21 | DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 33 | #include "net/can_emu.h" |
22 | DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 34 | #include "hw/dma/xlnx_csu_dma.h" |
23 | DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 35 | #include "hw/nvram/xlnx-bbram.h" |
24 | + | 36 | +#include "hw/nvram/xlnx-zynqmp-efuse.h" |
25 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 37 | |
26 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 38 | #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" |
27 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 39 | OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) |
28 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 40 | @@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState { |
29 | + | 41 | MemoryRegion *ddr_ram; |
30 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 42 | MemoryRegion ddr_ram_low, ddr_ram_high; |
31 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 43 | XlnxBBRam bbram; |
32 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 44 | + XlnxEFuse efuse; |
33 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 45 | + XlnxZynqMPEFuse efuse_ctrl; |
34 | + | 46 | |
35 | +DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 47 | MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS]; |
36 | +DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 48 | |
37 | +DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 49 | diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c |
38 | +DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
39 | + | ||
40 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
41 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
42 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
43 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
44 | + | ||
45 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
46 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
47 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
48 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
49 | + | ||
50 | +DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
51 | +DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
52 | +DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
53 | +DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
54 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
55 | index XXXXXXX..XXXXXXX 100644 | 50 | index XXXXXXX..XXXXXXX 100644 |
56 | --- a/target/arm/mve.decode | 51 | --- a/hw/arm/xlnx-zcu102.c |
57 | +++ b/target/arm/mve.decode | 52 | +++ b/hw/arm/xlnx-zcu102.c |
58 | @@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b | 53 | @@ -XXX,XX +XXX,XX @@ static void bbram_attach_drive(XlnxBBRam *dev) |
59 | VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h | ||
60 | VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b | ||
61 | VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h | ||
62 | + | ||
63 | +VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b | ||
64 | +VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h | ||
65 | +VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b | ||
66 | +VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h | ||
67 | +VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b | ||
68 | +VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h | ||
69 | +VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b | ||
70 | +VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h | ||
71 | + | ||
72 | +VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b | ||
73 | +VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h | ||
74 | +VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b | ||
75 | +VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h | ||
76 | + | ||
77 | +VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b | ||
78 | +VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h | ||
79 | +VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b | ||
80 | +VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h | ||
81 | +VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b | ||
82 | +VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h | ||
83 | +VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b | ||
84 | +VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h | ||
85 | + | ||
86 | +VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b | ||
87 | +VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h | ||
88 | +VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b | ||
89 | +VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h | ||
90 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
91 | index XXXXXXX..XXXXXXX 100644 | ||
92 | --- a/target/arm/mve_helper.c | ||
93 | +++ b/target/arm/mve_helper.c | ||
94 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh) | ||
95 | } | 54 | } |
96 | } | 55 | } |
97 | 56 | ||
98 | +static inline int64_t do_srshr(int64_t x, unsigned sh) | 57 | +static void efuse_attach_drive(XlnxEFuse *dev) |
99 | +{ | 58 | +{ |
100 | + if (likely(sh < 64)) { | 59 | + DriveInfo *dinfo; |
101 | + return (x >> sh) + ((x >> (sh - 1)) & 1); | 60 | + BlockBackend *blk; |
102 | + } else { | 61 | + |
103 | + /* Rounding the sign bit always produces 0. */ | 62 | + dinfo = drive_get_by_index(IF_PFLASH, 3); |
104 | + return 0; | 63 | + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; |
64 | + if (blk) { | ||
65 | + qdev_prop_set_drive(DEVICE(dev), "drive", blk); | ||
105 | + } | 66 | + } |
106 | +} | 67 | +} |
107 | + | 68 | + |
108 | DO_VSHRN_ALL(vshrn, DO_SHR) | 69 | static void xlnx_zcu102_init(MachineState *machine) |
109 | DO_VSHRN_ALL(vrshrn, do_urshr) | 70 | { |
71 | XlnxZCU102 *s = ZCU102_MACHINE(machine); | ||
72 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine) | ||
73 | /* Attach bbram backend, if given */ | ||
74 | bbram_attach_drive(&s->soc.bbram); | ||
75 | |||
76 | + /* Attach efuse backend, if given */ | ||
77 | + efuse_attach_drive(&s->soc.efuse); | ||
110 | + | 78 | + |
111 | +static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, | 79 | /* Create and plug in the SD cards */ |
112 | + bool *satp) | 80 | for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { |
81 | BusState *bus; | ||
82 | diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c | ||
83 | index XXXXXXX..XXXXXXX 100644 | ||
84 | --- a/hw/arm/xlnx-zynqmp.c | ||
85 | +++ b/hw/arm/xlnx-zynqmp.c | ||
86 | @@ -XXX,XX +XXX,XX @@ | ||
87 | #define BBRAM_ADDR 0xffcd0000 | ||
88 | #define BBRAM_IRQ 11 | ||
89 | |||
90 | +#define EFUSE_ADDR 0xffcc0000 | ||
91 | +#define EFUSE_IRQ 87 | ||
92 | + | ||
93 | #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ | ||
94 | |||
95 | static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { | ||
96 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic) | ||
97 | sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]); | ||
98 | } | ||
99 | |||
100 | +static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic) | ||
113 | +{ | 101 | +{ |
114 | + if (val > max) { | 102 | + Object *bits = OBJECT(&s->efuse); |
115 | + *satp = true; | 103 | + Object *ctrl = OBJECT(&s->efuse_ctrl); |
116 | + return max; | 104 | + SysBusDevice *sbd; |
117 | + } else if (val < min) { | 105 | + |
118 | + *satp = true; | 106 | + object_initialize_child(OBJECT(s), "efuse-ctrl", &s->efuse_ctrl, |
119 | + return min; | 107 | + TYPE_XLNX_ZYNQMP_EFUSE); |
120 | + } else { | 108 | + |
121 | + return val; | 109 | + object_initialize_child_with_props(ctrl, "xlnx-efuse@0", bits, |
122 | + } | 110 | + sizeof(s->efuse), |
111 | + TYPE_XLNX_EFUSE, &error_abort, | ||
112 | + "efuse-nr", "3", | ||
113 | + "efuse-size", "2048", | ||
114 | + NULL); | ||
115 | + | ||
116 | + qdev_realize(DEVICE(bits), NULL, &error_abort); | ||
117 | + object_property_set_link(ctrl, "efuse", bits, &error_abort); | ||
118 | + | ||
119 | + sbd = SYS_BUS_DEVICE(ctrl); | ||
120 | + sysbus_realize(sbd, &error_abort); | ||
121 | + sysbus_mmio_map(sbd, 0, EFUSE_ADDR); | ||
122 | + sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]); | ||
123 | +} | 123 | +} |
124 | + | 124 | + |
125 | +/* Saturating narrowing right shifts */ | 125 | static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) |
126 | +#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ | 126 | { |
127 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | 127 | static const struct UnimpInfo { |
128 | + void *vm, uint32_t shift) \ | 128 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) |
129 | + { \ | 129 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]); |
130 | + LTYPE *m = vm; \ | 130 | |
131 | + TYPE *d = vd; \ | 131 | xlnx_zynqmp_create_bbram(s, gic_spi); |
132 | + uint16_t mask = mve_element_mask(env); \ | 132 | + xlnx_zynqmp_create_efuse(s, gic_spi); |
133 | + bool qc = false; \ | 133 | xlnx_zynqmp_create_unimp_mmio(s); |
134 | + unsigned le; \ | 134 | |
135 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | 135 | for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { |
136 | + bool sat = false; \ | 136 | diff --git a/hw/Kconfig b/hw/Kconfig |
137 | + TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ | ||
138 | + mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ | ||
139 | + qc |= sat && (mask & 1 << (TOP * ESIZE)); \ | ||
140 | + } \ | ||
141 | + if (qc) { \ | ||
142 | + env->vfp.qc[0] = qc; \ | ||
143 | + } \ | ||
144 | + mve_advance_vpt(env); \ | ||
145 | + } | ||
146 | + | ||
147 | +#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ | ||
148 | + DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ | ||
149 | + DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) | ||
150 | + | ||
151 | +#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ | ||
152 | + DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ | ||
153 | + DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) | ||
154 | + | ||
155 | +#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ | ||
156 | + DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ | ||
157 | + DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) | ||
158 | + | ||
159 | +#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ | ||
160 | + DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ | ||
161 | + DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) | ||
162 | + | ||
163 | +#define DO_SHRN_SB(N, M, SATP) \ | ||
164 | + do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) | ||
165 | +#define DO_SHRN_UB(N, M, SATP) \ | ||
166 | + do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) | ||
167 | +#define DO_SHRUN_B(N, M, SATP) \ | ||
168 | + do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) | ||
169 | + | ||
170 | +#define DO_SHRN_SH(N, M, SATP) \ | ||
171 | + do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) | ||
172 | +#define DO_SHRN_UH(N, M, SATP) \ | ||
173 | + do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) | ||
174 | +#define DO_SHRUN_H(N, M, SATP) \ | ||
175 | + do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) | ||
176 | + | ||
177 | +#define DO_RSHRN_SB(N, M, SATP) \ | ||
178 | + do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) | ||
179 | +#define DO_RSHRN_UB(N, M, SATP) \ | ||
180 | + do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) | ||
181 | +#define DO_RSHRUN_B(N, M, SATP) \ | ||
182 | + do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) | ||
183 | + | ||
184 | +#define DO_RSHRN_SH(N, M, SATP) \ | ||
185 | + do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) | ||
186 | +#define DO_RSHRN_UH(N, M, SATP) \ | ||
187 | + do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) | ||
188 | +#define DO_RSHRUN_H(N, M, SATP) \ | ||
189 | + do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) | ||
190 | + | ||
191 | +DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) | ||
192 | +DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) | ||
193 | +DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) | ||
194 | +DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) | ||
195 | +DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) | ||
196 | +DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) | ||
197 | + | ||
198 | +DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) | ||
199 | +DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) | ||
200 | +DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) | ||
201 | +DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) | ||
202 | +DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) | ||
203 | +DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) | ||
204 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
205 | index XXXXXXX..XXXXXXX 100644 | 137 | index XXXXXXX..XXXXXXX 100644 |
206 | --- a/target/arm/translate-mve.c | 138 | --- a/hw/Kconfig |
207 | +++ b/target/arm/translate-mve.c | 139 | +++ b/hw/Kconfig |
208 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb) | 140 | @@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP |
209 | DO_2SHIFT_N(VSHRNT, vshrnt) | 141 | select CAN_BUS |
210 | DO_2SHIFT_N(VRSHRNB, vrshrnb) | 142 | select PTIMER |
211 | DO_2SHIFT_N(VRSHRNT, vrshrnt) | 143 | select XLNX_BBRAM |
212 | +DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s) | 144 | + select XLNX_EFUSE_ZYNQMP |
213 | +DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s) | ||
214 | +DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u) | ||
215 | +DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u) | ||
216 | +DO_2SHIFT_N(VQSHRUNB, vqshrunb) | ||
217 | +DO_2SHIFT_N(VQSHRUNT, vqshrunt) | ||
218 | +DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s) | ||
219 | +DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s) | ||
220 | +DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u) | ||
221 | +DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u) | ||
222 | +DO_2SHIFT_N(VQRSHRUNB, vqrshrunb) | ||
223 | +DO_2SHIFT_N(VQRSHRUNT, vqrshrunt) | ||
224 | -- | 145 | -- |
225 | 2.20.1 | 146 | 2.20.1 |
226 | 147 | ||
227 | 148 | diff view generated by jsdifflib |
1 | From: Joe Komlodi <joe.komlodi@xilinx.com> | 1 | From: Tong Ho <tong.ho@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute | 3 | Add BBRAM and eFUSE usage to the Xilinx Versal Virt board |
4 | FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will | 4 | document. |
5 | assert due to fpst->default_nan_mode being set. | ||
6 | 5 | ||
7 | To avoid this, we check to see what NaN mode we're running in before we call | 6 | Signed-off-by: Tong Ho <tong.ho@xilinx.com> |
8 | floatxx_silence_nan(). | 7 | Message-id: 20210917052400.1249094-10-tong.ho@xilinx.com |
9 | |||
10 | Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 10 | --- |
16 | target/arm/helper-a64.c | 12 +++++++++--- | 11 | docs/system/arm/xlnx-versal-virt.rst | 49 ++++++++++++++++++++++++++++ |
17 | target/arm/vfp_helper.c | 24 ++++++++++++++++++------ | 12 | 1 file changed, 49 insertions(+) |
18 | 2 files changed, 27 insertions(+), 9 deletions(-) | ||
19 | 13 | ||
20 | diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c | 14 | diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst |
21 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/target/arm/helper-a64.c | 16 | --- a/docs/system/arm/xlnx-versal-virt.rst |
23 | +++ b/target/arm/helper-a64.c | 17 | +++ b/docs/system/arm/xlnx-versal-virt.rst |
24 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp) | 18 | @@ -XXX,XX +XXX,XX @@ Implemented devices: |
25 | float16 nan = a; | 19 | - OCM (256KB of On Chip Memory) |
26 | if (float16_is_signaling_nan(a, fpst)) { | 20 | - XRAM (4MB of on chip Accelerator RAM) |
27 | float_raise(float_flag_invalid, fpst); | 21 | - DDR memory |
28 | - nan = float16_silence_nan(a, fpst); | 22 | +- BBRAM (36 bytes of Battery-backed RAM) |
29 | + if (!fpst->default_nan_mode) { | 23 | +- eFUSE (3072 bytes of one-time field-programmable bit array) |
30 | + nan = float16_silence_nan(a, fpst); | 24 | |
31 | + } | 25 | QEMU does not yet model any other devices, including the PL and the AI Engine. |
32 | } | 26 | |
33 | if (fpst->default_nan_mode) { | 27 | @@ -XXX,XX +XXX,XX @@ Run the following at the U-Boot prompt: |
34 | nan = float16_default_nan(fpst); | 28 | fdt set /chosen/dom0 reg <0x00000000 0x40000000 0x0 0x03100000> |
35 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp) | 29 | booti 30000000 - 20000000 |
36 | float32 nan = a; | 30 | |
37 | if (float32_is_signaling_nan(a, fpst)) { | 31 | +BBRAM File Backend |
38 | float_raise(float_flag_invalid, fpst); | 32 | +"""""""""""""""""" |
39 | - nan = float32_silence_nan(a, fpst); | 33 | +BBRAM can have an optional file backend, which must be a seekable |
40 | + if (!fpst->default_nan_mode) { | 34 | +binary file with a size of 36 bytes or larger. A file with all |
41 | + nan = float32_silence_nan(a, fpst); | 35 | +binary 0s is a 'blank'. |
42 | + } | 36 | + |
43 | } | 37 | +To add a file-backend for the BBRAM: |
44 | if (fpst->default_nan_mode) { | 38 | + |
45 | nan = float32_default_nan(fpst); | 39 | +.. code-block:: bash |
46 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp) | 40 | + |
47 | float64 nan = a; | 41 | + -drive if=pflash,index=0,file=versal-bbram.bin,format=raw |
48 | if (float64_is_signaling_nan(a, fpst)) { | 42 | + |
49 | float_raise(float_flag_invalid, fpst); | 43 | +To use a different index value, N, from default of 0, add: |
50 | - nan = float64_silence_nan(a, fpst); | 44 | + |
51 | + if (!fpst->default_nan_mode) { | 45 | +.. code-block:: bash |
52 | + nan = float64_silence_nan(a, fpst); | 46 | + |
53 | + } | 47 | + -global xlnx,bbram-ctrl.drive-index=N |
54 | } | 48 | + |
55 | if (fpst->default_nan_mode) { | 49 | +eFUSE File Backend |
56 | nan = float64_default_nan(fpst); | 50 | +"""""""""""""""""" |
57 | diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c | 51 | +eFUSE can have an optional file backend, which must be a seekable |
58 | index XXXXXXX..XXXXXXX 100644 | 52 | +binary file with a size of 3072 bytes or larger. A file with all |
59 | --- a/target/arm/vfp_helper.c | 53 | +binary 0s is a 'blank'. |
60 | +++ b/target/arm/vfp_helper.c | 54 | + |
61 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp) | 55 | +To add a file-backend for the eFUSE: |
62 | float16 nan = f16; | 56 | + |
63 | if (float16_is_signaling_nan(f16, fpst)) { | 57 | +.. code-block:: bash |
64 | float_raise(float_flag_invalid, fpst); | 58 | + |
65 | - nan = float16_silence_nan(f16, fpst); | 59 | + -drive if=pflash,index=1,file=versal-efuse.bin,format=raw |
66 | + if (!fpst->default_nan_mode) { | 60 | + |
67 | + nan = float16_silence_nan(f16, fpst); | 61 | +To use a different index value, N, from default of 1, add: |
68 | + } | 62 | + |
69 | } | 63 | +.. code-block:: bash |
70 | if (fpst->default_nan_mode) { | 64 | + |
71 | nan = float16_default_nan(fpst); | 65 | + -global xlnx,efuse.drive-index=N |
72 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp) | 66 | + |
73 | float32 nan = f32; | 67 | +.. warning:: |
74 | if (float32_is_signaling_nan(f32, fpst)) { | 68 | + In actual physical Versal, BBRAM and eFUSE contain sensitive data. |
75 | float_raise(float_flag_invalid, fpst); | 69 | + The QEMU device models do **not** encrypt nor obfuscate any data |
76 | - nan = float32_silence_nan(f32, fpst); | 70 | + when holding them in models' memory or when writing them to their |
77 | + if (!fpst->default_nan_mode) { | 71 | + file backends. |
78 | + nan = float32_silence_nan(f32, fpst); | 72 | + |
79 | + } | 73 | + Thus, a file backend should be used with caution, and 'format=luks' |
80 | } | 74 | + is highly recommended (albeit with usage complexity). |
81 | if (fpst->default_nan_mode) { | 75 | + |
82 | nan = float32_default_nan(fpst); | 76 | + Better yet, do not use actual product data when running guest image |
83 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp) | 77 | + on this Xilinx Versal Virt board. |
84 | float64 nan = f64; | ||
85 | if (float64_is_signaling_nan(f64, fpst)) { | ||
86 | float_raise(float_flag_invalid, fpst); | ||
87 | - nan = float64_silence_nan(f64, fpst); | ||
88 | + if (!fpst->default_nan_mode) { | ||
89 | + nan = float64_silence_nan(f64, fpst); | ||
90 | + } | ||
91 | } | ||
92 | if (fpst->default_nan_mode) { | ||
93 | nan = float64_default_nan(fpst); | ||
94 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp) | ||
95 | float16 nan = f16; | ||
96 | if (float16_is_signaling_nan(f16, s)) { | ||
97 | float_raise(float_flag_invalid, s); | ||
98 | - nan = float16_silence_nan(f16, s); | ||
99 | + if (!s->default_nan_mode) { | ||
100 | + nan = float16_silence_nan(f16, fpstp); | ||
101 | + } | ||
102 | } | ||
103 | if (s->default_nan_mode) { | ||
104 | nan = float16_default_nan(s); | ||
105 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) | ||
106 | float32 nan = f32; | ||
107 | if (float32_is_signaling_nan(f32, s)) { | ||
108 | float_raise(float_flag_invalid, s); | ||
109 | - nan = float32_silence_nan(f32, s); | ||
110 | + if (!s->default_nan_mode) { | ||
111 | + nan = float32_silence_nan(f32, fpstp); | ||
112 | + } | ||
113 | } | ||
114 | if (s->default_nan_mode) { | ||
115 | nan = float32_default_nan(s); | ||
116 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) | ||
117 | float64 nan = f64; | ||
118 | if (float64_is_signaling_nan(f64, s)) { | ||
119 | float_raise(float_flag_invalid, s); | ||
120 | - nan = float64_silence_nan(f64, s); | ||
121 | + if (!s->default_nan_mode) { | ||
122 | + nan = float64_silence_nan(f64, fpstp); | ||
123 | + } | ||
124 | } | ||
125 | if (s->default_nan_mode) { | ||
126 | nan = float64_default_nan(s); | ||
127 | -- | 78 | -- |
128 | 2.20.1 | 79 | 2.20.1 |
129 | 80 | ||
130 | 81 | diff view generated by jsdifflib |
1 | Implement the MVE VSHLC insn, which performs a shift left of the | 1 | The aarch64-linux QEMU usermode binaries can never run 32-bit |
---|---|---|---|
2 | entire vector with carry in bits provided from a general purpose | 2 | code, so they do not need to include the GDB XML for it. |
3 | register and carry out bits written back to that register. | 3 | (arm_cpu_register_gdb_regs_for_features() will not use these |
4 | XML files if the CPU has ARM_FEATURE_AARCH64, so we will not | ||
5 | advertise to gdb that we have them.) | ||
4 | 6 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20210628135835.6690-14-peter.maydell@linaro.org | 9 | Message-id: 20210921162901.17508-2-peter.maydell@linaro.org |
8 | --- | 10 | --- |
9 | target/arm/helper-mve.h | 2 ++ | 11 | configs/targets/aarch64-linux-user.mak | 2 +- |
10 | target/arm/mve.decode | 2 ++ | 12 | configs/targets/aarch64_be-linux-user.mak | 2 +- |
11 | target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++ | 13 | 2 files changed, 2 insertions(+), 2 deletions(-) |
12 | target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++ | ||
13 | 4 files changed, 72 insertions(+) | ||
14 | 14 | ||
15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | 15 | diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper-mve.h | 17 | --- a/configs/targets/aarch64-linux-user.mak |
18 | +++ b/target/arm/helper-mve.h | 18 | +++ b/configs/targets/aarch64-linux-user.mak |
19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 19 | @@ -XXX,XX +XXX,XX @@ |
20 | DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 20 | TARGET_ARCH=aarch64 |
21 | DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 21 | TARGET_BASE_ARCH=arm |
22 | DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 22 | -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml |
23 | + | 23 | +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml |
24 | +DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) | 24 | TARGET_HAS_BFLT=y |
25 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | 25 | CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y |
26 | diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak | ||
26 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/target/arm/mve.decode | 28 | --- a/configs/targets/aarch64_be-linux-user.mak |
28 | +++ b/target/arm/mve.decode | 29 | +++ b/configs/targets/aarch64_be-linux-user.mak |
29 | @@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b | 30 | @@ -XXX,XX +XXX,XX @@ |
30 | VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h | 31 | TARGET_ARCH=aarch64 |
31 | VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b | 32 | TARGET_BASE_ARCH=arm |
32 | VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h | 33 | TARGET_WORDS_BIGENDIAN=y |
33 | + | 34 | -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml |
34 | +VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd | 35 | +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml |
35 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | 36 | TARGET_HAS_BFLT=y |
36 | index XXXXXXX..XXXXXXX 100644 | 37 | CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y |
37 | --- a/target/arm/mve_helper.c | ||
38 | +++ b/target/arm/mve_helper.c | ||
39 | @@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) | ||
40 | DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) | ||
41 | DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) | ||
42 | DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) | ||
43 | + | ||
44 | +uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, | ||
45 | + uint32_t shift) | ||
46 | +{ | ||
47 | + uint32_t *d = vd; | ||
48 | + uint16_t mask = mve_element_mask(env); | ||
49 | + unsigned e; | ||
50 | + uint32_t r; | ||
51 | + | ||
52 | + /* | ||
53 | + * For each 32-bit element, we shift it left, bringing in the | ||
54 | + * low 'shift' bits of rdm at the bottom. Bits shifted out at | ||
55 | + * the top become the new rdm, if the predicate mask permits. | ||
56 | + * The final rdm value is returned to update the register. | ||
57 | + * shift == 0 here means "shift by 32 bits". | ||
58 | + */ | ||
59 | + if (shift == 0) { | ||
60 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { | ||
61 | + r = rdm; | ||
62 | + if (mask & 1) { | ||
63 | + rdm = d[H4(e)]; | ||
64 | + } | ||
65 | + mergemask(&d[H4(e)], r, mask); | ||
66 | + } | ||
67 | + } else { | ||
68 | + uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); | ||
69 | + | ||
70 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { | ||
71 | + r = (d[H4(e)] << shift) | (rdm & shiftmask); | ||
72 | + if (mask & 1) { | ||
73 | + rdm = d[H4(e)] >> (32 - shift); | ||
74 | + } | ||
75 | + mergemask(&d[H4(e)], r, mask); | ||
76 | + } | ||
77 | + } | ||
78 | + mve_advance_vpt(env); | ||
79 | + return rdm; | ||
80 | +} | ||
81 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
82 | index XXXXXXX..XXXXXXX 100644 | ||
83 | --- a/target/arm/translate-mve.c | ||
84 | +++ b/target/arm/translate-mve.c | ||
85 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u) | ||
86 | DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u) | ||
87 | DO_2SHIFT_N(VQRSHRUNB, vqrshrunb) | ||
88 | DO_2SHIFT_N(VQRSHRUNT, vqrshrunt) | ||
89 | + | ||
90 | +static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a) | ||
91 | +{ | ||
92 | + /* | ||
93 | + * Whole Vector Left Shift with Carry. The carry is taken | ||
94 | + * from a general purpose register and written back there. | ||
95 | + * An imm of 0 means "shift by 32". | ||
96 | + */ | ||
97 | + TCGv_ptr qd; | ||
98 | + TCGv_i32 rdm; | ||
99 | + | ||
100 | + if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { | ||
101 | + return false; | ||
102 | + } | ||
103 | + if (a->rdm == 13 || a->rdm == 15) { | ||
104 | + /* CONSTRAINED UNPREDICTABLE: we UNDEF */ | ||
105 | + return false; | ||
106 | + } | ||
107 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
108 | + return true; | ||
109 | + } | ||
110 | + | ||
111 | + qd = mve_qreg_ptr(a->qd); | ||
112 | + rdm = load_reg(s, a->rdm); | ||
113 | + gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm)); | ||
114 | + store_reg(s, a->rdm, rdm); | ||
115 | + tcg_temp_free_ptr(qd); | ||
116 | + mve_update_eci(s); | ||
117 | + return true; | ||
118 | +} | ||
119 | -- | 38 | -- |
120 | 2.20.1 | 39 | 2.20.1 |
121 | 40 | ||
122 | 41 | diff view generated by jsdifflib |
1 | Implement the MVE VSRI and VSLI insns, which perform a | 1 | We're going to move this code to a different file; fix the coding |
---|---|---|---|
2 | shift-and-insert operation. | 2 | style first so checkpatch doesn't complain. This includes deleting |
3 | the spurious 'break' statements after returns in the | ||
4 | vfp_gdb_get_reg() function. | ||
3 | 5 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20210628135835.6690-11-peter.maydell@linaro.org | 9 | Message-id: 20210921162901.17508-3-peter.maydell@linaro.org |
7 | --- | 10 | --- |
8 | target/arm/helper-mve.h | 8 ++++++++ | 11 | target/arm/helper.c | 23 ++++++++++++++++------- |
9 | target/arm/mve.decode | 9 ++++++++ | 12 | 1 file changed, 16 insertions(+), 7 deletions(-) |
10 | target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/translate-mve.c | 3 +++ | ||
12 | 4 files changed, 62 insertions(+) | ||
13 | 13 | ||
14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper-mve.h | 16 | --- a/target/arm/helper.c |
17 | +++ b/target/arm/helper-mve.h | 17 | +++ b/target/arm/helper.c |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 18 | @@ -XXX,XX +XXX,XX @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) |
19 | DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 19 | } |
20 | DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 20 | } |
21 | DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 21 | switch (reg - nregs) { |
22 | + | 22 | - case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); break; |
23 | +DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 23 | - case 1: return gdb_get_reg32(buf, vfp_get_fpscr(env)); break; |
24 | +DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 24 | - case 2: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); break; |
25 | +DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 25 | + case 0: |
26 | + | 26 | + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); |
27 | +DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 27 | + case 1: |
28 | +DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 28 | + return gdb_get_reg32(buf, vfp_get_fpscr(env)); |
29 | +DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 29 | + case 2: |
30 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | 30 | + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); |
31 | index XXXXXXX..XXXXXXX 100644 | 31 | } |
32 | --- a/target/arm/mve.decode | 32 | return 0; |
33 | +++ b/target/arm/mve.decode | 33 | } |
34 | @@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h | 34 | @@ -XXX,XX +XXX,XX @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
35 | 35 | } | |
36 | VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b | 36 | } |
37 | VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h | 37 | switch (reg - nregs) { |
38 | + | 38 | - case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; |
39 | +# Shift-and-insert | 39 | - case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4; |
40 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b | 40 | - case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; |
41 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h | 41 | + case 0: |
42 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w | 42 | + env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); |
43 | + | 43 | + return 4; |
44 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b | 44 | + case 1: |
45 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h | 45 | + vfp_set_fpscr(env, ldl_p(buf)); |
46 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w | 46 | + return 4; |
47 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | 47 | + case 2: |
48 | index XXXXXXX..XXXXXXX 100644 | 48 | + env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); |
49 | --- a/target/arm/mve_helper.c | 49 | + return 4; |
50 | +++ b/target/arm/mve_helper.c | 50 | } |
51 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | 51 | return 0; |
52 | DO_2SHIFT_U(vrshli_u, DO_VRSHLU) | 52 | } |
53 | DO_2SHIFT_S(vrshli_s, DO_VRSHLS) | 53 | @@ -XXX,XX +XXX,XX @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) |
54 | 54 | return gdb_get_reg32(buf, vfp_get_fpsr(env)); | |
55 | +/* Shift-and-insert; we always work with 64 bits at a time */ | 55 | case 33: |
56 | +#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ | 56 | /* FPCR */ |
57 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | 57 | - return gdb_get_reg32(buf,vfp_get_fpcr(env)); |
58 | + void *vm, uint32_t shift) \ | 58 | + return gdb_get_reg32(buf, vfp_get_fpcr(env)); |
59 | + { \ | 59 | default: |
60 | + uint64_t *d = vd, *m = vm; \ | 60 | return 0; |
61 | + uint16_t mask; \ | 61 | } |
62 | + uint64_t shiftmask; \ | ||
63 | + unsigned e; \ | ||
64 | + if (shift == 0 || shift == ESIZE * 8) { \ | ||
65 | + /* \ | ||
66 | + * Only VSLI can shift by 0; only VSRI can shift by <dt>. \ | ||
67 | + * The generic logic would give the right answer for 0 but \ | ||
68 | + * fails for <dt>. \ | ||
69 | + */ \ | ||
70 | + goto done; \ | ||
71 | + } \ | ||
72 | + assert(shift < ESIZE * 8); \ | ||
73 | + mask = mve_element_mask(env); \ | ||
74 | + /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ | ||
75 | + shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ | ||
76 | + for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ | ||
77 | + uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ | ||
78 | + (d[H8(e)] & ~shiftmask); \ | ||
79 | + mergemask(&d[H8(e)], r, mask); \ | ||
80 | + } \ | ||
81 | +done: \ | ||
82 | + mve_advance_vpt(env); \ | ||
83 | + } | ||
84 | + | ||
85 | +#define DO_SHL(N, SHIFT) ((N) << (SHIFT)) | ||
86 | +#define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) | ||
87 | +#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) | ||
88 | +#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) | ||
89 | + | ||
90 | +DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) | ||
91 | +DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) | ||
92 | +DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) | ||
93 | +DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) | ||
94 | +DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) | ||
95 | +DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) | ||
96 | + | ||
97 | /* | ||
98 | * Long shifts taking half-sized inputs from top or bottom of the input | ||
99 | * vector and producing a double-width result. ESIZE, TYPE are for | ||
100 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
101 | index XXXXXXX..XXXXXXX 100644 | ||
102 | --- a/target/arm/translate-mve.c | ||
103 | +++ b/target/arm/translate-mve.c | ||
104 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true) | ||
105 | DO_2SHIFT(VRSHRI_S, vrshli_s, true) | ||
106 | DO_2SHIFT(VRSHRI_U, vrshli_u, true) | ||
107 | |||
108 | +DO_2SHIFT(VSRI, vsri, false) | ||
109 | +DO_2SHIFT(VSLI, vsli, false) | ||
110 | + | ||
111 | #define DO_VSHLL(INSN, FN) \ | ||
112 | static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | ||
113 | { \ | ||
114 | -- | 62 | -- |
115 | 2.20.1 | 63 | 2.20.1 |
116 | 64 | ||
117 | 65 | diff view generated by jsdifflib |
1 | Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN. | 1 | Currently helper.c includes some code which is part of the arm |
---|---|---|---|
2 | target's gdbstub support. This code has a better home: in gdbstub.c | ||
3 | and gdbstub64.c. Move it there. | ||
2 | 4 | ||
3 | do_urshr() is borrowed from sve_helper.c. | 5 | Because aarch64_fpu_gdb_get_reg() and aarch64_fpu_gdb_set_reg() move |
6 | into gdbstub64.c, this means that they're now compiled only for | ||
7 | TARGET_AARCH64 rather than always. That is the only case when they | ||
8 | would ever be used, but it does mean that the ifdef in | ||
9 | arm_cpu_register_gdb_regs_for_features() needs to be adjusted to | ||
10 | match. | ||
4 | 11 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20210628135835.6690-12-peter.maydell@linaro.org | 15 | Message-id: 20210921162901.17508-4-peter.maydell@linaro.org |
8 | --- | 16 | --- |
9 | target/arm/helper-mve.h | 10 ++++++++++ | 17 | target/arm/internals.h | 7 ++ |
10 | target/arm/mve.decode | 11 +++++++++++ | 18 | target/arm/gdbstub.c | 130 ++++++++++++++++++++ |
11 | target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++ | 19 | target/arm/gdbstub64.c | 140 +++++++++++++++++++++ |
12 | target/arm/translate-mve.c | 15 ++++++++++++++ | 20 | target/arm/helper.c | 271 ----------------------------------------- |
13 | 4 files changed, 76 insertions(+) | 21 | 4 files changed, 277 insertions(+), 271 deletions(-) |
14 | 22 | ||
15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | 23 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
16 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper-mve.h | 25 | --- a/target/arm/internals.h |
18 | +++ b/target/arm/helper-mve.h | 26 | +++ b/target/arm/internals.h |
19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 27 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) |
20 | DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 28 | return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); |
21 | DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 29 | } |
22 | DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 30 | |
23 | + | 31 | +#ifdef TARGET_AARCH64 |
24 | +DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 32 | +int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); |
25 | +DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 33 | +int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); |
26 | +DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 34 | +int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); |
27 | +DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 35 | +int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); |
28 | + | 36 | +#endif |
29 | +DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 37 | + |
30 | +DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 38 | #endif |
31 | +DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 39 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c |
32 | +DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
34 | index XXXXXXX..XXXXXXX 100644 | 40 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/target/arm/mve.decode | 41 | --- a/target/arm/gdbstub.c |
36 | +++ b/target/arm/mve.decode | 42 | +++ b/target/arm/gdbstub.c |
37 | @@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w | 43 | @@ -XXX,XX +XXX,XX @@ |
38 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b | 44 | */ |
39 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h | 45 | #include "qemu/osdep.h" |
40 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w | 46 | #include "cpu.h" |
41 | + | 47 | +#include "internals.h" |
42 | +# Narrowing shifts (which only support b and h sizes) | 48 | #include "exec/gdbstub.h" |
43 | +VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b | 49 | |
44 | +VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h | 50 | typedef struct RegisterSysregXmlParam { |
45 | +VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b | 51 | @@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) |
46 | +VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h | 52 | return 0; |
47 | + | 53 | } |
48 | +VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b | 54 | |
49 | +VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h | 55 | +static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) |
50 | +VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b | 56 | +{ |
51 | +VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h | 57 | + ARMCPU *cpu = env_archcpu(env); |
52 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | 58 | + int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; |
59 | + | ||
60 | + /* VFP data registers are always little-endian. */ | ||
61 | + if (reg < nregs) { | ||
62 | + return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg)); | ||
63 | + } | ||
64 | + if (arm_feature(env, ARM_FEATURE_NEON)) { | ||
65 | + /* Aliases for Q regs. */ | ||
66 | + nregs += 16; | ||
67 | + if (reg < nregs) { | ||
68 | + uint64_t *q = aa32_vfp_qreg(env, reg - 32); | ||
69 | + return gdb_get_reg128(buf, q[0], q[1]); | ||
70 | + } | ||
71 | + } | ||
72 | + switch (reg - nregs) { | ||
73 | + case 0: | ||
74 | + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); | ||
75 | + case 1: | ||
76 | + return gdb_get_reg32(buf, vfp_get_fpscr(env)); | ||
77 | + case 2: | ||
78 | + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); | ||
79 | + } | ||
80 | + return 0; | ||
81 | +} | ||
82 | + | ||
83 | +static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | ||
84 | +{ | ||
85 | + ARMCPU *cpu = env_archcpu(env); | ||
86 | + int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; | ||
87 | + | ||
88 | + if (reg < nregs) { | ||
89 | + *aa32_vfp_dreg(env, reg) = ldq_le_p(buf); | ||
90 | + return 8; | ||
91 | + } | ||
92 | + if (arm_feature(env, ARM_FEATURE_NEON)) { | ||
93 | + nregs += 16; | ||
94 | + if (reg < nregs) { | ||
95 | + uint64_t *q = aa32_vfp_qreg(env, reg - 32); | ||
96 | + q[0] = ldq_le_p(buf); | ||
97 | + q[1] = ldq_le_p(buf + 8); | ||
98 | + return 16; | ||
99 | + } | ||
100 | + } | ||
101 | + switch (reg - nregs) { | ||
102 | + case 0: | ||
103 | + env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); | ||
104 | + return 4; | ||
105 | + case 1: | ||
106 | + vfp_set_fpscr(env, ldl_p(buf)); | ||
107 | + return 4; | ||
108 | + case 2: | ||
109 | + env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); | ||
110 | + return 4; | ||
111 | + } | ||
112 | + return 0; | ||
113 | +} | ||
114 | + | ||
115 | +/** | ||
116 | + * arm_get/set_gdb_*: get/set a gdb register | ||
117 | + * @env: the CPU state | ||
118 | + * @buf: a buffer to copy to/from | ||
119 | + * @reg: register number (offset from start of group) | ||
120 | + * | ||
121 | + * We return the number of bytes copied | ||
122 | + */ | ||
123 | + | ||
124 | +static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) | ||
125 | +{ | ||
126 | + ARMCPU *cpu = env_archcpu(env); | ||
127 | + const ARMCPRegInfo *ri; | ||
128 | + uint32_t key; | ||
129 | + | ||
130 | + key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg]; | ||
131 | + ri = get_arm_cp_reginfo(cpu->cp_regs, key); | ||
132 | + if (ri) { | ||
133 | + if (cpreg_field_is_64bit(ri)) { | ||
134 | + return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); | ||
135 | + } else { | ||
136 | + return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); | ||
137 | + } | ||
138 | + } | ||
139 | + return 0; | ||
140 | +} | ||
141 | + | ||
142 | +static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) | ||
143 | +{ | ||
144 | + return 0; | ||
145 | +} | ||
146 | + | ||
147 | static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, | ||
148 | ARMCPRegInfo *ri, uint32_t ri_key, | ||
149 | int bitsize, int regnum) | ||
150 | @@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) | ||
151 | } | ||
152 | return NULL; | ||
153 | } | ||
154 | + | ||
155 | +void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
156 | +{ | ||
157 | + CPUState *cs = CPU(cpu); | ||
158 | + CPUARMState *env = &cpu->env; | ||
159 | + | ||
160 | + if (arm_feature(env, ARM_FEATURE_AARCH64)) { | ||
161 | + /* | ||
162 | + * The lower part of each SVE register aliases to the FPU | ||
163 | + * registers so we don't need to include both. | ||
164 | + */ | ||
165 | +#ifdef TARGET_AARCH64 | ||
166 | + if (isar_feature_aa64_sve(&cpu->isar)) { | ||
167 | + gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg, | ||
168 | + arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs), | ||
169 | + "sve-registers.xml", 0); | ||
170 | + } else { | ||
171 | + gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | ||
172 | + aarch64_fpu_gdb_set_reg, | ||
173 | + 34, "aarch64-fpu.xml", 0); | ||
174 | + } | ||
175 | +#endif | ||
176 | + } else if (arm_feature(env, ARM_FEATURE_NEON)) { | ||
177 | + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, | ||
178 | + 51, "arm-neon.xml", 0); | ||
179 | + } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { | ||
180 | + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, | ||
181 | + 35, "arm-vfp3.xml", 0); | ||
182 | + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
183 | + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, | ||
184 | + 19, "arm-vfp.xml", 0); | ||
185 | + } | ||
186 | + gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, | ||
187 | + arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), | ||
188 | + "system-registers.xml", 0); | ||
189 | + | ||
190 | +} | ||
191 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | 192 | index XXXXXXX..XXXXXXX 100644 |
54 | --- a/target/arm/mve_helper.c | 193 | --- a/target/arm/gdbstub64.c |
55 | +++ b/target/arm/mve_helper.c | 194 | +++ b/target/arm/gdbstub64.c |
56 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) | 195 | @@ -XXX,XX +XXX,XX @@ |
57 | 196 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
58 | DO_VSHLL_ALL(vshllb, false) | 197 | */ |
59 | DO_VSHLL_ALL(vshllt, true) | 198 | #include "qemu/osdep.h" |
60 | + | 199 | +#include "qemu/log.h" |
61 | +/* | 200 | #include "cpu.h" |
62 | + * Narrowing right shifts, taking a double sized input, shifting it | 201 | +#include "internals.h" |
63 | + * and putting the result in either the top or bottom half of the output. | 202 | #include "exec/gdbstub.h" |
64 | + * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. | 203 | |
65 | + */ | 204 | int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) |
66 | +#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ | 205 | @@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) |
67 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | 206 | /* Unknown register. */ |
68 | + void *vm, uint32_t shift) \ | 207 | return 0; |
69 | + { \ | 208 | } |
70 | + LTYPE *m = vm; \ | 209 | + |
71 | + TYPE *d = vd; \ | 210 | +int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) |
72 | + uint16_t mask = mve_element_mask(env); \ | 211 | +{ |
73 | + unsigned le; \ | 212 | + switch (reg) { |
74 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | 213 | + case 0 ... 31: |
75 | + TYPE r = FN(m[H##LESIZE(le)], shift); \ | 214 | + { |
76 | + mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ | 215 | + /* 128 bit FP register - quads are in LE order */ |
77 | + } \ | 216 | + uint64_t *q = aa64_vfp_qreg(env, reg); |
78 | + mve_advance_vpt(env); \ | 217 | + return gdb_get_reg128(buf, q[1], q[0]); |
79 | + } | 218 | + } |
80 | + | 219 | + case 32: |
81 | +#define DO_VSHRN_ALL(OP, FN) \ | 220 | + /* FPSR */ |
82 | + DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ | 221 | + return gdb_get_reg32(buf, vfp_get_fpsr(env)); |
83 | + DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ | 222 | + case 33: |
84 | + DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ | 223 | + /* FPCR */ |
85 | + DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) | 224 | + return gdb_get_reg32(buf, vfp_get_fpcr(env)); |
86 | + | 225 | + default: |
87 | +static inline uint64_t do_urshr(uint64_t x, unsigned sh) | ||
88 | +{ | ||
89 | + if (likely(sh < 64)) { | ||
90 | + return (x >> sh) + ((x >> (sh - 1)) & 1); | ||
91 | + } else if (sh == 64) { | ||
92 | + return x >> 63; | ||
93 | + } else { | ||
94 | + return 0; | 226 | + return 0; |
95 | + } | 227 | + } |
96 | +} | 228 | +} |
97 | + | 229 | + |
98 | +DO_VSHRN_ALL(vshrn, DO_SHR) | 230 | +int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
99 | +DO_VSHRN_ALL(vrshrn, do_urshr) | 231 | +{ |
100 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | 232 | + switch (reg) { |
233 | + case 0 ... 31: | ||
234 | + /* 128 bit FP register */ | ||
235 | + { | ||
236 | + uint64_t *q = aa64_vfp_qreg(env, reg); | ||
237 | + q[0] = ldq_le_p(buf); | ||
238 | + q[1] = ldq_le_p(buf + 8); | ||
239 | + return 16; | ||
240 | + } | ||
241 | + case 32: | ||
242 | + /* FPSR */ | ||
243 | + vfp_set_fpsr(env, ldl_p(buf)); | ||
244 | + return 4; | ||
245 | + case 33: | ||
246 | + /* FPCR */ | ||
247 | + vfp_set_fpcr(env, ldl_p(buf)); | ||
248 | + return 4; | ||
249 | + default: | ||
250 | + return 0; | ||
251 | + } | ||
252 | +} | ||
253 | + | ||
254 | +int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) | ||
255 | +{ | ||
256 | + ARMCPU *cpu = env_archcpu(env); | ||
257 | + | ||
258 | + switch (reg) { | ||
259 | + /* The first 32 registers are the zregs */ | ||
260 | + case 0 ... 31: | ||
261 | + { | ||
262 | + int vq, len = 0; | ||
263 | + for (vq = 0; vq < cpu->sve_max_vq; vq++) { | ||
264 | + len += gdb_get_reg128(buf, | ||
265 | + env->vfp.zregs[reg].d[vq * 2 + 1], | ||
266 | + env->vfp.zregs[reg].d[vq * 2]); | ||
267 | + } | ||
268 | + return len; | ||
269 | + } | ||
270 | + case 32: | ||
271 | + return gdb_get_reg32(buf, vfp_get_fpsr(env)); | ||
272 | + case 33: | ||
273 | + return gdb_get_reg32(buf, vfp_get_fpcr(env)); | ||
274 | + /* then 16 predicates and the ffr */ | ||
275 | + case 34 ... 50: | ||
276 | + { | ||
277 | + int preg = reg - 34; | ||
278 | + int vq, len = 0; | ||
279 | + for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { | ||
280 | + len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); | ||
281 | + } | ||
282 | + return len; | ||
283 | + } | ||
284 | + case 51: | ||
285 | + { | ||
286 | + /* | ||
287 | + * We report in Vector Granules (VG) which is 64bit in a Z reg | ||
288 | + * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. | ||
289 | + */ | ||
290 | + int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1; | ||
291 | + return gdb_get_reg64(buf, vq * 2); | ||
292 | + } | ||
293 | + default: | ||
294 | + /* gdbstub asked for something out our range */ | ||
295 | + qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg); | ||
296 | + break; | ||
297 | + } | ||
298 | + | ||
299 | + return 0; | ||
300 | +} | ||
301 | + | ||
302 | +int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) | ||
303 | +{ | ||
304 | + ARMCPU *cpu = env_archcpu(env); | ||
305 | + | ||
306 | + /* The first 32 registers are the zregs */ | ||
307 | + switch (reg) { | ||
308 | + /* The first 32 registers are the zregs */ | ||
309 | + case 0 ... 31: | ||
310 | + { | ||
311 | + int vq, len = 0; | ||
312 | + uint64_t *p = (uint64_t *) buf; | ||
313 | + for (vq = 0; vq < cpu->sve_max_vq; vq++) { | ||
314 | + env->vfp.zregs[reg].d[vq * 2 + 1] = *p++; | ||
315 | + env->vfp.zregs[reg].d[vq * 2] = *p++; | ||
316 | + len += 16; | ||
317 | + } | ||
318 | + return len; | ||
319 | + } | ||
320 | + case 32: | ||
321 | + vfp_set_fpsr(env, *(uint32_t *)buf); | ||
322 | + return 4; | ||
323 | + case 33: | ||
324 | + vfp_set_fpcr(env, *(uint32_t *)buf); | ||
325 | + return 4; | ||
326 | + case 34 ... 50: | ||
327 | + { | ||
328 | + int preg = reg - 34; | ||
329 | + int vq, len = 0; | ||
330 | + uint64_t *p = (uint64_t *) buf; | ||
331 | + for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { | ||
332 | + env->vfp.pregs[preg].p[vq / 4] = *p++; | ||
333 | + len += 8; | ||
334 | + } | ||
335 | + return len; | ||
336 | + } | ||
337 | + case 51: | ||
338 | + /* cannot set vg via gdbstub */ | ||
339 | + return 0; | ||
340 | + default: | ||
341 | + /* gdbstub asked for something out our range */ | ||
342 | + break; | ||
343 | + } | ||
344 | + | ||
345 | + return 0; | ||
346 | +} | ||
347 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
101 | index XXXXXXX..XXXXXXX 100644 | 348 | index XXXXXXX..XXXXXXX 100644 |
102 | --- a/target/arm/translate-mve.c | 349 | --- a/target/arm/helper.c |
103 | +++ b/target/arm/translate-mve.c | 350 | +++ b/target/arm/helper.c |
104 | @@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs) | 351 | @@ -XXX,XX +XXX,XX @@ |
105 | DO_VSHLL(VSHLL_BU, vshllbu) | 352 | #include "trace.h" |
106 | DO_VSHLL(VSHLL_TS, vshllts) | 353 | #include "cpu.h" |
107 | DO_VSHLL(VSHLL_TU, vshlltu) | 354 | #include "internals.h" |
108 | + | 355 | -#include "exec/gdbstub.h" |
109 | +#define DO_2SHIFT_N(INSN, FN) \ | 356 | #include "exec/helper-proto.h" |
110 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | 357 | #include "qemu/host-utils.h" |
111 | + { \ | 358 | #include "qemu/main-loop.h" |
112 | + static MVEGenTwoOpShiftFn * const fns[] = { \ | 359 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, |
113 | + gen_helper_mve_##FN##b, \ | 360 | static void switch_mode(CPUARMState *env, int mode); |
114 | + gen_helper_mve_##FN##h, \ | 361 | static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); |
115 | + }; \ | 362 | |
116 | + return do_2shift(s, a, fns[a->size], false); \ | 363 | -static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) |
117 | + } | 364 | -{ |
118 | + | 365 | - ARMCPU *cpu = env_archcpu(env); |
119 | +DO_2SHIFT_N(VSHRNB, vshrnb) | 366 | - int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; |
120 | +DO_2SHIFT_N(VSHRNT, vshrnt) | 367 | - |
121 | +DO_2SHIFT_N(VRSHRNB, vrshrnb) | 368 | - /* VFP data registers are always little-endian. */ |
122 | +DO_2SHIFT_N(VRSHRNT, vrshrnt) | 369 | - if (reg < nregs) { |
370 | - return gdb_get_reg64(buf, *aa32_vfp_dreg(env, reg)); | ||
371 | - } | ||
372 | - if (arm_feature(env, ARM_FEATURE_NEON)) { | ||
373 | - /* Aliases for Q regs. */ | ||
374 | - nregs += 16; | ||
375 | - if (reg < nregs) { | ||
376 | - uint64_t *q = aa32_vfp_qreg(env, reg - 32); | ||
377 | - return gdb_get_reg128(buf, q[0], q[1]); | ||
378 | - } | ||
379 | - } | ||
380 | - switch (reg - nregs) { | ||
381 | - case 0: | ||
382 | - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); | ||
383 | - case 1: | ||
384 | - return gdb_get_reg32(buf, vfp_get_fpscr(env)); | ||
385 | - case 2: | ||
386 | - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); | ||
387 | - } | ||
388 | - return 0; | ||
389 | -} | ||
390 | - | ||
391 | -static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | ||
392 | -{ | ||
393 | - ARMCPU *cpu = env_archcpu(env); | ||
394 | - int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; | ||
395 | - | ||
396 | - if (reg < nregs) { | ||
397 | - *aa32_vfp_dreg(env, reg) = ldq_le_p(buf); | ||
398 | - return 8; | ||
399 | - } | ||
400 | - if (arm_feature(env, ARM_FEATURE_NEON)) { | ||
401 | - nregs += 16; | ||
402 | - if (reg < nregs) { | ||
403 | - uint64_t *q = aa32_vfp_qreg(env, reg - 32); | ||
404 | - q[0] = ldq_le_p(buf); | ||
405 | - q[1] = ldq_le_p(buf + 8); | ||
406 | - return 16; | ||
407 | - } | ||
408 | - } | ||
409 | - switch (reg - nregs) { | ||
410 | - case 0: | ||
411 | - env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); | ||
412 | - return 4; | ||
413 | - case 1: | ||
414 | - vfp_set_fpscr(env, ldl_p(buf)); | ||
415 | - return 4; | ||
416 | - case 2: | ||
417 | - env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); | ||
418 | - return 4; | ||
419 | - } | ||
420 | - return 0; | ||
421 | -} | ||
422 | - | ||
423 | -static int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) | ||
424 | -{ | ||
425 | - switch (reg) { | ||
426 | - case 0 ... 31: | ||
427 | - { | ||
428 | - /* 128 bit FP register - quads are in LE order */ | ||
429 | - uint64_t *q = aa64_vfp_qreg(env, reg); | ||
430 | - return gdb_get_reg128(buf, q[1], q[0]); | ||
431 | - } | ||
432 | - case 32: | ||
433 | - /* FPSR */ | ||
434 | - return gdb_get_reg32(buf, vfp_get_fpsr(env)); | ||
435 | - case 33: | ||
436 | - /* FPCR */ | ||
437 | - return gdb_get_reg32(buf, vfp_get_fpcr(env)); | ||
438 | - default: | ||
439 | - return 0; | ||
440 | - } | ||
441 | -} | ||
442 | - | ||
443 | -static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | ||
444 | -{ | ||
445 | - switch (reg) { | ||
446 | - case 0 ... 31: | ||
447 | - /* 128 bit FP register */ | ||
448 | - { | ||
449 | - uint64_t *q = aa64_vfp_qreg(env, reg); | ||
450 | - q[0] = ldq_le_p(buf); | ||
451 | - q[1] = ldq_le_p(buf + 8); | ||
452 | - return 16; | ||
453 | - } | ||
454 | - case 32: | ||
455 | - /* FPSR */ | ||
456 | - vfp_set_fpsr(env, ldl_p(buf)); | ||
457 | - return 4; | ||
458 | - case 33: | ||
459 | - /* FPCR */ | ||
460 | - vfp_set_fpcr(env, ldl_p(buf)); | ||
461 | - return 4; | ||
462 | - default: | ||
463 | - return 0; | ||
464 | - } | ||
465 | -} | ||
466 | - | ||
467 | static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
468 | { | ||
469 | assert(ri->fieldoffset); | ||
470 | @@ -XXX,XX +XXX,XX @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, | ||
471 | } | ||
472 | } | ||
473 | |||
474 | -/** | ||
475 | - * arm_get/set_gdb_*: get/set a gdb register | ||
476 | - * @env: the CPU state | ||
477 | - * @buf: a buffer to copy to/from | ||
478 | - * @reg: register number (offset from start of group) | ||
479 | - * | ||
480 | - * We return the number of bytes copied | ||
481 | - */ | ||
482 | - | ||
483 | -static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) | ||
484 | -{ | ||
485 | - ARMCPU *cpu = env_archcpu(env); | ||
486 | - const ARMCPRegInfo *ri; | ||
487 | - uint32_t key; | ||
488 | - | ||
489 | - key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg]; | ||
490 | - ri = get_arm_cp_reginfo(cpu->cp_regs, key); | ||
491 | - if (ri) { | ||
492 | - if (cpreg_field_is_64bit(ri)) { | ||
493 | - return gdb_get_reg64(buf, (uint64_t)read_raw_cp_reg(env, ri)); | ||
494 | - } else { | ||
495 | - return gdb_get_reg32(buf, (uint32_t)read_raw_cp_reg(env, ri)); | ||
496 | - } | ||
497 | - } | ||
498 | - return 0; | ||
499 | -} | ||
500 | - | ||
501 | -static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) | ||
502 | -{ | ||
503 | - return 0; | ||
504 | -} | ||
505 | - | ||
506 | -#ifdef TARGET_AARCH64 | ||
507 | -static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) | ||
508 | -{ | ||
509 | - ARMCPU *cpu = env_archcpu(env); | ||
510 | - | ||
511 | - switch (reg) { | ||
512 | - /* The first 32 registers are the zregs */ | ||
513 | - case 0 ... 31: | ||
514 | - { | ||
515 | - int vq, len = 0; | ||
516 | - for (vq = 0; vq < cpu->sve_max_vq; vq++) { | ||
517 | - len += gdb_get_reg128(buf, | ||
518 | - env->vfp.zregs[reg].d[vq * 2 + 1], | ||
519 | - env->vfp.zregs[reg].d[vq * 2]); | ||
520 | - } | ||
521 | - return len; | ||
522 | - } | ||
523 | - case 32: | ||
524 | - return gdb_get_reg32(buf, vfp_get_fpsr(env)); | ||
525 | - case 33: | ||
526 | - return gdb_get_reg32(buf, vfp_get_fpcr(env)); | ||
527 | - /* then 16 predicates and the ffr */ | ||
528 | - case 34 ... 50: | ||
529 | - { | ||
530 | - int preg = reg - 34; | ||
531 | - int vq, len = 0; | ||
532 | - for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { | ||
533 | - len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); | ||
534 | - } | ||
535 | - return len; | ||
536 | - } | ||
537 | - case 51: | ||
538 | - { | ||
539 | - /* | ||
540 | - * We report in Vector Granules (VG) which is 64bit in a Z reg | ||
541 | - * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. | ||
542 | - */ | ||
543 | - int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1; | ||
544 | - return gdb_get_reg64(buf, vq * 2); | ||
545 | - } | ||
546 | - default: | ||
547 | - /* gdbstub asked for something out our range */ | ||
548 | - qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg); | ||
549 | - break; | ||
550 | - } | ||
551 | - | ||
552 | - return 0; | ||
553 | -} | ||
554 | - | ||
555 | -static int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) | ||
556 | -{ | ||
557 | - ARMCPU *cpu = env_archcpu(env); | ||
558 | - | ||
559 | - /* The first 32 registers are the zregs */ | ||
560 | - switch (reg) { | ||
561 | - /* The first 32 registers are the zregs */ | ||
562 | - case 0 ... 31: | ||
563 | - { | ||
564 | - int vq, len = 0; | ||
565 | - uint64_t *p = (uint64_t *) buf; | ||
566 | - for (vq = 0; vq < cpu->sve_max_vq; vq++) { | ||
567 | - env->vfp.zregs[reg].d[vq * 2 + 1] = *p++; | ||
568 | - env->vfp.zregs[reg].d[vq * 2] = *p++; | ||
569 | - len += 16; | ||
570 | - } | ||
571 | - return len; | ||
572 | - } | ||
573 | - case 32: | ||
574 | - vfp_set_fpsr(env, *(uint32_t *)buf); | ||
575 | - return 4; | ||
576 | - case 33: | ||
577 | - vfp_set_fpcr(env, *(uint32_t *)buf); | ||
578 | - return 4; | ||
579 | - case 34 ... 50: | ||
580 | - { | ||
581 | - int preg = reg - 34; | ||
582 | - int vq, len = 0; | ||
583 | - uint64_t *p = (uint64_t *) buf; | ||
584 | - for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) { | ||
585 | - env->vfp.pregs[preg].p[vq / 4] = *p++; | ||
586 | - len += 8; | ||
587 | - } | ||
588 | - return len; | ||
589 | - } | ||
590 | - case 51: | ||
591 | - /* cannot set vg via gdbstub */ | ||
592 | - return 0; | ||
593 | - default: | ||
594 | - /* gdbstub asked for something out our range */ | ||
595 | - break; | ||
596 | - } | ||
597 | - | ||
598 | - return 0; | ||
599 | -} | ||
600 | -#endif /* TARGET_AARCH64 */ | ||
601 | - | ||
602 | static bool raw_accessors_invalid(const ARMCPRegInfo *ri) | ||
603 | { | ||
604 | /* Return true if the regdef would cause an assertion if you called | ||
605 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
606 | #endif | ||
607 | } | ||
608 | |||
609 | -void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
610 | -{ | ||
611 | - CPUState *cs = CPU(cpu); | ||
612 | - CPUARMState *env = &cpu->env; | ||
613 | - | ||
614 | - if (arm_feature(env, ARM_FEATURE_AARCH64)) { | ||
615 | - /* | ||
616 | - * The lower part of each SVE register aliases to the FPU | ||
617 | - * registers so we don't need to include both. | ||
618 | - */ | ||
619 | -#ifdef TARGET_AARCH64 | ||
620 | - if (isar_feature_aa64_sve(&cpu->isar)) { | ||
621 | - gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg, | ||
622 | - arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs), | ||
623 | - "sve-registers.xml", 0); | ||
624 | - } else | ||
625 | -#endif | ||
626 | - { | ||
627 | - gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | ||
628 | - aarch64_fpu_gdb_set_reg, | ||
629 | - 34, "aarch64-fpu.xml", 0); | ||
630 | - } | ||
631 | - } else if (arm_feature(env, ARM_FEATURE_NEON)) { | ||
632 | - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, | ||
633 | - 51, "arm-neon.xml", 0); | ||
634 | - } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { | ||
635 | - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, | ||
636 | - 35, "arm-vfp3.xml", 0); | ||
637 | - } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
638 | - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, | ||
639 | - 19, "arm-vfp.xml", 0); | ||
640 | - } | ||
641 | - gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, | ||
642 | - arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), | ||
643 | - "system-registers.xml", 0); | ||
644 | - | ||
645 | -} | ||
646 | - | ||
647 | /* Sort alphabetically by type name, except for "any". */ | ||
648 | static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) | ||
649 | { | ||
123 | -- | 650 | -- |
124 | 2.20.1 | 651 | 2.20.1 |
125 | 652 | ||
126 | 653 | diff view generated by jsdifflib |
1 | Implement the MVE VHLL (vector shift left long) insn. This has two | 1 | Currently we send VFP XML which includes D0..D15 or D0..D31, plus |
---|---|---|---|
2 | encodings: the T1 encoding is the usual shift-by-immediate format, | 2 | FPSID, FPSCR and FPEXC. The upstream GDB tolerates this, but its |
3 | and the T2 encoding is a special case where the shift count is always | 3 | definition of this XML feature does not include FPSID or FPEXC. In |
4 | equal to the element size. | 4 | particular, for M-profile cores there are no FPSID or FPEXC |
5 | registers, so advertising those is wrong. | ||
6 | |||
7 | Move FPSID and FPEXC into their own bit of XML which we only send for | ||
8 | A and R profile cores. This brings our definition of the XML | ||
9 | org.gnu.gdb.arm.vfp feature into line with GDB's own (at least for | ||
10 | non-Neon cores...) and means we don't claim to have FPSID and FPEXC | ||
11 | on M-profile. | ||
12 | |||
13 | (It seems unlikely to me that any gdbstub users really care about | ||
14 | being able to look at FPEXC and FPSID; but we've supplied them to gdb | ||
15 | for a decade and it's not hard to keep doing so.) | ||
5 | 16 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20210628135835.6690-10-peter.maydell@linaro.org | 19 | Message-id: 20210921162901.17508-5-peter.maydell@linaro.org |
9 | --- | 20 | --- |
10 | target/arm/helper-mve.h | 9 +++++++ | 21 | configs/targets/aarch64-softmmu.mak | 2 +- |
11 | target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++--- | 22 | configs/targets/arm-linux-user.mak | 2 +- |
12 | target/arm/mve_helper.c | 32 +++++++++++++++++++++++ | 23 | configs/targets/arm-softmmu.mak | 2 +- |
13 | target/arm/translate-mve.c | 15 +++++++++++ | 24 | configs/targets/armeb-linux-user.mak | 2 +- |
14 | 4 files changed, 105 insertions(+), 4 deletions(-) | 25 | target/arm/gdbstub.c | 56 ++++++++++++++++++++-------- |
15 | 26 | gdb-xml/arm-neon.xml | 2 - | |
16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | 27 | gdb-xml/arm-vfp-sysregs.xml | 17 +++++++++ |
17 | index XXXXXXX..XXXXXXX 100644 | 28 | gdb-xml/arm-vfp.xml | 2 - |
18 | --- a/target/arm/helper-mve.h | 29 | gdb-xml/arm-vfp3.xml | 2 - |
19 | +++ b/target/arm/helper-mve.h | 30 | 9 files changed, 61 insertions(+), 26 deletions(-) |
20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 31 | create mode 100644 gdb-xml/arm-vfp-sysregs.xml |
21 | DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 32 | |
22 | DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 33 | diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak |
23 | DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 34 | index XXXXXXX..XXXXXXX 100644 |
24 | + | 35 | --- a/configs/targets/aarch64-softmmu.mak |
25 | +DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 36 | +++ b/configs/targets/aarch64-softmmu.mak |
26 | +DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 37 | @@ -XXX,XX +XXX,XX @@ |
27 | +DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 38 | TARGET_ARCH=aarch64 |
28 | +DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 39 | TARGET_BASE_ARCH=arm |
29 | +DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 40 | TARGET_SUPPORTS_MTTCG=y |
30 | +DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 41 | -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml |
31 | +DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 42 | +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml |
32 | +DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 43 | TARGET_NEED_FDT=y |
33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | 44 | diff --git a/configs/targets/arm-linux-user.mak b/configs/targets/arm-linux-user.mak |
34 | index XXXXXXX..XXXXXXX 100644 | 45 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/target/arm/mve.decode | 46 | --- a/configs/targets/arm-linux-user.mak |
36 | +++ b/target/arm/mve.decode | 47 | +++ b/configs/targets/arm-linux-user.mak |
37 | @@ -XXX,XX +XXX,XX @@ | 48 | @@ -XXX,XX +XXX,XX @@ |
38 | @2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 | 49 | TARGET_ARCH=arm |
39 | @2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 | 50 | TARGET_SYSTBL_ABI=common,oabi |
40 | 51 | TARGET_SYSTBL=syscall.tbl | |
41 | +@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0 | 52 | -TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml |
42 | +@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 | 53 | +TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml |
43 | +# VSHLL encoding T2 where shift == esize | 54 | TARGET_HAS_BFLT=y |
44 | +@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \ | 55 | CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y |
45 | + qd=%qd qm=%qm size=0 shift=8 | 56 | diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.mak |
46 | +@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \ | 57 | index XXXXXXX..XXXXXXX 100644 |
47 | + qd=%qd qm=%qm size=1 shift=16 | 58 | --- a/configs/targets/arm-softmmu.mak |
48 | + | 59 | +++ b/configs/targets/arm-softmmu.mak |
49 | # Right shifts are encoded as N - shift, where N is the element size in bits. | 60 | @@ -XXX,XX +XXX,XX @@ |
50 | %rshift_i5 16:5 !function=rsub_32 | 61 | TARGET_ARCH=arm |
51 | %rshift_i4 16:4 !function=rsub_16 | 62 | TARGET_SUPPORTS_MTTCG=y |
52 | @@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op | 63 | -TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml |
53 | VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op | 64 | +TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml |
54 | VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op | 65 | TARGET_NEED_FDT=y |
55 | 66 | diff --git a/configs/targets/armeb-linux-user.mak b/configs/targets/armeb-linux-user.mak | |
56 | -VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | 67 | index XXXXXXX..XXXXXXX 100644 |
57 | -VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | 68 | --- a/configs/targets/armeb-linux-user.mak |
58 | +# The VSHLL T2 encoding is not a @2op pattern, but is here because it | 69 | +++ b/configs/targets/armeb-linux-user.mak |
59 | +# overlaps what would be size=0b11 VMULH/VRMULH | 70 | @@ -XXX,XX +XXX,XX @@ TARGET_ARCH=arm |
71 | TARGET_SYSTBL_ABI=common,oabi | ||
72 | TARGET_SYSTBL=syscall.tbl | ||
73 | TARGET_WORDS_BIGENDIAN=y | ||
74 | -TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml | ||
75 | +TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml | ||
76 | TARGET_HAS_BFLT=y | ||
77 | CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y | ||
78 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | ||
79 | index XXXXXXX..XXXXXXX 100644 | ||
80 | --- a/target/arm/gdbstub.c | ||
81 | +++ b/target/arm/gdbstub.c | ||
82 | @@ -XXX,XX +XXX,XX @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) | ||
83 | } | ||
84 | switch (reg - nregs) { | ||
85 | case 0: | ||
86 | - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); | ||
87 | - case 1: | ||
88 | return gdb_get_reg32(buf, vfp_get_fpscr(env)); | ||
89 | - case 2: | ||
90 | - return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); | ||
91 | } | ||
92 | return 0; | ||
93 | } | ||
94 | @@ -XXX,XX +XXX,XX @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) | ||
95 | } | ||
96 | } | ||
97 | switch (reg - nregs) { | ||
98 | + case 0: | ||
99 | + vfp_set_fpscr(env, ldl_p(buf)); | ||
100 | + return 4; | ||
101 | + } | ||
102 | + return 0; | ||
103 | +} | ||
104 | + | ||
105 | +static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) | ||
60 | +{ | 106 | +{ |
61 | + VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b | 107 | + switch (reg) { |
62 | + VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h | 108 | + case 0: |
63 | 109 | + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); | |
64 | -VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | 110 | + case 1: |
65 | -VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | 111 | + return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPEXC]); |
66 | + VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | 112 | + } |
113 | + return 0; | ||
67 | +} | 114 | +} |
68 | + | 115 | + |
116 | +static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) | ||
69 | +{ | 117 | +{ |
70 | + VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b | 118 | + switch (reg) { |
71 | + VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h | 119 | case 0: |
72 | + | 120 | env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); |
73 | + VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | 121 | return 4; |
74 | +} | 122 | case 1: |
75 | + | 123 | - vfp_set_fpscr(env, ldl_p(buf)); |
76 | +{ | 124 | - return 4; |
77 | + VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b | 125 | - case 2: |
78 | + VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h | 126 | env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); |
79 | + | 127 | return 4; |
80 | + VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | 128 | } |
81 | +} | 129 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) |
82 | + | 130 | 34, "aarch64-fpu.xml", 0); |
83 | +{ | 131 | } |
84 | + VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b | 132 | #endif |
85 | + VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h | 133 | - } else if (arm_feature(env, ARM_FEATURE_NEON)) { |
86 | + | 134 | - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
87 | + VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | 135 | - 51, "arm-neon.xml", 0); |
88 | +} | 136 | - } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { |
89 | 137 | - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, | |
90 | VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op | 138 | - 35, "arm-vfp3.xml", 0); |
91 | VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op | 139 | - } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
92 | @@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | 140 | - gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
93 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | 141 | - 19, "arm-vfp.xml", 0); |
94 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | 142 | + } else { |
95 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | 143 | + if (arm_feature(env, ARM_FEATURE_NEON)) { |
96 | + | 144 | + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
97 | +# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file | 145 | + 49, "arm-neon.xml", 0); |
98 | +VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b | 146 | + } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { |
99 | +VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h | 147 | + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
100 | + | 148 | + 33, "arm-vfp3.xml", 0); |
101 | +VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b | 149 | + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
102 | +VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h | 150 | + gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, |
103 | + | 151 | + 17, "arm-vfp.xml", 0); |
104 | +VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b | 152 | + } |
105 | +VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h | 153 | + if (!arm_feature(env, ARM_FEATURE_M)) { |
106 | + | 154 | + /* |
107 | +VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b | 155 | + * A and R profile have FP sysregs FPEXC and FPSID that we |
108 | +VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h | 156 | + * expose to gdb. |
109 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | 157 | + */ |
110 | index XXXXXXX..XXXXXXX 100644 | 158 | + gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_sysreg, |
111 | --- a/target/arm/mve_helper.c | 159 | + 2, "arm-vfp-sysregs.xml", 0); |
112 | +++ b/target/arm/mve_helper.c | 160 | + } |
113 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) | 161 | } |
114 | DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | 162 | gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, |
115 | DO_2SHIFT_U(vrshli_u, DO_VRSHLU) | 163 | arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), |
116 | DO_2SHIFT_S(vrshli_s, DO_VRSHLS) | 164 | diff --git a/gdb-xml/arm-neon.xml b/gdb-xml/arm-neon.xml |
117 | + | 165 | index XXXXXXX..XXXXXXX 100644 |
118 | +/* | 166 | --- a/gdb-xml/arm-neon.xml |
119 | + * Long shifts taking half-sized inputs from top or bottom of the input | 167 | +++ b/gdb-xml/arm-neon.xml |
120 | + * vector and producing a double-width result. ESIZE, TYPE are for | 168 | @@ -XXX,XX +XXX,XX @@ |
121 | + * the input, and LESIZE, LTYPE for the output. | 169 | <reg name="q14" bitsize="128" type="neon_q"/> |
122 | + * Unlike the normal shift helpers, we do not handle negative shift counts, | 170 | <reg name="q15" bitsize="128" type="neon_q"/> |
123 | + * because the long shift is strictly left-only. | 171 | |
124 | + */ | 172 | - <reg name="fpsid" bitsize="32" type="int" group="float"/> |
125 | +#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ | 173 | <reg name="fpscr" bitsize="32" type="int" group="float"/> |
126 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | 174 | - <reg name="fpexc" bitsize="32" type="int" group="float"/> |
127 | + void *vm, uint32_t shift) \ | 175 | </feature> |
128 | + { \ | 176 | diff --git a/gdb-xml/arm-vfp-sysregs.xml b/gdb-xml/arm-vfp-sysregs.xml |
129 | + LTYPE *d = vd; \ | 177 | new file mode 100644 |
130 | + TYPE *m = vm; \ | 178 | index XXXXXXX..XXXXXXX |
131 | + uint16_t mask = mve_element_mask(env); \ | 179 | --- /dev/null |
132 | + unsigned le; \ | 180 | +++ b/gdb-xml/arm-vfp-sysregs.xml |
133 | + assert(shift <= 16); \ | 181 | @@ -XXX,XX +XXX,XX @@ |
134 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | 182 | +<?xml version="1.0"?> |
135 | + LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ | 183 | +<!-- Copyright (C) 2021 Linaro Ltd. |
136 | + mergemask(&d[H##LESIZE(le)], r, mask); \ | 184 | + |
137 | + } \ | 185 | + Copying and distribution of this file, with or without modification, |
138 | + mve_advance_vpt(env); \ | 186 | + are permitted in any medium without royalty provided the copyright |
139 | + } | 187 | + notice and this notice are preserved. |
140 | + | 188 | + |
141 | +#define DO_VSHLL_ALL(OP, TOP) \ | 189 | + These are A/R profile VFP system registers. Debugger users probably |
142 | + DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ | 190 | + don't really care about these, but because we used to (incorrectly) |
143 | + DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ | 191 | + provide them to gdb in the org.gnu.gdb.arm.vfp XML we continue |
144 | + DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ | 192 | + to do so via this separate XML. |
145 | + DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ | 193 | + --> |
146 | + | 194 | +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> |
147 | +DO_VSHLL_ALL(vshllb, false) | 195 | +<feature name="org.qemu.gdb.arm.vfp-sysregs"> |
148 | +DO_VSHLL_ALL(vshllt, true) | 196 | + <reg name="fpsid" bitsize="32" type="int" group="float"/> |
149 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | 197 | + <reg name="fpexc" bitsize="32" type="int" group="float"/> |
150 | index XXXXXXX..XXXXXXX 100644 | 198 | +</feature> |
151 | --- a/target/arm/translate-mve.c | 199 | diff --git a/gdb-xml/arm-vfp.xml b/gdb-xml/arm-vfp.xml |
152 | +++ b/target/arm/translate-mve.c | 200 | index XXXXXXX..XXXXXXX 100644 |
153 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true) | 201 | --- a/gdb-xml/arm-vfp.xml |
154 | DO_2SHIFT(VSHRI_U, vshli_u, true) | 202 | +++ b/gdb-xml/arm-vfp.xml |
155 | DO_2SHIFT(VRSHRI_S, vrshli_s, true) | 203 | @@ -XXX,XX +XXX,XX @@ |
156 | DO_2SHIFT(VRSHRI_U, vrshli_u, true) | 204 | <reg name="d14" bitsize="64" type="float"/> |
157 | + | 205 | <reg name="d15" bitsize="64" type="float"/> |
158 | +#define DO_VSHLL(INSN, FN) \ | 206 | |
159 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | 207 | - <reg name="fpsid" bitsize="32" type="int" group="float"/> |
160 | + { \ | 208 | <reg name="fpscr" bitsize="32" type="int" group="float"/> |
161 | + static MVEGenTwoOpShiftFn * const fns[] = { \ | 209 | - <reg name="fpexc" bitsize="32" type="int" group="float"/> |
162 | + gen_helper_mve_##FN##b, \ | 210 | </feature> |
163 | + gen_helper_mve_##FN##h, \ | 211 | diff --git a/gdb-xml/arm-vfp3.xml b/gdb-xml/arm-vfp3.xml |
164 | + }; \ | 212 | index XXXXXXX..XXXXXXX 100644 |
165 | + return do_2shift(s, a, fns[a->size], false); \ | 213 | --- a/gdb-xml/arm-vfp3.xml |
166 | + } | 214 | +++ b/gdb-xml/arm-vfp3.xml |
167 | + | 215 | @@ -XXX,XX +XXX,XX @@ |
168 | +DO_VSHLL(VSHLL_BS, vshllbs) | 216 | <reg name="d30" bitsize="64" type="float"/> |
169 | +DO_VSHLL(VSHLL_BU, vshllbu) | 217 | <reg name="d31" bitsize="64" type="float"/> |
170 | +DO_VSHLL(VSHLL_TS, vshllts) | 218 | |
171 | +DO_VSHLL(VSHLL_TU, vshlltu) | 219 | - <reg name="fpsid" bitsize="32" type="int" group="float"/> |
220 | <reg name="fpscr" bitsize="32" type="int" group="float"/> | ||
221 | - <reg name="fpexc" bitsize="32" type="int" group="float"/> | ||
222 | </feature> | ||
172 | -- | 223 | -- |
173 | 2.20.1 | 224 | 2.20.1 |
174 | 225 | ||
175 | 226 | diff view generated by jsdifflib |
1 | The A64 AdvSIMD modified-immediate grouping uses almost the same | 1 | The function scsi_bus_new() creates a new SCSI bus; callers can |
---|---|---|---|
2 | constant encoding that A32 Neon does; reuse asimd_imm_const() (to | 2 | either pass in a name argument to specify the name of the new bus, or |
3 | which we add the AArch64-specific case for cmode 15 op 1) instead of | 3 | they can pass in NULL to allow the bus to be given an automatically |
4 | reimplementing it all. | 4 | generated unique name. Almost all callers want to use the |
5 | autogenerated name; the only exception is the virtio-scsi device. | ||
6 | |||
7 | Taking a name argument that should almost always be NULL is an | ||
8 | easy-to-misuse API design -- it encourages callers to think perhaps | ||
9 | they should pass in some standard name like "scsi" or "scsi-bus". We | ||
10 | don't do this anywhere for SCSI, but we do (incorrectly) do it for | ||
11 | other bus types such as i2c. | ||
12 | |||
13 | The function name also implies that it will return a newly allocated | ||
14 | object, when it in fact does in-place allocation. We more commonly | ||
15 | name such functions foo_init(), with foo_new() being the | ||
16 | allocate-and-return variant. | ||
17 | |||
18 | Replace all the scsi_bus_new() callsites with either: | ||
19 | * scsi_bus_init() for the usual case where the caller wants | ||
20 | an autogenerated bus name | ||
21 | * scsi_bus_init_named() for the rare case where the caller | ||
22 | needs to specify the bus name | ||
23 | |||
24 | and document that for the _named() version it's then the caller's | ||
25 | responsibility to think about uniqueness of bus names. | ||
5 | 26 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 28 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
8 | Message-id: 20210628135835.6690-5-peter.maydell@linaro.org | 29 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> |
30 | Acked-by: Paolo Bonzini <pbonzini@redhat.com> | ||
31 | Message-id: 20210923121153.23754-2-peter.maydell@linaro.org | ||
9 | --- | 32 | --- |
10 | target/arm/translate.h | 3 +- | 33 | include/hw/scsi/scsi.h | 30 ++++++++++++++++++++++++++++-- |
11 | target/arm/translate-a64.c | 86 ++++---------------------------------- | 34 | hw/scsi/esp-pci.c | 2 +- |
12 | target/arm/translate.c | 17 +++++++- | 35 | hw/scsi/esp.c | 2 +- |
13 | 3 files changed, 24 insertions(+), 82 deletions(-) | 36 | hw/scsi/lsi53c895a.c | 2 +- |
14 | 37 | hw/scsi/megasas.c | 3 +-- | |
15 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 38 | hw/scsi/mptsas.c | 2 +- |
16 | index XXXXXXX..XXXXXXX 100644 | 39 | hw/scsi/scsi-bus.c | 4 ++-- |
17 | --- a/target/arm/translate.h | 40 | hw/scsi/spapr_vscsi.c | 3 +-- |
18 | +++ b/target/arm/translate.h | 41 | hw/scsi/virtio-scsi.c | 4 ++-- |
19 | @@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc) | 42 | hw/scsi/vmw_pvscsi.c | 3 +-- |
20 | * VMVN and VBIC (when cmode < 14 && op == 1). | 43 | hw/usb/dev-storage-bot.c | 3 +-- |
21 | * | 44 | hw/usb/dev-storage-classic.c | 4 ++-- |
22 | * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; | 45 | hw/usb/dev-uas.c | 3 +-- |
23 | - * callers must catch this. | 46 | 13 files changed, 43 insertions(+), 22 deletions(-) |
24 | + * callers must catch this; we return the 64-bit constant value defined | 47 | |
25 | + * for AArch64. | 48 | diff --git a/include/hw/scsi/scsi.h b/include/hw/scsi/scsi.h |
26 | * | 49 | index XXXXXXX..XXXXXXX 100644 |
27 | * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but | 50 | --- a/include/hw/scsi/scsi.h |
28 | * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; | 51 | +++ b/include/hw/scsi/scsi.h |
29 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 52 | @@ -XXX,XX +XXX,XX @@ struct SCSIBus { |
30 | index XXXXXXX..XXXXXXX 100644 | 53 | const SCSIBusInfo *info; |
31 | --- a/target/arm/translate-a64.c | 54 | }; |
32 | +++ b/target/arm/translate-a64.c | 55 | |
33 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | 56 | -void scsi_bus_new(SCSIBus *bus, size_t bus_size, DeviceState *host, |
57 | - const SCSIBusInfo *info, const char *bus_name); | ||
58 | +/** | ||
59 | + * scsi_bus_init_named: Initialize a SCSI bus with the specified name | ||
60 | + * @bus: SCSIBus object to initialize | ||
61 | + * @bus_size: size of @bus object | ||
62 | + * @host: Device which owns the bus (generally the SCSI controller) | ||
63 | + * @info: structure defining callbacks etc for the controller | ||
64 | + * @bus_name: Name to use for this bus | ||
65 | + * | ||
66 | + * This in-place initializes @bus as a new SCSI bus with a name | ||
67 | + * provided by the caller. It is the caller's responsibility to make | ||
68 | + * sure that name does not clash with the name of any other bus in the | ||
69 | + * system. Unless you need the new bus to have a specific name, you | ||
70 | + * should use scsi_bus_new() instead. | ||
71 | + */ | ||
72 | +void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host, | ||
73 | + const SCSIBusInfo *info, const char *bus_name); | ||
74 | + | ||
75 | +/** | ||
76 | + * scsi_bus_init: Initialize a SCSI bus | ||
77 | + * | ||
78 | + * This in-place-initializes @bus as a new SCSI bus and gives it | ||
79 | + * an automatically generated unique name. | ||
80 | + */ | ||
81 | +static inline void scsi_bus_init(SCSIBus *bus, size_t bus_size, | ||
82 | + DeviceState *host, const SCSIBusInfo *info) | ||
83 | +{ | ||
84 | + scsi_bus_init_named(bus, bus_size, host, info, NULL); | ||
85 | +} | ||
86 | |||
87 | static inline SCSIBus *scsi_bus_from_device(SCSIDevice *d) | ||
34 | { | 88 | { |
35 | int rd = extract32(insn, 0, 5); | 89 | diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c |
36 | int cmode = extract32(insn, 12, 4); | 90 | index XXXXXXX..XXXXXXX 100644 |
37 | - int cmode_3_1 = extract32(cmode, 1, 3); | 91 | --- a/hw/scsi/esp-pci.c |
38 | - int cmode_0 = extract32(cmode, 0, 1); | 92 | +++ b/hw/scsi/esp-pci.c |
39 | int o2 = extract32(insn, 11, 1); | 93 | @@ -XXX,XX +XXX,XX @@ static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp) |
40 | uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); | 94 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io); |
41 | bool is_neg = extract32(insn, 29, 1); | 95 | s->irq = pci_allocate_irq(dev); |
42 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | 96 | |
97 | - scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL); | ||
98 | + scsi_bus_init(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info); | ||
99 | } | ||
100 | |||
101 | static void esp_pci_scsi_exit(PCIDevice *d) | ||
102 | diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c | ||
103 | index XXXXXXX..XXXXXXX 100644 | ||
104 | --- a/hw/scsi/esp.c | ||
105 | +++ b/hw/scsi/esp.c | ||
106 | @@ -XXX,XX +XXX,XX @@ static void sysbus_esp_realize(DeviceState *dev, Error **errp) | ||
107 | |||
108 | qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); | ||
109 | |||
110 | - scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL); | ||
111 | + scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); | ||
112 | } | ||
113 | |||
114 | static void sysbus_esp_hard_reset(DeviceState *dev) | ||
115 | diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c | ||
116 | index XXXXXXX..XXXXXXX 100644 | ||
117 | --- a/hw/scsi/lsi53c895a.c | ||
118 | +++ b/hw/scsi/lsi53c895a.c | ||
119 | @@ -XXX,XX +XXX,XX @@ static void lsi_scsi_realize(PCIDevice *dev, Error **errp) | ||
120 | pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_io); | ||
121 | QTAILQ_INIT(&s->queue); | ||
122 | |||
123 | - scsi_bus_new(&s->bus, sizeof(s->bus), d, &lsi_scsi_info, NULL); | ||
124 | + scsi_bus_init(&s->bus, sizeof(s->bus), d, &lsi_scsi_info); | ||
125 | } | ||
126 | |||
127 | static void lsi_scsi_exit(PCIDevice *dev) | ||
128 | diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c | ||
129 | index XXXXXXX..XXXXXXX 100644 | ||
130 | --- a/hw/scsi/megasas.c | ||
131 | +++ b/hw/scsi/megasas.c | ||
132 | @@ -XXX,XX +XXX,XX @@ static void megasas_scsi_realize(PCIDevice *dev, Error **errp) | ||
133 | s->frames[i].state = s; | ||
134 | } | ||
135 | |||
136 | - scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev), | ||
137 | - &megasas_scsi_info, NULL); | ||
138 | + scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &megasas_scsi_info); | ||
139 | } | ||
140 | |||
141 | static Property megasas_properties_gen1[] = { | ||
142 | diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c | ||
143 | index XXXXXXX..XXXXXXX 100644 | ||
144 | --- a/hw/scsi/mptsas.c | ||
145 | +++ b/hw/scsi/mptsas.c | ||
146 | @@ -XXX,XX +XXX,XX @@ static void mptsas_scsi_realize(PCIDevice *dev, Error **errp) | ||
147 | |||
148 | s->request_bh = qemu_bh_new(mptsas_fetch_requests, s); | ||
149 | |||
150 | - scsi_bus_new(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info, NULL); | ||
151 | + scsi_bus_init(&s->bus, sizeof(s->bus), &dev->qdev, &mptsas_scsi_info); | ||
152 | } | ||
153 | |||
154 | static void mptsas_scsi_uninit(PCIDevice *dev) | ||
155 | diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c | ||
156 | index XXXXXXX..XXXXXXX 100644 | ||
157 | --- a/hw/scsi/scsi-bus.c | ||
158 | +++ b/hw/scsi/scsi-bus.c | ||
159 | @@ -XXX,XX +XXX,XX @@ void scsi_device_unit_attention_reported(SCSIDevice *s) | ||
160 | } | ||
161 | |||
162 | /* Create a scsi bus, and attach devices to it. */ | ||
163 | -void scsi_bus_new(SCSIBus *bus, size_t bus_size, DeviceState *host, | ||
164 | - const SCSIBusInfo *info, const char *bus_name) | ||
165 | +void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host, | ||
166 | + const SCSIBusInfo *info, const char *bus_name) | ||
167 | { | ||
168 | qbus_create_inplace(bus, bus_size, TYPE_SCSI_BUS, host, bus_name); | ||
169 | bus->busnr = next_scsi_bus++; | ||
170 | diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c | ||
171 | index XXXXXXX..XXXXXXX 100644 | ||
172 | --- a/hw/scsi/spapr_vscsi.c | ||
173 | +++ b/hw/scsi/spapr_vscsi.c | ||
174 | @@ -XXX,XX +XXX,XX @@ static void spapr_vscsi_realize(SpaprVioDevice *dev, Error **errp) | ||
175 | |||
176 | dev->crq.SendFunc = vscsi_do_crq; | ||
177 | |||
178 | - scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev), | ||
179 | - &vscsi_scsi_info, NULL); | ||
180 | + scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &vscsi_scsi_info); | ||
181 | |||
182 | /* ibmvscsi SCSI bus does not allow hotplug. */ | ||
183 | qbus_set_hotplug_handler(BUS(&s->bus), NULL); | ||
184 | diff --git a/hw/scsi/virtio-scsi.c b/hw/scsi/virtio-scsi.c | ||
185 | index XXXXXXX..XXXXXXX 100644 | ||
186 | --- a/hw/scsi/virtio-scsi.c | ||
187 | +++ b/hw/scsi/virtio-scsi.c | ||
188 | @@ -XXX,XX +XXX,XX @@ static void virtio_scsi_device_realize(DeviceState *dev, Error **errp) | ||
43 | return; | 189 | return; |
44 | } | 190 | } |
45 | 191 | ||
46 | - /* See AdvSIMDExpandImm() in ARM ARM */ | 192 | - scsi_bus_new(&s->bus, sizeof(s->bus), dev, |
47 | - switch (cmode_3_1) { | 193 | - &virtio_scsi_scsi_info, vdev->bus_name); |
48 | - case 0: /* Replicate(Zeros(24):imm8, 2) */ | 194 | + scsi_bus_init_named(&s->bus, sizeof(s->bus), dev, |
49 | - case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ | 195 | + &virtio_scsi_scsi_info, vdev->bus_name); |
50 | - case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ | 196 | /* override default SCSI bus hotplug-handler, with virtio-scsi's one */ |
51 | - case 3: /* Replicate(imm8:Zeros(24), 2) */ | 197 | qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(dev)); |
52 | - { | 198 | |
53 | - int shift = cmode_3_1 * 8; | 199 | diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c |
54 | - imm = bitfield_replicate(abcdefgh << shift, 32); | 200 | index XXXXXXX..XXXXXXX 100644 |
55 | - break; | 201 | --- a/hw/scsi/vmw_pvscsi.c |
56 | - } | 202 | +++ b/hw/scsi/vmw_pvscsi.c |
57 | - case 4: /* Replicate(Zeros(8):imm8, 4) */ | 203 | @@ -XXX,XX +XXX,XX @@ pvscsi_realizefn(PCIDevice *pci_dev, Error **errp) |
58 | - case 5: /* Replicate(imm8:Zeros(8), 4) */ | 204 | |
59 | - { | 205 | s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s); |
60 | - int shift = (cmode_3_1 & 0x1) * 8; | 206 | |
61 | - imm = bitfield_replicate(abcdefgh << shift, 16); | 207 | - scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev), |
62 | - break; | 208 | - &pvscsi_scsi_info, NULL); |
63 | - } | 209 | + scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev), &pvscsi_scsi_info); |
64 | - case 6: | 210 | /* override default SCSI bus hotplug-handler, with pvscsi's one */ |
65 | - if (cmode_0) { | 211 | qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(s)); |
66 | - /* Replicate(Zeros(8):imm8:Ones(16), 2) */ | 212 | pvscsi_reset_state(s); |
67 | - imm = (abcdefgh << 16) | 0xffff; | 213 | diff --git a/hw/usb/dev-storage-bot.c b/hw/usb/dev-storage-bot.c |
68 | - } else { | 214 | index XXXXXXX..XXXXXXX 100644 |
69 | - /* Replicate(Zeros(16):imm8:Ones(8), 2) */ | 215 | --- a/hw/usb/dev-storage-bot.c |
70 | - imm = (abcdefgh << 8) | 0xff; | 216 | +++ b/hw/usb/dev-storage-bot.c |
71 | - } | 217 | @@ -XXX,XX +XXX,XX @@ static void usb_msd_bot_realize(USBDevice *dev, Error **errp) |
72 | - imm = bitfield_replicate(imm, 32); | 218 | s->dev.auto_attach = 0; |
73 | - break; | ||
74 | - case 7: | ||
75 | - if (!cmode_0 && !is_neg) { | ||
76 | - imm = bitfield_replicate(abcdefgh, 8); | ||
77 | - } else if (!cmode_0 && is_neg) { | ||
78 | - int i; | ||
79 | - imm = 0; | ||
80 | - for (i = 0; i < 8; i++) { | ||
81 | - if ((abcdefgh) & (1 << i)) { | ||
82 | - imm |= 0xffULL << (i * 8); | ||
83 | - } | ||
84 | - } | ||
85 | - } else if (cmode_0) { | ||
86 | - if (is_neg) { | ||
87 | - imm = (abcdefgh & 0x3f) << 48; | ||
88 | - if (abcdefgh & 0x80) { | ||
89 | - imm |= 0x8000000000000000ULL; | ||
90 | - } | ||
91 | - if (abcdefgh & 0x40) { | ||
92 | - imm |= 0x3fc0000000000000ULL; | ||
93 | - } else { | ||
94 | - imm |= 0x4000000000000000ULL; | ||
95 | - } | ||
96 | - } else { | ||
97 | - if (o2) { | ||
98 | - /* FMOV (vector, immediate) - half-precision */ | ||
99 | - imm = vfp_expand_imm(MO_16, abcdefgh); | ||
100 | - /* now duplicate across the lanes */ | ||
101 | - imm = bitfield_replicate(imm, 16); | ||
102 | - } else { | ||
103 | - imm = (abcdefgh & 0x3f) << 19; | ||
104 | - if (abcdefgh & 0x80) { | ||
105 | - imm |= 0x80000000; | ||
106 | - } | ||
107 | - if (abcdefgh & 0x40) { | ||
108 | - imm |= 0x3e000000; | ||
109 | - } else { | ||
110 | - imm |= 0x40000000; | ||
111 | - } | ||
112 | - imm |= (imm << 32); | ||
113 | - } | ||
114 | - } | ||
115 | - } | ||
116 | - break; | ||
117 | - default: | ||
118 | - g_assert_not_reached(); | ||
119 | - } | ||
120 | - | ||
121 | - if (cmode_3_1 != 7 && is_neg) { | ||
122 | - imm = ~imm; | ||
123 | + if (cmode == 15 && o2 && !is_neg) { | ||
124 | + /* FMOV (vector, immediate) - half-precision */ | ||
125 | + imm = vfp_expand_imm(MO_16, abcdefgh); | ||
126 | + /* now duplicate across the lanes */ | ||
127 | + imm = bitfield_replicate(imm, 16); | ||
128 | + } else { | ||
129 | + imm = asimd_imm_const(abcdefgh, cmode, is_neg); | ||
130 | } | 219 | } |
131 | 220 | ||
132 | if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) { | 221 | - scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev), |
133 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 222 | - &usb_msd_scsi_info_bot, NULL); |
134 | index XXXXXXX..XXXXXXX 100644 | 223 | + scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &usb_msd_scsi_info_bot); |
135 | --- a/target/arm/translate.c | 224 | usb_msd_handle_reset(dev); |
136 | +++ b/target/arm/translate.c | 225 | } |
137 | @@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) | 226 | |
138 | case 14: | 227 | diff --git a/hw/usb/dev-storage-classic.c b/hw/usb/dev-storage-classic.c |
139 | if (op) { | 228 | index XXXXXXX..XXXXXXX 100644 |
140 | /* | 229 | --- a/hw/usb/dev-storage-classic.c |
141 | - * This is the only case where the top and bottom 32 bits | 230 | +++ b/hw/usb/dev-storage-classic.c |
142 | - * of the encoded constant differ. | 231 | @@ -XXX,XX +XXX,XX @@ static void usb_msd_storage_realize(USBDevice *dev, Error **errp) |
143 | + * This and cmode == 15 op == 1 are the only cases where | 232 | usb_desc_create_serial(dev); |
144 | + * the top and bottom 32 bits of the encoded constant differ. | 233 | usb_desc_init(dev); |
145 | */ | 234 | dev->flags |= (1 << USB_DEV_FLAG_IS_SCSI_STORAGE); |
146 | uint64_t imm64 = 0; | 235 | - scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev), |
147 | int n; | 236 | - &usb_msd_scsi_info_storage, NULL); |
148 | @@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) | 237 | + scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), |
149 | imm |= (imm << 8) | (imm << 16) | (imm << 24); | 238 | + &usb_msd_scsi_info_storage); |
150 | break; | 239 | scsi_dev = scsi_bus_legacy_add_drive(&s->bus, blk, 0, !!s->removable, |
151 | case 15: | 240 | s->conf.bootindex, s->conf.share_rw, |
152 | + if (op) { | 241 | s->conf.rerror, s->conf.werror, |
153 | + /* Reserved encoding for AArch32; valid for AArch64 */ | 242 | diff --git a/hw/usb/dev-uas.c b/hw/usb/dev-uas.c |
154 | + uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48; | 243 | index XXXXXXX..XXXXXXX 100644 |
155 | + if (imm & 0x80) { | 244 | --- a/hw/usb/dev-uas.c |
156 | + imm64 |= 0x8000000000000000ULL; | 245 | +++ b/hw/usb/dev-uas.c |
157 | + } | 246 | @@ -XXX,XX +XXX,XX @@ static void usb_uas_realize(USBDevice *dev, Error **errp) |
158 | + if (imm & 0x40) { | 247 | uas->status_bh = qemu_bh_new(usb_uas_send_status_bh, uas); |
159 | + imm64 |= 0x3fc0000000000000ULL; | 248 | |
160 | + } else { | 249 | dev->flags |= (1 << USB_DEV_FLAG_IS_SCSI_STORAGE); |
161 | + imm64 |= 0x4000000000000000ULL; | 250 | - scsi_bus_new(&uas->bus, sizeof(uas->bus), DEVICE(dev), |
162 | + } | 251 | - &usb_uas_scsi_info, NULL); |
163 | + return imm64; | 252 | + scsi_bus_init(&uas->bus, sizeof(uas->bus), DEVICE(dev), &usb_uas_scsi_info); |
164 | + } | 253 | } |
165 | imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | 254 | |
166 | | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | 255 | static const VMStateDescription vmstate_usb_uas = { |
167 | break; | ||
168 | -- | 256 | -- |
169 | 2.20.1 | 257 | 2.20.1 |
170 | 258 | ||
171 | 259 | diff view generated by jsdifflib |
1 | Implement the MVE vector shift right by immediate insns VSHRI and | 1 | Rename ipack_bus_new_inplace() to ipack_bus_init(), to bring it in to |
---|---|---|---|
2 | VRSHRI. As with Neon, we implement these by using helper functions | 2 | line with a "_init for in-place init, _new for allocate-and-return" |
3 | which perform left shifts but allow negative shift counts to indicate | 3 | convention. Drop the 'name' argument, because the only caller does |
4 | right shifts. | 4 | not pass in a name. If a future caller does need to specify the bus |
5 | name, we should create an ipack_bus_init_named() function at that | ||
6 | point. | ||
5 | 7 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
8 | Message-id: 20210628135835.6690-9-peter.maydell@linaro.org | 10 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> |
11 | Message-id: 20210923121153.23754-3-peter.maydell@linaro.org | ||
9 | --- | 12 | --- |
10 | target/arm/helper-mve.h | 12 ++++++++++++ | 13 | include/hw/ipack/ipack.h | 8 ++++---- |
11 | target/arm/translate.h | 20 ++++++++++++++++++++ | 14 | hw/ipack/ipack.c | 10 +++++----- |
12 | target/arm/mve.decode | 28 ++++++++++++++++++++++++++++ | 15 | hw/ipack/tpci200.c | 4 ++-- |
13 | target/arm/mve_helper.c | 7 +++++++ | 16 | 3 files changed, 11 insertions(+), 11 deletions(-) |
14 | target/arm/translate-mve.c | 5 +++++ | ||
15 | target/arm/translate-neon.c | 18 ------------------ | ||
16 | 6 files changed, 72 insertions(+), 18 deletions(-) | ||
17 | 17 | ||
18 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | 18 | diff --git a/include/hw/ipack/ipack.h b/include/hw/ipack/ipack.h |
19 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/helper-mve.h | 20 | --- a/include/hw/ipack/ipack.h |
21 | +++ b/target/arm/helper-mve.h | 21 | +++ b/include/hw/ipack/ipack.h |
22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) | 22 | @@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ipack_device; |
23 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) | 23 | VMSTATE_STRUCT(_field, _state, 1, vmstate_ipack_device, IPackDevice) |
24 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | 24 | |
25 | 25 | IPackDevice *ipack_device_find(IPackBus *bus, int32_t slot); | |
26 | +DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 26 | -void ipack_bus_new_inplace(IPackBus *bus, size_t bus_size, |
27 | +DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 27 | - DeviceState *parent, |
28 | +DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 28 | - const char *name, uint8_t n_slots, |
29 | + | 29 | - qemu_irq_handler handler); |
30 | DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 30 | +void ipack_bus_init(IPackBus *bus, size_t bus_size, |
31 | DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 31 | + DeviceState *parent, |
32 | DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 32 | + uint8_t n_slots, |
33 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 33 | + qemu_irq_handler handler); |
34 | DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 34 | |
35 | DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 35 | #endif |
36 | DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | 36 | diff --git a/hw/ipack/ipack.c b/hw/ipack/ipack.c |
37 | + | ||
38 | +DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
39 | +DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
40 | +DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
41 | + | ||
42 | +DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
43 | +DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
44 | +DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
45 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
46 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
47 | --- a/target/arm/translate.h | 38 | --- a/hw/ipack/ipack.c |
48 | +++ b/target/arm/translate.h | 39 | +++ b/hw/ipack/ipack.c |
49 | @@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x) | 40 | @@ -XXX,XX +XXX,XX @@ IPackDevice *ipack_device_find(IPackBus *bus, int32_t slot) |
50 | return x * 2 + 1; | 41 | return NULL; |
51 | } | 42 | } |
52 | 43 | ||
53 | +static inline int rsub_64(DisasContext *s, int x) | 44 | -void ipack_bus_new_inplace(IPackBus *bus, size_t bus_size, |
54 | +{ | 45 | - DeviceState *parent, |
55 | + return 64 - x; | 46 | - const char *name, uint8_t n_slots, |
56 | +} | 47 | - qemu_irq_handler handler) |
57 | + | 48 | +void ipack_bus_init(IPackBus *bus, size_t bus_size, |
58 | +static inline int rsub_32(DisasContext *s, int x) | 49 | + DeviceState *parent, |
59 | +{ | 50 | + uint8_t n_slots, |
60 | + return 32 - x; | 51 | + qemu_irq_handler handler) |
61 | +} | ||
62 | + | ||
63 | +static inline int rsub_16(DisasContext *s, int x) | ||
64 | +{ | ||
65 | + return 16 - x; | ||
66 | +} | ||
67 | + | ||
68 | +static inline int rsub_8(DisasContext *s, int x) | ||
69 | +{ | ||
70 | + return 8 - x; | ||
71 | +} | ||
72 | + | ||
73 | static inline int arm_dc_feature(DisasContext *dc, int feature) | ||
74 | { | 52 | { |
75 | return (dc->features & (1ULL << feature)) != 0; | 53 | - qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, name); |
76 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | 54 | + qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, NULL); |
55 | bus->n_slots = n_slots; | ||
56 | bus->set_irq = handler; | ||
57 | } | ||
58 | diff --git a/hw/ipack/tpci200.c b/hw/ipack/tpci200.c | ||
77 | index XXXXXXX..XXXXXXX 100644 | 59 | index XXXXXXX..XXXXXXX 100644 |
78 | --- a/target/arm/mve.decode | 60 | --- a/hw/ipack/tpci200.c |
79 | +++ b/target/arm/mve.decode | 61 | +++ b/hw/ipack/tpci200.c |
80 | @@ -XXX,XX +XXX,XX @@ | 62 | @@ -XXX,XX +XXX,XX @@ static void tpci200_realize(PCIDevice *pci_dev, Error **errp) |
81 | @2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 | 63 | pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las2); |
82 | @2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 | 64 | pci_register_bar(&s->dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las3); |
83 | 65 | ||
84 | +# Right shifts are encoded as N - shift, where N is the element size in bits. | 66 | - ipack_bus_new_inplace(&s->bus, sizeof(s->bus), DEVICE(pci_dev), NULL, |
85 | +%rshift_i5 16:5 !function=rsub_32 | 67 | - N_MODULES, tpci200_set_irq); |
86 | +%rshift_i4 16:4 !function=rsub_16 | 68 | + ipack_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev), |
87 | +%rshift_i3 16:3 !function=rsub_8 | 69 | + N_MODULES, tpci200_set_irq); |
88 | + | ||
89 | +@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
90 | + size=0 shift=%rshift_i3 | ||
91 | +@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
92 | + size=1 shift=%rshift_i4 | ||
93 | +@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
94 | + size=2 shift=%rshift_i5 | ||
95 | + | ||
96 | # Vector loads and stores | ||
97 | |||
98 | # Widening loads and narrowing stores: | ||
99 | @@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
100 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b | ||
101 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h | ||
102 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w | ||
103 | + | ||
104 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b | ||
105 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h | ||
106 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w | ||
107 | + | ||
108 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b | ||
109 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h | ||
110 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w | ||
111 | + | ||
112 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | ||
113 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | ||
114 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
115 | + | ||
116 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | ||
117 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | ||
118 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
119 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
120 | index XXXXXXX..XXXXXXX 100644 | ||
121 | --- a/target/arm/mve_helper.c | ||
122 | +++ b/target/arm/mve_helper.c | ||
123 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t) | ||
124 | DO_2SHIFT(OP##b, 1, uint8_t, FN) \ | ||
125 | DO_2SHIFT(OP##h, 2, uint16_t, FN) \ | ||
126 | DO_2SHIFT(OP##w, 4, uint32_t, FN) | ||
127 | +#define DO_2SHIFT_S(OP, FN) \ | ||
128 | + DO_2SHIFT(OP##b, 1, int8_t, FN) \ | ||
129 | + DO_2SHIFT(OP##h, 2, int16_t, FN) \ | ||
130 | + DO_2SHIFT(OP##w, 4, int32_t, FN) | ||
131 | |||
132 | #define DO_2SHIFT_SAT_U(OP, FN) \ | ||
133 | DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ | ||
134 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t) | ||
135 | DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) | ||
136 | |||
137 | DO_2SHIFT_U(vshli_u, DO_VSHLU) | ||
138 | +DO_2SHIFT_S(vshli_s, DO_VSHLS) | ||
139 | DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) | ||
140 | DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) | ||
141 | DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
142 | +DO_2SHIFT_U(vrshli_u, DO_VRSHLU) | ||
143 | +DO_2SHIFT_S(vrshli_s, DO_VRSHLS) | ||
144 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
145 | index XXXXXXX..XXXXXXX 100644 | ||
146 | --- a/target/arm/translate-mve.c | ||
147 | +++ b/target/arm/translate-mve.c | ||
148 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false) | ||
149 | DO_2SHIFT(VQSHLI_S, vqshli_s, false) | ||
150 | DO_2SHIFT(VQSHLI_U, vqshli_u, false) | ||
151 | DO_2SHIFT(VQSHLUI, vqshlui_s, false) | ||
152 | +/* These right shifts use a left-shift helper with negated shift count */ | ||
153 | +DO_2SHIFT(VSHRI_S, vshli_s, true) | ||
154 | +DO_2SHIFT(VSHRI_U, vshli_u, true) | ||
155 | +DO_2SHIFT(VRSHRI_S, vrshli_s, true) | ||
156 | +DO_2SHIFT(VRSHRI_U, vrshli_u, true) | ||
157 | diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c | ||
158 | index XXXXXXX..XXXXXXX 100644 | ||
159 | --- a/target/arm/translate-neon.c | ||
160 | +++ b/target/arm/translate-neon.c | ||
161 | @@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x) | ||
162 | return x + 1; | ||
163 | } | 70 | } |
164 | 71 | ||
165 | -static inline int rsub_64(DisasContext *s, int x) | 72 | static const VMStateDescription vmstate_tpci200 = { |
166 | -{ | ||
167 | - return 64 - x; | ||
168 | -} | ||
169 | - | ||
170 | -static inline int rsub_32(DisasContext *s, int x) | ||
171 | -{ | ||
172 | - return 32 - x; | ||
173 | -} | ||
174 | -static inline int rsub_16(DisasContext *s, int x) | ||
175 | -{ | ||
176 | - return 16 - x; | ||
177 | -} | ||
178 | -static inline int rsub_8(DisasContext *s, int x) | ||
179 | -{ | ||
180 | - return 8 - x; | ||
181 | -} | ||
182 | - | ||
183 | static inline int neon_3same_fp_size(DisasContext *s, int x) | ||
184 | { | ||
185 | /* Convert 0==fp32, 1==fp16 into a MO_* value */ | ||
186 | -- | 73 | -- |
187 | 2.20.1 | 74 | 2.20.1 |
188 | 75 | ||
189 | 76 | diff view generated by jsdifflib |
1 | The function asimd_imm_const() in translate-neon.c is an | 1 | Rename the pci_root_bus_new_inplace() function to |
---|---|---|---|
2 | implementation of the pseudocode AdvSIMDExpandImm(), which we will | 2 | pci_root_bus_init(); this brings the bus type in to line with a |
3 | also want for MVE. Move the implementation to translate.c, with a | 3 | "_init for in-place init, _new for allocate-and-return" convention. |
4 | prototype in translate.h. | 4 | To do this we need to rename the implementation-internal function |
5 | that was using the pci_root_bus_init() name to | ||
6 | pci_root_bus_internal_init(). | ||
5 | 7 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
8 | Message-id: 20210628135835.6690-4-peter.maydell@linaro.org | 10 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> |
11 | Message-id: 20210923121153.23754-4-peter.maydell@linaro.org | ||
9 | --- | 12 | --- |
10 | target/arm/translate.h | 16 ++++++++++ | 13 | include/hw/pci/pci.h | 10 +++++----- |
11 | target/arm/translate-neon.c | 63 ------------------------------------- | 14 | hw/pci-host/raven.c | 4 ++-- |
12 | target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++ | 15 | hw/pci-host/versatile.c | 6 +++--- |
13 | 3 files changed, 73 insertions(+), 63 deletions(-) | 16 | hw/pci/pci.c | 26 +++++++++++++------------- |
17 | 4 files changed, 23 insertions(+), 23 deletions(-) | ||
14 | 18 | ||
15 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 19 | diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h |
16 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate.h | 21 | --- a/include/hw/pci/pci.h |
18 | +++ b/target/arm/translate.h | 22 | +++ b/include/hw/pci/pci.h |
19 | @@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc) | 23 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS) |
20 | return opc | s->be_data; | 24 | |
25 | bool pci_bus_is_express(PCIBus *bus); | ||
26 | |||
27 | -void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, | ||
28 | - const char *name, | ||
29 | - MemoryRegion *address_space_mem, | ||
30 | - MemoryRegion *address_space_io, | ||
31 | - uint8_t devfn_min, const char *typename); | ||
32 | +void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, | ||
33 | + const char *name, | ||
34 | + MemoryRegion *address_space_mem, | ||
35 | + MemoryRegion *address_space_io, | ||
36 | + uint8_t devfn_min, const char *typename); | ||
37 | PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, | ||
38 | MemoryRegion *address_space_mem, | ||
39 | MemoryRegion *address_space_io, | ||
40 | diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/pci-host/raven.c | ||
43 | +++ b/hw/pci-host/raven.c | ||
44 | @@ -XXX,XX +XXX,XX @@ static void raven_pcihost_initfn(Object *obj) | ||
45 | memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR, | ||
46 | &s->pci_io_non_contiguous, 1); | ||
47 | memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory); | ||
48 | - pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, | ||
49 | - &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS); | ||
50 | + pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, | ||
51 | + &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS); | ||
52 | |||
53 | /* Bus master address space */ | ||
54 | memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB); | ||
55 | diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/hw/pci-host/versatile.c | ||
58 | +++ b/hw/pci-host/versatile.c | ||
59 | @@ -XXX,XX +XXX,XX @@ static void pci_vpb_realize(DeviceState *dev, Error **errp) | ||
60 | memory_region_init(&s->pci_io_space, OBJECT(s), "pci_io", 4 * GiB); | ||
61 | memory_region_init(&s->pci_mem_space, OBJECT(s), "pci_mem", 4 * GiB); | ||
62 | |||
63 | - pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), dev, "pci", | ||
64 | - &s->pci_mem_space, &s->pci_io_space, | ||
65 | - PCI_DEVFN(11, 0), TYPE_PCI_BUS); | ||
66 | + pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), dev, "pci", | ||
67 | + &s->pci_mem_space, &s->pci_io_space, | ||
68 | + PCI_DEVFN(11, 0), TYPE_PCI_BUS); | ||
69 | h->bus = &s->pci_bus; | ||
70 | |||
71 | object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_VERSATILE_PCI_HOST); | ||
72 | diff --git a/hw/pci/pci.c b/hw/pci/pci.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/hw/pci/pci.c | ||
75 | +++ b/hw/pci/pci.c | ||
76 | @@ -XXX,XX +XXX,XX @@ bool pci_bus_bypass_iommu(PCIBus *bus) | ||
77 | return host_bridge->bypass_iommu; | ||
21 | } | 78 | } |
22 | 79 | ||
23 | +/** | 80 | -static void pci_root_bus_init(PCIBus *bus, DeviceState *parent, |
24 | + * asimd_imm_const: Expand an encoded SIMD constant value | 81 | - MemoryRegion *address_space_mem, |
25 | + * | 82 | - MemoryRegion *address_space_io, |
26 | + * Expand a SIMD constant value. This is essentially the pseudocode | 83 | - uint8_t devfn_min) |
27 | + * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for | 84 | +static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent, |
28 | + * VMVN and VBIC (when cmode < 14 && op == 1). | 85 | + MemoryRegion *address_space_mem, |
29 | + * | 86 | + MemoryRegion *address_space_io, |
30 | + * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; | 87 | + uint8_t devfn_min) |
31 | + * callers must catch this. | ||
32 | + * | ||
33 | + * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but | ||
34 | + * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; | ||
35 | + * we produce an immediate constant value of 0 in these cases. | ||
36 | + */ | ||
37 | +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op); | ||
38 | + | ||
39 | #endif /* TARGET_ARM_TRANSLATE_H */ | ||
40 | diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/arm/translate-neon.c | ||
43 | +++ b/target/arm/translate-neon.c | ||
44 | @@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh) | ||
45 | DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs) | ||
46 | DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu) | ||
47 | |||
48 | -static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) | ||
49 | -{ | ||
50 | - /* | ||
51 | - * Expand the encoded constant. | ||
52 | - * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE. | ||
53 | - * We choose to not special-case this and will behave as if a | ||
54 | - * valid constant encoding of 0 had been given. | ||
55 | - * cmode = 15 op = 1 must UNDEF; we assume decode has handled that. | ||
56 | - */ | ||
57 | - switch (cmode) { | ||
58 | - case 0: case 1: | ||
59 | - /* no-op */ | ||
60 | - break; | ||
61 | - case 2: case 3: | ||
62 | - imm <<= 8; | ||
63 | - break; | ||
64 | - case 4: case 5: | ||
65 | - imm <<= 16; | ||
66 | - break; | ||
67 | - case 6: case 7: | ||
68 | - imm <<= 24; | ||
69 | - break; | ||
70 | - case 8: case 9: | ||
71 | - imm |= imm << 16; | ||
72 | - break; | ||
73 | - case 10: case 11: | ||
74 | - imm = (imm << 8) | (imm << 24); | ||
75 | - break; | ||
76 | - case 12: | ||
77 | - imm = (imm << 8) | 0xff; | ||
78 | - break; | ||
79 | - case 13: | ||
80 | - imm = (imm << 16) | 0xffff; | ||
81 | - break; | ||
82 | - case 14: | ||
83 | - if (op) { | ||
84 | - /* | ||
85 | - * This is the only case where the top and bottom 32 bits | ||
86 | - * of the encoded constant differ. | ||
87 | - */ | ||
88 | - uint64_t imm64 = 0; | ||
89 | - int n; | ||
90 | - | ||
91 | - for (n = 0; n < 8; n++) { | ||
92 | - if (imm & (1 << n)) { | ||
93 | - imm64 |= (0xffULL << (n * 8)); | ||
94 | - } | ||
95 | - } | ||
96 | - return imm64; | ||
97 | - } | ||
98 | - imm |= (imm << 8) | (imm << 16) | (imm << 24); | ||
99 | - break; | ||
100 | - case 15: | ||
101 | - imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | ||
102 | - | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | ||
103 | - break; | ||
104 | - } | ||
105 | - if (op) { | ||
106 | - imm = ~imm; | ||
107 | - } | ||
108 | - return dup_const(MO_32, imm); | ||
109 | -} | ||
110 | - | ||
111 | static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, | ||
112 | GVecGen2iFn *fn) | ||
113 | { | 88 | { |
114 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 89 | assert(PCI_FUNC(devfn_min) == 0); |
115 | index XXXXXXX..XXXXXXX 100644 | 90 | bus->devfn_min = devfn_min; |
116 | --- a/target/arm/translate.c | 91 | @@ -XXX,XX +XXX,XX @@ bool pci_bus_is_express(PCIBus *bus) |
117 | +++ b/target/arm/translate.c | 92 | return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); |
118 | @@ -XXX,XX +XXX,XX @@ void arm_translate_init(void) | ||
119 | a64_translate_init(); | ||
120 | } | 93 | } |
121 | 94 | ||
122 | +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) | 95 | -void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, |
123 | +{ | 96 | - const char *name, |
124 | + /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */ | 97 | - MemoryRegion *address_space_mem, |
125 | + switch (cmode) { | 98 | - MemoryRegion *address_space_io, |
126 | + case 0: case 1: | 99 | - uint8_t devfn_min, const char *typename) |
127 | + /* no-op */ | 100 | +void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, |
128 | + break; | 101 | + const char *name, |
129 | + case 2: case 3: | 102 | + MemoryRegion *address_space_mem, |
130 | + imm <<= 8; | 103 | + MemoryRegion *address_space_io, |
131 | + break; | 104 | + uint8_t devfn_min, const char *typename) |
132 | + case 4: case 5: | ||
133 | + imm <<= 16; | ||
134 | + break; | ||
135 | + case 6: case 7: | ||
136 | + imm <<= 24; | ||
137 | + break; | ||
138 | + case 8: case 9: | ||
139 | + imm |= imm << 16; | ||
140 | + break; | ||
141 | + case 10: case 11: | ||
142 | + imm = (imm << 8) | (imm << 24); | ||
143 | + break; | ||
144 | + case 12: | ||
145 | + imm = (imm << 8) | 0xff; | ||
146 | + break; | ||
147 | + case 13: | ||
148 | + imm = (imm << 16) | 0xffff; | ||
149 | + break; | ||
150 | + case 14: | ||
151 | + if (op) { | ||
152 | + /* | ||
153 | + * This is the only case where the top and bottom 32 bits | ||
154 | + * of the encoded constant differ. | ||
155 | + */ | ||
156 | + uint64_t imm64 = 0; | ||
157 | + int n; | ||
158 | + | ||
159 | + for (n = 0; n < 8; n++) { | ||
160 | + if (imm & (1 << n)) { | ||
161 | + imm64 |= (0xffULL << (n * 8)); | ||
162 | + } | ||
163 | + } | ||
164 | + return imm64; | ||
165 | + } | ||
166 | + imm |= (imm << 8) | (imm << 16) | (imm << 24); | ||
167 | + break; | ||
168 | + case 15: | ||
169 | + imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | ||
170 | + | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | ||
171 | + break; | ||
172 | + } | ||
173 | + if (op) { | ||
174 | + imm = ~imm; | ||
175 | + } | ||
176 | + return dup_const(MO_32, imm); | ||
177 | +} | ||
178 | + | ||
179 | /* Generate a label used for skipping this instruction */ | ||
180 | void arm_gen_condlabel(DisasContext *s) | ||
181 | { | 105 | { |
106 | qbus_create_inplace(bus, bus_size, typename, parent, name); | ||
107 | - pci_root_bus_init(bus, parent, address_space_mem, address_space_io, | ||
108 | - devfn_min); | ||
109 | + pci_root_bus_internal_init(bus, parent, address_space_mem, | ||
110 | + address_space_io, devfn_min); | ||
111 | } | ||
112 | |||
113 | PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, | ||
114 | @@ -XXX,XX +XXX,XX @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, | ||
115 | PCIBus *bus; | ||
116 | |||
117 | bus = PCI_BUS(qbus_create(typename, parent, name)); | ||
118 | - pci_root_bus_init(bus, parent, address_space_mem, address_space_io, | ||
119 | - devfn_min); | ||
120 | + pci_root_bus_internal_init(bus, parent, address_space_mem, | ||
121 | + address_space_io, devfn_min); | ||
122 | return bus; | ||
123 | } | ||
124 | |||
182 | -- | 125 | -- |
183 | 2.20.1 | 126 | 2.20.1 |
184 | 127 | ||
185 | 128 | diff view generated by jsdifflib |
1 | In do_ldst(), the calculation of the offset needs to be based on the | 1 | Rename qbus_create_inplace() to qbus_init(); this is more in line |
---|---|---|---|
2 | size of the memory access, not the size of the elements in the | 2 | with our usual naming convention for functions that in-place |
3 | vector. This meant we were getting it wrong for the widening and | 3 | initialize objects. |
4 | narrowing variants of the various VLDR and VSTR insns. | ||
5 | 4 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
8 | Message-id: 20210628135835.6690-2-peter.maydell@linaro.org | 7 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> |
8 | Message-id: 20210923121153.23754-5-peter.maydell@linaro.org | ||
9 | --- | 9 | --- |
10 | target/arm/translate-mve.c | 17 +++++++++-------- | 10 | include/hw/qdev-core.h | 4 ++-- |
11 | 1 file changed, 9 insertions(+), 8 deletions(-) | 11 | hw/audio/intel-hda.c | 2 +- |
12 | hw/block/fdc.c | 2 +- | ||
13 | hw/block/swim.c | 3 +-- | ||
14 | hw/char/virtio-serial-bus.c | 4 ++-- | ||
15 | hw/core/bus.c | 11 ++++++----- | ||
16 | hw/core/sysbus.c | 10 ++++++---- | ||
17 | hw/gpio/bcm2835_gpio.c | 3 +-- | ||
18 | hw/ide/qdev.c | 2 +- | ||
19 | hw/ipack/ipack.c | 2 +- | ||
20 | hw/misc/mac_via.c | 4 ++-- | ||
21 | hw/misc/macio/cuda.c | 4 ++-- | ||
22 | hw/misc/macio/macio.c | 4 ++-- | ||
23 | hw/misc/macio/pmu.c | 4 ++-- | ||
24 | hw/nubus/nubus-bridge.c | 2 +- | ||
25 | hw/nvme/ctrl.c | 4 ++-- | ||
26 | hw/nvme/subsys.c | 3 +-- | ||
27 | hw/pci/pci.c | 2 +- | ||
28 | hw/pci/pci_bridge.c | 4 ++-- | ||
29 | hw/s390x/event-facility.c | 4 ++-- | ||
30 | hw/s390x/virtio-ccw.c | 3 +-- | ||
31 | hw/scsi/scsi-bus.c | 2 +- | ||
32 | hw/sd/allwinner-sdhost.c | 4 ++-- | ||
33 | hw/sd/bcm2835_sdhost.c | 4 ++-- | ||
34 | hw/sd/pl181.c | 3 +-- | ||
35 | hw/sd/pxa2xx_mmci.c | 4 ++-- | ||
36 | hw/sd/sdhci.c | 3 +-- | ||
37 | hw/sd/ssi-sd.c | 3 +-- | ||
38 | hw/usb/bus.c | 2 +- | ||
39 | hw/usb/dev-smartcard-reader.c | 3 +-- | ||
40 | hw/virtio/virtio-mmio.c | 3 +-- | ||
41 | hw/virtio/virtio-pci.c | 3 +-- | ||
42 | 32 files changed, 54 insertions(+), 61 deletions(-) | ||
12 | 43 | ||
13 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | 44 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h |
14 | index XXXXXXX..XXXXXXX 100644 | 45 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate-mve.c | 46 | --- a/include/hw/qdev-core.h |
16 | +++ b/target/arm/translate-mve.c | 47 | +++ b/include/hw/qdev-core.h |
17 | @@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s) | 48 | @@ -XXX,XX +XXX,XX @@ DeviceState *qdev_find_recursive(BusState *bus, const char *id); |
49 | typedef int (qbus_walkerfn)(BusState *bus, void *opaque); | ||
50 | typedef int (qdev_walkerfn)(DeviceState *dev, void *opaque); | ||
51 | |||
52 | -void qbus_create_inplace(void *bus, size_t size, const char *typename, | ||
53 | - DeviceState *parent, const char *name); | ||
54 | +void qbus_init(void *bus, size_t size, const char *typename, | ||
55 | + DeviceState *parent, const char *name); | ||
56 | BusState *qbus_create(const char *typename, DeviceState *parent, const char *name); | ||
57 | bool qbus_realize(BusState *bus, Error **errp); | ||
58 | void qbus_unrealize(BusState *bus); | ||
59 | diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c | ||
60 | index XXXXXXX..XXXXXXX 100644 | ||
61 | --- a/hw/audio/intel-hda.c | ||
62 | +++ b/hw/audio/intel-hda.c | ||
63 | @@ -XXX,XX +XXX,XX @@ void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size, | ||
64 | hda_codec_response_func response, | ||
65 | hda_codec_xfer_func xfer) | ||
66 | { | ||
67 | - qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL); | ||
68 | + qbus_init(bus, bus_size, TYPE_HDA_BUS, dev, NULL); | ||
69 | bus->response = response; | ||
70 | bus->xfer = xfer; | ||
71 | } | ||
72 | diff --git a/hw/block/fdc.c b/hw/block/fdc.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/hw/block/fdc.c | ||
75 | +++ b/hw/block/fdc.c | ||
76 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo floppy_bus_info = { | ||
77 | |||
78 | static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev) | ||
79 | { | ||
80 | - qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL); | ||
81 | + qbus_init(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL); | ||
82 | bus->fdc = fdc; | ||
83 | } | ||
84 | |||
85 | diff --git a/hw/block/swim.c b/hw/block/swim.c | ||
86 | index XXXXXXX..XXXXXXX 100644 | ||
87 | --- a/hw/block/swim.c | ||
88 | +++ b/hw/block/swim.c | ||
89 | @@ -XXX,XX +XXX,XX @@ static void sysbus_swim_realize(DeviceState *dev, Error **errp) | ||
90 | Swim *sys = SWIM(dev); | ||
91 | SWIMCtrl *swimctrl = &sys->ctrl; | ||
92 | |||
93 | - qbus_create_inplace(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev, | ||
94 | - NULL); | ||
95 | + qbus_init(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev, NULL); | ||
96 | swimctrl->bus.ctrl = swimctrl; | ||
97 | } | ||
98 | |||
99 | diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c | ||
100 | index XXXXXXX..XXXXXXX 100644 | ||
101 | --- a/hw/char/virtio-serial-bus.c | ||
102 | +++ b/hw/char/virtio-serial-bus.c | ||
103 | @@ -XXX,XX +XXX,XX @@ static void virtio_serial_device_realize(DeviceState *dev, Error **errp) | ||
104 | config_size); | ||
105 | |||
106 | /* Spawn a new virtio-serial bus on which the ports will ride as devices */ | ||
107 | - qbus_create_inplace(&vser->bus, sizeof(vser->bus), TYPE_VIRTIO_SERIAL_BUS, | ||
108 | - dev, vdev->bus_name); | ||
109 | + qbus_init(&vser->bus, sizeof(vser->bus), TYPE_VIRTIO_SERIAL_BUS, | ||
110 | + dev, vdev->bus_name); | ||
111 | qbus_set_hotplug_handler(BUS(&vser->bus), OBJECT(vser)); | ||
112 | vser->bus.vser = vser; | ||
113 | QTAILQ_INIT(&vser->ports); | ||
114 | diff --git a/hw/core/bus.c b/hw/core/bus.c | ||
115 | index XXXXXXX..XXXXXXX 100644 | ||
116 | --- a/hw/core/bus.c | ||
117 | +++ b/hw/core/bus.c | ||
118 | @@ -XXX,XX +XXX,XX @@ static void bus_reset_child_foreach(Object *obj, ResettableChildCallback cb, | ||
18 | } | 119 | } |
19 | } | 120 | } |
20 | 121 | ||
21 | -static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) | 122 | -static void qbus_init(BusState *bus, DeviceState *parent, const char *name) |
22 | +static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn, | 123 | +static void qbus_init_internal(BusState *bus, DeviceState *parent, |
23 | + unsigned msize) | 124 | + const char *name) |
24 | { | 125 | { |
25 | TCGv_i32 addr; | 126 | const char *typename = object_get_typename(OBJECT(bus)); |
26 | uint32_t offset; | 127 | BusClass *bc; |
27 | @@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) | 128 | @@ -XXX,XX +XXX,XX @@ static void bus_unparent(Object *obj) |
28 | return true; | 129 | bus->parent = NULL; |
130 | } | ||
131 | |||
132 | -void qbus_create_inplace(void *bus, size_t size, const char *typename, | ||
133 | - DeviceState *parent, const char *name) | ||
134 | +void qbus_init(void *bus, size_t size, const char *typename, | ||
135 | + DeviceState *parent, const char *name) | ||
136 | { | ||
137 | object_initialize(bus, size, typename); | ||
138 | - qbus_init(bus, parent, name); | ||
139 | + qbus_init_internal(bus, parent, name); | ||
140 | } | ||
141 | |||
142 | BusState *qbus_create(const char *typename, DeviceState *parent, const char *name) | ||
143 | @@ -XXX,XX +XXX,XX @@ BusState *qbus_create(const char *typename, DeviceState *parent, const char *nam | ||
144 | BusState *bus; | ||
145 | |||
146 | bus = BUS(object_new(typename)); | ||
147 | - qbus_init(bus, parent, name); | ||
148 | + qbus_init_internal(bus, parent, name); | ||
149 | |||
150 | return bus; | ||
151 | } | ||
152 | diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c | ||
153 | index XXXXXXX..XXXXXXX 100644 | ||
154 | --- a/hw/core/sysbus.c | ||
155 | +++ b/hw/core/sysbus.c | ||
156 | @@ -XXX,XX +XXX,XX @@ static BusState *main_system_bus; | ||
157 | |||
158 | static void main_system_bus_create(void) | ||
159 | { | ||
160 | - /* assign main_system_bus before qbus_create_inplace() | ||
161 | - * in order to make "if (bus != sysbus_get_default())" work */ | ||
162 | + /* | ||
163 | + * assign main_system_bus before qbus_init() | ||
164 | + * in order to make "if (bus != sysbus_get_default())" work | ||
165 | + */ | ||
166 | main_system_bus = g_malloc0(system_bus_info.instance_size); | ||
167 | - qbus_create_inplace(main_system_bus, system_bus_info.instance_size, | ||
168 | - TYPE_SYSTEM_BUS, NULL, "main-system-bus"); | ||
169 | + qbus_init(main_system_bus, system_bus_info.instance_size, | ||
170 | + TYPE_SYSTEM_BUS, NULL, "main-system-bus"); | ||
171 | OBJECT(main_system_bus)->free = g_free; | ||
172 | } | ||
173 | |||
174 | diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c | ||
175 | index XXXXXXX..XXXXXXX 100644 | ||
176 | --- a/hw/gpio/bcm2835_gpio.c | ||
177 | +++ b/hw/gpio/bcm2835_gpio.c | ||
178 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_gpio_init(Object *obj) | ||
179 | DeviceState *dev = DEVICE(obj); | ||
180 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
181 | |||
182 | - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), | ||
183 | - TYPE_SD_BUS, DEVICE(s), "sd-bus"); | ||
184 | + qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(s), "sd-bus"); | ||
185 | |||
186 | memory_region_init_io(&s->iomem, obj, | ||
187 | &bcm2835_gpio_ops, s, "bcm2835_gpio", 0x1000); | ||
188 | diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c | ||
189 | index XXXXXXX..XXXXXXX 100644 | ||
190 | --- a/hw/ide/qdev.c | ||
191 | +++ b/hw/ide/qdev.c | ||
192 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo ide_bus_info = { | ||
193 | void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev, | ||
194 | int bus_id, int max_units) | ||
195 | { | ||
196 | - qbus_create_inplace(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL); | ||
197 | + qbus_init(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL); | ||
198 | idebus->bus_id = bus_id; | ||
199 | idebus->max_units = max_units; | ||
200 | } | ||
201 | diff --git a/hw/ipack/ipack.c b/hw/ipack/ipack.c | ||
202 | index XXXXXXX..XXXXXXX 100644 | ||
203 | --- a/hw/ipack/ipack.c | ||
204 | +++ b/hw/ipack/ipack.c | ||
205 | @@ -XXX,XX +XXX,XX @@ void ipack_bus_init(IPackBus *bus, size_t bus_size, | ||
206 | uint8_t n_slots, | ||
207 | qemu_irq_handler handler) | ||
208 | { | ||
209 | - qbus_create_inplace(bus, bus_size, TYPE_IPACK_BUS, parent, NULL); | ||
210 | + qbus_init(bus, bus_size, TYPE_IPACK_BUS, parent, NULL); | ||
211 | bus->n_slots = n_slots; | ||
212 | bus->set_irq = handler; | ||
213 | } | ||
214 | diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c | ||
215 | index XXXXXXX..XXXXXXX 100644 | ||
216 | --- a/hw/misc/mac_via.c | ||
217 | +++ b/hw/misc/mac_via.c | ||
218 | @@ -XXX,XX +XXX,XX @@ static void mos6522_q800_via1_init(Object *obj) | ||
219 | sysbus_init_mmio(sbd, &v1s->via_mem); | ||
220 | |||
221 | /* ADB */ | ||
222 | - qbus_create_inplace((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus), | ||
223 | - TYPE_ADB_BUS, DEVICE(v1s), "adb.0"); | ||
224 | + qbus_init((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus), | ||
225 | + TYPE_ADB_BUS, DEVICE(v1s), "adb.0"); | ||
226 | |||
227 | qdev_init_gpio_in(DEVICE(obj), via1_irq_request, VIA1_IRQ_NB); | ||
228 | } | ||
229 | diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c | ||
230 | index XXXXXXX..XXXXXXX 100644 | ||
231 | --- a/hw/misc/macio/cuda.c | ||
232 | +++ b/hw/misc/macio/cuda.c | ||
233 | @@ -XXX,XX +XXX,XX @@ static void cuda_init(Object *obj) | ||
234 | memory_region_init_io(&s->mem, obj, &mos6522_cuda_ops, s, "cuda", 0x2000); | ||
235 | sysbus_init_mmio(sbd, &s->mem); | ||
236 | |||
237 | - qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, | ||
238 | - DEVICE(obj), "adb.0"); | ||
239 | + qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, | ||
240 | + DEVICE(obj), "adb.0"); | ||
241 | } | ||
242 | |||
243 | static Property cuda_properties[] = { | ||
244 | diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c | ||
245 | index XXXXXXX..XXXXXXX 100644 | ||
246 | --- a/hw/misc/macio/macio.c | ||
247 | +++ b/hw/misc/macio/macio.c | ||
248 | @@ -XXX,XX +XXX,XX @@ static void macio_instance_init(Object *obj) | ||
249 | |||
250 | memory_region_init(&s->bar, obj, "macio", 0x80000); | ||
251 | |||
252 | - qbus_create_inplace(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS, | ||
253 | - DEVICE(obj), "macio.0"); | ||
254 | + qbus_init(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS, | ||
255 | + DEVICE(obj), "macio.0"); | ||
256 | |||
257 | object_initialize_child(OBJECT(s), "dbdma", &s->dbdma, TYPE_MAC_DBDMA); | ||
258 | |||
259 | diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c | ||
260 | index XXXXXXX..XXXXXXX 100644 | ||
261 | --- a/hw/misc/macio/pmu.c | ||
262 | +++ b/hw/misc/macio/pmu.c | ||
263 | @@ -XXX,XX +XXX,XX @@ static void pmu_realize(DeviceState *dev, Error **errp) | ||
264 | timer_mod(s->one_sec_timer, s->one_sec_target); | ||
265 | |||
266 | if (s->has_adb) { | ||
267 | - qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, | ||
268 | - dev, "adb.0"); | ||
269 | + qbus_init(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS, | ||
270 | + dev, "adb.0"); | ||
271 | adb_register_autopoll_callback(adb_bus, pmu_adb_poll, s); | ||
29 | } | 272 | } |
30 | 273 | } | |
31 | - offset = a->imm << a->size; | 274 | diff --git a/hw/nubus/nubus-bridge.c b/hw/nubus/nubus-bridge.c |
32 | + offset = a->imm << msize; | 275 | index XXXXXXX..XXXXXXX 100644 |
33 | if (!a->a) { | 276 | --- a/hw/nubus/nubus-bridge.c |
34 | offset = -offset; | 277 | +++ b/hw/nubus/nubus-bridge.c |
278 | @@ -XXX,XX +XXX,XX @@ static void nubus_bridge_init(Object *obj) | ||
279 | NubusBridge *s = NUBUS_BRIDGE(obj); | ||
280 | NubusBus *bus = &s->bus; | ||
281 | |||
282 | - qbus_create_inplace(bus, sizeof(s->bus), TYPE_NUBUS_BUS, DEVICE(s), NULL); | ||
283 | + qbus_init(bus, sizeof(s->bus), TYPE_NUBUS_BUS, DEVICE(s), NULL); | ||
284 | |||
285 | qdev_init_gpio_out(DEVICE(s), bus->irqs, NUBUS_IRQS); | ||
286 | } | ||
287 | diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c | ||
288 | index XXXXXXX..XXXXXXX 100644 | ||
289 | --- a/hw/nvme/ctrl.c | ||
290 | +++ b/hw/nvme/ctrl.c | ||
291 | @@ -XXX,XX +XXX,XX @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) | ||
292 | return; | ||
35 | } | 293 | } |
36 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) | 294 | |
37 | { gen_helper_mve_vstrw, gen_helper_mve_vldrw }, | 295 | - qbus_create_inplace(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS, |
38 | { NULL, NULL } | 296 | - &pci_dev->qdev, n->parent_obj.qdev.id); |
39 | }; | 297 | + qbus_init(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS, |
40 | - return do_ldst(s, a, ldstfns[a->size][a->l]); | 298 | + &pci_dev->qdev, n->parent_obj.qdev.id); |
41 | + return do_ldst(s, a, ldstfns[a->size][a->l], a->size); | 299 | |
42 | } | 300 | nvme_init_state(n); |
43 | 301 | if (nvme_init_pci(n, pci_dev, errp)) { | |
44 | -#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \ | 302 | diff --git a/hw/nvme/subsys.c b/hw/nvme/subsys.c |
45 | +#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \ | 303 | index XXXXXXX..XXXXXXX 100644 |
46 | static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \ | 304 | --- a/hw/nvme/subsys.c |
47 | { \ | 305 | +++ b/hw/nvme/subsys.c |
48 | static MVEGenLdStFn * const ldstfns[2][2] = { \ | 306 | @@ -XXX,XX +XXX,XX @@ static void nvme_subsys_realize(DeviceState *dev, Error **errp) |
49 | { gen_helper_mve_##ST, gen_helper_mve_##SLD }, \ | 307 | { |
50 | { NULL, gen_helper_mve_##ULD }, \ | 308 | NvmeSubsystem *subsys = NVME_SUBSYS(dev); |
51 | }; \ | 309 | |
52 | - return do_ldst(s, a, ldstfns[a->u][a->l]); \ | 310 | - qbus_create_inplace(&subsys->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev, |
53 | + return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \ | 311 | - dev->id); |
312 | + qbus_init(&subsys->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev, dev->id); | ||
313 | |||
314 | nvme_subsys_setup(subsys); | ||
315 | } | ||
316 | diff --git a/hw/pci/pci.c b/hw/pci/pci.c | ||
317 | index XXXXXXX..XXXXXXX 100644 | ||
318 | --- a/hw/pci/pci.c | ||
319 | +++ b/hw/pci/pci.c | ||
320 | @@ -XXX,XX +XXX,XX @@ void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, | ||
321 | MemoryRegion *address_space_io, | ||
322 | uint8_t devfn_min, const char *typename) | ||
323 | { | ||
324 | - qbus_create_inplace(bus, bus_size, typename, parent, name); | ||
325 | + qbus_init(bus, bus_size, typename, parent, name); | ||
326 | pci_root_bus_internal_init(bus, parent, address_space_mem, | ||
327 | address_space_io, devfn_min); | ||
328 | } | ||
329 | diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c | ||
330 | index XXXXXXX..XXXXXXX 100644 | ||
331 | --- a/hw/pci/pci_bridge.c | ||
332 | +++ b/hw/pci/pci_bridge.c | ||
333 | @@ -XXX,XX +XXX,XX @@ void pci_bridge_initfn(PCIDevice *dev, const char *typename) | ||
334 | br->bus_name = dev->qdev.id; | ||
54 | } | 335 | } |
55 | 336 | ||
56 | -DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h) | 337 | - qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev), |
57 | -DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w) | 338 | - br->bus_name); |
58 | -DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w) | 339 | + qbus_init(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev), |
59 | +DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8) | 340 | + br->bus_name); |
60 | +DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8) | 341 | sec_bus->parent_dev = dev; |
61 | +DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16) | 342 | sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn; |
62 | 343 | sec_bus->address_space_mem = &br->address_space_mem; | |
63 | static bool trans_VDUP(DisasContext *s, arg_VDUP *a) | 344 | diff --git a/hw/s390x/event-facility.c b/hw/s390x/event-facility.c |
64 | { | 345 | index XXXXXXX..XXXXXXX 100644 |
346 | --- a/hw/s390x/event-facility.c | ||
347 | +++ b/hw/s390x/event-facility.c | ||
348 | @@ -XXX,XX +XXX,XX @@ static void init_event_facility(Object *obj) | ||
349 | sclp_event_set_allow_all_mask_sizes); | ||
350 | |||
351 | /* Spawn a new bus for SCLP events */ | ||
352 | - qbus_create_inplace(&event_facility->sbus, sizeof(event_facility->sbus), | ||
353 | - TYPE_SCLP_EVENTS_BUS, sdev, NULL); | ||
354 | + qbus_init(&event_facility->sbus, sizeof(event_facility->sbus), | ||
355 | + TYPE_SCLP_EVENTS_BUS, sdev, NULL); | ||
356 | |||
357 | object_initialize_child(obj, TYPE_SCLP_QUIESCE, | ||
358 | &event_facility->quiesce, | ||
359 | diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c | ||
360 | index XXXXXXX..XXXXXXX 100644 | ||
361 | --- a/hw/s390x/virtio-ccw.c | ||
362 | +++ b/hw/s390x/virtio-ccw.c | ||
363 | @@ -XXX,XX +XXX,XX @@ static void virtio_ccw_bus_new(VirtioBusState *bus, size_t bus_size, | ||
364 | DeviceState *qdev = DEVICE(dev); | ||
365 | char virtio_bus_name[] = "virtio-bus"; | ||
366 | |||
367 | - qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_CCW_BUS, | ||
368 | - qdev, virtio_bus_name); | ||
369 | + qbus_init(bus, bus_size, TYPE_VIRTIO_CCW_BUS, qdev, virtio_bus_name); | ||
370 | } | ||
371 | |||
372 | static void virtio_ccw_bus_class_init(ObjectClass *klass, void *data) | ||
373 | diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c | ||
374 | index XXXXXXX..XXXXXXX 100644 | ||
375 | --- a/hw/scsi/scsi-bus.c | ||
376 | +++ b/hw/scsi/scsi-bus.c | ||
377 | @@ -XXX,XX +XXX,XX @@ void scsi_device_unit_attention_reported(SCSIDevice *s) | ||
378 | void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host, | ||
379 | const SCSIBusInfo *info, const char *bus_name) | ||
380 | { | ||
381 | - qbus_create_inplace(bus, bus_size, TYPE_SCSI_BUS, host, bus_name); | ||
382 | + qbus_init(bus, bus_size, TYPE_SCSI_BUS, host, bus_name); | ||
383 | bus->busnr = next_scsi_bus++; | ||
384 | bus->info = info; | ||
385 | qbus_set_bus_hotplug_handler(BUS(bus)); | ||
386 | diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c | ||
387 | index XXXXXXX..XXXXXXX 100644 | ||
388 | --- a/hw/sd/allwinner-sdhost.c | ||
389 | +++ b/hw/sd/allwinner-sdhost.c | ||
390 | @@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_init(Object *obj) | ||
391 | { | ||
392 | AwSdHostState *s = AW_SDHOST(obj); | ||
393 | |||
394 | - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), | ||
395 | - TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus"); | ||
396 | + qbus_init(&s->sdbus, sizeof(s->sdbus), | ||
397 | + TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus"); | ||
398 | |||
399 | memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s, | ||
400 | TYPE_AW_SDHOST, 4 * KiB); | ||
401 | diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c | ||
402 | index XXXXXXX..XXXXXXX 100644 | ||
403 | --- a/hw/sd/bcm2835_sdhost.c | ||
404 | +++ b/hw/sd/bcm2835_sdhost.c | ||
405 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_init(Object *obj) | ||
406 | { | ||
407 | BCM2835SDHostState *s = BCM2835_SDHOST(obj); | ||
408 | |||
409 | - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), | ||
410 | - TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus"); | ||
411 | + qbus_init(&s->sdbus, sizeof(s->sdbus), | ||
412 | + TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus"); | ||
413 | |||
414 | memory_region_init_io(&s->iomem, obj, &bcm2835_sdhost_ops, s, | ||
415 | TYPE_BCM2835_SDHOST, 0x1000); | ||
416 | diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c | ||
417 | index XXXXXXX..XXXXXXX 100644 | ||
418 | --- a/hw/sd/pl181.c | ||
419 | +++ b/hw/sd/pl181.c | ||
420 | @@ -XXX,XX +XXX,XX @@ static void pl181_init(Object *obj) | ||
421 | qdev_init_gpio_out_named(dev, &s->card_readonly, "card-read-only", 1); | ||
422 | qdev_init_gpio_out_named(dev, &s->card_inserted, "card-inserted", 1); | ||
423 | |||
424 | - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), | ||
425 | - TYPE_PL181_BUS, dev, "sd-bus"); | ||
426 | + qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_PL181_BUS, dev, "sd-bus"); | ||
427 | } | ||
428 | |||
429 | static void pl181_class_init(ObjectClass *klass, void *data) | ||
430 | diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c | ||
431 | index XXXXXXX..XXXXXXX 100644 | ||
432 | --- a/hw/sd/pxa2xx_mmci.c | ||
433 | +++ b/hw/sd/pxa2xx_mmci.c | ||
434 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_mmci_instance_init(Object *obj) | ||
435 | qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1); | ||
436 | qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1); | ||
437 | |||
438 | - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), | ||
439 | - TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus"); | ||
440 | + qbus_init(&s->sdbus, sizeof(s->sdbus), | ||
441 | + TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus"); | ||
442 | } | ||
443 | |||
444 | static void pxa2xx_mmci_class_init(ObjectClass *klass, void *data) | ||
445 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | ||
446 | index XXXXXXX..XXXXXXX 100644 | ||
447 | --- a/hw/sd/sdhci.c | ||
448 | +++ b/hw/sd/sdhci.c | ||
449 | @@ -XXX,XX +XXX,XX @@ static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) | ||
450 | |||
451 | void sdhci_initfn(SDHCIState *s) | ||
452 | { | ||
453 | - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), | ||
454 | - TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); | ||
455 | + qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); | ||
456 | |||
457 | s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); | ||
458 | s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); | ||
459 | diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c | ||
460 | index XXXXXXX..XXXXXXX 100644 | ||
461 | --- a/hw/sd/ssi-sd.c | ||
462 | +++ b/hw/sd/ssi-sd.c | ||
463 | @@ -XXX,XX +XXX,XX @@ static void ssi_sd_realize(SSIPeripheral *d, Error **errp) | ||
464 | DeviceState *carddev; | ||
465 | DriveInfo *dinfo; | ||
466 | |||
467 | - qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, | ||
468 | - DEVICE(d), "sd-bus"); | ||
469 | + qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(d), "sd-bus"); | ||
470 | |||
471 | /* Create and plug in the sd card */ | ||
472 | /* FIXME use a qdev drive property instead of drive_get_next() */ | ||
473 | diff --git a/hw/usb/bus.c b/hw/usb/bus.c | ||
474 | index XXXXXXX..XXXXXXX 100644 | ||
475 | --- a/hw/usb/bus.c | ||
476 | +++ b/hw/usb/bus.c | ||
477 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_usb_device = { | ||
478 | void usb_bus_new(USBBus *bus, size_t bus_size, | ||
479 | USBBusOps *ops, DeviceState *host) | ||
480 | { | ||
481 | - qbus_create_inplace(bus, bus_size, TYPE_USB_BUS, host, NULL); | ||
482 | + qbus_init(bus, bus_size, TYPE_USB_BUS, host, NULL); | ||
483 | qbus_set_bus_hotplug_handler(BUS(bus)); | ||
484 | bus->ops = ops; | ||
485 | bus->busnr = next_usb_bus++; | ||
486 | diff --git a/hw/usb/dev-smartcard-reader.c b/hw/usb/dev-smartcard-reader.c | ||
487 | index XXXXXXX..XXXXXXX 100644 | ||
488 | --- a/hw/usb/dev-smartcard-reader.c | ||
489 | +++ b/hw/usb/dev-smartcard-reader.c | ||
490 | @@ -XXX,XX +XXX,XX @@ static void ccid_realize(USBDevice *dev, Error **errp) | ||
491 | |||
492 | usb_desc_create_serial(dev); | ||
493 | usb_desc_init(dev); | ||
494 | - qbus_create_inplace(&s->bus, sizeof(s->bus), TYPE_CCID_BUS, DEVICE(dev), | ||
495 | - NULL); | ||
496 | + qbus_init(&s->bus, sizeof(s->bus), TYPE_CCID_BUS, DEVICE(dev), NULL); | ||
497 | qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(dev)); | ||
498 | s->intr = usb_ep_get(dev, USB_TOKEN_IN, CCID_INT_IN_EP); | ||
499 | s->bulk = usb_ep_get(dev, USB_TOKEN_IN, CCID_BULK_IN_EP); | ||
500 | diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c | ||
501 | index XXXXXXX..XXXXXXX 100644 | ||
502 | --- a/hw/virtio/virtio-mmio.c | ||
503 | +++ b/hw/virtio/virtio-mmio.c | ||
504 | @@ -XXX,XX +XXX,XX @@ static void virtio_mmio_realizefn(DeviceState *d, Error **errp) | ||
505 | VirtIOMMIOProxy *proxy = VIRTIO_MMIO(d); | ||
506 | SysBusDevice *sbd = SYS_BUS_DEVICE(d); | ||
507 | |||
508 | - qbus_create_inplace(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS, | ||
509 | - d, NULL); | ||
510 | + qbus_init(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS, d, NULL); | ||
511 | sysbus_init_irq(sbd, &proxy->irq); | ||
512 | |||
513 | if (!kvm_eventfds_enabled()) { | ||
514 | diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c | ||
515 | index XXXXXXX..XXXXXXX 100644 | ||
516 | --- a/hw/virtio/virtio-pci.c | ||
517 | +++ b/hw/virtio/virtio-pci.c | ||
518 | @@ -XXX,XX +XXX,XX @@ static void virtio_pci_bus_new(VirtioBusState *bus, size_t bus_size, | ||
519 | DeviceState *qdev = DEVICE(dev); | ||
520 | char virtio_bus_name[] = "virtio-bus"; | ||
521 | |||
522 | - qbus_create_inplace(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev, | ||
523 | - virtio_bus_name); | ||
524 | + qbus_init(bus, bus_size, TYPE_VIRTIO_PCI_BUS, qdev, virtio_bus_name); | ||
525 | } | ||
526 | |||
527 | static void virtio_pci_bus_class_init(ObjectClass *klass, void *data) | ||
65 | -- | 528 | -- |
66 | 2.20.1 | 529 | 2.20.1 |
67 | 530 | ||
68 | 531 | diff view generated by jsdifflib |
1 | Implement the MVE shifts by register, which perform | 1 | Rename the "allocate and return" qbus creation function to |
---|---|---|---|
2 | shifts on a single general-purpose register. | 2 | qbus_new(), to bring it into line with our _init vs _new convention. |
3 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
6 | Message-id: 20210628135835.6690-19-peter.maydell@linaro.org | 6 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> |
7 | Reviewed-by: Corey Minyard <cminyard@mvista.com> | ||
8 | Message-id: 20210923121153.23754-6-peter.maydell@linaro.org | ||
7 | --- | 9 | --- |
8 | target/arm/helper-mve.h | 2 ++ | 10 | include/hw/qdev-core.h | 2 +- |
9 | target/arm/translate.h | 1 + | 11 | hw/core/bus.c | 2 +- |
10 | target/arm/t32.decode | 18 ++++++++++++++---- | 12 | hw/hyperv/vmbus.c | 2 +- |
11 | target/arm/mve_helper.c | 10 ++++++++++ | 13 | hw/i2c/core.c | 2 +- |
12 | target/arm/translate.c | 30 ++++++++++++++++++++++++++++++ | 14 | hw/isa/isa-bus.c | 2 +- |
13 | 5 files changed, 57 insertions(+), 4 deletions(-) | 15 | hw/misc/auxbus.c | 2 +- |
14 | 16 | hw/pci/pci.c | 2 +- | |
15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | 17 | hw/ppc/spapr_vio.c | 2 +- |
16 | index XXXXXXX..XXXXXXX 100644 | 18 | hw/s390x/ap-bridge.c | 2 +- |
17 | --- a/target/arm/helper-mve.h | 19 | hw/s390x/css-bridge.c | 2 +- |
18 | +++ b/target/arm/helper-mve.h | 20 | hw/s390x/s390-pci-bus.c | 2 +- |
19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) | 21 | hw/ssi/ssi.c | 2 +- |
20 | 22 | hw/xen/xen-bus.c | 2 +- | |
21 | DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | 23 | hw/xen/xen-legacy-backend.c | 2 +- |
22 | DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | 24 | 14 files changed, 14 insertions(+), 14 deletions(-) |
23 | +DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | 25 | |
24 | +DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32) | 26 | diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h |
25 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 27 | index XXXXXXX..XXXXXXX 100644 |
26 | index XXXXXXX..XXXXXXX 100644 | 28 | --- a/include/hw/qdev-core.h |
27 | --- a/target/arm/translate.h | 29 | +++ b/include/hw/qdev-core.h |
28 | +++ b/target/arm/translate.h | 30 | @@ -XXX,XX +XXX,XX @@ typedef int (qdev_walkerfn)(DeviceState *dev, void *opaque); |
29 | @@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | 31 | |
30 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | 32 | void qbus_init(void *bus, size_t size, const char *typename, |
31 | typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); | 33 | DeviceState *parent, const char *name); |
32 | typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); | 34 | -BusState *qbus_create(const char *typename, DeviceState *parent, const char *name); |
33 | +typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); | 35 | +BusState *qbus_new(const char *typename, DeviceState *parent, const char *name); |
34 | 36 | bool qbus_realize(BusState *bus, Error **errp); | |
35 | /** | 37 | void qbus_unrealize(BusState *bus); |
36 | * arm_tbflags_from_tb: | 38 | |
37 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | 39 | diff --git a/hw/core/bus.c b/hw/core/bus.c |
38 | index XXXXXXX..XXXXXXX 100644 | 40 | index XXXXXXX..XXXXXXX 100644 |
39 | --- a/target/arm/t32.decode | 41 | --- a/hw/core/bus.c |
40 | +++ b/target/arm/t32.decode | 42 | +++ b/hw/core/bus.c |
41 | @@ -XXX,XX +XXX,XX @@ | 43 | @@ -XXX,XX +XXX,XX @@ void qbus_init(void *bus, size_t size, const char *typename, |
42 | &mve_shl_ri rdalo rdahi shim | 44 | qbus_init_internal(bus, parent, name); |
43 | &mve_shl_rr rdalo rdahi rm | 45 | } |
44 | &mve_sh_ri rda shim | 46 | |
45 | +&mve_sh_rr rda rm | 47 | -BusState *qbus_create(const char *typename, DeviceState *parent, const char *name) |
46 | 48 | +BusState *qbus_new(const char *typename, DeviceState *parent, const char *name) | |
47 | # rdahi: bits [3:1] from insn, bit 0 is 1 | 49 | { |
48 | # rdalo: bits [3:1] from insn, bit 0 is 0 | 50 | BusState *bus; |
49 | @@ -XXX,XX +XXX,XX @@ | 51 | |
50 | &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 | 52 | diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c |
51 | @mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \ | 53 | index XXXXXXX..XXXXXXX 100644 |
52 | &mve_sh_ri shim=%imm5_12_6 | 54 | --- a/hw/hyperv/vmbus.c |
53 | +@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr | 55 | +++ b/hw/hyperv/vmbus.c |
54 | 56 | @@ -XXX,XX +XXX,XX @@ static void vmbus_bridge_realize(DeviceState *dev, Error **errp) | |
55 | { | 57 | return; |
56 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | ||
57 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
58 | SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
59 | } | 58 | } |
60 | 59 | ||
61 | - LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | 60 | - bridge->bus = VMBUS(qbus_create(TYPE_VMBUS, dev, "vmbus")); |
62 | - ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | 61 | + bridge->bus = VMBUS(qbus_new(TYPE_VMBUS, dev, "vmbus")); |
63 | - UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr | ||
64 | - SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr | ||
65 | + { | ||
66 | + UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr | ||
67 | + LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | ||
68 | + UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr | ||
69 | + } | ||
70 | + | ||
71 | + { | ||
72 | + SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr | ||
73 | + ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | ||
74 | + SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr | ||
75 | + } | ||
76 | + | ||
77 | UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr | ||
78 | SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr | ||
79 | ] | ||
80 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
81 | index XXXXXXX..XXXXXXX 100644 | ||
82 | --- a/target/arm/mve_helper.c | ||
83 | +++ b/target/arm/mve_helper.c | ||
84 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
85 | { | ||
86 | return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); | ||
87 | } | 62 | } |
88 | + | 63 | |
89 | +uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) | 64 | static char *vmbus_bridge_ofw_unit_address(const SysBusDevice *dev) |
90 | +{ | 65 | diff --git a/hw/i2c/core.c b/hw/i2c/core.c |
91 | + return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); | 66 | index XXXXXXX..XXXXXXX 100644 |
92 | +} | 67 | --- a/hw/i2c/core.c |
93 | + | 68 | +++ b/hw/i2c/core.c |
94 | +uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) | 69 | @@ -XXX,XX +XXX,XX @@ I2CBus *i2c_init_bus(DeviceState *parent, const char *name) |
95 | +{ | 70 | { |
96 | + return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); | 71 | I2CBus *bus; |
97 | +} | 72 | |
98 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 73 | - bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name)); |
99 | index XXXXXXX..XXXXXXX 100644 | 74 | + bus = I2C_BUS(qbus_new(TYPE_I2C_BUS, parent, name)); |
100 | --- a/target/arm/translate.c | 75 | QLIST_INIT(&bus->current_devs); |
101 | +++ b/target/arm/translate.c | 76 | vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_i2c_bus, bus); |
102 | @@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) | 77 | return bus; |
103 | return do_mve_sh_ri(s, a, gen_mve_uqshl); | 78 | diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c |
79 | index XXXXXXX..XXXXXXX 100644 | ||
80 | --- a/hw/isa/isa-bus.c | ||
81 | +++ b/hw/isa/isa-bus.c | ||
82 | @@ -XXX,XX +XXX,XX @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion* address_space, | ||
83 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
84 | } | ||
85 | |||
86 | - isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL)); | ||
87 | + isabus = ISA_BUS(qbus_new(TYPE_ISA_BUS, dev, NULL)); | ||
88 | isabus->address_space = address_space; | ||
89 | isabus->address_space_io = address_space_io; | ||
90 | return isabus; | ||
91 | diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c | ||
92 | index XXXXXXX..XXXXXXX 100644 | ||
93 | --- a/hw/misc/auxbus.c | ||
94 | +++ b/hw/misc/auxbus.c | ||
95 | @@ -XXX,XX +XXX,XX @@ AUXBus *aux_bus_init(DeviceState *parent, const char *name) | ||
96 | AUXBus *bus; | ||
97 | Object *auxtoi2c; | ||
98 | |||
99 | - bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name)); | ||
100 | + bus = AUX_BUS(qbus_new(TYPE_AUX_BUS, parent, name)); | ||
101 | auxtoi2c = object_new_with_props(TYPE_AUXTOI2C, OBJECT(bus), "i2c", | ||
102 | &error_abort, NULL); | ||
103 | |||
104 | diff --git a/hw/pci/pci.c b/hw/pci/pci.c | ||
105 | index XXXXXXX..XXXXXXX 100644 | ||
106 | --- a/hw/pci/pci.c | ||
107 | +++ b/hw/pci/pci.c | ||
108 | @@ -XXX,XX +XXX,XX @@ PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, | ||
109 | { | ||
110 | PCIBus *bus; | ||
111 | |||
112 | - bus = PCI_BUS(qbus_create(typename, parent, name)); | ||
113 | + bus = PCI_BUS(qbus_new(typename, parent, name)); | ||
114 | pci_root_bus_internal_init(bus, parent, address_space_mem, | ||
115 | address_space_io, devfn_min); | ||
116 | return bus; | ||
117 | diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c | ||
118 | index XXXXXXX..XXXXXXX 100644 | ||
119 | --- a/hw/ppc/spapr_vio.c | ||
120 | +++ b/hw/ppc/spapr_vio.c | ||
121 | @@ -XXX,XX +XXX,XX @@ SpaprVioBus *spapr_vio_bus_init(void) | ||
122 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
123 | |||
124 | /* Create bus on bridge device */ | ||
125 | - qbus = qbus_create(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio"); | ||
126 | + qbus = qbus_new(TYPE_SPAPR_VIO_BUS, dev, "spapr-vio"); | ||
127 | bus = SPAPR_VIO_BUS(qbus); | ||
128 | bus->next_reg = SPAPR_VIO_REG_BASE; | ||
129 | |||
130 | diff --git a/hw/s390x/ap-bridge.c b/hw/s390x/ap-bridge.c | ||
131 | index XXXXXXX..XXXXXXX 100644 | ||
132 | --- a/hw/s390x/ap-bridge.c | ||
133 | +++ b/hw/s390x/ap-bridge.c | ||
134 | @@ -XXX,XX +XXX,XX @@ void s390_init_ap(void) | ||
135 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
136 | |||
137 | /* Create bus on bridge device */ | ||
138 | - bus = qbus_create(TYPE_AP_BUS, dev, TYPE_AP_BUS); | ||
139 | + bus = qbus_new(TYPE_AP_BUS, dev, TYPE_AP_BUS); | ||
140 | |||
141 | /* Enable hotplugging */ | ||
142 | qbus_set_hotplug_handler(bus, OBJECT(dev)); | ||
143 | diff --git a/hw/s390x/css-bridge.c b/hw/s390x/css-bridge.c | ||
144 | index XXXXXXX..XXXXXXX 100644 | ||
145 | --- a/hw/s390x/css-bridge.c | ||
146 | +++ b/hw/s390x/css-bridge.c | ||
147 | @@ -XXX,XX +XXX,XX @@ VirtualCssBus *virtual_css_bus_init(void) | ||
148 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
149 | |||
150 | /* Create bus on bridge device */ | ||
151 | - bus = qbus_create(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css"); | ||
152 | + bus = qbus_new(TYPE_VIRTUAL_CSS_BUS, dev, "virtual-css"); | ||
153 | cbus = VIRTUAL_CSS_BUS(bus); | ||
154 | |||
155 | /* Enable hotplugging */ | ||
156 | diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c | ||
157 | index XXXXXXX..XXXXXXX 100644 | ||
158 | --- a/hw/s390x/s390-pci-bus.c | ||
159 | +++ b/hw/s390x/s390-pci-bus.c | ||
160 | @@ -XXX,XX +XXX,XX @@ static void s390_pcihost_realize(DeviceState *dev, Error **errp) | ||
161 | qbus_set_hotplug_handler(bus, OBJECT(dev)); | ||
162 | phb->bus = b; | ||
163 | |||
164 | - s->bus = S390_PCI_BUS(qbus_create(TYPE_S390_PCI_BUS, dev, NULL)); | ||
165 | + s->bus = S390_PCI_BUS(qbus_new(TYPE_S390_PCI_BUS, dev, NULL)); | ||
166 | qbus_set_hotplug_handler(BUS(s->bus), OBJECT(dev)); | ||
167 | |||
168 | s->iommu_table = g_hash_table_new_full(g_int64_hash, g_int64_equal, | ||
169 | diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c | ||
170 | index XXXXXXX..XXXXXXX 100644 | ||
171 | --- a/hw/ssi/ssi.c | ||
172 | +++ b/hw/ssi/ssi.c | ||
173 | @@ -XXX,XX +XXX,XX @@ DeviceState *ssi_create_peripheral(SSIBus *bus, const char *name) | ||
174 | SSIBus *ssi_create_bus(DeviceState *parent, const char *name) | ||
175 | { | ||
176 | BusState *bus; | ||
177 | - bus = qbus_create(TYPE_SSI_BUS, parent, name); | ||
178 | + bus = qbus_new(TYPE_SSI_BUS, parent, name); | ||
179 | return SSI_BUS(bus); | ||
104 | } | 180 | } |
105 | 181 | ||
106 | +static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn) | 182 | diff --git a/hw/xen/xen-bus.c b/hw/xen/xen-bus.c |
107 | +{ | 183 | index XXXXXXX..XXXXXXX 100644 |
108 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | 184 | --- a/hw/xen/xen-bus.c |
109 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | 185 | +++ b/hw/xen/xen-bus.c |
110 | + return false; | 186 | @@ -XXX,XX +XXX,XX @@ type_init(xen_register_types) |
111 | + } | 187 | void xen_bus_init(void) |
112 | + if (!dc_isar_feature(aa32_mve, s) || | 188 | { |
113 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | 189 | DeviceState *dev = qdev_new(TYPE_XEN_BRIDGE); |
114 | + a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 || | 190 | - BusState *bus = qbus_create(TYPE_XEN_BUS, dev, NULL); |
115 | + a->rm == a->rda) { | 191 | + BusState *bus = qbus_new(TYPE_XEN_BUS, dev, NULL); |
116 | + /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */ | 192 | |
117 | + unallocated_encoding(s); | 193 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
118 | + return true; | 194 | qbus_set_bus_hotplug_handler(bus); |
119 | + } | 195 | diff --git a/hw/xen/xen-legacy-backend.c b/hw/xen/xen-legacy-backend.c |
120 | + | 196 | index XXXXXXX..XXXXXXX 100644 |
121 | + /* The helper takes care of the sign-extension of the low 8 bits of Rm */ | 197 | --- a/hw/xen/xen-legacy-backend.c |
122 | + fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]); | 198 | +++ b/hw/xen/xen-legacy-backend.c |
123 | + return true; | 199 | @@ -XXX,XX +XXX,XX @@ int xen_be_init(void) |
124 | +} | 200 | |
125 | + | 201 | xen_sysdev = qdev_new(TYPE_XENSYSDEV); |
126 | +static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a) | 202 | sysbus_realize_and_unref(SYS_BUS_DEVICE(xen_sysdev), &error_fatal); |
127 | +{ | 203 | - xen_sysbus = qbus_create(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus"); |
128 | + return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr); | 204 | + xen_sysbus = qbus_new(TYPE_XENSYSBUS, xen_sysdev, "xen-sysbus"); |
129 | +} | 205 | qbus_set_bus_hotplug_handler(xen_sysbus); |
130 | + | 206 | |
131 | +static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a) | 207 | return 0; |
132 | +{ | ||
133 | + return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl); | ||
134 | +} | ||
135 | + | ||
136 | /* | ||
137 | * Multiply and multiply accumulate | ||
138 | */ | ||
139 | -- | 208 | -- |
140 | 2.20.1 | 209 | 2.20.1 |
141 | 210 | ||
142 | 211 | diff view generated by jsdifflib |
1 | Implement the MVE VADDLV insn; this is similar to VADDV, except | 1 | The function ide_bus_new() does an in-place initialization. Rename |
---|---|---|---|
2 | that it accumulates 32-bit elements into a 64-bit accumulator | 2 | it to ide_bus_init() to follow our _init vs _new convention. |
3 | stored in a pair of general-purpose registers. | ||
4 | 3 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
7 | Message-id: 20210628135835.6690-15-peter.maydell@linaro.org | 6 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> |
7 | Reviewed-by: Corey Minyard <cminyard@mvista.com> | ||
8 | Reviewed-by: John Snow <jsnow@redhat.com> | ||
9 | Acked-by: John Snow <jsnow@redhat.com> (Feel free to merge.) | ||
10 | Message-id: 20210923121153.23754-7-peter.maydell@linaro.org | ||
8 | --- | 11 | --- |
9 | target/arm/helper-mve.h | 3 ++ | 12 | include/hw/ide/internal.h | 4 ++-- |
10 | target/arm/mve.decode | 6 +++- | 13 | hw/ide/ahci.c | 2 +- |
11 | target/arm/mve_helper.c | 19 ++++++++++++ | 14 | hw/ide/cmd646.c | 2 +- |
12 | target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++ | 15 | hw/ide/isa.c | 2 +- |
13 | 4 files changed, 90 insertions(+), 1 deletion(-) | 16 | hw/ide/macio.c | 2 +- |
17 | hw/ide/microdrive.c | 2 +- | ||
18 | hw/ide/mmio.c | 2 +- | ||
19 | hw/ide/piix.c | 2 +- | ||
20 | hw/ide/qdev.c | 2 +- | ||
21 | hw/ide/sii3112.c | 2 +- | ||
22 | hw/ide/via.c | 2 +- | ||
23 | 11 files changed, 12 insertions(+), 12 deletions(-) | ||
14 | 24 | ||
15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | 25 | diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h |
16 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper-mve.h | 27 | --- a/include/hw/ide/internal.h |
18 | +++ b/target/arm/helper-mve.h | 28 | +++ b/include/hw/ide/internal.h |
19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32) | 29 | @@ -XXX,XX +XXX,XX @@ void ide_atapi_cmd(IDEState *s); |
20 | DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) | 30 | void ide_atapi_cmd_reply_end(IDEState *s); |
21 | DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) | 31 | |
22 | 32 | /* hw/ide/qdev.c */ | |
23 | +DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64) | 33 | -void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev, |
24 | +DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64) | 34 | - int bus_id, int max_units); |
25 | + | 35 | +void ide_bus_init(IDEBus *idebus, size_t idebus_size, DeviceState *dev, |
26 | DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) | 36 | + int bus_id, int max_units); |
27 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) | 37 | IDEDevice *ide_create_drive(IDEBus *bus, int unit, DriveInfo *drive); |
28 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | 38 | |
29 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | 39 | int ide_handle_rw_error(IDEState *s, int error, int op); |
40 | diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | 41 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/target/arm/mve.decode | 42 | --- a/hw/ide/ahci.c |
32 | +++ b/target/arm/mve.decode | 43 | +++ b/hw/ide/ahci.c |
33 | @@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar | 44 | @@ -XXX,XX +XXX,XX @@ void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports) |
34 | VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar | 45 | for (i = 0; i < s->ports; i++) { |
35 | 46 | AHCIDevice *ad = &s->dev[i]; | |
36 | # Vector add across vector | 47 | |
37 | -VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo | 48 | - ide_bus_new(&ad->port, sizeof(ad->port), qdev, i, 1); |
38 | +{ | 49 | + ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1); |
39 | + VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo | 50 | ide_init2(&ad->port, irqs[i]); |
40 | + VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \ | 51 | |
41 | + rdahi=%rdahi rdalo=%rdalo | 52 | ad->hba = s; |
42 | +} | 53 | diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c |
43 | |||
44 | # Predicate operations | ||
45 | %mask_22_13 22:1 13:3 | ||
46 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | 54 | index XXXXXXX..XXXXXXX 100644 |
48 | --- a/target/arm/mve_helper.c | 55 | --- a/hw/ide/cmd646.c |
49 | +++ b/target/arm/mve_helper.c | 56 | +++ b/hw/ide/cmd646.c |
50 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t) | 57 | @@ -XXX,XX +XXX,XX @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp) |
51 | DO_VADDV(vaddvuh, 2, uint16_t) | 58 | |
52 | DO_VADDV(vaddvuw, 4, uint32_t) | 59 | qdev_init_gpio_in(ds, cmd646_set_irq, 2); |
53 | 60 | for (i = 0; i < 2; i++) { | |
54 | +#define DO_VADDLV(OP, TYPE, LTYPE) \ | 61 | - ide_bus_new(&d->bus[i], sizeof(d->bus[i]), ds, i, 2); |
55 | + uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ | 62 | + ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2); |
56 | + uint64_t ra) \ | 63 | ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i)); |
57 | + { \ | 64 | |
58 | + uint16_t mask = mve_element_mask(env); \ | 65 | bmdma_init(&d->bus[i], &d->bmdma[i], d); |
59 | + unsigned e; \ | 66 | diff --git a/hw/ide/isa.c b/hw/ide/isa.c |
60 | + TYPE *m = vm; \ | ||
61 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ | ||
62 | + if (mask & 1) { \ | ||
63 | + ra += (LTYPE)m[H4(e)]; \ | ||
64 | + } \ | ||
65 | + } \ | ||
66 | + mve_advance_vpt(env); \ | ||
67 | + return ra; \ | ||
68 | + } \ | ||
69 | + | ||
70 | +DO_VADDLV(vaddlv_s, int32_t, int64_t) | ||
71 | +DO_VADDLV(vaddlv_u, uint32_t, uint64_t) | ||
72 | + | ||
73 | /* Shifts by immediate */ | ||
74 | #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ | ||
75 | void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
76 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
77 | index XXXXXXX..XXXXXXX 100644 | 67 | index XXXXXXX..XXXXXXX 100644 |
78 | --- a/target/arm/translate-mve.c | 68 | --- a/hw/ide/isa.c |
79 | +++ b/target/arm/translate-mve.c | 69 | +++ b/hw/ide/isa.c |
80 | @@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a) | 70 | @@ -XXX,XX +XXX,XX @@ static void isa_ide_realizefn(DeviceState *dev, Error **errp) |
81 | return true; | 71 | ISADevice *isadev = ISA_DEVICE(dev); |
72 | ISAIDEState *s = ISA_IDE(dev); | ||
73 | |||
74 | - ide_bus_new(&s->bus, sizeof(s->bus), dev, 0, 2); | ||
75 | + ide_bus_init(&s->bus, sizeof(s->bus), dev, 0, 2); | ||
76 | ide_init_ioport(&s->bus, isadev, s->iobase, s->iobase2); | ||
77 | isa_init_irq(isadev, &s->irq, s->isairq); | ||
78 | ide_init2(&s->bus, s->irq); | ||
79 | diff --git a/hw/ide/macio.c b/hw/ide/macio.c | ||
80 | index XXXXXXX..XXXXXXX 100644 | ||
81 | --- a/hw/ide/macio.c | ||
82 | +++ b/hw/ide/macio.c | ||
83 | @@ -XXX,XX +XXX,XX @@ static void macio_ide_initfn(Object *obj) | ||
84 | SysBusDevice *d = SYS_BUS_DEVICE(obj); | ||
85 | MACIOIDEState *s = MACIO_IDE(obj); | ||
86 | |||
87 | - ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); | ||
88 | + ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); | ||
89 | memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000); | ||
90 | sysbus_init_mmio(d, &s->mem); | ||
91 | sysbus_init_irq(d, &s->real_ide_irq); | ||
92 | diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c | ||
93 | index XXXXXXX..XXXXXXX 100644 | ||
94 | --- a/hw/ide/microdrive.c | ||
95 | +++ b/hw/ide/microdrive.c | ||
96 | @@ -XXX,XX +XXX,XX @@ static void microdrive_init(Object *obj) | ||
97 | { | ||
98 | MicroDriveState *md = MICRODRIVE(obj); | ||
99 | |||
100 | - ide_bus_new(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1); | ||
101 | + ide_bus_init(&md->bus, sizeof(md->bus), DEVICE(obj), 0, 1); | ||
82 | } | 102 | } |
83 | 103 | ||
84 | +static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a) | 104 | static void microdrive_class_init(ObjectClass *oc, void *data) |
85 | +{ | 105 | diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c |
86 | + /* | 106 | index XXXXXXX..XXXXXXX 100644 |
87 | + * Vector Add Long Across Vector: accumulate the 32-bit | 107 | --- a/hw/ide/mmio.c |
88 | + * elements of the vector into a 64-bit result stored in | 108 | +++ b/hw/ide/mmio.c |
89 | + * a pair of general-purpose registers. | 109 | @@ -XXX,XX +XXX,XX @@ static void mmio_ide_initfn(Object *obj) |
90 | + * No need to check Qm's bank: it is only 3 bits in decode. | 110 | SysBusDevice *d = SYS_BUS_DEVICE(obj); |
91 | + */ | 111 | MMIOState *s = MMIO_IDE(obj); |
92 | + TCGv_ptr qm; | 112 | |
93 | + TCGv_i64 rda; | 113 | - ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); |
94 | + TCGv_i32 rdalo, rdahi; | 114 | + ide_bus_init(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2); |
95 | + | 115 | sysbus_init_irq(d, &s->irq); |
96 | + if (!dc_isar_feature(aa32_mve, s)) { | 116 | } |
97 | + return false; | 117 | |
98 | + } | 118 | diff --git a/hw/ide/piix.c b/hw/ide/piix.c |
99 | + /* | 119 | index XXXXXXX..XXXXXXX 100644 |
100 | + * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related | 120 | --- a/hw/ide/piix.c |
101 | + * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. | 121 | +++ b/hw/ide/piix.c |
102 | + */ | 122 | @@ -XXX,XX +XXX,XX @@ static int pci_piix_init_ports(PCIIDEState *d) |
103 | + if (a->rdahi == 13 || a->rdahi == 15) { | 123 | int i, ret; |
104 | + return false; | 124 | |
105 | + } | 125 | for (i = 0; i < 2; i++) { |
106 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | 126 | - ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); |
107 | + return true; | 127 | + ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); |
108 | + } | 128 | ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, |
109 | + | 129 | port_info[i].iobase2); |
110 | + /* | 130 | if (ret) { |
111 | + * This insn is subject to beat-wise execution. Partial execution | 131 | diff --git a/hw/ide/qdev.c b/hw/ide/qdev.c |
112 | + * of an A=0 (no-accumulate) insn which does not execute the first | 132 | index XXXXXXX..XXXXXXX 100644 |
113 | + * beat must start with the current value of RdaHi:RdaLo, not zero. | 133 | --- a/hw/ide/qdev.c |
114 | + */ | 134 | +++ b/hw/ide/qdev.c |
115 | + if (a->a || mve_skip_first_beat(s)) { | 135 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo ide_bus_info = { |
116 | + /* Accumulate input from RdaHi:RdaLo */ | 136 | .class_init = ide_bus_class_init, |
117 | + rda = tcg_temp_new_i64(); | 137 | }; |
118 | + rdalo = load_reg(s, a->rdalo); | 138 | |
119 | + rdahi = load_reg(s, a->rdahi); | 139 | -void ide_bus_new(IDEBus *idebus, size_t idebus_size, DeviceState *dev, |
120 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); | 140 | +void ide_bus_init(IDEBus *idebus, size_t idebus_size, DeviceState *dev, |
121 | + tcg_temp_free_i32(rdalo); | 141 | int bus_id, int max_units) |
122 | + tcg_temp_free_i32(rdahi); | ||
123 | + } else { | ||
124 | + /* Accumulate starting at zero */ | ||
125 | + rda = tcg_const_i64(0); | ||
126 | + } | ||
127 | + | ||
128 | + qm = mve_qreg_ptr(a->qm); | ||
129 | + if (a->u) { | ||
130 | + gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda); | ||
131 | + } else { | ||
132 | + gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda); | ||
133 | + } | ||
134 | + tcg_temp_free_ptr(qm); | ||
135 | + | ||
136 | + rdalo = tcg_temp_new_i32(); | ||
137 | + rdahi = tcg_temp_new_i32(); | ||
138 | + tcg_gen_extrl_i64_i32(rdalo, rda); | ||
139 | + tcg_gen_extrh_i64_i32(rdahi, rda); | ||
140 | + store_reg(s, a->rdalo, rdalo); | ||
141 | + store_reg(s, a->rdahi, rdahi); | ||
142 | + tcg_temp_free_i64(rda); | ||
143 | + mve_update_eci(s); | ||
144 | + return true; | ||
145 | +} | ||
146 | + | ||
147 | static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) | ||
148 | { | 142 | { |
149 | TCGv_ptr qd; | 143 | qbus_init(idebus, idebus_size, TYPE_IDE_BUS, dev, NULL); |
144 | diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c | ||
145 | index XXXXXXX..XXXXXXX 100644 | ||
146 | --- a/hw/ide/sii3112.c | ||
147 | +++ b/hw/ide/sii3112.c | ||
148 | @@ -XXX,XX +XXX,XX @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp) | ||
149 | |||
150 | qdev_init_gpio_in(ds, sii3112_set_irq, 2); | ||
151 | for (i = 0; i < 2; i++) { | ||
152 | - ide_bus_new(&s->bus[i], sizeof(s->bus[i]), ds, i, 1); | ||
153 | + ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1); | ||
154 | ide_init2(&s->bus[i], qdev_get_gpio_in(ds, i)); | ||
155 | |||
156 | bmdma_init(&s->bus[i], &s->bmdma[i], s); | ||
157 | diff --git a/hw/ide/via.c b/hw/ide/via.c | ||
158 | index XXXXXXX..XXXXXXX 100644 | ||
159 | --- a/hw/ide/via.c | ||
160 | +++ b/hw/ide/via.c | ||
161 | @@ -XXX,XX +XXX,XX @@ static void via_ide_realize(PCIDevice *dev, Error **errp) | ||
162 | |||
163 | qdev_init_gpio_in(ds, via_ide_set_irq, 2); | ||
164 | for (i = 0; i < 2; i++) { | ||
165 | - ide_bus_new(&d->bus[i], sizeof(d->bus[i]), ds, i, 2); | ||
166 | + ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, 2); | ||
167 | ide_init2(&d->bus[i], qdev_get_gpio_in(ds, i)); | ||
168 | |||
169 | bmdma_init(&d->bus[i], &d->bmdma[i], d); | ||
150 | -- | 170 | -- |
151 | 2.20.1 | 171 | 2.20.1 |
152 | 172 | ||
153 | 173 | diff view generated by jsdifflib |
1 | Use dup_const() instead of bitfield_replicate() in | 1 | From: Xuzhou Cheng <xuzhou.cheng@windriver.com> |
---|---|---|---|
2 | disas_simd_mod_imm(). | ||
3 | 2 | ||
4 | (We can't replace the other use of bitfield_replicate() in this file, | 3 | The Linux spi-imx driver does not work on QEMU. The reason is that the |
5 | in logic_imm_decode_wmask(), because that location needs to handle 2 | 4 | state of m25p80 loops in STATE_READING_DATA state after receiving |
6 | and 4 bit elements, which dup_const() cannot.) | 5 | RDSR command, the new command is ignored. Before sending a new command, |
6 | CS line should be pulled high to make the state of m25p80 back to IDLE. | ||
7 | 7 | ||
8 | Currently the SPI flash CS line is connected to the SPI controller, but | ||
9 | on the real board, it's connected to GPIO3_19. This matches the ecspi1 | ||
10 | device node in the board dts. | ||
11 | |||
12 | ecspi1 node in imx6qdl-sabrelite.dtsi: | ||
13 | &ecspi1 { | ||
14 | cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; | ||
15 | pinctrl-names = "default"; | ||
16 | pinctrl-0 = <&pinctrl_ecspi1>; | ||
17 | status = "okay"; | ||
18 | |||
19 | flash: m25p80@0 { | ||
20 | compatible = "sst,sst25vf016b", "jedec,spi-nor"; | ||
21 | spi-max-frequency = <20000000>; | ||
22 | reg = <0>; | ||
23 | }; | ||
24 | }; | ||
25 | |||
26 | Should connect the SSI_GPIO_CS to GPIO3_19 when adding a spi-nor to | ||
27 | spi1 on sabrelite machine. | ||
28 | |||
29 | Verified this patch on Linux v5.14. | ||
30 | |||
31 | Logs: | ||
32 | # echo "01234567899876543210" > test | ||
33 | # mtd_debug erase /dev/mtd0 0x0 0x1000 | ||
34 | Erased 4096 bytes from address 0x00000000 in flash | ||
35 | # mtd_debug write /dev/mtdblock0 0x0 20 test | ||
36 | Copied 20 bytes from test to address 0x00000000 in flash | ||
37 | # mtd_debug read /dev/mtdblock0 0x0 20 test_out | ||
38 | Copied 20 bytes from address 0x00000000 in flash to test_out | ||
39 | # cat test_out | ||
40 | 01234567899876543210# | ||
41 | |||
42 | Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> | ||
43 | Reported-by: Guenter Roeck <linux@roeck-us.net> | ||
44 | Reviewed-by: Bin Meng <bin.meng@windriver.com> | ||
45 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
46 | Message-id: 20210927142825.491-1-xchengl.cn@gmail.com | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 47 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20210628135835.6690-6-peter.maydell@linaro.org | ||
11 | --- | 48 | --- |
12 | target/arm/translate-a64.c | 2 +- | 49 | hw/arm/sabrelite.c | 2 +- |
13 | 1 file changed, 1 insertion(+), 1 deletion(-) | 50 | 1 file changed, 1 insertion(+), 1 deletion(-) |
14 | 51 | ||
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 52 | diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c |
16 | index XXXXXXX..XXXXXXX 100644 | 53 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate-a64.c | 54 | --- a/hw/arm/sabrelite.c |
18 | +++ b/target/arm/translate-a64.c | 55 | +++ b/hw/arm/sabrelite.c |
19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | 56 | @@ -XXX,XX +XXX,XX @@ static void sabrelite_init(MachineState *machine) |
20 | /* FMOV (vector, immediate) - half-precision */ | 57 | qdev_realize_and_unref(flash_dev, BUS(spi_bus), &error_fatal); |
21 | imm = vfp_expand_imm(MO_16, abcdefgh); | 58 | |
22 | /* now duplicate across the lanes */ | 59 | cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); |
23 | - imm = bitfield_replicate(imm, 16); | 60 | - sysbus_connect_irq(SYS_BUS_DEVICE(spi_dev), 1, cs_line); |
24 | + imm = dup_const(MO_16, imm); | 61 | + qdev_connect_gpio_out(DEVICE(&s->gpio[2]), 19, cs_line); |
25 | } else { | 62 | } |
26 | imm = asimd_imm_const(abcdefgh, cmode, is_neg); | 63 | } |
27 | } | 64 | } |
28 | -- | 65 | -- |
29 | 2.20.1 | 66 | 2.20.1 |
30 | 67 | ||
31 | 68 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Implement the MVE logical-immediate insns (VMOV, VMVN, | ||
2 | VORR and VBIC). These have essentially the same encoding | ||
3 | as their Neon equivalents, and we implement the decode | ||
4 | in the same way. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20210628135835.6690-7-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/helper-mve.h | 4 +++ | ||
11 | target/arm/mve.decode | 17 +++++++++++++ | ||
12 | target/arm/mve_helper.c | 24 ++++++++++++++++++ | ||
13 | target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++ | ||
14 | 4 files changed, 95 insertions(+) | ||
15 | |||
16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/helper-mve.h | ||
19 | +++ b/target/arm/helper-mve.h | ||
20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
21 | DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
22 | DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
23 | DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
24 | + | ||
25 | +DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
26 | +DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
27 | +DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
28 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/mve.decode | ||
31 | +++ b/target/arm/mve.decode | ||
32 | @@ -XXX,XX +XXX,XX @@ | ||
33 | # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit | ||
34 | %size_28 28:1 !function=plus_1 | ||
35 | |||
36 | +# 1imm format immediate | ||
37 | +%imm_28_16_0 28:1 16:3 0:4 | ||
38 | + | ||
39 | &vldr_vstr rn qd imm p a w size l u | ||
40 | &1op qd qm size | ||
41 | &2op qd qm qn size | ||
42 | &2scalar qd qn rm size | ||
43 | +&1imm qd imm cmode op | ||
44 | |||
45 | @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 | ||
46 | # Note that both Rn and Qd are 3 bits only (no D bit) | ||
47 | @@ -XXX,XX +XXX,XX @@ | ||
48 | @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0 | ||
49 | @2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \ | ||
50 | size=%size_28 | ||
51 | +@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0 | ||
52 | |||
53 | # The _rev suffix indicates that Vn and Vm are reversed. This is | ||
54 | # the case for shifts. In the Arm ARM these insns are documented | ||
55 | @@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd | ||
56 | # Predicate operations | ||
57 | %mask_22_13 22:1 13:3 | ||
58 | VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 | ||
59 | + | ||
60 | +# Logical immediate operations (1 reg and modified-immediate) | ||
61 | + | ||
62 | +# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but | ||
63 | +# not in a way we can conveniently represent in decodetree without | ||
64 | +# a lot of repetition: | ||
65 | +# VORR: op=0, (cmode & 1) && cmode < 12 | ||
66 | +# VBIC: op=1, (cmode & 1) && cmode < 12 | ||
67 | +# VMOV: everything else | ||
68 | +# So we have a single decode line and check the cmode/op in the | ||
69 | +# trans function. | ||
70 | +Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm | ||
71 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
72 | index XXXXXXX..XXXXXXX 100644 | ||
73 | --- a/target/arm/mve_helper.c | ||
74 | +++ b/target/arm/mve_helper.c | ||
75 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG) | ||
76 | DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) | ||
77 | DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) | ||
78 | |||
79 | +/* | ||
80 | + * 1 operand immediates: Vda is destination and possibly also one source. | ||
81 | + * All these insns work at 64-bit widths. | ||
82 | + */ | ||
83 | +#define DO_1OP_IMM(OP, FN) \ | ||
84 | + void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ | ||
85 | + { \ | ||
86 | + uint64_t *da = vda; \ | ||
87 | + uint16_t mask = mve_element_mask(env); \ | ||
88 | + unsigned e; \ | ||
89 | + for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ | ||
90 | + mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ | ||
91 | + } \ | ||
92 | + mve_advance_vpt(env); \ | ||
93 | + } | ||
94 | + | ||
95 | +#define DO_MOVI(N, I) (I) | ||
96 | +#define DO_ANDI(N, I) ((N) & (I)) | ||
97 | +#define DO_ORRI(N, I) ((N) | (I)) | ||
98 | + | ||
99 | +DO_1OP_IMM(vmovi, DO_MOVI) | ||
100 | +DO_1OP_IMM(vandi, DO_ANDI) | ||
101 | +DO_1OP_IMM(vorri, DO_ORRI) | ||
102 | + | ||
103 | #define DO_2OP(OP, ESIZE, TYPE, FN) \ | ||
104 | void HELPER(glue(mve_, OP))(CPUARMState *env, \ | ||
105 | void *vd, void *vn, void *vm) \ | ||
106 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
107 | index XXXXXXX..XXXXXXX 100644 | ||
108 | --- a/target/arm/translate-mve.c | ||
109 | +++ b/target/arm/translate-mve.c | ||
110 | @@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
111 | typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
112 | typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
113 | typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
114 | +typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
115 | |||
116 | /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ | ||
117 | static inline long mve_qreg_offset(unsigned reg) | ||
118 | @@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a) | ||
119 | mve_update_eci(s); | ||
120 | return true; | ||
121 | } | ||
122 | + | ||
123 | +static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) | ||
124 | +{ | ||
125 | + TCGv_ptr qd; | ||
126 | + uint64_t imm; | ||
127 | + | ||
128 | + if (!dc_isar_feature(aa32_mve, s) || | ||
129 | + !mve_check_qreg_bank(s, a->qd) || | ||
130 | + !fn) { | ||
131 | + return false; | ||
132 | + } | ||
133 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
134 | + return true; | ||
135 | + } | ||
136 | + | ||
137 | + imm = asimd_imm_const(a->imm, a->cmode, a->op); | ||
138 | + | ||
139 | + qd = mve_qreg_ptr(a->qd); | ||
140 | + fn(cpu_env, qd, tcg_constant_i64(imm)); | ||
141 | + tcg_temp_free_ptr(qd); | ||
142 | + mve_update_eci(s); | ||
143 | + return true; | ||
144 | +} | ||
145 | + | ||
146 | +static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) | ||
147 | +{ | ||
148 | + /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ | ||
149 | + MVEGenOneOpImmFn *fn; | ||
150 | + | ||
151 | + if ((a->cmode & 1) && a->cmode < 12) { | ||
152 | + if (a->op) { | ||
153 | + /* | ||
154 | + * For op=1, the immediate will be inverted by asimd_imm_const(), | ||
155 | + * so the VBIC becomes a logical AND operation. | ||
156 | + */ | ||
157 | + fn = gen_helper_mve_vandi; | ||
158 | + } else { | ||
159 | + fn = gen_helper_mve_vorri; | ||
160 | + } | ||
161 | + } else { | ||
162 | + /* There is one unallocated cmode/op combination in this space */ | ||
163 | + if (a->cmode == 15 && a->op == 1) { | ||
164 | + return false; | ||
165 | + } | ||
166 | + /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */ | ||
167 | + fn = gen_helper_mve_vmovi; | ||
168 | + } | ||
169 | + return do_1imm(s, a, fn); | ||
170 | +} | ||
171 | -- | ||
172 | 2.20.1 | ||
173 | |||
174 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL | ||
2 | and VQSHLU. | ||
3 | 1 | ||
4 | The size-and-immediate encoding here is the same as Neon, and we | ||
5 | handle it the same way neon-dp.decode does. | ||
6 | |||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20210628135835.6690-8-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/helper-mve.h | 16 +++++++++++ | ||
12 | target/arm/mve.decode | 23 +++++++++++++++ | ||
13 | target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++ | ||
14 | target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++ | ||
15 | 4 files changed, 147 insertions(+) | ||
16 | |||
17 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/helper-mve.h | ||
20 | +++ b/target/arm/helper-mve.h | ||
21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
22 | DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
23 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
24 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
25 | + | ||
26 | +DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
28 | +DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
29 | + | ||
30 | +DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
31 | +DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
32 | +DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
33 | + | ||
34 | +DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
35 | +DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
36 | +DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
37 | + | ||
38 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
39 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
40 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
41 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/mve.decode | ||
44 | +++ b/target/arm/mve.decode | ||
45 | @@ -XXX,XX +XXX,XX @@ | ||
46 | &2op qd qm qn size | ||
47 | &2scalar qd qn rm size | ||
48 | &1imm qd imm cmode op | ||
49 | +&2shift qd qm shift size | ||
50 | |||
51 | @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 | ||
52 | # Note that both Rn and Qd are 3 bits only (no D bit) | ||
53 | @@ -XXX,XX +XXX,XX @@ | ||
54 | @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn | ||
55 | @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn | ||
56 | |||
57 | +@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0 | ||
58 | +@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 | ||
59 | +@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 | ||
60 | + | ||
61 | # Vector loads and stores | ||
62 | |||
63 | # Widening loads and narrowing stores: | ||
64 | @@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 | ||
65 | # So we have a single decode line and check the cmode/op in the | ||
66 | # trans function. | ||
67 | Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm | ||
68 | + | ||
69 | +# Shifts by immediate | ||
70 | + | ||
71 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b | ||
72 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h | ||
73 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w | ||
74 | + | ||
75 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b | ||
76 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h | ||
77 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
78 | + | ||
79 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b | ||
80 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h | ||
81 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
82 | + | ||
83 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b | ||
84 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h | ||
85 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w | ||
86 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/target/arm/mve_helper.c | ||
89 | +++ b/target/arm/mve_helper.c | ||
90 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) | ||
91 | WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) | ||
92 | #define DO_UQRSHL_OP(N, M, satp) \ | ||
93 | WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) | ||
94 | +#define DO_SUQSHL_OP(N, M, satp) \ | ||
95 | + WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) | ||
96 | |||
97 | DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) | ||
98 | DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) | ||
99 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t) | ||
100 | DO_VADDV(vaddvub, 1, uint8_t) | ||
101 | DO_VADDV(vaddvuh, 2, uint16_t) | ||
102 | DO_VADDV(vaddvuw, 4, uint32_t) | ||
103 | + | ||
104 | +/* Shifts by immediate */ | ||
105 | +#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ | ||
106 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
107 | + void *vm, uint32_t shift) \ | ||
108 | + { \ | ||
109 | + TYPE *d = vd, *m = vm; \ | ||
110 | + uint16_t mask = mve_element_mask(env); \ | ||
111 | + unsigned e; \ | ||
112 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
113 | + mergemask(&d[H##ESIZE(e)], \ | ||
114 | + FN(m[H##ESIZE(e)], shift), mask); \ | ||
115 | + } \ | ||
116 | + mve_advance_vpt(env); \ | ||
117 | + } | ||
118 | + | ||
119 | +#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ | ||
120 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
121 | + void *vm, uint32_t shift) \ | ||
122 | + { \ | ||
123 | + TYPE *d = vd, *m = vm; \ | ||
124 | + uint16_t mask = mve_element_mask(env); \ | ||
125 | + unsigned e; \ | ||
126 | + bool qc = false; \ | ||
127 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
128 | + bool sat = false; \ | ||
129 | + mergemask(&d[H##ESIZE(e)], \ | ||
130 | + FN(m[H##ESIZE(e)], shift, &sat), mask); \ | ||
131 | + qc |= sat & mask & 1; \ | ||
132 | + } \ | ||
133 | + if (qc) { \ | ||
134 | + env->vfp.qc[0] = qc; \ | ||
135 | + } \ | ||
136 | + mve_advance_vpt(env); \ | ||
137 | + } | ||
138 | + | ||
139 | +/* provide unsigned 2-op shift helpers for all sizes */ | ||
140 | +#define DO_2SHIFT_U(OP, FN) \ | ||
141 | + DO_2SHIFT(OP##b, 1, uint8_t, FN) \ | ||
142 | + DO_2SHIFT(OP##h, 2, uint16_t, FN) \ | ||
143 | + DO_2SHIFT(OP##w, 4, uint32_t, FN) | ||
144 | + | ||
145 | +#define DO_2SHIFT_SAT_U(OP, FN) \ | ||
146 | + DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ | ||
147 | + DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ | ||
148 | + DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) | ||
149 | +#define DO_2SHIFT_SAT_S(OP, FN) \ | ||
150 | + DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ | ||
151 | + DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ | ||
152 | + DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) | ||
153 | + | ||
154 | +DO_2SHIFT_U(vshli_u, DO_VSHLU) | ||
155 | +DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) | ||
156 | +DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) | ||
157 | +DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
158 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
159 | index XXXXXXX..XXXXXXX 100644 | ||
160 | --- a/target/arm/translate-mve.c | ||
161 | +++ b/target/arm/translate-mve.c | ||
162 | @@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
163 | typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
164 | typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
165 | typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
166 | +typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
167 | typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
168 | typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
169 | typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
170 | @@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) | ||
171 | } | ||
172 | return do_1imm(s, a, fn); | ||
173 | } | ||
174 | + | ||
175 | +static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, | ||
176 | + bool negateshift) | ||
177 | +{ | ||
178 | + TCGv_ptr qd, qm; | ||
179 | + int shift = a->shift; | ||
180 | + | ||
181 | + if (!dc_isar_feature(aa32_mve, s) || | ||
182 | + !mve_check_qreg_bank(s, a->qd | a->qm) || | ||
183 | + !fn) { | ||
184 | + return false; | ||
185 | + } | ||
186 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
187 | + return true; | ||
188 | + } | ||
189 | + | ||
190 | + /* | ||
191 | + * When we handle a right shift insn using a left-shift helper | ||
192 | + * which permits a negative shift count to indicate a right-shift, | ||
193 | + * we must negate the shift count. | ||
194 | + */ | ||
195 | + if (negateshift) { | ||
196 | + shift = -shift; | ||
197 | + } | ||
198 | + | ||
199 | + qd = mve_qreg_ptr(a->qd); | ||
200 | + qm = mve_qreg_ptr(a->qm); | ||
201 | + fn(cpu_env, qd, qm, tcg_constant_i32(shift)); | ||
202 | + tcg_temp_free_ptr(qd); | ||
203 | + tcg_temp_free_ptr(qm); | ||
204 | + mve_update_eci(s); | ||
205 | + return true; | ||
206 | +} | ||
207 | + | ||
208 | +#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \ | ||
209 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | ||
210 | + { \ | ||
211 | + static MVEGenTwoOpShiftFn * const fns[] = { \ | ||
212 | + gen_helper_mve_##FN##b, \ | ||
213 | + gen_helper_mve_##FN##h, \ | ||
214 | + gen_helper_mve_##FN##w, \ | ||
215 | + NULL, \ | ||
216 | + }; \ | ||
217 | + return do_2shift(s, a, fns[a->size], NEGATESHIFT); \ | ||
218 | + } | ||
219 | + | ||
220 | +DO_2SHIFT(VSHLI, vshli_u, false) | ||
221 | +DO_2SHIFT(VQSHLI_S, vqshli_s, false) | ||
222 | +DO_2SHIFT(VQSHLI_U, vqshli_u, false) | ||
223 | +DO_2SHIFT(VQSHLUI, vqshlui_s, false) | ||
224 | -- | ||
225 | 2.20.1 | ||
226 | |||
227 | diff view generated by jsdifflib |