[PULL 00/24] target-arm queue
[PULL 00/37] target-arm queue
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The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
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More accumulated patches from during the freeze...
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Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
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The following changes since commit c83fcfaf8a54d0d034bd0edf7bbb3b0d16669be9:
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5
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-08-26' into staging (2021-08-26 13:42:34 +0100)
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6
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210826
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10
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for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
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for you to fetch changes up to d2e6f370138a7f32bc28b20dcd55374b7a638f39:
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target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
13
hw/arm/xlnx-zynqmp: Add unimplemented APU mmio (2021-08-26 17:02:01 +0100)
12
14
13
----------------------------------------------------------------
15
----------------------------------------------------------------
14
target-arm queue:
16
target-arm queue:
15
* more MVE instructions
17
* hw/dma/xlnx-zdma, xlnx_csu_dma: Require 'dma' link property to be set
16
* hw/gpio/gpio_pwr: use shutdown function for reboot
18
* hw/arm/Kconfig: no need to enable ACPI_MEMORY_HOTPLUG/ACPI_NVDIMM explicitly
17
* target/arm: Check NaN mode before silencing NaN
19
* target/arm/cpu: Introduce sve_vq_supported bitmap
18
* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
20
* docs/specs: Convert ACPI spec docs to rST
19
* hw/arm: Add basic power management to raspi.
21
* arch_init: Clean up and refactoring
20
* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
22
* hw/core/loader: In gunzip(), check index is in range before use, not after
23
* softmmu/physmem.c: Remove unneeded NULL check in qemu_ram_alloc_from_fd()
24
* softmmu/physmem.c: Check return value from realpath()
25
* Zero-initialize sockaddr_in structs
26
* raspi: Use error_fatal for SoC realize errors, not error_abort
27
* target/arm: Avoid assertion trying to use KVM and multiple ASes
28
* target/arm: Implement HSTR.TTEE
29
* target/arm: Implement HSTR.TJDBX
30
* target/arm: Do hflags rebuild in cpsr_write()
31
* hw/arm/xlnx-versal, xlnx-zynqmp: Add unimplemented APU mmio
21
32
22
----------------------------------------------------------------
33
----------------------------------------------------------------
23
Joe Komlodi (1):
34
Andrew Jones (4):
24
target/arm: Check NaN mode before silencing NaN
35
target/arm/cpu: Introduce sve_vq_supported bitmap
36
target/arm/kvm64: Ensure sve vls map is completely clear
37
target/arm/cpu64: Replace kvm_supported with sve_vq_supported
38
target/arm/cpu64: Validate sve vector lengths are supported
25
39
26
Maxim Uvarov (1):
40
Ani Sinha (1):
27
hw/gpio/gpio_pwr: use shutdown function for reboot
41
hw/arm/Kconfig: no need to enable ACPI_MEMORY_HOTPLUG/ACPI_NVDIMM explicitly
28
42
29
Nolan Leake (1):
43
Peter Maydell (26):
30
hw/arm: Add basic power management to raspi.
44
docs/specs/acpu_cpu_hotplug: Convert to rST
45
docs/specs/acpi_mem_hotplug: Convert to rST
46
docs/specs/acpi_pci_hotplug: Convert to rST
47
docs/specs/acpi_nvdimm: Convert to rST
48
MAINTAINERS: Add ACPI specs documents to ACPI and NVDIMM sections
49
softmmu: Use accel_find("xen") instead of xen_available()
50
monitor: Use accel_find("kvm") instead of kvm_available()
51
softmmu/arch_init.c: Trim down include list
52
meson.build: Define QEMU_ARCH in config-target.h
53
arch_init.h: Add QEMU_ARCH_HEXAGON
54
arch_init.h: Move QEMU_ARCH_VIRTIO_* to qdev-monitor.c
55
arch_init.h: Don't include arch_init.h unnecessarily
56
stubs: Remove unused arch_type.c stub
57
hw/core/loader: In gunzip(), check index is in range before use, not after
58
softmmu/physmem.c: Remove unneeded NULL check in qemu_ram_alloc_from_fd()
59
softmmu/physmem.c: Check return value from realpath()
60
net: Zero sockaddr_in in parse_host_port()
61
gdbstub: Zero-initialize sockaddr structs
62
tests/qtest/ipmi-bt-test: Zero-initialize sockaddr struct
63
tests/tcg/multiarch/linux-test: Zero-initialize sockaddr structs
64
raspi: Use error_fatal for SoC realize errors, not error_abort
65
target/arm: Avoid assertion trying to use KVM and multiple ASes
66
hw/arm/virt: Delete EL3 error checksnow provided in CPU realize
67
target/arm: Implement HSTR.TTEE
68
target/arm: Implement HSTR.TJDBX
69
target/arm: Do hflags rebuild in cpsr_write()
31
70
32
Patrick Venture (2):
71
Philippe Mathieu-Daudé (4):
33
docs/system/arm: Add quanta-q7l1-bmc reference
72
hw/arm/xlnx-zynqmp: Realize qspi controller *after* qspi_dma
34
docs/system/arm: Add quanta-gbs-bmc reference
73
hw/dma/xlnx_csu_dma: Run trivial checks early in realize()
74
hw/dma/xlnx_csu_dma: Always expect 'dma' link property to be set
75
hw/dma/xlnx-zdma Always expect 'dma' link property to be set
35
76
36
Peter Maydell (18):
77
Tong Ho (2):
37
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
78
hw/arm/xlnx-versal: Add unimplemented APU mmio
38
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
79
hw/arm/xlnx-zynqmp: Add unimplemented APU mmio
39
target/arm: Make asimd_imm_const() public
40
target/arm: Use asimd_imm_const for A64 decode
41
target/arm: Use dup_const() instead of bitfield_replicate()
42
target/arm: Implement MVE logical immediate insns
43
target/arm: Implement MVE vector shift left by immediate insns
44
target/arm: Implement MVE vector shift right by immediate insns
45
target/arm: Implement MVE VSHLL
46
target/arm: Implement MVE VSRI, VSLI
47
target/arm: Implement MVE VSHRN, VRSHRN
48
target/arm: Implement MVE saturating narrowing shifts
49
target/arm: Implement MVE VSHLC
50
target/arm: Implement MVE VADDLV
51
target/arm: Implement MVE long shifts by immediate
52
target/arm: Implement MVE long shifts by register
53
target/arm: Implement MVE shifts by immediate
54
target/arm: Implement MVE shifts by register
55
80
56
Philippe Mathieu-Daudé (1):
81
docs/specs/acpi_cpu_hotplug.rst | 235 +++++++++++++++++++++
57
tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
82
docs/specs/acpi_cpu_hotplug.txt | 160 --------------
83
docs/specs/acpi_mem_hotplug.rst | 128 +++++++++++
84
docs/specs/acpi_mem_hotplug.txt | 94 ---------
85
docs/specs/acpi_nvdimm.rst | 228 ++++++++++++++++++++
86
docs/specs/acpi_nvdimm.txt | 188 -----------------
87
.../{acpi_pci_hotplug.txt => acpi_pci_hotplug.rst} | 37 ++--
88
docs/specs/index.rst | 4 +
89
meson.build | 2 +
90
include/hw/arm/xlnx-versal.h | 2 +
91
include/hw/arm/xlnx-zynqmp.h | 7 +
92
include/hw/dma/xlnx-zdma.h | 2 +-
93
include/hw/dma/xlnx_csu_dma.h | 2 +-
94
include/sysemu/arch_init.h | 15 +-
95
target/arm/cpu.h | 17 +-
96
target/arm/helper.h | 2 +
97
target/arm/syndrome.h | 7 +
98
blockdev.c | 1 -
99
gdbstub.c | 4 +-
100
hw/arm/raspi.c | 2 +-
101
hw/arm/virt.c | 5 -
102
hw/arm/xlnx-versal.c | 4 +
103
hw/arm/xlnx-zynqmp.c | 86 ++++++--
104
hw/core/loader.c | 35 ++-
105
hw/dma/xlnx-zdma.c | 24 +--
106
hw/dma/xlnx_csu_dma.c | 31 ++-
107
hw/i386/pc.c | 1 -
108
hw/i386/pc_piix.c | 1 -
109
hw/i386/pc_q35.c | 1 -
110
hw/mips/jazz.c | 1 -
111
hw/mips/malta.c | 1 -
112
hw/ppc/prep.c | 1 -
113
hw/riscv/sifive_e.c | 1 -
114
hw/riscv/sifive_u.c | 1 -
115
hw/riscv/spike.c | 1 -
116
hw/riscv/virt.c | 1 -
117
linux-user/arm/signal.c | 2 -
118
monitor/qmp-cmds.c | 3 +-
119
net/net.c | 2 +
120
softmmu/arch_init.c | 66 ------
121
softmmu/physmem.c | 5 +-
122
softmmu/qdev-monitor.c | 9 +
123
softmmu/vl.c | 6 +-
124
stubs/arch_type.c | 4 -
125
target/arm/cpu.c | 23 ++
126
target/arm/cpu64.c | 118 +++++------
127
target/arm/helper.c | 40 +++-
128
target/arm/kvm64.c | 2 +-
129
target/arm/op_helper.c | 16 ++
130
target/arm/translate.c | 12 ++
131
target/ppc/cpu_init.c | 1 -
132
target/s390x/cpu-sysemu.c | 1 -
133
tests/qtest/ipmi-bt-test.c | 2 +-
134
tests/tcg/multiarch/linux-test.c | 4 +-
135
MAINTAINERS | 5 +
136
hw/arm/Kconfig | 2 -
137
stubs/meson.build | 1 -
138
57 files changed, 949 insertions(+), 707 deletions(-)
139
create mode 100644 docs/specs/acpi_cpu_hotplug.rst
140
delete mode 100644 docs/specs/acpi_cpu_hotplug.txt
141
create mode 100644 docs/specs/acpi_mem_hotplug.rst
142
delete mode 100644 docs/specs/acpi_mem_hotplug.txt
143
create mode 100644 docs/specs/acpi_nvdimm.rst
144
delete mode 100644 docs/specs/acpi_nvdimm.txt
145
rename docs/specs/{acpi_pci_hotplug.txt => acpi_pci_hotplug.rst} (51%)
146
delete mode 100644 stubs/arch_type.c
58
147
59
docs/system/arm/aspeed.rst | 1 +
60
docs/system/arm/nuvoton.rst | 5 +-
61
include/hw/arm/bcm2835_peripherals.h | 3 +-
62
include/hw/misc/bcm2835_powermgt.h | 29 ++
63
target/arm/helper-mve.h | 108 +++++++
64
target/arm/translate.h | 41 +++
65
target/arm/mve.decode | 177 ++++++++++-
66
target/arm/t32.decode | 71 ++++-
67
hw/arm/bcm2835_peripherals.c | 13 +-
68
hw/gpio/gpio_pwr.c | 2 +-
69
hw/misc/bcm2835_powermgt.c | 160 ++++++++++
70
target/arm/helper-a64.c | 12 +-
71
target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--
72
target/arm/translate-a64.c | 86 +-----
73
target/arm/translate-mve.c | 261 +++++++++++++++-
74
target/arm/translate-neon.c | 81 -----
75
target/arm/translate.c | 327 +++++++++++++++++++-
76
target/arm/vfp_helper.c | 24 +-
77
hw/misc/meson.build | 1 +
78
tests/acceptance/boot_linux_console.py | 43 +++
79
20 files changed, 1760 insertions(+), 209 deletions(-)
80
create mode 100644 include/hw/misc/bcm2835_powermgt.h
81
create mode 100644 hw/misc/bcm2835_powermgt.c
82
diff view generated by jsdifflib
[PULL 23/24] target/arm: Implement MVE shifts by immediate
[PULL 01/37] hw/arm/xlnx-zynqmp: Realize qspi controller *after* qspi_dma
1
Implement the MVE shifts by immediate, which perform shifts
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
on a single general-purpose register.
3
2
4
These patterns overlap with the long-shift-by-immediates,
3
If we link QOM object (a) as a property of QOM object (b),
5
so we have to rearrange the grouping a little here.
4
we must set the property *before* (b) is realized.
6
5
6
Move QSPI realization *after* QSPI DMA.
7
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20210819163422.2863447-2-philmd@redhat.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
10
---
12
---
11
target/arm/helper-mve.h | 3 ++
13
hw/arm/xlnx-zynqmp.c | 42 ++++++++++++++++++++----------------------
12
target/arm/translate.h | 1 +
14
1 file changed, 20 insertions(+), 22 deletions(-)
13
target/arm/t32.decode | 31 ++++++++++++++-----
14
target/arm/mve_helper.c | 10 ++++++
15
target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++--
16
5 files changed, 104 insertions(+), 9 deletions(-)
17
15
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
16
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper-mve.h
18
--- a/hw/arm/xlnx-zynqmp.c
21
+++ b/target/arm/helper-mve.h
19
+++ b/hw/arm/xlnx-zynqmp.c
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
20
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
23
DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
21
g_free(bus_name);
24
DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
22
}
25
DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
23
24
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) {
25
- return;
26
- }
27
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
28
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
29
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
30
-
31
- for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
32
- gchar *bus_name;
33
- gchar *target_bus;
34
-
35
- /* Alias controller SPI bus to the SoC itself */
36
- bus_name = g_strdup_printf("qspi%d", i);
37
- target_bus = g_strdup_printf("spi%d", i);
38
- object_property_add_alias(OBJECT(s), bus_name,
39
- OBJECT(&s->qspi), target_bus);
40
- g_free(bus_name);
41
- g_free(target_bus);
42
- }
43
-
44
if (!sysbus_realize(SYS_BUS_DEVICE(&s->dp), errp)) {
45
return;
46
}
47
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
48
49
sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi_dma), 0, QSPI_DMA_ADDR);
50
sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0, gic_spi[QSPI_IRQ]);
51
- object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma",
52
- OBJECT(&s->qspi_dma), errp);
26
+
53
+
27
+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
54
+ if (!object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma",
28
+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
55
+ OBJECT(&s->qspi_dma), errp)) {
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
56
+ return;
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate.h
32
+++ b/target/arm/translate.h
33
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
34
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
35
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
36
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
37
+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
38
39
/**
40
* arm_tbflags_from_tb:
41
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/t32.decode
44
+++ b/target/arm/t32.decode
45
@@ -XXX,XX +XXX,XX @@
46
47
&mve_shl_ri rdalo rdahi shim
48
&mve_shl_rr rdalo rdahi rm
49
+&mve_sh_ri rda shim
50
51
# rdahi: bits [3:1] from insn, bit 0 is 1
52
# rdalo: bits [3:1] from insn, bit 0 is 0
53
@@ -XXX,XX +XXX,XX @@
54
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
55
@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
56
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
57
+@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
58
+ &mve_sh_ri shim=%imm5_12_6
59
60
{
61
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
62
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
63
# the rest fall through (where ORR_rrri and MOV_rxri will end up
64
# handling them as r13 and r15 accesses with the same semantics as A32).
65
[
66
- LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
67
- LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
68
- ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
69
+ {
70
+ UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri
71
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
72
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
73
+ }
57
+ }
74
58
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) {
75
- UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
76
- URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
77
- SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
78
- SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
79
+ {
80
+ URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri
81
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
82
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
83
+ }
84
+
85
+ {
86
+ SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri
87
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
88
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
89
+ }
90
+
91
+ {
92
+ SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri
93
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
94
+ }
95
96
LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
97
ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
98
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/mve_helper.c
101
+++ b/target/arm/mve_helper.c
102
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
103
{
104
return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
105
}
106
+
107
+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
108
+{
109
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
110
+}
111
+
112
+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
113
+{
114
+ return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
115
+}
116
diff --git a/target/arm/translate.c b/target/arm/translate.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/target/arm/translate.c
119
+++ b/target/arm/translate.c
120
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
121
122
static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
123
{
124
- TCGv_i32 t = tcg_temp_new_i32();
125
+ TCGv_i32 t;
126
127
+ /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
128
+ if (sh == 32) {
129
+ tcg_gen_movi_i32(d, 0);
130
+ return;
59
+ return;
131
+ }
60
+ }
132
+ t = tcg_temp_new_i32();
61
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR);
133
tcg_gen_extract_i32(t, a, sh - 1, 1);
62
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR);
134
tcg_gen_sari_i32(d, a, sh);
63
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]);
135
tcg_gen_add_i32(d, d, t);
64
+
136
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
65
+ for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) {
137
66
+ g_autofree gchar *bus_name = g_strdup_printf("qspi%d", i);
138
static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
67
+ g_autofree gchar *target_bus = g_strdup_printf("spi%d", i);
139
{
68
+
140
- TCGv_i32 t = tcg_temp_new_i32();
69
+ /* Alias controller SPI bus to the SoC itself */
141
+ TCGv_i32 t;
70
+ object_property_add_alias(OBJECT(s), bus_name,
142
71
+ OBJECT(&s->qspi), target_bus);
143
+ /* Handle shift by the input size for the benefit of trans_URSHR_ri */
144
+ if (sh == 32) {
145
+ tcg_gen_extract_i32(d, a, sh - 1, 1);
146
+ return;
147
+ }
72
+ }
148
+ t = tcg_temp_new_i32();
149
tcg_gen_extract_i32(t, a, sh - 1, 1);
150
tcg_gen_shri_i32(d, a, sh);
151
tcg_gen_add_i32(d, d, t);
152
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
153
return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
154
}
73
}
155
74
156
+static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
75
static Property xlnx_zynqmp_props[] = {
157
+{
158
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
159
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
160
+ return false;
161
+ }
162
+ if (!dc_isar_feature(aa32_mve, s) ||
163
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
164
+ a->rda == 13 || a->rda == 15) {
165
+ /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
166
+ unallocated_encoding(s);
167
+ return true;
168
+ }
169
+
170
+ if (a->shim == 0) {
171
+ a->shim = 32;
172
+ }
173
+ fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
174
+
175
+ return true;
176
+}
177
+
178
+static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
179
+{
180
+ return do_mve_sh_ri(s, a, gen_urshr32_i32);
181
+}
182
+
183
+static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
184
+{
185
+ return do_mve_sh_ri(s, a, gen_srshr32_i32);
186
+}
187
+
188
+static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
189
+{
190
+ gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
191
+}
192
+
193
+static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
194
+{
195
+ return do_mve_sh_ri(s, a, gen_mve_sqshl);
196
+}
197
+
198
+static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
199
+{
200
+ gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
201
+}
202
+
203
+static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
204
+{
205
+ return do_mve_sh_ri(s, a, gen_mve_uqshl);
206
+}
207
+
208
/*
209
* Multiply and multiply accumulate
210
*/
211
--
76
--
212
2.20.1
77
2.20.1
213
78
214
79
diff view generated by jsdifflib
[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
[PULL 02/37] hw/dma/xlnx_csu_dma: Run trivial checks early in realize()
1
From: Patrick Venture <venture@google.com>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
Adds a line-item reference to the supported quanta-q71l-bmc aspeed
3
If some property are not set, we'll return indicating a failure,
4
entry.
4
so it is pointless to allocate / initialize some fields too early.
5
Move the trivial checks earlier in realize().
5
6
6
Signed-off-by: Patrick Venture <venture@google.com>
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210615192848.1065297-2-venture@google.com
9
Message-id: 20210819163422.2863447-3-philmd@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
docs/system/arm/aspeed.rst | 1 +
12
hw/dma/xlnx_csu_dma.c | 10 +++++-----
12
1 file changed, 1 insertion(+)
13
1 file changed, 5 insertions(+), 5 deletions(-)
13
14
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
15
diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/aspeed.rst
17
--- a/hw/dma/xlnx_csu_dma.c
17
+++ b/docs/system/arm/aspeed.rst
18
+++ b/hw/dma/xlnx_csu_dma.c
18
@@ -XXX,XX +XXX,XX @@ etc.
19
@@ -XXX,XX +XXX,XX @@ static void xlnx_csu_dma_realize(DeviceState *dev, Error **errp)
19
AST2400 SoC based machines :
20
XlnxCSUDMA *s = XLNX_CSU_DMA(dev);
20
21
RegisterInfoArray *reg_array;
21
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
22
22
+- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
23
+ if (!s->is_dst && !s->tx_dev) {
23
24
+ error_setg(errp, "zynqmp.csu-dma: Stream not connected");
24
AST2500 SoC based machines :
25
+ return;
26
+ }
27
+
28
reg_array =
29
register_init_block32(dev, xlnx_csu_dma_regs_info[!!s->is_dst],
30
XLNX_CSU_DMA_R_MAX,
31
@@ -XXX,XX +XXX,XX @@ static void xlnx_csu_dma_realize(DeviceState *dev, Error **errp)
32
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
33
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
34
35
- if (!s->is_dst && !s->tx_dev) {
36
- error_setg(errp, "zynqmp.csu-dma: Stream not connected");
37
- return;
38
- }
39
-
40
s->src_timer = ptimer_init(xlnx_csu_dma_src_timeout_hit,
41
s, PTIMER_POLICY_DEFAULT);
25
42
26
--
43
--
27
2.20.1
44
2.20.1
28
45
29
46
diff view generated by jsdifflib
[PULL 03/24] hw/arm: Add basic power management to raspi.
[PULL 03/37] hw/dma/xlnx_csu_dma: Always expect 'dma' link property to be set
1
From: Nolan Leake <nolan@sigbus.net>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
This is just enough to make reboot and poweroff work. Works for
3
Simplify by always passing a MemoryRegion property to the device.
4
linux, u-boot, and the arm trusted firmware. Not tested, but should
4
Doing so we can move the AddressSpace field to the device struct,
5
work for plan9, and bare-metal/hobby OSes, since they seem to generally
5
removing need for heap allocation.
6
do what linux does for reset.
7
6
8
The watchdog timer functionality is not yet implemented.
7
Update the Xilinx ZynqMP SoC model to pass the default system
8
memory instead of a NULL value.
9
9
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
10
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Nolan Leake <nolan@sigbus.net>
11
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20210819163422.2863447-4-philmd@redhat.com
14
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
15
[PMM: tweaked commit title; fixed region size to 0x200;
16
moved header file to include/]
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
15
---
19
include/hw/arm/bcm2835_peripherals.h | 3 +-
16
include/hw/dma/xlnx_csu_dma.h | 2 +-
20
include/hw/misc/bcm2835_powermgt.h | 29 +++++
17
hw/arm/xlnx-zynqmp.c | 4 ++++
21
hw/arm/bcm2835_peripherals.c | 13 ++-
18
hw/dma/xlnx_csu_dma.c | 21 ++++++++++-----------
22
hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++
19
3 files changed, 15 insertions(+), 12 deletions(-)
23
hw/misc/meson.build | 1 +
24
5 files changed, 204 insertions(+), 2 deletions(-)
25
create mode 100644 include/hw/misc/bcm2835_powermgt.h
26
create mode 100644 hw/misc/bcm2835_powermgt.c
27
20
28
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
21
diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw/dma/xlnx_csu_dma.h
29
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/bcm2835_peripherals.h
23
--- a/include/hw/dma/xlnx_csu_dma.h
31
+++ b/include/hw/arm/bcm2835_peripherals.h
24
+++ b/include/hw/dma/xlnx_csu_dma.h
32
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ typedef struct XlnxCSUDMA {
33
#include "hw/misc/bcm2835_mphi.h"
26
MemoryRegion iomem;
34
#include "hw/misc/bcm2835_thermal.h"
27
MemTxAttrs attr;
35
#include "hw/misc/bcm2835_cprman.h"
28
MemoryRegion *dma_mr;
36
+#include "hw/misc/bcm2835_powermgt.h"
29
- AddressSpace *dma_as;
37
#include "hw/sd/sdhci.h"
30
+ AddressSpace dma_as;
38
#include "hw/sd/bcm2835_sdhost.h"
31
qemu_irq irq;
39
#include "hw/gpio/bcm2835_gpio.h"
32
StreamSink *tx_dev; /* Used as generic StreamSink */
40
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
33
ptimer_state *src_timer;
41
BCM2835MphiState mphi;
34
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
42
UnimplementedDeviceState txp;
43
UnimplementedDeviceState armtmr;
44
- UnimplementedDeviceState powermgt;
45
+ BCM2835PowerMgtState powermgt;
46
BCM2835CprmanState cprman;
47
PL011State uart0;
48
BCM2835AuxState aux;
49
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
50
new file mode 100644
51
index XXXXXXX..XXXXXXX
52
--- /dev/null
53
+++ b/include/hw/misc/bcm2835_powermgt.h
54
@@ -XXX,XX +XXX,XX @@
55
+/*
56
+ * BCM2835 Power Management emulation
57
+ *
58
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
59
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
60
+ *
61
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
62
+ * See the COPYING file in the top-level directory.
63
+ */
64
+
65
+#ifndef BCM2835_POWERMGT_H
66
+#define BCM2835_POWERMGT_H
67
+
68
+#include "hw/sysbus.h"
69
+#include "qom/object.h"
70
+
71
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
72
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
73
+
74
+struct BCM2835PowerMgtState {
75
+ SysBusDevice busdev;
76
+ MemoryRegion iomem;
77
+
78
+ uint32_t rstc;
79
+ uint32_t rsts;
80
+ uint32_t wdog;
81
+};
82
+
83
+#endif
84
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
85
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/arm/bcm2835_peripherals.c
36
--- a/hw/arm/xlnx-zynqmp.c
87
+++ b/hw/arm/bcm2835_peripherals.c
37
+++ b/hw/arm/xlnx-zynqmp.c
88
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
38
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
89
39
gic_spi[adma_ch_intr[i]]);
90
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
40
}
91
OBJECT(&s->gpu_bus_mr));
41
92
+
42
+ if (!object_property_set_link(OBJECT(&s->qspi_dma), "dma",
93
+ /* Power Management */
43
+ OBJECT(system_memory), errp)) {
94
+ object_initialize_child(obj, "powermgt", &s->powermgt,
95
+ TYPE_BCM2835_POWERMGT);
96
}
97
98
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
99
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
100
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
101
INTERRUPT_USB));
102
103
+ /* Power Management */
104
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
105
+ return;
44
+ return;
106
+ }
45
+ }
107
+
46
if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi_dma), errp)) {
108
+ memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
47
return;
109
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
48
}
110
+
49
diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c
111
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
50
index XXXXXXX..XXXXXXX 100644
112
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
51
--- a/hw/dma/xlnx_csu_dma.c
113
- create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
52
+++ b/hw/dma/xlnx_csu_dma.c
114
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
53
@@ -XXX,XX +XXX,XX @@ static uint32_t xlnx_csu_dma_read(XlnxCSUDMA *s, uint8_t *buf, uint32_t len)
115
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
54
for (i = 0; i < len && (result == MEMTX_OK); i += s->width) {
116
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
55
uint32_t mlen = MIN(len - i, s->width);
117
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
56
118
new file mode 100644
57
- result = address_space_rw(s->dma_as, addr, s->attr,
119
index XXXXXXX..XXXXXXX
58
+ result = address_space_rw(&s->dma_as, addr, s->attr,
120
--- /dev/null
59
buf + i, mlen, false);
121
+++ b/hw/misc/bcm2835_powermgt.c
60
}
122
@@ -XXX,XX +XXX,XX @@
61
} else {
123
+/*
62
- result = address_space_rw(s->dma_as, addr, s->attr, buf, len, false);
124
+ * BCM2835 Power Management emulation
63
+ result = address_space_rw(&s->dma_as, addr, s->attr, buf, len, false);
125
+ *
64
}
126
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
65
127
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
66
if (result == MEMTX_OK) {
128
+ *
67
@@ -XXX,XX +XXX,XX @@ static uint32_t xlnx_csu_dma_write(XlnxCSUDMA *s, uint8_t *buf, uint32_t len)
129
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
68
for (i = 0; i < len && (result == MEMTX_OK); i += s->width) {
130
+ * See the COPYING file in the top-level directory.
69
uint32_t mlen = MIN(len - i, s->width);
131
+ */
70
132
+
71
- result = address_space_rw(s->dma_as, addr, s->attr,
133
+#include "qemu/osdep.h"
72
+ result = address_space_rw(&s->dma_as, addr, s->attr,
134
+#include "qemu/log.h"
73
buf, mlen, true);
135
+#include "qemu/module.h"
74
buf += mlen;
136
+#include "hw/misc/bcm2835_powermgt.h"
75
}
137
+#include "migration/vmstate.h"
76
} else {
138
+#include "sysemu/runstate.h"
77
- result = address_space_rw(s->dma_as, addr, s->attr, buf, len, true);
139
+
78
+ result = address_space_rw(&s->dma_as, addr, s->attr, buf, len, true);
140
+#define PASSWORD 0x5a000000
79
}
141
+#define PASSWORD_MASK 0xff000000
80
142
+
81
if (result != MEMTX_OK) {
143
+#define R_RSTC 0x1c
82
@@ -XXX,XX +XXX,XX @@ static void xlnx_csu_dma_realize(DeviceState *dev, Error **errp)
144
+#define V_RSTC_RESET 0x20
83
return;
145
+#define R_RSTS 0x20
84
}
146
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
85
147
+#define R_WDOG 0x24
86
+ if (!s->dma_mr) {
148
+
87
+ error_setg(errp, TYPE_XLNX_CSU_DMA " 'dma' link not set");
149
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
150
+ unsigned size)
151
+{
152
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
153
+ uint32_t res = 0;
154
+
155
+ switch (offset) {
156
+ case R_RSTC:
157
+ res = s->rstc;
158
+ break;
159
+ case R_RSTS:
160
+ res = s->rsts;
161
+ break;
162
+ case R_WDOG:
163
+ res = s->wdog;
164
+ break;
165
+
166
+ default:
167
+ qemu_log_mask(LOG_UNIMP,
168
+ "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
169
+ "\n", offset);
170
+ res = 0;
171
+ break;
172
+ }
173
+
174
+ return res;
175
+}
176
+
177
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
178
+ uint64_t value, unsigned size)
179
+{
180
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
181
+
182
+ if ((value & PASSWORD_MASK) != PASSWORD) {
183
+ qemu_log_mask(LOG_GUEST_ERROR,
184
+ "bcm2835_powermgt_write: Bad password 0x%"PRIx64
185
+ " at offset 0x%08"HWADDR_PRIx"\n",
186
+ value, offset);
187
+ return;
88
+ return;
188
+ }
89
+ }
90
+ address_space_init(&s->dma_as, s->dma_mr, "csu-dma");
189
+
91
+
190
+ value = value & ~PASSWORD_MASK;
92
reg_array =
191
+
93
register_init_block32(dev, xlnx_csu_dma_regs_info[!!s->is_dst],
192
+ switch (offset) {
94
XLNX_CSU_DMA_R_MAX,
193
+ case R_RSTC:
95
@@ -XXX,XX +XXX,XX @@ static void xlnx_csu_dma_realize(DeviceState *dev, Error **errp)
194
+ s->rstc = value;
96
s->src_timer = ptimer_init(xlnx_csu_dma_src_timeout_hit,
195
+ if (value & V_RSTC_RESET) {
97
s, PTIMER_POLICY_DEFAULT);
196
+ if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
98
197
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
99
- if (s->dma_mr) {
198
+ } else {
100
- s->dma_as = g_malloc0(sizeof(AddressSpace));
199
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
101
- address_space_init(s->dma_as, s->dma_mr, NULL);
200
+ }
102
- } else {
201
+ }
103
- s->dma_as = &address_space_memory;
202
+ break;
104
- }
203
+ case R_RSTS:
105
-
204
+ qemu_log_mask(LOG_UNIMP,
106
s->attr = MEMTXATTRS_UNSPECIFIED;
205
+ "bcm2835_powermgt_write: RSTS\n");
107
206
+ s->rsts = value;
108
s->r_size_last_word = 0;
207
+ break;
208
+ case R_WDOG:
209
+ qemu_log_mask(LOG_UNIMP,
210
+ "bcm2835_powermgt_write: WDOG\n");
211
+ s->wdog = value;
212
+ break;
213
+
214
+ default:
215
+ qemu_log_mask(LOG_UNIMP,
216
+ "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
217
+ "\n", offset);
218
+ break;
219
+ }
220
+}
221
+
222
+static const MemoryRegionOps bcm2835_powermgt_ops = {
223
+ .read = bcm2835_powermgt_read,
224
+ .write = bcm2835_powermgt_write,
225
+ .endianness = DEVICE_NATIVE_ENDIAN,
226
+ .impl.min_access_size = 4,
227
+ .impl.max_access_size = 4,
228
+};
229
+
230
+static const VMStateDescription vmstate_bcm2835_powermgt = {
231
+ .name = TYPE_BCM2835_POWERMGT,
232
+ .version_id = 1,
233
+ .minimum_version_id = 1,
234
+ .fields = (VMStateField[]) {
235
+ VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
236
+ VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
237
+ VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
238
+ VMSTATE_END_OF_LIST()
239
+ }
240
+};
241
+
242
+static void bcm2835_powermgt_init(Object *obj)
243
+{
244
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
245
+
246
+ memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
247
+ TYPE_BCM2835_POWERMGT, 0x200);
248
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
249
+}
250
+
251
+static void bcm2835_powermgt_reset(DeviceState *dev)
252
+{
253
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
254
+
255
+ /* https://elinux.org/BCM2835_registers#PM */
256
+ s->rstc = 0x00000102;
257
+ s->rsts = 0x00001000;
258
+ s->wdog = 0x00000000;
259
+}
260
+
261
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
262
+{
263
+ DeviceClass *dc = DEVICE_CLASS(klass);
264
+
265
+ dc->reset = bcm2835_powermgt_reset;
266
+ dc->vmsd = &vmstate_bcm2835_powermgt;
267
+}
268
+
269
+static TypeInfo bcm2835_powermgt_info = {
270
+ .name = TYPE_BCM2835_POWERMGT,
271
+ .parent = TYPE_SYS_BUS_DEVICE,
272
+ .instance_size = sizeof(BCM2835PowerMgtState),
273
+ .class_init = bcm2835_powermgt_class_init,
274
+ .instance_init = bcm2835_powermgt_init,
275
+};
276
+
277
+static void bcm2835_powermgt_register_types(void)
278
+{
279
+ type_register_static(&bcm2835_powermgt_info);
280
+}
281
+
282
+type_init(bcm2835_powermgt_register_types)
283
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
284
index XXXXXXX..XXXXXXX 100644
285
--- a/hw/misc/meson.build
286
+++ b/hw/misc/meson.build
287
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
288
'bcm2835_rng.c',
289
'bcm2835_thermal.c',
290
'bcm2835_cprman.c',
291
+ 'bcm2835_powermgt.c',
292
))
293
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
294
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
295
--
109
--
296
2.20.1
110
2.20.1
297
111
298
112
diff view generated by jsdifflib
[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
[PULL 04/37] hw/dma/xlnx-zdma Always expect 'dma' link property to be set
1
In do_ldst(), the calculation of the offset needs to be based on the
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
size of the memory access, not the size of the elements in the
3
vector. This meant we were getting it wrong for the widening and
4
narrowing variants of the various VLDR and VSTR insns.
5
2
3
Simplify by always passing a MemoryRegion property to the device.
4
Doing so we can move the AddressSpace field to the device struct,
5
removing need for heap allocation.
6
7
Update the Xilinx ZynqMP / Versal SoC models to pass the default
8
system memory instead of a NULL value.
9
10
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Message-id: 20210819163422.2863447-5-philmd@redhat.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
9
---
15
---
10
target/arm/translate-mve.c | 17 +++++++++--------
16
include/hw/dma/xlnx-zdma.h | 2 +-
11
1 file changed, 9 insertions(+), 8 deletions(-)
17
hw/arm/xlnx-versal.c | 2 ++
18
hw/arm/xlnx-zynqmp.c | 8 ++++++++
19
hw/dma/xlnx-zdma.c | 24 ++++++++++++------------
20
4 files changed, 23 insertions(+), 13 deletions(-)
12
21
13
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
22
diff --git a/include/hw/dma/xlnx-zdma.h b/include/hw/dma/xlnx-zdma.h
14
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-mve.c
24
--- a/include/hw/dma/xlnx-zdma.h
16
+++ b/target/arm/translate-mve.c
25
+++ b/include/hw/dma/xlnx-zdma.h
17
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
26
@@ -XXX,XX +XXX,XX @@ struct XlnxZDMA {
27
MemoryRegion iomem;
28
MemTxAttrs attr;
29
MemoryRegion *dma_mr;
30
- AddressSpace *dma_as;
31
+ AddressSpace dma_as;
32
qemu_irq irq_zdma_ch_imr;
33
34
struct {
35
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/arm/xlnx-versal.c
38
+++ b/hw/arm/xlnx-versal.c
39
@@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic)
40
TYPE_XLNX_ZDMA);
41
dev = DEVICE(&s->lpd.iou.adma[i]);
42
object_property_set_int(OBJECT(dev), "bus-width", 128, &error_abort);
43
+ object_property_set_link(OBJECT(dev), "dma",
44
+ OBJECT(get_system_memory()), &error_fatal);
45
sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
46
47
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
48
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/arm/xlnx-zynqmp.c
51
+++ b/hw/arm/xlnx-zynqmp.c
52
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
53
errp)) {
54
return;
55
}
56
+ if (!object_property_set_link(OBJECT(&s->gdma[i]), "dma",
57
+ OBJECT(system_memory), errp)) {
58
+ return;
59
+ }
60
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) {
61
return;
62
}
63
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
18
}
64
}
65
66
for (i = 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) {
67
+ if (!object_property_set_link(OBJECT(&s->adma[i]), "dma",
68
+ OBJECT(system_memory), errp)) {
69
+ return;
70
+ }
71
if (!sysbus_realize(SYS_BUS_DEVICE(&s->adma[i]), errp)) {
72
return;
73
}
74
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/hw/dma/xlnx-zdma.c
77
+++ b/hw/dma/xlnx-zdma.c
78
@@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr,
79
return false;
80
}
81
82
- descr->addr = address_space_ldq_le(s->dma_as, addr, s->attr, NULL);
83
- descr->size = address_space_ldl_le(s->dma_as, addr + 8, s->attr, NULL);
84
- descr->attr = address_space_ldl_le(s->dma_as, addr + 12, s->attr, NULL);
85
+ descr->addr = address_space_ldq_le(&s->dma_as, addr, s->attr, NULL);
86
+ descr->size = address_space_ldl_le(&s->dma_as, addr + 8, s->attr, NULL);
87
+ descr->attr = address_space_ldl_le(&s->dma_as, addr + 12, s->attr, NULL);
88
return true;
19
}
89
}
20
90
21
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
91
@@ -XXX,XX +XXX,XX @@ static void zdma_update_descr_addr(XlnxZDMA *s, bool type,
22
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
92
} else {
23
+ unsigned msize)
93
addr = zdma_get_regaddr64(s, basereg);
24
{
94
addr += sizeof(s->dsc_dst);
25
TCGv_i32 addr;
95
- next = address_space_ldq_le(s->dma_as, addr, s->attr, NULL);
26
uint32_t offset;
96
+ next = address_space_ldq_le(&s->dma_as, addr, s->attr, NULL);
27
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
28
return true;
29
}
97
}
30
98
31
- offset = a->imm << a->size;
99
zdma_put_regaddr64(s, basereg, next);
32
+ offset = a->imm << msize;
100
@@ -XXX,XX +XXX,XX @@ static void zdma_write_dst(XlnxZDMA *s, uint8_t *buf, uint32_t len)
33
if (!a->a) {
101
}
34
offset = -offset;
102
}
103
104
- address_space_write(s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen);
105
+ address_space_write(&s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen);
106
if (burst_type == AXI_BURST_INCR) {
107
s->dsc_dst.addr += dlen;
108
}
109
@@ -XXX,XX +XXX,XX @@ static void zdma_process_descr(XlnxZDMA *s)
110
len = s->cfg.bus_width / 8;
111
}
112
} else {
113
- address_space_read(s->dma_as, src_addr, s->attr, s->buf, len);
114
+ address_space_read(&s->dma_as, src_addr, s->attr, s->buf, len);
115
if (burst_type == AXI_BURST_INCR) {
116
src_addr += len;
117
}
118
@@ -XXX,XX +XXX,XX @@ static void zdma_realize(DeviceState *dev, Error **errp)
119
XlnxZDMA *s = XLNX_ZDMA(dev);
120
unsigned int i;
121
122
+ if (!s->dma_mr) {
123
+ error_setg(errp, TYPE_XLNX_ZDMA " 'dma' link not set");
124
+ return;
125
+ }
126
+ address_space_init(&s->dma_as, s->dma_mr, "zdma-dma");
127
+
128
for (i = 0; i < ARRAY_SIZE(zdma_regs_info); ++i) {
129
RegisterInfo *r = &s->regs_info[zdma_regs_info[i].addr / 4];
130
131
@@ -XXX,XX +XXX,XX @@ static void zdma_realize(DeviceState *dev, Error **errp)
132
};
35
}
133
}
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
134
37
{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
135
- if (s->dma_mr) {
38
{ NULL, NULL }
136
- s->dma_as = g_malloc0(sizeof(AddressSpace));
39
};
137
- address_space_init(s->dma_as, s->dma_mr, NULL);
40
- return do_ldst(s, a, ldstfns[a->size][a->l]);
138
- } else {
41
+ return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
139
- s->dma_as = &address_space_memory;
140
- }
141
s->attr = MEMTXATTRS_UNSPECIFIED;
42
}
142
}
43
143
44
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \
45
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \
46
static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \
47
{ \
48
static MVEGenLdStFn * const ldstfns[2][2] = { \
49
{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
50
{ NULL, gen_helper_mve_##ULD }, \
51
}; \
52
- return do_ldst(s, a, ldstfns[a->u][a->l]); \
53
+ return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \
54
}
55
56
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
57
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
58
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
59
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
60
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
61
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
62
63
static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
64
{
65
--
144
--
66
2.20.1
145
2.20.1
67
146
68
147
diff view generated by jsdifflib
New patch
[PULL 05/37] hw/arm/Kconfig: no need to enable ACPI_MEMORY_HOTPLUG/ACPI_NVDIMM explicitly
1
From: Ani Sinha <ani@anisinha.ca>
1
2
3
Since commit
4
36b79e3219d ("hw/acpi/Kconfig: Add missing Kconfig dependencies (build error)"),
5
ACPI_MEMORY_HOTPLUG and ACPI_NVDIMM is implicitly turned on when
6
ACPI_HW_REDUCED is selected. ACPI_HW_REDUCED is already enabled. No need to
7
turn on ACPI_MEMORY_HOTPLUG or ACPI_NVDIMM explicitly. This is a minor cleanup.
8
9
Signed-off-by: Ani Sinha <ani@anisinha.ca>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20210819162637.518507-1-ani@anisinha.ca
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/Kconfig | 2 --
15
1 file changed, 2 deletions(-)
16
17
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/Kconfig
20
+++ b/hw/arm/Kconfig
21
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
22
select ACPI_PCI
23
select MEM_DEVICE
24
select DIMM
25
- select ACPI_MEMORY_HOTPLUG
26
select ACPI_HW_REDUCED
27
- select ACPI_NVDIMM
28
select ACPI_APEI
29
30
config CHEETAH
31
--
32
2.20.1
33
34
diff view generated by jsdifflib
New patch
[PULL 06/37] target/arm/cpu: Introduce sve_vq_supported bitmap
1
From: Andrew Jones <drjones@redhat.com>
1
2
3
Allow CPUs that support SVE to specify which SVE vector lengths they
4
support by setting them in this bitmap. Currently only the 'max' and
5
'host' CPU types supports SVE and 'host' requires KVM which obtains
6
its supported bitmap from the host. So, we only need to initialize the
7
bitmap for 'max' with TCG. And, since 'max' should support all SVE
8
vector lengths we simply fill the bitmap. Future CPU types may have
9
less trivial maps though.
10
11
Signed-off-by: Andrew Jones <drjones@redhat.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20210823160647.34028-2-drjones@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/cpu.h | 4 ++++
18
target/arm/cpu64.c | 2 ++
19
2 files changed, 6 insertions(+)
20
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
24
+++ b/target/arm/cpu.h
25
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
26
* While processing properties during initialization, corresponding
27
* sve_vq_init bits are set for bits in sve_vq_map that have been
28
* set by properties.
29
+ *
30
+ * Bits set in sve_vq_supported represent valid vector lengths for
31
+ * the CPU type.
32
*/
33
DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
34
DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
35
+ DECLARE_BITMAP(sve_vq_supported, ARM_MAX_VQ);
36
37
/* Generic timer counter frequency, in Hz */
38
uint64_t gt_cntfrq_hz;
39
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/cpu64.c
42
+++ b/target/arm/cpu64.c
43
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
44
/* Default to PAUTH on, with the architected algorithm. */
45
qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property);
46
qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property);
47
+
48
+ bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ);
49
}
50
51
aarch64_add_sve_properties(obj);
52
--
53
2.20.1
54
55
diff view generated by jsdifflib
[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
[PULL 07/37] target/arm/kvm64: Ensure sve vls map is completely clear
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
qemu has 2 type of functions: shutdown and reboot. Shutdown
3
bitmap_clear() only clears the given range. While the given
4
function has to be used for machine shutdown. Otherwise we cause
4
range should be sufficient in this case we might as well be
5
a reset with a bogus "cause" value, when we intended a shutdown.
5
100% sure all bits are zeroed by using bitmap_zero().
6
6
7
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
[PMM: tweaked commit message]
10
Message-id: 20210823160647.34028-3-drjones@redhat.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
12
---
13
hw/gpio/gpio_pwr.c | 2 +-
13
target/arm/kvm64.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
15
16
diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
16
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/gpio/gpio_pwr.c
18
--- a/target/arm/kvm64.c
19
+++ b/hw/gpio/gpio_pwr.c
19
+++ b/target/arm/kvm64.c
20
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
20
@@ -XXX,XX +XXX,XX @@ void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
21
static void gpio_pwr_shutdown(void *opaque, int n, int level)
21
uint32_t vq = 0;
22
{
22
int i, j;
23
if (level) {
23
24
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
24
- bitmap_clear(map, 0, ARM_MAX_VQ);
25
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
25
+ bitmap_zero(map, ARM_MAX_VQ);
26
}
26
27
}
27
/*
28
28
* KVM ensures all host CPUs support the same set of vector lengths.
29
--
29
--
30
2.20.1
30
2.20.1
31
31
32
32
diff view generated by jsdifflib
[PULL 05/24] target/arm: Check NaN mode before silencing NaN
[PULL 08/37] target/arm/cpu64: Replace kvm_supported with sve_vq_supported
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
3
Now that we have an ARMCPU member sve_vq_supported we no longer
4
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
4
need the local kvm_supported bitmap for KVM's supported vector
5
assert due to fpst->default_nan_mode being set.
5
lengths.
6
6
7
To avoid this, we check to see what NaN mode we're running in before we call
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
8
floatxx_silence_nan().
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
10
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
10
Message-id: 20210823160647.34028-4-drjones@redhat.com
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
12
---
16
target/arm/helper-a64.c | 12 +++++++++---
13
target/arm/cpu64.c | 19 +++++++++++--------
17
target/arm/vfp_helper.c | 24 ++++++++++++++++++------
14
1 file changed, 11 insertions(+), 8 deletions(-)
18
2 files changed, 27 insertions(+), 9 deletions(-)
19
15
20
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
16
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
21
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper-a64.c
18
--- a/target/arm/cpu64.c
23
+++ b/target/arm/helper-a64.c
19
+++ b/target/arm/cpu64.c
24
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
20
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
25
float16 nan = a;
21
* any of the above. Finally, if SVE is not disabled, then at least one
26
if (float16_is_signaling_nan(a, fpst)) {
22
* vector length must be enabled.
27
float_raise(float_flag_invalid, fpst);
23
*/
28
- nan = float16_silence_nan(a, fpst);
24
- DECLARE_BITMAP(kvm_supported, ARM_MAX_VQ);
29
+ if (!fpst->default_nan_mode) {
25
DECLARE_BITMAP(tmp, ARM_MAX_VQ);
30
+ nan = float16_silence_nan(a, fpst);
26
uint32_t vq, max_vq = 0;
31
+ }
27
32
}
28
- /* Collect the set of vector lengths supported by KVM. */
33
if (fpst->default_nan_mode) {
29
- bitmap_zero(kvm_supported, ARM_MAX_VQ);
34
nan = float16_default_nan(fpst);
30
+ /*
35
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
31
+ * CPU models specify a set of supported vector lengths which are
36
float32 nan = a;
32
+ * enabled by default. Attempting to enable any vector length not set
37
if (float32_is_signaling_nan(a, fpst)) {
33
+ * in the supported bitmap results in an error. When KVM is enabled we
38
float_raise(float_flag_invalid, fpst);
34
+ * fetch the supported bitmap from the host.
39
- nan = float32_silence_nan(a, fpst);
35
+ */
40
+ if (!fpst->default_nan_mode) {
36
if (kvm_enabled() && kvm_arm_sve_supported()) {
41
+ nan = float32_silence_nan(a, fpst);
37
- kvm_arm_sve_get_vls(CPU(cpu), kvm_supported);
42
+ }
38
+ kvm_arm_sve_get_vls(CPU(cpu), cpu->sve_vq_supported);
43
}
39
} else if (kvm_enabled()) {
44
if (fpst->default_nan_mode) {
40
assert(!cpu_isar_feature(aa64_sve, cpu));
45
nan = float32_default_nan(fpst);
41
}
46
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
42
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
47
float64 nan = a;
43
* For KVM we have to automatically enable all supported unitialized
48
if (float64_is_signaling_nan(a, fpst)) {
44
* lengths, even when the smaller lengths are not all powers-of-two.
49
float_raise(float_flag_invalid, fpst);
45
*/
50
- nan = float64_silence_nan(a, fpst);
46
- bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq);
51
+ if (!fpst->default_nan_mode) {
47
+ bitmap_andnot(tmp, cpu->sve_vq_supported, cpu->sve_vq_init, max_vq);
52
+ nan = float64_silence_nan(a, fpst);
48
bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);
53
+ }
49
} else {
54
}
50
/* Propagate enabled bits down through required powers-of-two. */
55
if (fpst->default_nan_mode) {
51
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
56
nan = float64_default_nan(fpst);
52
/* Disabling a supported length disables all larger lengths. */
57
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
53
for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
58
index XXXXXXX..XXXXXXX 100644
54
if (test_bit(vq - 1, cpu->sve_vq_init) &&
59
--- a/target/arm/vfp_helper.c
55
- test_bit(vq - 1, kvm_supported)) {
60
+++ b/target/arm/vfp_helper.c
56
+ test_bit(vq - 1, cpu->sve_vq_supported)) {
61
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
57
break;
62
float16 nan = f16;
58
}
63
if (float16_is_signaling_nan(f16, fpst)) {
59
}
64
float_raise(float_flag_invalid, fpst);
60
max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
65
- nan = float16_silence_nan(f16, fpst);
61
- bitmap_andnot(cpu->sve_vq_map, kvm_supported,
66
+ if (!fpst->default_nan_mode) {
62
+ bitmap_andnot(cpu->sve_vq_map, cpu->sve_vq_supported,
67
+ nan = float16_silence_nan(f16, fpst);
63
cpu->sve_vq_init, max_vq);
68
+ }
64
if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) {
69
}
65
error_setg(errp, "cannot disable sve%d", vq * 128);
70
if (fpst->default_nan_mode) {
66
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
71
nan = float16_default_nan(fpst);
67
72
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
68
if (kvm_enabled()) {
73
float32 nan = f32;
69
/* Ensure the set of lengths matches what KVM supports. */
74
if (float32_is_signaling_nan(f32, fpst)) {
70
- bitmap_xor(tmp, cpu->sve_vq_map, kvm_supported, max_vq);
75
float_raise(float_flag_invalid, fpst);
71
+ bitmap_xor(tmp, cpu->sve_vq_map, cpu->sve_vq_supported, max_vq);
76
- nan = float32_silence_nan(f32, fpst);
72
if (!bitmap_empty(tmp, max_vq)) {
77
+ if (!fpst->default_nan_mode) {
73
vq = find_last_bit(tmp, max_vq) + 1;
78
+ nan = float32_silence_nan(f32, fpst);
74
if (test_bit(vq - 1, cpu->sve_vq_map)) {
79
+ }
80
}
81
if (fpst->default_nan_mode) {
82
nan = float32_default_nan(fpst);
83
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
84
float64 nan = f64;
85
if (float64_is_signaling_nan(f64, fpst)) {
86
float_raise(float_flag_invalid, fpst);
87
- nan = float64_silence_nan(f64, fpst);
88
+ if (!fpst->default_nan_mode) {
89
+ nan = float64_silence_nan(f64, fpst);
90
+ }
91
}
92
if (fpst->default_nan_mode) {
93
nan = float64_default_nan(fpst);
94
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
95
float16 nan = f16;
96
if (float16_is_signaling_nan(f16, s)) {
97
float_raise(float_flag_invalid, s);
98
- nan = float16_silence_nan(f16, s);
99
+ if (!s->default_nan_mode) {
100
+ nan = float16_silence_nan(f16, fpstp);
101
+ }
102
}
103
if (s->default_nan_mode) {
104
nan = float16_default_nan(s);
105
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
106
float32 nan = f32;
107
if (float32_is_signaling_nan(f32, s)) {
108
float_raise(float_flag_invalid, s);
109
- nan = float32_silence_nan(f32, s);
110
+ if (!s->default_nan_mode) {
111
+ nan = float32_silence_nan(f32, fpstp);
112
+ }
113
}
114
if (s->default_nan_mode) {
115
nan = float32_default_nan(s);
116
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
117
float64 nan = f64;
118
if (float64_is_signaling_nan(f64, s)) {
119
float_raise(float_flag_invalid, s);
120
- nan = float64_silence_nan(f64, s);
121
+ if (!s->default_nan_mode) {
122
+ nan = float64_silence_nan(f64, fpstp);
123
+ }
124
}
125
if (s->default_nan_mode) {
126
nan = float64_default_nan(s);
127
--
75
--
128
2.20.1
76
2.20.1
129
77
130
78
diff view generated by jsdifflib
[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
[PULL 09/37] target/arm/cpu64: Validate sve vector lengths are supported
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
Add a test booting and quickly shutdown a raspi2 machine,
3
Future CPU types may specify which vector lengths are supported.
4
to test the power management model:
4
We can apply nearly the same logic to validate those lengths
5
as we do for KVM's supported vector lengths. We merge the code
6
where we can, but unfortunately can't completely merge it because
7
KVM requires all vector lengths, power-of-two or not, smaller than
8
the maximum enabled length to also be enabled. The architecture
9
only requires all the power-of-two lengths, though, so TCG will
10
only enforce that.
5
11
6
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
12
Signed-off-by: Andrew Jones <drjones@redhat.com>
7
console: [ 0.000000] Booting Linux on physical CPU 0xf00
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
14
Message-id: 20210823160647.34028-5-drjones@redhat.com
9
console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
10
console: [ 0.000000] CPU: div instructions available: patching division code
11
console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
12
console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
13
...
14
console: Boot successful.
15
console: cat /proc/cpuinfo
16
console: / # cat /proc/cpuinfo
17
...
18
console: processor : 3
19
console: model name : ARMv7 Processor rev 5 (v7l)
20
console: BogoMIPS : 125.00
21
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
22
console: CPU implementer : 0x41
23
console: CPU architecture: 7
24
console: CPU variant : 0x0
25
console: CPU part : 0xc07
26
console: CPU revision : 5
27
console: Hardware : BCM2835
28
console: Revision : 0000
29
console: Serial : 0000000000000000
30
console: cat /proc/iomem
31
console: / # cat /proc/iomem
32
console: 00000000-3bffffff : System RAM
33
console: 00008000-00afffff : Kernel code
34
console: 00c00000-00d468ef : Kernel data
35
console: 3f006000-3f006fff : dwc_otg
36
console: 3f007000-3f007eff : /soc/dma@7e007000
37
console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
38
console: 3f100000-3f100027 : /soc/watchdog@7e100000
39
console: 3f101000-3f102fff : /soc/cprman@7e101000
40
console: 3f200000-3f2000b3 : /soc/gpio@7e200000
41
PASS (24.59 s)
42
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
43
JOB TIME : 25.02 s
44
45
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
46
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
47
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
48
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
49
---
16
---
50
tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
17
target/arm/cpu64.c | 101 ++++++++++++++++++++-------------------------
51
1 file changed, 43 insertions(+)
18
1 file changed, 45 insertions(+), 56 deletions(-)
52
19
53
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
20
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
54
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
55
--- a/tests/acceptance/boot_linux_console.py
22
--- a/target/arm/cpu64.c
56
+++ b/tests/acceptance/boot_linux_console.py
23
+++ b/target/arm/cpu64.c
57
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
58
from avocado import skip
25
break;
59
from avocado import skipUnless
26
}
60
from avocado_qemu import Test
27
}
61
+from avocado_qemu import exec_command
28
- max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
62
from avocado_qemu import exec_command_and_wait_for_pattern
29
- bitmap_andnot(cpu->sve_vq_map, cpu->sve_vq_supported,
63
from avocado_qemu import interrupt_interactive_console_until_pattern
30
- cpu->sve_vq_init, max_vq);
64
from avocado_qemu import wait_for_console_pattern
31
- if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) {
65
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
32
- error_setg(errp, "cannot disable sve%d", vq * 128);
66
"""
33
- error_append_hint(errp, "Disabling sve%d results in all "
67
self.do_test_arm_raspi2(0)
34
- "vector lengths being disabled.\n",
68
35
- vq * 128);
69
+ def test_arm_raspi2_initrd(self):
36
- error_append_hint(errp, "With SVE enabled, at least one "
70
+ """
37
- "vector length must be enabled.\n");
71
+ :avocado: tags=arch:arm
38
- return;
72
+ :avocado: tags=machine:raspi2
39
- }
73
+ """
40
} else {
74
+ deb_url = ('http://archive.raspberrypi.org/debian/'
41
/* Disabling a power-of-two disables all larger lengths. */
75
+ 'pool/main/r/raspberrypi-firmware/'
42
- if (test_bit(0, cpu->sve_vq_init)) {
76
+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')
43
- error_setg(errp, "cannot disable sve128");
77
+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
44
- error_append_hint(errp, "Disabling sve128 results in all "
78
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
45
- "vector lengths being disabled.\n");
79
+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
46
- error_append_hint(errp, "With SVE enabled, at least one "
80
+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
47
- "vector length must be enabled.\n");
48
- return;
49
- }
50
- for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
51
+ for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) {
52
if (test_bit(vq - 1, cpu->sve_vq_init)) {
53
break;
54
}
55
}
56
- max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
57
- bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
58
+ }
81
+
59
+
82
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
60
+ max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
83
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
61
+ bitmap_andnot(cpu->sve_vq_map, cpu->sve_vq_supported,
84
+ 'arm/rootfs-armv7a.cpio.gz')
62
+ cpu->sve_vq_init, max_vq);
85
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
63
+ if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) {
86
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
64
+ error_setg(errp, "cannot disable sve%d", vq * 128);
87
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
65
+ error_append_hint(errp, "Disabling sve%d results in all "
88
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
66
+ "vector lengths being disabled.\n",
89
+
67
+ vq * 128);
90
+ self.vm.set_console()
68
+ error_append_hint(errp, "With SVE enabled, at least one "
91
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
69
+ "vector length must be enabled.\n");
92
+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '
70
+ return;
93
+ 'panic=-1 noreboot ' +
71
}
94
+ 'dwc_otg.fiq_fsm_enable=0')
72
95
+ self.vm.add_args('-kernel', kernel_path,
73
max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;
96
+ '-dtb', dtb_path,
74
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
97
+ '-initrd', initrd_path,
75
assert(max_vq != 0);
98
+ '-append', kernel_command_line,
76
bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq);
99
+ '-no-reboot')
77
100
+ self.vm.launch()
78
- if (kvm_enabled()) {
101
+ self.wait_for_console_pattern('Boot successful.')
79
- /* Ensure the set of lengths matches what KVM supports. */
102
+
80
- bitmap_xor(tmp, cpu->sve_vq_map, cpu->sve_vq_supported, max_vq);
103
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
81
- if (!bitmap_empty(tmp, max_vq)) {
104
+ 'BCM2835')
82
- vq = find_last_bit(tmp, max_vq) + 1;
105
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
83
- if (test_bit(vq - 1, cpu->sve_vq_map)) {
106
+ '/soc/cprman@7e101000')
84
- if (cpu->sve_max_vq) {
107
+ exec_command(self, 'halt')
85
- error_setg(errp, "cannot set sve-max-vq=%d",
108
+ # Wait for VM to shut down gracefully
86
- cpu->sve_max_vq);
109
+ self.vm.wait()
87
- error_append_hint(errp, "This KVM host does not support "
110
+
88
- "the vector length %d-bits.\n",
111
def test_arm_exynos4210_initrd(self):
89
- vq * 128);
112
"""
90
- error_append_hint(errp, "It may not be possible to use "
113
:avocado: tags=arch:arm
91
- "sve-max-vq with this KVM host. Try "
92
- "using only sve<N> properties.\n");
93
- } else {
94
- error_setg(errp, "cannot enable sve%d", vq * 128);
95
- error_append_hint(errp, "This KVM host does not support "
96
- "the vector length %d-bits.\n",
97
- vq * 128);
98
- }
99
+ /* Ensure the set of lengths matches what is supported. */
100
+ bitmap_xor(tmp, cpu->sve_vq_map, cpu->sve_vq_supported, max_vq);
101
+ if (!bitmap_empty(tmp, max_vq)) {
102
+ vq = find_last_bit(tmp, max_vq) + 1;
103
+ if (test_bit(vq - 1, cpu->sve_vq_map)) {
104
+ if (cpu->sve_max_vq) {
105
+ error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq);
106
+ error_append_hint(errp, "This CPU does not support "
107
+ "the vector length %d-bits.\n", vq * 128);
108
+ error_append_hint(errp, "It may not be possible to use "
109
+ "sve-max-vq with this CPU. Try "
110
+ "using only sve<N> properties.\n");
111
} else {
112
+ error_setg(errp, "cannot enable sve%d", vq * 128);
113
+ error_append_hint(errp, "This CPU does not support "
114
+ "the vector length %d-bits.\n", vq * 128);
115
+ }
116
+ return;
117
+ } else {
118
+ if (kvm_enabled()) {
119
error_setg(errp, "cannot disable sve%d", vq * 128);
120
error_append_hint(errp, "The KVM host requires all "
121
"supported vector lengths smaller "
122
"than %d bits to also be enabled.\n",
123
max_vq * 128);
124
- }
125
- return;
126
- }
127
- } else {
128
- /* Ensure all required powers-of-two are enabled. */
129
- for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
130
- if (!test_bit(vq - 1, cpu->sve_vq_map)) {
131
- error_setg(errp, "cannot disable sve%d", vq * 128);
132
- error_append_hint(errp, "sve%d is required as it "
133
- "is a power-of-two length smaller than "
134
- "the maximum, sve%d\n",
135
- vq * 128, max_vq * 128);
136
return;
137
+ } else {
138
+ /* Ensure all required powers-of-two are enabled. */
139
+ for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
140
+ if (!test_bit(vq - 1, cpu->sve_vq_map)) {
141
+ error_setg(errp, "cannot disable sve%d", vq * 128);
142
+ error_append_hint(errp, "sve%d is required as it "
143
+ "is a power-of-two length smaller "
144
+ "than the maximum, sve%d\n",
145
+ vq * 128, max_vq * 128);
146
+ return;
147
+ }
148
+ }
149
}
150
}
151
}
114
--
152
--
115
2.20.1
153
2.20.1
116
154
117
155
diff view generated by jsdifflib
[PULL 21/24] target/arm: Implement MVE long shifts by immediate
[PULL 10/37] docs/specs/acpu_cpu_hotplug: Convert to rST
1
The MVE extension to v8.1M includes some new shift instructions which
1
Do a basic conversion of the acpi_cpu_hotplug spec document to rST.
2
sit entirely within the non-coprocessor part of the encoding space
3
and which operate only on general-purpose registers. They take up
4
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
5
with Rm == 13 or 15.
6
7
Implement the long shifts by immediate, which perform shifts on a
8
pair of general-purpose registers treated as a 64-bit quantity, with
9
an immediate shift count between 1 and 32.
10
11
Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
12
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
13
cases where v8.1M now requires that. (Trying to change MOVS and ORRS
14
is too difficult, because the functions that generate the code are
15
shared between a dozen different kinds of arithmetic or logical
16
instruction for all A32, T16 and T32 encodings, and for some insns
17
and some encodings Rm==13,15 are valid.)
18
19
We make the helper functions we need for UQSHLL and SQSHLL take
20
a 32-bit value which the helper casts to int8_t because we'll need
21
these helpers also for the shift-by-register insns, where the shift
22
count might be < 0 or > 32.
23
2
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
26
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
5
Message-id: 20210727170414.3368-2-peter.maydell@linaro.org
27
---
6
---
28
target/arm/helper-mve.h | 3 ++
7
docs/specs/acpi_cpu_hotplug.rst | 235 ++++++++++++++++++++++++++++++++
29
target/arm/translate.h | 1 +
8
docs/specs/acpi_cpu_hotplug.txt | 160 ----------------------
30
target/arm/t32.decode | 28 +++++++++++++
9
docs/specs/index.rst | 1 +
31
target/arm/mve_helper.c | 10 +++++
10
3 files changed, 236 insertions(+), 160 deletions(-)
32
target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++
11
create mode 100644 docs/specs/acpi_cpu_hotplug.rst
33
5 files changed, 132 insertions(+)
12
delete mode 100644 docs/specs/acpi_cpu_hotplug.txt
34
13
35
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
14
diff --git a/docs/specs/acpi_cpu_hotplug.rst b/docs/specs/acpi_cpu_hotplug.rst
15
new file mode 100644
16
index XXXXXXX..XXXXXXX
17
--- /dev/null
18
+++ b/docs/specs/acpi_cpu_hotplug.rst
19
@@ -XXX,XX +XXX,XX @@
20
+QEMU<->ACPI BIOS CPU hotplug interface
21
+======================================
22
+
23
+QEMU supports CPU hotplug via ACPI. This document
24
+describes the interface between QEMU and the ACPI BIOS.
25
+
26
+ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
27
+and hot-remove events.
28
+
29
+
30
+Legacy ACPI CPU hotplug interface registers
31
+-------------------------------------------
32
+
33
+CPU present bitmap for:
34
+
35
+- ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
36
+- PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access)
37
+- One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
38
+- The first DWORD in bitmap is used in write mode to switch from legacy
39
+ to modern CPU hotplug interface, write 0 into it to do switch.
40
+
41
+QEMU sets corresponding CPU bit on hot-add event and issues SCI
42
+with GPE.2 event set. CPU present map is read by ACPI BIOS GPE.2 handler
43
+to notify OS about CPU hot-add events. CPU hot-remove isn't supported.
44
+
45
+
46
+Modern ACPI CPU hotplug interface registers
47
+-------------------------------------------
48
+
49
+Register block base address:
50
+
51
+- ICH9-LPC IO port 0x0cd8
52
+- PIIX-PM IO port 0xaf00
53
+
54
+Register block size:
55
+
56
+- ACPI_CPU_HOTPLUG_REG_LEN = 12
57
+
58
+All accesses to registers described below, imply little-endian byte order.
59
+
60
+Reserved registers behavior:
61
+
62
+- write accesses are ignored
63
+- read accesses return all bits set to 0.
64
+
65
+The last stored value in 'CPU selector' must refer to a possible CPU, otherwise
66
+
67
+- reads from any register return 0
68
+- writes to any other register are ignored until valid value is stored into it
69
+
70
+On QEMU start, 'CPU selector' is initialized to a valid value, on reset it
71
+keeps the current value.
72
+
73
+Read access behavior
74
+^^^^^^^^^^^^^^^^^^^^
75
+
76
+offset [0x0-0x3]
77
+ Command data 2: (DWORD access)
78
+
79
+ If value last stored in 'Command field' is:
80
+
81
+ 0:
82
+ reads as 0x0
83
+ 3:
84
+ upper 32 bits of architecture specific CPU ID value
85
+ other values:
86
+ reserved
87
+
88
+offset [0x4]
89
+ CPU device status fields: (1 byte access)
90
+
91
+ bits:
92
+
93
+ 0:
94
+ Device is enabled and may be used by guest
95
+ 1:
96
+ Device insert event, used to distinguish device for which
97
+ no device check event to OSPM was issued.
98
+ It's valid only when bit 0 is set.
99
+ 2:
100
+ Device remove event, used to distinguish device for which
101
+ no device eject request to OSPM was issued. Firmware must
102
+ ignore this bit.
103
+ 3:
104
+ reserved and should be ignored by OSPM
105
+ 4:
106
+ if set to 1, OSPM requests firmware to perform device eject.
107
+ 5-7:
108
+ reserved and should be ignored by OSPM
109
+
110
+offset [0x5-0x7]
111
+ reserved
112
+
113
+offset [0x8]
114
+ Command data: (DWORD access)
115
+
116
+ If value last stored in 'Command field' is one of:
117
+
118
+ 0:
119
+ contains 'CPU selector' value of a CPU with pending event[s]
120
+ 3:
121
+ lower 32 bits of architecture specific CPU ID value
122
+ (in x86 case: APIC ID)
123
+ otherwise:
124
+ contains 0
125
+
126
+Write access behavior
127
+^^^^^^^^^^^^^^^^^^^^^
128
+
129
+offset [0x0-0x3]
130
+ CPU selector: (DWORD access)
131
+
132
+ Selects active CPU device. All following accesses to other
133
+ registers will read/store data from/to selected CPU.
134
+ Valid values: [0 .. max_cpus)
135
+
136
+offset [0x4]
137
+ CPU device control fields: (1 byte access)
138
+
139
+ bits:
140
+
141
+ 0:
142
+ reserved, OSPM must clear it before writing to register.
143
+ 1:
144
+ if set to 1 clears device insert event, set by OSPM
145
+ after it has emitted device check event for the
146
+ selected CPU device
147
+ 2:
148
+ if set to 1 clears device remove event, set by OSPM
149
+ after it has emitted device eject request for the
150
+ selected CPU device.
151
+ 3:
152
+ if set to 1 initiates device eject, set by OSPM when it
153
+ triggers CPU device removal and calls _EJ0 method or by firmware
154
+ when bit #4 is set. In case bit #4 were set, it's cleared as
155
+ part of device eject.
156
+ 4:
157
+ if set to 1, OSPM hands over device eject to firmware.
158
+ Firmware shall issue device eject request as described above
159
+ (bit #3) and OSPM should not touch device eject bit (#3) in case
160
+ it's asked firmware to perform CPU device eject.
161
+ 5-7:
162
+ reserved, OSPM must clear them before writing to register
163
+
164
+offset[0x5]
165
+ Command field: (1 byte access)
166
+
167
+ value:
168
+
169
+ 0:
170
+ selects a CPU device with inserting/removing events and
171
+ following reads from 'Command data' register return
172
+ selected CPU ('CPU selector' value).
173
+ If no CPU with events found, the current 'CPU selector' doesn't
174
+ change and corresponding insert/remove event flags are not modified.
175
+
176
+ 1:
177
+ following writes to 'Command data' register set OST event
178
+ register in QEMU
179
+ 2:
180
+ following writes to 'Command data' register set OST status
181
+ register in QEMU
182
+ 3:
183
+ following reads from 'Command data' and 'Command data 2' return
184
+ architecture specific CPU ID value for currently selected CPU.
185
+ other values:
186
+ reserved
187
+
188
+offset [0x6-0x7]
189
+ reserved
190
+
191
+offset [0x8]
192
+ Command data: (DWORD access)
193
+
194
+ If last stored 'Command field' value is:
195
+
196
+ 1:
197
+ stores value into OST event register
198
+ 2:
199
+ stores value into OST status register, triggers
200
+ ACPI_DEVICE_OST QMP event from QEMU to external applications
201
+ with current values of OST event and status registers.
202
+ other values:
203
+ reserved
204
+
205
+Typical usecases
206
+----------------
207
+
208
+(x86) Detecting and enabling modern CPU hotplug interface
209
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
210
+
211
+QEMU starts with legacy CPU hotplug interface enabled. Detecting and
212
+switching to modern interface is based on the 2 legacy CPU hotplug features:
213
+
214
+#. Writes into CPU bitmap are ignored.
215
+#. CPU bitmap always has bit #0 set, corresponding to boot CPU.
216
+
217
+Use following steps to detect and enable modern CPU hotplug interface:
218
+
219
+#. Store 0x0 to the 'CPU selector' register, attempting to switch to modern mode
220
+#. Store 0x0 to the 'CPU selector' register, to ensure valid selector value
221
+#. Store 0x0 to the 'Command field' register
222
+#. Read the 'Command data 2' register.
223
+ If read value is 0x0, the modern interface is enabled.
224
+ Otherwise legacy or no CPU hotplug interface available
225
+
226
+Get a cpu with pending event
227
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
228
+
229
+#. Store 0x0 to the 'CPU selector' register.
230
+#. Store 0x0 to the 'Command field' register.
231
+#. Read the 'CPU device status fields' register.
232
+#. If both bit #1 and bit #2 are clear in the value read, there is no CPU
233
+ with a pending event and selected CPU remains unchanged.
234
+#. Otherwise, read the 'Command data' register. The value read is the
235
+ selector of the CPU with the pending event (which is already selected).
236
+
237
+Enumerate CPUs present/non present CPUs
238
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
239
+
240
+#. Set the present CPU count to 0.
241
+#. Set the iterator to 0.
242
+#. Store 0x0 to the 'CPU selector' register, to ensure that it's in
243
+ a valid state and that access to other registers won't be ignored.
244
+#. Store 0x0 to the 'Command field' register to make 'Command data'
245
+ register return 'CPU selector' value of selected CPU
246
+#. Read the 'CPU device status fields' register.
247
+#. If bit #0 is set, increment the present CPU count.
248
+#. Increment the iterator.
249
+#. Store the iterator to the 'CPU selector' register.
250
+#. Read the 'Command data' register.
251
+#. If the value read is not zero, goto 05.
252
+#. Otherwise store 0x0 to the 'CPU selector' register, to put it
253
+ into a valid state and exit.
254
+ The iterator at this point equals "max_cpus".
255
diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.txt
256
deleted file mode 100644
257
index XXXXXXX..XXXXXXX
258
--- a/docs/specs/acpi_cpu_hotplug.txt
259
+++ /dev/null
260
@@ -XXX,XX +XXX,XX @@
261
-QEMU<->ACPI BIOS CPU hotplug interface
262
---------------------------------------
263
-
264
-QEMU supports CPU hotplug via ACPI. This document
265
-describes the interface between QEMU and the ACPI BIOS.
266
-
267
-ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
268
-and hot-remove events.
269
-
270
-============================================
271
-Legacy ACPI CPU hotplug interface registers:
272
---------------------------------------------
273
-CPU present bitmap for:
274
- ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
275
- PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access)
276
- One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
277
- The first DWORD in bitmap is used in write mode to switch from legacy
278
- to modern CPU hotplug interface, write 0 into it to do switch.
279
----------------------------------------------------------------
280
-QEMU sets corresponding CPU bit on hot-add event and issues SCI
281
-with GPE.2 event set. CPU present map is read by ACPI BIOS GPE.2 handler
282
-to notify OS about CPU hot-add events. CPU hot-remove isn't supported.
283
-
284
-=====================================
285
-Modern ACPI CPU hotplug interface registers:
286
--------------------------------------
287
-Register block base address:
288
- ICH9-LPC IO port 0x0cd8
289
- PIIX-PM IO port 0xaf00
290
-Register block size:
291
- ACPI_CPU_HOTPLUG_REG_LEN = 12
292
-
293
-All accesses to registers described below, imply little-endian byte order.
294
-
295
-Reserved resisters behavior:
296
- - write accesses are ignored
297
- - read accesses return all bits set to 0.
298
-
299
-The last stored value in 'CPU selector' must refer to a possible CPU, otherwise
300
- - reads from any register return 0
301
- - writes to any other register are ignored until valid value is stored into it
302
-On QEMU start, 'CPU selector' is initialized to a valid value, on reset it
303
-keeps the current value.
304
-
305
-read access:
306
- offset:
307
- [0x0-0x3] Command data 2: (DWORD access)
308
- if value last stored in 'Command field':
309
- 0: reads as 0x0
310
- 3: upper 32 bits of architecture specific CPU ID value
311
- other values: reserved
312
- [0x4] CPU device status fields: (1 byte access)
313
- bits:
314
- 0: Device is enabled and may be used by guest
315
- 1: Device insert event, used to distinguish device for which
316
- no device check event to OSPM was issued.
317
- It's valid only when bit 0 is set.
318
- 2: Device remove event, used to distinguish device for which
319
- no device eject request to OSPM was issued. Firmware must
320
- ignore this bit.
321
- 3: reserved and should be ignored by OSPM
322
- 4: if set to 1, OSPM requests firmware to perform device eject.
323
- 5-7: reserved and should be ignored by OSPM
324
- [0x5-0x7] reserved
325
- [0x8] Command data: (DWORD access)
326
- contains 0 unless value last stored in 'Command field' is one of:
327
- 0: contains 'CPU selector' value of a CPU with pending event[s]
328
- 3: lower 32 bits of architecture specific CPU ID value
329
- (in x86 case: APIC ID)
330
-
331
-write access:
332
- offset:
333
- [0x0-0x3] CPU selector: (DWORD access)
334
- selects active CPU device. All following accesses to other
335
- registers will read/store data from/to selected CPU.
336
- Valid values: [0 .. max_cpus)
337
- [0x4] CPU device control fields: (1 byte access)
338
- bits:
339
- 0: reserved, OSPM must clear it before writing to register.
340
- 1: if set to 1 clears device insert event, set by OSPM
341
- after it has emitted device check event for the
342
- selected CPU device
343
- 2: if set to 1 clears device remove event, set by OSPM
344
- after it has emitted device eject request for the
345
- selected CPU device.
346
- 3: if set to 1 initiates device eject, set by OSPM when it
347
- triggers CPU device removal and calls _EJ0 method or by firmware
348
- when bit #4 is set. In case bit #4 were set, it's cleared as
349
- part of device eject.
350
- 4: if set to 1, OSPM hands over device eject to firmware.
351
- Firmware shall issue device eject request as described above
352
- (bit #3) and OSPM should not touch device eject bit (#3) in case
353
- it's asked firmware to perform CPU device eject.
354
- 5-7: reserved, OSPM must clear them before writing to register
355
- [0x5] Command field: (1 byte access)
356
- value:
357
- 0: selects a CPU device with inserting/removing events and
358
- following reads from 'Command data' register return
359
- selected CPU ('CPU selector' value).
360
- If no CPU with events found, the current 'CPU selector' doesn't
361
- change and corresponding insert/remove event flags are not modified.
362
- 1: following writes to 'Command data' register set OST event
363
- register in QEMU
364
- 2: following writes to 'Command data' register set OST status
365
- register in QEMU
366
- 3: following reads from 'Command data' and 'Command data 2' return
367
- architecture specific CPU ID value for currently selected CPU.
368
- other values: reserved
369
- [0x6-0x7] reserved
370
- [0x8] Command data: (DWORD access)
371
- if last stored 'Command field' value:
372
- 1: stores value into OST event register
373
- 2: stores value into OST status register, triggers
374
- ACPI_DEVICE_OST QMP event from QEMU to external applications
375
- with current values of OST event and status registers.
376
- other values: reserved
377
-
378
-Typical usecases:
379
- - (x86) Detecting and enabling modern CPU hotplug interface.
380
- QEMU starts with legacy CPU hotplug interface enabled. Detecting and
381
- switching to modern interface is based on the 2 legacy CPU hotplug features:
382
- 1. Writes into CPU bitmap are ignored.
383
- 2. CPU bitmap always has bit#0 set, corresponding to boot CPU.
384
-
385
- Use following steps to detect and enable modern CPU hotplug interface:
386
- 1. Store 0x0 to the 'CPU selector' register,
387
- attempting to switch to modern mode
388
- 2. Store 0x0 to the 'CPU selector' register,
389
- to ensure valid selector value
390
- 3. Store 0x0 to the 'Command field' register,
391
- 4. Read the 'Command data 2' register.
392
- If read value is 0x0, the modern interface is enabled.
393
- Otherwise legacy or no CPU hotplug interface available
394
-
395
- - Get a cpu with pending event
396
- 1. Store 0x0 to the 'CPU selector' register.
397
- 2. Store 0x0 to the 'Command field' register.
398
- 3. Read the 'CPU device status fields' register.
399
- 4. If both bit#1 and bit#2 are clear in the value read, there is no CPU
400
- with a pending event and selected CPU remains unchanged.
401
- 5. Otherwise, read the 'Command data' register. The value read is the
402
- selector of the CPU with the pending event (which is already
403
- selected).
404
-
405
- - Enumerate CPUs present/non present CPUs
406
- 01. Set the present CPU count to 0.
407
- 02. Set the iterator to 0.
408
- 03. Store 0x0 to the 'CPU selector' register, to ensure that it's in
409
- a valid state and that access to other registers won't be ignored.
410
- 04. Store 0x0 to the 'Command field' register to make 'Command data'
411
- register return 'CPU selector' value of selected CPU
412
- 05. Read the 'CPU device status fields' register.
413
- 06. If bit#0 is set, increment the present CPU count.
414
- 07. Increment the iterator.
415
- 08. Store the iterator to the 'CPU selector' register.
416
- 09. Read the 'Command data' register.
417
- 10. If the value read is not zero, goto 05.
418
- 11. Otherwise store 0x0 to the 'CPU selector' register, to put it
419
- into a valid state and exit.
420
- The iterator at this point equals "max_cpus".
421
diff --git a/docs/specs/index.rst b/docs/specs/index.rst
36
index XXXXXXX..XXXXXXX 100644
422
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper-mve.h
423
--- a/docs/specs/index.rst
38
+++ b/target/arm/helper-mve.h
424
+++ b/docs/specs/index.rst
39
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
425
@@ -XXX,XX +XXX,XX @@ guest hardware that is specific to QEMU.
40
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
426
acpi_hw_reduced_hotplug
41
427
tpm
42
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
428
acpi_hest_ghes
43
+
429
+ acpi_cpu_hotplug
44
+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
45
+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
46
diff --git a/target/arm/translate.h b/target/arm/translate.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/translate.h
49
+++ b/target/arm/translate.h
50
@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
51
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
52
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
53
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
54
+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
55
56
/**
57
* arm_tbflags_from_tb:
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
61
+++ b/target/arm/t32.decode
62
@@ -XXX,XX +XXX,XX @@
63
&mcr !extern cp opc1 crn crm opc2 rt
64
&mcrr !extern cp opc1 crm rt rt2
65
66
+&mve_shl_ri rdalo rdahi shim
67
+
68
+# rdahi: bits [3:1] from insn, bit 0 is 1
69
+# rdalo: bits [3:1] from insn, bit 0 is 0
70
+%rdahi_9 9:3 !function=times_2_plus_1
71
+%rdalo_17 17:3 !function=times_2
72
+
73
# Data-processing (register)
74
75
%imm5_12_6 12:3 6:2
76
@@ -XXX,XX +XXX,XX @@
77
@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
78
&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
79
80
+@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
81
+ &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
82
+
83
{
84
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
85
AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
86
}
87
BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
88
{
89
+ # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
90
+ # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
91
+ # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
92
+ # they explicitly call unallocated_encoding() for cases that must UNDEF
93
+ # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
94
+ # the rest fall through (where ORR_rrri and MOV_rxri will end up
95
+ # handling them as r13 and r15 accesses with the same semantics as A32).
96
+ [
97
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
98
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
99
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
100
+
101
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
102
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
103
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
104
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
105
+ ]
106
+
107
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
108
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
109
}
110
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/arm/mve_helper.c
113
+++ b/target/arm/mve_helper.c
114
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
115
mve_advance_vpt(env);
116
return rdm;
117
}
118
+
119
+uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
120
+{
121
+ return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
122
+}
123
+
124
+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
+{
126
+ return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
+}
128
diff --git a/target/arm/translate.c b/target/arm/translate.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/target/arm/translate.c
131
+++ b/target/arm/translate.c
132
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
133
return true;
134
}
135
136
+/*
137
+ * v8.1M MVE wide-shifts
138
+ */
139
+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
140
+ WideShiftImmFn *fn)
141
+{
142
+ TCGv_i64 rda;
143
+ TCGv_i32 rdalo, rdahi;
144
+
145
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
146
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
147
+ return false;
148
+ }
149
+ if (a->rdahi == 15) {
150
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
151
+ return false;
152
+ }
153
+ if (!dc_isar_feature(aa32_mve, s) ||
154
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
155
+ a->rdahi == 13) {
156
+ /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
157
+ unallocated_encoding(s);
158
+ return true;
159
+ }
160
+
161
+ if (a->shim == 0) {
162
+ a->shim = 32;
163
+ }
164
+
165
+ rda = tcg_temp_new_i64();
166
+ rdalo = load_reg(s, a->rdalo);
167
+ rdahi = load_reg(s, a->rdahi);
168
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
169
+
170
+ fn(rda, rda, a->shim);
171
+
172
+ tcg_gen_extrl_i64_i32(rdalo, rda);
173
+ tcg_gen_extrh_i64_i32(rdahi, rda);
174
+ store_reg(s, a->rdalo, rdalo);
175
+ store_reg(s, a->rdahi, rdahi);
176
+ tcg_temp_free_i64(rda);
177
+
178
+ return true;
179
+}
180
+
181
+static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
182
+{
183
+ return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
184
+}
185
+
186
+static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
187
+{
188
+ return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
189
+}
190
+
191
+static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
192
+{
193
+ return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
194
+}
195
+
196
+static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
197
+{
198
+ gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
199
+}
200
+
201
+static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
202
+{
203
+ return do_mve_shl_ri(s, a, gen_mve_sqshll);
204
+}
205
+
206
+static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
207
+{
208
+ gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
209
+}
210
+
211
+static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
212
+{
213
+ return do_mve_shl_ri(s, a, gen_mve_uqshll);
214
+}
215
+
216
+static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
217
+{
218
+ return do_mve_shl_ri(s, a, gen_srshr64_i64);
219
+}
220
+
221
+static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
222
+{
223
+ return do_mve_shl_ri(s, a, gen_urshr64_i64);
224
+}
225
+
226
/*
227
* Multiply and multiply accumulate
228
*/
229
--
430
--
230
2.20.1
431
2.20.1
231
432
232
433
diff view generated by jsdifflib
[PULL 20/24] target/arm: Implement MVE VADDLV
[PULL 11/37] docs/specs/acpi_mem_hotplug: Convert to rST
1
Implement the MVE VADDLV insn; this is similar to VADDV, except
1
Convert the acpi memory hotplug spec to rST.
2
that it accumulates 32-bit elements into a 64-bit accumulator
2
3
stored in a pair of general-purpose registers.
3
Note that this includes converting a lot of weird whitespace
4
characters to plain old spaces (the rST parser does not like
5
whatever the old ones were).
4
6
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
7
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
9
Message-id: 20210727170414.3368-3-peter.maydell@linaro.org
8
---
10
---
9
target/arm/helper-mve.h | 3 ++
11
docs/specs/acpi_mem_hotplug.rst | 128 ++++++++++++++++++++++++++++++++
10
target/arm/mve.decode | 6 +++-
12
docs/specs/acpi_mem_hotplug.txt | 94 -----------------------
11
target/arm/mve_helper.c | 19 ++++++++++++
13
docs/specs/index.rst | 1 +
12
target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
14
3 files changed, 129 insertions(+), 94 deletions(-)
13
4 files changed, 90 insertions(+), 1 deletion(-)
15
create mode 100644 docs/specs/acpi_mem_hotplug.rst
14
16
delete mode 100644 docs/specs/acpi_mem_hotplug.txt
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
17
18
diff --git a/docs/specs/acpi_mem_hotplug.rst b/docs/specs/acpi_mem_hotplug.rst
19
new file mode 100644
20
index XXXXXXX..XXXXXXX
21
--- /dev/null
22
+++ b/docs/specs/acpi_mem_hotplug.rst
23
@@ -XXX,XX +XXX,XX @@
24
+QEMU<->ACPI BIOS memory hotplug interface
25
+=========================================
26
+
27
+ACPI BIOS GPE.3 handler is dedicated for notifying OS about memory hot-add
28
+and hot-remove events.
29
+
30
+Memory hot-plug interface (IO port 0xa00-0xa17, 1-4 byte access)
31
+----------------------------------------------------------------
32
+
33
+Read access behavior
34
+^^^^^^^^^^^^^^^^^^^^
35
+
36
+[0x0-0x3]
37
+ Lo part of memory device phys address
38
+[0x4-0x7]
39
+ Hi part of memory device phys address
40
+[0x8-0xb]
41
+ Lo part of memory device size in bytes
42
+[0xc-0xf]
43
+ Hi part of memory device size in bytes
44
+[0x10-0x13]
45
+ Memory device proximity domain
46
+[0x14]
47
+ Memory device status fields
48
+
49
+ bits:
50
+
51
+ 0:
52
+ Device is enabled and may be used by guest
53
+ 1:
54
+ Device insert event, used to distinguish device for which
55
+ no device check event to OSPM was issued.
56
+ It's valid only when bit 1 is set.
57
+ 2:
58
+ Device remove event, used to distinguish device for which
59
+ no device eject request to OSPM was issued.
60
+ 3-7:
61
+ reserved and should be ignored by OSPM
62
+
63
+[0x15-0x17]
64
+ reserved
65
+
66
+Write access behavior
67
+^^^^^^^^^^^^^^^^^^^^^
68
+
69
+
70
+[0x0-0x3]
71
+ Memory device slot selector, selects active memory device.
72
+ All following accesses to other registers in 0xa00-0xa17
73
+ region will read/store data from/to selected memory device.
74
+[0x4-0x7]
75
+ OST event code reported by OSPM
76
+[0x8-0xb]
77
+ OST status code reported by OSPM
78
+[0xc-0x13]
79
+ reserved, writes into it are ignored
80
+[0x14]
81
+ Memory device control fields
82
+
83
+ bits:
84
+
85
+ 0:
86
+ reserved, OSPM must clear it before writing to register.
87
+ Due to BUG in versions prior 2.4 that field isn't cleared
88
+ when other fields are written. Keep it reserved and don't
89
+ try to reuse it.
90
+ 1:
91
+ if set to 1 clears device insert event, set by OSPM
92
+ after it has emitted device check event for the
93
+ selected memory device
94
+ 2:
95
+ if set to 1 clears device remove event, set by OSPM
96
+ after it has emitted device eject request for the
97
+ selected memory device
98
+ 3:
99
+ if set to 1 initiates device eject, set by OSPM when it
100
+ triggers memory device removal and calls _EJ0 method
101
+ 4-7:
102
+ reserved, OSPM must clear them before writing to register
103
+
104
+Selecting memory device slot beyond present range has no effect on platform:
105
+
106
+- write accesses to memory hot-plug registers not documented above are ignored
107
+- read accesses to memory hot-plug registers not documented above return
108
+ all bits set to 1.
109
+
110
+Memory hot remove process diagram
111
+---------------------------------
112
+
113
+::
114
+
115
+ +-------------+ +-----------------------+ +------------------+
116
+ | 1. QEMU | | 2. QEMU | |3. QEMU |
117
+ | device_del +---->+ device unplug request +----->+Send SCI to guest,|
118
+ | | | cb | |return control to |
119
+ | | | | |management |
120
+ +-------------+ +-----------------------+ +------------------+
121
+
122
+ +---------------------------------------------------------------------+
123
+
124
+ +---------------------+ +-------------------------+
125
+ | OSPM: | remove event | OSPM: |
126
+ | send Eject Request, | | Scan memory devices |
127
+ | clear remove event +<-------------+ for event flags |
128
+ | | | |
129
+ +---------------------+ +-------------------------+
130
+ |
131
+ |
132
+ +---------v--------+ +-----------------------+
133
+ | Guest OS: | success | OSPM: |
134
+ | process Ejection +----------->+ Execute _EJ0 method, |
135
+ | request | | set eject bit in flags|
136
+ +------------------+ +-----------------------+
137
+ |failure |
138
+ v v
139
+ +------------------------+ +-----------------------+
140
+ | OSPM: | | QEMU: |
141
+ | set OST event & status | | call device unplug cb |
142
+ | fields | | |
143
+ +------------------------+ +-----------------------+
144
+ | |
145
+ v v
146
+ +------------------+ +-------------------+
147
+ |QEMU: | |QEMU: |
148
+ |Send OST QMP event| |Send device deleted|
149
+ | | |QMP event |
150
+ +------------------+ | |
151
+ +-------------------+
152
diff --git a/docs/specs/acpi_mem_hotplug.txt b/docs/specs/acpi_mem_hotplug.txt
153
deleted file mode 100644
154
index XXXXXXX..XXXXXXX
155
--- a/docs/specs/acpi_mem_hotplug.txt
156
+++ /dev/null
157
@@ -XXX,XX +XXX,XX @@
158
-QEMU<->ACPI BIOS memory hotplug interface
159
---------------------------------------
160
-
161
-ACPI BIOS GPE.3 handler is dedicated for notifying OS about memory hot-add
162
-and hot-remove events.
163
-
164
-Memory hot-plug interface (IO port 0xa00-0xa17, 1-4 byte access):
165
----------------------------------------------------------------
166
-0xa00:
167
- read access:
168
- [0x0-0x3] Lo part of memory device phys address
169
- [0x4-0x7] Hi part of memory device phys address
170
- [0x8-0xb] Lo part of memory device size in bytes
171
- [0xc-0xf] Hi part of memory device size in bytes
172
- [0x10-0x13] Memory device proximity domain
173
- [0x14] Memory device status fields
174
- bits:
175
- 0: Device is enabled and may be used by guest
176
- 1: Device insert event, used to distinguish device for which
177
- no device check event to OSPM was issued.
178
- It's valid only when bit 1 is set.
179
- 2: Device remove event, used to distinguish device for which
180
- no device eject request to OSPM was issued.
181
- 3-7: reserved and should be ignored by OSPM
182
- [0x15-0x17] reserved
183
-
184
- write access:
185
- [0x0-0x3] Memory device slot selector, selects active memory device.
186
- All following accesses to other registers in 0xa00-0xa17
187
- region will read/store data from/to selected memory device.
188
- [0x4-0x7] OST event code reported by OSPM
189
- [0x8-0xb] OST status code reported by OSPM
190
- [0xc-0x13] reserved, writes into it are ignored
191
- [0x14] Memory device control fields
192
- bits:
193
- 0: reserved, OSPM must clear it before writing to register.
194
- Due to BUG in versions prior 2.4 that field isn't cleared
195
- when other fields are written. Keep it reserved and don't
196
- try to reuse it.
197
- 1: if set to 1 clears device insert event, set by OSPM
198
- after it has emitted device check event for the
199
- selected memory device
200
- 2: if set to 1 clears device remove event, set by OSPM
201
- after it has emitted device eject request for the
202
- selected memory device
203
- 3: if set to 1 initiates device eject, set by OSPM when it
204
- triggers memory device removal and calls _EJ0 method
205
- 4-7: reserved, OSPM must clear them before writing to register
206
-
207
-Selecting memory device slot beyond present range has no effect on platform:
208
- - write accesses to memory hot-plug registers not documented above are
209
- ignored
210
- - read accesses to memory hot-plug registers not documented above return
211
- all bits set to 1.
212
-
213
-Memory hot remove process diagram:
214
-----------------------------------
215
- +-------------+     +-----------------------+      +------------------+     
216
- |  1. QEMU    |     | 2. QEMU               |      |3. QEMU           |     
217
- |  device_del +---->+ device unplug request +----->+Send SCI to guest,|     
218
- |             |     |         cb            |      |return control to |     
219
- +-------------+     +-----------------------+      |management        |     
220
-                                                    +------------------+     
221
-                                                                             
222
- +---------------------------------------------------------------------+     
223
-                                                                             
224
- +---------------------+              +-------------------------+            
225
- | OSPM:               | remove event | OSPM:                   |            
226
- | send Eject Request, |              | Scan memory devices     |            
227
- | clear remove event  +<-------------+ for event flags         |            
228
- |                     |              |                         |            
229
- +---------------------+              +-------------------------+            
230
-           |                                                                 
231
-           |                                                                 
232
- +---------v--------+            +-----------------------+                   
233
- | Guest OS:        |  success   | OSPM:                 |                   
234
- | process Ejection +----------->+ Execute _EJ0 method,  |                   
235
- | request          |            | set eject bit in flags|                   
236
- +------------------+            +-----------------------+                   
237
-           |failure                         |                                
238
-           v                                v                                
239
- +------------------------+      +-----------------------+                   
240
- | OSPM:                  |      | QEMU:                 |                   
241
- | set OST event & status |      | call device unplug cb |                   
242
- | fields                 |      |                       |                   
243
- +------------------------+      +-----------------------+                   
244
-          |                                  |                               
245
-          v                                  v                               
246
- +------------------+              +-------------------+                     
247
- |QEMU:             |              |QEMU:              |                     
248
- |Send OST QMP event|              |Send device deleted|                     
249
- |                  |              |QMP event          |                     
250
- +------------------+              |                   |                     
251
-                                   +-------------------+
252
diff --git a/docs/specs/index.rst b/docs/specs/index.rst
16
index XXXXXXX..XXXXXXX 100644
253
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-mve.h
254
--- a/docs/specs/index.rst
18
+++ b/target/arm/helper-mve.h
255
+++ b/docs/specs/index.rst
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
256
@@ -XXX,XX +XXX,XX @@ guest hardware that is specific to QEMU.
20
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
257
tpm
21
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
258
acpi_hest_ghes
22
259
acpi_cpu_hotplug
23
+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
260
+ acpi_mem_hotplug
24
+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
25
+
26
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
27
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
28
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
29
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/mve.decode
32
+++ b/target/arm/mve.decode
33
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
34
VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
35
36
# Vector add across vector
37
-VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
38
+{
39
+ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
40
+ VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
41
+ rdahi=%rdahi rdalo=%rdalo
42
+}
43
44
# Predicate operations
45
%mask_22_13 22:1 13:3
46
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/mve_helper.c
49
+++ b/target/arm/mve_helper.c
50
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
51
DO_VADDV(vaddvuh, 2, uint16_t)
52
DO_VADDV(vaddvuw, 4, uint32_t)
53
54
+#define DO_VADDLV(OP, TYPE, LTYPE) \
55
+ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
56
+ uint64_t ra) \
57
+ { \
58
+ uint16_t mask = mve_element_mask(env); \
59
+ unsigned e; \
60
+ TYPE *m = vm; \
61
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
62
+ if (mask & 1) { \
63
+ ra += (LTYPE)m[H4(e)]; \
64
+ } \
65
+ } \
66
+ mve_advance_vpt(env); \
67
+ return ra; \
68
+ } \
69
+
70
+DO_VADDLV(vaddlv_s, int32_t, int64_t)
71
+DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
72
+
73
/* Shifts by immediate */
74
#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
75
void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
76
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/translate-mve.c
79
+++ b/target/arm/translate-mve.c
80
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
81
return true;
82
}
83
84
+static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
85
+{
86
+ /*
87
+ * Vector Add Long Across Vector: accumulate the 32-bit
88
+ * elements of the vector into a 64-bit result stored in
89
+ * a pair of general-purpose registers.
90
+ * No need to check Qm's bank: it is only 3 bits in decode.
91
+ */
92
+ TCGv_ptr qm;
93
+ TCGv_i64 rda;
94
+ TCGv_i32 rdalo, rdahi;
95
+
96
+ if (!dc_isar_feature(aa32_mve, s)) {
97
+ return false;
98
+ }
99
+ /*
100
+ * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
101
+ * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
102
+ */
103
+ if (a->rdahi == 13 || a->rdahi == 15) {
104
+ return false;
105
+ }
106
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
107
+ return true;
108
+ }
109
+
110
+ /*
111
+ * This insn is subject to beat-wise execution. Partial execution
112
+ * of an A=0 (no-accumulate) insn which does not execute the first
113
+ * beat must start with the current value of RdaHi:RdaLo, not zero.
114
+ */
115
+ if (a->a || mve_skip_first_beat(s)) {
116
+ /* Accumulate input from RdaHi:RdaLo */
117
+ rda = tcg_temp_new_i64();
118
+ rdalo = load_reg(s, a->rdalo);
119
+ rdahi = load_reg(s, a->rdahi);
120
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
121
+ tcg_temp_free_i32(rdalo);
122
+ tcg_temp_free_i32(rdahi);
123
+ } else {
124
+ /* Accumulate starting at zero */
125
+ rda = tcg_const_i64(0);
126
+ }
127
+
128
+ qm = mve_qreg_ptr(a->qm);
129
+ if (a->u) {
130
+ gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
131
+ } else {
132
+ gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
133
+ }
134
+ tcg_temp_free_ptr(qm);
135
+
136
+ rdalo = tcg_temp_new_i32();
137
+ rdahi = tcg_temp_new_i32();
138
+ tcg_gen_extrl_i64_i32(rdalo, rda);
139
+ tcg_gen_extrh_i64_i32(rdahi, rda);
140
+ store_reg(s, a->rdalo, rdalo);
141
+ store_reg(s, a->rdahi, rdahi);
142
+ tcg_temp_free_i64(rda);
143
+ mve_update_eci(s);
144
+ return true;
145
+}
146
+
147
static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
148
{
149
TCGv_ptr qd;
150
--
261
--
151
2.20.1
262
2.20.1
152
263
153
264
diff view generated by jsdifflib
[PULL 19/24] target/arm: Implement MVE VSHLC
[PULL 12/37] docs/specs/acpi_pci_hotplug: Convert to rST
1
Implement the MVE VSHLC insn, which performs a shift left of the
1
Convert the PCI hotplug spec document to rST.
2
entire vector with carry in bits provided from a general purpose
3
register and carry out bits written back to that register.
4
2
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
7
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
8
---
5
---
9
target/arm/helper-mve.h | 2 ++
6
...i_pci_hotplug.txt => acpi_pci_hotplug.rst} | 37 ++++++++++---------
10
target/arm/mve.decode | 2 ++
7
docs/specs/index.rst | 1 +
11
target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++
8
2 files changed, 21 insertions(+), 17 deletions(-)
12
target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
9
rename docs/specs/{acpi_pci_hotplug.txt => acpi_pci_hotplug.rst} (51%)
13
4 files changed, 72 insertions(+)
14
10
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
11
diff --git a/docs/specs/acpi_pci_hotplug.txt b/docs/specs/acpi_pci_hotplug.rst
12
similarity index 51%
13
rename from docs/specs/acpi_pci_hotplug.txt
14
rename to docs/specs/acpi_pci_hotplug.rst
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-mve.h
16
--- a/docs/specs/acpi_pci_hotplug.txt
18
+++ b/target/arm/helper-mve.h
17
+++ b/docs/specs/acpi_pci_hotplug.rst
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
18
@@ -XXX,XX +XXX,XX @@
20
DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
QEMU<->ACPI BIOS PCI hotplug interface
21
DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
---------------------------------------
22
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
+======================================
22
23
QEMU supports PCI hotplug via ACPI, for PCI bus 0. This document
24
describes the interface between QEMU and the ACPI BIOS.
25
26
-ACPI GPE block (IO ports 0xafe0-0xafe3, byte access):
27
------------------------------------------
28
+ACPI GPE block (IO ports 0xafe0-0xafe3, byte access)
29
+----------------------------------------------------
30
31
Generic ACPI GPE block. Bit 1 (GPE.1) used to notify PCI hotplug/eject
32
event to ACPI BIOS, via SCI interrupt.
33
34
-PCI slot injection notification pending (IO port 0xae00-0xae03, 4-byte access):
35
----------------------------------------------------------------
36
+PCI slot injection notification pending (IO port 0xae00-0xae03, 4-byte access)
37
+------------------------------------------------------------------------------
23
+
38
+
24
+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
39
Slot injection notification pending. One bit per slot.
25
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
40
41
Read by ACPI BIOS GPE.1 handler to notify OS of injection
42
events. Read-only.
43
44
-PCI slot removal notification (IO port 0xae04-0xae07, 4-byte access):
45
------------------------------------------------------
46
+PCI slot removal notification (IO port 0xae04-0xae07, 4-byte access)
47
+--------------------------------------------------------------------
48
+
49
Slot removal notification pending. One bit per slot.
50
51
Read by ACPI BIOS GPE.1 handler to notify OS of removal
52
events. Read-only.
53
54
-PCI device eject (IO port 0xae08-0xae0b, 4-byte access):
55
-----------------------------------------
56
+PCI device eject (IO port 0xae08-0xae0b, 4-byte access)
57
+-------------------------------------------------------
58
59
Write: Used by ACPI BIOS _EJ0 method to request device removal.
60
One bit per slot.
61
62
Read: Hotplug features register. Used by platform to identify features
63
available. Current base feature set (no bits set):
64
- - Read-only "up" register @0xae00, 4-byte access, bit per slot
65
- - Read-only "down" register @0xae04, 4-byte access, bit per slot
66
- - Read/write "eject" register @0xae08, 4-byte access,
67
- write: bit per slot eject, read: hotplug feature set
68
- - Read-only hotplug capable register @0xae0c, 4-byte access, bit per slot
69
70
-PCI removability status (IO port 0xae0c-0xae0f, 4-byte access):
71
------------------------------------------------
72
+- Read-only "up" register @0xae00, 4-byte access, bit per slot
73
+- Read-only "down" register @0xae04, 4-byte access, bit per slot
74
+- Read/write "eject" register @0xae08, 4-byte access,
75
+ write: bit per slot eject, read: hotplug feature set
76
+- Read-only hotplug capable register @0xae0c, 4-byte access, bit per slot
77
+
78
+PCI removability status (IO port 0xae0c-0xae0f, 4-byte access)
79
+--------------------------------------------------------------
80
81
Used by ACPI BIOS _RMV method to indicate removability status to OS. One
82
-bit per slot. Read-only
83
+bit per slot. Read-only.
84
diff --git a/docs/specs/index.rst b/docs/specs/index.rst
26
index XXXXXXX..XXXXXXX 100644
85
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/mve.decode
86
--- a/docs/specs/index.rst
28
+++ b/target/arm/mve.decode
87
+++ b/docs/specs/index.rst
29
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
88
@@ -XXX,XX +XXX,XX @@ guest hardware that is specific to QEMU.
30
VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
89
acpi_hest_ghes
31
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
90
acpi_cpu_hotplug
32
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
91
acpi_mem_hotplug
33
+
92
+ acpi_pci_hotplug
34
+VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
35
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/mve_helper.c
38
+++ b/target/arm/mve_helper.c
39
@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
40
DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
41
DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
42
DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
43
+
44
+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
45
+ uint32_t shift)
46
+{
47
+ uint32_t *d = vd;
48
+ uint16_t mask = mve_element_mask(env);
49
+ unsigned e;
50
+ uint32_t r;
51
+
52
+ /*
53
+ * For each 32-bit element, we shift it left, bringing in the
54
+ * low 'shift' bits of rdm at the bottom. Bits shifted out at
55
+ * the top become the new rdm, if the predicate mask permits.
56
+ * The final rdm value is returned to update the register.
57
+ * shift == 0 here means "shift by 32 bits".
58
+ */
59
+ if (shift == 0) {
60
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
61
+ r = rdm;
62
+ if (mask & 1) {
63
+ rdm = d[H4(e)];
64
+ }
65
+ mergemask(&d[H4(e)], r, mask);
66
+ }
67
+ } else {
68
+ uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
69
+
70
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
71
+ r = (d[H4(e)] << shift) | (rdm & shiftmask);
72
+ if (mask & 1) {
73
+ rdm = d[H4(e)] >> (32 - shift);
74
+ }
75
+ mergemask(&d[H4(e)], r, mask);
76
+ }
77
+ }
78
+ mve_advance_vpt(env);
79
+ return rdm;
80
+}
81
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/translate-mve.c
84
+++ b/target/arm/translate-mve.c
85
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
86
DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
87
DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
88
DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
89
+
90
+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
91
+{
92
+ /*
93
+ * Whole Vector Left Shift with Carry. The carry is taken
94
+ * from a general purpose register and written back there.
95
+ * An imm of 0 means "shift by 32".
96
+ */
97
+ TCGv_ptr qd;
98
+ TCGv_i32 rdm;
99
+
100
+ if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
101
+ return false;
102
+ }
103
+ if (a->rdm == 13 || a->rdm == 15) {
104
+ /* CONSTRAINED UNPREDICTABLE: we UNDEF */
105
+ return false;
106
+ }
107
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
108
+ return true;
109
+ }
110
+
111
+ qd = mve_qreg_ptr(a->qd);
112
+ rdm = load_reg(s, a->rdm);
113
+ gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
114
+ store_reg(s, a->rdm, rdm);
115
+ tcg_temp_free_ptr(qd);
116
+ mve_update_eci(s);
117
+ return true;
118
+}
119
--
93
--
120
2.20.1
94
2.20.1
121
95
122
96
diff view generated by jsdifflib
[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
[PULL 13/37] docs/specs/acpi_nvdimm: Convert to rST
1
Implement the MVE saturating shift-right-and-narrow insns
1
Convert the ACPI NVDIMM spec document to rST.
2
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
3
4
do_srshr() is borrowed from sve_helper.c.
5
2
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
8
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
5
Message-id: 20210727170414.3368-5-peter.maydell@linaro.org
9
---
6
---
10
target/arm/helper-mve.h | 30 +++++++++++
7
docs/specs/acpi_nvdimm.rst | 228 +++++++++++++++++++++++++++++++++++++
11
target/arm/mve.decode | 28 ++++++++++
8
docs/specs/acpi_nvdimm.txt | 188 ------------------------------
12
target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++
9
docs/specs/index.rst | 1 +
13
target/arm/translate-mve.c | 12 +++++
10
3 files changed, 229 insertions(+), 188 deletions(-)
14
4 files changed, 174 insertions(+)
11
create mode 100644 docs/specs/acpi_nvdimm.rst
12
delete mode 100644 docs/specs/acpi_nvdimm.txt
15
13
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
14
diff --git a/docs/specs/acpi_nvdimm.rst b/docs/specs/acpi_nvdimm.rst
15
new file mode 100644
16
index XXXXXXX..XXXXXXX
17
--- /dev/null
18
+++ b/docs/specs/acpi_nvdimm.rst
19
@@ -XXX,XX +XXX,XX @@
20
+QEMU<->ACPI BIOS NVDIMM interface
21
+=================================
22
+
23
+QEMU supports NVDIMM via ACPI. This document describes the basic concepts of
24
+NVDIMM ACPI and the interface between QEMU and the ACPI BIOS.
25
+
26
+NVDIMM ACPI Background
27
+----------------------
28
+
29
+NVDIMM is introduced in ACPI 6.0 which defines an NVDIMM root device under
30
+_SB scope with a _HID of "ACPI0012". For each NVDIMM present or intended
31
+to be supported by platform, platform firmware also exposes an ACPI
32
+Namespace Device under the root device.
33
+
34
+The NVDIMM child devices under the NVDIMM root device are defined with _ADR
35
+corresponding to the NFIT device handle. The NVDIMM root device and the
36
+NVDIMM devices can have device specific methods (_DSM) to provide additional
37
+functions specific to a particular NVDIMM implementation.
38
+
39
+This is an example from ACPI 6.0, a platform contains one NVDIMM::
40
+
41
+ Scope (\_SB){
42
+ Device (NVDR) // Root device
43
+ {
44
+ Name (_HID, "ACPI0012")
45
+ Method (_STA) {...}
46
+ Method (_FIT) {...}
47
+ Method (_DSM, ...) {...}
48
+ Device (NVD)
49
+ {
50
+ Name(_ADR, h) //where h is NFIT Device Handle for this NVDIMM
51
+ Method (_DSM, ...) {...}
52
+ }
53
+ }
54
+ }
55
+
56
+Methods supported on both NVDIMM root device and NVDIMM device
57
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
58
+
59
+_DSM (Device Specific Method)
60
+ It is a control method that enables devices to provide device specific
61
+ control functions that are consumed by the device driver.
62
+ The NVDIMM DSM specification can be found at
63
+ http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf
64
+
65
+ Arguments:
66
+
67
+ Arg0
68
+ A Buffer containing a UUID (16 Bytes)
69
+ Arg1
70
+ An Integer containing the Revision ID (4 Bytes)
71
+ Arg2
72
+ An Integer containing the Function Index (4 Bytes)
73
+ Arg3
74
+ A package containing parameters for the function specified by the
75
+ UUID, Revision ID, and Function Index
76
+
77
+ Return Value:
78
+
79
+ If Function Index = 0, a Buffer containing a function index bitfield.
80
+ Otherwise, the return value and type depends on the UUID, revision ID
81
+ and function index which are described in the DSM specification.
82
+
83
+Methods on NVDIMM ROOT Device
84
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
85
+
86
+_FIT(Firmware Interface Table)
87
+ It evaluates to a buffer returning data in the format of a series of NFIT
88
+ Type Structure.
89
+
90
+ Arguments: None
91
+
92
+ Return Value:
93
+ A Buffer containing a list of NFIT Type structure entries.
94
+
95
+ The detailed definition of the structure can be found at ACPI 6.0: 5.2.25
96
+ NVDIMM Firmware Interface Table (NFIT).
97
+
98
+QEMU NVDIMM Implementation
99
+--------------------------
100
+
101
+QEMU uses 4 bytes IO Port starting from 0x0a18 and a RAM-based memory page
102
+for NVDIMM ACPI.
103
+
104
+Memory:
105
+ QEMU uses BIOS Linker/loader feature to ask BIOS to allocate a memory
106
+ page and dynamically patch its address into an int32 object named "MEMA"
107
+ in ACPI.
108
+
109
+ This page is RAM-based and it is used to transfer data between _DSM
110
+ method and QEMU. If ACPI has control, this pages is owned by ACPI which
111
+ writes _DSM input data to it, otherwise, it is owned by QEMU which
112
+ emulates _DSM access and writes the output data to it.
113
+
114
+ ACPI writes _DSM Input Data (based on the offset in the page):
115
+
116
+ [0x0 - 0x3]
117
+ 4 bytes, NVDIMM Device Handle.
118
+
119
+ The handle is completely QEMU internal thing, the values in
120
+ range [1, 0xFFFF] indicate nvdimm device. Other values are
121
+ reserved for other purposes.
122
+
123
+ Reserved handles:
124
+
125
+ - 0 is reserved for nvdimm root device named NVDR.
126
+ - 0x10000 is reserved for QEMU internal DSM function called on
127
+ the root device.
128
+
129
+ [0x4 - 0x7]
130
+ 4 bytes, Revision ID, that is the Arg1 of _DSM method.
131
+
132
+ [0x8 - 0xB]
133
+ 4 bytes. Function Index, that is the Arg2 of _DSM method.
134
+
135
+ [0xC - 0xFFF]
136
+ 4084 bytes, the Arg3 of _DSM method.
137
+
138
+ QEMU writes Output Data (based on the offset in the page):
139
+
140
+ [0x0 - 0x3]
141
+ 4 bytes, the length of result
142
+
143
+ [0x4 - 0xFFF]
144
+ 4092 bytes, the DSM result filled by QEMU
145
+
146
+IO Port 0x0a18 - 0xa1b:
147
+ ACPI writes the address of the memory page allocated by BIOS to this
148
+ port then QEMU gets the control and fills the result in the memory page.
149
+
150
+ Write Access:
151
+
152
+ [0x0a18 - 0xa1b]
153
+ 4 bytes, the address of the memory page allocated by BIOS.
154
+
155
+_DSM process diagram
156
+--------------------
157
+
158
+"MEMA" indicates the address of memory page allocated by BIOS.
159
+
160
+::
161
+
162
+ +----------------------+ +-----------------------+
163
+ | 1. OSPM | | 2. OSPM |
164
+ | save _DSM input data | | write "MEMA" to | Exit to QEMU
165
+ | to the page +----->| IO port 0x0a18 +------------+
166
+ | indicated by "MEMA" | | | |
167
+ +----------------------+ +-----------------------+ |
168
+ |
169
+ v
170
+ +--------------------+ +-----------+ +------------------+--------+
171
+ | 5 QEMU | | 4 QEMU | | 3. QEMU |
172
+ | write _DSM result | | emulate | | get _DSM input data from |
173
+ | to the page +<------+ _DSM +<-----+ the page indicated by the |
174
+ | | | | | value from the IO port |
175
+ +--------+-----------+ +-----------+ +---------------------------+
176
+ |
177
+ | Enter Guest
178
+ |
179
+ v
180
+ +--------------------------+ +--------------+
181
+ | 6 OSPM | | 7 OSPM |
182
+ | result size is returned | | _DSM return |
183
+ | by reading DSM +----->+ |
184
+ | result from the page | | |
185
+ +--------------------------+ +--------------+
186
+
187
+NVDIMM hotplug
188
+--------------
189
+
190
+ACPI BIOS GPE.4 handler is dedicated for notifying OS about nvdimm device
191
+hot-add event.
192
+
193
+QEMU internal use only _DSM functions
194
+-------------------------------------
195
+
196
+Read FIT
197
+^^^^^^^^
198
+
199
+_FIT method uses _DSM method to fetch NFIT structures blob from QEMU
200
+in 1 page sized increments which are then concatenated and returned
201
+as _FIT method result.
202
+
203
+Input parameters:
204
+
205
+Arg0
206
+ UUID {set to 648B9CF2-CDA1-4312-8AD9-49C4AF32BD62}
207
+Arg1
208
+ Revision ID (set to 1)
209
+Arg2
210
+ Function Index, 0x1
211
+Arg3
212
+ A package containing a buffer whose layout is as follows:
213
+
214
+ +----------+--------+--------+-------------------------------------------+
215
+ | Field | Length | Offset | Description |
216
+ +----------+--------+--------+-------------------------------------------+
217
+ | offset | 4 | 0 | offset in QEMU's NFIT structures blob to |
218
+ | | | | read from |
219
+ +----------+--------+--------+-------------------------------------------+
220
+
221
+Output layout in the dsm memory page:
222
+
223
+ +----------+--------+--------+-------------------------------------------+
224
+ | Field | Length | Offset | Description |
225
+ +----------+--------+--------+-------------------------------------------+
226
+ | length | 4 | 0 | length of entire returned data |
227
+ | | | | (including this header) |
228
+ +----------+--------+--------+-------------------------------------------+
229
+ | | | | return status codes |
230
+ | | | | |
231
+ | | | | - 0x0 - success |
232
+ | | | | - 0x100 - error caused by NFIT update |
233
+ | status | 4 | 4 | while read by _FIT wasn't completed |
234
+ | | | | - other codes follow Chapter 3 in |
235
+ | | | | DSM Spec Rev1 |
236
+ +----------+--------+--------+-------------------------------------------+
237
+ | fit data | Varies | 8 | contains FIT data. This field is present |
238
+ | | | | if status field is 0. |
239
+ +----------+--------+--------+-------------------------------------------+
240
+
241
+The FIT offset is maintained by the OSPM itself, current offset plus
242
+the size of the fit data returned by the function is the next offset
243
+OSPM should read. When all FIT data has been read out, zero fit data
244
+size is returned.
245
+
246
+If it returns status code 0x100, OSPM should restart to read FIT (read
247
+from offset 0 again).
248
diff --git a/docs/specs/acpi_nvdimm.txt b/docs/specs/acpi_nvdimm.txt
249
deleted file mode 100644
250
index XXXXXXX..XXXXXXX
251
--- a/docs/specs/acpi_nvdimm.txt
252
+++ /dev/null
253
@@ -XXX,XX +XXX,XX @@
254
-QEMU<->ACPI BIOS NVDIMM interface
255
----------------------------------
256
-
257
-QEMU supports NVDIMM via ACPI. This document describes the basic concepts of
258
-NVDIMM ACPI and the interface between QEMU and the ACPI BIOS.
259
-
260
-NVDIMM ACPI Background
261
-----------------------
262
-NVDIMM is introduced in ACPI 6.0 which defines an NVDIMM root device under
263
-_SB scope with a _HID of “ACPI0012”. For each NVDIMM present or intended
264
-to be supported by platform, platform firmware also exposes an ACPI
265
-Namespace Device under the root device.
266
-
267
-The NVDIMM child devices under the NVDIMM root device are defined with _ADR
268
-corresponding to the NFIT device handle. The NVDIMM root device and the
269
-NVDIMM devices can have device specific methods (_DSM) to provide additional
270
-functions specific to a particular NVDIMM implementation.
271
-
272
-This is an example from ACPI 6.0, a platform contains one NVDIMM:
273
-
274
-Scope (\_SB){
275
- Device (NVDR) // Root device
276
- {
277
- Name (_HID, “ACPI0012”)
278
- Method (_STA) {...}
279
- Method (_FIT) {...}
280
- Method (_DSM, ...) {...}
281
- Device (NVD)
282
- {
283
- Name(_ADR, h) //where h is NFIT Device Handle for this NVDIMM
284
- Method (_DSM, ...) {...}
285
- }
286
- }
287
-}
288
-
289
-Method supported on both NVDIMM root device and NVDIMM device
290
-_DSM (Device Specific Method)
291
- It is a control method that enables devices to provide device specific
292
- control functions that are consumed by the device driver.
293
- The NVDIMM DSM specification can be found at:
294
- http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf
295
-
296
- Arguments:
297
- Arg0 – A Buffer containing a UUID (16 Bytes)
298
- Arg1 – An Integer containing the Revision ID (4 Bytes)
299
- Arg2 – An Integer containing the Function Index (4 Bytes)
300
- Arg3 – A package containing parameters for the function specified by the
301
- UUID, Revision ID, and Function Index
302
-
303
- Return Value:
304
- If Function Index = 0, a Buffer containing a function index bitfield.
305
- Otherwise, the return value and type depends on the UUID, revision ID
306
- and function index which are described in the DSM specification.
307
-
308
-Methods on NVDIMM ROOT Device
309
-_FIT(Firmware Interface Table)
310
- It evaluates to a buffer returning data in the format of a series of NFIT
311
- Type Structure.
312
-
313
- Arguments: None
314
-
315
- Return Value:
316
- A Buffer containing a list of NFIT Type structure entries.
317
-
318
- The detailed definition of the structure can be found at ACPI 6.0: 5.2.25
319
- NVDIMM Firmware Interface Table (NFIT).
320
-
321
-QEMU NVDIMM Implementation
322
-==========================
323
-QEMU uses 4 bytes IO Port starting from 0x0a18 and a RAM-based memory page
324
-for NVDIMM ACPI.
325
-
326
-Memory:
327
- QEMU uses BIOS Linker/loader feature to ask BIOS to allocate a memory
328
- page and dynamically patch its address into an int32 object named "MEMA"
329
- in ACPI.
330
-
331
- This page is RAM-based and it is used to transfer data between _DSM
332
- method and QEMU. If ACPI has control, this pages is owned by ACPI which
333
- writes _DSM input data to it, otherwise, it is owned by QEMU which
334
- emulates _DSM access and writes the output data to it.
335
-
336
- ACPI writes _DSM Input Data (based on the offset in the page):
337
- [0x0 - 0x3]: 4 bytes, NVDIMM Device Handle.
338
-
339
- The handle is completely QEMU internal thing, the values in
340
- range [1, 0xFFFF] indicate nvdimm device. Other values are
341
- reserved for other purposes.
342
-
343
- Reserved handles:
344
- 0 is reserved for nvdimm root device named NVDR.
345
- 0x10000 is reserved for QEMU internal DSM function called on
346
- the root device.
347
-
348
- [0x4 - 0x7]: 4 bytes, Revision ID, that is the Arg1 of _DSM method.
349
- [0x8 - 0xB]: 4 bytes. Function Index, that is the Arg2 of _DSM method.
350
- [0xC - 0xFFF]: 4084 bytes, the Arg3 of _DSM method.
351
-
352
- QEMU Writes Output Data (based on the offset in the page):
353
- [0x0 - 0x3]: 4 bytes, the length of result
354
- [0x4 - 0xFFF]: 4092 bytes, the DSM result filled by QEMU
355
-
356
-IO Port 0x0a18 - 0xa1b:
357
- ACPI writes the address of the memory page allocated by BIOS to this
358
- port then QEMU gets the control and fills the result in the memory page.
359
-
360
- write Access:
361
- [0x0a18 - 0xa1b]: 4 bytes, the address of the memory page allocated
362
- by BIOS.
363
-
364
-_DSM process diagram:
365
----------------------
366
-"MEMA" indicates the address of memory page allocated by BIOS.
367
-
368
- +----------------------+   +-----------------------+
369
- |   1. OSPM   |      | 2. OSPM |
370
- | save _DSM input data | | write "MEMA" to | Exit to QEMU
371
- | to the page +----->| IO port 0x0a18 +------------+
372
- | indicated by "MEMA" | | | |
373
- +----------------------+ +-----------------------+ |
374
-  |
375
-  v
376
- +------------- ----+ +-----------+ +------------------+--------+
377
- | 5 QEMU | | 4 QEMU | | 3. QEMU |
378
- | write _DSM result | | emulate | | get _DSM input data from |
379
- | to the page +<------+ _DSM +<-----+ the page indicated by the |
380
- | | | | | value from the IO port |
381
- +--------+-----------+ +-----------+ +---------------------------+
382
- |
383
- | Enter Guest
384
- |
385
- v
386
- +--------------------------+ +--------------+
387
- | 6 OSPM | | 7 OSPM |
388
- | result size is returned | | _DSM return |
389
- | by reading DSM +----->+ |
390
- | result from the page | | |
391
- +--------------------------+ +--------------+
392
-
393
-NVDIMM hotplug
394
---------------
395
-ACPI BIOS GPE.4 handler is dedicated for notifying OS about nvdimm device
396
-hot-add event.
397
-
398
-QEMU internal use only _DSM function
399
-------------------------------------
400
-1) Read FIT
401
- _FIT method uses _DSM method to fetch NFIT structures blob from QEMU
402
- in 1 page sized increments which are then concatenated and returned
403
- as _FIT method result.
404
-
405
- Input parameters:
406
- Arg0 – UUID {set to 648B9CF2-CDA1-4312-8AD9-49C4AF32BD62}
407
- Arg1 – Revision ID (set to 1)
408
- Arg2 - Function Index, 0x1
409
- Arg3 - A package containing a buffer whose layout is as follows:
410
-
411
- +----------+--------+--------+-------------------------------------------+
412
- | Field | Length | Offset | Description |
413
- +----------+--------+--------+-------------------------------------------+
414
- | offset | 4 | 0 | offset in QEMU's NFIT structures blob to |
415
- | | | | read from |
416
- +----------+--------+--------+-------------------------------------------+
417
-
418
- Output layout in the dsm memory page:
419
- +----------+--------+--------+-------------------------------------------+
420
- | Field | Length | Offset | Description |
421
- +----------+--------+--------+-------------------------------------------+
422
- | length | 4 | 0 | length of entire returned data |
423
- | | | | (including this header) |
424
- +----------+-----------------+-------------------------------------------+
425
- | | | | return status codes |
426
- | | | | 0x0 - success |
427
- | | | | 0x100 - error caused by NFIT update while |
428
- | status | 4 | 4 | read by _FIT wasn't completed, other |
429
- | | | | codes follow Chapter 3 in DSM Spec Rev1 |
430
- +----------+-----------------+-------------------------------------------+
431
- | fit data | Varies | 8 | contains FIT data, this field is present |
432
- | | | | if status field is 0; |
433
- +----------+--------+--------+-------------------------------------------+
434
-
435
- The FIT offset is maintained by the OSPM itself, current offset plus
436
- the size of the fit data returned by the function is the next offset
437
- OSPM should read. When all FIT data has been read out, zero fit data
438
- size is returned.
439
-
440
- If it returns status code 0x100, OSPM should restart to read FIT (read
441
- from offset 0 again).
442
diff --git a/docs/specs/index.rst b/docs/specs/index.rst
17
index XXXXXXX..XXXXXXX 100644
443
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-mve.h
444
--- a/docs/specs/index.rst
19
+++ b/target/arm/helper-mve.h
445
+++ b/docs/specs/index.rst
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
446
@@ -XXX,XX +XXX,XX @@ guest hardware that is specific to QEMU.
21
DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
447
acpi_cpu_hotplug
22
DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
448
acpi_mem_hotplug
23
DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
449
acpi_pci_hotplug
24
+
450
+ acpi_nvdimm
25
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
+
35
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+
40
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+
45
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
46
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
+
50
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
53
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
54
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/mve.decode
57
+++ b/target/arm/mve.decode
58
@@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
59
VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
60
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
61
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
62
+
63
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
64
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
65
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
66
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
67
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
68
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
69
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
70
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
71
+
72
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
73
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
74
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
75
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
76
+
77
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
78
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
79
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
80
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
81
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
82
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
83
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
84
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
85
+
86
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
87
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
88
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
89
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
90
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/mve_helper.c
93
+++ b/target/arm/mve_helper.c
94
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
95
}
96
}
97
98
+static inline int64_t do_srshr(int64_t x, unsigned sh)
99
+{
100
+ if (likely(sh < 64)) {
101
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
102
+ } else {
103
+ /* Rounding the sign bit always produces 0. */
104
+ return 0;
105
+ }
106
+}
107
+
108
DO_VSHRN_ALL(vshrn, DO_SHR)
109
DO_VSHRN_ALL(vrshrn, do_urshr)
110
+
111
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
112
+ bool *satp)
113
+{
114
+ if (val > max) {
115
+ *satp = true;
116
+ return max;
117
+ } else if (val < min) {
118
+ *satp = true;
119
+ return min;
120
+ } else {
121
+ return val;
122
+ }
123
+}
124
+
125
+/* Saturating narrowing right shifts */
126
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
127
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
128
+ void *vm, uint32_t shift) \
129
+ { \
130
+ LTYPE *m = vm; \
131
+ TYPE *d = vd; \
132
+ uint16_t mask = mve_element_mask(env); \
133
+ bool qc = false; \
134
+ unsigned le; \
135
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
136
+ bool sat = false; \
137
+ TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \
138
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
139
+ qc |= sat && (mask & 1 << (TOP * ESIZE)); \
140
+ } \
141
+ if (qc) { \
142
+ env->vfp.qc[0] = qc; \
143
+ } \
144
+ mve_advance_vpt(env); \
145
+ }
146
+
147
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \
148
+ DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \
149
+ DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
150
+
151
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \
152
+ DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \
153
+ DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
154
+
155
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \
156
+ DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \
157
+ DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
158
+
159
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \
160
+ DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \
161
+ DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
162
+
163
+#define DO_SHRN_SB(N, M, SATP) \
164
+ do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
165
+#define DO_SHRN_UB(N, M, SATP) \
166
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
167
+#define DO_SHRUN_B(N, M, SATP) \
168
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
169
+
170
+#define DO_SHRN_SH(N, M, SATP) \
171
+ do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
172
+#define DO_SHRN_UH(N, M, SATP) \
173
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
174
+#define DO_SHRUN_H(N, M, SATP) \
175
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
176
+
177
+#define DO_RSHRN_SB(N, M, SATP) \
178
+ do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
179
+#define DO_RSHRN_UB(N, M, SATP) \
180
+ do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
181
+#define DO_RSHRUN_B(N, M, SATP) \
182
+ do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
183
+
184
+#define DO_RSHRN_SH(N, M, SATP) \
185
+ do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
186
+#define DO_RSHRN_UH(N, M, SATP) \
187
+ do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
188
+#define DO_RSHRUN_H(N, M, SATP) \
189
+ do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
190
+
191
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
192
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
193
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
194
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
195
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
196
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
197
+
198
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
199
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
200
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
201
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
202
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
203
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
204
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
205
index XXXXXXX..XXXXXXX 100644
206
--- a/target/arm/translate-mve.c
207
+++ b/target/arm/translate-mve.c
208
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
209
DO_2SHIFT_N(VSHRNT, vshrnt)
210
DO_2SHIFT_N(VRSHRNB, vrshrnb)
211
DO_2SHIFT_N(VRSHRNT, vrshrnt)
212
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
213
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
214
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
215
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
216
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
217
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
218
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
219
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
220
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
221
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
222
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
223
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
224
--
451
--
225
2.20.1
452
2.20.1
226
453
227
454
diff view generated by jsdifflib
New patch
[PULL 14/37] MAINTAINERS: Add ACPI specs documents to ACPI and NVDIMM sections
1
Add entries for the ACPI specs documents in docs/specs to
2
appropriate sections of MAINTAINERS.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
6
Message-id: 20210727170414.3368-6-peter.maydell@linaro.org
7
---
8
MAINTAINERS | 5 +++++
9
1 file changed, 5 insertions(+)
10
11
diff --git a/MAINTAINERS b/MAINTAINERS
12
index XXXXXXX..XXXXXXX 100644
13
--- a/MAINTAINERS
14
+++ b/MAINTAINERS
15
@@ -XXX,XX +XXX,XX @@ F: qapi/acpi.json
16
F: tests/qtest/bios-tables-test*
17
F: tests/qtest/acpi-utils.[hc]
18
F: tests/data/acpi/
19
+F: docs/specs/acpi_cpu_hotplug.rst
20
+F: docs/specs/acpi_mem_hotplug.rst
21
+F: docs/specs/acpi_pci_hotplug.rst
22
+F: docs/specs/acpi_hw_reduced_hotplug.rst
23
24
ACPI/HEST/GHES
25
R: Dongjiu Geng <gengdongjiu1@gmail.com>
26
@@ -XXX,XX +XXX,XX @@ F: hw/acpi/nvdimm.c
27
F: hw/mem/nvdimm.c
28
F: include/hw/mem/nvdimm.h
29
F: docs/nvdimm.txt
30
+F: docs/specs/acpi_nvdimm.rst
31
32
e1000x
33
M: Dmitry Fleytman <dmitry.fleytman@gmail.com>
34
--
35
2.20.1
36
37
diff view generated by jsdifflib
[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
[PULL 15/37] softmmu: Use accel_find("xen") instead of xen_available()
1
Implement the MVE VSRI and VSLI insns, which perform a
1
The xen_available() function is used only to produce an error
2
shift-and-insert operation.
2
for some Xen-specific command line options in QEMU binaries where
3
Xen support was not compiled in: it just returns the value of
4
the CONFIG_XEN define.
5
6
Now that accelerators are QOM classes, we can check for
7
"does this binary have Xen compiled in" with accel_find("xen"),
8
and drop the xen_available() function.
3
9
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
12
Message-id: 20210730105947.28215-2-peter.maydell@linaro.org
7
---
13
---
8
target/arm/helper-mve.h | 8 ++++++++
14
include/sysemu/arch_init.h | 1 -
9
target/arm/mve.decode | 9 ++++++++
15
softmmu/arch_init.c | 9 ---------
10
target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++
16
softmmu/vl.c | 6 +++---
11
target/arm/translate-mve.c | 3 +++
17
3 files changed, 3 insertions(+), 13 deletions(-)
12
4 files changed, 62 insertions(+)
13
18
14
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
19
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper-mve.h
21
--- a/include/sysemu/arch_init.h
17
+++ b/target/arm/helper-mve.h
22
+++ b/include/sysemu/arch_init.h
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
@@ -XXX,XX +XXX,XX @@ enum {
19
DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
extern const uint32_t arch_type;
20
DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
21
DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
int kvm_available(void);
22
+
27
-int xen_available(void);
23
+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
24
+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
/* default virtio transport per architecture */
25
+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
#define QEMU_ARCH_VIRTIO_PCI (QEMU_ARCH_ALPHA | QEMU_ARCH_ARM | \
26
+
31
diff --git a/softmmu/arch_init.c b/softmmu/arch_init.c
27
+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
31
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/mve.decode
33
--- a/softmmu/arch_init.c
33
+++ b/target/arm/mve.decode
34
+++ b/softmmu/arch_init.c
34
@@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
35
@@ -XXX,XX +XXX,XX @@ int kvm_available(void)
35
36
return 0;
36
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
37
#endif
37
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
38
}
38
+
39
-
39
+# Shift-and-insert
40
-int xen_available(void)
40
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
41
-{
41
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
42
-#ifdef CONFIG_XEN
42
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
43
- return 1;
43
+
44
-#else
44
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
45
- return 0;
45
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
46
-#endif
46
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
47
-}
47
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
48
diff --git a/softmmu/vl.c b/softmmu/vl.c
48
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/mve_helper.c
50
--- a/softmmu/vl.c
50
+++ b/target/arm/mve_helper.c
51
+++ b/softmmu/vl.c
51
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
52
@@ -XXX,XX +XXX,XX @@ void qemu_init(int argc, char **argv, char **envp)
52
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
53
has_defaults = 0;
53
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
54
break;
54
55
case QEMU_OPTION_xen_domid:
55
+/* Shift-and-insert; we always work with 64 bits at a time */
56
- if (!(xen_available())) {
56
+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \
57
+ if (!(accel_find("xen"))) {
57
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
58
error_report("Option not supported for this target");
58
+ void *vm, uint32_t shift) \
59
exit(1);
59
+ { \
60
}
60
+ uint64_t *d = vd, *m = vm; \
61
xen_domid = atoi(optarg);
61
+ uint16_t mask; \
62
break;
62
+ uint64_t shiftmask; \
63
case QEMU_OPTION_xen_attach:
63
+ unsigned e; \
64
- if (!(xen_available())) {
64
+ if (shift == 0 || shift == ESIZE * 8) { \
65
+ if (!(accel_find("xen"))) {
65
+ /* \
66
error_report("Option not supported for this target");
66
+ * Only VSLI can shift by 0; only VSRI can shift by <dt>. \
67
exit(1);
67
+ * The generic logic would give the right answer for 0 but \
68
}
68
+ * fails for <dt>. \
69
xen_mode = XEN_ATTACH;
69
+ */ \
70
break;
70
+ goto done; \
71
case QEMU_OPTION_xen_domid_restrict:
71
+ } \
72
- if (!(xen_available())) {
72
+ assert(shift < ESIZE * 8); \
73
+ if (!(accel_find("xen"))) {
73
+ mask = mve_element_mask(env); \
74
error_report("Option not supported for this target");
74
+ /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \
75
exit(1);
75
+ shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \
76
}
76
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
77
+ uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \
78
+ (d[H8(e)] & ~shiftmask); \
79
+ mergemask(&d[H8(e)], r, mask); \
80
+ } \
81
+done: \
82
+ mve_advance_vpt(env); \
83
+ }
84
+
85
+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
86
+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
87
+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
88
+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
89
+
90
+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
91
+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
92
+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
93
+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
94
+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
95
+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
96
+
97
/*
98
* Long shifts taking half-sized inputs from top or bottom of the input
99
* vector and producing a double-width result. ESIZE, TYPE are for
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
105
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
106
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
107
108
+DO_2SHIFT(VSRI, vsri, false)
109
+DO_2SHIFT(VSLI, vsli, false)
110
+
111
#define DO_VSHLL(INSN, FN) \
112
static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
113
{ \
114
--
77
--
115
2.20.1
78
2.20.1
116
79
117
80
diff view generated by jsdifflib
[PULL 15/24] target/arm: Implement MVE VSHLL
[PULL 16/37] monitor: Use accel_find("kvm") instead of kvm_available()
1
Implement the MVE VHLL (vector shift left long) insn. This has two
1
The kvm_available() function reports whether KVM support was
2
encodings: the T1 encoding is the usual shift-by-immediate format,
2
compiled into the QEMU binary; it returns the value of the
3
and the T2 encoding is a special case where the shift count is always
3
CONFIG_KVM define.
4
equal to the element size.
4
5
The only place in the codebase where we use this function is
6
in qmp_query_kvm(). Now that accelerators are based on QOM
7
classes we can instead use accel_find("kvm") and remove the
8
kvm_available() function.
5
9
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
12
Message-id: 20210730105947.28215-3-peter.maydell@linaro.org
9
---
13
---
10
target/arm/helper-mve.h | 9 +++++++
14
include/sysemu/arch_init.h | 2 --
11
target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++---
15
monitor/qmp-cmds.c | 2 +-
12
target/arm/mve_helper.c | 32 +++++++++++++++++++++++
16
softmmu/arch_init.c | 9 ---------
13
target/arm/translate-mve.c | 15 +++++++++++
17
3 files changed, 1 insertion(+), 12 deletions(-)
14
4 files changed, 105 insertions(+), 4 deletions(-)
15
18
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
19
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
17
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-mve.h
21
--- a/include/sysemu/arch_init.h
19
+++ b/target/arm/helper-mve.h
22
+++ b/include/sysemu/arch_init.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
@@ -XXX,XX +XXX,XX @@ enum {
21
DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
22
DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
extern const uint32_t arch_type;
23
DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
24
+
27
-int kvm_available(void);
25
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
-
26
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
/* default virtio transport per architecture */
27
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
#define QEMU_ARCH_VIRTIO_PCI (QEMU_ARCH_ALPHA | QEMU_ARCH_ARM | \
28
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
QEMU_ARCH_HPPA | QEMU_ARCH_I386 | \
29
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
diff --git a/monitor/qmp-cmds.c b/monitor/qmp-cmds.c
30
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
34
--- a/monitor/qmp-cmds.c
36
+++ b/target/arm/mve.decode
35
+++ b/monitor/qmp-cmds.c
37
@@ -XXX,XX +XXX,XX @@
36
@@ -XXX,XX +XXX,XX @@ KvmInfo *qmp_query_kvm(Error **errp)
38
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
37
KvmInfo *info = g_malloc0(sizeof(*info));
39
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
38
40
39
info->enabled = kvm_enabled();
41
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
40
- info->present = kvm_available();
42
+@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
41
+ info->present = accel_find("kvm");
43
+# VSHLL encoding T2 where shift == esize
42
44
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
43
return info;
45
+ qd=%qd qm=%qm size=0 shift=8
44
}
46
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
45
diff --git a/softmmu/arch_init.c b/softmmu/arch_init.c
47
+ qd=%qd qm=%qm size=1 shift=16
48
+
49
# Right shifts are encoded as N - shift, where N is the element size in bits.
50
%rshift_i5 16:5 !function=rsub_32
51
%rshift_i4 16:4 !function=rsub_16
52
@@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
53
VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
54
VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
55
56
-VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
57
-VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
58
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
59
+# overlaps what would be size=0b11 VMULH/VRMULH
60
+{
61
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
62
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
63
64
-VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
65
-VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
66
+ VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
67
+}
68
+
69
+{
70
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
71
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
72
+
73
+ VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
74
+}
75
+
76
+{
77
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
78
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
79
+
80
+ VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
81
+}
82
+
83
+{
84
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
85
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
86
+
87
+ VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
88
+}
89
90
VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
91
VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
92
@@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
93
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
94
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
95
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
96
+
97
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
98
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
99
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
100
+
101
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
102
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
103
+
104
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
105
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
106
+
107
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
108
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
109
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
110
index XXXXXXX..XXXXXXX 100644
46
index XXXXXXX..XXXXXXX 100644
111
--- a/target/arm/mve_helper.c
47
--- a/softmmu/arch_init.c
112
+++ b/target/arm/mve_helper.c
48
+++ b/softmmu/arch_init.c
113
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
49
@@ -XXX,XX +XXX,XX @@ int graphic_depth = 32;
114
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
50
#endif
115
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
51
116
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
52
const uint32_t arch_type = QEMU_ARCH;
117
+
53
-
118
+/*
54
-int kvm_available(void)
119
+ * Long shifts taking half-sized inputs from top or bottom of the input
55
-{
120
+ * vector and producing a double-width result. ESIZE, TYPE are for
56
-#ifdef CONFIG_KVM
121
+ * the input, and LESIZE, LTYPE for the output.
57
- return 1;
122
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
58
-#else
123
+ * because the long shift is strictly left-only.
59
- return 0;
124
+ */
60
-#endif
125
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \
61
-}
126
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
127
+ void *vm, uint32_t shift) \
128
+ { \
129
+ LTYPE *d = vd; \
130
+ TYPE *m = vm; \
131
+ uint16_t mask = mve_element_mask(env); \
132
+ unsigned le; \
133
+ assert(shift <= 16); \
134
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
135
+ LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \
136
+ mergemask(&d[H##LESIZE(le)], r, mask); \
137
+ } \
138
+ mve_advance_vpt(env); \
139
+ }
140
+
141
+#define DO_VSHLL_ALL(OP, TOP) \
142
+ DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \
143
+ DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \
144
+ DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \
145
+ DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \
146
+
147
+DO_VSHLL_ALL(vshllb, false)
148
+DO_VSHLL_ALL(vshllt, true)
149
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/target/arm/translate-mve.c
152
+++ b/target/arm/translate-mve.c
153
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
154
DO_2SHIFT(VSHRI_U, vshli_u, true)
155
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
+
158
+#define DO_VSHLL(INSN, FN) \
159
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
160
+ { \
161
+ static MVEGenTwoOpShiftFn * const fns[] = { \
162
+ gen_helper_mve_##FN##b, \
163
+ gen_helper_mve_##FN##h, \
164
+ }; \
165
+ return do_2shift(s, a, fns[a->size], false); \
166
+ }
167
+
168
+DO_VSHLL(VSHLL_BS, vshllbs)
169
+DO_VSHLL(VSHLL_BU, vshllbu)
170
+DO_VSHLL(VSHLL_TS, vshllts)
171
+DO_VSHLL(VSHLL_TU, vshlltu)
172
--
62
--
173
2.20.1
63
2.20.1
174
64
175
65
diff view generated by jsdifflib
[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
[PULL 17/37] softmmu/arch_init.c: Trim down include list
1
The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
1
arch_init.c does very little but has a long list of #include lines.
2
insns had some bugs:
2
Remove all the unnecessary ones.
3
* the 32x32 multiply of elements was being done as 32x32->32,
4
not 32x32->64
5
* we were incorrectly maintaining the accumulator in its full
6
72-bit form across all 4 beats of the insn; in the pseudocode
7
it is squashed back into the 64 bits of the RdaHi:RdaLo
8
registers after each beat
9
3
10
In particular, fixing the second of these allows us to recast
11
the implementation to avoid 128-bit arithmetic entirely.
12
13
Since the element size here is always 4, we can also drop the
14
parameterization of ESIZE to make the code a little more readable.
15
16
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
6
Message-id: 20210730105947.28215-4-peter.maydell@linaro.org
20
---
7
---
21
target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
8
softmmu/arch_init.c | 7 -------
22
1 file changed, 21 insertions(+), 17 deletions(-)
9
1 file changed, 7 deletions(-)
23
10
24
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
11
diff --git a/softmmu/arch_init.c b/softmmu/arch_init.c
25
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/mve_helper.c
13
--- a/softmmu/arch_init.c
27
+++ b/target/arm/mve_helper.c
14
+++ b/softmmu/arch_init.c
28
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@
29
*/
16
*/
30
31
#include "qemu/osdep.h"
17
#include "qemu/osdep.h"
32
-#include "qemu/int128.h"
18
#include "sysemu/arch_init.h"
33
#include "cpu.h"
19
-#include "hw/pci/pci.h"
34
#include "internals.h"
20
-#include "hw/audio/soundhw.h"
35
#include "vec_internal.h"
21
-#include "qapi/error.h"
36
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
22
-#include "qemu/config-file.h"
37
DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
23
-#include "qemu/error-report.h"
38
24
-#include "hw/acpi/acpi.h"
39
/*
25
-#include "qemu/help_option.h"
40
- * Rounding multiply add long dual accumulate high: we must keep
26
41
- * a 72-bit internal accumulator value and return the top 64 bits.
27
#ifdef TARGET_SPARC
42
+ * Rounding multiply add long dual accumulate high. In the pseudocode
28
int graphic_width = 1024;
43
+ * this is implemented with a 72-bit internal accumulator value of which
44
+ * the top 64 bits are returned. We optimize this to avoid having to
45
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
46
+ * is squashed back into 64-bits after each beat.
47
*/
48
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \
49
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \
50
uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
51
void *vm, uint64_t a) \
52
{ \
53
uint16_t mask = mve_element_mask(env); \
54
unsigned e; \
55
TYPE *n = vn, *m = vm; \
56
- Int128 acc = int128_lshift(TO128(a), 8); \
57
- for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
58
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
59
if (mask & 1) { \
60
+ LTYPE mul; \
61
if (e & 1) { \
62
- acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
63
- m[H##ESIZE(e)])); \
64
+ mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \
65
+ if (SUB) { \
66
+ mul = -mul; \
67
+ } \
68
} else { \
69
- acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
70
- m[H##ESIZE(e)])); \
71
+ mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \
72
} \
73
- acc = int128_add(acc, int128_make64(1 << 7)); \
74
+ mul = (mul >> 8) + ((mul >> 7) & 1); \
75
+ a += mul; \
76
} \
77
} \
78
mve_advance_vpt(env); \
79
- return int128_getlo(int128_rshift(acc, 8)); \
80
+ return a; \
81
}
82
83
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
84
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
85
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
86
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
87
88
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
89
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
90
91
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
92
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
93
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
94
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
95
96
/* Vector add across vector */
97
#define DO_VADDV(OP, ESIZE, TYPE) \
98
--
29
--
99
2.20.1
30
2.20.1
100
31
101
32
diff view generated by jsdifflib
New patch
[PULL 18/37] meson.build: Define QEMU_ARCH in config-target.h
1
Instead of using an ifdef ladder in arch_init.c (which we then have
2
to manually update every time we add or remove a target
3
architecture), have meson.build put "#define QEMU_ARCH QEMU_ARCH_FOO"
4
in the config-target.h file.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210730105947.28215-5-peter.maydell@linaro.org
10
---
11
meson.build | 2 ++
12
softmmu/arch_init.c | 41 -----------------------------------------
13
2 files changed, 2 insertions(+), 41 deletions(-)
14
15
diff --git a/meson.build b/meson.build
16
index XXXXXXX..XXXXXXX 100644
17
--- a/meson.build
18
+++ b/meson.build
19
@@ -XXX,XX +XXX,XX @@ foreach target : target_dirs
20
config_target_data.set(k, v)
21
endif
22
endforeach
23
+ config_target_data.set('QEMU_ARCH',
24
+ 'QEMU_ARCH_' + config_target['TARGET_BASE_ARCH'].to_upper())
25
config_target_h += {target: configure_file(output: target + '-config-target.h',
26
configuration: config_target_data)}
27
28
diff --git a/softmmu/arch_init.c b/softmmu/arch_init.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/softmmu/arch_init.c
31
+++ b/softmmu/arch_init.c
32
@@ -XXX,XX +XXX,XX @@ int graphic_height = 600;
33
int graphic_depth = 32;
34
#endif
35
36
-
37
-#if defined(TARGET_ALPHA)
38
-#define QEMU_ARCH QEMU_ARCH_ALPHA
39
-#elif defined(TARGET_ARM)
40
-#define QEMU_ARCH QEMU_ARCH_ARM
41
-#elif defined(TARGET_CRIS)
42
-#define QEMU_ARCH QEMU_ARCH_CRIS
43
-#elif defined(TARGET_HPPA)
44
-#define QEMU_ARCH QEMU_ARCH_HPPA
45
-#elif defined(TARGET_I386)
46
-#define QEMU_ARCH QEMU_ARCH_I386
47
-#elif defined(TARGET_M68K)
48
-#define QEMU_ARCH QEMU_ARCH_M68K
49
-#elif defined(TARGET_MICROBLAZE)
50
-#define QEMU_ARCH QEMU_ARCH_MICROBLAZE
51
-#elif defined(TARGET_MIPS)
52
-#define QEMU_ARCH QEMU_ARCH_MIPS
53
-#elif defined(TARGET_NIOS2)
54
-#define QEMU_ARCH QEMU_ARCH_NIOS2
55
-#elif defined(TARGET_OPENRISC)
56
-#define QEMU_ARCH QEMU_ARCH_OPENRISC
57
-#elif defined(TARGET_PPC)
58
-#define QEMU_ARCH QEMU_ARCH_PPC
59
-#elif defined(TARGET_RISCV)
60
-#define QEMU_ARCH QEMU_ARCH_RISCV
61
-#elif defined(TARGET_RX)
62
-#define QEMU_ARCH QEMU_ARCH_RX
63
-#elif defined(TARGET_S390X)
64
-#define QEMU_ARCH QEMU_ARCH_S390X
65
-#elif defined(TARGET_SH4)
66
-#define QEMU_ARCH QEMU_ARCH_SH4
67
-#elif defined(TARGET_SPARC)
68
-#define QEMU_ARCH QEMU_ARCH_SPARC
69
-#elif defined(TARGET_TRICORE)
70
-#define QEMU_ARCH QEMU_ARCH_TRICORE
71
-#elif defined(TARGET_XTENSA)
72
-#define QEMU_ARCH QEMU_ARCH_XTENSA
73
-#elif defined(TARGET_AVR)
74
-#define QEMU_ARCH QEMU_ARCH_AVR
75
-#endif
76
-
77
const uint32_t arch_type = QEMU_ARCH;
78
--
79
2.20.1
80
81
diff view generated by jsdifflib
New patch
[PULL 19/37] arch_init.h: Add QEMU_ARCH_HEXAGON
1
When Hexagon was added we forgot to add it to the QEMU_ARCH_*
2
enumeration. This doesn't cause a visible effect because at the
3
moment Hexagon is linux-user only and the QEMU_ARCH_* constants are
4
only used in softmmu, but we might as well add it in, since it's the
5
only architecture currently missing from the list.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
11
Message-id: 20210730105947.28215-6-peter.maydell@linaro.org
12
---
13
include/sysemu/arch_init.h | 1 +
14
1 file changed, 1 insertion(+)
15
16
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/sysemu/arch_init.h
19
+++ b/include/sysemu/arch_init.h
20
@@ -XXX,XX +XXX,XX @@ enum {
21
QEMU_ARCH_RISCV = (1 << 19),
22
QEMU_ARCH_RX = (1 << 20),
23
QEMU_ARCH_AVR = (1 << 21),
24
+ QEMU_ARCH_HEXAGON = (1 << 22),
25
26
QEMU_ARCH_NONE = (1 << 31),
27
};
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
[PULL 20/37] arch_init.h: Move QEMU_ARCH_VIRTIO_* to qdev-monitor.c
1
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
1
The QEMU_ARCH_VIRTIO_* defines are used only in one file,
2
and VQSHLU.
2
qdev-monitor.c. Move them to that file.
3
4
The size-and-immediate encoding here is the same as Neon, and we
5
handle it the same way neon-dp.decode does.
6
3
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
6
Reviewed-by: Markus Armbruster <armbru@redhat.com>
7
Message-id: 20210730105947.28215-7-peter.maydell@linaro.org
10
---
8
---
11
target/arm/helper-mve.h | 16 +++++++++++
9
include/sysemu/arch_init.h | 9 ---------
12
target/arm/mve.decode | 23 +++++++++++++++
10
softmmu/qdev-monitor.c | 9 +++++++++
13
target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++
11
2 files changed, 9 insertions(+), 9 deletions(-)
14
target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
15
4 files changed, 147 insertions(+)
16
12
17
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
13
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
18
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper-mve.h
15
--- a/include/sysemu/arch_init.h
20
+++ b/target/arm/helper-mve.h
16
+++ b/include/sysemu/arch_init.h
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
17
@@ -XXX,XX +XXX,XX @@ enum {
22
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
18
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
19
extern const uint32_t arch_type;
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
20
21
-/* default virtio transport per architecture */
22
-#define QEMU_ARCH_VIRTIO_PCI (QEMU_ARCH_ALPHA | QEMU_ARCH_ARM | \
23
- QEMU_ARCH_HPPA | QEMU_ARCH_I386 | \
24
- QEMU_ARCH_MIPS | QEMU_ARCH_PPC | \
25
- QEMU_ARCH_RISCV | QEMU_ARCH_SH4 | \
26
- QEMU_ARCH_SPARC | QEMU_ARCH_XTENSA)
27
-#define QEMU_ARCH_VIRTIO_CCW (QEMU_ARCH_S390X)
28
-#define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K)
29
-
30
#endif
31
diff --git a/softmmu/qdev-monitor.c b/softmmu/qdev-monitor.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/softmmu/qdev-monitor.c
34
+++ b/softmmu/qdev-monitor.c
35
@@ -XXX,XX +XXX,XX @@ typedef struct QDevAlias
36
uint32_t arch_mask;
37
} QDevAlias;
38
39
+/* default virtio transport per architecture */
40
+#define QEMU_ARCH_VIRTIO_PCI (QEMU_ARCH_ALPHA | QEMU_ARCH_ARM | \
41
+ QEMU_ARCH_HPPA | QEMU_ARCH_I386 | \
42
+ QEMU_ARCH_MIPS | QEMU_ARCH_PPC | \
43
+ QEMU_ARCH_RISCV | QEMU_ARCH_SH4 | \
44
+ QEMU_ARCH_SPARC | QEMU_ARCH_XTENSA)
45
+#define QEMU_ARCH_VIRTIO_CCW (QEMU_ARCH_S390X)
46
+#define QEMU_ARCH_VIRTIO_MMIO (QEMU_ARCH_M68K)
25
+
47
+
26
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
/* Please keep this table sorted by typename. */
27
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
static const QDevAlias qdev_alias_table[] = {
28
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
50
{ "AC97", "ac97" }, /* -soundhw name */
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+
34
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/mve.decode
44
+++ b/target/arm/mve.decode
45
@@ -XXX,XX +XXX,XX @@
46
&2op qd qm qn size
47
&2scalar qd qn rm size
48
&1imm qd imm cmode op
49
+&2shift qd qm shift size
50
51
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
52
# Note that both Rn and Qd are 3 bits only (no D bit)
53
@@ -XXX,XX +XXX,XX @@
54
@2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
55
@2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
56
57
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
58
+@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
59
+@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
60
+
61
# Vector loads and stores
62
63
# Widening loads and narrowing stores:
64
@@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
65
# So we have a single decode line and check the cmode/op in the
66
# trans function.
67
Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
68
+
69
+# Shifts by immediate
70
+
71
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
72
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
73
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
74
+
75
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
76
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
77
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
78
+
79
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
80
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
81
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
82
+
83
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
84
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
85
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
86
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/mve_helper.c
89
+++ b/target/arm/mve_helper.c
90
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
91
WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
92
#define DO_UQRSHL_OP(N, M, satp) \
93
WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
94
+#define DO_SUQSHL_OP(N, M, satp) \
95
+ WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
96
97
DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
98
DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
99
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
100
DO_VADDV(vaddvub, 1, uint8_t)
101
DO_VADDV(vaddvuh, 2, uint16_t)
102
DO_VADDV(vaddvuw, 4, uint32_t)
103
+
104
+/* Shifts by immediate */
105
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
106
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
107
+ void *vm, uint32_t shift) \
108
+ { \
109
+ TYPE *d = vd, *m = vm; \
110
+ uint16_t mask = mve_element_mask(env); \
111
+ unsigned e; \
112
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
113
+ mergemask(&d[H##ESIZE(e)], \
114
+ FN(m[H##ESIZE(e)], shift), mask); \
115
+ } \
116
+ mve_advance_vpt(env); \
117
+ }
118
+
119
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \
120
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
121
+ void *vm, uint32_t shift) \
122
+ { \
123
+ TYPE *d = vd, *m = vm; \
124
+ uint16_t mask = mve_element_mask(env); \
125
+ unsigned e; \
126
+ bool qc = false; \
127
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
128
+ bool sat = false; \
129
+ mergemask(&d[H##ESIZE(e)], \
130
+ FN(m[H##ESIZE(e)], shift, &sat), mask); \
131
+ qc |= sat & mask & 1; \
132
+ } \
133
+ if (qc) { \
134
+ env->vfp.qc[0] = qc; \
135
+ } \
136
+ mve_advance_vpt(env); \
137
+ }
138
+
139
+/* provide unsigned 2-op shift helpers for all sizes */
140
+#define DO_2SHIFT_U(OP, FN) \
141
+ DO_2SHIFT(OP##b, 1, uint8_t, FN) \
142
+ DO_2SHIFT(OP##h, 2, uint16_t, FN) \
143
+ DO_2SHIFT(OP##w, 4, uint32_t, FN)
144
+
145
+#define DO_2SHIFT_SAT_U(OP, FN) \
146
+ DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
147
+ DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \
148
+ DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
149
+#define DO_2SHIFT_SAT_S(OP, FN) \
150
+ DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \
151
+ DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \
152
+ DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
153
+
154
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
155
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
156
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
157
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
158
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/target/arm/translate-mve.c
161
+++ b/target/arm/translate-mve.c
162
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
163
typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
164
typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
165
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
166
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
167
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
168
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
169
typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
170
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
171
}
172
return do_1imm(s, a, fn);
173
}
174
+
175
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
176
+ bool negateshift)
177
+{
178
+ TCGv_ptr qd, qm;
179
+ int shift = a->shift;
180
+
181
+ if (!dc_isar_feature(aa32_mve, s) ||
182
+ !mve_check_qreg_bank(s, a->qd | a->qm) ||
183
+ !fn) {
184
+ return false;
185
+ }
186
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
187
+ return true;
188
+ }
189
+
190
+ /*
191
+ * When we handle a right shift insn using a left-shift helper
192
+ * which permits a negative shift count to indicate a right-shift,
193
+ * we must negate the shift count.
194
+ */
195
+ if (negateshift) {
196
+ shift = -shift;
197
+ }
198
+
199
+ qd = mve_qreg_ptr(a->qd);
200
+ qm = mve_qreg_ptr(a->qm);
201
+ fn(cpu_env, qd, qm, tcg_constant_i32(shift));
202
+ tcg_temp_free_ptr(qd);
203
+ tcg_temp_free_ptr(qm);
204
+ mve_update_eci(s);
205
+ return true;
206
+}
207
+
208
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \
209
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
210
+ { \
211
+ static MVEGenTwoOpShiftFn * const fns[] = { \
212
+ gen_helper_mve_##FN##b, \
213
+ gen_helper_mve_##FN##h, \
214
+ gen_helper_mve_##FN##w, \
215
+ NULL, \
216
+ }; \
217
+ return do_2shift(s, a, fns[a->size], NEGATESHIFT); \
218
+ }
219
+
220
+DO_2SHIFT(VSHLI, vshli_u, false)
221
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
222
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
223
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
224
--
51
--
225
2.20.1
52
2.20.1
226
53
227
54
diff view generated by jsdifflib
[PULL 12/24] target/arm: Implement MVE logical immediate insns
[PULL 21/37] arch_init.h: Don't include arch_init.h unnecessarily
1
Implement the MVE logical-immediate insns (VMOV, VMVN,
1
arch_init.h only defines the QEMU_ARCH_* enumeration and the
2
VORR and VBIC). These have essentially the same encoding
2
arch_type global. Don't include it in files that don't use those.
3
as their Neon equivalents, and we implement the decode
4
in the same way.
5
3
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20210730105947.28215-8-peter.maydell@linaro.org
9
---
9
---
10
target/arm/helper-mve.h | 4 +++
10
blockdev.c | 1 -
11
target/arm/mve.decode | 17 +++++++++++++
11
hw/i386/pc.c | 1 -
12
target/arm/mve_helper.c | 24 ++++++++++++++++++
12
hw/i386/pc_piix.c | 1 -
13
target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
13
hw/i386/pc_q35.c | 1 -
14
4 files changed, 95 insertions(+)
14
hw/mips/jazz.c | 1 -
15
hw/mips/malta.c | 1 -
16
hw/ppc/prep.c | 1 -
17
hw/riscv/sifive_e.c | 1 -
18
hw/riscv/sifive_u.c | 1 -
19
hw/riscv/spike.c | 1 -
20
hw/riscv/virt.c | 1 -
21
monitor/qmp-cmds.c | 1 -
22
target/ppc/cpu_init.c | 1 -
23
target/s390x/cpu-sysemu.c | 1 -
24
14 files changed, 14 deletions(-)
15
25
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
26
diff --git a/blockdev.c b/blockdev.c
17
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-mve.h
28
--- a/blockdev.c
19
+++ b/target/arm/helper-mve.h
29
+++ b/blockdev.c
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
30
@@ -XXX,XX +XXX,XX @@
21
DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
31
#include "sysemu/iothread.h"
22
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
32
#include "block/block_int.h"
23
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
33
#include "block/trace.h"
24
+
34
-#include "sysemu/arch_init.h"
25
+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
35
#include "sysemu/runstate.h"
26
+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
36
#include "sysemu/replay.h"
27
+DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
37
#include "qemu/cutils.h"
28
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
38
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
29
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/mve.decode
40
--- a/hw/i386/pc.c
31
+++ b/target/arm/mve.decode
41
+++ b/hw/i386/pc.c
32
@@ -XXX,XX +XXX,XX @@
42
@@ -XXX,XX +XXX,XX @@
33
# VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
43
#include "hw/xen/start_info.h"
34
%size_28 28:1 !function=plus_1
44
#include "ui/qemu-spice.h"
35
45
#include "exec/memory.h"
36
+# 1imm format immediate
46
-#include "sysemu/arch_init.h"
37
+%imm_28_16_0 28:1 16:3 0:4
47
#include "qemu/bitmap.h"
38
+
48
#include "qemu/config-file.h"
39
&vldr_vstr rn qd imm p a w size l u
49
#include "qemu/error-report.h"
40
&1op qd qm size
50
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
41
&2op qd qm qn size
51
index XXXXXXX..XXXXXXX 100644
42
&2scalar qd qn rm size
52
--- a/hw/i386/pc_piix.c
43
+&1imm qd imm cmode op
53
+++ b/hw/i386/pc_piix.c
44
45
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
46
# Note that both Rn and Qd are 3 bits only (no D bit)
47
@@ -XXX,XX +XXX,XX @@
54
@@ -XXX,XX +XXX,XX @@
48
@2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
55
#include "sysemu/kvm.h"
49
@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
56
#include "hw/kvm/clock.h"
50
size=%size_28
57
#include "hw/sysbus.h"
51
+@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
58
-#include "sysemu/arch_init.h"
52
59
#include "hw/i2c/smbus_eeprom.h"
53
# The _rev suffix indicates that Vn and Vm are reversed. This is
60
#include "hw/xen/xen-x86.h"
54
# the case for shifts. In the Arm ARM these insns are documented
61
#include "exec/memory.h"
55
@@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
62
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
56
# Predicate operations
57
%mask_22_13 22:1 13:3
58
VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
59
+
60
+# Logical immediate operations (1 reg and modified-immediate)
61
+
62
+# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
63
+# not in a way we can conveniently represent in decodetree without
64
+# a lot of repetition:
65
+# VORR: op=0, (cmode & 1) && cmode < 12
66
+# VBIC: op=1, (cmode & 1) && cmode < 12
67
+# VMOV: everything else
68
+# So we have a single decode line and check the cmode/op in the
69
+# trans function.
70
+Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
71
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
72
index XXXXXXX..XXXXXXX 100644
63
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/mve_helper.c
64
--- a/hw/i386/pc_q35.c
74
+++ b/target/arm/mve_helper.c
65
+++ b/hw/i386/pc_q35.c
75
@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
66
@@ -XXX,XX +XXX,XX @@
76
DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
67
#include "qemu/osdep.h"
77
DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
68
#include "qemu/units.h"
78
69
#include "hw/loader.h"
79
+/*
70
-#include "sysemu/arch_init.h"
80
+ * 1 operand immediates: Vda is destination and possibly also one source.
71
#include "hw/i2c/smbus_eeprom.h"
81
+ * All these insns work at 64-bit widths.
72
#include "hw/rtc/mc146818rtc.h"
82
+ */
73
#include "sysemu/kvm.h"
83
+#define DO_1OP_IMM(OP, FN) \
74
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
84
+ void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \
85
+ { \
86
+ uint64_t *da = vda; \
87
+ uint16_t mask = mve_element_mask(env); \
88
+ unsigned e; \
89
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
90
+ mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \
91
+ } \
92
+ mve_advance_vpt(env); \
93
+ }
94
+
95
+#define DO_MOVI(N, I) (I)
96
+#define DO_ANDI(N, I) ((N) & (I))
97
+#define DO_ORRI(N, I) ((N) | (I))
98
+
99
+DO_1OP_IMM(vmovi, DO_MOVI)
100
+DO_1OP_IMM(vandi, DO_ANDI)
101
+DO_1OP_IMM(vorri, DO_ORRI)
102
+
103
#define DO_2OP(OP, ESIZE, TYPE, FN) \
104
void HELPER(glue(mve_, OP))(CPUARMState *env, \
105
void *vd, void *vn, void *vm) \
106
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
107
index XXXXXXX..XXXXXXX 100644
75
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-mve.c
76
--- a/hw/mips/jazz.c
109
+++ b/target/arm/translate-mve.c
77
+++ b/hw/mips/jazz.c
110
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
78
@@ -XXX,XX +XXX,XX @@
111
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
79
#include "hw/isa/isa.h"
112
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
80
#include "hw/block/fdc.h"
113
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
81
#include "sysemu/sysemu.h"
114
+typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
82
-#include "sysemu/arch_init.h"
115
83
#include "hw/boards.h"
116
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
84
#include "net/net.h"
117
static inline long mve_qreg_offset(unsigned reg)
85
#include "hw/scsi/esp.h"
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
86
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
119
mve_update_eci(s);
87
index XXXXXXX..XXXXXXX 100644
120
return true;
88
--- a/hw/mips/malta.c
121
}
89
+++ b/hw/mips/malta.c
122
+
90
@@ -XXX,XX +XXX,XX @@
123
+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
91
#include "hw/mips/mips.h"
124
+{
92
#include "hw/mips/cpudevs.h"
125
+ TCGv_ptr qd;
93
#include "hw/pci/pci.h"
126
+ uint64_t imm;
94
-#include "sysemu/arch_init.h"
127
+
95
#include "qemu/log.h"
128
+ if (!dc_isar_feature(aa32_mve, s) ||
96
#include "hw/mips/bios.h"
129
+ !mve_check_qreg_bank(s, a->qd) ||
97
#include "hw/ide.h"
130
+ !fn) {
98
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
131
+ return false;
99
index XXXXXXX..XXXXXXX 100644
132
+ }
100
--- a/hw/ppc/prep.c
133
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
101
+++ b/hw/ppc/prep.c
134
+ return true;
102
@@ -XXX,XX +XXX,XX @@
135
+ }
103
#include "hw/rtc/mc146818rtc.h"
136
+
104
#include "hw/isa/pc87312.h"
137
+ imm = asimd_imm_const(a->imm, a->cmode, a->op);
105
#include "hw/qdev-properties.h"
138
+
106
-#include "sysemu/arch_init.h"
139
+ qd = mve_qreg_ptr(a->qd);
107
#include "sysemu/kvm.h"
140
+ fn(cpu_env, qd, tcg_constant_i64(imm));
108
#include "sysemu/reset.h"
141
+ tcg_temp_free_ptr(qd);
109
#include "trace.h"
142
+ mve_update_eci(s);
110
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
143
+ return true;
111
index XXXXXXX..XXXXXXX 100644
144
+}
112
--- a/hw/riscv/sifive_e.c
145
+
113
+++ b/hw/riscv/sifive_e.c
146
+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
114
@@ -XXX,XX +XXX,XX @@
147
+{
115
#include "hw/intc/sifive_plic.h"
148
+ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
116
#include "hw/misc/sifive_e_prci.h"
149
+ MVEGenOneOpImmFn *fn;
117
#include "chardev/char.h"
150
+
118
-#include "sysemu/arch_init.h"
151
+ if ((a->cmode & 1) && a->cmode < 12) {
119
#include "sysemu/sysemu.h"
152
+ if (a->op) {
120
153
+ /*
121
static const MemMapEntry sifive_e_memmap[] = {
154
+ * For op=1, the immediate will be inverted by asimd_imm_const(),
122
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
155
+ * so the VBIC becomes a logical AND operation.
123
index XXXXXXX..XXXXXXX 100644
156
+ */
124
--- a/hw/riscv/sifive_u.c
157
+ fn = gen_helper_mve_vandi;
125
+++ b/hw/riscv/sifive_u.c
158
+ } else {
126
@@ -XXX,XX +XXX,XX @@
159
+ fn = gen_helper_mve_vorri;
127
#include "hw/intc/sifive_plic.h"
160
+ }
128
#include "chardev/char.h"
161
+ } else {
129
#include "net/eth.h"
162
+ /* There is one unallocated cmode/op combination in this space */
130
-#include "sysemu/arch_init.h"
163
+ if (a->cmode == 15 && a->op == 1) {
131
#include "sysemu/device_tree.h"
164
+ return false;
132
#include "sysemu/runstate.h"
165
+ }
133
#include "sysemu/sysemu.h"
166
+ /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
134
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
167
+ fn = gen_helper_mve_vmovi;
135
index XXXXXXX..XXXXXXX 100644
168
+ }
136
--- a/hw/riscv/spike.c
169
+ return do_1imm(s, a, fn);
137
+++ b/hw/riscv/spike.c
170
+}
138
@@ -XXX,XX +XXX,XX @@
139
#include "hw/char/riscv_htif.h"
140
#include "hw/intc/sifive_clint.h"
141
#include "chardev/char.h"
142
-#include "sysemu/arch_init.h"
143
#include "sysemu/device_tree.h"
144
#include "sysemu/sysemu.h"
145
146
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
147
index XXXXXXX..XXXXXXX 100644
148
--- a/hw/riscv/virt.c
149
+++ b/hw/riscv/virt.c
150
@@ -XXX,XX +XXX,XX @@
151
#include "hw/intc/sifive_plic.h"
152
#include "hw/misc/sifive_test.h"
153
#include "chardev/char.h"
154
-#include "sysemu/arch_init.h"
155
#include "sysemu/device_tree.h"
156
#include "sysemu/sysemu.h"
157
#include "hw/pci/pci.h"
158
diff --git a/monitor/qmp-cmds.c b/monitor/qmp-cmds.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/monitor/qmp-cmds.c
161
+++ b/monitor/qmp-cmds.c
162
@@ -XXX,XX +XXX,XX @@
163
#include "sysemu/kvm.h"
164
#include "sysemu/runstate.h"
165
#include "sysemu/runstate-action.h"
166
-#include "sysemu/arch_init.h"
167
#include "sysemu/blockdev.h"
168
#include "sysemu/block-backend.h"
169
#include "qapi/error.h"
170
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
171
index XXXXXXX..XXXXXXX 100644
172
--- a/target/ppc/cpu_init.c
173
+++ b/target/ppc/cpu_init.c
174
@@ -XXX,XX +XXX,XX @@
175
#include "disas/dis-asm.h"
176
#include "exec/gdbstub.h"
177
#include "kvm_ppc.h"
178
-#include "sysemu/arch_init.h"
179
#include "sysemu/cpus.h"
180
#include "sysemu/hw_accel.h"
181
#include "sysemu/tcg.h"
182
diff --git a/target/s390x/cpu-sysemu.c b/target/s390x/cpu-sysemu.c
183
index XXXXXXX..XXXXXXX 100644
184
--- a/target/s390x/cpu-sysemu.c
185
+++ b/target/s390x/cpu-sysemu.c
186
@@ -XXX,XX +XXX,XX @@
187
188
#include "hw/s390x/pv.h"
189
#include "hw/boards.h"
190
-#include "sysemu/arch_init.h"
191
#include "sysemu/sysemu.h"
192
#include "sysemu/tcg.h"
193
#include "hw/core/sysemu-cpu-ops.h"
171
--
194
--
172
2.20.1
195
2.20.1
173
196
174
197
diff view generated by jsdifflib
New patch
[PULL 22/37] stubs: Remove unused arch_type.c stub
1
We added a stub for the arch_type global in commit 5964ed56d9a1 so
2
that we could compile blockdev.c into the tools. However, in commit
3
9db1d3a2be9bf we removed the only use of arch_type from blockdev.c.
4
The stub is therefore no longer needed, and we can delete it again,
5
together with the QEMU_ARCH_NONE value that only the stub was using.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20210730105947.28215-9-peter.maydell@linaro.org
11
---
12
include/sysemu/arch_init.h | 2 --
13
stubs/arch_type.c | 4 ----
14
stubs/meson.build | 1 -
15
3 files changed, 7 deletions(-)
16
delete mode 100644 stubs/arch_type.c
17
18
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/sysemu/arch_init.h
21
+++ b/include/sysemu/arch_init.h
22
@@ -XXX,XX +XXX,XX @@ enum {
23
QEMU_ARCH_RX = (1 << 20),
24
QEMU_ARCH_AVR = (1 << 21),
25
QEMU_ARCH_HEXAGON = (1 << 22),
26
-
27
- QEMU_ARCH_NONE = (1 << 31),
28
};
29
30
extern const uint32_t arch_type;
31
diff --git a/stubs/arch_type.c b/stubs/arch_type.c
32
deleted file mode 100644
33
index XXXXXXX..XXXXXXX
34
--- a/stubs/arch_type.c
35
+++ /dev/null
36
@@ -XXX,XX +XXX,XX @@
37
-#include "qemu/osdep.h"
38
-#include "sysemu/arch_init.h"
39
-
40
-const uint32_t arch_type = QEMU_ARCH_NONE;
41
diff --git a/stubs/meson.build b/stubs/meson.build
42
index XXXXXXX..XXXXXXX 100644
43
--- a/stubs/meson.build
44
+++ b/stubs/meson.build
45
@@ -XXX,XX +XXX,XX @@
46
-stub_ss.add(files('arch_type.c'))
47
stub_ss.add(files('bdrv-next-monitor-owned.c'))
48
stub_ss.add(files('blk-commit-all.c'))
49
stub_ss.add(files('blk-exp-close-all.c'))
50
--
51
2.20.1
52
53
diff view generated by jsdifflib
New patch
[PULL 23/37] hw/core/loader: In gunzip(), check index is in range before use, not after
1
The gunzip() function reads various fields from a passed in source
2
buffer in order to skip a header before passing the actual compressed
3
data to the zlib inflate() function. It does check whether the
4
passed in buffer is too small, but unfortunately it checks that only
5
after reading bytes from the src buffer, so it could read off the end
6
of the buffer.
1
7
8
You can see this with valgrind:
9
10
$ printf "%b" '\x1f\x8b' > /tmp/image
11
$ valgrind qemu-system-aarch64 -display none -M virt -cpu max -kernel /tmp/image
12
[...]
13
==19224== Invalid read of size 1
14
==19224== at 0x67302E: gunzip (loader.c:558)
15
==19224== by 0x673907: load_image_gzipped_buffer (loader.c:788)
16
==19224== by 0xA18032: load_aarch64_image (boot.c:932)
17
==19224== by 0xA18489: arm_setup_direct_kernel_boot (boot.c:1063)
18
==19224== by 0xA18D90: arm_load_kernel (boot.c:1317)
19
==19224== by 0x9F3651: machvirt_init (virt.c:2114)
20
==19224== by 0x794B7A: machine_run_board_init (machine.c:1272)
21
==19224== by 0xD5CAD3: qemu_init_board (vl.c:2618)
22
==19224== by 0xD5CCA6: qmp_x_exit_preconfig (vl.c:2692)
23
==19224== by 0xD5F32E: qemu_init (vl.c:3713)
24
==19224== by 0x5ADDB1: main (main.c:49)
25
==19224== Address 0x3802a873 is 0 bytes after a block of size 3 alloc'd
26
==19224== at 0x4C31B0F: malloc (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
27
==19224== by 0x61E7657: g_file_get_contents (in /usr/lib/x86_64-linux-gnu/libglib-2.0.so.0.5600.4)
28
==19224== by 0x673895: load_image_gzipped_buffer (loader.c:771)
29
==19224== by 0xA18032: load_aarch64_image (boot.c:932)
30
==19224== by 0xA18489: arm_setup_direct_kernel_boot (boot.c:1063)
31
==19224== by 0xA18D90: arm_load_kernel (boot.c:1317)
32
==19224== by 0x9F3651: machvirt_init (virt.c:2114)
33
==19224== by 0x794B7A: machine_run_board_init (machine.c:1272)
34
==19224== by 0xD5CAD3: qemu_init_board (vl.c:2618)
35
==19224== by 0xD5CCA6: qmp_x_exit_preconfig (vl.c:2692)
36
==19224== by 0xD5F32E: qemu_init (vl.c:3713)
37
==19224== by 0x5ADDB1: main (main.c:49)
38
39
Check that we have enough bytes of data to read the header bytes that
40
we read before we read them.
41
42
Fixes: Coverity 1458997
43
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
44
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
45
Message-id: 20210812141803.20913-1-peter.maydell@linaro.org
46
---
47
hw/core/loader.c | 35 +++++++++++++++++++++++++----------
48
1 file changed, 25 insertions(+), 10 deletions(-)
49
50
diff --git a/hw/core/loader.c b/hw/core/loader.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/hw/core/loader.c
53
+++ b/hw/core/loader.c
54
@@ -XXX,XX +XXX,XX @@ ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src, size_t srclen)
55
56
/* skip header */
57
i = 10;
58
+ if (srclen < 4) {
59
+ goto toosmall;
60
+ }
61
flags = src[3];
62
if (src[2] != DEFLATED || (flags & RESERVED) != 0) {
63
puts ("Error: Bad gzipped data\n");
64
return -1;
65
}
66
- if ((flags & EXTRA_FIELD) != 0)
67
+ if ((flags & EXTRA_FIELD) != 0) {
68
+ if (srclen < 12) {
69
+ goto toosmall;
70
+ }
71
i = 12 + src[10] + (src[11] << 8);
72
- if ((flags & ORIG_NAME) != 0)
73
- while (src[i++] != 0)
74
- ;
75
- if ((flags & COMMENT) != 0)
76
- while (src[i++] != 0)
77
- ;
78
- if ((flags & HEAD_CRC) != 0)
79
+ }
80
+ if ((flags & ORIG_NAME) != 0) {
81
+ while (i < srclen && src[i++] != 0) {
82
+ /* do nothing */
83
+ }
84
+ }
85
+ if ((flags & COMMENT) != 0) {
86
+ while (i < srclen && src[i++] != 0) {
87
+ /* do nothing */
88
+ }
89
+ }
90
+ if ((flags & HEAD_CRC) != 0) {
91
i += 2;
92
+ }
93
if (i >= srclen) {
94
- puts ("Error: gunzip out of data in header\n");
95
- return -1;
96
+ goto toosmall;
97
}
98
99
s.zalloc = zalloc;
100
@@ -XXX,XX +XXX,XX @@ ssize_t gunzip(void *dst, size_t dstlen, uint8_t *src, size_t srclen)
101
inflateEnd(&s);
102
103
return dstbytes;
104
+
105
+toosmall:
106
+ puts("Error: gunzip out of data in header\n");
107
+ return -1;
108
}
109
110
/* Load a U-Boot image. */
111
--
112
2.20.1
113
114
diff view generated by jsdifflib
New patch
[PULL 24/37] softmmu/physmem.c: Remove unneeded NULL check in qemu_ram_alloc_from_fd()
1
In the alignment check added to qemu_ram_alloc_from_fd() in commit
2
ce317be98db0dfdfa, the condition includes a check that 'mr' is not
3
NULL. This check is unnecessary because we can assume that the
4
caller always passes us a valid MemoryRegion, and indeed later in the
5
function we assume mr is not NULL when we pass it to file_ram_alloc()
6
as new_block->mr. Remove it.
1
7
8
Fixes: Coverity 1459867
9
Fixes: ce317be98d ("exec: fetch the alignment of Linux devdax pmem character device nodes")
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Jingqi Liu <jingqi.liu@intel.com>
12
Message-id: 20210812150624.29139-1-peter.maydell@linaro.org
13
---
14
softmmu/physmem.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/softmmu/physmem.c
20
+++ b/softmmu/physmem.c
21
@@ -XXX,XX +XXX,XX @@ RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr,
22
}
23
24
file_align = get_file_align(fd);
25
- if (file_align > 0 && mr && file_align > mr->align) {
26
+ if (file_align > 0 && file_align > mr->align) {
27
error_setg(errp, "backing store align 0x%" PRIx64
28
" is larger than 'align' option 0x%" PRIx64,
29
file_align, mr->align);
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
New patch
[PULL 25/37] softmmu/physmem.c: Check return value from realpath()
1
The realpath() function can return NULL on error, so we need to check
2
for it to avoid crashing when we try to strstr() into it.
3
This can happen if we run out of memory, or if /sys/ is not mounted,
4
among other situations.
1
5
6
Fixes: Coverity 1459913, 1460474
7
Fixes: ce317be98db0 ("exec: fetch the alignment of Linux devdax pmem character device nodes")
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Jingqi Liu <jingqi.liu@intel.com>
10
Message-id: 20210812151525.31456-1-peter.maydell@linaro.org
11
---
12
softmmu/physmem.c | 3 +++
13
1 file changed, 3 insertions(+)
14
15
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/softmmu/physmem.c
18
+++ b/softmmu/physmem.c
19
@@ -XXX,XX +XXX,XX @@ static int64_t get_file_align(int fd)
20
path = g_strdup_printf("/sys/dev/char/%d:%d",
21
major(st.st_rdev), minor(st.st_rdev));
22
rpath = realpath(path, NULL);
23
+ if (!rpath) {
24
+ return -errno;
25
+ }
26
27
rc = daxctl_new(&ctx);
28
if (rc) {
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
New patch
[PULL 26/37] net: Zero sockaddr_in in parse_host_port()
1
We don't currently zero-initialize the 'struct sockaddr_in' that
2
parse_host_port() fills in, so any fields we don't explicitly
3
initialize might be left as random garbage. POSIX states that
4
implementations may define extensions in sockaddr_in, and that those
5
extensions must not trigger if zero-initialized. So not zero
6
initializing might result in inadvertently triggering an impdef
7
extension.
1
8
9
memset() the sockaddr_in before we start to fill it in.
10
11
Fixes: Coverity CID 1005338
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Eric Blake <eblake@redhat.com>
14
Message-id: 20210813150506.7768-2-peter.maydell@linaro.org
15
---
16
net/net.c | 2 ++
17
1 file changed, 2 insertions(+)
18
19
diff --git a/net/net.c b/net/net.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/net/net.c
22
+++ b/net/net.c
23
@@ -XXX,XX +XXX,XX @@ int parse_host_port(struct sockaddr_in *saddr, const char *str,
24
const char *addr, *p, *r;
25
int port, ret = 0;
26
27
+ memset(saddr, 0, sizeof(*saddr));
28
+
29
substrings = g_strsplit(str, ":", 2);
30
if (!substrings || !substrings[0] || !substrings[1]) {
31
error_setg(errp, "host address '%s' doesn't contain ':' "
32
--
33
2.20.1
34
35
diff view generated by jsdifflib
New patch
[PULL 27/37] gdbstub: Zero-initialize sockaddr structs
1
Zero-initialize sockaddr_in and sockaddr_un structs that we're about
2
to fill in and pass to bind() or connect(), to ensure we don't leave
3
possible implementation-defined extension fields as uninitialized
4
garbage.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Eric Blake <eblake@redhat.com>
8
Message-id: 20210813150506.7768-3-peter.maydell@linaro.org
9
---
10
gdbstub.c | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/gdbstub.c b/gdbstub.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/gdbstub.c
16
+++ b/gdbstub.c
17
@@ -XXX,XX +XXX,XX @@ static bool gdb_accept_socket(int gdb_fd)
18
19
static int gdbserver_open_socket(const char *path)
20
{
21
- struct sockaddr_un sockaddr;
22
+ struct sockaddr_un sockaddr = {};
23
int fd, ret;
24
25
fd = socket(AF_UNIX, SOCK_STREAM, 0);
26
@@ -XXX,XX +XXX,XX @@ static int gdbserver_open_socket(const char *path)
27
28
static bool gdb_accept_tcp(int gdb_fd)
29
{
30
- struct sockaddr_in sockaddr;
31
+ struct sockaddr_in sockaddr = {};
32
socklen_t len;
33
int fd;
34
35
--
36
2.20.1
37
38
diff view generated by jsdifflib
New patch
[PULL 28/37] tests/qtest/ipmi-bt-test: Zero-initialize sockaddr struct
1
Zero-initialize the sockaddr_in struct that we're about to fill in
2
and pass to bind(), to ensure we don't leave possible
3
implementation-defined extension fields as uninitialized garbage.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Eric Blake <eblake@redhat.com>
7
Reviewed-by: Corey Minyard <cminyard@mvista.com>
8
Acked-by: Thomas Huth <thuth@redhat.com>
9
Message-id: 20210813150506.7768-4-peter.maydell@linaro.org
10
---
11
tests/qtest/ipmi-bt-test.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/tests/qtest/ipmi-bt-test.c b/tests/qtest/ipmi-bt-test.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/qtest/ipmi-bt-test.c
17
+++ b/tests/qtest/ipmi-bt-test.c
18
@@ -XXX,XX +XXX,XX @@ static void test_enable_irq(void)
19
*/
20
static void open_socket(void)
21
{
22
- struct sockaddr_in myaddr;
23
+ struct sockaddr_in myaddr = {};
24
socklen_t addrlen;
25
26
myaddr.sin_family = AF_INET;
27
--
28
2.20.1
29
30
diff view generated by jsdifflib
New patch
[PULL 29/37] tests/tcg/multiarch/linux-test: Zero-initialize sockaddr structs
1
Zero-initialize sockaddr_in and sockaddr_un structs that we're about
2
to fill in and pass to bind() or connect(), to ensure we don't leave
3
possible implementation-defined extension fields as uninitialized
4
garbage.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Eric Blake <eblake@redhat.com>
8
Message-id: 20210813150506.7768-5-peter.maydell@linaro.org
9
---
10
tests/tcg/multiarch/linux-test.c | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/tests/tcg/multiarch/linux-test.c b/tests/tcg/multiarch/linux-test.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/tests/tcg/multiarch/linux-test.c
16
+++ b/tests/tcg/multiarch/linux-test.c
17
@@ -XXX,XX +XXX,XX @@ static void test_time(void)
18
static int server_socket(void)
19
{
20
int val, fd;
21
- struct sockaddr_in sockaddr;
22
+ struct sockaddr_in sockaddr = {};
23
24
/* server socket */
25
fd = chk_error(socket(PF_INET, SOCK_STREAM, 0));
26
@@ -XXX,XX +XXX,XX @@ static int server_socket(void)
27
static int client_socket(uint16_t port)
28
{
29
int fd;
30
- struct sockaddr_in sockaddr;
31
+ struct sockaddr_in sockaddr = {};
32
33
/* server socket */
34
fd = chk_error(socket(PF_INET, SOCK_STREAM, 0));
35
--
36
2.20.1
37
38
diff view generated by jsdifflib
[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
[PULL 30/37] raspi: Use error_fatal for SoC realize errors, not error_abort
1
Use dup_const() instead of bitfield_replicate() in
1
The SoC realize can fail for legitimate reasons, because it propagates
2
disas_simd_mod_imm().
2
errors up from CPU realize, which in turn can be provoked by user
3
3
error in setting commandline options. Use error_fatal so we report
4
(We can't replace the other use of bitfield_replicate() in this file,
4
the error message to the user and exit, rather than asserting
5
in logic_imm_decode_wmask(), because that location needs to handle 2
5
via error_abort.
6
and 4 bit elements, which dup_const() cannot.)
7
6
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20210816135842.25302-2-peter.maydell@linaro.org
11
---
11
---
12
target/arm/translate-a64.c | 2 +-
12
hw/arm/raspi.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
17
--- a/hw/arm/raspi.c
18
+++ b/target/arm/translate-a64.c
18
+++ b/hw/arm/raspi.c
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
20
/* FMOV (vector, immediate) - half-precision */
20
object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram));
21
imm = vfp_expand_imm(MO_16, abcdefgh);
21
object_property_set_int(OBJECT(&s->soc), "board-rev", board_rev,
22
/* now duplicate across the lanes */
22
&error_abort);
23
- imm = bitfield_replicate(imm, 16);
23
- qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
24
+ imm = dup_const(MO_16, imm);
24
+ qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
25
} else {
25
26
imm = asimd_imm_const(abcdefgh, cmode, is_neg);
26
/* Create and plug in the SD cards */
27
}
27
di = drive_get_next(IF_SD);
28
--
28
--
29
2.20.1
29
2.20.1
30
30
31
31
diff view generated by jsdifflib
[PULL 24/24] target/arm: Implement MVE shifts by register
[PULL 31/37] target/arm: Avoid assertion trying to use KVM and multiple ASes
1
Implement the MVE shifts by register, which perform
1
KVM cannot support multiple address spaces per CPU; if you try to
2
shifts on a single general-purpose register.
2
create more than one then cpu_address_space_init() will assert.
3
3
4
In the Arm CPU realize function, detect the configurations which
5
would cause us to need more than one AS, and cleanly fail the
6
realize rather than blundering on into the assertion. This
7
turns this:
8
$ qemu-system-aarch64 -enable-kvm -display none -cpu max -machine raspi3b
9
qemu-system-aarch64: ../../softmmu/physmem.c:747: cpu_address_space_init: Assertion `asidx == 0 || !kvm_enabled()' failed.
10
Aborted
11
12
into:
13
$ qemu-system-aarch64 -enable-kvm -display none -machine raspi3b
14
qemu-system-aarch64: Cannot enable KVM when guest CPU has EL3 enabled
15
16
and this:
17
$ qemu-system-aarch64 -enable-kvm -display none -machine mps3-an524
18
qemu-system-aarch64: ../../softmmu/physmem.c:747: cpu_address_space_init: Assertion `asidx == 0 || !kvm_enabled()' failed.
19
Aborted
20
21
into:
22
$ qemu-system-aarch64 -enable-kvm -display none -machine mps3-an524
23
qemu-system-aarch64: Cannot enable KVM when using an M-profile guest CPU
24
25
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/528
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
28
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
29
Message-id: 20210816135842.25302-3-peter.maydell@linaro.org
7
---
30
---
8
target/arm/helper-mve.h | 2 ++
31
target/arm/cpu.c | 23 +++++++++++++++++++++++
9
target/arm/translate.h | 1 +
32
1 file changed, 23 insertions(+)
10
target/arm/t32.decode | 18 ++++++++++++++----
11
target/arm/mve_helper.c | 10 ++++++++++
12
target/arm/translate.c | 30 ++++++++++++++++++++++++++++++
13
5 files changed, 57 insertions(+), 4 deletions(-)
14
33
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
34
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
16
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-mve.h
36
--- a/target/arm/cpu.c
18
+++ b/target/arm/helper-mve.h
37
+++ b/target/arm/cpu.c
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
38
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
20
39
}
21
DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
22
DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
23
+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
24
+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
25
diff --git a/target/arm/translate.h b/target/arm/translate.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/translate.h
28
+++ b/target/arm/translate.h
29
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
30
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
31
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
32
typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
33
+typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
34
35
/**
36
* arm_tbflags_from_tb:
37
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/t32.decode
40
+++ b/target/arm/t32.decode
41
@@ -XXX,XX +XXX,XX @@
42
&mve_shl_ri rdalo rdahi shim
43
&mve_shl_rr rdalo rdahi rm
44
&mve_sh_ri rda shim
45
+&mve_sh_rr rda rm
46
47
# rdahi: bits [3:1] from insn, bit 0 is 1
48
# rdalo: bits [3:1] from insn, bit 0 is 0
49
@@ -XXX,XX +XXX,XX @@
50
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
51
@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
52
&mve_sh_ri shim=%imm5_12_6
53
+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
54
55
{
56
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
57
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
58
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
59
}
40
}
60
41
61
- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
42
+ if (kvm_enabled()) {
62
- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
43
+ /*
63
- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
44
+ * Catch all the cases which might cause us to create more than one
64
- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
45
+ * address space for the CPU (otherwise we will assert() later in
65
+ {
46
+ * cpu_address_space_init()).
66
+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr
47
+ */
67
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
48
+ if (arm_feature(env, ARM_FEATURE_M)) {
68
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
49
+ error_setg(errp,
50
+ "Cannot enable KVM when using an M-profile guest CPU");
51
+ return;
52
+ }
53
+ if (cpu->has_el3) {
54
+ error_setg(errp,
55
+ "Cannot enable KVM when guest CPU has EL3 enabled");
56
+ return;
57
+ }
58
+ if (cpu->tag_memory) {
59
+ error_setg(errp,
60
+ "Cannot enable KVM when guest CPUs has MTE enabled");
61
+ return;
62
+ }
69
+ }
63
+ }
70
+
64
+
71
+ {
65
{
72
+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr
66
uint64_t scale;
73
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
67
74
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
75
+ }
76
+
77
UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
78
SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
79
]
80
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/mve_helper.c
83
+++ b/target/arm/mve_helper.c
84
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
85
{
86
return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
87
}
88
+
89
+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
90
+{
91
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
92
+}
93
+
94
+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
95
+{
96
+ return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
97
+}
98
diff --git a/target/arm/translate.c b/target/arm/translate.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/translate.c
101
+++ b/target/arm/translate.c
102
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
103
return do_mve_sh_ri(s, a, gen_mve_uqshl);
104
}
105
106
+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
107
+{
108
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
109
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
110
+ return false;
111
+ }
112
+ if (!dc_isar_feature(aa32_mve, s) ||
113
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
114
+ a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
115
+ a->rm == a->rda) {
116
+ /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
117
+ unallocated_encoding(s);
118
+ return true;
119
+ }
120
+
121
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
122
+ fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
123
+ return true;
124
+}
125
+
126
+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
127
+{
128
+ return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
129
+}
130
+
131
+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
132
+{
133
+ return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
134
+}
135
+
136
/*
137
* Multiply and multiply accumulate
138
*/
139
--
68
--
140
2.20.1
69
2.20.1
141
70
142
71
diff view generated by jsdifflib
[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
[PULL 32/37] hw/arm/virt: Delete EL3 error checksnow provided in CPU realize
1
The A64 AdvSIMD modified-immediate grouping uses almost the same
1
Now that the CPU realize function will fail cleanly if we ask for EL3
2
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
2
when KVM is enabled, we don't need to check for errors explicitly in
3
which we add the AArch64-specific case for cmode 15 op 1) instead of
3
the virt board code. The reported message is slightly different;
4
reimplementing it all.
4
it is now:
5
qemu-system-aarch64: Cannot enable KVM when guest CPU has EL3 enabled
6
instead of:
7
qemu-system-aarch64: mach-virt: KVM does not support Security extensions
8
9
We don't delete the MTE check because there the logic is more
10
complex; deleting the check would work but makes the error message
11
less helpful, as it would read:
12
qemu-system-aarch64: MTE requested, but not supported by the guest CPU
13
instead of:
14
qemu-system-aarch64: mach-virt: KVM does not support providing MTE to the guest CPU
5
15
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
18
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Message-id: 20210816135842.25302-4-peter.maydell@linaro.org
9
---
20
---
10
target/arm/translate.h | 3 +-
21
hw/arm/virt.c | 5 -----
11
target/arm/translate-a64.c | 86 ++++----------------------------------
22
1 file changed, 5 deletions(-)
12
target/arm/translate.c | 17 +++++++-
13
3 files changed, 24 insertions(+), 82 deletions(-)
14
23
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
24
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
16
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.h
26
--- a/hw/arm/virt.c
18
+++ b/target/arm/translate.h
27
+++ b/hw/arm/virt.c
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
28
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
20
* VMVN and VBIC (when cmode < 14 && op == 1).
21
*
22
* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
23
- * callers must catch this.
24
+ * callers must catch this; we return the 64-bit constant value defined
25
+ * for AArch64.
26
*
27
* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
28
* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
29
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate-a64.c
32
+++ b/target/arm/translate-a64.c
33
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
34
{
35
int rd = extract32(insn, 0, 5);
36
int cmode = extract32(insn, 12, 4);
37
- int cmode_3_1 = extract32(cmode, 1, 3);
38
- int cmode_0 = extract32(cmode, 0, 1);
39
int o2 = extract32(insn, 11, 1);
40
uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
41
bool is_neg = extract32(insn, 29, 1);
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
43
return;
44
}
29
}
45
30
46
- /* See AdvSIMDExpandImm() in ARM ARM */
31
if (vms->secure) {
47
- switch (cmode_3_1) {
32
- if (kvm_enabled()) {
48
- case 0: /* Replicate(Zeros(24):imm8, 2) */
33
- error_report("mach-virt: KVM does not support Security extensions");
49
- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
34
- exit(1);
50
- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
51
- case 3: /* Replicate(imm8:Zeros(24), 2) */
52
- {
53
- int shift = cmode_3_1 * 8;
54
- imm = bitfield_replicate(abcdefgh << shift, 32);
55
- break;
56
- }
57
- case 4: /* Replicate(Zeros(8):imm8, 4) */
58
- case 5: /* Replicate(imm8:Zeros(8), 4) */
59
- {
60
- int shift = (cmode_3_1 & 0x1) * 8;
61
- imm = bitfield_replicate(abcdefgh << shift, 16);
62
- break;
63
- }
64
- case 6:
65
- if (cmode_0) {
66
- /* Replicate(Zeros(8):imm8:Ones(16), 2) */
67
- imm = (abcdefgh << 16) | 0xffff;
68
- } else {
69
- /* Replicate(Zeros(16):imm8:Ones(8), 2) */
70
- imm = (abcdefgh << 8) | 0xff;
71
- }
35
- }
72
- imm = bitfield_replicate(imm, 32);
73
- break;
74
- case 7:
75
- if (!cmode_0 && !is_neg) {
76
- imm = bitfield_replicate(abcdefgh, 8);
77
- } else if (!cmode_0 && is_neg) {
78
- int i;
79
- imm = 0;
80
- for (i = 0; i < 8; i++) {
81
- if ((abcdefgh) & (1 << i)) {
82
- imm |= 0xffULL << (i * 8);
83
- }
84
- }
85
- } else if (cmode_0) {
86
- if (is_neg) {
87
- imm = (abcdefgh & 0x3f) << 48;
88
- if (abcdefgh & 0x80) {
89
- imm |= 0x8000000000000000ULL;
90
- }
91
- if (abcdefgh & 0x40) {
92
- imm |= 0x3fc0000000000000ULL;
93
- } else {
94
- imm |= 0x4000000000000000ULL;
95
- }
96
- } else {
97
- if (o2) {
98
- /* FMOV (vector, immediate) - half-precision */
99
- imm = vfp_expand_imm(MO_16, abcdefgh);
100
- /* now duplicate across the lanes */
101
- imm = bitfield_replicate(imm, 16);
102
- } else {
103
- imm = (abcdefgh & 0x3f) << 19;
104
- if (abcdefgh & 0x80) {
105
- imm |= 0x80000000;
106
- }
107
- if (abcdefgh & 0x40) {
108
- imm |= 0x3e000000;
109
- } else {
110
- imm |= 0x40000000;
111
- }
112
- imm |= (imm << 32);
113
- }
114
- }
115
- }
116
- break;
117
- default:
118
- g_assert_not_reached();
119
- }
120
-
36
-
121
- if (cmode_3_1 != 7 && is_neg) {
37
/*
122
- imm = ~imm;
38
* The Secure view of the world is the same as the NonSecure,
123
+ if (cmode == 15 && o2 && !is_neg) {
39
* but with a few extra devices. Create it as a container region
124
+ /* FMOV (vector, immediate) - half-precision */
125
+ imm = vfp_expand_imm(MO_16, abcdefgh);
126
+ /* now duplicate across the lanes */
127
+ imm = bitfield_replicate(imm, 16);
128
+ } else {
129
+ imm = asimd_imm_const(abcdefgh, cmode, is_neg);
130
}
131
132
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
133
diff --git a/target/arm/translate.c b/target/arm/translate.c
134
index XXXXXXX..XXXXXXX 100644
135
--- a/target/arm/translate.c
136
+++ b/target/arm/translate.c
137
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
138
case 14:
139
if (op) {
140
/*
141
- * This is the only case where the top and bottom 32 bits
142
- * of the encoded constant differ.
143
+ * This and cmode == 15 op == 1 are the only cases where
144
+ * the top and bottom 32 bits of the encoded constant differ.
145
*/
146
uint64_t imm64 = 0;
147
int n;
148
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
149
imm |= (imm << 8) | (imm << 16) | (imm << 24);
150
break;
151
case 15:
152
+ if (op) {
153
+ /* Reserved encoding for AArch32; valid for AArch64 */
154
+ uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
155
+ if (imm & 0x80) {
156
+ imm64 |= 0x8000000000000000ULL;
157
+ }
158
+ if (imm & 0x40) {
159
+ imm64 |= 0x3fc0000000000000ULL;
160
+ } else {
161
+ imm64 |= 0x4000000000000000ULL;
162
+ }
163
+ return imm64;
164
+ }
165
imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
166
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
167
break;
168
--
40
--
169
2.20.1
41
2.20.1
170
42
171
43
diff view generated by jsdifflib
[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
[PULL 33/37] target/arm: Implement HSTR.TTEE
1
Implement the MVE vector shift right by immediate insns VSHRI and
1
In v7, the HSTR register has a TTEE bit which allows EL0/EL1 accesses
2
VRSHRI. As with Neon, we implement these by using helper functions
2
to the Thumb2EE TEECR and TEEHBR registers to be trapped to the
3
which perform left shifts but allow negative shift counts to indicate
3
hypervisor. Implement these traps.
4
right shifts.
5
4
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
7
Message-id: 20210816180305.20137-2-peter.maydell@linaro.org
9
---
8
---
10
target/arm/helper-mve.h | 12 ++++++++++++
9
target/arm/cpu.h | 2 ++
11
target/arm/translate.h | 20 ++++++++++++++++++++
10
target/arm/helper.c | 18 ++++++++++++++++--
12
target/arm/mve.decode | 28 ++++++++++++++++++++++++++++
11
2 files changed, 18 insertions(+), 2 deletions(-)
13
target/arm/mve_helper.c | 7 +++++++
14
target/arm/translate-mve.c | 5 +++++
15
target/arm/translate-neon.c | 18 ------------------
16
6 files changed, 72 insertions(+), 18 deletions(-)
17
12
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper-mve.h
15
--- a/target/arm/cpu.h
21
+++ b/target/arm/helper-mve.h
16
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
17
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
18
#define SCR_ENSCXT (1U << 25)
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
19
#define SCR_ATA (1U << 26)
25
20
26
+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
+#define HSTR_TTEE (1 << 16)
27
+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
22
+
30
DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
/* Return the current FPSCR value. */
31
DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
uint32_t vfp_get_fpscr(CPUARMState *env);
32
DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
33
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
diff --git a/target/arm/helper.c b/target/arm/helper.c
34
DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+
42
+DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
45
diff --git a/target/arm/translate.h b/target/arm/translate.h
46
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/translate.h
28
--- a/target/arm/helper.c
48
+++ b/target/arm/translate.h
29
+++ b/target/arm/helper.c
49
@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
30
@@ -XXX,XX +XXX,XX @@ static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
50
return x * 2 + 1;
31
env->teecr = value;
51
}
32
}
52
33
53
+static inline int rsub_64(DisasContext *s, int x)
34
+static CPAccessResult teecr_access(CPUARMState *env, const ARMCPRegInfo *ri,
35
+ bool isread)
54
+{
36
+{
55
+ return 64 - x;
37
+ /*
38
+ * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
39
+ * at all, so we don't need to check whether we're v8A.
40
+ */
41
+ if (arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) &&
42
+ (env->cp15.hstr_el2 & HSTR_TTEE)) {
43
+ return CP_ACCESS_TRAP_EL2;
44
+ }
45
+ return CP_ACCESS_OK;
56
+}
46
+}
57
+
47
+
58
+static inline int rsub_32(DisasContext *s, int x)
48
static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
59
+{
49
bool isread)
60
+ return 32 - x;
61
+}
62
+
63
+static inline int rsub_16(DisasContext *s, int x)
64
+{
65
+ return 16 - x;
66
+}
67
+
68
+static inline int rsub_8(DisasContext *s, int x)
69
+{
70
+ return 8 - x;
71
+}
72
+
73
static inline int arm_dc_feature(DisasContext *dc, int feature)
74
{
50
{
75
return (dc->features & (1ULL << feature)) != 0;
51
if (arm_current_el(env) == 0 && (env->teecr & 1)) {
76
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
52
return CP_ACCESS_TRAP;
77
index XXXXXXX..XXXXXXX 100644
53
}
78
--- a/target/arm/mve.decode
54
- return CP_ACCESS_OK;
79
+++ b/target/arm/mve.decode
55
+ return teecr_access(env, ri, isread);
80
@@ -XXX,XX +XXX,XX @@
81
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
82
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
83
84
+# Right shifts are encoded as N - shift, where N is the element size in bits.
85
+%rshift_i5 16:5 !function=rsub_32
86
+%rshift_i4 16:4 !function=rsub_16
87
+%rshift_i3 16:3 !function=rsub_8
88
+
89
+@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
90
+ size=0 shift=%rshift_i3
91
+@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
92
+ size=1 shift=%rshift_i4
93
+@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
94
+ size=2 shift=%rshift_i5
95
+
96
# Vector loads and stores
97
98
# Widening loads and narrowing stores:
99
@@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
100
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
101
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
102
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
103
+
104
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
105
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
106
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
107
+
108
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
109
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
110
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
111
+
112
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
113
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
114
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
115
+
116
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
117
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
118
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
119
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/arm/mve_helper.c
122
+++ b/target/arm/mve_helper.c
123
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
124
DO_2SHIFT(OP##b, 1, uint8_t, FN) \
125
DO_2SHIFT(OP##h, 2, uint16_t, FN) \
126
DO_2SHIFT(OP##w, 4, uint32_t, FN)
127
+#define DO_2SHIFT_S(OP, FN) \
128
+ DO_2SHIFT(OP##b, 1, int8_t, FN) \
129
+ DO_2SHIFT(OP##h, 2, int16_t, FN) \
130
+ DO_2SHIFT(OP##w, 4, int32_t, FN)
131
132
#define DO_2SHIFT_SAT_U(OP, FN) \
133
DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
134
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
135
DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
136
137
DO_2SHIFT_U(vshli_u, DO_VSHLU)
138
+DO_2SHIFT_S(vshli_s, DO_VSHLS)
139
DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
140
DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
141
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
142
+DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
143
+DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
144
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
145
index XXXXXXX..XXXXXXX 100644
146
--- a/target/arm/translate-mve.c
147
+++ b/target/arm/translate-mve.c
148
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
149
DO_2SHIFT(VQSHLI_S, vqshli_s, false)
150
DO_2SHIFT(VQSHLI_U, vqshli_u, false)
151
DO_2SHIFT(VQSHLUI, vqshlui_s, false)
152
+/* These right shifts use a left-shift helper with negated shift count */
153
+DO_2SHIFT(VSHRI_S, vshli_s, true)
154
+DO_2SHIFT(VSHRI_U, vshli_u, true)
155
+DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
+DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/target/arm/translate-neon.c
160
+++ b/target/arm/translate-neon.c
161
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
162
return x + 1;
163
}
56
}
164
57
165
-static inline int rsub_64(DisasContext *s, int x)
58
static const ARMCPRegInfo t2ee_cp_reginfo[] = {
166
-{
59
{ .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
167
- return 64 - x;
60
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
168
-}
61
.resetvalue = 0,
169
-
62
- .writefn = teecr_write },
170
-static inline int rsub_32(DisasContext *s, int x)
63
+ .writefn = teecr_write, .accessfn = teecr_access },
171
-{
64
{ .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
172
- return 32 - x;
65
.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
173
-}
66
.accessfn = teehbr_access, .resetvalue = 0 },
174
-static inline int rsub_16(DisasContext *s, int x)
175
-{
176
- return 16 - x;
177
-}
178
-static inline int rsub_8(DisasContext *s, int x)
179
-{
180
- return 8 - x;
181
-}
182
-
183
static inline int neon_3same_fp_size(DisasContext *s, int x)
184
{
185
/* Convert 0==fp32, 1==fp16 into a MO_* value */
186
--
67
--
187
2.20.1
68
2.20.1
188
69
189
70
diff view generated by jsdifflib
[PULL 22/24] target/arm: Implement MVE long shifts by register
[PULL 34/37] target/arm: Implement HSTR.TJDBX
1
Implement the MVE long shifts by register, which perform shifts on a
1
In v7A, the HSTR register has a TJDBX bit which traps NS EL0/EL1
2
pair of general-purpose registers treated as a 64-bit quantity, with
2
access to the JOSCR and JMCR trivial Jazelle registers, and also BXJ.
3
the shift count in another general-purpose register, which might be
3
Implement these traps. In v8A this HSTR bit doesn't exist, so don't
4
either positive or negative.
4
trap for v8A CPUs.
5
6
Like the long-shifts-by-immediate, these encodings sit in the space
7
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
8
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
9
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
10
we have to move the CSEL pattern into the same decodetree group.
11
5
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
8
Message-id: 20210816180305.20137-3-peter.maydell@linaro.org
15
---
9
---
16
target/arm/helper-mve.h | 6 +++
10
target/arm/cpu.h | 1 +
17
target/arm/translate.h | 1 +
11
target/arm/helper.h | 2 ++
18
target/arm/t32.decode | 16 +++++--
12
target/arm/syndrome.h | 7 +++++++
19
target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
13
target/arm/helper.c | 17 +++++++++++++++++
20
target/arm/translate.c | 69 ++++++++++++++++++++++++++++++
14
target/arm/op_helper.c | 16 ++++++++++++++++
21
5 files changed, 182 insertions(+), 3 deletions(-)
15
target/arm/translate.c | 12 ++++++++++++
16
6 files changed, 55 insertions(+)
22
17
23
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/helper-mve.h
20
--- a/target/arm/cpu.h
26
+++ b/target/arm/helper-mve.h
21
+++ b/target/arm/cpu.h
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
28
23
#define SCR_ATA (1U << 26)
29
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
24
30
25
#define HSTR_TTEE (1 << 16)
31
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
26
+#define HSTR_TJDBX (1 << 17)
32
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
27
33
DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
28
/* Return the current FPSCR value. */
34
DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
29
uint32_t vfp_get_fpscr(CPUARMState *env);
35
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
30
diff --git a/target/arm/helper.h b/target/arm/helper.h
36
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
37
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
38
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
39
diff --git a/target/arm/translate.h b/target/arm/translate.h
40
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/translate.h
32
--- a/target/arm/helper.h
42
+++ b/target/arm/translate.h
33
+++ b/target/arm/helper.h
43
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
34
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(v7m_vlldm, void, env, i32)
44
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
35
45
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
36
DEF_HELPER_2(v8m_stackcheck, void, env, i32)
46
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
37
47
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
38
+DEF_HELPER_FLAGS_2(check_bxj_trap, TCG_CALL_NO_WG, void, env, i32)
48
39
+
49
/**
40
DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32)
50
* arm_tbflags_from_tb:
41
DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)
51
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
42
DEF_HELPER_2(get_cp_reg, i32, env, ptr)
43
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
52
index XXXXXXX..XXXXXXX 100644
44
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/t32.decode
45
--- a/target/arm/syndrome.h
54
+++ b/target/arm/t32.decode
46
+++ b/target/arm/syndrome.h
55
@@ -XXX,XX +XXX,XX @@
47
@@ -XXX,XX +XXX,XX @@ enum arm_exception_class {
56
&mcrr !extern cp opc1 crm rt rt2
48
EC_ADVSIMDFPACCESSTRAP = 0x07,
57
49
EC_FPIDTRAP = 0x08,
58
&mve_shl_ri rdalo rdahi shim
50
EC_PACTRAP = 0x09,
59
+&mve_shl_rr rdalo rdahi rm
51
+ EC_BXJTRAP = 0x0a,
60
52
EC_CP14RRTTRAP = 0x0c,
61
# rdahi: bits [3:1] from insn, bit 0 is 1
53
EC_BTITRAP = 0x0d,
62
# rdalo: bits [3:1] from insn, bit 0 is 0
54
EC_ILLEGALSTATE = 0x0e,
63
@@ -XXX,XX +XXX,XX @@
55
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_btitrap(int btype)
64
56
return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype;
65
@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
66
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
67
+@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
68
+ &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
69
70
{
71
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
72
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
73
URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
74
SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
75
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
76
+
77
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
78
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
79
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
80
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
81
+ UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
82
+ SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
83
]
84
85
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
86
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
87
+
88
+ # v8.1M CSEL and friends
89
+ CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
90
}
57
}
91
{
58
92
MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
59
+static inline uint32_t syn_bxjtrap(int cv, int cond, int rm)
93
@@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
94
}
95
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
96
97
-# v8.1M CSEL and friends
98
-CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
99
-
100
# Data-processing (register-shifted register)
101
102
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
103
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/arm/mve_helper.c
106
+++ b/target/arm/mve_helper.c
107
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
108
return rdm;
109
}
110
111
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
112
+{
60
+{
113
+ return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
61
+ return (EC_BXJTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL |
62
+ (cv << 24) | (cond << 20) | rm;
114
+}
63
+}
115
+
64
+
116
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
65
static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
66
{
67
return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
68
diff --git a/target/arm/helper.c b/target/arm/helper.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/target/arm/helper.c
71
+++ b/target/arm/helper.c
72
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri,
73
return CP_ACCESS_OK;
74
}
75
76
+static CPAccessResult access_joscr_jmcr(CPUARMState *env,
77
+ const ARMCPRegInfo *ri, bool isread)
117
+{
78
+{
118
+ return do_uqrshl_d(n, (int8_t)shift, false, NULL);
79
+ /*
80
+ * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
81
+ * in v7A, not in v8A.
82
+ */
83
+ if (!arm_feature(env, ARM_FEATURE_V8) &&
84
+ arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) &&
85
+ (env->cp15.hstr_el2 & HSTR_TJDBX)) {
86
+ return CP_ACCESS_TRAP_EL2;
87
+ }
88
+ return CP_ACCESS_OK;
119
+}
89
+}
120
+
90
+
121
uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
91
static const ARMCPRegInfo jazelle_regs[] = {
122
{
92
{ .name = "JIDR",
123
return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
93
.cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0,
124
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
94
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
125
{
95
.type = ARM_CP_CONST, .resetvalue = 0 },
126
return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
96
{ .name = "JOSCR",
97
.cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0,
98
+ .accessfn = access_joscr_jmcr,
99
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
100
{ .name = "JMCR",
101
.cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0,
102
+ .accessfn = access_joscr_jmcr,
103
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
104
REGINFO_SENTINEL
105
};
106
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/op_helper.c
109
+++ b/target/arm/op_helper.c
110
@@ -XXX,XX +XXX,XX @@ void HELPER(setend)(CPUARMState *env)
111
arm_rebuild_hflags(env);
127
}
112
}
128
+
113
129
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
114
+void HELPER(check_bxj_trap)(CPUARMState *env, uint32_t rm)
130
+{
115
+{
131
+ return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
116
+ /*
117
+ * Only called if in NS EL0 or EL1 for a BXJ for a v7A CPU;
118
+ * check if HSTR.TJDBX means we need to trap to EL2.
119
+ */
120
+ if (env->cp15.hstr_el2 & HSTR_TJDBX) {
121
+ /*
122
+ * We know the condition code check passed, so take the IMPDEF
123
+ * choice to always report CV=1 COND 0xe
124
+ */
125
+ uint32_t syn = syn_bxjtrap(1, 0xe, rm);
126
+ raise_exception_ra(env, EXCP_HYP_TRAP, syn, 2, GETPC());
127
+ }
132
+}
128
+}
133
+
129
+
134
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
130
#ifndef CONFIG_USER_ONLY
135
+{
131
/* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
136
+ return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
132
* The function returns the target EL (1-3) if the instruction is to be trapped;
137
+}
138
+
139
+/* Operate on 64-bit values, but saturate at 48 bits */
140
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
141
+ bool round, uint32_t *sat)
142
+{
143
+ if (shift <= -48) {
144
+ /* Rounding the sign bit always produces 0. */
145
+ if (round) {
146
+ return 0;
147
+ }
148
+ return src >> 63;
149
+ } else if (shift < 0) {
150
+ if (round) {
151
+ src >>= -shift - 1;
152
+ return (src >> 1) + (src & 1);
153
+ }
154
+ return src >> -shift;
155
+ } else if (shift < 48) {
156
+ int64_t val = src << shift;
157
+ int64_t extval = sextract64(val, 0, 48);
158
+ if (!sat || val == extval) {
159
+ return extval;
160
+ }
161
+ } else if (!sat || src == 0) {
162
+ return 0;
163
+ }
164
+
165
+ *sat = 1;
166
+ return (1ULL << 47) - (src >= 0);
167
+}
168
+
169
+/* Operate on 64-bit values, but saturate at 48 bits */
170
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
171
+ bool round, uint32_t *sat)
172
+{
173
+ uint64_t val, extval;
174
+
175
+ if (shift <= -(48 + round)) {
176
+ return 0;
177
+ } else if (shift < 0) {
178
+ if (round) {
179
+ val = src >> (-shift - 1);
180
+ val = (val >> 1) + (val & 1);
181
+ } else {
182
+ val = src >> -shift;
183
+ }
184
+ extval = extract64(val, 0, 48);
185
+ if (!sat || val == extval) {
186
+ return extval;
187
+ }
188
+ } else if (shift < 48) {
189
+ uint64_t val = src << shift;
190
+ uint64_t extval = extract64(val, 0, 48);
191
+ if (!sat || val == extval) {
192
+ return extval;
193
+ }
194
+ } else if (!sat || src == 0) {
195
+ return 0;
196
+ }
197
+
198
+ *sat = 1;
199
+ return MAKE_64BIT_MASK(0, 48);
200
+}
201
+
202
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
203
+{
204
+ return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
205
+}
206
+
207
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
208
+{
209
+ return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
210
+}
211
diff --git a/target/arm/translate.c b/target/arm/translate.c
133
diff --git a/target/arm/translate.c b/target/arm/translate.c
212
index XXXXXXX..XXXXXXX 100644
134
index XXXXXXX..XXXXXXX 100644
213
--- a/target/arm/translate.c
135
--- a/target/arm/translate.c
214
+++ b/target/arm/translate.c
136
+++ b/target/arm/translate.c
215
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
137
@@ -XXX,XX +XXX,XX @@ static bool trans_BXJ(DisasContext *s, arg_BXJ *a)
216
return do_mve_shl_ri(s, a, gen_urshr64_i64);
138
if (!ENABLE_ARCH_5J || arm_dc_feature(s, ARM_FEATURE_M)) {
217
}
139
return false;
218
140
}
219
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
141
+ /*
220
+{
142
+ * v7A allows BXJ to be trapped via HSTR.TJDBX. We don't waste a
221
+ TCGv_i64 rda;
143
+ * TBFLAGS bit on a basically-never-happens case, so call a helper
222
+ TCGv_i32 rdalo, rdahi;
144
+ * function to check for the trap and raise the exception if needed
223
+
145
+ * (passing it the register number for the syndrome value).
224
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
146
+ * v8A doesn't have this HSTR bit.
225
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
147
+ */
226
+ return false;
148
+ if (!arm_dc_feature(s, ARM_FEATURE_V8) &&
149
+ arm_dc_feature(s, ARM_FEATURE_EL2) &&
150
+ s->current_el < 2 && s->ns) {
151
+ gen_helper_check_bxj_trap(cpu_env, tcg_constant_i32(a->rm));
227
+ }
152
+ }
228
+ if (a->rdahi == 15) {
153
/* Trivial implementation equivalent to bx. */
229
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
154
gen_bx(s, load_reg(s, a->rm));
230
+ return false;
155
return true;
231
+ }
232
+ if (!dc_isar_feature(aa32_mve, s) ||
233
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
234
+ a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
235
+ a->rm == a->rdahi || a->rm == a->rdalo) {
236
+ /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
237
+ unallocated_encoding(s);
238
+ return true;
239
+ }
240
+
241
+ rda = tcg_temp_new_i64();
242
+ rdalo = load_reg(s, a->rdalo);
243
+ rdahi = load_reg(s, a->rdahi);
244
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
245
+
246
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
247
+ fn(rda, cpu_env, rda, cpu_R[a->rm]);
248
+
249
+ tcg_gen_extrl_i64_i32(rdalo, rda);
250
+ tcg_gen_extrh_i64_i32(rdahi, rda);
251
+ store_reg(s, a->rdalo, rdalo);
252
+ store_reg(s, a->rdahi, rdahi);
253
+ tcg_temp_free_i64(rda);
254
+
255
+ return true;
256
+}
257
+
258
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
259
+{
260
+ return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
261
+}
262
+
263
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
264
+{
265
+ return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
266
+}
267
+
268
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
269
+{
270
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
271
+}
272
+
273
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
274
+{
275
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
276
+}
277
+
278
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
279
+{
280
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
281
+}
282
+
283
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
284
+{
285
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
286
+}
287
+
288
/*
289
* Multiply and multiply accumulate
290
*/
291
--
156
--
292
2.20.1
157
2.20.1
293
158
294
159
diff view generated by jsdifflib
[PULL 09/24] target/arm: Make asimd_imm_const() public
[PULL 35/37] target/arm: Do hflags rebuild in cpsr_write()
1
The function asimd_imm_const() in translate-neon.c is an
1
Currently we rely on all the callsites of cpsr_write() to rebuild the
2
implementation of the pseudocode AdvSIMDExpandImm(), which we will
2
cached hflags if they change one of the CPSR bits which we use as a
3
also want for MVE. Move the implementation to translate.c, with a
3
TB flag and cache in hflags. This is a bit awkward when we want to
4
prototype in translate.h.
4
change the set of CPSR bits that we cache, because it means we need
5
to re-audit all the cpsr_write() callsites to see which flags they
6
are writing and whether they now need to rebuild the hflags.
7
8
Switch instead to making cpsr_write() call arm_rebuild_hflags()
9
itself if one of the bits being changed is a cached bit.
10
11
We don't do the rebuild for the CPSRWriteRaw write type, because that
12
kind of write is generally doing something special anyway. For the
13
CPSRWriteRaw callsites in the KVM code and inbound migration we
14
definitely don't want to recalculate the hflags; the callsites in
15
boot.c and arm-powerctl.c have to do a rebuild-hflags call themselves
16
anyway because of other CPU state changes they make.
17
18
This allows us to drop explicit arm_rebuild_hflags() calls in a
19
couple of places where the only reason we needed to call it was the
20
CPSR write.
21
22
This fixes a bug where we were incorrectly failing to rebuild hflags
23
in the code path for a gdbstub write to CPSR, which meant that you
24
could make QEMU assert by breaking into a running guest, altering the
25
CPSR to change the value of, for example, CPSR.E, and then
26
continuing.
5
27
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
29
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
30
Message-id: 20210817201843.3829-1-peter.maydell@linaro.org
9
---
31
---
10
target/arm/translate.h | 16 ++++++++++
32
target/arm/cpu.h | 10 ++++++++--
11
target/arm/translate-neon.c | 63 -------------------------------------
33
linux-user/arm/signal.c | 2 --
12
target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++
34
target/arm/helper.c | 5 +++++
13
3 files changed, 73 insertions(+), 63 deletions(-)
35
3 files changed, 13 insertions(+), 4 deletions(-)
14
36
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
37
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.h
39
--- a/target/arm/cpu.h
18
+++ b/target/arm/translate.h
40
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
41
@@ -XXX,XX +XXX,XX @@ uint32_t cpsr_read(CPUARMState *env);
20
return opc | s->be_data;
42
typedef enum CPSRWriteType {
43
CPSRWriteByInstr = 0, /* from guest MSR or CPS */
44
CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
45
- CPSRWriteRaw = 2, /* trust values, do not switch reg banks */
46
+ CPSRWriteRaw = 2,
47
+ /* trust values, no reg bank switch, no hflags rebuild */
48
CPSRWriteByGDBStub = 3, /* from the GDB stub */
49
} CPSRWriteType;
50
51
-/* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/
52
+/*
53
+ * Set the CPSR. Note that some bits of mask must be all-set or all-clear.
54
+ * This will do an arm_rebuild_hflags() if any of the bits in @mask
55
+ * correspond to TB flags bits cached in the hflags, unless @write_type
56
+ * is CPSRWriteRaw.
57
+ */
58
void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
59
CPSRWriteType write_type);
60
61
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/linux-user/arm/signal.c
64
+++ b/linux-user/arm/signal.c
65
@@ -XXX,XX +XXX,XX @@ setup_return(CPUARMState *env, struct target_sigaction *ka,
66
env->regs[14] = retcode;
67
env->regs[15] = handler & (thumb ? ~1 : ~3);
68
cpsr_write(env, cpsr, CPSR_IT | CPSR_T | CPSR_E, CPSRWriteByInstr);
69
- arm_rebuild_hflags(env);
70
71
return 0;
21
}
72
}
22
73
@@ -XXX,XX +XXX,XX @@ restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)
23
+/**
74
__get_user(env->regs[15], &sc->arm_pc);
24
+ * asimd_imm_const: Expand an encoded SIMD constant value
75
__get_user(cpsr, &sc->arm_cpsr);
25
+ *
76
cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
26
+ * Expand a SIMD constant value. This is essentially the pseudocode
77
- arm_rebuild_hflags(env);
27
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
78
28
+ * VMVN and VBIC (when cmode < 14 && op == 1).
79
err |= !valid_user_regs(env);
29
+ *
80
30
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
81
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
+ * callers must catch this.
32
+ *
33
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
34
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
35
+ * we produce an immediate constant value of 0 in these cases.
36
+ */
37
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
38
+
39
#endif /* TARGET_ARM_TRANSLATE_H */
40
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
41
index XXXXXXX..XXXXXXX 100644
82
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/translate-neon.c
83
--- a/target/arm/helper.c
43
+++ b/target/arm/translate-neon.c
84
+++ b/target/arm/helper.c
44
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
85
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
45
DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
86
CPSRWriteType write_type)
46
DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
47
48
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
49
-{
50
- /*
51
- * Expand the encoded constant.
52
- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
53
- * We choose to not special-case this and will behave as if a
54
- * valid constant encoding of 0 had been given.
55
- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
56
- */
57
- switch (cmode) {
58
- case 0: case 1:
59
- /* no-op */
60
- break;
61
- case 2: case 3:
62
- imm <<= 8;
63
- break;
64
- case 4: case 5:
65
- imm <<= 16;
66
- break;
67
- case 6: case 7:
68
- imm <<= 24;
69
- break;
70
- case 8: case 9:
71
- imm |= imm << 16;
72
- break;
73
- case 10: case 11:
74
- imm = (imm << 8) | (imm << 24);
75
- break;
76
- case 12:
77
- imm = (imm << 8) | 0xff;
78
- break;
79
- case 13:
80
- imm = (imm << 16) | 0xffff;
81
- break;
82
- case 14:
83
- if (op) {
84
- /*
85
- * This is the only case where the top and bottom 32 bits
86
- * of the encoded constant differ.
87
- */
88
- uint64_t imm64 = 0;
89
- int n;
90
-
91
- for (n = 0; n < 8; n++) {
92
- if (imm & (1 << n)) {
93
- imm64 |= (0xffULL << (n * 8));
94
- }
95
- }
96
- return imm64;
97
- }
98
- imm |= (imm << 8) | (imm << 16) | (imm << 24);
99
- break;
100
- case 15:
101
- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
102
- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
103
- break;
104
- }
105
- if (op) {
106
- imm = ~imm;
107
- }
108
- return dup_const(MO_32, imm);
109
-}
110
-
111
static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
112
GVecGen2iFn *fn)
113
{
87
{
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
88
uint32_t changed_daif;
115
index XXXXXXX..XXXXXXX 100644
89
+ bool rebuild_hflags = (write_type != CPSRWriteRaw) &&
116
--- a/target/arm/translate.c
90
+ (mask & (CPSR_M | CPSR_E | CPSR_IL));
117
+++ b/target/arm/translate.c
91
118
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
92
if (mask & CPSR_NZCV) {
119
a64_translate_init();
93
env->ZF = (~val) & CPSR_Z;
94
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
95
}
96
mask &= ~CACHED_CPSR_BITS;
97
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
98
+ if (rebuild_hflags) {
99
+ arm_rebuild_hflags(env);
100
+ }
120
}
101
}
121
102
122
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
103
/* Sign/zero extend */
123
+{
124
+ /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
125
+ switch (cmode) {
126
+ case 0: case 1:
127
+ /* no-op */
128
+ break;
129
+ case 2: case 3:
130
+ imm <<= 8;
131
+ break;
132
+ case 4: case 5:
133
+ imm <<= 16;
134
+ break;
135
+ case 6: case 7:
136
+ imm <<= 24;
137
+ break;
138
+ case 8: case 9:
139
+ imm |= imm << 16;
140
+ break;
141
+ case 10: case 11:
142
+ imm = (imm << 8) | (imm << 24);
143
+ break;
144
+ case 12:
145
+ imm = (imm << 8) | 0xff;
146
+ break;
147
+ case 13:
148
+ imm = (imm << 16) | 0xffff;
149
+ break;
150
+ case 14:
151
+ if (op) {
152
+ /*
153
+ * This is the only case where the top and bottom 32 bits
154
+ * of the encoded constant differ.
155
+ */
156
+ uint64_t imm64 = 0;
157
+ int n;
158
+
159
+ for (n = 0; n < 8; n++) {
160
+ if (imm & (1 << n)) {
161
+ imm64 |= (0xffULL << (n * 8));
162
+ }
163
+ }
164
+ return imm64;
165
+ }
166
+ imm |= (imm << 8) | (imm << 16) | (imm << 24);
167
+ break;
168
+ case 15:
169
+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
170
+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
171
+ break;
172
+ }
173
+ if (op) {
174
+ imm = ~imm;
175
+ }
176
+ return dup_const(MO_32, imm);
177
+}
178
+
179
/* Generate a label used for skipping this instruction */
180
void arm_gen_condlabel(DisasContext *s)
181
{
182
--
104
--
183
2.20.1
105
2.20.1
184
106
185
107
diff view generated by jsdifflib
[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
[PULL 36/37] hw/arm/xlnx-versal: Add unimplemented APU mmio
1
From: Patrick Venture <venture@google.com>
1
From: Tong Ho <tong.ho@xilinx.com>
2
2
3
Add line item reference to quanta-gbs-bmc machine.
3
Add unimplemented APU mmio region to xlnx-versal for booting
4
bare-metal guests built with standalone bsp, which access the
5
region from one of the following places:
6
https://github.com/Xilinx/embeddedsw/blob/release-2020.2/lib/bsp/standalone/src/arm/ARMv8/64bit/armclang/boot.S#L139
7
https://github.com/Xilinx/embeddedsw/blob/release-2020.2/lib/bsp/standalone/src/arm/ARMv8/64bit/gcc/boot.S#L183
4
8
5
Signed-off-by: Patrick Venture <venture@google.com>
9
Acked-by: Alistair Francis <alistair.francis@wdc.com>
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
10
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Message-id: 20210615192848.1065297-3-venture@google.com
11
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
8
[PMM: fixed underline Sphinx warning]
12
Message-id: 20210823173818.201259-2-tong.ho@xilinx.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
14
---
11
docs/system/arm/nuvoton.rst | 5 +++--
15
include/hw/arm/xlnx-versal.h | 2 ++
12
1 file changed, 3 insertions(+), 2 deletions(-)
16
hw/arm/xlnx-versal.c | 2 ++
17
2 files changed, 4 insertions(+)
13
18
14
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
19
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/nuvoton.rst
21
--- a/include/hw/arm/xlnx-versal.h
17
+++ b/docs/system/arm/nuvoton.rst
22
+++ b/include/hw/arm/xlnx-versal.h
18
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ struct Versal {
19
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
24
#define MM_IOU_SCNTRS_SIZE 0x10000
20
-=====================================================
25
#define MM_FPD_CRF 0xfd1a0000U
21
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
26
#define MM_FPD_CRF_SIZE 0x140000
22
+================================================================
27
+#define MM_FPD_FPD_APU 0xfd5c0000
23
28
+#define MM_FPD_FPD_APU_SIZE 0x100
24
The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
29
25
designed to be used as Baseboard Management Controllers (BMCs) in various
30
#define MM_PMC_SD0 0xf1040000U
26
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
31
#define MM_PMC_SD0_SIZE 0x10000
27
The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
32
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
28
Hyperscale applications. The following machines are based on this chip :
33
index XXXXXXX..XXXXXXX 100644
29
34
--- a/hw/arm/xlnx-versal.c
30
+- ``quanta-gbs-bmc`` Quanta GBS server BMC
35
+++ b/hw/arm/xlnx-versal.c
31
- ``quanta-gsj`` Quanta GSJ server BMC
36
@@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s)
32
37
MM_CRL, MM_CRL_SIZE);
33
There are also two more SoCs, NPCM710 and NPCM705, which are single-core
38
versal_unimp_area(s, "crf", &s->mr_ps,
39
MM_FPD_CRF, MM_FPD_CRF_SIZE);
40
+ versal_unimp_area(s, "apu", &s->mr_ps,
41
+ MM_FPD_FPD_APU, MM_FPD_FPD_APU_SIZE);
42
versal_unimp_area(s, "crp", &s->mr_ps,
43
MM_PMC_CRP, MM_PMC_CRP_SIZE);
44
versal_unimp_area(s, "iou-scntr", &s->mr_ps,
34
--
45
--
35
2.20.1
46
2.20.1
36
47
37
48
diff view generated by jsdifflib
[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
[PULL 37/37] hw/arm/xlnx-zynqmp: Add unimplemented APU mmio
1
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
1
From: Tong Ho <tong.ho@xilinx.com>
2
2
3
do_urshr() is borrowed from sve_helper.c.
3
Add unimplemented APU mmio region to xlnx-zynqmp for booting
4
bare-metal guests built with standalone bsp, which access the
5
region from one of the following places:
6
https://github.com/Xilinx/embeddedsw/blob/release-2020.2/lib/bsp/standalone/src/arm/ARMv8/64bit/armclang/boot.S#L139
7
https://github.com/Xilinx/embeddedsw/blob/release-2020.2/lib/bsp/standalone/src/arm/ARMv8/64bit/gcc/boot.S#L183
4
8
9
Acked-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
11
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
12
Message-id: 20210823173818.201259-3-tong.ho@xilinx.com
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
8
---
14
---
9
target/arm/helper-mve.h | 10 ++++++++++
15
include/hw/arm/xlnx-zynqmp.h | 7 +++++++
10
target/arm/mve.decode | 11 +++++++++++
16
hw/arm/xlnx-zynqmp.c | 32 ++++++++++++++++++++++++++++++++
11
target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++
17
2 files changed, 39 insertions(+)
12
target/arm/translate-mve.c | 15 ++++++++++++++
13
4 files changed, 76 insertions(+)
14
18
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
19
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-mve.h
21
--- a/include/hw/arm/xlnx-zynqmp.h
18
+++ b/target/arm/helper-mve.h
22
+++ b/include/hw/arm/xlnx-zynqmp.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
20
DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
21
DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
22
DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
27
+/*
28
+ * Unimplemented mmio regions needed to boot some images.
29
+ */
30
+#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
23
+
31
+
24
+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
struct XlnxZynqMPState {
25
+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
/*< private >*/
26
+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
DeviceState parent_obj;
27
+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
36
MemoryRegion *ddr_ram;
37
MemoryRegion ddr_ram_low, ddr_ram_high;
38
39
+ MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
28
+
40
+
29
+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
30
+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
31
+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN];
32
+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
46
--- a/hw/arm/xlnx-zynqmp.c
36
+++ b/target/arm/mve.decode
47
+++ b/hw/arm/xlnx-zynqmp.c
37
@@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
48
@@ -XXX,XX +XXX,XX @@
38
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
49
#include "qemu/module.h"
39
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
50
#include "hw/arm/xlnx-zynqmp.h"
40
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
51
#include "hw/intc/arm_gic_common.h"
52
+#include "hw/misc/unimp.h"
53
#include "hw/boards.h"
54
#include "sysemu/kvm.h"
55
#include "sysemu/sysemu.h"
56
@@ -XXX,XX +XXX,XX @@
57
#define DPDMA_ADDR 0xfd4c0000
58
#define DPDMA_IRQ 116
59
60
+#define APU_ADDR 0xfd5c0000
61
+#define APU_SIZE 0x100
41
+
62
+
42
+# Narrowing shifts (which only support b and h sizes)
63
#define IPI_ADDR 0xFF300000
43
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
64
#define IPI_IRQ 64
44
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
65
45
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
66
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
46
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
67
qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
68
}
69
70
+static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
71
+{
72
+ static const struct UnimpInfo {
73
+ const char *name;
74
+ hwaddr base;
75
+ hwaddr size;
76
+ } unimp_areas[ARRAY_SIZE(s->mr_unimp)] = {
77
+ { .name = "apu", APU_ADDR, APU_SIZE },
78
+ };
79
+ unsigned int nr;
47
+
80
+
48
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
81
+ for (nr = 0; nr < ARRAY_SIZE(unimp_areas); nr++) {
49
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
82
+ const struct UnimpInfo *info = &unimp_areas[nr];
50
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
83
+ DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
51
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
84
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
52
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/mve_helper.c
55
+++ b/target/arm/mve_helper.c
56
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
57
58
DO_VSHLL_ALL(vshllb, false)
59
DO_VSHLL_ALL(vshllt, true)
60
+
85
+
61
+/*
86
+ assert(info->name && info->base && info->size > 0);
62
+ * Narrowing right shifts, taking a double sized input, shifting it
87
+ qdev_prop_set_string(dev, "name", info->name);
63
+ * and putting the result in either the top or bottom half of the output.
88
+ qdev_prop_set_uint64(dev, "size", info->size);
64
+ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
89
+ object_property_add_child(OBJECT(s), info->name, OBJECT(dev));
65
+ */
66
+#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
67
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
68
+ void *vm, uint32_t shift) \
69
+ { \
70
+ LTYPE *m = vm; \
71
+ TYPE *d = vd; \
72
+ uint16_t mask = mve_element_mask(env); \
73
+ unsigned le; \
74
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
75
+ TYPE r = FN(m[H##LESIZE(le)], shift); \
76
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
77
+ } \
78
+ mve_advance_vpt(env); \
79
+ }
80
+
90
+
81
+#define DO_VSHRN_ALL(OP, FN) \
91
+ sysbus_realize_and_unref(sbd, &error_fatal);
82
+ DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \
92
+ sysbus_mmio_map(sbd, 0, info->base);
83
+ DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \
84
+ DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \
85
+ DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
86
+
87
+static inline uint64_t do_urshr(uint64_t x, unsigned sh)
88
+{
89
+ if (likely(sh < 64)) {
90
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
91
+ } else if (sh == 64) {
92
+ return x >> 63;
93
+ } else {
94
+ return 0;
95
+ }
93
+ }
96
+}
94
+}
97
+
95
+
98
+DO_VSHRN_ALL(vshrn, DO_SHR)
96
static void xlnx_zynqmp_init(Object *obj)
99
+DO_VSHRN_ALL(vrshrn, do_urshr)
97
{
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
98
MachineState *ms = MACHINE(qdev_get_machine());
101
index XXXXXXX..XXXXXXX 100644
99
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
102
--- a/target/arm/translate-mve.c
100
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
103
+++ b/target/arm/translate-mve.c
101
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
104
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
102
105
DO_VSHLL(VSHLL_BU, vshllbu)
103
+ xlnx_zynqmp_create_unimp_mmio(s);
106
DO_VSHLL(VSHLL_TS, vshllts)
107
DO_VSHLL(VSHLL_TU, vshlltu)
108
+
104
+
109
+#define DO_2SHIFT_N(INSN, FN) \
105
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
110
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
106
if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
111
+ { \
107
errp)) {
112
+ static MVEGenTwoOpShiftFn * const fns[] = { \
113
+ gen_helper_mve_##FN##b, \
114
+ gen_helper_mve_##FN##h, \
115
+ }; \
116
+ return do_2shift(s, a, fns[a->size], false); \
117
+ }
118
+
119
+DO_2SHIFT_N(VSHRNB, vshrnb)
120
+DO_2SHIFT_N(VSHRNT, vshrnt)
121
+DO_2SHIFT_N(VRSHRNB, vrshrnb)
122
+DO_2SHIFT_N(VRSHRNT, vrshrnt)
123
--
108
--
124
2.20.1
109
2.20.1
125
110
126
111
diff view generated by jsdifflib

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